Index: trunk/firmware/FSBL/CubeMX/.mxproject =================================================================== --- trunk/firmware/FSBL/CubeMX/.mxproject (revision 16) +++ trunk/firmware/FSBL/CubeMX/.mxproject (revision 16) @@ -0,0 +1,64 @@ +[FSBL:PreviousGenFiles] +HeaderPath=..\FSBL\Inc +HeaderFiles=gpio.h;xspi.h;stm32n6xx_it.h;stm32n6xx_hal_conf.h;main.h; +SourcePath=..\FSBL\Src +SourceFiles=gpio.c;xspi.c;stm32n6xx_it.c;stm32n6xx_hal_msp.c;main.c; + +[FSBL:PreviousLibFiles] +LibFiles=Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_xspi.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_xspi.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h; + +[FSBL:PreviousUsedMakefileFiles] +SourceFiles=FSBL\Src\main.c;FSBL\Src\gpio.c;FSBL\Src\xspi.c;FSBL\Src\stm32n6xx_it.c;FSBL\Src\stm32n6xx_hal_msp.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include;FSBL\Inc;Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Appli:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h; + +[Appli:PreviousUsedMakefileFiles] +SourceFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[ExtMemLoader:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h; + +[ExtMemLoader:PreviousUsedMakefileFiles] +SourceFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousLibFiles] +LibFiles=Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_xspi.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_xspi.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_clang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm52.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\tz_context.h;Drivers\CMSIS\Include\m-profile\armv7m_cachel1.h;Drivers\CMSIS\Include\m-profile\armv7m_mpu.h;Drivers\CMSIS\Include\m-profile\armv81m_pac.h;Drivers\CMSIS\Include\m-profile\armv8m_mpu.h;Drivers\CMSIS\Include\m-profile\armv8m_pmu.h;Drivers\CMSIS\Include\m-profile\cmsis_armclang_m.h;Drivers\CMSIS\Include\m-profile\cmsis_clang_m.h;Drivers\CMSIS\Include\m-profile\cmsis_gcc_m.h;Drivers\CMSIS\Include\m-profile\cmsis_iccarm_m.h;Drivers\CMSIS\Include\m-profile\cmsis_tiarmclang_m.h;Drivers\CMSIS\Include\r-profile\cmsis_armclang_r.h;Drivers\CMSIS\Include\r-profile\cmsis_clang_r.h;Drivers\CMSIS\Include\r-profile\cmsis_gcc_r.h;Drivers\CMSIS\Include\r-profile\cmsis_iccarm_r.h; + +[PreviousUsedMakefileFiles] +SourceFiles=FSBL\Src\main.c;FSBL\Src\gpio.c;FSBL\Src\xspi.c;FSBL\Src\stm32n6xx_it.c;FSBL\Src\stm32n6xx_hal_msp.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Src\;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Src\;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;FSBL\Src\system_stm32n6xx_fsbl.c;Appli\Src\;ExtMemLoader\Src\system_stm32n6xx_fsbl.c;;; +HeaderPath=Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include;Drivers\CMSIS\Include\m-profile;Drivers\CMSIS\Include\r-profile;FSBL\Inc; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[FSBL:PreviousUsedCubeIDEFiles] +SourceFiles=FSBL\Src\main.c;FSBL\Src\gpio.c;FSBL\Src\xspi.c;FSBL\Src\stm32n6xx_it.c;FSBL\Src\stm32n6xx_hal_msp.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include;FSBL\Inc;Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Appli:PreviousUsedCubeIDEFiles] +SourceFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[ExtMemLoader:PreviousUsedCubeIDEFiles] +SourceFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousUsedCubeIDEFiles] +SourceFiles=FSBL\Src\main.c;FSBL\Src\gpio.c;FSBL\Src\xspi.c;FSBL\Src\stm32n6xx_it.c;FSBL\Src\stm32n6xx_hal_msp.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Src\;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_xspi.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Src\;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;FSBL\Src\system_stm32n6xx_fsbl.c;Appli\Src\;ExtMemLoader\Src\system_stm32n6xx_fsbl.c;;; +HeaderPath=Drivers\STM32N6xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32N6xx\Include;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Include;Drivers\CMSIS\Include\m-profile;Drivers\CMSIS\Include\r-profile;FSBL\Inc; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +HeaderPath=..\FSBL\Inc +HeaderFiles=gpio.h;xspi.h;stm32n6xx_it.h;stm32n6xx_hal_conf.h;main.h; +SourcePath=..\FSBL\Src +SourceFiles=gpio.c;xspi.c;stm32n6xx_it.c;stm32n6xx_hal_msp.c;main.c; + Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/Include/partition_stm32n6xx.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/Include/partition_stm32n6xx.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/Include/partition_stm32n6xx.h (revision 16) @@ -0,0 +1,71 @@ +/** + ****************************************************************************** + * @file partition_stm32n6xx.h + * @author MCD Application Team + * @brief CMSIS STM32N6xx Device Header File for Initial Setup for + * Secure / Non-Secure Zones based on CMSIS CORE V5.3.1 + * + * The file is included in system_stm32N6xx_s.c in secure application. + * It includes the configuration section that allows to select the + * STM32N6xx device partitioning file for system core secure attributes + * and interrupt secure and non-secure assignment. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32N6xx + * @{ + */ + +#ifndef PARTITION_STM32N6XX_H +#define PARTITION_STM32N6XX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Secure_configuration_section + * @{ + */ + +#if defined(STM32N657xx) + #include "partition_stm32n657xx.h" +#elif defined(STM32N655xx) + #include "partition_stm32n655xx.h" +#elif defined(STM32N647xx) + #include "partition_stm32n647xx.h" +#elif defined(STM32N645xx) + #include "partition_stm32n645xx.h" +#else + #error "Please select first the target STM32N6xx device used in your application (in stm32n6xx.h file)" +#endif + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* PARTITION_STM32N6XX_H */ + +/** + * @} + */ + +/** + * @} + */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/Include/stm32n657xx.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/Include/stm32n657xx.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/Include/stm32n657xx.h (revision 16) @@ -0,0 +1,43056 @@ +/** + ****************************************************************************** + * @file stm32n657xx.h + * @author MCD Application Team + * @brief CMSIS STM32N657xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32N657xx_H +#define STM32N657xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + +/** @addtogroup STM32N657xx + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +typedef enum +{ +/* ====================================== ARM Cortex-M55 Specific Interrupt Numbers ======================================== */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ +#endif + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* ====================================== STM32N6xx Specific Interrupt Numbers ============================================= */ + PVD_PVM_IRQn = 0, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */ + DTS_IRQn = 2, /*!< Thermal Sensor interruption */ + RCC_IRQn = 3, /*!< RCC non-secure global interrupts through EXTI Line detection */ + LOCKUP_IRQn = 4, /*!< LOCKUP / (no Overstack in CM55) */ + CACHE_ECC_IRQn = 5, /*!< Error ECC cache interrupt */ + TCM_ECC_IRQn = 6, /*!< TCM ECC interrupts */ + BKP_ECC_IRQn = 7, /*!< Backup RAM Interrupts */ + FPU_IRQn = 8, /*!< FPU interrupt */ + RTC_S_IRQn = 10, /*!< RTC secure interrupts through EXTI Line detection */ + TAMP_IRQn = 11, /*!< Tamper secure and non-secure interrupts through EXTI Line detection */ + RIFSC_TAMPER_IRQn = 12, /*!< RIF Tamper interrupts */ + IAC_IRQn = 13, /*!< IAC interrupt */ + RCC_S_IRQn = 14, /*!< RCC secure global interrupts through EXTI Line detection */ + RTC_IRQn = 16, /*!< RTC non-secure interrupts through EXTI Line detection */ + IWDG_IRQn = 18, /*!< Internal Watchdog interrupt */ + WWDG_IRQn = 19, /*!< Window Watchdog interrupt */ + EXTI0_IRQn = 20, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 21, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 22, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 23, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 24, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 25, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 26, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 27, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 28, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 29, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 30, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 31, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 32, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 33, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 34, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 35, /*!< EXTI Line15 interrupt */ + SAES_IRQn = 36, /*!< SAES interrupt */ + CRYP_IRQn = 37, /*!< CRYP interrupt */ + PKA_IRQn = 38, /*!< PKA interrupt */ + HASH_IRQn = 39, /*!< HASH interrupt */ + RNG_IRQn = 40, /*!< RNG global interrupt */ + MCE1_IRQn = 42, /*!< MCE1 global interrupt */ + MCE2_IRQn = 43, /*!< MCE2 global interrupt */ + MCE3_IRQn = 44, /*!< MCE3 global interrupt */ + MCE4_IRQn = 45, /*!< MCE4 global interrupt */ + ADC1_2_IRQn = 46, /*!< ADC1 & ADC2 interrupt */ + CSI_IRQn = 47, /*!< CSI global interrupt */ + DCMIPP_IRQn = 48, /*!< DCMIPP global interrupt */ + PAHB_ERR_IRQn = 52, /*!< PAHB error interrupt */ + NPU0_IRQn = 53, /*!< NPU mst_ints[0] line interrupt */ + NPU1_IRQn = 54, /*!< NPU mst_ints[1] line interrupt */ + NPU2_IRQn = 55, /*!< NPU mst_ints[2] line interrupt */ + NPU3_IRQn = 56, /*!< NPU mst_ints[3] line interrupt */ + CACHEAXI_IRQn = 57, /*!< NPU cache interrupt */ + LTDC_LO_IRQn = 58, /*!< LTDC low-layer global interrupt */ + LTDC_LO_ERR_IRQn = 59, /*!< LTDC low-layer error interrupt */ + DMA2D_IRQn = 60, /*!< DMA2D global interrupt */ + JPEG_IRQn = 61, /*!< JPEG global interrupt */ + VENC_IRQn = 62, /*!< VENC global interrupt */ + GFXMMU_IRQn = 63, /*!< GFXMMU global interrupt */ + GFXTIM_IRQn = 64, /*!< GFXTIM global interrupt */ + GPU2D_IRQn = 65, /*!< GPU2D interrupt */ + GPU2D_ER_IRQn = 66, /*!< GPU2D error interrupt */ + ICACHE_IRQn = 67, /*!< GPU2D cache interrupt */ + HPDMA1_Channel0_IRQn = 68, /*!< HPDMA1 Channel 0 global interrupt */ + HPDMA1_Channel1_IRQn = 69, /*!< HPDMA1 Channel 1 global interrupt */ + HPDMA1_Channel2_IRQn = 70, /*!< HPDMA1 Channel 2 global interrupt */ + HPDMA1_Channel3_IRQn = 71, /*!< HPDMA1 Channel 3 global interrupt */ + HPDMA1_Channel4_IRQn = 72, /*!< HPDMA1 Channel 4 global interrupt */ + HPDMA1_Channel5_IRQn = 73, /*!< HPDMA1 Channel 5 global interrupt */ + HPDMA1_Channel6_IRQn = 74, /*!< HPDMA1 Channel 6 global interrupt */ + HPDMA1_Channel7_IRQn = 75, /*!< HPDMA1 Channel 7 global interrupt */ + HPDMA1_Channel8_IRQn = 76, /*!< HPDMA1 Channel 8 global interrupt */ + HPDMA1_Channel9_IRQn = 77, /*!< HPDMA1 Channel 9 global interrupt */ + HPDMA1_Channel10_IRQn = 78, /*!< HPDMA1 Channel 10 global interrupt */ + HPDMA1_Channel11_IRQn = 79, /*!< HPDMA1 Channel 11 global interrupt */ + HPDMA1_Channel12_IRQn = 80, /*!< HPDMA1 Channel 12 global interrupt */ + HPDMA1_Channel13_IRQn = 81, /*!< HPDMA1 Channel 13 global interrupt */ + HPDMA1_Channel14_IRQn = 82, /*!< HPDMA1 Channel 14 global interrupt */ + HPDMA1_Channel15_IRQn = 83, /*!< HPDMA1 Channel 15 global interrupt */ + GPDMA1_Channel0_IRQn = 84, /*!< GPDMA1 Channel 0 interrupt */ + GPDMA1_Channel1_IRQn = 85, /*!< GPDMA1 Channel 1 interrupt */ + GPDMA1_Channel2_IRQn = 86, /*!< GPDMA1 Channel 2 interrupt */ + GPDMA1_Channel3_IRQn = 87, /*!< GPDMA1 Channel 3 interrupt */ + GPDMA1_Channel4_IRQn = 88, /*!< GPDMA1 Channel 4 interrupt */ + GPDMA1_Channel5_IRQn = 89, /*!< GPDMA1 Channel 5 interrupt */ + GPDMA1_Channel6_IRQn = 90, /*!< GPDMA1 Channel 6 interrupt */ + GPDMA1_Channel7_IRQn = 91, /*!< GPDMA1 Channel 7 interrupt */ + GPDMA1_Channel8_IRQn = 92, /*!< GPDMA1 Channel 8 interrupt */ + GPDMA1_Channel9_IRQn = 93, /*!< GPDMA1 Channel 9 interrupt */ + GPDMA1_Channel10_IRQn = 94, /*!< GPDMA1 Channel 10 interrupt */ + GPDMA1_Channel11_IRQn = 95, /*!< GPDMA1 Channel 11 interrupt */ + GPDMA1_Channel12_IRQn = 96, /*!< GPDMA1 Channel 12 interrupt */ + GPDMA1_Channel13_IRQn = 97, /*!< GPDMA1 Channel 13 interrupt */ + GPDMA1_Channel14_IRQn = 98, /*!< GPDMA1 Channel 14 interrupt */ + GPDMA1_Channel15_IRQn = 99, /*!< GPDMA1 Channel 15 interrupt */ + I2C1_EV_IRQn = 100, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 101, /*!< I2C1 error interrupt */ + I2C2_EV_IRQn = 102, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 103, /*!< I2C2 error interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + I2C4_EV_IRQn = 106, /*!< I2C4 event interrupt */ + I2C4_ER_IRQn = 107, /*!< I2C4 error interrupt */ + I3C1_EV_IRQn = 108, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 109, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 110, /*!< I3C2 event interrupt */ + I3C2_ER_IRQn = 111, /*!< I3C2 error interrupt */ + TIM1_BRK_IRQn = 112, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 113, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 114, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 115, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 116, /*!< TIM2 global interrupt */ + TIM3_IRQn = 117, /*!< TIM3 global interrupt */ + TIM4_IRQn = 118, /*!< TIM4 global interrupt */ + TIM5_IRQn = 119, /*!< TIM5 global interrupt */ + TIM6_IRQn = 120, /*!< TIM6 global interrupt */ + TIM7_IRQn = 121, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 122, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 123, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 124, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 125, /*!< TIM8 Capture Compare interrupt */ + TIM9_IRQn = 126, /*!< TIM9 global interrupt */ + TIM10_IRQn = 127, /*!< TIM10 global interrupt */ + TIM11_IRQn = 128, /*!< TIM11 global interrupt */ + TIM12_IRQn = 129, /*!< TIM12 global interrupt */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + TIM15_IRQn = 132, /*!< TIM15 global interrupt */ + TIM16_IRQn = 133, /*!< TIM16 global interrupt */ + TIM17_IRQn = 134, /*!< TIM17 global interrupt */ + TIM18_IRQn = 135, /*!< TIM18 global interrupt */ + LPTIM1_IRQn = 136, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 137, /*!< LPTIM2 global interrupt */ + LPTIM3_IRQn = 138, /*!< LPTIM3 global interrupt */ + LPTIM4_IRQn = 139, /*!< LPTIM4 global interrupt */ + LPTIM5_IRQn = 140, /*!< LPTIM5 global interrupt */ + ADF1_FLT0_IRQn = 141, /*!< ADF1 Filter 0 global interrupt */ + MDF1_FLT0_IRQn = 142, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 143, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 144, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 145, /*!< MDF1 Filter 3 global interrupt */ + MDF1_FLT4_IRQn = 146, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 147, /*!< MDF1 Filter 5 global interrupt */ + SAI1_A_IRQn = 148, /*!< Serial Audio Interface 1 block A interrupt */ + SAI1_B_IRQn = 149, /*!< Serial Audio Interface 1 block B interrupt */ + SAI2_A_IRQn = 150, /*!< Serial Audio Interface 2 block A interrupt */ + SAI2_B_IRQn = 151, /*!< Serial Audio Interface 2 block B interrupt */ + SPDIFRX1_IRQn = 152, /*!< SPDIFRX1 interrupt */ + SPI1_IRQn = 153, /*!< SPI1 global interrupt */ + SPI2_IRQn = 154, /*!< SPI2 global interrupt */ + SPI3_IRQn = 155, /*!< SPI3 global interrupt */ + SPI4_IRQn = 156, /*!< SPI4 global interrupt */ + SPI5_IRQn = 157, /*!< SPI5 global interrupt */ + SPI6_IRQn = 158, /*!< SPI6 global interrupt */ + USART1_IRQn = 159, /*!< USART1 global interrupt */ + USART2_IRQn = 160, /*!< USART2 global interrupt */ + USART3_IRQn = 161, /*!< USART3 global interrupt */ + UART4_IRQn = 162, /*!< UART4 global interrupt */ + UART5_IRQn = 163, /*!< UART5 global interrupt */ + USART6_IRQn = 164, /*!< USART3 global interrupt */ + UART7_IRQn = 165, /*!< UART7 global interrupt */ + UART8_IRQn = 166, /*!< UART8 global interrupt */ + UART9_IRQn = 167, /*!< UART9 global interrupt */ + USART10_IRQn = 168, /*!< USART10 global interrupt */ + LPUART1_IRQn = 169, /*!< LPUART1 global interrupt */ + XSPI1_IRQn = 170, /*!< XSPI1 global interrupt */ + XSPI2_IRQn = 171, /*!< XSPI2 global interrupt */ + XSPI3_IRQn = 172, /*!< XSPI3 global interrupt */ + FMC_IRQn = 173, /*!< FMC global interrupt */ + SDMMC1_IRQn = 174, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 175, /*!< SDMMC2 global interrupt */ + UCPD1_IRQn = 176, /*!< UCPD1 global interrupt */ + USB1_OTG_HS_IRQn = 177, /*!< USB1 OTG HS interrupt */ + USB2_OTG_HS_IRQn = 178, /*!< USB2 OTG HS interrupt */ + ETH1_IRQn = 179, /*!< ETH1 global interrupt */ + FDCAN1_IT0_IRQn = 180, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 181, /*!< FDCAN1 interrupt 1 */ + FDCAN2_IT0_IRQn = 182, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 183, /*!< FDCAN2 interrupt 1 */ + FDCAN3_IT0_IRQn = 184, /*!< FDCAN3 interrupt 0 */ + FDCAN3_IT1_IRQn = 185, /*!< FDCAN3 interrupt 1 */ + FDCAN_CU_IRQn = 186, /*!< FDCAN Clock Unit interrupt */ + MDIOS_IRQn = 187, /*!< MDIOS global interrupt */ + DCMI_PSSI_IRQn = 188, /*!< DCMI/PSSI global interrupt */ + WAKEUP_PIN_IRQn = 189, /*!< Wake-up pins interrupt */ + CTI_INT0_IRQn = 190, /*!< CTI INT0 interrupt */ + CTI_INT1_IRQn = 191, /*!< CTI INT1 interrupt */ + LTDC_UP_IRQn = 193, /*!< LTDC up-layer global interrupt */ + LTDC_UP_ERR_IRQn = 194, /*!< LTDC up-layer error interrupt */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Configuration of the Cortex-M55 Processor and Core Peripherals + */ +#define __CM55_REV 0x0101U /*!< Cortex-M55 revision r1p1 */ +#define __FPU_PRESENT 1U /*!< CM55 Floating Point Unit present */ +#define __DSP_PRESENT 1U /*!< CM55 Digital Signal Processing Unit present */ +#define __MPU_PRESENT 1U /*!< CM55 Memory Programming Unit present */ +#define __ICACHE_PRESENT 1U /*!< CM55 Instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM55 Data cache present */ +#define __VTOR_PRESENT 1U /*!< CM55 Vector table offset register present */ +#define __PMU_PRESENT 1U /*!< CM55 Performance Monitoring Unit present */ +#define __PMU_NUM_EVENTCNT 8U /*!< CM55 can monitor up to 8 PMU events */ +#define __NVIC_PRIO_BITS 4U /*!< CM55 uses 4 bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __SAUREGION_PRESENT 1U /*!< SAU regions present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CPU_IN_SECURE_STATE +#endif + +#define CPU_AS_TRUSTED_DOMAIN + +#include "core_cm55.h" /*!< ARM Cortex-M55 processor and core peripherals */ +#include "system_stm32n6xx.h" /*!< STM32N6xx System */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32N6xx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020-0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044-0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + __IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */ + __IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */ + __IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */ + __IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074-0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090-0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + __IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */ + __IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */ + __IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */ + __IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */ + __IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */ + __IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x0C8-0x0CC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */ +} ADC_Common_TypeDef; + +/** + * @brief Boot and Security + */ + +typedef struct +{ + __IO uint32_t FVRw[384]; /*!< BSEC fuse word (0-383) value register, Address offset: 0x000-0x5FC */ + uint32_t RESERVED0[128]; /*!< Reserved, Address offset: 0x600-0x7FC */ + __IO uint32_t SPLOCKx[12]; /*!< BSEC sticky program lock register (0-11), Address offset: 0x800-0x82C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x830-0x83C */ + __IO uint32_t SWLOCKx[12]; /*!< BSEC sticky write lock register (0-11), Address offset: 0x840-0x86C */ + uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x870-0x87C */ + __IO uint32_t SRLOCKx[12]; /*!< BSEC sticky reload lock register (0-11), Address offset: 0x880-0x8AC */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x8B0-0x8BC */ + __IO uint32_t OTPVLDRx[12]; /*!< BSEC OTP valid register (0-11), Address offset: 0x8C0-0x8EC */ + uint32_t RESERVED4[20]; /*!< Reserved, Address offset: 0x8F0-0x93C */ + __IO uint32_t SFSRx[12]; /*!< BSEC shadowed fuses status register (0-11), Address offset: 0x940-0x96C */ + uint32_t RESERVED5[165]; /*!< Reserved, Address offset: 0x970-0xC00 */ + __IO uint32_t OTPCR; /*!< BSEC OTP control register, Address offset: 0xC04 */ + __IO uint32_t WDR; /*!< BSEC write data register, Address offset: 0xC08 */ + uint32_t RESERVED6[125]; /*!< Reserved, Address offset: 0xC0C-0xDFC */ + __IO uint32_t SCRATCHRx[4]; /*!< BSEC scratch register (0-3), Address offset: 0xE00-0xE0C */ + __IO uint32_t LOCKR; /*!< BSEC lock register, Address offset: 0xE10 */ + __IO uint32_t JTAGINR; /*!< BSEC JTAG input register, Address offset: 0xE14 */ + __IO uint32_t JTAGOUTR; /*!< BSEC JTAG output register, Address offset: 0xE18 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xE1C-0xE20 */ + __IO uint32_t UNMAPR; /*!< BSEC unmap register, Address offset: 0xE24 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0xE28-0xE3C */ + __IO uint32_t SR; /*!< BSEC status register, Address offset: 0xE40 */ + __IO uint32_t OTPSR; /*!< BSEC OTP status register, Address offset: 0xE44 */ + uint32_t RESERVED9[14]; /*!< Reserved, Address offset: 0xE48-0xE7C */ + __IO uint32_t EPOCHRx[2]; /*!< BSEC epoch register (0-1), Address offset: 0xE80-0xE84 */ + __IO uint32_t EPOCHSELR; /*!< BSEC epoch select register, Address offset: 0xE88 */ + __IO uint32_t DBGCR; /*!< BSEC debug control register, Address offset: 0xE8C */ + __IO uint32_t AP_UNLOCK; /*!< BSEC AP unlock, Address offset: 0xE90 */ + __IO uint32_t HDPLSR; /*!< BSEC hide protection level status register, Address offset: 0xE94 */ + __IO uint32_t HDPLCR; /*!< BSEC hide protection level control register, Address offset: 0xE98 */ + __IO uint32_t NEXTLR; /*!< BSEC next hide protection level register, Address offset: 0xE9C */ + uint32_t RESERVED10[40]; /*!< Reserved, Address offset: 0xEA0-0xF3C */ + __IO uint32_t WOSCRx[8]; /*!< BSEC write once scratch register (0-7), Address offset: 0xF40-0xF5C */ + uint32_t RESERVED11[34]; /*!< Reserved, Address offset: 0xF60-0xFE4 */ + __IO uint32_t HRCR; /*!< BSEC hot reset count register, Address offset: 0xFE8 */ + __IO uint32_t WRCR; /*!< BSEC warm reset count register, Address offset: 0xFEC */ +} BSEC_TypeDef; + +/** + * @brief Axi Cache + */ +typedef struct +{ + __IO uint32_t CR1; /*!< CACHEAXI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CACHEAXI status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< CACHEAXI interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< CACHEAXI flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< CACHEAXI read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< CACHEAXI read miss monitor register, Address offset: 0x14 */ + __IO uint32_t RAMMONR; /*!< CACHEAXI read-allocate miss monitor register, Address offset: 0x18 */ + __IO uint32_t EVIMONR; /*!< CACHEAXI eviction monitor register, Address offset: 0x1C */ + __IO uint32_t WHMONR; /*!< CACHEAXI write-hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< CACHEAXI write-miss monitor register, Address offset: 0x24 */ + __IO uint32_t WAMMONR; /*!< CACHEAXI write-allocate miss monitor register, Address offset: 0x28 */ + __IO uint32_t WTMONR; /*!< CACHEAXI write-through monitor register, Address offset: 0x2C */ + uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x30-0xFC */ + __IO uint32_t CR2; /*!< CACHEAXI control register 2, Address offset: 0x100 */ + __IO uint32_t CMDRSADDRR; /*!< CACHEAXI command start address register, Address offset: 0x104 */ + __IO uint32_t CMDREADDRR; /*!< CACHEAXI command end address register, Address offset: 0x108 */ +} CACHEAXI_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Cryp Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/* + * @brief (CSI) + */ +typedef struct +{ + __IO uint32_t CR; /*!< CSI-2 Host control register Address offset: 0x0000 */ + __IO uint32_t PCR; /*!< CSI-2 Host DPHY_RX control register Address offset: 0x0004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x0008-0x000C */ + __IO uint32_t VC0CFGR1; /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */ + __IO uint32_t VC0CFGR2; /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */ + __IO uint32_t VC0CFGR3; /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */ + __IO uint32_t VC0CFGR4; /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */ + __IO uint32_t VC1CFGR1; /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */ + __IO uint32_t VC1CFGR2; /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */ + __IO uint32_t VC1CFGR3; /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */ + __IO uint32_t VC1CFGR4; /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */ + __IO uint32_t VC2CFGR1; /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */ + __IO uint32_t VC2CFGR2; /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */ + __IO uint32_t VC2CFGR3; /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */ + __IO uint32_t VC2CFGR4; /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */ + __IO uint32_t VC3CFGR1; /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */ + __IO uint32_t VC3CFGR2; /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */ + __IO uint32_t VC3CFGR3; /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */ + __IO uint32_t VC3CFGR4; /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */ + __IO uint32_t LB0CFGR; /*!< CSI-2 Host line byte 0 configuration register Address offset: 0x0050 */ + __IO uint32_t LB1CFGR; /*!< CSI-2 Host line byte 1 configuration register Address offset: 0x0054 */ + __IO uint32_t LB2CFGR; /*!< CSI-2 Host line byte 2 configuration register Address offset: 0x0058 */ + __IO uint32_t LB3CFGR; /*!< CSI-2 Host line byte 3 configuration register Address offset: 0x005C */ + __IO uint32_t TIM0CFGR; /*!< CSI-2 Host timer 0 configuration register Address offset: 0x0060 */ + __IO uint32_t TIM1CFGR; /*!< CSI-2 Host timer 1 configuration register Address offset: 0x0064 */ + __IO uint32_t TIM2CFGR; /*!< CSI-2 Host timer 2 configuration register Address offset: 0x0068 */ + __IO uint32_t TIM3CFGR; /*!< CSI-2 Host timer 3 configuration register Address offset: 0x006C */ + __IO uint32_t LMCFGR; /*!< CSI-2 Host lane merger configuration register Address offset: 0x0070 */ + __IO uint32_t PRGITR; /*!< CSI-2 Host program interrupt register Address offset: 0x0074 */ + __IO uint32_t WDR; /*!< CSI-2 Host watchdog register Address offset: 0x0078 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x007C */ + __IO uint32_t IER0; /*!< CSI-2 Host Interrupt enable register 0 Address offset: 0x0080 */ + __IO uint32_t IER1; /*!< CSI-2 Host Interrupt enable register 1 Address offset: 0x0084 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0088-0x008C */ + __IO uint32_t SR0; /*!< CSI-2 Host status register 0 Address offset: 0x0090 */ + __IO uint32_t SR1; /*!< CSI-2 Host status register 1 Address offset: 0x0094 */ + uint32_t RESERVED3[26]; /*!< Reserved Address offset: 0x0098-0x00FC */ + __IO uint32_t FCR0; /*!< CSI-2 Host Flag clear register 0 Address offset: 0x0100 */ + __IO uint32_t FCR1; /*!< CSI-2 Host Flag clear register 1 Address offset: 0x0104 */ + uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x0108-0x010C */ + __IO uint32_t SPDFR; /*!< CSI-2 Host short packet data field register Address offset: 0x0110 */ + __IO uint32_t ERR1; /*!< CSI-2 Host error register 1 Address offset: 0x0114 */ + __IO uint32_t ERR2; /*!< CSI-2 Host error register 2 Address offset: 0x0118 */ + uint32_t RESERVED5[953]; /*!< Reserved Address offset: 0x011C-0x0FFC */ + __IO uint32_t PRCR; /*!< CSI PHY reset control register Address offset: 0x1000 */ + __IO uint32_t PMCR; /*!< CSI PHY mode control register Address offset: 0x1004 */ + __IO uint32_t PFCR; /*!< CSI PHY frequency control register Address offset: 0x1008 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x100C */ + __IO uint32_t PTCR0; /*!< CSI PHY test control register 0 Address offset: 0x1010 */ + __IO uint32_t PTCR1; /*!< CSI PHY test control register 1 Address offset: 0x1014 */ + __IO uint32_t PTSR; /*!< CSI PHY test status register Address offset: 0x1018 */ + uint32_t RESERVED7[1017]; /*!< Reserved Address offset: 0x101C-0x1FFC */ +} CSI_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x10 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1HFZ1 freeze register, Address offset: 0x14 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x18 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x1C */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register, Address offset: 0x20 */ + __IO uint32_t AHB1FZ1; /*!< Debug MCU AHB1FZ1 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB5FZ1; /*!< Debug MCU AHB5FZ1 freeze register, Address offset: 0x28 */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x2C-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU authentication device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +#define DCMIPP_NUM_OF_PIPES 0x03U + +typedef struct +{ + uint32_t PxRIxCR1; /*! DCMIPP Pipex ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2) */ + uint32_t PxRIxCR2; /*! DCMIPP Pipex ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2) */ +} DCMIPP_Region_TypeDef; + +/* + * @brief Digital camera interface pixel pipeline DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< DCMIPP IPPLUG global register 1 Address offset: 0x000 */ + __IO uint32_t IPGR2; /*!< DCMIPP IPPLUG global register 2 Address offset: 0x004 */ + __IO uint32_t IPGR3; /*!< DCMIPP IPPLUG global register 3 Address offset: 0x008 */ + uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x00C-0x018 */ + __IO uint32_t IPGR8; /*!< DCMIPP IPPLUG identification register Address offset: 0x01C */ + __IO uint32_t IPC1R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */ + __IO uint32_t IPC1R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */ + __IO uint32_t IPC1R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x02C */ + __IO uint32_t IPC2R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x030 */ + __IO uint32_t IPC2R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x034 */ + __IO uint32_t IPC2R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x038 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t IPC3R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x040 */ + __IO uint32_t IPC3R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x044 */ + __IO uint32_t IPC3R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x04C */ + __IO uint32_t IPC4R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x050 */ + __IO uint32_t IPC4R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x054 */ + __IO uint32_t IPC4R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t IPC5R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x060 */ + __IO uint32_t IPC5R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x064 */ + __IO uint32_t IPC5R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x068 */ + uint32_t RESERVED5[38]; /*!< Reserved Address offset: 0x06C-0x100 */ + __IO uint32_t PRCR; /*!< DCMIPP parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< DCMIPP parallel interface embedded synchronization code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */ + uint32_t RESERVED6[57]; /*!< Reserved Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< DCMIPP parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< DCMIPP parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< DCMIPP parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< DCMIPP common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< DCMIPP common frame counter register Address offset: 0x208 */ + uint32_t RESERVED8[121]; /*!< Reserved Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< DCMIPP common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< DCMIPP common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< DCMIPP common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< DCMIPP common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< DCMIPP Pipe0 flow selection configuration register Address offset: 0x404 */ + uint32_t RESERVED10[62]; /*!< Reserved Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< DCMIPP Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< DCMIPP Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< DCMIPP Pipe0 stat/crop size register Address offset: 0x508 */ + uint32_t RESERVED11[41]; /*!< Reserved Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< DCMIPP Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< DCMIPP Pipe0 dump limit register Address offset: 0x5B4 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< DCMIPP Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2 Address offset: 0x5C8 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x5C8-0x5CC */ + __IO uint32_t P0STM0AR; /*!< DCMIPP Pipe0 status Memory0 address register Address offset: 0x5D0 */ + uint32_t RESERVED14[8]; /*!< Reserved Address offset: 0x5D4-0x5F0 */ + __IO uint32_t P0IER; /*!< DCMIPP Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< DCMIPP Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< DCMIPP Pipe0 interrupt clear register Address offset: 0x5FC */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x600 */ + __IO uint32_t P0CFSCR; /*!< DCMIPP Pipe0 current flow selection configuration register Address offset: 0x604 */ + uint32_t RESERVED17[62]; /*!< Reserved Address offset: 0x608-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< DCMIPP Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< DCMIPP Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< DCMIPP Pipe0 current stat/crop size register Address offset: 0x708 */ + uint32_t RESERVED18[45]; /*!< Reserved Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< DCMIPP Pipe0 current pixel packer configuration register Address offset: 0x7C0 */ + __IO uint32_t P0CPPM0AR1; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2 Address offset: */ + uint32_t RESERVED19[14]; /*!< Reserved Address offset: 0x7C8-0x7FC */ + __IO uint32_t P1FSCR; /*!< DCMIPP Pipe1 flow selection configuration register Address offset: 0x804 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0x808-0x81C */ + __IO uint32_t P1SRCR; /*!< DCMIPP Pipe1 stat removal configuration register Address offset: 0x820 */ + __IO uint32_t P1BPRCR; /*!< DCMIPP Pipe1 bad pixel removal control register Address offset: 0x824 */ + __IO uint32_t P1BPRSR; /*!< DCMIPP Pipe1 bad pixel removal status register Address offset: 0x828 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x82C */ + __IO uint32_t P1DECR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x830 */ + uint32_t RESERVED22[3]; /*!< Reserved Address offset: 0x834-0x83C */ + __IO uint32_t P1BLCCR; /*!< DCMIPP Pipe1 black level calibration control register Address offset: 0x840 */ + __IO uint32_t P1EXCR1; /*!< DCMIPP Pipe1 exposure control register 1 Address offset: 0x844 */ + __IO uint32_t P1EXCR2; /*!< DCMIPP Pipe1 exposure control register 2 Address offset: 0x848 */ + uint32_t RESERVED23; /*!< Reserved Address offset: 0x84C */ + __IO uint32_t P1ST1CR; /*!< DCMIPP Pipe1 statistics 1 control register Address offset: 0x850 */ + __IO uint32_t P1ST2CR; /*!< DCMIPP Pipe1 statistics 2 control register Address offset: 0x854 */ + __IO uint32_t P1ST3CR; /*!< DCMIPP Pipe1 statistics 3 control register Address offset: 0x858 */ + __IO uint32_t P1STSTR; /*!< DCMIPP Pipe1 statistics window start register Address offset: 0x85C */ + __IO uint32_t P1STSZR; /*!< DCMIPP Pipe1 statistics window size register Address offset: 0x860 */ + __IO uint32_t P1ST1SR; /*!< DCMIPP Pipe1 statistics 1 status register Address offset: 0x864 */ + __IO uint32_t P1ST2SR; /*!< DCMIPP Pipe1 statistics 2 status register Address offset: 0x868 */ + __IO uint32_t P1ST3SR; /*!< DCMIPP Pipe1 statistics 3 status register Address offset: 0x86C */ + __IO uint32_t P1DMCR; /*!< DCMIPP Pipe1 demosaicing configuration register Address offset: 0x870 */ + uint32_t RESERVED24[3]; /*!< Reserved Address offset: 0x874-0x87C */ + __IO uint32_t P1CCCR; /*!< DCMIPP Pipe1 ColorConv configuration register Address offset: 0x880 */ + __IO uint32_t P1CCRR1; /*!< DCMIPP Pipe1 ColorConv red coefficient register 1 Address offset: 0x884 */ + __IO uint32_t P1CCRR2; /*!< DCMIPP Pipe1 ColorConv red coefficient register 2 Address offset: 0x888 */ + __IO uint32_t P1CCGR1; /*!< DCMIPP Pipe1 ColorConv green coefficient register 1 Address offset: 0x88C */ + __IO uint32_t P1CCGR2; /*!< DCMIPP Pipe1 ColorConv green coefficient register 2 Address offset: 0x890 */ + __IO uint32_t P1CCBR1; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1 Address offset: 0x894 */ + __IO uint32_t P1CCBR2; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2 Address offset: 0x898 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x89C */ + __IO uint32_t P1CTCR1; /*!< DCMIPP Pipe1 contrast control register 1 Address offset: 0x8A0 */ + __IO uint32_t P1CTCR2; /*!< DCMIPP Pipe1 contrast control register 2 Address offset: 0x8A4 */ + __IO uint32_t P1CTCR3; /*!< DCMIPP Pipe1 contrast control register 3 Address offset: 0x8A8 */ + uint32_t RESERVED26[21]; /*!< Reserved Address offset: 0x8AC-0x8FC */ + __IO uint32_t P1FCTCR; /*!< DCMIPP Pipe1 flow control configuration register Address offset: 0x900 */ + __IO uint32_t P1CRSTR; /*!< DCMIPP Pipe1 crop window start register Address offset: 0x904 */ + __IO uint32_t P1CRSZR; /*!< DCMIPP Pipe1 crop window size register Address offset: 0x908 */ + __IO uint32_t P1DCCR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x90C */ + __IO uint32_t P1DSCR; /*!< DCMIPP Pipe1 downsize configuration register Address offset: 0x910 */ + __IO uint32_t P1DSRTIOR; /*!< DCMIPP Pipe1 downsize ratio register Address offset: 0x914 */ + __IO uint32_t P1DSSZR; /*!< DCMIPP Pipe1 downsize destination size register Address offset: 0x918 */ + uint32_t RESERVED28; /*!< Reserved Address offset: */ + __IO uint32_t P1CMRICR; /*!< DCMIPP Pipe1 common ROI configuration register Address offset: 0x920 */ + __IO uint32_t P1RIxCR1; /*!< DCMIPP Pipe1 ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */ + __IO uint32_t P1RIxCR2; /*!< DCMIPP Pipe1 ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */ + uint32_t RESERVED29[17]; /*!< Reserved Address offset: */ + __IO uint32_t P1GMCR; /*!< DCMIPP Pipe1 gamma configuration register Address offset: 0x970 */ + uint32_t RESERVED30[3]; /*!< Reserved Address offset: 0x974-0x97C */ + __IO uint32_t P1YUVCR; /*!< DCMIPP Pipe1 YUVConv configuration register Address offset: 0x980 */ + __IO uint32_t P1YUVRR1; /*!< DCMIPP Pipe1 YUVConv red coefficient register 1 Address offset: 0x984 */ + __IO uint32_t P1YUVRR2; /*!< DCMIPP Pipe1 YUVConv red coefficient register 2 Address offset: 0x988 */ + __IO uint32_t P1YUVGR1; /*!< DCMIPP Pipe1 YUVConv green coefficient register 1 Address offset: 0x98C */ + __IO uint32_t P1YUVGR2; /*!< DCMIPP Pipe1 YUVConv green coefficient register 2 Address offset: 0x990 */ + __IO uint32_t P1YUVBR1; /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1 Address offset: 0x994 */ + __IO uint32_t P1YUVBR2; /*!< DCMIPP Pipe1 YUV blue coefficient register 2 Address offset: 0x998 */ + uint32_t RESERVED31[9]; /*!< Reserved Address offset: 0x99C-0x9BC */ + __IO uint32_t P1PPCR; /*!< DCMIPP Pipe1 pixel packer configuration register Address offset: 0x9C0 */ + __IO uint32_t P1PPM0AR1; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1 Address offset: 0x9C4 */ + __IO uint32_t P1PPM0AR2; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2 Address offset: 0x9C8 */ + __IO uint32_t P1PPM0PR; /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register Address offset: 0x9CC */ + __IO uint32_t P1STM0AR; /*!< DCMIPP Pipe1 status Memory0 address register Address offset: 0x9D0 */ + __IO uint32_t P1PPM1AR1; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1 Address offset: 0x9D4 */ + __IO uint32_t P1PPM1AR2; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2 Address offset: 0x9D8 */ + __IO uint32_t P1PPM1PR; /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register Address offset: 0x9DC */ + __IO uint32_t P1STM1AR; /*!< DCMIPP Pipe1 status Memory1 address register Address offset: 0x9E0 */ + __IO uint32_t P1PPM2AR1; /*!< DCMIPP Pipe1 pixel packer memory2 address register 1 Address offset: 0x9E4 */ + __IO uint32_t P1PPM2AR2; /*!< DCMIPP Pipe1 pixel packer memory2 address register 2 Address offset: 0x9E8 */ + __IO uint32_t RESERVED34; /*!< Reserved Address offset: 0x9EC */ + __IO uint32_t P1STM2AR; /*!< DCMIPP Pipe1 status Memory2 address register Address offset: 0x9F0 */ + __IO uint32_t P1IER; /*!< DCMIPP Pipe1 interrupt enable register Address offset: 0x9F4 */ + __IO uint32_t P1SR; /*!< DCMIPP Pipe1 status register Address offset: 0x9F8 */ + __IO uint32_t P1FCR; /*!< DCMIPP Pipe1 interrupt clear register Address offset: 0x9FC */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0xA00 */ + __IO uint32_t P1CFSCR; /*!< DCMIPP Pipe1 current flow selection configuration register Address offset: 0xA04 */ + uint32_t RESERVED36[7]; /*!< Reserved Address offset: 0xA08-0xA20 */ + __IO uint32_t P1CBPRCR; /*!< DCMIPP Pipe1 current bad pixel removal register Address offset: 0xA24 */ + uint32_t RESERVED37[6]; /*!< Reserved Address offset: 0xA28-0xA3C */ + __IO uint32_t P1CBLCCR; /*!< DCMIPP Pipe1 current black level calibration control register Address offset: 0xA40 */ + __IO uint32_t P1CEXCR1; /*!< DCMIPP Pipe1 current exposure control register 1 Address offset: 0xA44 */ + __IO uint32_t P1CEXCR2; /*!< DCMIPP Pipe1 current exposure control register 2 Address offset: 0xA48 */ + uint32_t RESERVED38; /*!< Reserved Address offset: 0xA4C */ + __IO uint32_t P1CST1CR; /*!< DCMIPP Pipe1 current statistics 1 control register Address offset: 0xA50 */ + __IO uint32_t P1CST2CR; /*!< DCMIPP Pipe1 current statistics 2 control register Address offset: 0xA54 */ + __IO uint32_t P1CST3CR; /*!< DCMIPP Pipe1 current statistics 3 control register Address offset: 0xA58 */ + __IO uint32_t P1CSTSTR; /*!< DCMIPP Pipe1 current statistics window start register Address offset: 0xA5C */ + __IO uint32_t P1CSTSZR; /*!< DCMIPP Pipe1 current statistics window size register Address offset: 0xA60 */ + uint32_t RESERVED39[7]; /*!< Reserved Address offset: 0xA64-0xA7C */ + __IO uint32_t P1CCCCR; /*!< DCMIPP Pipe1 current ColorConv configuration register Address offset: 0xA80 */ + __IO uint32_t P1CCCRR1; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1 Address offset: 0xA84 */ + __IO uint32_t P1CCCRR2; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2 Address offset: 0xA88 */ + __IO uint32_t P1CCCGR1; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1 Address offset: 0xA8C */ + __IO uint32_t P1CCCGR2; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2 Address offset: 0xA90 */ + __IO uint32_t P1CCCBR1; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1 Address offset: 0xA94 */ + __IO uint32_t P1CCCBR2; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2 Address offset: 0xA98 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0xA9C */ + __IO uint32_t P1CCTCR1; /*!< DCMIPP Pipe1 current contrast control register 1 Address offset: 0xAA0 */ + __IO uint32_t P1CCTCR2; /*!< DCMIPP Pipe1 current contrast control register 2 Address offset: 0xAA4 */ + __IO uint32_t P1CCTCR3; /*!< DCMIPP Pipe1 current contrast control register 3 Address offset: 0xAA8 */ + uint32_t RESERVED41[21]; /*!< Reserved Address offset: 0xAAC-0xAFC */ + __IO uint32_t P1CFCTCR; /*!< DCMIPP Pipe1 current flow control configuration register Address offset: 0xB00 */ + __IO uint32_t P1CCRSTR; /*!< DCMIPP Pipe1 current crop window start register Address offset: 0xB04 */ + __IO uint32_t P1CCRSZR; /*!< DCMIPP Pipe1 current crop window size register Address offset: 0xB08 */ + __IO uint32_t P1CDCCR; /*!< DCMIPP Pipe1 current decimation register Address offset: 0xB0C */ + __IO uint32_t P1CDSCR; /*!< DCMIPP Pipe1 current downsize configuration register Address offset: 0xB10 */ + __IO uint32_t P1CDSRTIOR; /*!< DCMIPP Pipe1 current downsize ratio register Address offset: 0xB14 */ + __IO uint32_t P1CDSSZR; /*!< DCMIPP Pipe1 current downsize destination size register Address offset: 0xB18 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0xB1C */ + uint32_t P1CCMRICR; /*!< DCMIPP Pipe1 current common ROI configuration register Address offset: 0xB20 */ + __IO uint32_t P1CRIxCR1; /*!< DCMIPP Pipe1 current ROIx configuration register 1 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */ + __IO uint32_t P1CRIxCR2; /*!< DCMIPP Pipe1 current ROIx configuration register 2 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */ + uint32_t RESERVED44[37]; /*!< Reserved Address offset: 0xB64-0xBBC */ + __IO uint32_t P1CPPCR; /*!< DCMIPP Pipe1 current pixel packer configuration register Address offset: 0xBC0 */ + __IO uint32_t P1CPPM0AR1; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC4 */ + __IO uint32_t P1CPPM0AR2; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC8 */ + __IO uint32_t P1CPPM0PR; /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register Address offset: 0xBCC */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0xBD0 */ + __IO uint32_t P1CPPM1AR1; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1 Address offset: 0xBD4 */ + __IO uint32_t P1CPPM1AR2; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2 Address offset: 0xBD8 */ + __IO uint32_t P1CPPM1PR; /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register Address offset: 0xBDC */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0xBE0 */ + __IO uint32_t P1CPPM2AR1; /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1 Address offset: 0xBE4 */ + __IO uint32_t P1CPPM2AR2; /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2 Address offset: 0xBE8 */ + uint32_t RESERVED48[6]; /*!< Reserved Address offset: 0xBE8-0xBFC */ + __IO uint32_t P2FSCR; /*!< DCMIPP Pipe2 flow selection configuration register Address offset: 0xC04 */ + uint32_t RESERVED49[62]; /*!< Reserved Address offset: 0xC08-0xCFC */ + __IO uint32_t P2FCTCR; /*!< DCMIPP Pipe2 flow control configuration register Address offset: 0xD00 */ + __IO uint32_t P2CRSTR; /*!< DCMIPP Pipe2 crop window start register Address offset: 0xD04 */ + __IO uint32_t P2CRSZR; /*!< DCMIPP Pipe2 crop window size register Address offset: 0xD08 */ + __IO uint32_t P2DCCR; /*!< DCMIPP Pipe2 decimation register Address offset: 0xD0C */ + __IO uint32_t P2DSCR; /*!< DCMIPP Pipe2 downsize configuration register Address offset: 0xD10 */ + __IO uint32_t P2DSRTIOR; /*!< DCMIPP Pipe2 downsize ratio register Address offset: 0xD14 */ + __IO uint32_t P2DSSZR; /*!< DCMIPP Pipe2 downsize destination size register Address offset: 0xD18 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0xD1C */ + __IO uint32_t P2CMRICR; /*!< DCMIPP Pipe2 common ROI configuration register Address offset: 0xD20 */ + __IO uint32_t P2RIxCR1; /*!< DCMIPP Pipe2 ROIx configuration register 1 Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */ + __IO uint32_t P2RIxCR2; /*!< DCMIPP Pipe2 ROIx configuration register 2 Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */ + uint32_t RESERVED53[17]; /*!< Reserved Address offset: */ + __IO uint32_t P2GMCR; /*!< DCMIPP Pipe2 gamma configuration register Address offset: 0xD70 */ + uint32_t RESERVED54[19]; /*!< Reserved Address offset: 0xD74-0xDBC */ + __IO uint32_t P2PPCR; /*!< DCMIPP Pipe2 pixel packer configuration register Address offset: 0xDC0 */ + __IO uint32_t P2PPM0AR1; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1 Address offset: 0xDC4 */ + __IO uint32_t P2PPM0AR2; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2 Address offset: 0xDC8 */ + __IO uint32_t P2PPM0PR; /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register Address offset: 0xDCC */ + __IO uint32_t P2STM0AR; /*!< DCMIPP Pipe2 status Memory0 address register Address offset: 0xDD0 */ + uint32_t RESERVED55[8]; /*!< Reserved Address offset: 0xDD4-0xDF0 */ + __IO uint32_t P2IER; /*!< DCMIPP Pipe2 interrupt enable register Address offset: 0xDF4 */ + __IO uint32_t P2SR; /*!< DCMIPP Pipe2 status register Address offset: 0xDF8 */ + __IO uint32_t P2FCR; /*!< DCMIPP Pipe2 interrupt clear register Address offset: 0xDFC */ + uint32_t RESERVED56; /*!< Reserved Address offset: 0xE00 */ + __IO uint32_t P2CFSCR; /*!< DCMIPP Pipe2 current flow selection configuration register Address offset: 0xE04 */ + uint32_t RESERVED57[62]; /*!< Reserved Address offset: 0xE08-0xEFC */ + __IO uint32_t P2CFCTCR; /*!< DCMIPP Pipe2 current flow control configuration register Address offset: 0xF00 */ + __IO uint32_t P2CCRSTR; /*!< DCMIPP Pipe2 current crop window start register Address offset: 0xF04 */ + __IO uint32_t P2CCRSZR; /*!< DCMIPP Pipe2 current crop window size register Address offset: 0xF08 */ + __IO uint32_t P2CDCCR; /*!< DCMIPP Pipe2 current decimation register Address offset: 0xF0C */ + __IO uint32_t P2CDSCR; /*!< DCMIPP Pipe2 current downsize configuration register Address offset: 0xF10 */ + __IO uint32_t P2CDSRTIOR; /*!< DCMIPP Pipe2 current downsize ratio register Address offset: 0xF14 */ + __IO uint32_t P2CDSSZR; /*!< DCMIPP Pipe2 current downsize destination size register Address offset: 0xF18 */ + __IO uint32_t RESERVED59[2]; /*!< Reserved Address offset: 0xF1C-0xF20 */ + __IO uint32_t P2CRIxCR1; /*!< Pipe2 current ROIx configuration register 1 Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/ + __IO uint32_t P2CRIxCR2; /*!< Pipe2 current ROIx configuration register 2 Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/ + uint32_t RESERVED60[37]; /*!< Reserved Address offset: 0xF64-0xFBC */ + __IO uint32_t P2CPPCR; /*!< DCMIPP Pipe2 current pixel packer configuration register Address offset: 0xFC0 */ + __IO uint32_t P2CPPM0AR1; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1 Address offset: 0xFC4 */ + __IO uint32_t P2CPPM0AR2; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2 Address offset: 0xFC8 */ + __IO uint32_t P2CPPM0PR; /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register Address offset: 0xFCC */ + uint32_t RESERVED61[7]; /*!< Reserved Address offset: 0xFD0-0xFE8 */ + __IO uint32_t HWCFGR2; /*!< DCMIPP hardware configuration register 2 Address offset: 0xFEC */ + __IO uint32_t HWCFGR1; /*!< DCMIPP hardware configuration register 1 Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< DCMIPP version register Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< DCMIPP identification register Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< DCMIPP size identification register Address offset: 0xFFC */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CFG; /*!< Delay Block Configuration Register, Address offset: 0x00 */ + __IO uint32_t STATUS; /*!< Delay Block Status Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + __IO uint32_t CCIDCFGR; /*!< DMA channel x CID register, Address offset: 0x54 + (x * 0x80) */ + uint32_t RESERVED1[1]; /*!< Reserved 1, Address offset: 0x58 + (x * 0x80) */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C + (x * 0x80) */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 + (x * 0x80) */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS Controller + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x00-0x0F */ + __IO uint32_t PVTREG_LOCKR; /*!< DTS PVT Register Lock Register, Address offset: 0x10 */ + __IO uint32_t PVTLOCK_SR; /*!< DTS PVT Lock Status Register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1F */ + __IO uint32_t PVTTMR_CR; /*!< DTS PVT Timer Control Register, Address offset: 0x20 */ + __IO uint32_t PVTTMR_SR; /*!< DTS PVT Timer Status Register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x28-0x3F */ + __IO uint32_t PVT_IER; /*!< DTS PVT IRQ Enable Register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4F */ + __IO uint32_t PVTIRQTRMASKR; /*!< DTS PVT IRQ Timer Mask Register, Address offset: 0x50 */ + __IO uint32_t TS_MR; /*!< DTS PVT IRQ TS Mask Register, Address offset: 0x54 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x58-0x5F */ + __IO uint32_t PVTTR_SR; /*!< DTS PVT IRQ Timer Status Register, Address offset: 0x60 */ + __IO uint32_t TS_ISR; /*!< DTS PVT IRQ TS Status Register, Address offset: 0x64 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x68-0x6F */ + __IO uint32_t PVTTMRRAW_ISR; /*!< DTS PVT IRQ Timer Raw Status Register, Address offset: 0x70 */ + __IO uint32_t TSRAW_ISR; /*!< DTS PVT IRQ TS Raw Status Register, Address offset: 0x74 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x78-0x7F */ + __IO uint32_t TSCCLKSYNTHR; /*!< DTS TSC Clock Synthesizer Register, Address offset: 0x80 */ + __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register, Address offset: 0x84 */ + __IO uint32_t TSCSDIF_SR; /*!< DTS TSC SDIF Status Register, Address offset: 0x88 */ + __IO uint32_t TSCSDIF_CR; /*!< DTS TSC SDIF Register, Address offset: 0x8C */ + __IO uint32_t TSCSDIFHALTR; /*!< DTS TSC SDIF Halt Register, Address offset: 0x90 */ + __IO uint32_t TSCSDIF_CFGR; /*!< DTS TSC SDIF Control Register, Address offset: 0x94 */ + uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0x98-0x9F */ + __IO uint32_t TSCSMPL_CR; /*!< DTS TSC Sample Control Register, Address offset: 0xA0 */ + __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register, Address offset: 0xA4 */ + __IO uint32_t TSCSMPLCNTR; /*!< DTS TSC Sample Count Register, Address offset: 0xA8 */ +} DTS_TypeDef; + +/** + * @brief DTS Sensor Controller + */ +typedef struct +{ + __IO uint32_t TS_IER; /*!< DTS TSx IRQ Enable Register, Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TS_ISR; /*!< DTS TSx IRQ Status Register, Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TS_ICR; /*!< DTS TSx IRQ Clear Register, Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSIRQTESTR; /*!< DTS TSx IRQ Test Register, Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSSDIFRDATAR; /*!< DTS TSx SDIF RDATA Register, Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSSDIFDONER; /*!< DTS TSx SDIF Done Register, Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSSDIFDATAR; /*!< DTS TSx SDIF Data Register, Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */ + uint32_t RESERVED1[1]; /*!< Reserved, Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSALARMA_CFGR; /*!< DTS TSx Alarm A Configuration Register, Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSALARMB_CFGR; /*!< DTS TSx Alarm B Configuration Register, Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSHLSAMPLER; /*!< DTS TSx High/Low Sample Register, Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */ + __IO uint32_t TSHILORESETR; /*!< DTS TSx High/Low Reset Register, Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */ +} DTS_SensorTypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register, Address offset: 0x00 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register, Address offset: 0x04 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register , Address offset: 0x08 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register, Address offset: 0x0C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register, Address offset: 0x10 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register, Address offset: 0x14 */ + uint32_t RESERVED1[14]; + __IO uint32_t MACVTCR; /*!< VLAN tag Control register, Address offset: 0x50 */ + __IO uint32_t MACVTDR; /*!< VLAN tag data register, Address offset: 0x54 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register, Address offset: 0x58 */ + uint32_t RESERVED2; + __IO uint32_t MACVIR; /*!< VLAN inclusion register, Address offset: 0x60 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register, Address offset: 0x64 */ + uint32_t RESERVED3[2]; + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register, Address offset: 0x70 */ + uint32_t RESERVED4[7]; + __IO uint32_t MACRXFCR; /*!< Rx flow control register, Address offset: 0x90 */ + __IO uint32_t MACRXQCR; /*!< Rx Queue control register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register, Address offset: 0xA0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register, Address offset: 0xA4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register, Address offset: 0xA8 */ + uint32_t RESERVED6; + __IO uint32_t MACISR; /*!< Interrupt status register, Address offset: 0xB0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register, Address offset: 0xB4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register, Address offset: 0xB8 */ + uint32_t RESERVED7; + __IO uint32_t MACPCSR; /*!< PMT control status register, Address offset: 0xC0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register, Address offset: 0xC4 */ + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; /*!< LPI control and status register, Address offset: 0xD0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register, Address offset: 0xD4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register, Address offset: 0xD8 */ + __IO uint32_t MAC1USTCR; /*!< One-microsecond-tick counter register, Address offset: 0xDC */ + uint32_t RESERVED9[6]; + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register, Address offset: 0xF8 */ + uint32_t RESERVED10[5]; + __IO uint32_t MACVR; /*!< Version register, Address offset: 0x110 */ + __IO uint32_t MACDR; /*!< Debug register, Address offset: 0x114 */ + uint32_t RESERVED11; + __IO uint32_t MACHWF0R; /*!< HW feature 0 register, Address offset: 0x11C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register, Address offset: 0x120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register, Address offset: 0x124 */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register, Address offset: 0x128 */ + uint32_t RESERVED12[53]; + __IO uint32_t MACMDIOAR; /*!< MDIO address register, Address offset: 0x200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register, Address offset: 0x204 */ + uint32_t RESERVED13[2]; + __IO uint32_t MACARPAR; /*!< ARP address register, Address offset: 0x210 */ + uint32_t RESERVED14[7]; + __IO uint32_t MACCSRSWCR; /*!< CSR software control register, Address offset: 0x230 */ + __IO uint32_t MACFPECSR; /*!< FPE control and status register, Address offset: 0x234 */ + uint32_t RESERVED15[2]; + __IO uint32_t MACPRSTIMR; /*!< MAC presentation time register, Address offset: 0x0240 */ + __IO uint32_t MACPRSTIMUR; /*!< MAC presentation time update register, Address offset: 0x0244 */ + uint32_t RESERVED16[46]; + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register, Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register, Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register, Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register, Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register, Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register, Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register, Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register, Address offset: 0x031C */ + uint32_t RESERVED17[248]; + __IO uint32_t MMCCR; /*!< MMC control register, Address offset: 0x0700 */ + __IO uint32_t MMCRIR; /*!< MMC Rx interrupt register, Address offset: 0x0704 */ + __IO uint32_t MMCTIR; /*!< MMC Tx interrupt register, Address offset: 0x0708 */ + __IO uint32_t MMCRIMR; /*!< MMC Rx interrupt mask register, Address offset: 0x070C */ + __IO uint32_t MMCTIMR; /*!< MMC Tx interrupt mask register, Address offset: 0x0710 */ + uint32_t RESERVED18[14]; + __IO uint32_t MMCTSCGPR; /*!< Tx single collision good packets register, Address offset: 0x074C */ + __IO uint32_t MMCTMCGPR; /*!< Tx multiple collision good packets register, Address offset: 0x0750 */ + uint32_t RESERVED19[5]; + __IO uint32_t MMCTPCGR; /*!< Tx packet count good register, Address offset: 0x0768 */ + uint32_t RESERVED20[10]; + __IO uint32_t MMCRCRCEPR; /*!< Rx CRC error packets register, Address offset: 0x0794 */ + __IO uint32_t MMCRAEPR; /*!< Rx alignment error packets register, Address offset: 0x0798 */ + uint32_t RESERVED21[10]; + __IO uint32_t MMCRUPGR; /*!< Rx unicast packets good register, Address offset: 0x07C4 */ + uint32_t RESERVED22[9]; + __IO uint32_t MMCTLPIMSTR; /*!< Tx LPI microsecond timer register, Address offset: 0x07EC */ + __IO uint32_t MMCTLPITCR; /*!< Tx LPI transition counter register, Address offset: 0x07F0 */ + __IO uint32_t MMCRLPIMSTR; /*!< Rx LPI microsecond counter register, Address offset: 0x07F4 */ + __IO uint32_t MMCRLPITCR; /*!< Rx LPI transition counter register, Address offset: 0x07F8 */ + uint32_t RESERVED23[41]; + __IO uint32_t MMCFPETISR; /*!< MMC FPE Tx interrupt status register, Address offset: 0x08A0 */ + __IO uint32_t MMCFPETIMR; /*!< MMC FPE Tx interrupt mask register, Address offset: 0x08A4 */ + __IO uint32_t MMCFPETFCR; /*!< MMC FPE Tx fragment counter register, - Address offset: 0x08A8 */ + __IO uint32_t MMCTHRCR; /*!< MMC Tx hold request counter register, Address offset: 0x08AC */ + uint32_t RESERVED24[4]; + __IO uint32_t MMCFPERISR; /*!< MMC FPE Rx interrupt status register, Address offset: 0x08C0 */ + __IO uint32_t MMCFPERIMR; /*!< MMC FPE Rx interrupt mask register, Address offset: 0x08C4 */ + __IO uint32_t MMCRPAER; /*!< MMC Rx packet assembly error register, Address offset: 0x08C8 */ + __IO uint32_t MMCRPSMDER; /*!< MMC Rx packet SMD error register, Address offset: 0x08CC */ + __IO uint32_t MMCRPAOKR; /*!< MMC Rx packet assembly OK register, Address offset: 0x08D0 */ + __IO uint32_t MMCFPERFCR; /*!< MMC Rx FPE fragments counter register, Address offset: 0x08D4 */ + uint32_t RESERVED25[10]; + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register, Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 Address filter 0 register, Address offset: 0x0904 */ + uint32_t RESERVED26[2]; + __IO uint32_t MACL3A0R0R; /*!< Layer3 Address 0 filter 0 register, Address offset: 0x0910 */ + __IO uint32_t MACL3A1R0R; /*!< Layer3 Address 1 filter 0 register, Address offset: 0x0914 */ + __IO uint32_t MACL3A2R0R; /*!< Layer3 Address 2 filter 0 register, Address offset: 0x0918 */ + __IO uint32_t MACL3A3R0R; /*!< Layer3 Address 3 filter 0 register, Address offset: 0x091C */ + uint32_t RESERVED27[4]; + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register, Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register, Address offset: 0x0934 */ + uint32_t RESERVED28[2]; + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register, Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register, Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register, Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register, Address offset: 0x094C */ + uint32_t RESERVED29[72]; + __IO uint32_t MACIACR; /*!< MAC Indirect Access Control register, Address offset: 0x0A70 */ + __IO uint32_t MACTMRQR; /*!< MAC type-based Rx Queue mapping register, Address offset: 0x0A74 */ + uint32_t RESERVED30[34]; + __IO uint32_t MACTSCR; /*!< Timestamp control Register, Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Subsecond increment register, Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register, Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register, Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register, Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register, Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register, Address offset: 0x0B18 */ + uint32_t RESERVED31; + __IO uint32_t MACTSSR; /*!< Timestamp status register, Address offset: 0x0B20 */ + uint32_t RESERVED32[3]; + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register, Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register, Address offset: 0x0B34 */ + uint32_t RESERVED33[2]; + __IO uint32_t MACACR; /*!< Auxiliary control register, Address offset: 0x0B40 */ + uint32_t RESERVED34; + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register, Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register, Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register, Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register, Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register, Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register, Address offset: 0x0B5C */ + uint32_t RESERVED35[2]; + __IO uint32_t MACTSILR; /*!< Timestamp Ingress Latency register, Address offset: 0x0B68 */ + __IO uint32_t MACTSELR; /*!< Timestamp Egress Latency register, Address offset: 0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register, Address offset: 0x0B70 */ + uint32_t RESERVED36[3]; + __IO uint32_t MACPPSTTS0R; /*!< PPS 0 target time seconds register, Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTN0R; /*!< PPS 0 target time nanoseconds register, Address offset: 0x0B84 */ + __IO uint32_t MACPPSI0R; /*!< PPS 0 interval register, Address offset: 0x0B88 */ + __IO uint32_t MACPPSW0R; /*!< PPS 0 width register, Address offset: 0x0B8C */ + __IO uint32_t MACPPSTTS1R; /*!< PPS 1 target time seconds register, Address offset: 0x0B90 */ + __IO uint32_t MACPPSTTN1R; /*!< PPS 1 target time nanoseconds register, Address offset: 0x0B94 */ + __IO uint32_t MACPPSI1R; /*!< PPS 1 interval register, Address offset: 0x0B98 */ + __IO uint32_t MACPPSW1R; /*!< PPS 1 width register, Address offset: 0x0B9C */ + uint32_t RESERVED37[8]; + __IO uint32_t MACPOCR; /*!< PTP Offload control register, Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register, Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register, Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register, Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register, Address offset: 0x0BD0 */ + uint32_t RESERVED38[11]; + __IO uint32_t MTLOMR; /*!< Operating mode Register, Address offset: 0x0C00 */ + uint32_t RESERVED39[7]; + __IO uint32_t MTLISR; /*!< Interrupt status Register, Address offset: 0x0C20 */ + uint32_t RESERVED40[3]; + __IO uint32_t MTLRXQDMAMR; /*!< Rx Queue and DMA Channel Mapping Register, Address offset: 0x0C30 */ + uint32_t RESERVED41[3]; + __IO uint32_t MTLTBSCR; /*!< TBS control register, Address offset: 0x0C40 */ + uint32_t RESERVED42[3]; + __IO uint32_t MTLESTCR; /*!< EST Control Register, Address offset: 0x0C50 */ + __IO uint32_t MTLESTECR; /*!< EST Extended Control Register, Address offset: 0x0C54 */ + __IO uint32_t MTLESTSR; /*!< EST Status Register, Address offset: 0x0C58 */ + uint32_t RESERVED43; + __IO uint32_t MTLESTSCHER; /*!< EST Schedule Error Register, Address offset: 0x0C60 */ + __IO uint32_t MTLESTFSER; /*!< EST Frame size Error Register, Address offset: 0x0C64 */ + __IO uint32_t MTLESTFSCR; /*!< EST Frame size Capture Register, Address offset: 0x0C68 */ + uint32_t RESERVED44; + __IO uint32_t MTLESTIER; /*!< EST Interrupt Enable Register, Address offset: 0x0C70 */ + uint32_t RESERVED45[3]; + __IO uint32_t MTLESTGCLCR; /*!< EST Gate Control List Register, Address offset: 0x0C80 */ + __IO uint32_t MTLESTGCLDR; /*!< EST Gate Control List Data Register, Address offset: 0x0C84 */ + uint32_t RESERVED46[2]; + __IO uint32_t MTLFPECSR; /*!< FPE Frame Preemption Control Status Register, Address offset: 0x0C90 */ + __IO uint32_t MTLFPEAR; /*!< FPE Frame Preemption Advance Register, Address offset: 0x0C94 */ + uint32_t RESERVED47[26]; + struct { + __IO uint32_t MTLTXQOMR; /*!< Tx queue x operating mode Register, Address offset: 0x0D00 */ + __IO uint32_t MTLTXQUR; /*!< Tx queue x underflow register, Address offset: 0x0D04 */ + __IO uint32_t MTLTXQDR; /*!< Tx queue x debug register, Address offset: 0x0D08 */ + uint32_t RESERVED48[1]; + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register, Address offset: 0x0D50 */ + __IO uint32_t MTLTXQESR; /*!< Tx queue x ETS status Register, Address offset: 0x0D14 */ + __IO uint32_t MTLTXQQWR; /*!< Tx queue x quantum weight register, Address offset: 0x0D18 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register, Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register, Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register, Address offset: 0x0D64 */ + uint32_t RESERVED49[1]; + __IO uint32_t MTLQICSR; /*!< Queue 0 interrupt control status Register, Address offset: 0x0D2C */ + __IO uint32_t MTLRXQOMR; /*!< Rx queue x operating mode register, Address offset: 0x0D30 */ + __IO uint32_t MTLRXQMPOCR; /*!< Rx queue x missed packet and overflow counter register, Address offset: 0x0D34 */ + __IO uint32_t MTLRXQDR; /*!< Rx queue x debug register, Address offset: 0x0D38 */ + __IO uint32_t MTLRXQCR; /*!< Rx queue x control register, Address offset: 0x0D3C */ + } MTL_QUEUE[2]; + uint32_t RESERVED52[160]; + __IO uint32_t DMAMR; /*!< DMA mode register, Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register, Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register, Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register, Address offset: 0x100C */ + uint32_t RESERVED53[4]; + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register, Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register, Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register, Address offset: 0x1028 */ + uint32_t RESERVED54[5]; + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register, Address offset: 0x1040 */ + uint32_t RESERVED55[3]; + __IO uint32_t DMATBSCTRL0R; /*!< DMA TBS control register 0, Address offset: 0x1050 */ + uint32_t RESERVED56[37]; + struct { + uint32_t RESERVED57[6]; + __IO uint32_t DMACCR; /*!< Channel x control register, Address offset: 0x1100 */ + __IO uint32_t DMACTXCR; /*!< Channel x transmit control register, Address offset: 0x1104 */ + __IO uint32_t DMACRXCR; /*!< Channel x receive control register, Address offset: 0x1108 */ + uint32_t RESERVED58[2]; + __IO uint32_t DMACTXDLAR; /*!< Channel x Tx descriptor list address register, Address offset: 0x1114 */ + uint32_t RESERVED59; + __IO uint32_t DMACRXDLAR; /*!< Channel x Rx descriptor list address register, Address offset: 0x111C */ + __IO uint32_t DMACTXDTPR; /*!< Channel x Tx descriptor tail pointer register, Address offset: 0x1120 */ + uint32_t RESERVED60; + __IO uint32_t DMACRXDTPR; /*!< Channel x Rx descriptor tail pointer register, Address offset: 0x1128 */ + __IO uint32_t DMACTXRLR; /*!< Channel x Tx descriptor ring length register, Address offset: 0x112C */ + __IO uint32_t DMACRXRLR; /*!< Channel x Rx descriptor ring length register, Address offset: 0x1130 */ + __IO uint32_t DMACIER; /*!< Channel x interrupt enable register, Address offset: 0x1134 */ + __IO uint32_t DMACRXIWTR; /*!< Channel x Rx interrupt watchdog timer register, Address offset: 0x1138 */ + __IO uint32_t DMACSFCSR; /*!< Channel x slot function control status register, Address offset: 0x113C */ + uint32_t RESERVED61; + __IO uint32_t DMACCATXDR; /*!< Channel x current application transmit descriptor register, Address offset: 0x1144 */ + uint32_t RESERVED62; + __IO uint32_t DMACCARXDR; /*!< Channel x current application receive descriptor register, Address offset: 0x114C */ + uint32_t RESERVED63; + __IO uint32_t DMACCATXBR; /*!< Channel x current application transmit buffer register, Address offset: 0x1154 */ + uint32_t RESERVED64; + __IO uint32_t DMACCARXBR; /*!< Channel x current application receive buffer register, Address offset: 0x115C */ + __IO uint32_t DMACSR; /*!< Channel x status register, Address offset: 0x1160 */ + __IO uint32_t DMACMFCR; /*!< Channel x missed frame count register, Address offset: 0x1164 */ + } DMA_CH[2]; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x3C */ + __IO uint32_t RTSR3; /*!< EXTI Rising Trigger Selection Register 3, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling Trigger Selection Register 3, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software Interrupt event Register 3, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Pending Register 3, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Pending Register 3, Address offset: 0x50 */ + __IO uint32_t SECCFGR3; /*!< EXTI Security Configuration Register 3, Address offset: 0x54 */ + __IO uint32_t PRIVCFGR3; /*!< EXTI Privilege Configuration Register 3, Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED4[3]; /*!< Reserved 4, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ + uint32_t RESERVED6[2]; /*!< Reserved 6, 0x98 -- 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt Mask Register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event Mask Register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111];/*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM device 1/2 control register Address offset: 0x140-0x144 */ + __IO uint32_t SDTR; /*!< SDRAM timing register Address offset: 0x148 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM command mode register Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM refresh timer register Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM status register Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash Programmable control register Address offset: 0x080 */ + __IO uint32_t SR; /*!< FMC status register Address offset: 0x084 */ + __IO uint32_t PMEM; /*!< Common memory space timing register Address offset: 0x088 */ + __IO uint32_t PATT; /*!< Attribute memory space timing registers Address offset: 0x08C */ + __IO uint32_t HPR; /*!< FMC Hamming parity result registers Address offset: 0x090 */ + __IO uint32_t HECCR; /*!< FMC Hamming code ECC result register Address offset: 0x094 */ + uint32_t RESERVED0[58]; /*!< Reserved Address offset: 0x098-0x17C */ + __IO uint32_t IER; /*!< FMC NAND Interrupt Enable Register Address offset: 0x180 */ + __IO uint32_t ISR; /*!< FMC Controller Interrupt Status Register Address offset: 0x184 */ + __IO uint32_t ICR; /*!< FMC NAND Controller Interrupt Clear Register Address offset: 0x188 */ + uint32_t RESERVED1[29]; /*!< Reserved Address offset: 0x18C-0x1FC */ + __IO uint32_t CSQCR; /*!< FMC NAND Command Sequencer Control Register Address offset: 0x200 */ + __IO uint32_t CSQCFGR1; /*!< FMC NAND Command Sequencer Configuration Register 1 Address offset: 0x204 */ + __IO uint32_t CSQCFGR2; /*!< FMC NAND Command Sequencer Configuration Register 2 Address offset: 0x208 */ + __IO uint32_t CSQCFGR3; /*!< FMC NAND sequencer configuration register 3 Address offset: 0x20C */ + __IO uint32_t CSQAR1; /*!< FMC NAND Command Sequencer Address Register 1 Address offset: 0x210 */ + __IO uint32_t CSQAR2; /*!< FMC NAND Command Sequencer Address Register 2 Address offset: 0x214 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x218-0x21C */ + __IO uint32_t CSQIER; /*!< FMC NAND Command Sequencer Interrupt Enable Register Address offset: 0x220 */ + __IO uint32_t CSQISR; /*!< FMC NAND Command Sequencer Interrupt Status Register Address offset: 0x224 */ + __IO uint32_t CSQICR; /*!< FMC NAND Command Sequencer Interrupt Clear Register Address offset: 0x228 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x22C */ + __IO uint32_t CSQEMSR; /*!< FMC Command Sequencer Error Mapping Status register Address offset: 0x230 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x234-0x24C */ + __IO uint32_t BCHIER; /*!< FMC BCH Interrupt enable register Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< FMC BCH Interrupt and Status Register Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< FMC BCH Interrupt Clear Register Address offset: 0x258 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x25C */ + __IO uint32_t BCHPBR1; /*!< FMC BCH Parity Bits Register 1 Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< FMC BCH Parity Bits Register 2 Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< FMC BCH Parity Bits Register 3 Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< FMC BCH Parity Bits Register 4 Address offset: 0x26C */ + uint32_t RESERVED6[3]; /*!< Reserved Address offset: 0x270-0x278 */ + __IO uint32_t BCHDSR0; /*!< FMC BCH Decoder Status register 0 Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< FMC BCH Decoder Status register for bank 1 Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< FMC BCH Decoder Status register for bank 2 Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< FMC BCH Decoder Status register for bank 3 Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< FMC BCH Decoder Status register for bank 4 Address offset: 0x28C */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Common + */ +typedef struct{ + __IO uint32_t CFGR; /*!< FMC common configuration register Address offset: 0x020 */ +} FMC_Common_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO port secure configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< GPIO port privileged configuration register, Address offset: 0x34 */ + __IO uint32_t RCFGLOCKR; /*!< GPIO port resource configuration register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t DELAYR[2]; /*!< GPIO port delay register, Address offset: 0x40-0x44 */ + __IO uint32_t ADVCFGR[2]; /*!< GPIO port advanced configuration register, Address offset: 0x48-0x4C */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief Illegal Access Controller + */ +typedef struct +{ + __IO uint32_t IER[5]; /*!< Interrupt Enable register, Address offset: 0x000 */ + uint32_t RESERVED1[27]; /*!< Reserved, Address offset: 0x014-0x07C */ + __IO uint32_t ISR[5]; /*!< Interrupt Status register, Address offset: 0x080 */ + uint32_t RESERVED2[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t ICR[5]; /*!< Interrupt Clear register, Address offset: 0x100 */ +} IAC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ +} ICACHE_TypeDef; + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG key register Address offset: 0x000 */ + __IO uint32_t PR; /*!< IWDG prescaler register Address offset: 0x004 */ + __IO uint32_t RLR; /*!< IWDG reload register Address offset: 0x008 */ + __IO uint32_t SR; /*!< IWDG status register Address offset: 0x00C */ + __IO uint32_t WINR; /*!< IWDG window register Address offset: 0x010 */ + __IO uint32_t EWCR; /*!< IWDG early wakeup interrupt register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< IWDG interrupt clear register Address offset: 0x018 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller (LTDC) + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC synchronization size configuration register Address offset: 0x8 */ + __IO uint32_t BPCR; /*!< LTDC back porch configuration register Address offset: 0xc */ + __IO uint32_t AWCR; /*!< LTDC active width configuration register Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC total width configuration register Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC global control register Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: */ + __IO uint32_t SRCR; /*!< LTDC shadow reload configuration register Address offset: 0x24 */ + __IO uint32_t GCCR; /*!< LTDC gamma correction configuration register Address offset: 0x28 */ + __IO uint32_t BCCR; /*!< LTDC background color configuration register Address offset: 0x2c */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x30 */ + __IO uint32_t IER; /*!< LTDC interrupt enable register Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC interrupt status register Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register Address offset: 0x3c */ + __IO uint32_t LIPCR; /*!< LTDC line interrupt position configuration register Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC current position status register Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC current display status register Address offset: 0x48 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x4c */ + __IO uint32_t EDCR; /*!< LTDC external display control register Address offset: 0x60 */ + __IO uint32_t IER2; /*!< LTDC interrupt enable register 2 Address offset: 0x64 */ + __IO uint32_t ISR2; /*!< LTDC interrupt status register 2 Address offset: 0x68 */ + __IO uint32_t ICR2; /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */ + __IO uint32_t LIPCR2; /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x74 */ + __IO uint32_t ECRCR; /*!< LTDC expected CRC register Address offset: 0x78 */ + __IO uint32_t CCRCR; /*!< LTDC computed CRC register Address offset: 0x7c */ + __IO uint32_t RB0AR; /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */ + __IO uint32_t RB1AR; /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */ + __IO uint32_t RBPR; /*!< LTDC rotation buffer pitch register Address offset: 0x88 */ + __IO uint32_t RIFCR; /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */ + __IO uint32_t FUTR; /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller (LTDC) + */ +typedef struct +{ + __IO uint32_t C0R; /*!< LTDC layer x configuration 0 register Address offset: 0x100 */ + __IO uint32_t C1R; /*!< LTDC layer x configuration 1 register Address offset: 0x104 */ + __IO uint32_t RCR; /*!< LTDC layer x reload control register Address offset: 0x108 */ + __IO uint32_t CR; /*!< LTDC layer x control register Address offset: 0x10c */ + __IO uint32_t WHPCR; /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */ + __IO uint32_t WVPCR; /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */ + __IO uint32_t CKCR; /*!< LTDC layer x color keying configuration register Address offset: 0x118 */ + __IO uint32_t PFCR; /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */ + __IO uint32_t CACR; /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */ + __IO uint32_t DCCR; /*!< LTDC layer x default color configuration register Address offset: 0x124 */ + __IO uint32_t BFCR; /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */ + __IO uint32_t BLCR; /*!< LTDC layer x burst length configuration register Address offset: 0x12c */ + __IO uint32_t PCR; /*!< LTDC layer x planar configuration register Address offset: 0x130 */ + __IO uint32_t CFBAR; /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */ + __IO uint32_t CFBLR; /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */ + __IO uint32_t CFBLNR; /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */ + __IO uint32_t AFBA0R; /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */ + __IO uint32_t AFBA1R; /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */ + __IO uint32_t AFBLR; /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */ + __IO uint32_t AFBLNR; /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */ + __IO uint32_t CLUTWR; /*!< LTDC layer x CLUT write register Address offset: 0x150 */ + __IO uint32_t SISR; /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */ + __IO uint32_t SOSR; /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */ + __IO uint32_t SVSFR; /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */ + __IO uint32_t SVSPR; /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */ + __IO uint32_t SHSFR; /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */ + __IO uint32_t SHSPR; /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */ + __IO uint32_t CYR0R; /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */ + __IO uint32_t CYR1R; /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */ + __IO uint32_t FPF0R; /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */ + __IO uint32_t FPF1R; /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */ +} LTDC_Layer_TypeDef; + + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Memory Cipher Engine (MCE) + */ +typedef struct +{ + __IO uint32_t REGCR; /*!< MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t SADDR; /*!< MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t EADDR; /*!< MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */ +} MCE_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CCCFGR; /*!< MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR0; /*!< MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR1; /*!< MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR0; /*!< MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR1; /*!< MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR2; /*!< MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR3; /*!< MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */ +} MCE_Context_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MCE configuration register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< MCE status register, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< MCE illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< MCE illegal access clear register, Address offset: 0x00C */ + __IO uint32_t IAIER; /*!< MCE illegal access interrupt enable register, Address offset: 0x010 */ + uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x014-0x20 */ + __IO uint32_t IADDR; /*!< MCE illegal address register, Address offset: 0x024 */ + uint32_t RESERVED1[118]; /*!< Reserved, Address offset: 0x028-0x1FC */ + __IO uint32_t MKEYR0; /*!< MCE master key register 0, Address offset: 0x200 */ + __IO uint32_t MKEYR1; /*!< MCE master key register 1, Address offset: 0x204 */ + __IO uint32_t MKEYR2; /*!< MCE master key register 2, Address offset: 0x208 */ + __IO uint32_t MKEYR3; /*!< MCE master key register 3, Address offset: 0x20C */ + __IO uint32_t MKEYR4; /*!< MCE master key register 4, Address offset: 0x210 */ + __IO uint32_t MKEYR5; /*!< MCE master key register 5, Address offset: 0x214 */ + __IO uint32_t MKEYR6; /*!< MCE master key register 6, Address offset: 0x218 */ + __IO uint32_t MKEYR7; /*!< MCE master key register 7, Address offset: 0x21C */ + __IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address offset: 0x220 */ + __IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address offset: 0x224 */ + __IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address offset: 0x228 */ + __IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address offset: 0x22C */ + __IO uint32_t FMKEYR4; /*!< MCE fast master key register 4, Address offset: 0x230 */ + __IO uint32_t FMKEYR5; /*!< MCE fast master key register 5, Address offset: 0x234 */ + __IO uint32_t FMKEYR6; /*!< MCE fast master key register 6, Address offset: 0x238 */ + __IO uint32_t FMKEYR7; /*!< MCE fast master key register 7, Address offset: 0x23C */ +} MCE_TypeDef; + + + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Control register 1 Address offset: 0x000 */ + __IO uint32_t CR2; /*!< PWR Control Register 2 Address offset: 0x004 */ + __IO uint32_t CR3; /*!< PWR Control Register 3 Address offset: 0x008 */ + __IO uint32_t CR4; /*!< PWR Control Register 4 Address offset: 0x00C */ + uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x010-0x01C */ + __IO uint32_t VOSCR; /*!< PWR Voltage scaling control register Address offset: 0x020 */ + __IO uint32_t BDCR1; /*!< PWR Backup domain control register 1 Address offset: 0x024 */ + __IO uint32_t BDCR2; /*!< PWR Backup domain control register 2 Address offset: 0x028 */ + __IO uint32_t DBPCR; /*!< PWR Disable backup protection control register Address offset: 0x02C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register Address offset: 0x030 */ + __IO uint32_t SVMCR1; /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */ + __IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */ + __IO uint32_t SVMCR3; /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */ + uint32_t RESERVED1[4]; /*!< Reserved Address offset: 0x040-0x04C */ + __IO uint32_t WKUPCR; /*!< PWR Wakeup control register 1 Address offset: 0x050 */ + __IO uint32_t WKUPSR; /*!< PWR Wakeup control register 2 Address offset: 0x054 */ + __IO uint32_t WKUPEPR; /*!< PWR Wakeup control register 3 Address offset: 0x058 */ + uint32_t RESERVED2[5]; /*!< Reserved Address offset: 0x05C-0x06C */ + __IO uint32_t SECCFGR; /*!< PWR Security configuration register Address offset: 0x070 */ + __IO uint32_t PRIVCFGR; /*!< PWR Privilege configuration register Address offset: 0x074 */ +} PWR_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief RAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t ESEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t EDEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x18-0x20 */ + __IO uint32_t ECCKEYR; /*!< RAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< RAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC control register Address offset: 0x0000 */ + __IO uint32_t SR; /*!< RCC status register Address offset: 0x0004 */ + __IO uint32_t STOPCR; /*!< RCC Stop mode control register Address offset: 0x0008 */ + uint32_t RESERVED0[5]; /*!< Reserved Address offset: 0x000C-0x001C */ + __IO uint32_t CFGR1; /*!< RCC configuration register 1 Address offset: 0x0020 */ + __IO uint32_t CFGR2; /*!< RCC configuration register 2 Address offset: 0x0024 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0028 */ + __IO uint32_t BDCR; /*!< RCC backup domain protection register Address offset: 0x002C */ + __IO uint32_t HWRSR; /*!< RCC reset status register for hardware Address offset: 0x0030 */ + __IO uint32_t RSR; /*!< RCC reset register Address offset: 0x0034 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0038-0x003C */ + __IO uint32_t LSECFGR; /*!< RCC LSE configuration register Address offset: 0x0040 */ + __IO uint32_t MSICFGR; /*!< RCC MSI configuration register Address offset: 0x0044 */ + __IO uint32_t HSICFGR; /*!< RCC HSI configuration register Address offset: 0x0048 */ + __IO uint32_t HSIMCR; /*!< RCC HSI Monitor control register Address offset: 0x004C */ + __IO uint32_t HSIMSR; /*!< RCC HSI Monitor status register Address offset: 0x0050 */ + __IO uint32_t HSECFGR; /*!< RCC HSE configuration register Address offset: 0x0054 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x0058-0x007C */ + __IO uint32_t PLL1CFGR1; /*!< RCC PLL1 configuration register 1 Address offset: 0x0080 */ + __IO uint32_t PLL1CFGR2; /*!< RCC PLL1 configuration register 2 Address offset: 0x0084 */ + __IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 Address offset: 0x0088 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x008C */ + __IO uint32_t PLL2CFGR1; /*!< RCC PLL2 configuration register 1 Address offset: 0x0090 */ + __IO uint32_t PLL2CFGR2; /*!< RCC PLL2 configuration register 2 Address offset: 0x0094 */ + __IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 Address offset: 0x0098 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t PLL3CFGR1; /*!< RCC PLL3 configuration register 1 Address offset: 0x00A0 */ + __IO uint32_t PLL3CFGR2; /*!< RCC PLL3 configuration register 2 Address offset: 0x00A4 */ + __IO uint32_t PLL3CFGR3; /*!< RCC PLL3 configuration register 3 Address offset: 0x00A8 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t PLL4CFGR1; /*!< RCC PLL4 configuration register 1 Address offset: 0x00B0 */ + __IO uint32_t PLL4CFGR2; /*!< RCC PLL4 configuration register 2 Address offset: 0x00B4 */ + __IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 Address offset: 0x00B8 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x00BC-0x00C0 */ + __IO uint32_t IC1CFGR; /*!< RCC IC1 configuration register Address offset: 0x00C4 */ + __IO uint32_t IC2CFGR; /*!< RCC IC2 configuration register Address offset: 0x00C8 */ + __IO uint32_t IC3CFGR; /*!< RCC IC3 configuration register Address offset: 0x00CC */ + __IO uint32_t IC4CFGR; /*!< RCC IC4 configuration register Address offset: 0x00D0 */ + __IO uint32_t IC5CFGR; /*!< RCC IC5 configuration register Address offset: 0x00D4 */ + __IO uint32_t IC6CFGR; /*!< RCC IC6 configuration register Address offset: 0x00D8 */ + __IO uint32_t IC7CFGR; /*!< RCC IC7 configuration register Address offset: 0x00DC */ + __IO uint32_t IC8CFGR; /*!< RCC IC8 configuration register Address offset: 0x00E0 */ + __IO uint32_t IC9CFGR; /*!< RCC IC9 configuration register Address offset: 0x00E4 */ + __IO uint32_t IC10CFGR; /*!< RCC IC10 configuration register Address offset: 0x00E8 */ + __IO uint32_t IC11CFGR; /*!< RCC IC11 configuration register Address offset: 0x00EC */ + __IO uint32_t IC12CFGR; /*!< RCC IC12 configuration register Address offset: 0x00F0 */ + __IO uint32_t IC13CFGR; /*!< RCC IC13 configuration register Address offset: 0x00F4 */ + __IO uint32_t IC14CFGR; /*!< RCC IC14 configuration register Address offset: 0x00F8 */ + __IO uint32_t IC15CFGR; /*!< RCC IC15 configuration register Address offset: 0x00FC */ + __IO uint32_t IC16CFGR; /*!< RCC IC16 configuration register Address offset: 0x0100 */ + __IO uint32_t IC17CFGR; /*!< RCC IC17 configuration register Address offset: 0x0104 */ + __IO uint32_t IC18CFGR; /*!< RCC IC18 configuration register Address offset: 0x0108 */ + __IO uint32_t IC19CFGR; /*!< RCC IC19 configuration register Address offset: 0x010C */ + __IO uint32_t IC20CFGR; /*!< RCC IC20 configuration register Address offset: 0x0110 */ + uint32_t RESERVED8[4]; /*!< Reserved Address offset: 0x0114-0x0120 */ + __IO uint32_t CIER; /*!< RCC clock-source interrupt enable register Address offset: 0x0124 */ + __IO uint32_t CIFR; /*!< RCC clock-source interrupt flag register Address offset: 0x0128 */ + __IO uint32_t CICR; /*!< RCC clock-source interrupt clear register Address offset: 0x012C */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x0130-0x0140 */ + __IO uint32_t CCIPR1; /*!< RCC clock configuration for independent peripheral register 1 Address offset: 0x0144 */ + __IO uint32_t CCIPR2; /*!< RCC clock configuration for independent peripheral register 2 Address offset: 0x0148 */ + __IO uint32_t CCIPR3; /*!< RCC clock configuration for independent peripheral register 3 Address offset: 0x014C */ + __IO uint32_t CCIPR4; /*!< RCC clock configuration for independent peripheral register 4 Address offset: 0x0150 */ + __IO uint32_t CCIPR5; /*!< RCC clock configuration for independent peripheral register 5 Address offset: 0x0154 */ + __IO uint32_t CCIPR6; /*!< RCC clock configuration for independent peripheral register 6 Address offset: 0x0158 */ + __IO uint32_t CCIPR7; /*!< RCC clock configuration for independent peripheral register 7 Address offset: 0x015C */ + __IO uint32_t CCIPR8; /*!< RCC clock configuration for independent peripheral register 8 Address offset: 0x0160 */ + __IO uint32_t CCIPR9; /*!< RCC clock configuration for independent peripheral register 9 Address offset: 0x0164 */ + uint32_t RESERVED10[2]; /*!< Reserved Address offset: 0x0168-0x016C */ + __IO uint32_t CCIPR12; /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */ + __IO uint32_t CCIPR13; /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */ + __IO uint32_t CCIPR14; /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */ + uint32_t RESERVED11[35]; /*!< Reserved Address offset: 0x017C-0x0204 */ + __IO uint32_t MISCRSTR; /*!< RCC miscellaneous configurations reset register Address offset: 0x0208 */ + __IO uint32_t MEMRSTR; /*!< RCC embedded memories reset register Address offset: 0x020C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 reset register Address offset: 0x0210 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 reset register Address offset: 0x0214 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 reset register Address offset: 0x0218 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 reset register Address offset: 0x021C */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 reset register Address offset: 0x0220 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 reset register 1 Address offset: 0x0224 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 reset register 2 Address offset: 0x0228 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 reset register Address offset: 0x022C */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x0230 */ + __IO uint32_t APB4RSTR1; /*!< RCC APB4 reset register 1 Address offset: 0x0234 */ + __IO uint32_t APB4RSTR2; /*!< RCC APB4 reset register 2 Address offset: 0x0238 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 reset register Address offset: 0x023C */ + __IO uint32_t DIVENR; /*!< RCC IC dividers enable register Address offset: 0x0240 */ + __IO uint32_t BUSENR; /*!< RCC embedded buses enable register Address offset: 0x0244 */ + __IO uint32_t MISCENR; /*!< RCC miscellaneous configurations enable register Address offset: 0x0248 */ + __IO uint32_t MEMENR; /*!< RCC embedded memories enable register Address offset: 0x024C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 enable register Address offset: 0x0250 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 enable register Address offset: 0x0254 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 enable register Address offset: 0x0258 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 enable register Address offset: 0x025C */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register Address offset: 0x0260 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 enable register 1 Address offset: 0x0264 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 enable register 2 Address offset: 0x0268 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 enable register Address offset: 0x026C */ + __IO uint32_t APB3ENR; /*!< RCC APB3 enable register Address offset: 0x0270 */ + __IO uint32_t APB4ENR1; /*!< RCC APB4 enable register 1 Address offset: 0x0274 */ + __IO uint32_t APB4ENR2; /*!< RCC APB4 enable register 2 Address offset: 0x0278 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 enable register Address offset: 0x027C */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x0280 */ + __IO uint32_t BUSLPENR; /*!< RCC embedded buses sleep enable register Address offset: 0x0284 */ + __IO uint32_t MISCLPENR; /*!< RCC miscellaneous configurations sleep enable register Address offset: 0x0288 */ + __IO uint32_t MEMLPENR; /*!< RCC embedded memories sleep enable register Address offset: 0x028C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 sleep enable register Address offset: 0x0290 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 sleep enable register Address offset: 0x0294 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 sleep enable register Address offset: 0x0298 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 sleep enable register Address offset: 0x029C */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 sleep enable register Address offset: 0x02A0 */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x02A4 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x02A8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 sleep enable register Address offset: 0x02AC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 sleep enable register Address offset: 0x02B0 */ + __IO uint32_t APB4LPENR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x02B4 */ + __IO uint32_t APB4LPENR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x02B8 */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 sleep enable register Address offset: 0x02BC */ + uint32_t RESERVED14[99]; /*!< Reserved Address offset: 0x02C0-0x0448 */ + __IO uint32_t RDCR; /*!< RCC reset duration control register Address offset: 0x044C */ + uint32_t RESERVED15[204]; /*!< Reserved Address offset: 0x0450-0x077C */ + __IO uint32_t SECCFGR0; /*!< RCC oscillator secure configuration register 0 Address offset: 0x0780 */ + __IO uint32_t PRIVCFGR0; /*!< RCC oscillator privilege configuration register 0 Address offset: 0x0784 */ + __IO uint32_t LOCKCFGR0; /*!< RCC oscillator lock configuration register 0 Address offset: 0x0788 */ + __IO uint32_t PUBCFGR0; /*!< RCC oscillator public configuration register 0 Address offset: 0x078C */ + __IO uint32_t SECCFGR1; /*!< RCC PLL secure configuration register 1 Address offset: 0x0790 */ + __IO uint32_t PRIVCFGR1; /*!< RCC PLL privilege configuration register 1 Address offset: 0x0794 */ + __IO uint32_t LOCKCFGR1; /*!< RCC PLL lock configuration register 1 Address offset: 0x0798 */ + __IO uint32_t PUBCFGR1; /*!< RCC PLL public configuration register 1 Address offset: 0x079C */ + __IO uint32_t SECCFGR2; /*!< RCC divider secure configuration register 2 Address offset: 0x07A0 */ + __IO uint32_t PRIVCFGR2; /*!< RCC divider privilege configuration register 2 Address offset: 0x07A4 */ + __IO uint32_t LOCKCFGR2; /*!< RCC divider lock configuration register 2 Address offset: 0x07A8 */ + __IO uint32_t PUBCFGR2; /*!< RCC divider public configuration register 2 Address offset: 0x07AC */ + __IO uint32_t SECCFGR3; /*!< RCC system secure configuration register 3 Address offset: 0x07B0 */ + __IO uint32_t PRIVCFGR3; /*!< RCC system privilege configuration register 3 Address offset: 0x07B4 */ + __IO uint32_t LOCKCFGR3; /*!< RCC system lock configuration register 3 Address offset: 0x07B8 */ + __IO uint32_t PUBCFGR3; /*!< RCC system public configuration register 3 Address offset: 0x07BC */ + __IO uint32_t SECCFGR4; /*!< RCC bus secure configuration register 4 Address offset: 0x07C0 */ + __IO uint32_t PRIVCFGR4; /*!< RCC bus privilege configuration register 4 Address offset: 0x07C4 */ + __IO uint32_t LOCKCFGR4; /*!< RCC bus lock configuration register 4 Address offset: 0x07C8 */ + __IO uint32_t PUBCFGR4; /*!< RCC bus public configuration register 4 Address offset: 0x07CC */ + __IO uint32_t PUBCFGR5; /*!< RCC bus public configuration register 4 Address offset: 0x07D0 */ + uint32_t RESERVED16[11]; /*!< Reserved Address offset: 0x07D4-0x07FC */ + __IO uint32_t CSR; /*!< RCC control Set register Address offset: 0x0800 */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0x0804 */ + __IO uint32_t STOPCSR; /*!< RCC STOPCSR configuration register Address offset: 0x0808 */ + uint32_t RESERVED18[127]; /*!< Reserved Address offset: 0x080C-0x0A00 */ + __IO uint32_t MISCRSTSR; /*!< RCC miscellaneous reset register Address offset: 0x0A08 */ + __IO uint32_t MEMRSTSR; /*!< RCC memory reset register Address offset: 0x0A0C */ + __IO uint32_t AHB1RSTSR; /*!< RCC AHB1 reset register Address offset: 0x0A10 */ + __IO uint32_t AHB2RSTSR; /*!< RCC AHB2 reset register Address offset: 0x0A14 */ + __IO uint32_t AHB3RSTSR; /*!< RCC AHB3 reset register Address offset: 0x0A18 */ + __IO uint32_t AHB4RSTSR; /*!< RCC AHB4 reset register Address offset: 0x0A1C */ + __IO uint32_t AHB5RSTSR; /*!< RCC AHB5 reset register Address offset: 0x0A20 */ + __IO uint32_t APB1RSTSR1; /*!< RCC APB1 reset register 1 Address offset: 0x0A24 */ + __IO uint32_t APB1RSTSR2; /*!< RCC APB1 reset register 2 Address offset: 0x0A28 */ + __IO uint32_t APB2RSTSR; /*!< RCC APB2 reset register Address offset: 0x0A2C */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x0A30 */ + __IO uint32_t APB4RSTSR1; /*!< RCC APB4 reset register 1 Address offset: 0x0A34 */ + __IO uint32_t APB4RSTSR2; /*!< RCC APB4 reset register 2 Address offset: 0x0A38 */ + __IO uint32_t APB5RSTSR; /*!< RCC APB5 reset register Address offset: 0x0A3C */ + __IO uint32_t DIVENSR; /*!< RCC divider enable register Address offset: 0x0A40 */ + __IO uint32_t BUSENSR; /*!< RCC bus enable register Address offset: 0x0A44 */ + __IO uint32_t MISCENSR; /*!< RCC miscellaneous enable register Address offset: 0x0A48 */ + __IO uint32_t MEMENSR; /*!< RCC memory enable register Address offset: 0x0A4C */ + __IO uint32_t AHB1ENSR; /*!< RCC AHB1 enable register Address offset: 0x0A50 */ + __IO uint32_t AHB2ENSR; /*!< RCC AHB2 enable register Address offset: 0x0A54 */ + __IO uint32_t AHB3ENSR; /*!< RCC AHB3 enable register Address offset: 0x0A58 */ + __IO uint32_t AHB4ENSR; /*!< RCC AHB4 enable register Address offset: 0x0A5C */ + __IO uint32_t AHB5ENSR; /*!< RCC AHB5 enable register Address offset: 0x0A60 */ + __IO uint32_t APB1ENSR1; /*!< RCC APB1 enable register 1 Address offset: 0x0A64 */ + __IO uint32_t APB1ENSR2; /*!< RCC APB1 enable register 2 Address offset: 0x0A68 */ + __IO uint32_t APB2ENSR; /*!< RCC APB2 enable register Address offset: 0x0A6C */ + __IO uint32_t APB3ENSR; /*!< RCC APB3 enable register Address offset: 0x0A70 */ + __IO uint32_t APB4ENSR1; /*!< RCC APB4 enable register 1 Address offset: 0x0A74 */ + __IO uint32_t APB4ENSR2; /*!< RCC APB4 enable register 2 Address offset: 0x0A78 */ + __IO uint32_t APB5ENSR; /*!< RCC APB5 enable register Address offset: 0x0A7C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x0A80 */ + __IO uint32_t BUSLPENSR; /*!< RCC bus sleep enable register Address offset: 0x0A84 */ + __IO uint32_t MISCLPENSR; /*!< RCC miscellaneous sleep enable register Address offset: 0x0A88 */ + __IO uint32_t MEMLPENSR; /*!< RCC memory sleep enable register Address offset: 0x0A8C */ + __IO uint32_t AHB1LPENSR; /*!< RCC AHB1 sleep enable register Address offset: 0x0A90 */ + __IO uint32_t AHB2LPENSR; /*!< RCC AHB2 sleep enable register Address offset: 0x0A94 */ + __IO uint32_t AHB3LPENSR; /*!< RCC AHB3 sleep enable register Address offset: 0x0A98 */ + __IO uint32_t AHB4LPENSR; /*!< RCC AHB4 sleep enable register Address offset: 0x0A9C */ + __IO uint32_t AHB5LPENSR; /*!< RCC AHB5 sleep enable register Address offset: 0x0AA0 */ + __IO uint32_t APB1LPENSR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x0AA4 */ + __IO uint32_t APB1LPENSR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x0AA8 */ + __IO uint32_t APB2LPENSR; /*!< RCC APB2 sleep enable register Address offset: 0x0AAC */ + __IO uint32_t APB3LPENSR; /*!< RCC APB3 sleep enable register Address offset: 0x0AB0 */ + __IO uint32_t APB4LPENSR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x0AB4 */ + __IO uint32_t APB4LPENSR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x0AB8 */ + __IO uint32_t APB5LPENSR; /*!< RCC APB5 sleep enable register Address offset: 0x0ABC */ + uint32_t RESERVED21[305]; /*!< Reserved Address offset: 0x0AC0-0x0F80 */ + __IO uint32_t PRIVCFGSR0; /*!< RCC oscillator privilege configuration set register 0 Address offset: 0x0F84 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0F88 */ + __IO uint32_t PUBCFGSR0; /*!< RCC oscillator public configuration set register 0 Address offset: 0x0F8C */ + uint32_t RESERVED23; /*!< Reserved Address offset: 0x0F90 */ + __IO uint32_t PRIVCFGSR1; /*!< RCC PLL privilege configuration set register 1 Address offset: 0x0F94 */ + uint32_t RESERVED24; /*!< Reserved Address offset: 0x0F98 */ + __IO uint32_t PUBCFGSR1; /*!< RCC PLL public configuration set register 1 Address offset: 0x0F9C */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0FA0 */ + __IO uint32_t PRIVCFGSR2; /*!< RCC divider privilege configuration set register 2 Address offset: 0x0FA4 */ + uint32_t RESERVED26; /*!< Reserved Address offset: 0x0FA8 */ + __IO uint32_t PUBCFGSR2; /*!< RCC divider public configuration set register 2 Address offset: 0x0FAC */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0FB0 */ + __IO uint32_t PRIVCFGSR3; /*!< RCC system privilege configuration set register 3 Address offset: 0x0FB4 */ + uint32_t RESERVED28; /*!< Reserved Address offset: 0x0FB8 */ + __IO uint32_t PUBCFGSR3; /*!< RCC system public configuration set register 3 Address offset: 0x0FBC */ + uint32_t RESERVED29; /*!< Reserved Address offset: 0x0FC0 */ + __IO uint32_t PRIVCFGSR4; /*!< RCC privilege configuration set register 4 Address offset: 0x0FC4 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0FC8 */ + __IO uint32_t PUBCFGSR4; /*!< RCC public configuration set register 4 Address offset: 0x0FCC */ + __IO uint32_t PUBCFGSR5; /*!< RCC public configuration set register 5 Address offset: 0x0FD0 */ + uint32_t RESERVED31[11]; /*!< Reserved Address offset: 0x0FD4-0x0FFC */ + __IO uint32_t CCR; /*!< RCC control clear register Address offset: 0x1000 */ + uint32_t RESERVED32; /*!< Reserved Address offset: 0x1004 */ + __IO uint32_t STOPCCR; /*!< RCC Stop mode configuration clear register Address offset: 0x1008 */ + uint32_t RESERVED33[127]; /*!< Reserved Address offset: 0x100C-0x1200 */ + __IO uint32_t MISCRSTCR; /*!< RCC miscellaneous reset clear register Address offset: 0x1208 */ + __IO uint32_t MEMRSTCR; /*!< RCC memory reset clear register Address offset: 0x120C */ + __IO uint32_t AHB1RSTCR; /*!< RCC AHB1 reset clear register Address offset: 0x1210 */ + __IO uint32_t AHB2RSTCR; /*!< RCC AHB2 reset clear register Address offset: 0x1214 */ + __IO uint32_t AHB3RSTCR; /*!< RCC AHB3 reset r clear register Address offset: 0x1218 */ + __IO uint32_t AHB4RSTCR; /*!< RCC AHB4 reset clear register Address offset: 0x121C */ + __IO uint32_t AHB5RSTCR; /*!< RCC AHB5 reset clear register Address offset: 0x1220 */ + __IO uint32_t APB1RSTCR1; /*!< RCC APB1 reset clear register 1 Address offset: 0x1224 */ + __IO uint32_t APB1RSTCR2; /*!< RCC APB1 reset clear register 2 Address offset: 0x1228 */ + __IO uint32_t APB2RSTCR; /*!< RCC APB2 reset clear register Address offset: 0x122C */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x1230 */ + __IO uint32_t APB4RSTCR1; /*!< RCC APB4 reset clear register 1 Address offset: 0x1234 */ + __IO uint32_t APB4RSTCR2; /*!< RCC APB4 reset clear register 2 Address offset: 0x1238 */ + __IO uint32_t APB5RSTCR; /*!< RCC APB5 reset clear register Address offset: 0x123C */ + __IO uint32_t DIVENCR; /*!< RCC divider enable clear register Address offset: 0x1240 */ + __IO uint32_t BUSENCR; /*!< RCC bus enable clear register Address offset: 0x1244 */ + __IO uint32_t MISCENCR; /*!< RCC miscellaneous enable clear register Address offset: 0x1248 */ + __IO uint32_t MEMENCR; /*!< RCC memory enable clear register Address offset: 0x124C */ + __IO uint32_t AHB1ENCR; /*!< RCC AHB1 enable clear register Address offset: 0x1250 */ + __IO uint32_t AHB2ENCR; /*!< RCC AHB2 enable clear register Address offset: 0x1254 */ + __IO uint32_t AHB3ENCR; /*!< RCC AHB3 enable clear register Address offset: 0x1258 */ + __IO uint32_t AHB4ENCR; /*!< RCC AHB4 enable clear register Address offset: 0x125C */ + __IO uint32_t AHB5ENCR; /*!< RCC AHB5 enable clear register Address offset: 0x1260 */ + __IO uint32_t APB1ENCR1; /*!< RCC APB1 enable clear register 1 Address offset: 0x1264 */ + __IO uint32_t APB1ENCR2; /*!< RCC APB1 enable clear register 2 Address offset: 0x1268 */ + __IO uint32_t APB2ENCR; /*!< RCC APB2 enable clear register Address offset: 0x126C */ + __IO uint32_t APB3ENCR; /*!< RCC APB3 enable clear register Address offset: 0x1270 */ + __IO uint32_t APB4ENCR1; /*!< RCC APB4 enable clear register 1 Address offset: 0x1274 */ + __IO uint32_t APB4ENCR2; /*!< RCC APB4 enable clear register 2 Address offset: 0x1278 */ + __IO uint32_t APB5ENCR; /*!< RCC APB5 enable clear register Address offset: 0x127C */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x1280 */ + __IO uint32_t BUSLPENCR; /*!< RCC bus sleep enable clear register Address offset: 0x1284 */ + __IO uint32_t MISCLPENCR; /*!< RCC miscellaneous sleep enable clear register Address offset: 0x1288 */ + __IO uint32_t MEMLPENCR; /*!< RCC memory sleep enable clear register Address offset: 0x128C */ + __IO uint32_t AHB1LPENCR; /*!< RCC AHB1 sleep enable clear register Address offset: 0x1290 */ + __IO uint32_t AHB2LPENCR; /*!< RCC AHB2 sleep enable clear register Address offset: 0x1294 */ + __IO uint32_t AHB3LPENCR; /*!< RCC AHB3 sleep enable clear register Address offset: 0x1298 */ + __IO uint32_t AHB4LPENCR; /*!< RCC AHB4 sleep enable clear register Address offset: 0x129C */ + __IO uint32_t AHB5LPENCR; /*!< RCC AHB5 sleep enable clear register Address offset: 0x12A0 */ + __IO uint32_t APB1LPENCR1; /*!< RCC APB1 sleep enable clear register 1 Address offset: 0x12A4 */ + __IO uint32_t APB1LPENCR2; /*!< RCC APB1 sleep enable clear register 2 Address offset: 0x12A8 */ + __IO uint32_t APB2LPENCR; /*!< RCC APB2 sleep enable clear register Address offset: 0x12AC */ + __IO uint32_t APB3LPENCR; /*!< RCC APB3 sleep enable clear register Address offset: 0x12B0 */ + __IO uint32_t APB4LPENCR1; /*!< RCC APB4 sleep enable clear register 1 Address offset: 0x12B4 */ + __IO uint32_t APB4LPENCR2; /*!< RCC APB4 sleep enable clear register 2 Address offset: 0x12B8 */ + __IO uint32_t APB5LPENCR; /*!< RCC APB5 sleep enable clear register Address offset: 0x12BC */ + uint32_t RESERVED36[305]; /*!< Reserved Address offset: 0x12C0-0x1780 */ + __IO uint32_t PRIVCFGCR0; /*!< RCC oscillator privilege configuration clear register 0 Address offset: 0x1784 */ + uint32_t RESERVED37; /*!< Reserved Address offset: 0x1788 */ + __IO uint32_t PUBCFGCR0; /*!< RCC oscillator public configuration clear register 0 Address offset: 0x178C */ + uint32_t RESERVED38; /*!< Reserved Address offset: 0x1790 */ + __IO uint32_t PRIVCFGCR1; /*!< RCC PLL privilege configuration clear register 1 Address offset: 0x1794 */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x1798 */ + __IO uint32_t PUBCFGCR1; /*!< RCC PLL public configuration clear register 1 Address offset: 0x179C */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x17A0 */ + __IO uint32_t PRIVCFGCR2; /*!< RCC divider privilege configuration clear register 2 Address offset: 0x17A4 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x17A8 */ + __IO uint32_t PUBCFGCR2; /*!< RCC divider public configuration clear register 2 Address offset: 0x17AC */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x17B0 */ + __IO uint32_t PRIVCFGCR3; /*!< RCC system privilege configuration clear register 3 Address offset: 0x17B4 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x17B8 */ + __IO uint32_t PUBCFGCR3; /*!< RCC system public configuration clear register 3 Address offset: 0x17BC */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x17C0 */ + __IO uint32_t PRIVCFGCR4; /*!< RCC privilege configuration clear register 4 Address offset: 0x17C4 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x17C8 */ + __IO uint32_t PUBCFGCR4; /*!< RCC public configuration clear register 4 Address offset: 0x17CC */ + __IO uint32_t PUBCFGCR5; /*!< RCC public configuration clear register 5 Address offset: 0x17D0 */ +} RCC_TypeDef; + +/* + * @brief RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1) + */ +typedef struct +{ + __IO uint32_t RISC_CR; /*!< RIFSC RISC slave configuration register x Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved Address offset: 0x004-0x00C */ + __IO uint32_t RISC_SECCFGRx[6]; /*!< RIFSC RISC slave security configuration register x Address offset: 0x010-0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t RISC_PRIVCFGRx[6]; /*!< RIFSC RISFC slave privileged register x Address offset: 0x030-0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x048-0x04C */ + __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */ + uint32_t RESERVED3[742]; /*!< Reserved Address offset: 0x068-0xBFC */ + __IO uint32_t RIMC_CR; /*!< RIFSC RIMC master configuration register Address offset: 0xC00 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0xC04-0xC0C */ + __IO uint32_t RIMC_ATTRx[13]; /*!< RIFSC RIMC master attribute register x Address offset: 0xC10-0xC40 */ + uint32_t RESERVED5[219]; /*!< Reserved Address offset: 0xC40-0xFAC */ + __IO uint32_t PPSRx[6]; /*!< RIFSC peripheral protection status register x Address offset: 0xFB0-0xFC4 */ + uint32_t RESERVED6[8]; /*!< Reserved Address offset: 0xFC8-0xFE4 */ +} RIFSC_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) + */ +typedef struct +{ + __IO uint32_t CFGR; /*!< RISAF Region X configuration register */ + __IO uint32_t STARTR; /*!< RISAF Region X start address register */ + __IO uint32_t ENDR; /*!< RISAF Region X end address register */ + __IO uint32_t CIDCFGR; /*!< RISAF Region X CID configuration register */ + __IO uint32_t ACFGR; /*!< RISAF Region X subregion A configuration register */ + __IO uint32_t ASTARTR; /*!< RISAF Region X subregion A start address register */ + __IO uint32_t AENDR; /*!< RISAF Region X subregion A end address register */ + __IO uint32_t ANESTR; /*!< RISAF Region X subregion A nested mode register */ + __IO uint32_t BCFGR; /*!< RISAF Region X subregion B configuration register */ + __IO uint32_t BSTARTR; /*!< RISAF Region X subregion B start address register */ + __IO uint32_t BENDR; /*!< RISAF Region X subregion B end address register */ + __IO uint32_t BNESTR; /*!< RISAF Region X subregion B nested mode register */ + uint32_t RESERVED0[4]; /*!< Reserved */ +} RISAF_Region_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t IAESR; /*!< RISAF Illegal access error status register */ + __IO uint32_t IADDR; /*!< RISAF Illegal address register, */ +} RISAF_Illegal_TypeDef; + +/** + * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14) + */ +typedef struct +{ + __IO uint32_t CR; /*!< RISAF Configuration register, Address offset: 0x000 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< RISAF Illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< RISAF Illegal access clear register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, 0x010-0x01C */ + RISAF_Illegal_TypeDef IAR[1]; /*!< RISAF Illegal access error status and address register, 0x020-0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, 0x028-0x03C */ + RISAF_Region_TypeDef REG[15]; /*!< RISAF Region X configuration register, 0x040-0x3FC */ +} RISAF_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 7U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ +__IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SAES Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< SAES control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< SAES status register, Address offset: 0x004 */ + __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x008 */ + __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x00C */ + __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x010 */ + __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x014 */ + __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x018 */ + __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x01C */ + __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x020 */ + __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x024 */ + __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x028 */ + __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x02C */ + __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x030 */ + __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x034 */ + __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x038 */ + __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x03C */ + uint32_t RESERVED1[48]; /*!< Reserved, Address offset: 0x040 -- 0x0FC */ + __IO uint32_t DPACFGR; /*!< SAES DPA configuration register, Address offset: 0x100 */ + uint32_t RESERVED2[127]; /*!< Reserved, Address offset: 0x104 -- 0x2FC */ + __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ +} SAES_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + __IO uint32_t FIFOTHR; /*!< SDMMC data FIFO threshold register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x5C - 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< Core AHB Configuration Register, Address offset: 008h */ +} USB_PHY_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + __IO uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + __IO uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + __IO uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + __IO uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + __IO uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +typedef struct +{ + __IO uint32_t USBPHYC_CR; /*!< USB HS PHY Control Register, Address offset: 000h */ + __IO uint32_t USBPHYC_TRIM1CR; /*!< USB HS PHY Trimming_1 Register, Address offset: 004h */ + __IO uint32_t USBPHYC_TRIM2CR; /*!< USB HS PHY Trimming_2 Register, Address offset: 008h */ +} USB_HS_PHYC_GlobalTypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t BOOTCR; /*!< SYSCFG boot pin control register, Address offset: 0x00 */ + __IO uint32_t CM55CR; /*!< SYSCFG Cortex-M55 control register, Address offset: 0x04 */ + __IO uint32_t CM55TCMCR; /*!< SYSCFG Cortex-M55 TCM control register, Address offset: 0x08 */ + __IO uint32_t CM55RWMCR; /*!< SYSCFG Cortex-M55 memory RW margin register, Address offset: 0x0C */ + __IO uint32_t INITSVTORCR; /*!< SYSCFG Cortex-M55 SVTOR control register, Address offset: 0x10 */ + __IO uint32_t INITNSVTORCR; /*!< Cortex-M55 NSVTOR control register, Address offset: 0x14 */ + __IO uint32_t CM55RSTCR; /*!< SYSCFG Cortex-M55 reset type control register, Address offset: 0x18 */ + __IO uint32_t CM55PAHBWPR; /*!< SYSCFG Cortex-M55 P-AHB write posting control register, Address offset: 0x1C */ + __IO uint32_t VENCRAMCR; /*!< SYSCFG VENCRAM control register, Address offset: 0x20 */ + __IO uint32_t POTTAMPRSTCR; /*!< SYSCFG potential tamper reset register, Address offset: 0x24 */ + __IO uint32_t NPUNICQOSCR; /*!< SYSCFG NPUNIC QoS control register, Address offset: 0x28 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2C-0x30 */ + __IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */ + __IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */ + __IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x44 */ + __IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x48 */ + __IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x4C */ + __IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x50 */ + __IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x54 */ + __IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x58 */ + __IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x5C */ + __IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x60 */ + __IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */ + __IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */ + __IO uint32_t SEC_AIDCR; /*!< SYSCFG DMA CID secure control register, Address offset: 0x70 */ + __IO uint32_t FMC_RETIMECR; /*!< SYSCFG FMC retiming logic control register, Address offset: 0x74 */ + __IO uint32_t NPU_ICNCR; /*!< SYSCFG NPU RAM interleaving control register, Address offset: 0x78 */ + uint32_t RESERVED3[33]; /*!< Reserved, Address offset: 0x7C-0xFC */ + __IO uint32_t BOOTSR; /*!< SYSCFG boot pin status register, Address offset: 0x100 */ + __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register, Address offset: 0x104 */ + uint32_t RESERVED4[446]; /*!< Reserved, Address offset: 0x108-0x3FC */ + __IO uint32_t SECPRIV_AIDCR; /*!< SYSCFG DMA CID non-secure control register, Address offset: 0x800 */ + uint32_t RESERVED5[507]; /*!< Reserved, Address offset: 0x804-0xFEC */ + __IO uint32_t DEVICEID; /*!< SYSCFG Device ID, Address offset: 0xFF0 */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x43 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED1[221]; /*!< Reserved, 0x6C-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Extended-SPI Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** @} */ /* End of group STM32N6xx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal RAMs sizes */ +#define SRAM1_AXI_SIZE 0x100000UL /*!< SRAM1_AXI = 1024 Kbytes */ +#define SRAM2_AXI_SIZE 0x100000UL /*!< SRAM2_AXI = 1024 Kbytes */ +#define FLEXRAM_SIZE 0x64000UL /*!< FLEXRAM <= 400 Kbytes */ +#define SRAM3_AXI_SIZE 0x70000UL /*!< SRAM3_AXI = 448 Kbytes */ +#define SRAM4_AXI_SIZE 0x70000UL /*!< SRAM4_AXI = 448 Kbytes */ +#define SRAM5_AXI_SIZE 0x70000UL /*!< SRAM5_AXI = 448 Kbytes */ +#define SRAM6_AXI_SIZE 0x70000UL /*!< SRAM6_AXI = 448 Kbytes */ +#define SRAM1_AHB_SIZE 0x4000UL /*!< SRAM1_AHB = 16 Kbytes */ +#define SRAM2_AHB_SIZE 0x4000UL /*!< SRAM2_AHB = 16 Kbytes */ +#define VENC_RAM_SIZE 0x20000UL /*!< VENC RAM = 128 Kbytes */ +#define CACHEAXI_RAM_SIZE 0x40000UL /*!< CACHEAXI RAM = 256 Kbytes */ +#define BKPSRAM_SIZE 0x2000UL /*!< BKPSRAM = 8 Kbytes */ + + +#define FMC_BASE 0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */ +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK5 0xC0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK5_1 FMC_BANK5 +#define FMC_BANK5_2 (FMC_BANK5 + 0x04000000UL) +#define FMC_BANK5_3 (FMC_BANK5 + 0x08000000UL) +#define FMC_BANK5_4 (FMC_BANK5 + 0x0C000000UL) +#define FMC_BANK6 0xD0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */ +#define FMC_BANK6_1 FMC_BANK6 +#define FMC_BANK6_2 (FMC_BANK6 + 0x04000000UL) +#define FMC_BANK6_3 (FMC_BANK6 + 0x08000000UL) +#define FMC_BANK6_4 (FMC_BANK6 + 0x0C000000UL) +#define XSPI1_BASE 0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI */ +#define XSPI2_BASE 0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI */ +#define XSPI3_BASE 0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI */ + +/**************************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */ +/* */ +/**************************************************************************/ + +#define ITCM_BASE_NS 0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_NS 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_NS 0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_NS 0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_NS 0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_NS 0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_NS 0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_NS 0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_NS 0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_NS SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define CACHEAXI_RAM_BASE_NS 0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ +#define VENC_RAM_BASE_NS 0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS 0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS 0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS 0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS 0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_NS 0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_NS 0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_NS 0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_NS SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_NS 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02000000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define APB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define APB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08000000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x2400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define TIM10_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define TIM11_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define SPDIFRX_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I3C2_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL) +#define FDCAN3_BASE_NS (APB1PERIPH_BASE_NS + 0xE800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define ADC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL) +#define ADC2_BASE_NS (AHB1PERIPH_BASE_NS + 0x2100UL) +#define ADC12_COMMON_BASE_NS (AHB1PERIPH_BASE_NS + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x0400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x1000UL) +#define USART6_BASE_NS (APB2PERIPH_BASE_NS + 0x1400UL) +#define UART9_BASE_NS (APB2PERIPH_BASE_NS + 0x1800UL) +#define USART10_BASE_NS (APB2PERIPH_BASE_NS + 0x1C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define TIM18_BASE_NS (APB2PERIPH_BASE_NS + 0x3C00UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define TIM9_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI5_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5C00UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_NS (AHB2PERIPH_BASE_NS + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_NS (RAMCFG_BASE_NS + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_NS (RAMCFG_BASE_NS + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_NS (RAMCFG_BASE_NS + 0x0500UL) +#define MDF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x5000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x0080UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x0100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x0180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x0200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x0280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x0300UL) +#define ADF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x6000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_NS (APB3PERIPH_BASE_NS + 0x0000UL) +#define DBGMCU_BASE_NS (APB3PERIPH_BASE_NS + 0x1000UL) +#define DFT_APB_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) +#define HASH_BASE_NS (AHB3PERIPH_BASE_NS + 0x0400UL) +#define HASH_DIGEST_BASE_NS (AHB3PERIPH_BASE_NS + 0x0710UL) +#define CRYP_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define SAES_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define PKA_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define RIFSC_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define RISAF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x6000UL) +#define RISAF2_BASE_NS (AHB3PERIPH_BASE_NS + 0x7000UL) +#define RISAF3_BASE_NS (AHB3PERIPH_BASE_NS + 0x8000UL) +#define RISAF4_BASE_NS (AHB3PERIPH_BASE_NS + 0x9000UL) +#define RISAF5_BASE_NS (AHB3PERIPH_BASE_NS + 0xA000UL) +#define RISAF6_BASE_NS (AHB3PERIPH_BASE_NS + 0xB000UL) +#define RISAF7_BASE_NS (AHB3PERIPH_BASE_NS + 0xC000UL) +#define RISAF8_BASE_NS (AHB3PERIPH_BASE_NS + 0xD000UL) +#define RISAF9_BASE_NS (AHB3PERIPH_BASE_NS + 0xE000UL) +#define RISAF11_BASE_NS (AHB3PERIPH_BASE_NS + 0x010000UL) +#define RISAF12_BASE_NS (AHB3PERIPH_BASE_NS + 0x011000UL) +#define RISAF13_BASE_NS (AHB3PERIPH_BASE_NS + 0x012000UL) +#define RISAF14_BASE_NS (AHB3PERIPH_BASE_NS + 0x013000UL) +#define RISAF15_BASE_NS (AHB3PERIPH_BASE_NS + 0x014000UL) +#define RISAF21_BASE_NS (AHB3PERIPH_BASE_NS + 0x015000UL) +#define RISAF22_BASE_NS (AHB3PERIPH_BASE_NS + 0x016000UL) +#define RISAF23_BASE_NS (AHB3PERIPH_BASE_NS + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_NS (APB4PERIPH_BASE_NS + 0x0800UL) +#define LPUART1_BASE_NS (APB4PERIPH_BASE_NS + 0x0C00UL) +#define SPI6_BASE_NS (APB4PERIPH_BASE_NS + 0x1400UL) +#define I2C4_BASE_NS (APB4PERIPH_BASE_NS + 0x1C00UL) +#define LPTIM2_BASE_NS (APB4PERIPH_BASE_NS + 0x2400UL) +#define LPTIM3_BASE_NS (APB4PERIPH_BASE_NS + 0x2800UL) +#define LPTIM4_BASE_NS (APB4PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM5_BASE_NS (APB4PERIPH_BASE_NS + 0x3000UL) +#define VREFBUF_BASE_NS (APB4PERIPH_BASE_NS + 0x3C00UL) +#define RTC_BASE_NS (APB4PERIPH_BASE_NS + 0x4000UL) +#define TAMP_BASE_NS (APB4PERIPH_BASE_NS + 0x4400UL) +#define IWDG_BASE_NS (APB4PERIPH_BASE_NS + 0x4800UL) +#define SERC_BASE_NS (APB4PERIPH_BASE_NS + 0x7C00UL) +#define SYSCFG_BASE_NS (APB4PERIPH_BASE_NS + 0x8000UL) +#define BSEC_BASE_NS (APB4PERIPH_BASE_NS + 0x9000UL) +#define DTS_BASE_NS (APB4PERIPH_BASE_NS + 0xA000UL) +#define DTS_Sensor0_BASE_NS (DTS_BASE_NS + 0x0C0UL) +#define DTS_Sensor1_BASE_NS (DTS_BASE_NS + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_NS (AHB4PERIPH_BASE_NS + 0x0000UL) +#define GPIOB_BASE_NS (AHB4PERIPH_BASE_NS + 0x0400UL) +#define GPIOC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define GPIOD_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define GPIOE_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define GPIOF_BASE_NS (AHB4PERIPH_BASE_NS + 0x1400UL) +#define GPIOG_BASE_NS (AHB4PERIPH_BASE_NS + 0x1800UL) +#define GPIOH_BASE_NS (AHB4PERIPH_BASE_NS + 0x1C00UL) +#define GPION_BASE_NS (AHB4PERIPH_BASE_NS + 0x3400UL) +#define GPIOO_BASE_NS (AHB4PERIPH_BASE_NS + 0x3800UL) +#define GPIOP_BASE_NS (AHB4PERIPH_BASE_NS + 0x3C00UL) +#define GPIOQ_BASE_NS (AHB4PERIPH_BASE_NS + 0x4000UL) +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x4800UL) +#define CRC_BASE_NS (AHB4PERIPH_BASE_NS + 0x4C00UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_NS (APB5PERIPH_BASE_NS + 0x1000UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0100UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0200UL) +#define DCMIPP_BASE_NS (APB5PERIPH_BASE_NS + 0x2000UL) +#define GFXTIM_BASE_NS (APB5PERIPH_BASE_NS + 0x4000UL) +#define VENC_BASE_NS (APB5PERIPH_BASE_NS + 0x5000UL) +#define CSI_BASE_NS (APB5PERIPH_BASE_NS + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_NS (AHB5PERIPH_BASE_NS + 0x0000UL) +#define HPDMA1_Channel0_BASE_NS (HPDMA1_BASE_NS + 0x0050UL) +#define HPDMA1_Channel1_BASE_NS (HPDMA1_BASE_NS + 0x00D0UL) +#define HPDMA1_Channel2_BASE_NS (HPDMA1_BASE_NS + 0x0150UL) +#define HPDMA1_Channel3_BASE_NS (HPDMA1_BASE_NS + 0x01D0UL) +#define HPDMA1_Channel4_BASE_NS (HPDMA1_BASE_NS + 0x0250UL) +#define HPDMA1_Channel5_BASE_NS (HPDMA1_BASE_NS + 0x02D0UL) +#define HPDMA1_Channel6_BASE_NS (HPDMA1_BASE_NS + 0x0350UL) +#define HPDMA1_Channel7_BASE_NS (HPDMA1_BASE_NS + 0x03D0UL) +#define HPDMA1_Channel8_BASE_NS (HPDMA1_BASE_NS + 0x0450UL) +#define HPDMA1_Channel9_BASE_NS (HPDMA1_BASE_NS + 0x04D0UL) +#define HPDMA1_Channel10_BASE_NS (HPDMA1_BASE_NS + 0x0550UL) +#define HPDMA1_Channel11_BASE_NS (HPDMA1_BASE_NS + 0x05D0UL) +#define HPDMA1_Channel12_BASE_NS (HPDMA1_BASE_NS + 0x0650UL) +#define HPDMA1_Channel13_BASE_NS (HPDMA1_BASE_NS + 0x06D0UL) +#define HPDMA1_Channel14_BASE_NS (HPDMA1_BASE_NS + 0x0750UL) +#define HPDMA1_Channel15_BASE_NS (HPDMA1_BASE_NS + 0x07D0UL) +#define DMA2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x1000UL) +#define JPEG_BASE_NS (AHB5PERIPH_BASE_NS + 0x3000UL) +#define FMC_R_BASE_NS (AHB5PERIPH_BASE_NS + 0x4000UL) +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) +#define FMC_Common_R_BASE_NS (FMC_R_BASE_NS + 0x0020UL) +#define XSPI1_BASE_NS (AHB5PERIPH_BASE_NS + 0x5000UL) +#define PSSI_BASE_NS (AHB5PERIPH_BASE_NS + 0x6400UL) +#define SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6800UL) +#define DLYB_SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6C00UL) +#define SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x7000UL) +#define DLYB_SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x8000UL) +#define DCMI_BASE_NS (AHB5PERIPH_BASE_NS + 0x8400UL) +#define XSPI2_BASE_NS (AHB5PERIPH_BASE_NS + 0xA000UL) +#define XSPIM_BASE_NS (AHB5PERIPH_BASE_NS + 0xB400UL) +#define MCE1_BASE_NS (AHB5PERIPH_BASE_NS + 0xB800UL) +#define MCE1_REGION1_BASE_NS (MCE1_BASE_NS + 0x040UL) +#define MCE1_REGION2_BASE_NS (MCE1_BASE_NS + 0x050UL) +#define MCE1_REGION3_BASE_NS (MCE1_BASE_NS + 0x060UL) +#define MCE1_REGION4_BASE_NS (MCE1_BASE_NS + 0x070UL) +#define MCE1_CONTEXT1_BASE_NS (MCE1_BASE_NS + 0x240UL) +#define MCE1_CONTEXT2_BASE_NS (MCE1_BASE_NS + 0x270UL) +#define MCE2_BASE_NS (AHB5PERIPH_BASE_NS + 0xBC00UL) +#define MCE2_REGION1_BASE_NS (MCE2_BASE_NS + 0x040UL) +#define MCE2_REGION2_BASE_NS (MCE2_BASE_NS + 0x050UL) +#define MCE2_REGION3_BASE_NS (MCE2_BASE_NS + 0x060UL) +#define MCE2_REGION4_BASE_NS (MCE2_BASE_NS + 0x070UL) +#define MCE2_CONTEXT1_BASE_NS (MCE2_BASE_NS + 0x240UL) +#define MCE2_CONTEXT2_BASE_NS (MCE2_BASE_NS + 0x270UL) +#define MCE3_BASE_NS (AHB5PERIPH_BASE_NS + 0xC000UL) +#define MCE3_REGION1_BASE_NS (MCE3_BASE_NS + 0x040UL) +#define MCE3_REGION2_BASE_NS (MCE3_BASE_NS + 0x050UL) +#define MCE3_REGION3_BASE_NS (MCE3_BASE_NS + 0x060UL) +#define MCE3_REGION4_BASE_NS (MCE3_BASE_NS + 0x070UL) +#define MCE3_CONTEXT1_BASE_NS (MCE3_BASE_NS + 0x240UL) +#define MCE3_CONTEXT2_BASE_NS (MCE3_BASE_NS + 0x270UL) +#define MCE4_BASE_NS (AHB5PERIPH_BASE_NS + 0xE000UL) +#define MCE4_REGION1_BASE_NS (MCE4_BASE_NS + 0x040UL) +#define MCE4_REGION2_BASE_NS (MCE4_BASE_NS + 0x050UL) +#define MCE4_REGION3_BASE_NS (MCE4_BASE_NS + 0x060UL) +#define MCE4_REGION4_BASE_NS (MCE4_BASE_NS + 0x070UL) +#define MCE4_CONTEXT1_BASE_NS (MCE4_BASE_NS + 0x240UL) +#define MCE4_CONTEXT2_BASE_NS (MCE4_BASE_NS + 0x270UL) +#define XSPI3_BASE_NS (AHB5PERIPH_BASE_NS + 0xD000UL) +#define GFXMMU_BASE_NS (AHB5PERIPH_BASE_NS + 0x010000UL) +#define GPU2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x014000UL) +#define GPUCACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ICACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL) +#define ETH1_BASE_NS (AHB5PERIPH_BASE_NS + 0x016000UL) +#define ETH1_MAC_BASE_NS (ETH1_BASE_NS) +#define USB1_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x0A0000UL) +#define USB1_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x020000UL) +#define USB2_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x060000UL) +#define CACHEAXI_BASE_NS (AHB5PERIPH_BASE_NS + 0x0BFC00UL) +#define NPU_BASE_NS (AHB5PERIPH_BASE_NS + 0x0C0000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_NS (0x46009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_NS (BOOTROM_BASE_NS + 0x001004UL) + + +#if defined (CPU_IN_SECURE_STATE) +/*********************************************************************/ +/* */ +/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */ +/* */ +/*********************************************************************/ +#define ITCM_BASE_S 0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */ +#define BOOTROM_BASE_S 0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */ +#define DTCM_BASE_S 0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */ +#define SRAM1_AXI_BASE_S 0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */ +#define SRAM2_AXI_BASE_S 0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */ +#define SRAM3_AXI_BASE_S 0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */ +#define SRAM4_AXI_BASE_S 0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */ +#define SRAM5_AXI_BASE_S 0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */ +#define SRAM6_AXI_BASE_S 0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */ +#define SRAM_AXI_BASE_S SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */ +#define CACHEAXI_RAM_BASE_S 0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */ +#define VENC_RAM_BASE_S 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */ +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S 0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S 0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S 0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S 0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */ +#define STM500_CHANNELS_BASE_S 0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */ +#define SRAM1_AHB_BASE_S 0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */ +#define SRAM2_AHB_BASE_S 0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */ +#define SRAM_AHB_BASE_S SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */ +#define BKPSRAM_BASE_S 0x3C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */ +#define PERIPH_BASE_S 0x50000000UL /*!< Base address of : AHB/APB Peripherals */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02000000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define APB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define APB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08000000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x2400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define TIM10_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define TIM11_BASE_S (APB1PERIPH_BASE_S + 0x3400UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define SPDIFRX_BASE_S (APB1PERIPH_BASE_S + 0x4000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define I3C2_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL) +#define FDCAN3_BASE_S (APB1PERIPH_BASE_S + 0xE800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xFC00UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define ADC1_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL) +#define ADC2_BASE_S (AHB1PERIPH_BASE_S + 0x2100UL) +#define ADC12_COMMON_BASE_S (AHB1PERIPH_BASE_S + 0x2300UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x0000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x0400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x1000UL) +#define USART6_BASE_S (APB2PERIPH_BASE_S + 0x1400UL) +#define UART9_BASE_S (APB2PERIPH_BASE_S + 0x1800UL) +#define USART10_BASE_S (APB2PERIPH_BASE_S + 0x1C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define TIM18_BASE_S (APB2PERIPH_BASE_S + 0x3C00UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define TIM9_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI5_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5C00UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL) + +/*!< AHB2 peripherals */ +#define RAMCFG_BASE_S (AHB2PERIPH_BASE_S + 0x3000UL) +#define RAMCFG_SRAM1_AXI_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_AXI_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM3_AXI_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM4_AXI_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define RAMCFG_SRAM5_AXI_BASE_S (RAMCFG_BASE_S + 0x0200UL) +#define RAMCFG_SRAM6_AXI_BASE_S (RAMCFG_BASE_S + 0x0280UL) +#define RAMCFG_SRAM1_AHB_BASE_S (RAMCFG_BASE_S + 0x0300UL) +#define RAMCFG_SRAM2_AHB_BASE_S (RAMCFG_BASE_S + 0x0380UL) +#define RAMCFG_VENC_RAM_BASE_S (RAMCFG_BASE_S + 0x0400UL) +#define RAMCFG_BKPSRAM_BASE_S (RAMCFG_BASE_S + 0x0480UL) +#define RAMCFG_FLEXRAM_BASE_S (RAMCFG_BASE_S + 0x0500UL) +#define MDF1_BASE_S (AHB2PERIPH_BASE_S + 0x5000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x0080UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x0100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x0180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x0200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x0280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x0300UL) +#define ADF1_BASE_S (AHB2PERIPH_BASE_S + 0x6000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x0080UL) + +/*!< APB3 peripherals */ +#define DAP_ROM_BASE_S (APB3PERIPH_BASE_S + 0x0000UL) +#define DBGMCU_BASE_S (APB3PERIPH_BASE_S + 0x1000UL) +#define DFT_APB_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) +#define HASH_BASE_S (AHB3PERIPH_BASE_S + 0x0400UL) +#define HASH_DIGEST_BASE_S (AHB3PERIPH_BASE_S + 0x0710UL) +#define CRYP_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define SAES_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define PKA_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define RIFSC_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define IAC_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define RISAF1_BASE_S (AHB3PERIPH_BASE_S + 0x6000UL) +#define RISAF2_BASE_S (AHB3PERIPH_BASE_S + 0x7000UL) +#define RISAF3_BASE_S (AHB3PERIPH_BASE_S + 0x8000UL) +#define RISAF4_BASE_S (AHB3PERIPH_BASE_S + 0x9000UL) +#define RISAF5_BASE_S (AHB3PERIPH_BASE_S + 0xA000UL) +#define RISAF6_BASE_S (AHB3PERIPH_BASE_S + 0xB000UL) +#define RISAF7_BASE_S (AHB3PERIPH_BASE_S + 0xC000UL) +#define RISAF8_BASE_S (AHB3PERIPH_BASE_S + 0xD000UL) +#define RISAF9_BASE_S (AHB3PERIPH_BASE_S + 0xE000UL) +#define RISAF11_BASE_S (AHB3PERIPH_BASE_S + 0x010000UL) +#define RISAF12_BASE_S (AHB3PERIPH_BASE_S + 0x011000UL) +#define RISAF13_BASE_S (AHB3PERIPH_BASE_S + 0x012000UL) +#define RISAF14_BASE_S (AHB3PERIPH_BASE_S + 0x013000UL) +#define RISAF15_BASE_S (AHB3PERIPH_BASE_S + 0x014000UL) +#define RISAF21_BASE_S (AHB3PERIPH_BASE_S + 0x015000UL) +#define RISAF22_BASE_S (AHB3PERIPH_BASE_S + 0x016000UL) +#define RISAF23_BASE_S (AHB3PERIPH_BASE_S + 0x017000UL) + +/*!< APB4 peripherals */ +#define HDP_BASE_S (APB4PERIPH_BASE_S + 0x0800UL) +#define LPUART1_BASE_S (APB4PERIPH_BASE_S + 0x0C00UL) +#define SPI6_BASE_S (APB4PERIPH_BASE_S + 0x1400UL) +#define I2C4_BASE_S (APB4PERIPH_BASE_S + 0x1C00UL) +#define LPTIM2_BASE_S (APB4PERIPH_BASE_S + 0x2400UL) +#define LPTIM3_BASE_S (APB4PERIPH_BASE_S + 0x2800UL) +#define LPTIM4_BASE_S (APB4PERIPH_BASE_S + 0x2C00UL) +#define LPTIM5_BASE_S (APB4PERIPH_BASE_S + 0x3000UL) +#define VREFBUF_BASE_S (APB4PERIPH_BASE_S + 0x3C00UL) +#define RTC_BASE_S (APB4PERIPH_BASE_S + 0x4000UL) +#define TAMP_BASE_S (APB4PERIPH_BASE_S + 0x4400UL) +#define IWDG_BASE_S (APB4PERIPH_BASE_S + 0x4800UL) + +#define SERC_BASE_S (APB4PERIPH_BASE_S + 0x7C00UL) +#define SYSCFG_BASE_S (APB4PERIPH_BASE_S + 0x8000UL) +#define BSEC_BASE_S (APB4PERIPH_BASE_S + 0x9000UL) +#define DTS_BASE_S (APB4PERIPH_BASE_S + 0xA000UL) +#define DTS_Sensor0_BASE_S (DTS_BASE_S + 0x0C0UL) +#define DTS_Sensor1_BASE_S (DTS_BASE_S + 0x100UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE_S (AHB4PERIPH_BASE_S + 0x0000UL) +#define GPIOB_BASE_S (AHB4PERIPH_BASE_S + 0x0400UL) +#define GPIOC_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define GPIOD_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define GPIOE_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define GPIOF_BASE_S (AHB4PERIPH_BASE_S + 0x1400UL) +#define GPIOG_BASE_S (AHB4PERIPH_BASE_S + 0x1800UL) +#define GPIOH_BASE_S (AHB4PERIPH_BASE_S + 0x1C00UL) +#define GPION_BASE_S (AHB4PERIPH_BASE_S + 0x3400UL) +#define GPIOO_BASE_S (AHB4PERIPH_BASE_S + 0x3800UL) +#define GPIOP_BASE_S (AHB4PERIPH_BASE_S + 0x3C00UL) +#define GPIOQ_BASE_S (AHB4PERIPH_BASE_S + 0x4000UL) +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x4800UL) +#define CRC_BASE_S (AHB4PERIPH_BASE_S + 0x4C00UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE_S (APB5PERIPH_BASE_S + 0x1000UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0100UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0200UL) +#define DCMIPP_BASE_S (APB5PERIPH_BASE_S + 0x2000UL) +#define GFXTIM_BASE_S (APB5PERIPH_BASE_S + 0x4000UL) +#define VENC_BASE_S (APB5PERIPH_BASE_S + 0x5000UL) +#define CSI_BASE_S (APB5PERIPH_BASE_S + 0x6000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE_S (AHB5PERIPH_BASE_S + 0x0000UL) +#define HPDMA1_Channel0_BASE_S (HPDMA1_BASE_S + 0x0050UL) +#define HPDMA1_Channel1_BASE_S (HPDMA1_BASE_S + 0x00D0UL) +#define HPDMA1_Channel2_BASE_S (HPDMA1_BASE_S + 0x0150UL) +#define HPDMA1_Channel3_BASE_S (HPDMA1_BASE_S + 0x01D0UL) +#define HPDMA1_Channel4_BASE_S (HPDMA1_BASE_S + 0x0250UL) +#define HPDMA1_Channel5_BASE_S (HPDMA1_BASE_S + 0x02D0UL) +#define HPDMA1_Channel6_BASE_S (HPDMA1_BASE_S + 0x0350UL) +#define HPDMA1_Channel7_BASE_S (HPDMA1_BASE_S + 0x03D0UL) +#define HPDMA1_Channel8_BASE_S (HPDMA1_BASE_S + 0x0450UL) +#define HPDMA1_Channel9_BASE_S (HPDMA1_BASE_S + 0x04D0UL) +#define HPDMA1_Channel10_BASE_S (HPDMA1_BASE_S + 0x0550UL) +#define HPDMA1_Channel11_BASE_S (HPDMA1_BASE_S + 0x05D0UL) +#define HPDMA1_Channel12_BASE_S (HPDMA1_BASE_S + 0x0650UL) +#define HPDMA1_Channel13_BASE_S (HPDMA1_BASE_S + 0x06D0UL) +#define HPDMA1_Channel14_BASE_S (HPDMA1_BASE_S + 0x0750UL) +#define HPDMA1_Channel15_BASE_S (HPDMA1_BASE_S + 0x07D0UL) +#define DMA2D_BASE_S (AHB5PERIPH_BASE_S + 0x1000UL) +#define JPEG_BASE_S (AHB5PERIPH_BASE_S + 0x3000UL) +#define FMC_R_BASE_S (AHB5PERIPH_BASE_S + 0x4000UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) +#define FMC_Common_R_BASE_S (FMC_R_BASE_S + 0x0020UL) +#define XSPI1_BASE_S (AHB5PERIPH_BASE_S + 0x5000UL) +#define PSSI_BASE_S (AHB5PERIPH_BASE_S + 0x6400UL) +#define SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6800UL) +#define DLYB_SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6C00UL) +#define SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x7000UL) +#define DLYB_SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x8000UL) +#define DCMI_BASE_S (AHB5PERIPH_BASE_S + 0x8400UL) +#define XSPI2_BASE_S (AHB5PERIPH_BASE_S + 0xA000UL) +#define XSPIM_BASE_S (AHB5PERIPH_BASE_S + 0xB400UL) +#define MCE1_BASE_S (AHB5PERIPH_BASE_S + 0xB800UL) +#define MCE1_REGION1_BASE_S (MCE1_BASE_S + 0x040UL) +#define MCE1_REGION2_BASE_S (MCE1_BASE_S + 0x050UL) +#define MCE1_REGION3_BASE_S (MCE1_BASE_S + 0x060UL) +#define MCE1_REGION4_BASE_S (MCE1_BASE_S + 0x070UL) +#define MCE1_CONTEXT1_BASE_S (MCE1_BASE_S + 0x240UL) +#define MCE1_CONTEXT2_BASE_S (MCE1_BASE_S + 0x270UL) +#define MCE2_BASE_S (AHB5PERIPH_BASE_S + 0xBC00UL) +#define MCE2_REGION1_BASE_S (MCE2_BASE_S + 0x040UL) +#define MCE2_REGION2_BASE_S (MCE2_BASE_S + 0x050UL) +#define MCE2_REGION3_BASE_S (MCE2_BASE_S + 0x060UL) +#define MCE2_REGION4_BASE_S (MCE2_BASE_S + 0x070UL) +#define MCE2_CONTEXT1_BASE_S (MCE2_BASE_S + 0x240UL) +#define MCE2_CONTEXT2_BASE_S (MCE2_BASE_S + 0x270UL) +#define MCE3_BASE_S (AHB5PERIPH_BASE_S + 0xC000UL) +#define MCE3_REGION1_BASE_S (MCE3_BASE_S + 0x040UL) +#define MCE3_REGION2_BASE_S (MCE3_BASE_S + 0x050UL) +#define MCE3_REGION3_BASE_S (MCE3_BASE_S + 0x060UL) +#define MCE3_REGION4_BASE_S (MCE3_BASE_S + 0x070UL) +#define MCE3_CONTEXT1_BASE_S (MCE3_BASE_S + 0x240UL) +#define MCE3_CONTEXT2_BASE_S (MCE3_BASE_S + 0x270UL) +#define MCE4_BASE_S (AHB5PERIPH_BASE_S + 0xE000UL) +#define MCE4_REGION1_BASE_S (MCE4_BASE_S + 0x040UL) +#define MCE4_REGION2_BASE_S (MCE4_BASE_S + 0x050UL) +#define MCE4_REGION3_BASE_S (MCE4_BASE_S + 0x060UL) +#define MCE4_REGION4_BASE_S (MCE4_BASE_S + 0x070UL) +#define MCE4_CONTEXT1_BASE_S (MCE4_BASE_S + 0x240UL) +#define MCE4_CONTEXT2_BASE_S (MCE4_BASE_S + 0x270UL) +#define XSPI3_BASE_S (AHB5PERIPH_BASE_S + 0xD000UL) +#define GFXMMU_BASE_S (AHB5PERIPH_BASE_S + 0x010000UL) +#define GPU2D_BASE_S (AHB5PERIPH_BASE_S + 0x014000UL) +#define GPUCACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ICACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL) +#define ETH1_BASE_S (AHB5PERIPH_BASE_S + 0x016000UL) +#define ETH1_MAC_BASE_S (ETH1_BASE_S) +#define USB1_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x01FC00UL) +#define USB2_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x0A0000UL) +#define USB1_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x020000UL) +#define USB2_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x060000UL) +#define CACHEAXI_BASE_S (AHB5PERIPH_BASE_S + 0x0BFC00UL) +#define NPU_BASE_S (AHB5PERIPH_BASE_S + 0x0C0000UL) + + +/*!< Unique device ID register base address */ +#define UID_BASE_S (0x56009014UL) + +/*!< Revision ID base address */ +#define REVID_BASE_S (BOOTROM_BASE_S + 0x001004UL) + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32N6xx_Peripheral_declaration + * @{ + */ +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS) +#define BSEC_NS ((BSEC_TypeDef *) BSEC_BASE_NS) +#define CACHEAXI_NS ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CRYP_NS ((CRYP_TypeDef *) CRYP_BASE_NS) +#define CSI_NS ((CSI_TypeDef *) CSI_BASE_NS) +#define DBGMCU_NS ((DBGMCU_TypeDef *) DBGMCU_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define DCMIPP_NS ((DCMIPP_TypeDef *) DCMIPP_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define DTS_NS ((DTS_TypeDef *) DTS_BASE_NS) +#define DTS_Sensor0_NS ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS) +#define DTS_Sensor1_NS ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS) +#define ETH1_NS ((ETH_TypeDef *) ETH1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS) +#define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS) +#define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) +#define FMC_Common_R_NS ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPION_NS ((GPIO_TypeDef *) GPION_BASE_NS) +#define GPIOO_NS ((GPIO_TypeDef *) GPIOO_BASE_NS) +#define GPIOP_NS ((GPIO_TypeDef *) GPIOP_BASE_NS) +#define GPIOQ_NS ((GPIO_TypeDef *) GPIOQ_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HPDMA1_NS ((DMA_TypeDef *) HPDMA1_BASE_NS) +#define HPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS) +#define HPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS) +#define HPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS) +#define HPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS) +#define HPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS) +#define HPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS) +#define HPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS) +#define HPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS) +#define HPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS) +#define HPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS) +#define HPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS) +#define HPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS) +#define HPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS) +#define HPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS) +#define HPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS) +#define HPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *)LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS) +#define MCE1_NS ((MCE_TypeDef *) MCE1_BASE_NS) +#define MCE1_REGION1_NS ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS) +#define MCE1_REGION2_NS ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS) +#define MCE1_REGION3_NS ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS) +#define MCE1_REGION4_NS ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS) +#define MCE1_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS) +#define MCE1_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS) +#define MCE2_NS ((MCE_TypeDef *) MCE2_BASE_NS) +#define MCE2_REGION1_NS ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS) +#define MCE2_REGION2_NS ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS) +#define MCE2_REGION3_NS ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS) +#define MCE2_REGION4_NS ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS) +#define MCE2_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS) +#define MCE2_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS) +#define MCE3_NS ((MCE_TypeDef *) MCE3_BASE_NS) +#define MCE3_REGION1_NS ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS) +#define MCE3_REGION2_NS ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS) +#define MCE3_REGION3_NS ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS) +#define MCE3_REGION4_NS ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS) +#define MCE3_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS) +#define MCE3_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS) +#define MCE4_NS ((MCE_TypeDef *) MCE4_BASE_NS) +#define MCE4_REGION1_NS ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS) +#define MCE4_REGION2_NS ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS) +#define MCE4_REGION3_NS ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS) +#define MCE4_REGION4_NS ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS) +#define MCE4_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS) +#define MCE4_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS) +#define MDIOS_NS ((MDIOS_TypeDef *) MDIOS_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_NS ((RAMCFG_TypeDef *) RAMCFG_BASE_NS) +#define RAMCFG_SRAM1_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS) +#define RAMCFG_SRAM2_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS) +#define RAMCFG_SRAM3_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS) +#define RAMCFG_SRAM4_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS) +#define RAMCFG_SRAM5_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS) +#define RAMCFG_SRAM6_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS) +#define RAMCFG_SRAM1_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS) +#define RAMCFG_SRAM2_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS) +#define RAMCFG_VENC_RAM_NS ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS) +#define RAMCFG_FLEXRAM_NS ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RIFSC_NS ((RIFSC_TypeDef *) RIFSC_BASE_NS) +#define RISAF1_NS ((RISAF_TypeDef *) RISAF1_BASE_NS) +#define RISAF2_NS ((RISAF_TypeDef *) RISAF2_BASE_NS) +#define RISAF3_NS ((RISAF_TypeDef *) RISAF3_BASE_NS) +#define RISAF4_NS ((RISAF_TypeDef *) RISAF4_BASE_NS) +#define RISAF5_NS ((RISAF_TypeDef *) RISAF5_BASE_NS) +#define RISAF6_NS ((RISAF_TypeDef *) RISAF6_BASE_NS) +#define RISAF7_NS ((RISAF_TypeDef *) RISAF7_BASE_NS) +#define RISAF8_NS ((RISAF_TypeDef *) RISAF8_BASE_NS) +#define RISAF9_NS ((RISAF_TypeDef *) RISAF9_BASE_NS) +#define RISAF11_NS ((RISAF_TypeDef *) RISAF11_BASE_NS) +#define RISAF12_NS ((RISAF_TypeDef *) RISAF12_BASE_NS) +#define RISAF13_NS ((RISAF_TypeDef *) RISAF13_BASE_NS) +#define RISAF14_NS ((RISAF_TypeDef *) RISAF14_BASE_NS) +#define RISAF15_NS ((RISAF_TypeDef *) RISAF15_BASE_NS) +#define RISAF21_NS ((RISAF_TypeDef *) RISAF21_BASE_NS) +#define RISAF22_NS ((RISAF_TypeDef *) RISAF22_BASE_NS) +#define RISAF23_NS ((RISAF_TypeDef *) RISAF23_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((SAES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define SPDIFRX_NS ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define TIM9_NS ((TIM_TypeDef *) TIM9_BASE_NS) +#define TIM10_NS ((TIM_TypeDef *) TIM10_BASE_NS) +#define TIM11_NS ((TIM_TypeDef *) TIM11_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *) TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *) TIM14_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TIM18_NS ((TIM_TypeDef *) TIM18_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define UART7_NS ((USART_TypeDef *) UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *) UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *) UART9_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *) USART10_BASE_NS) +#define USB1_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS) +#define USB2_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS) +#define USB1_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS) +#define USB2_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS) +#define VENC_NS ((VENC_TypeDef *) VENC_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define XSPI1_NS ((XSPI_TypeDef *) XSPI1_BASE_NS) +#define XSPI2_NS ((XSPI_TypeDef *) XSPI2_BASE_NS) +#define XSPI3_NS ((XSPI_TypeDef *) XSPI3_BASE_NS) +#define XSPIM_NS ((XSPIM_TypeDef *) XSPIM_BASE_NS) + +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S) +#define BSEC_S ((BSEC_TypeDef *) BSEC_BASE_S) +#define CACHEAXI_S ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CRYP_S ((CRYP_TypeDef *) CRYP_BASE_S) +#define CSI_S ((CSI_TypeDef *) CSI_BASE_S) +#define DBGMCU_S ((DBGMCU_TypeDef *) DBGMCU_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define DCMIPP_S ((DCMIPP_TypeDef *) DCMIPP_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define DTS_S ((DTS_TypeDef *) DTS_BASE_S) +#define DTS_Sensor0_S ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S) +#define DTS_Sensor1_S ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S) +#define ETH1_S ((ETH_TypeDef *) ETH1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S) +#define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S) +#define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) +#define FMC_Common_R_S ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPION_S ((GPIO_TypeDef *) GPION_BASE_S) +#define GPIOO_S ((GPIO_TypeDef *) GPIOO_BASE_S) +#define GPIOP_S ((GPIO_TypeDef *) GPIOP_BASE_S) +#define GPIOQ_S ((GPIO_TypeDef *) GPIOQ_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HPDMA1_S ((DMA_TypeDef *) HPDMA1_BASE_S) +#define HPDMA1_Channel0_S ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S) +#define HPDMA1_Channel1_S ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S) +#define HPDMA1_Channel2_S ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S) +#define HPDMA1_Channel3_S ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S) +#define HPDMA1_Channel4_S ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S) +#define HPDMA1_Channel5_S ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S) +#define HPDMA1_Channel6_S ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S) +#define HPDMA1_Channel7_S ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S) +#define HPDMA1_Channel8_S ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S) +#define HPDMA1_Channel9_S ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S) +#define HPDMA1_Channel10_S ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S) +#define HPDMA1_Channel11_S ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S) +#define HPDMA1_Channel12_S ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S) +#define HPDMA1_Channel13_S ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S) +#define HPDMA1_Channel14_S ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S) +#define HPDMA1_Channel15_S ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define IAC_S ((IAC_TypeDef *) IAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define LTDC_S ((LTDC_TypeDef *)LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S) +#define MCE1_S ((MCE_TypeDef *) MCE1_BASE_S) +#define MCE1_REGION1_S ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S) +#define MCE1_REGION2_S ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S) +#define MCE1_REGION3_S ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S) +#define MCE1_REGION4_S ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S) +#define MCE1_CONTEXT1_S ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S) +#define MCE1_CONTEXT2_S ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S) +#define MCE2_S ((MCE_TypeDef *) MCE2_BASE_S) +#define MCE2_REGION1_S ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S) +#define MCE2_REGION2_S ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S) +#define MCE2_REGION3_S ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S) +#define MCE2_REGION4_S ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S) +#define MCE2_CONTEXT1_S ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S) +#define MCE2_CONTEXT2_S ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S) +#define MCE3_S ((MCE_TypeDef *) MCE3_BASE_S) +#define MCE3_REGION1_S ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S) +#define MCE3_REGION2_S ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S) +#define MCE3_REGION3_S ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S) +#define MCE3_REGION4_S ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S) +#define MCE3_CONTEXT1_S ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S) +#define MCE3_CONTEXT2_S ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S) +#define MCE4_S ((MCE_TypeDef *) MCE4_BASE_S) +#define MCE4_REGION1_S ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S) +#define MCE4_REGION2_S ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S) +#define MCE4_REGION3_S ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S) +#define MCE4_REGION4_S ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S) +#define MCE4_CONTEXT1_S ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S) +#define MCE4_CONTEXT2_S ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S) +#define MDIOS_S ((MDIOS_TypeDef *) MDIOS_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_S ((RAMCFG_TypeDef *) RAMCFG_BASE_S) +#define RAMCFG_SRAM1_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S) +#define RAMCFG_SRAM2_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S) +#define RAMCFG_SRAM3_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S) +#define RAMCFG_SRAM4_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S) +#define RAMCFG_SRAM5_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S) +#define RAMCFG_SRAM6_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S) +#define RAMCFG_SRAM1_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S) +#define RAMCFG_SRAM2_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S) +#define RAMCFG_VENC_RAM_S ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS) +#define RAMCFG_BKPSRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S) +#define RAMCFG_FLEXRAM_S ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RIFSC_S ((RIFSC_TypeDef *) RIFSC_BASE_S) +#define RISAF1_S ((RISAF_TypeDef *) RISAF1_BASE_S) +#define RISAF2_S ((RISAF_TypeDef *) RISAF2_BASE_S) +#define RISAF3_S ((RISAF_TypeDef *) RISAF3_BASE_S) +#define RISAF4_S ((RISAF_TypeDef *) RISAF4_BASE_S) +#define RISAF5_S ((RISAF_TypeDef *) RISAF5_BASE_S) +#define RISAF6_S ((RISAF_TypeDef *) RISAF6_BASE_S) +#define RISAF7_S ((RISAF_TypeDef *) RISAF7_BASE_S) +#define RISAF8_S ((RISAF_TypeDef *) RISAF8_BASE_S) +#define RISAF9_S ((RISAF_TypeDef *) RISAF9_BASE_S) +#define RISAF11_S ((RISAF_TypeDef *) RISAF11_BASE_S) +#define RISAF12_S ((RISAF_TypeDef *) RISAF12_BASE_S) +#define RISAF13_S ((RISAF_TypeDef *) RISAF13_BASE_S) +#define RISAF14_S ((RISAF_TypeDef *) RISAF14_BASE_S) +#define RISAF15_S ((RISAF_TypeDef *) RISAF15_BASE_S) +#define RISAF21_S ((RISAF_TypeDef *) RISAF21_BASE_S) +#define RISAF22_S ((RISAF_TypeDef *) RISAF22_BASE_S) +#define RISAF23_S ((RISAF_TypeDef *) RISAF23_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((SAES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define SPDIFRX_S ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define TIM9_S ((TIM_TypeDef *) TIM9_BASE_S) +#define TIM10_S ((TIM_TypeDef *) TIM10_BASE_S) +#define TIM11_S ((TIM_TypeDef *) TIM11_BASE_S) +#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *) TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *) TIM14_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TIM18_S ((TIM_TypeDef *) TIM18_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define UART7_S ((USART_TypeDef *) UART7_BASE_S) +#define UART8_S ((USART_TypeDef *) UART8_BASE_S) +#define UART9_S ((USART_TypeDef *) UART9_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define USART10_S ((USART_TypeDef *) USART10_BASE_S) +#define USB1_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S) +#define USB2_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S) +#define USB1_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S) +#define USB2_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S) +#define VENC_S ((VENC_TypeDef *) VENC_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define XSPI1_S ((XSPI_TypeDef *) XSPI1_BASE_S) +#define XSPI2_S ((XSPI_TypeDef *) XSPI2_BASE_S) +#define XSPI3_S ((XSPI_TypeDef *) XSPI3_BASE_S) +#define XSPIM_S ((XSPIM_TypeDef *) XSPIM_BASE_S) +#endif + +/*!< Peripheral Instance aliases for Non-Secure/Secure execution */ +#if defined (CPU_IN_SECURE_STATE) +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define BSEC BSEC_S +#define BSEC_BASE BSEC_BASE_S + +#define CACHEAXI CACHEAXI_S +#define CACHEAXI_BASE CACHEAXI_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define CRYP CRYP_S +#define CRYP_BASE CRYP_BASE_S + +#define CSI CSI_S +#define CSI_BASE CSI_BASE_S + +#define DBGMCU DBGMCU_S +#define DBGMCU_BASE DBGMCU_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define DCMIPP DCMIPP_S +#define DCMIPP_BASE DCMIPP_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define DTS_Sensor0 DTS_Sensor0_S +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_S + +#define DTS_Sensor1 DTS_Sensor1_S +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_S + +#define ETH1 ETH1_S +#define ETH1_BASE ETH1_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define FDCAN3 FDCAN3_S +#define FDCAN3_BASE FDCAN3_BASE_S + +#define FDCAN_CCU FDCAN_CCU_S +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_S + +#define FMC_R_BASE FMC_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define FMC_Common_R FMC_Common_R_S +#define FMC_Common_R_BASE FMC_Common_R_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPION GPION_S +#define GPION_BASE GPION_BASE_S + +#define GPIOO GPIOO_S +#define GPIOO_BASE GPIOO_BASE_S + +#define GPIOP GPIOP_S +#define GPIOP_BASE GPIOP_BASE_S + +#define GPIOQ GPIOQ_S +#define GPIOQ_BASE GPIOQ_BASE_S + +#define GPU2D GPU2D_BASE_S +#define GPU2D_BASE GPU2D_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define HPDMA1 HPDMA1_S +#define HPDMA1_BASE HPDMA1_BASE_S + +#define HPDMA1_Channel0 HPDMA1_Channel0_S +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_S + +#define HPDMA1_Channel1 HPDMA1_Channel1_S +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_S + +#define HPDMA1_Channel2 HPDMA1_Channel2_S +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_S + +#define HPDMA1_Channel3 HPDMA1_Channel3_S +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_S + +#define HPDMA1_Channel4 HPDMA1_Channel4_S +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_S + +#define HPDMA1_Channel5 HPDMA1_Channel5_S +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_S + +#define HPDMA1_Channel6 HPDMA1_Channel6_S +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_S + +#define HPDMA1_Channel7 HPDMA1_Channel7_S +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_S + +#define HPDMA1_Channel8 HPDMA1_Channel8_S +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_S + +#define HPDMA1_Channel9 HPDMA1_Channel9_S +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_S + +#define HPDMA1_Channel10 HPDMA1_Channel10_S +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_S + +#define HPDMA1_Channel11 HPDMA1_Channel11_S +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_S + +#define HPDMA1_Channel12 HPDMA1_Channel12_S +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_S + +#define HPDMA1_Channel13 HPDMA1_Channel13_S +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_S + +#define HPDMA1_Channel14 HPDMA1_Channel14_S +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_S + +#define HPDMA1_Channel15 HPDMA1_Channel15_S +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define IAC IAC_S +#define IAC_BASE IAC_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1 LTDC_Layer1_S +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S + +#define LTDC_Layer2 LTDC_Layer2_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define MCE1 MCE1_S +#define MCE1_BASE MCE1_BASE_S + +#define MCE1_REGION1 MCE1_REGION1_S +#define MCE1_REGION1_BASE MCE1_REGION1_BASE_S + +#define MCE1_REGION2 MCE1_REGION2_S +#define MCE1_REGION2_BASE MCE1_REGION2_BASE_S + +#define MCE1_REGION3 MCE1_REGION3_S +#define MCE1_REGION3_BASE MCE1_REGION3_BASE_S + +#define MCE1_REGION4 MCE1_REGION4_S +#define MCE1_REGION4_BASE MCE1_REGION4_BASE_S + +#define MCE1_CONTEXT1 MCE1_CONTEXT1_S +#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_S + +#define MCE1_CONTEXT2 MCE1_CONTEXT2_S +#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_S + +#define MCE2 MCE2_S +#define MCE2_BASE MCE2_BASE_S + +#define MCE2_REGION1 MCE2_REGION1_S +#define MCE2_REGION1_BASE MCE2_REGION1_BASE_S + +#define MCE2_REGION2 MCE2_REGION2_S +#define MCE2_REGION2_BASE MCE2_REGION2_BASE_S + +#define MCE2_REGION3 MCE2_REGION3_S +#define MCE2_REGION3_BASE MCE2_REGION3_BASE_S + +#define MCE2_REGION4 MCE2_REGION4_S +#define MCE2_REGION4_BASE MCE2_REGION4_BASE_S + +#define MCE2_CONTEXT1 MCE2_CONTEXT1_S +#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_S + +#define MCE2_CONTEXT2 MCE2_CONTEXT2_S +#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_S + +#define MCE3 MCE3_S +#define MCE3_BASE MCE3_BASE_S + +#define MCE3_REGION1 MCE3_REGION1_S +#define MCE3_REGION1_BASE MCE3_REGION1_BASE_S + +#define MCE3_REGION2 MCE3_REGION2_S +#define MCE3_REGION2_BASE MCE3_REGION2_BASE_S + +#define MCE3_REGION3 MCE3_REGION3_S +#define MCE3_REGION3_BASE MCE3_REGION3_BASE_S + +#define MCE3_REGION4 MCE3_REGION4_S +#define MCE3_REGION4_BASE MCE3_REGION4_BASE_S + +#define MCE3_CONTEXT1 MCE3_CONTEXT1_S +#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_S + +#define MCE3_CONTEXT2 MCE3_CONTEXT2_S +#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_S + +#define MCE4 MCE4_S +#define MCE4_BASE MCE4_BASE_S + +#define MCE4_REGION1 MCE4_REGION1_S +#define MCE4_REGION1_BASE MCE4_REGION1_BASE_S + +#define MCE4_REGION2 MCE4_REGION2_S +#define MCE4_REGION2_BASE MCE4_REGION2_BASE_S + +#define MCE4_REGION3 MCE4_REGION3_S +#define MCE4_REGION3_BASE MCE4_REGION3_BASE_S + +#define MCE4_REGION4 MCE4_REGION4_S +#define MCE4_REGION4_BASE MCE4_REGION4_BASE_S + +#define MCE4_CONTEXT1 MCE4_CONTEXT1_S +#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_S + +#define MCE4_CONTEXT2 MCE4_CONTEXT2_S +#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define MDIOS MDIOS_S +#define MDIOS_BASE MDIOS_BASE_S + +#define NPU_PRESENT +#define NPU_BASE NPU_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG RAMCFG_S +#define RAMCFG_BASE RAMCFG_BASE_S + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_S +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_S + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_S +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_S + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_S +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_S + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_S +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_S + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_S +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_S + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_S +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_S + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_S +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_S + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_S +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_S + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_S +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_S + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_S +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_S + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_S +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define RIFSC RIFSC_S +#define RIFSC_BASE RIFSC_BASE_S + +#define RISAF1 RISAF1_S +#define RISAF1_BASE RISAF1_BASE_S + +#define RISAF2 RISAF2_S +#define RISAF2_BASE RISAF2_BASE_S + +#define RISAF3 RISAF3_S +#define RISAF3_BASE RISAF3_BASE_S + +#define RISAF4 RISAF4_S +#define RISAF4_BASE RISAF4_BASE_S + +#define RISAF5 RISAF5_S +#define RISAF5_BASE RISAF5_BASE_S + +#define RISAF6 RISAF6_S +#define RISAF6_BASE RISAF6_BASE_S + +#define RISAF7 RISAF7_S +#define RISAF7_BASE RISAF7_BASE_S + +#define RISAF8 RISAF8_S +#define RISAF8_BASE RISAF8_BASE_S + +#define RISAF9 RISAF9_S +#define RISAF9_BASE RISAF9_BASE_S + +#define RISAF11 RISAF11_S +#define RISAF11_BASE RISAF11_BASE_S + +#define RISAF12 RISAF12_S +#define RISAF12_BASE RISAF12_BASE_S + +#define RISAF13 RISAF13_S +#define RISAF13_BASE RISAF13_BASE_S + +#define RISAF14 RISAF14_S +#define RISAF14_BASE RISAF14_BASE_S + +#define RISAF15 RISAF15_S +#define RISAF15_BASE RISAF15_BASE_S + +#define RISAF21 RISAF21_S +#define RISAF21_BASE RISAF21_BASE_S + +#define RISAF22 RISAF22_S +#define RISAF22_BASE RISAF22_BASE_S + +#define RISAF23 RISAF23_S +#define RISAF23_BASE RISAF23_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define SPDIFRX SPDIFRX_S +#define SPDIFRX_BASE SPDIFRX_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM9 TIM9_S +#define TIM9_BASE TIM9_BASE_S + +#define TIM10 TIM10_S +#define TIM10_BASE TIM10_BASE_S + +#define TIM11 TIM11_S +#define TIM11_BASE TIM11_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define TIM18 TIM18_S +#define TIM18_BASE TIM18_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USB1_OTG_HS USB1_OTG_HS_S +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_S + +#define USB2_OTG_HS USB2_OTG_HS_S +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_S + +#define USB1_HS_PHYC USB1_HS_PHYC_S +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_S + +#define USB2_HS_PHYC USB2_HS_PHYC_S +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_S + +#define VENC VENC_S +#define VENC_BASE VENC_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define XSPI1 XSPI1_S + +#define XSPI2 XSPI2_S + +#define XSPI3 XSPI3_S + +#define XSPIM XSPIM_S +#define XSPIM_BASE XSPIM_BASE_S + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_S + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_S + +#else + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS + +#define BSEC BSEC_NS +#define BSEC_BASE BSEC_BASE_NS + +#define CACHEAXI CACHEAXI_NS +#define CACHEAXI_BASE CACHEAXI_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define CRYP CRYP_NS +#define CRYP_BASE CRYP_BASE_NS + +#define CSI CSI_NS +#define CSI_BASE CSI_BASE_NS + +#define DBGMCU DBGMCU_NS +#define DBGMCU_BASE DBGMCU_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define DCMIPP DCMIPP_NS +#define DCMIPP_BASE DCMIPP_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define DTS_Sensor0 DTS_Sensor0_NS +#define DTS_Sensor0_BASE DTS_Sensor0_BASE_NS + +#define DTS_Sensor1 DTS_Sensor1_NS +#define DTS_Sensor1_BASE DTS_Sensor1_BASE_NS + +#define ETH1 ETH1_NS +#define ETH1_BASE ETH1_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define FDCAN3 FDCAN3_NS +#define FDCAN3_BASE FDCAN3_BASE_NS + +#define FDCAN_CCU FDCAN_CCU_NS +#define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS + +#define FMC_R_BASE FMC_R_BASE_NS +#define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_Rv FMC_Bank1_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define FMC_Common_R FMC_Common_R_NS +#define FMC_Common_R_BASE FMC_Common_R_BASE_NS + +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPION GPION_NS +#define GPION_BASE GPION_BASE_NS + +#define GPIOO GPIOO_NS +#define GPIOO_BASE GPIOO_BASE_NS + +#define GPIOP GPIOP_NS +#define GPIOP_BASE GPIOP_BASE_NS + +#define GPIOQ GPIOQ_NS +#define GPIOQ_BASE GPIOQ_BASE_NS + +#define GPU2D GPU2D_BASE_NS +#define GPU2D_BASE GPU2D_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define HPDMA1 HPDMA1_NS +#define HPDMA1_BASE HPDMA1_BASE_NS + +#define HPDMA1_Channel0 HPDMA1_Channel0_NS +#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_NS + +#define HPDMA1_Channel1 HPDMA1_Channel1_NS +#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_NS + +#define HPDMA1_Channel2 HPDMA1_Channel2_NS +#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_NS + +#define HPDMA1_Channel3 HPDMA1_Channel3_NS +#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_NS + +#define HPDMA1_Channel4 HPDMA1_Channel4_NS +#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_NS + +#define HPDMA1_Channel5 HPDMA1_Channel5_NS +#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_NS + +#define HPDMA1_Channel6 HPDMA1_Channel6_NS +#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_NS + +#define HPDMA1_Channel7 HPDMA1_Channel7_NS +#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_NS + +#define HPDMA1_Channel8 HPDMA1_Channel8_NS +#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_NS + +#define HPDMA1_Channel9 HPDMA1_Channel9_NS +#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_NS + +#define HPDMA1_Channel10 HPDMA1_Channel10_NS +#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_NS + +#define HPDMA1_Channel11 HPDMA1_Channel11_NS +#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_NS + +#define HPDMA1_Channel12 HPDMA1_Channel12_NS +#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_NS + +#define HPDMA1_Channel13 HPDMA1_Channel13_NS +#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_NS + +#define HPDMA1_Channel14 HPDMA1_Channel14_NS +#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_NS + +#define HPDMA1_Channel15 HPDMA1_Channel15_NS +#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define MCE1 MCE1_NS +#define MCE1_BASE MCE1_BASE_NS + +#define MCE1_REGION1 MCE1_REGION1_NS +#define MCE1_REGION1_BASE MCE1_REGION1_BASE_NS + +#define MCE1_REGION2 MCE1_REGION2_NS +#define MCE1_REGION2_BASE MCE1_REGION2_BASE_NS + +#define MCE1_REGION3 MCE1_REGION3_NS +#define MCE1_REGION3_BASE MCE1_REGION3_BASE_NS + +#define MCE1_REGION4 MCE1_REGION4_NS +#define MCE1_REGION4_BASE MCE1_REGION4_BASE_NS + +#define MCE1_CONTEXT1 MCE1_CONTEXT1_NS +#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_NS + +#define MCE1_CONTEXT2 MCE1_CONTEXT2_NS +#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_NS + +#define MCE2 MCE2_NS +#define MCE2_BASE MCE2_BASE_NS + +#define MCE2_REGION1 MCE2_REGION1_NS +#define MCE2_REGION1_BASE MCE2_REGION1_BASE_NS + +#define MCE2_REGION2 MCE2_REGION2_NS +#define MCE2_REGION2_BASE MCE2_REGION2_BASE_NS + +#define MCE2_REGION3 MCE2_REGION3_NS +#define MCE2_REGION3_BASE MCE2_REGION3_BASE_NS + +#define MCE2_REGION4 MCE2_REGION4_NS +#define MCE2_REGION4_BASE MCE2_REGION4_BASE_NS + +#define MCE2_CONTEXT1 MCE2_CONTEXT1_NS +#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_NS + +#define MCE2_CONTEXT2 MCE2_CONTEXT2_NS +#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_NS + +#define MCE3 MCE3_NS +#define MCE3_BASE MCE3_BASE_NS + +#define MCE3_REGION1 MCE3_REGION1_NS +#define MCE3_REGION1_BASE MCE3_REGION1_BASE_NS + +#define MCE3_REGION2 MCE3_REGION2_NS +#define MCE3_REGION2_BASE MCE3_REGION2_BASE_NS + +#define MCE3_REGION3 MCE3_REGION3_NS +#define MCE3_REGION3_BASE MCE3_REGION3_BASE_NS + +#define MCE3_REGION4 MCE3_REGION4_NS +#define MCE3_REGION4_BASE MCE3_REGION4_BASE_NS + +#define MCE3_CONTEXT1 MCE3_CONTEXT1_NS +#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_NS + +#define MCE3_CONTEXT2 MCE3_CONTEXT2_NS +#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_NS + +#define MCE4 MCE4_NS +#define MCE4_BASE MCE4_BASE_NS + +#define MCE4_REGION1 MCE4_REGION1_NS +#define MCE4_REGION1_BASE MCE4_REGION1_BASE_NS + +#define MCE4_REGION2 MCE4_REGION2_NS +#define MCE4_REGION2_BASE MCE4_REGION2_BASE_NS + +#define MCE4_REGION3 MCE4_REGION3_NS +#define MCE4_REGION3_BASE MCE4_REGION3_BASE_NS + +#define MCE4_REGION4 MCE4_REGION4_NS +#define MCE4_REGION4_BASE MCE4_REGION4_BASE_NS + +#define MCE4_CONTEXT1 MCE4_CONTEXT1_NS +#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_NS + +#define MCE4_CONTEXT2 MCE4_CONTEXT2_NS +#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define MDIOS MDIOS_NS +#define MDIOS_BASE MDIOS_BASE_NS + +#define NPU_PRESENT +#define NPU_BASE NPU_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG RAMCFG_NS +#define RAMCFG_BASE RAMCFG_BASE_NS + +#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_NS +#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_NS + +#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_NS +#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_NS + +#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_NS +#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_NS + +#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_NS +#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_NS + +#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_NS +#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_NS + +#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_NS +#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_NS + +#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_NS +#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_NS + +#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_NS +#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_NS + +#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_NS +#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_NS + +#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_NS +#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_NS + +#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_NS +#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define RIFSC RIFSC_NS +#define RIFSC_BASE RIFSC_BASE_NS + +#define RISAF1 RISAF1_NS +#define RISAF1_BASE RISAF1_BASE_NS + +#define RISAF2 RISAF2_NS +#define RISAF2_BASE RISAF2_BASE_NS + +#define RISAF3 RISAF3_NS +#define RISAF3_BASE RISAF3_BASE_NS + +#define RISAF4 RISAF4_NS +#define RISAF4_BASE RISAF4_BASE_NS + +#define RISAF5 RISAF5_NS +#define RISAF5_BASE RISAF5_BASE_NS + +#define RISAF6 RISAF6_NS +#define RISAF6_BASE RISAF6_BASE_NS + +#define RISAF7 RISAF7_NS +#define RISAF7_BASE RISAF7_BASE_NS + +#define RISAF8 RISAF8_NS +#define RISAF8_BASE RISAF8_BASE_NS + +#define RISAF9 RISAF9_NS +#define RISAF9_BASE RISAF9_BASE_NS + +#define RISAF11 RISAF11_NS +#define RISAF11_BASE RISAF11_BASE_NS + +#define RISAF12 RISAF12_NS +#define RISAF12_BASE RISAF12_BASE_NS + +#define RISAF13 RISAF13_NS +#define RISAF13_BASE RISAF13_BASE_NS + +#define RISAF14 RISAF14_NS +#define RISAF14_BASE RISAF14_BASE_NS + +#define RISAF15 RISAF15_NS +#define RISAF15_BASE RISAF15_BASE_NS + +#define RISAF21 RISAF21_NS +#define RISAF21_BASE RISAF21_BASE_NS + +#define RISAF22 RISAF22_NS +#define RISAF22_BASE RISAF22_BASE_NS + +#define RISAF23 RISAF23_NS +#define RISAF23_BASE RISAF23_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define SPDIFRX SPDIFRX_NS +#define SPDIFRX_BASE SPDIFRX_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM9 TIM9_NS +#define TIM9_BASE TIM9_BASE_NS + +#define TIM10 TIM10_NS +#define TIM10_BASE TIM10_BASE_NS + +#define TIM11 TIM11_NS +#define TIM11_BASE TIM11_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define TIM18 TIM18_NS +#define TIM18_BASE TIM18_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USB1_OTG_HS USB1_OTG_HS_NS +#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_NS + +#define USB2_OTG_HS USB2_OTG_HS_NS +#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_NS + +#define USB1_HS_PHYC USB1_HS_PHYC_NS +#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_NS + +#define USB2_HS_PHYC USB2_HS_PHYC_NS +#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_NS + +#define VENC VENC_NS +#define VENC_BASE VENC_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define XSPI1 XSPI1_NS + +#define XSPI2 XSPI2_NS + +#define XSPI3 XSPI3_NS + +#define XSPIM XSPIM_NS +#define XSPIM_BASE XSPIM_BASE_NS + +/*!< Unique device ID register base address */ +#define UID_BASE UID_BASE_NS + +/*!< Revision ID base address */ +#define REVID_BASE REVID_BASE_NS + +#endif + +/** @} */ /* End of group STM32N6xx_Peripheral_declaration */ + +/** @addtogroup STM32N6xx_Peripheral_Timing_Definition + * @{ + */ + +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ + +/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* Specific device feature definitions */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30UL) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register ******************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register *****************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */ +#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */ +#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */ +#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */ +#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */ +#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */ +#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */ +#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */ +#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */ +#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */ +#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */ +#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */ +#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */ +#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */ +#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */ +#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR1 register ***************/ +#define ADC_OFCFGR1_POSOFF_Pos (24UL) +#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */ + +#define ADC_OFCFGR1_USAT_Pos (25UL) +#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */ + +#define ADC_OFCFGR1_SSAT_Pos (26UL) +#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */ + +#define ADC_OFCFGR1_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */ +#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR2 register ***************/ +#define ADC_OFCFGR2_POSOFF_Pos (24UL) +#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */ + +#define ADC_OFCFGR2_USAT_Pos (25UL) +#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */ + +#define ADC_OFCFGR2_SSAT_Pos (26UL) +#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */ + +#define ADC_OFCFGR2_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */ +#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR3 register ***************/ +#define ADC_OFCFGR3_POSOFF_Pos (24UL) +#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */ + +#define ADC_OFCFGR3_USAT_Pos (25UL) +#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */ + +#define ADC_OFCFGR3_SSAT_Pos (26UL) +#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */ + +#define ADC_OFCFGR3_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */ +#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFCFGR4 register ***************/ +#define ADC_OFCFGR4_POSOFF_Pos (24UL) +#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */ +#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */ + +#define ADC_OFCFGR4_USAT_Pos (25UL) +#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */ + +#define ADC_OFCFGR4_SSAT_Pos (26UL) +#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */ +#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */ + +#define ADC_OFCFGR4_OFFSET_CH_Pos (27UL) +#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */ +#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */ +#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET_Pos (0UL) +#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */ +#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET_Pos (0UL) +#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */ +#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET_Pos (0UL) +#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */ +#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET_Pos (0UL) +#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */ +#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */ +#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD1TR_LT register *************/ +#define ADC_AWD1LTR_LTR_Pos (0UL) +#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD1TR_HT register *******************/ +#define ADC_AWD1HTR_HTR_Pos (0UL) +#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */ +#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */ + +#define ADC_AWD1HTR_AWDFILT_Pos (29UL) +#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */ +#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */ +#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */ +#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */ +#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for ADC_AWD2TR_LT register *******************/ +#define ADC_AWD2LTR_LTR_Pos (0UL) +#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD2TR_HT register *******************/ +#define ADC_AWD2HTR_HTR_Pos (0UL) +#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_LT register *******************/ +#define ADC_AWD3LTR_LTR_Pos (0UL) +#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_AWD3TR_HT register *******************/ +#define ADC_AWD3HTR_HTR_Pos (0UL) +#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */ +#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */ +#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */ +#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */ +#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */ +#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0UL) +#define ADC_CALFACT_CALFACT_S_Msk (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000003FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x80UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16UL) +#define ADC_CALFACT_CALFACT_D_Msk (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x03FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x80UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ + +#define ADC_CALFACT_CALADDOS_Pos (31UL) +#define ADC_CALFACT_CALADDOS_Msk (0x01UL << ADC_CALFACT_CALADDOS_Pos) /*!< 0x80000000 */ +#define ADC_CALFACT_CALADDOS ADC_CALFACT_CALADDOS_Msk /*!< ADC calibration additional offset mode */ + +/******************** Bit definition for ADC_OR option register ***************/ +#define ADC_OR_OP0_Pos (0UL) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal reference voltage buffer */ + +#define ADC_OR_OP1_Pos (1UL) +#define ADC_OR_OP1_Msk (0x1UL << ADC_OR_OP1_Pos) /*!< 0x00000002 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC internal bandgap */ + +#define ADC_OR_OP2_Pos (2UL) +#define ADC_OR_OP2_Msk (0x1UL << ADC_OR_OP2_Pos) /*!< 0x00000004 */ +#define ADC_OR_OP2 ADC_OR_OP2_Msk /*!< ADC internal path to VDDCORE */ + + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* BSEC unit (Boot and Security) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for BSEC_FVRw register *******************/ +#define BSEC_FVRw_FV_Pos (0UL) +#define BSEC_FVRw_FV_Msk (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_FVRw_FV BSEC_FVRw_FV_Msk /*!< Fuse value */ + +/***************** Bit definition for BSEC_SPLOCKx register *****************/ +#define BSEC_SPLOCKx_SPLOCK0_Pos (0UL) +#define BSEC_SPLOCKx_SPLOCK0_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SPLOCKx_SPLOCK0 BSEC_SPLOCKx_SPLOCK0_Msk /*!< Sticky programming lock for word (32*x) */ +#define BSEC_SPLOCKx_SPLOCK1_Pos (1UL) +#define BSEC_SPLOCKx_SPLOCK1_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SPLOCKx_SPLOCK1 BSEC_SPLOCKx_SPLOCK1_Msk /*!< Sticky programming lock for word (1+32*x) */ +#define BSEC_SPLOCKx_SPLOCK2_Pos (2UL) +#define BSEC_SPLOCKx_SPLOCK2_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SPLOCKx_SPLOCK2 BSEC_SPLOCKx_SPLOCK2_Msk /*!< Sticky programming lock for word (2+32*x) */ +#define BSEC_SPLOCKx_SPLOCK3_Pos (3UL) +#define BSEC_SPLOCKx_SPLOCK3_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SPLOCKx_SPLOCK3 BSEC_SPLOCKx_SPLOCK3_Msk /*!< Sticky programming lock for word (3+32*x) */ +#define BSEC_SPLOCKx_SPLOCK4_Pos (4UL) +#define BSEC_SPLOCKx_SPLOCK4_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SPLOCKx_SPLOCK4 BSEC_SPLOCKx_SPLOCK4_Msk /*!< Sticky programming lock for word (4+32*x) */ +#define BSEC_SPLOCKx_SPLOCK5_Pos (5UL) +#define BSEC_SPLOCKx_SPLOCK5_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SPLOCKx_SPLOCK5 BSEC_SPLOCKx_SPLOCK5_Msk /*!< Sticky programming lock for word (5+32*x) */ +#define BSEC_SPLOCKx_SPLOCK6_Pos (6UL) +#define BSEC_SPLOCKx_SPLOCK6_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SPLOCKx_SPLOCK6 BSEC_SPLOCKx_SPLOCK6_Msk /*!< Sticky programming lock for word (6+32*x) */ +#define BSEC_SPLOCKx_SPLOCK7_Pos (7UL) +#define BSEC_SPLOCKx_SPLOCK7_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SPLOCKx_SPLOCK7 BSEC_SPLOCKx_SPLOCK7_Msk /*!< Sticky programming lock for word (7+32*x) */ +#define BSEC_SPLOCKx_SPLOCK8_Pos (8UL) +#define BSEC_SPLOCKx_SPLOCK8_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SPLOCKx_SPLOCK8 BSEC_SPLOCKx_SPLOCK8_Msk /*!< Sticky programming lock for word (8+32*x) */ +#define BSEC_SPLOCKx_SPLOCK9_Pos (9UL) +#define BSEC_SPLOCKx_SPLOCK9_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SPLOCKx_SPLOCK9 BSEC_SPLOCKx_SPLOCK9_Msk /*!< Sticky programming lock for word (9+32*x) */ +#define BSEC_SPLOCKx_SPLOCK10_Pos (10UL) +#define BSEC_SPLOCKx_SPLOCK10_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SPLOCKx_SPLOCK10 BSEC_SPLOCKx_SPLOCK10_Msk /*!< Sticky programming lock for word (10+32*x) */ +#define BSEC_SPLOCKx_SPLOCK11_Pos (11UL) +#define BSEC_SPLOCKx_SPLOCK11_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SPLOCKx_SPLOCK11 BSEC_SPLOCKx_SPLOCK11_Msk /*!< Sticky programming lock for word (11+32*x) */ +#define BSEC_SPLOCKx_SPLOCK12_Pos (12UL) +#define BSEC_SPLOCKx_SPLOCK12_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SPLOCKx_SPLOCK12 BSEC_SPLOCKx_SPLOCK12_Msk /*!< Sticky programming lock for word (12+32*x) */ +#define BSEC_SPLOCKx_SPLOCK13_Pos (13UL) +#define BSEC_SPLOCKx_SPLOCK13_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SPLOCKx_SPLOCK13 BSEC_SPLOCKx_SPLOCK13_Msk /*!< Sticky programming lock for word (13+32*x) */ +#define BSEC_SPLOCKx_SPLOCK14_Pos (14UL) +#define BSEC_SPLOCKx_SPLOCK14_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SPLOCKx_SPLOCK14 BSEC_SPLOCKx_SPLOCK14_Msk /*!< Sticky programming lock for word (14+32*x) */ +#define BSEC_SPLOCKx_SPLOCK15_Pos (15UL) +#define BSEC_SPLOCKx_SPLOCK15_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SPLOCKx_SPLOCK15 BSEC_SPLOCKx_SPLOCK15_Msk /*!< Sticky programming lock for word (15+32*x) */ +#define BSEC_SPLOCKx_SPLOCK16_Pos (16UL) +#define BSEC_SPLOCKx_SPLOCK16_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SPLOCKx_SPLOCK16 BSEC_SPLOCKx_SPLOCK16_Msk /*!< Sticky programming lock for word (16+32*x) */ +#define BSEC_SPLOCKx_SPLOCK17_Pos (17UL) +#define BSEC_SPLOCKx_SPLOCK17_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SPLOCKx_SPLOCK17 BSEC_SPLOCKx_SPLOCK17_Msk /*!< Sticky programming lock for word (17+32*x) */ +#define BSEC_SPLOCKx_SPLOCK18_Pos (18UL) +#define BSEC_SPLOCKx_SPLOCK18_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SPLOCKx_SPLOCK18 BSEC_SPLOCKx_SPLOCK18_Msk /*!< Sticky programming lock for word (18+32*x) */ +#define BSEC_SPLOCKx_SPLOCK19_Pos (19UL) +#define BSEC_SPLOCKx_SPLOCK19_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SPLOCKx_SPLOCK19 BSEC_SPLOCKx_SPLOCK19_Msk /*!< Sticky programming lock for word (19+32*x) */ +#define BSEC_SPLOCKx_SPLOCK20_Pos (20UL) +#define BSEC_SPLOCKx_SPLOCK20_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SPLOCKx_SPLOCK20 BSEC_SPLOCKx_SPLOCK20_Msk /*!< Sticky programming lock for word (20+32*x) */ +#define BSEC_SPLOCKx_SPLOCK21_Pos (21UL) +#define BSEC_SPLOCKx_SPLOCK21_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SPLOCKx_SPLOCK21 BSEC_SPLOCKx_SPLOCK21_Msk /*!< Sticky programming lock for word (21+32*x) */ +#define BSEC_SPLOCKx_SPLOCK22_Pos (22UL) +#define BSEC_SPLOCKx_SPLOCK22_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SPLOCKx_SPLOCK22 BSEC_SPLOCKx_SPLOCK22_Msk /*!< Sticky programming lock for word (22+32*x) */ +#define BSEC_SPLOCKx_SPLOCK23_Pos (23UL) +#define BSEC_SPLOCKx_SPLOCK23_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SPLOCKx_SPLOCK23 BSEC_SPLOCKx_SPLOCK23_Msk /*!< Sticky programming lock for word (23+32*x) */ +#define BSEC_SPLOCKx_SPLOCK24_Pos (24UL) +#define BSEC_SPLOCKx_SPLOCK24_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SPLOCKx_SPLOCK24 BSEC_SPLOCKx_SPLOCK24_Msk /*!< Sticky programming lock for word (24+32*x) */ +#define BSEC_SPLOCKx_SPLOCK25_Pos (25UL) +#define BSEC_SPLOCKx_SPLOCK25_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SPLOCKx_SPLOCK25 BSEC_SPLOCKx_SPLOCK25_Msk /*!< Sticky programming lock for word (25+32*x) */ +#define BSEC_SPLOCKx_SPLOCK26_Pos (26UL) +#define BSEC_SPLOCKx_SPLOCK26_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SPLOCKx_SPLOCK26 BSEC_SPLOCKx_SPLOCK26_Msk /*!< Sticky programming lock for word (26+32*x) */ +#define BSEC_SPLOCKx_SPLOCK27_Pos (27UL) +#define BSEC_SPLOCKx_SPLOCK27_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SPLOCKx_SPLOCK27 BSEC_SPLOCKx_SPLOCK27_Msk /*!< Sticky programming lock for word (27+32*x) */ +#define BSEC_SPLOCKx_SPLOCK28_Pos (28UL) +#define BSEC_SPLOCKx_SPLOCK28_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SPLOCKx_SPLOCK28 BSEC_SPLOCKx_SPLOCK28_Msk /*!< Sticky programming lock for word (28+32*x) */ +#define BSEC_SPLOCKx_SPLOCK29_Pos (29UL) +#define BSEC_SPLOCKx_SPLOCK29_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SPLOCKx_SPLOCK29 BSEC_SPLOCKx_SPLOCK29_Msk /*!< Sticky programming lock for word (29+32*x) */ +#define BSEC_SPLOCKx_SPLOCK30_Pos (30UL) +#define BSEC_SPLOCKx_SPLOCK30_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SPLOCKx_SPLOCK30 BSEC_SPLOCKx_SPLOCK30_Msk /*!< Sticky programming lock for word (30+32*x) */ +#define BSEC_SPLOCKx_SPLOCK31_Pos (31UL) +#define BSEC_SPLOCKx_SPLOCK31_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SPLOCKx_SPLOCK31 BSEC_SPLOCKx_SPLOCK31_Msk /*!< Sticky programming lock for word (31+32*x) */ + +/***************** Bit definition for BSEC_SWLOCKx register *****************/ +#define BSEC_SWLOCKx_SWLOCK0_Pos (0UL) +#define BSEC_SWLOCKx_SWLOCK0_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SWLOCKx_SWLOCK0 BSEC_SWLOCKx_SWLOCK0_Msk /*!< Sticky write lock for shadow register (32*x) */ +#define BSEC_SWLOCKx_SWLOCK1_Pos (1UL) +#define BSEC_SWLOCKx_SWLOCK1_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SWLOCKx_SWLOCK1 BSEC_SWLOCKx_SWLOCK1_Msk /*!< Sticky write lock for shadow register (1+32*x) */ +#define BSEC_SWLOCKx_SWLOCK2_Pos (2UL) +#define BSEC_SWLOCKx_SWLOCK2_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SWLOCKx_SWLOCK2 BSEC_SWLOCKx_SWLOCK2_Msk /*!< Sticky write lock for shadow register (2+32*x) */ +#define BSEC_SWLOCKx_SWLOCK3_Pos (3UL) +#define BSEC_SWLOCKx_SWLOCK3_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SWLOCKx_SWLOCK3 BSEC_SWLOCKx_SWLOCK3_Msk /*!< Sticky write lock for shadow register (3+32*x) */ +#define BSEC_SWLOCKx_SWLOCK4_Pos (4UL) +#define BSEC_SWLOCKx_SWLOCK4_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SWLOCKx_SWLOCK4 BSEC_SWLOCKx_SWLOCK4_Msk /*!< Sticky write lock for shadow register (4+32*x) */ +#define BSEC_SWLOCKx_SWLOCK5_Pos (5UL) +#define BSEC_SWLOCKx_SWLOCK5_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SWLOCKx_SWLOCK5 BSEC_SWLOCKx_SWLOCK5_Msk /*!< Sticky write lock for shadow register (5+32*x) */ +#define BSEC_SWLOCKx_SWLOCK6_Pos (6UL) +#define BSEC_SWLOCKx_SWLOCK6_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SWLOCKx_SWLOCK6 BSEC_SWLOCKx_SWLOCK6_Msk /*!< Sticky write lock for shadow register (6+32*x) */ +#define BSEC_SWLOCKx_SWLOCK7_Pos (7UL) +#define BSEC_SWLOCKx_SWLOCK7_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SWLOCKx_SWLOCK7 BSEC_SWLOCKx_SWLOCK7_Msk /*!< Sticky write lock for shadow register (7+32*x) */ +#define BSEC_SWLOCKx_SWLOCK8_Pos (8UL) +#define BSEC_SWLOCKx_SWLOCK8_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SWLOCKx_SWLOCK8 BSEC_SWLOCKx_SWLOCK8_Msk /*!< Sticky write lock for shadow register (8+32*x) */ +#define BSEC_SWLOCKx_SWLOCK9_Pos (9UL) +#define BSEC_SWLOCKx_SWLOCK9_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SWLOCKx_SWLOCK9 BSEC_SWLOCKx_SWLOCK9_Msk /*!< Sticky write lock for shadow register (9+32*x) */ +#define BSEC_SWLOCKx_SWLOCK10_Pos (10UL) +#define BSEC_SWLOCKx_SWLOCK10_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SWLOCKx_SWLOCK10 BSEC_SWLOCKx_SWLOCK10_Msk /*!< Sticky write lock for shadow register (10+32*x) */ +#define BSEC_SWLOCKx_SWLOCK11_Pos (11UL) +#define BSEC_SWLOCKx_SWLOCK11_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SWLOCKx_SWLOCK11 BSEC_SWLOCKx_SWLOCK11_Msk /*!< Sticky write lock for shadow register (11+32*x) */ +#define BSEC_SWLOCKx_SWLOCK12_Pos (12UL) +#define BSEC_SWLOCKx_SWLOCK12_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SWLOCKx_SWLOCK12 BSEC_SWLOCKx_SWLOCK12_Msk /*!< Sticky write lock for shadow register (12+32*x) */ +#define BSEC_SWLOCKx_SWLOCK13_Pos (13UL) +#define BSEC_SWLOCKx_SWLOCK13_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SWLOCKx_SWLOCK13 BSEC_SWLOCKx_SWLOCK13_Msk /*!< Sticky write lock for shadow register (13+32*x) */ +#define BSEC_SWLOCKx_SWLOCK14_Pos (14UL) +#define BSEC_SWLOCKx_SWLOCK14_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SWLOCKx_SWLOCK14 BSEC_SWLOCKx_SWLOCK14_Msk /*!< Sticky write lock for shadow register (14+32*x) */ +#define BSEC_SWLOCKx_SWLOCK15_Pos (15UL) +#define BSEC_SWLOCKx_SWLOCK15_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SWLOCKx_SWLOCK15 BSEC_SWLOCKx_SWLOCK15_Msk /*!< Sticky write lock for shadow register (15+32*x) */ +#define BSEC_SWLOCKx_SWLOCK16_Pos (16UL) +#define BSEC_SWLOCKx_SWLOCK16_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SWLOCKx_SWLOCK16 BSEC_SWLOCKx_SWLOCK16_Msk /*!< Sticky write lock for shadow register (16+32*x) */ +#define BSEC_SWLOCKx_SWLOCK17_Pos (17UL) +#define BSEC_SWLOCKx_SWLOCK17_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SWLOCKx_SWLOCK17 BSEC_SWLOCKx_SWLOCK17_Msk /*!< Sticky write lock for shadow register (17+32*x) */ +#define BSEC_SWLOCKx_SWLOCK18_Pos (18UL) +#define BSEC_SWLOCKx_SWLOCK18_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SWLOCKx_SWLOCK18 BSEC_SWLOCKx_SWLOCK18_Msk /*!< Sticky write lock for shadow register (18+32*x) */ +#define BSEC_SWLOCKx_SWLOCK19_Pos (19UL) +#define BSEC_SWLOCKx_SWLOCK19_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SWLOCKx_SWLOCK19 BSEC_SWLOCKx_SWLOCK19_Msk /*!< Sticky write lock for shadow register (19+32*x) */ +#define BSEC_SWLOCKx_SWLOCK20_Pos (20UL) +#define BSEC_SWLOCKx_SWLOCK20_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SWLOCKx_SWLOCK20 BSEC_SWLOCKx_SWLOCK20_Msk /*!< Sticky write lock for shadow register (20+32*x) */ +#define BSEC_SWLOCKx_SWLOCK21_Pos (21UL) +#define BSEC_SWLOCKx_SWLOCK21_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SWLOCKx_SWLOCK21 BSEC_SWLOCKx_SWLOCK21_Msk /*!< Sticky write lock for shadow register (21+32*x) */ +#define BSEC_SWLOCKx_SWLOCK22_Pos (22UL) +#define BSEC_SWLOCKx_SWLOCK22_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SWLOCKx_SWLOCK22 BSEC_SWLOCKx_SWLOCK22_Msk /*!< Sticky write lock for shadow register (22+32*x) */ +#define BSEC_SWLOCKx_SWLOCK23_Pos (23UL) +#define BSEC_SWLOCKx_SWLOCK23_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SWLOCKx_SWLOCK23 BSEC_SWLOCKx_SWLOCK23_Msk /*!< Sticky write lock for shadow register (23+32*x) */ +#define BSEC_SWLOCKx_SWLOCK24_Pos (24UL) +#define BSEC_SWLOCKx_SWLOCK24_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SWLOCKx_SWLOCK24 BSEC_SWLOCKx_SWLOCK24_Msk /*!< Sticky write lock for shadow register (24+32*x) */ +#define BSEC_SWLOCKx_SWLOCK25_Pos (25UL) +#define BSEC_SWLOCKx_SWLOCK25_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SWLOCKx_SWLOCK25 BSEC_SWLOCKx_SWLOCK25_Msk /*!< Sticky write lock for shadow register (25+32*x) */ +#define BSEC_SWLOCKx_SWLOCK26_Pos (26UL) +#define BSEC_SWLOCKx_SWLOCK26_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SWLOCKx_SWLOCK26 BSEC_SWLOCKx_SWLOCK26_Msk /*!< Sticky write lock for shadow register (26+32*x) */ +#define BSEC_SWLOCKx_SWLOCK27_Pos (27UL) +#define BSEC_SWLOCKx_SWLOCK27_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SWLOCKx_SWLOCK27 BSEC_SWLOCKx_SWLOCK27_Msk /*!< Sticky write lock for shadow register (27+32*x) */ +#define BSEC_SWLOCKx_SWLOCK28_Pos (28UL) +#define BSEC_SWLOCKx_SWLOCK28_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SWLOCKx_SWLOCK28 BSEC_SWLOCKx_SWLOCK28_Msk /*!< Sticky write lock for shadow register (28+32*x) */ +#define BSEC_SWLOCKx_SWLOCK29_Pos (29UL) +#define BSEC_SWLOCKx_SWLOCK29_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SWLOCKx_SWLOCK29 BSEC_SWLOCKx_SWLOCK29_Msk /*!< Sticky write lock for shadow register (29+32*x) */ +#define BSEC_SWLOCKx_SWLOCK30_Pos (30UL) +#define BSEC_SWLOCKx_SWLOCK30_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SWLOCKx_SWLOCK30 BSEC_SWLOCKx_SWLOCK30_Msk /*!< Sticky write lock for shadow register (30+32*x) */ +#define BSEC_SWLOCKx_SWLOCK31_Pos (31UL) +#define BSEC_SWLOCKx_SWLOCK31_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SWLOCKx_SWLOCK31 BSEC_SWLOCKx_SWLOCK31_Msk /*!< Sticky write lock for shadow register (31+32*x) */ + +/***************** Bit definition for BSEC_SRLOCKx register *****************/ +#define BSEC_SRLOCKx_SRLOCK0_Pos (0UL) +#define BSEC_SRLOCKx_SRLOCK0_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos) /*!< 0x00000001 */ +#define BSEC_SRLOCKx_SRLOCK0 BSEC_SRLOCKx_SRLOCK0_Msk /*!< Sticky reload lock for fuse word (32*x) */ +#define BSEC_SRLOCKx_SRLOCK1_Pos (1UL) +#define BSEC_SRLOCKx_SRLOCK1_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos) /*!< 0x00000002 */ +#define BSEC_SRLOCKx_SRLOCK1 BSEC_SRLOCKx_SRLOCK1_Msk /*!< Sticky reload lock for fuse word (1+32*x) */ +#define BSEC_SRLOCKx_SRLOCK2_Pos (2UL) +#define BSEC_SRLOCKx_SRLOCK2_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos) /*!< 0x00000004 */ +#define BSEC_SRLOCKx_SRLOCK2 BSEC_SRLOCKx_SRLOCK2_Msk /*!< Sticky reload lock for fuse word (2+32*x) */ +#define BSEC_SRLOCKx_SRLOCK3_Pos (3UL) +#define BSEC_SRLOCKx_SRLOCK3_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos) /*!< 0x00000008 */ +#define BSEC_SRLOCKx_SRLOCK3 BSEC_SRLOCKx_SRLOCK3_Msk /*!< Sticky reload lock for fuse word (3+32*x) */ +#define BSEC_SRLOCKx_SRLOCK4_Pos (4UL) +#define BSEC_SRLOCKx_SRLOCK4_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos) /*!< 0x00000010 */ +#define BSEC_SRLOCKx_SRLOCK4 BSEC_SRLOCKx_SRLOCK4_Msk /*!< Sticky reload lock for fuse word (4+32*x) */ +#define BSEC_SRLOCKx_SRLOCK5_Pos (5UL) +#define BSEC_SRLOCKx_SRLOCK5_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos) /*!< 0x00000020 */ +#define BSEC_SRLOCKx_SRLOCK5 BSEC_SRLOCKx_SRLOCK5_Msk /*!< Sticky reload lock for fuse word (5+32*x) */ +#define BSEC_SRLOCKx_SRLOCK6_Pos (6UL) +#define BSEC_SRLOCKx_SRLOCK6_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos) /*!< 0x00000040 */ +#define BSEC_SRLOCKx_SRLOCK6 BSEC_SRLOCKx_SRLOCK6_Msk /*!< Sticky reload lock for fuse word (6+32*x) */ +#define BSEC_SRLOCKx_SRLOCK7_Pos (7UL) +#define BSEC_SRLOCKx_SRLOCK7_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos) /*!< 0x00000080 */ +#define BSEC_SRLOCKx_SRLOCK7 BSEC_SRLOCKx_SRLOCK7_Msk /*!< Sticky reload lock for fuse word (7+32*x) */ +#define BSEC_SRLOCKx_SRLOCK8_Pos (8UL) +#define BSEC_SRLOCKx_SRLOCK8_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos) /*!< 0x00000100 */ +#define BSEC_SRLOCKx_SRLOCK8 BSEC_SRLOCKx_SRLOCK8_Msk /*!< Sticky reload lock for fuse word (8+32*x) */ +#define BSEC_SRLOCKx_SRLOCK9_Pos (9UL) +#define BSEC_SRLOCKx_SRLOCK9_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos) /*!< 0x00000200 */ +#define BSEC_SRLOCKx_SRLOCK9 BSEC_SRLOCKx_SRLOCK9_Msk /*!< Sticky reload lock for fuse word (9+32*x) */ +#define BSEC_SRLOCKx_SRLOCK10_Pos (10UL) +#define BSEC_SRLOCKx_SRLOCK10_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos) /*!< 0x00000400 */ +#define BSEC_SRLOCKx_SRLOCK10 BSEC_SRLOCKx_SRLOCK10_Msk /*!< Sticky reload lock for fuse word (10+2*x) */ +#define BSEC_SRLOCKx_SRLOCK11_Pos (11UL) +#define BSEC_SRLOCKx_SRLOCK11_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos) /*!< 0x00000800 */ +#define BSEC_SRLOCKx_SRLOCK11 BSEC_SRLOCKx_SRLOCK11_Msk /*!< Sticky reload lock for fuse word (11+32*x) */ +#define BSEC_SRLOCKx_SRLOCK12_Pos (12UL) +#define BSEC_SRLOCKx_SRLOCK12_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos) /*!< 0x00001000 */ +#define BSEC_SRLOCKx_SRLOCK12 BSEC_SRLOCKx_SRLOCK12_Msk /*!< Sticky reload lock for fuse word (12+32*x) */ +#define BSEC_SRLOCKx_SRLOCK13_Pos (13UL) +#define BSEC_SRLOCKx_SRLOCK13_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos) /*!< 0x00002000 */ +#define BSEC_SRLOCKx_SRLOCK13 BSEC_SRLOCKx_SRLOCK13_Msk /*!< Sticky reload lock for fuse word (13+32*x) */ +#define BSEC_SRLOCKx_SRLOCK14_Pos (14UL) +#define BSEC_SRLOCKx_SRLOCK14_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos) /*!< 0x00004000 */ +#define BSEC_SRLOCKx_SRLOCK14 BSEC_SRLOCKx_SRLOCK14_Msk /*!< Sticky reload lock for fuse word (14+32*x) */ +#define BSEC_SRLOCKx_SRLOCK15_Pos (15UL) +#define BSEC_SRLOCKx_SRLOCK15_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos) /*!< 0x00008000 */ +#define BSEC_SRLOCKx_SRLOCK15 BSEC_SRLOCKx_SRLOCK15_Msk /*!< Sticky reload lock for fuse word (15+32*x) */ +#define BSEC_SRLOCKx_SRLOCK16_Pos (16UL) +#define BSEC_SRLOCKx_SRLOCK16_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos) /*!< 0x00010000 */ +#define BSEC_SRLOCKx_SRLOCK16 BSEC_SRLOCKx_SRLOCK16_Msk /*!< Sticky reload lock for fuse word (16+32*x) */ +#define BSEC_SRLOCKx_SRLOCK17_Pos (17UL) +#define BSEC_SRLOCKx_SRLOCK17_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos) /*!< 0x00020000 */ +#define BSEC_SRLOCKx_SRLOCK17 BSEC_SRLOCKx_SRLOCK17_Msk /*!< Sticky reload lock for fuse word (17+32*x) */ +#define BSEC_SRLOCKx_SRLOCK18_Pos (18UL) +#define BSEC_SRLOCKx_SRLOCK18_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos) /*!< 0x00040000 */ +#define BSEC_SRLOCKx_SRLOCK18 BSEC_SRLOCKx_SRLOCK18_Msk /*!< Sticky reload lock for fuse word (18+32*x) */ +#define BSEC_SRLOCKx_SRLOCK19_Pos (19UL) +#define BSEC_SRLOCKx_SRLOCK19_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos) /*!< 0x00080000 */ +#define BSEC_SRLOCKx_SRLOCK19 BSEC_SRLOCKx_SRLOCK19_Msk /*!< Sticky reload lock for fuse word (19+32*x) */ +#define BSEC_SRLOCKx_SRLOCK20_Pos (20UL) +#define BSEC_SRLOCKx_SRLOCK20_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos) /*!< 0x00100000 */ +#define BSEC_SRLOCKx_SRLOCK20 BSEC_SRLOCKx_SRLOCK20_Msk /*!< Sticky reload lock for fuse word (20+32*x) */ +#define BSEC_SRLOCKx_SRLOCK21_Pos (21UL) +#define BSEC_SRLOCKx_SRLOCK21_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos) /*!< 0x00200000 */ +#define BSEC_SRLOCKx_SRLOCK21 BSEC_SRLOCKx_SRLOCK21_Msk /*!< Sticky reload lock for fuse word (21+32*x) */ +#define BSEC_SRLOCKx_SRLOCK22_Pos (22UL) +#define BSEC_SRLOCKx_SRLOCK22_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos) /*!< 0x00400000 */ +#define BSEC_SRLOCKx_SRLOCK22 BSEC_SRLOCKx_SRLOCK22_Msk /*!< Sticky reload lock for fuse word (22+32*x) */ +#define BSEC_SRLOCKx_SRLOCK23_Pos (23UL) +#define BSEC_SRLOCKx_SRLOCK23_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos) /*!< 0x00800000 */ +#define BSEC_SRLOCKx_SRLOCK23 BSEC_SRLOCKx_SRLOCK23_Msk /*!< Sticky reload lock for fuse word (23+32*x) */ +#define BSEC_SRLOCKx_SRLOCK24_Pos (24UL) +#define BSEC_SRLOCKx_SRLOCK24_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos) /*!< 0x01000000 */ +#define BSEC_SRLOCKx_SRLOCK24 BSEC_SRLOCKx_SRLOCK24_Msk /*!< Sticky reload lock for fuse word (24+32*x) */ +#define BSEC_SRLOCKx_SRLOCK25_Pos (25UL) +#define BSEC_SRLOCKx_SRLOCK25_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos) /*!< 0x02000000 */ +#define BSEC_SRLOCKx_SRLOCK25 BSEC_SRLOCKx_SRLOCK25_Msk /*!< Sticky reload lock for fuse word (25+32*x) */ +#define BSEC_SRLOCKx_SRLOCK26_Pos (26UL) +#define BSEC_SRLOCKx_SRLOCK26_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos) /*!< 0x04000000 */ +#define BSEC_SRLOCKx_SRLOCK26 BSEC_SRLOCKx_SRLOCK26_Msk /*!< Sticky reload lock for fuse word (26+32*x) */ +#define BSEC_SRLOCKx_SRLOCK27_Pos (27UL) +#define BSEC_SRLOCKx_SRLOCK27_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos) /*!< 0x08000000 */ +#define BSEC_SRLOCKx_SRLOCK27 BSEC_SRLOCKx_SRLOCK27_Msk /*!< Sticky reload lock for fuse word (27+32*x) */ +#define BSEC_SRLOCKx_SRLOCK28_Pos (28UL) +#define BSEC_SRLOCKx_SRLOCK28_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos) /*!< 0x10000000 */ +#define BSEC_SRLOCKx_SRLOCK28 BSEC_SRLOCKx_SRLOCK28_Msk /*!< Sticky reload lock for fuse word (28+32*x) */ +#define BSEC_SRLOCKx_SRLOCK29_Pos (29UL) +#define BSEC_SRLOCKx_SRLOCK29_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos) /*!< 0x20000000 */ +#define BSEC_SRLOCKx_SRLOCK29 BSEC_SRLOCKx_SRLOCK29_Msk /*!< Sticky reload lock for fuse word (29+32*x) */ +#define BSEC_SRLOCKx_SRLOCK30_Pos (30UL) +#define BSEC_SRLOCKx_SRLOCK30_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos) /*!< 0x40000000 */ +#define BSEC_SRLOCKx_SRLOCK30 BSEC_SRLOCKx_SRLOCK30_Msk /*!< Sticky reload lock for fuse word (30+32*x) */ +#define BSEC_SRLOCKx_SRLOCK31_Pos (31UL) +#define BSEC_SRLOCKx_SRLOCK31_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos) /*!< 0x80000000 */ +#define BSEC_SRLOCKx_SRLOCK31 BSEC_SRLOCKx_SRLOCK31_Msk /*!< Sticky reload lock for fuse word (31+32*x) */ + +/**************** Bit definition for BSEC_OTPVLDRx register *****************/ +#define BSEC_OTPVLDRx_VLDF0_Pos (0UL) +#define BSEC_OTPVLDRx_VLDF0_Msk (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos) /*!< 0x00000001 */ +#define BSEC_OTPVLDRx_VLDF0 BSEC_OTPVLDRx_VLDF0_Msk /*!< Valid flag for shadow register (32*x) */ +#define BSEC_OTPVLDRx_VLDF1_Pos (1UL) +#define BSEC_OTPVLDRx_VLDF1_Msk (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos) /*!< 0x00000002 */ +#define BSEC_OTPVLDRx_VLDF1 BSEC_OTPVLDRx_VLDF1_Msk /*!< Valid flag for shadow register (1+32*x) */ +#define BSEC_OTPVLDRx_VLDF2_Pos (2UL) +#define BSEC_OTPVLDRx_VLDF2_Msk (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos) /*!< 0x00000004 */ +#define BSEC_OTPVLDRx_VLDF2 BSEC_OTPVLDRx_VLDF2_Msk /*!< Valid flag for shadow register (2+32*x) */ +#define BSEC_OTPVLDRx_VLDF3_Pos (3UL) +#define BSEC_OTPVLDRx_VLDF3_Msk (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos) /*!< 0x00000008 */ +#define BSEC_OTPVLDRx_VLDF3 BSEC_OTPVLDRx_VLDF3_Msk /*!< Valid flag for shadow register (3+32*x) */ +#define BSEC_OTPVLDRx_VLDF4_Pos (4UL) +#define BSEC_OTPVLDRx_VLDF4_Msk (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos) /*!< 0x00000010 */ +#define BSEC_OTPVLDRx_VLDF4 BSEC_OTPVLDRx_VLDF4_Msk /*!< Valid flag for shadow register (4+32*x) */ +#define BSEC_OTPVLDRx_VLDF5_Pos (5UL) +#define BSEC_OTPVLDRx_VLDF5_Msk (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos) /*!< 0x00000020 */ +#define BSEC_OTPVLDRx_VLDF5 BSEC_OTPVLDRx_VLDF5_Msk /*!< Valid flag for shadow register (5+32*x) */ +#define BSEC_OTPVLDRx_VLDF6_Pos (6UL) +#define BSEC_OTPVLDRx_VLDF6_Msk (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos) /*!< 0x00000040 */ +#define BSEC_OTPVLDRx_VLDF6 BSEC_OTPVLDRx_VLDF6_Msk /*!< Valid flag for shadow register (6+32*x) */ +#define BSEC_OTPVLDRx_VLDF7_Pos (7UL) +#define BSEC_OTPVLDRx_VLDF7_Msk (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos) /*!< 0x00000080 */ +#define BSEC_OTPVLDRx_VLDF7 BSEC_OTPVLDRx_VLDF7_Msk /*!< Valid flag for shadow register (7+32*x) */ +#define BSEC_OTPVLDRx_VLDF8_Pos (8UL) +#define BSEC_OTPVLDRx_VLDF8_Msk (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos) /*!< 0x00000100 */ +#define BSEC_OTPVLDRx_VLDF8 BSEC_OTPVLDRx_VLDF8_Msk /*!< Valid flag for shadow register (8+32*x) */ +#define BSEC_OTPVLDRx_VLDF9_Pos (9UL) +#define BSEC_OTPVLDRx_VLDF9_Msk (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos) /*!< 0x00000200 */ +#define BSEC_OTPVLDRx_VLDF9 BSEC_OTPVLDRx_VLDF9_Msk /*!< Valid flag for shadow register (9+32*x) */ +#define BSEC_OTPVLDRx_VLDF10_Pos (10UL) +#define BSEC_OTPVLDRx_VLDF10_Msk (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos) /*!< 0x00000400 */ +#define BSEC_OTPVLDRx_VLDF10 BSEC_OTPVLDRx_VLDF10_Msk /*!< Valid flag for shadow register (10+32*x) */ +#define BSEC_OTPVLDRx_VLDF11_Pos (11UL) +#define BSEC_OTPVLDRx_VLDF11_Msk (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos) /*!< 0x00000800 */ +#define BSEC_OTPVLDRx_VLDF11 BSEC_OTPVLDRx_VLDF11_Msk /*!< Valid flag for shadow register (11+32*x) */ +#define BSEC_OTPVLDRx_VLDF12_Pos (12UL) +#define BSEC_OTPVLDRx_VLDF12_Msk (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos) /*!< 0x00001000 */ +#define BSEC_OTPVLDRx_VLDF12 BSEC_OTPVLDRx_VLDF12_Msk /*!< Valid flag for shadow register (12+32*x) */ +#define BSEC_OTPVLDRx_VLDF13_Pos (13UL) +#define BSEC_OTPVLDRx_VLDF13_Msk (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos) /*!< 0x00002000 */ +#define BSEC_OTPVLDRx_VLDF13 BSEC_OTPVLDRx_VLDF13_Msk /*!< Valid flag for shadow register (13+32*x) */ +#define BSEC_OTPVLDRx_VLDF14_Pos (14UL) +#define BSEC_OTPVLDRx_VLDF14_Msk (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos) /*!< 0x00004000 */ +#define BSEC_OTPVLDRx_VLDF14 BSEC_OTPVLDRx_VLDF14_Msk /*!< Valid flag for shadow register (14+32*x) */ +#define BSEC_OTPVLDRx_VLDF15_Pos (15UL) +#define BSEC_OTPVLDRx_VLDF15_Msk (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos) /*!< 0x00008000 */ +#define BSEC_OTPVLDRx_VLDF15 BSEC_OTPVLDRx_VLDF15_Msk /*!< Valid flag for shadow register (15+32*x) */ +#define BSEC_OTPVLDRx_VLDF16_Pos (16UL) +#define BSEC_OTPVLDRx_VLDF16_Msk (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos) /*!< 0x00010000 */ +#define BSEC_OTPVLDRx_VLDF16 BSEC_OTPVLDRx_VLDF16_Msk /*!< Valid flag for shadow register (16+32*x) */ +#define BSEC_OTPVLDRx_VLDF17_Pos (17UL) +#define BSEC_OTPVLDRx_VLDF17_Msk (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos) /*!< 0x00020000 */ +#define BSEC_OTPVLDRx_VLDF17 BSEC_OTPVLDRx_VLDF17_Msk /*!< Valid flag for shadow register (17+32*x) */ +#define BSEC_OTPVLDRx_VLDF18_Pos (18UL) +#define BSEC_OTPVLDRx_VLDF18_Msk (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos) /*!< 0x00040000 */ +#define BSEC_OTPVLDRx_VLDF18 BSEC_OTPVLDRx_VLDF18_Msk /*!< Valid flag for shadow register (18+32*x) */ +#define BSEC_OTPVLDRx_VLDF19_Pos (19UL) +#define BSEC_OTPVLDRx_VLDF19_Msk (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos) /*!< 0x00080000 */ +#define BSEC_OTPVLDRx_VLDF19 BSEC_OTPVLDRx_VLDF19_Msk /*!< Valid flag for shadow register (19+32*x) */ +#define BSEC_OTPVLDRx_VLDF20_Pos (20UL) +#define BSEC_OTPVLDRx_VLDF20_Msk (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos) /*!< 0x00100000 */ +#define BSEC_OTPVLDRx_VLDF20 BSEC_OTPVLDRx_VLDF20_Msk /*!< Valid flag for shadow register (20+32*x) */ +#define BSEC_OTPVLDRx_VLDF21_Pos (21UL) +#define BSEC_OTPVLDRx_VLDF21_Msk (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos) /*!< 0x00200000 */ +#define BSEC_OTPVLDRx_VLDF21 BSEC_OTPVLDRx_VLDF21_Msk /*!< Valid flag for shadow register (21+32*x) */ +#define BSEC_OTPVLDRx_VLDF22_Pos (22UL) +#define BSEC_OTPVLDRx_VLDF22_Msk (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos) /*!< 0x00400000 */ +#define BSEC_OTPVLDRx_VLDF22 BSEC_OTPVLDRx_VLDF22_Msk /*!< Valid flag for shadow register (22+32*x) */ +#define BSEC_OTPVLDRx_VLDF23_Pos (23UL) +#define BSEC_OTPVLDRx_VLDF23_Msk (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos) /*!< 0x00800000 */ +#define BSEC_OTPVLDRx_VLDF23 BSEC_OTPVLDRx_VLDF23_Msk /*!< Valid flag for shadow register (23+32*x) */ +#define BSEC_OTPVLDRx_VLDF24_Pos (24UL) +#define BSEC_OTPVLDRx_VLDF24_Msk (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos) /*!< 0x01000000 */ +#define BSEC_OTPVLDRx_VLDF24 BSEC_OTPVLDRx_VLDF24_Msk /*!< Valid flag for shadow register (24+32*x) */ +#define BSEC_OTPVLDRx_VLDF25_Pos (25UL) +#define BSEC_OTPVLDRx_VLDF25_Msk (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos) /*!< 0x02000000 */ +#define BSEC_OTPVLDRx_VLDF25 BSEC_OTPVLDRx_VLDF25_Msk /*!< Valid flag for shadow register (25+32*x) */ +#define BSEC_OTPVLDRx_VLDF26_Pos (26UL) +#define BSEC_OTPVLDRx_VLDF26_Msk (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos) /*!< 0x04000000 */ +#define BSEC_OTPVLDRx_VLDF26 BSEC_OTPVLDRx_VLDF26_Msk /*!< Valid flag for shadow register (26+32*x) */ +#define BSEC_OTPVLDRx_VLDF27_Pos (27UL) +#define BSEC_OTPVLDRx_VLDF27_Msk (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos) /*!< 0x08000000 */ +#define BSEC_OTPVLDRx_VLDF27 BSEC_OTPVLDRx_VLDF27_Msk /*!< Valid flag for shadow register (27+32*x) */ +#define BSEC_OTPVLDRx_VLDF28_Pos (28UL) +#define BSEC_OTPVLDRx_VLDF28_Msk (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos) /*!< 0x10000000 */ +#define BSEC_OTPVLDRx_VLDF28 BSEC_OTPVLDRx_VLDF28_Msk /*!< Valid flag for shadow register (28+32*x) */ +#define BSEC_OTPVLDRx_VLDF29_Pos (29UL) +#define BSEC_OTPVLDRx_VLDF29_Msk (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos) /*!< 0x20000000 */ +#define BSEC_OTPVLDRx_VLDF29 BSEC_OTPVLDRx_VLDF29_Msk /*!< Valid flag for shadow register (29+32*x) */ +#define BSEC_OTPVLDRx_VLDF30_Pos (30UL) +#define BSEC_OTPVLDRx_VLDF30_Msk (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos) /*!< 0x40000000 */ +#define BSEC_OTPVLDRx_VLDF30 BSEC_OTPVLDRx_VLDF30_Msk /*!< Valid flag for shadow register (30+32*x) */ +#define BSEC_OTPVLDRx_VLDF31_Pos (31UL) +#define BSEC_OTPVLDRx_VLDF31_Msk (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos) /*!< 0x80000000 */ +#define BSEC_OTPVLDRx_VLDF31 BSEC_OTPVLDRx_VLDF31_Msk /*!< Valid flag for shadow register (31+32*x) */ + +/****************** Bit definition for BSEC_SFSRx register ******************/ +#define BSEC_SFSRx_SFW0_Pos (0UL) +#define BSEC_SFSRx_SFW0_Msk (0x1UL << BSEC_SFSRx_SFW0_Pos) /*!< 0x00000001 */ +#define BSEC_SFSRx_SFW0 BSEC_SFSRx_SFW0_Msk /*!< Shadowed fuse word (32*x) */ +#define BSEC_SFSRx_SFW1_Pos (1UL) +#define BSEC_SFSRx_SFW1_Msk (0x1UL << BSEC_SFSRx_SFW1_Pos) /*!< 0x00000002 */ +#define BSEC_SFSRx_SFW1 BSEC_SFSRx_SFW1_Msk /*!< Shadowed fuse word (1+32*x) */ +#define BSEC_SFSRx_SFW2_Pos (2UL) +#define BSEC_SFSRx_SFW2_Msk (0x1UL << BSEC_SFSRx_SFW2_Pos) /*!< 0x00000004 */ +#define BSEC_SFSRx_SFW2 BSEC_SFSRx_SFW2_Msk /*!< Shadowed fuse word (2+32*x) */ +#define BSEC_SFSRx_SFW3_Pos (3UL) +#define BSEC_SFSRx_SFW3_Msk (0x1UL << BSEC_SFSRx_SFW3_Pos) /*!< 0x00000008 */ +#define BSEC_SFSRx_SFW3 BSEC_SFSRx_SFW3_Msk /*!< Shadowed fuse word (3+32*x) */ +#define BSEC_SFSRx_SFW4_Pos (4UL) +#define BSEC_SFSRx_SFW4_Msk (0x1UL << BSEC_SFSRx_SFW4_Pos) /*!< 0x00000010 */ +#define BSEC_SFSRx_SFW4 BSEC_SFSRx_SFW4_Msk /*!< Shadowed fuse word (4+32*x) */ +#define BSEC_SFSRx_SFW5_Pos (5UL) +#define BSEC_SFSRx_SFW5_Msk (0x1UL << BSEC_SFSRx_SFW5_Pos) /*!< 0x00000020 */ +#define BSEC_SFSRx_SFW5 BSEC_SFSRx_SFW5_Msk /*!< Shadowed fuse word (5+32*x) */ +#define BSEC_SFSRx_SFW6_Pos (6UL) +#define BSEC_SFSRx_SFW6_Msk (0x1UL << BSEC_SFSRx_SFW6_Pos) /*!< 0x00000040 */ +#define BSEC_SFSRx_SFW6 BSEC_SFSRx_SFW6_Msk /*!< Shadowed fuse word (6+32*x) */ +#define BSEC_SFSRx_SFW7_Pos (7UL) +#define BSEC_SFSRx_SFW7_Msk (0x1UL << BSEC_SFSRx_SFW7_Pos) /*!< 0x00000080 */ +#define BSEC_SFSRx_SFW7 BSEC_SFSRx_SFW7_Msk /*!< Shadowed fuse word (7+32*x) */ +#define BSEC_SFSRx_SFW8_Pos (8UL) +#define BSEC_SFSRx_SFW8_Msk (0x1UL << BSEC_SFSRx_SFW8_Pos) /*!< 0x00000100 */ +#define BSEC_SFSRx_SFW8 BSEC_SFSRx_SFW8_Msk /*!< Shadowed fuse word (8+32*x) */ +#define BSEC_SFSRx_SFW9_Pos (9UL) +#define BSEC_SFSRx_SFW9_Msk (0x1UL << BSEC_SFSRx_SFW9_Pos) /*!< 0x00000200 */ +#define BSEC_SFSRx_SFW9 BSEC_SFSRx_SFW9_Msk /*!< Shadowed fuse word (9+32*x) */ +#define BSEC_SFSRx_SFW10_Pos (10UL) +#define BSEC_SFSRx_SFW10_Msk (0x1UL << BSEC_SFSRx_SFW10_Pos) /*!< 0x00000400 */ +#define BSEC_SFSRx_SFW10 BSEC_SFSRx_SFW10_Msk /*!< Shadowed fuse word (10+32*x) */ +#define BSEC_SFSRx_SFW11_Pos (11UL) +#define BSEC_SFSRx_SFW11_Msk (0x1UL << BSEC_SFSRx_SFW11_Pos) /*!< 0x00000800 */ +#define BSEC_SFSRx_SFW11 BSEC_SFSRx_SFW11_Msk /*!< Shadowed fuse word (11+32*x) */ +#define BSEC_SFSRx_SFW12_Pos (12UL) +#define BSEC_SFSRx_SFW12_Msk (0x1UL << BSEC_SFSRx_SFW12_Pos) /*!< 0x00001000 */ +#define BSEC_SFSRx_SFW12 BSEC_SFSRx_SFW12_Msk /*!< Shadowed fuse word (12+32*x) */ +#define BSEC_SFSRx_SFW13_Pos (13UL) +#define BSEC_SFSRx_SFW13_Msk (0x1UL << BSEC_SFSRx_SFW13_Pos) /*!< 0x00002000 */ +#define BSEC_SFSRx_SFW13 BSEC_SFSRx_SFW13_Msk /*!< Shadowed fuse word (13+32*x) */ +#define BSEC_SFSRx_SFW14_Pos (14UL) +#define BSEC_SFSRx_SFW14_Msk (0x1UL << BSEC_SFSRx_SFW14_Pos) /*!< 0x00004000 */ +#define BSEC_SFSRx_SFW14 BSEC_SFSRx_SFW14_Msk /*!< Shadowed fuse word (14+32*x) */ +#define BSEC_SFSRx_SFW15_Pos (15UL) +#define BSEC_SFSRx_SFW15_Msk (0x1UL << BSEC_SFSRx_SFW15_Pos) /*!< 0x00008000 */ +#define BSEC_SFSRx_SFW15 BSEC_SFSRx_SFW15_Msk /*!< Shadowed fuse word (15+32*x) */ +#define BSEC_SFSRx_SFW16_Pos (16UL) +#define BSEC_SFSRx_SFW16_Msk (0x1UL << BSEC_SFSRx_SFW16_Pos) /*!< 0x00010000 */ +#define BSEC_SFSRx_SFW16 BSEC_SFSRx_SFW16_Msk /*!< Shadowed fuse word (16+32*x) */ +#define BSEC_SFSRx_SFW17_Pos (17UL) +#define BSEC_SFSRx_SFW17_Msk (0x1UL << BSEC_SFSRx_SFW17_Pos) /*!< 0x00020000 */ +#define BSEC_SFSRx_SFW17 BSEC_SFSRx_SFW17_Msk /*!< Shadowed fuse word (17+32*x) */ +#define BSEC_SFSRx_SFW18_Pos (18UL) +#define BSEC_SFSRx_SFW18_Msk (0x1UL << BSEC_SFSRx_SFW18_Pos) /*!< 0x00040000 */ +#define BSEC_SFSRx_SFW18 BSEC_SFSRx_SFW18_Msk /*!< Shadowed fuse word (18+32*x) */ +#define BSEC_SFSRx_SFW19_Pos (19UL) +#define BSEC_SFSRx_SFW19_Msk (0x1UL << BSEC_SFSRx_SFW19_Pos) /*!< 0x00080000 */ +#define BSEC_SFSRx_SFW19 BSEC_SFSRx_SFW19_Msk /*!< Shadowed fuse word (19+32*x) */ +#define BSEC_SFSRx_SFW20_Pos (20UL) +#define BSEC_SFSRx_SFW20_Msk (0x1UL << BSEC_SFSRx_SFW20_Pos) /*!< 0x00100000 */ +#define BSEC_SFSRx_SFW20 BSEC_SFSRx_SFW20_Msk /*!< Shadowed fuse word (20+32*x) */ +#define BSEC_SFSRx_SFW21_Pos (21UL) +#define BSEC_SFSRx_SFW21_Msk (0x1UL << BSEC_SFSRx_SFW21_Pos) /*!< 0x00200000 */ +#define BSEC_SFSRx_SFW21 BSEC_SFSRx_SFW21_Msk /*!< Shadowed fuse word (21+32*x) */ +#define BSEC_SFSRx_SFW22_Pos (22UL) +#define BSEC_SFSRx_SFW22_Msk (0x1UL << BSEC_SFSRx_SFW22_Pos) /*!< 0x00400000 */ +#define BSEC_SFSRx_SFW22 BSEC_SFSRx_SFW22_Msk /*!< Shadowed fuse word (22+32*x) */ +#define BSEC_SFSRx_SFW23_Pos (23UL) +#define BSEC_SFSRx_SFW23_Msk (0x1UL << BSEC_SFSRx_SFW23_Pos) /*!< 0x00800000 */ +#define BSEC_SFSRx_SFW23 BSEC_SFSRx_SFW23_Msk /*!< Shadowed fuse word (23+32*x) */ +#define BSEC_SFSRx_SFW24_Pos (24UL) +#define BSEC_SFSRx_SFW24_Msk (0x1UL << BSEC_SFSRx_SFW24_Pos) /*!< 0x01000000 */ +#define BSEC_SFSRx_SFW24 BSEC_SFSRx_SFW24_Msk /*!< Shadowed fuse word (24+32*x) */ +#define BSEC_SFSRx_SFW25_Pos (25UL) +#define BSEC_SFSRx_SFW25_Msk (0x1UL << BSEC_SFSRx_SFW25_Pos) /*!< 0x02000000 */ +#define BSEC_SFSRx_SFW25 BSEC_SFSRx_SFW25_Msk /*!< Shadowed fuse word (25+32*x) */ +#define BSEC_SFSRx_SFW26_Pos (26UL) +#define BSEC_SFSRx_SFW26_Msk (0x1UL << BSEC_SFSRx_SFW26_Pos) /*!< 0x04000000 */ +#define BSEC_SFSRx_SFW26 BSEC_SFSRx_SFW26_Msk /*!< Shadowed fuse word (26+32*x) */ +#define BSEC_SFSRx_SFW27_Pos (27UL) +#define BSEC_SFSRx_SFW27_Msk (0x1UL << BSEC_SFSRx_SFW27_Pos) /*!< 0x08000000 */ +#define BSEC_SFSRx_SFW27 BSEC_SFSRx_SFW27_Msk /*!< Shadowed fuse word (27+32*x) */ +#define BSEC_SFSRx_SFW28_Pos (28UL) +#define BSEC_SFSRx_SFW28_Msk (0x1UL << BSEC_SFSRx_SFW28_Pos) /*!< 0x10000000 */ +#define BSEC_SFSRx_SFW28 BSEC_SFSRx_SFW28_Msk /*!< Shadowed fuse word (28+32*x) */ +#define BSEC_SFSRx_SFW29_Pos (29UL) +#define BSEC_SFSRx_SFW29_Msk (0x1UL << BSEC_SFSRx_SFW29_Pos) /*!< 0x20000000 */ +#define BSEC_SFSRx_SFW29 BSEC_SFSRx_SFW29_Msk /*!< Shadowed fuse word (29+32*x) */ +#define BSEC_SFSRx_SFW30_Pos (30UL) +#define BSEC_SFSRx_SFW30_Msk (0x1UL << BSEC_SFSRx_SFW30_Pos) /*!< 0x40000000 */ +#define BSEC_SFSRx_SFW30 BSEC_SFSRx_SFW30_Msk /*!< Shadowed fuse word (30+32*x) */ +#define BSEC_SFSRx_SFW31_Pos (31UL) +#define BSEC_SFSRx_SFW31_Msk (0x1UL << BSEC_SFSRx_SFW31_Pos) /*!< 0x80000000 */ +#define BSEC_SFSRx_SFW31 BSEC_SFSRx_SFW31_Msk /*!< Shadowed fuse word (31+32*x) */ + +/****************** Bit definition for BSEC_OTPCR register ******************/ +#define BSEC_OTPCR_ADDR_Pos (0UL) +#define BSEC_OTPCR_ADDR_Msk (0x1FFUL << BSEC_OTPCR_ADDR_Pos) /*!< 0x000001FF */ +#define BSEC_OTPCR_ADDR BSEC_OTPCR_ADDR_Msk /*!< Fuse word address */ +#define BSEC_OTPCR_PROG_Pos (13UL) +#define BSEC_OTPCR_PROG_Msk (0x1UL << BSEC_OTPCR_PROG_Pos) /*!< 0x00002000 */ +#define BSEC_OTPCR_PROG BSEC_OTPCR_PROG_Msk /*!< Fuse word programming */ +#define BSEC_OTPCR_PPLOCK_Pos (14UL) +#define BSEC_OTPCR_PPLOCK_Msk (0x1UL << BSEC_OTPCR_PPLOCK_Pos) /*!< 0x00004000 */ +#define BSEC_OTPCR_PPLOCK BSEC_OTPCR_PPLOCK_Msk /*!< Permanent programming lock */ +#define BSEC_OTPCR_LASTCID_Pos (19UL) +#define BSEC_OTPCR_LASTCID_Msk (0x7UL << BSEC_OTPCR_LASTCID_Pos) /*!< 0x00380000 */ +#define BSEC_OTPCR_LASTCID BSEC_OTPCR_LASTCID_Msk /*!< Last CID */ + +/******************* Bit definition for BSEC_WDR register *******************/ +#define BSEC_WDR_WRDATA_Pos (0UL) +#define BSEC_WDR_WRDATA_Msk (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WDR_WRDATA BSEC_WDR_WRDATA_Msk /*!< OTP write data */ + +/**************** Bit definition for BSEC_SCRATCHRx register ****************/ +#define BSEC_SCRATCHRx_SDATA_Pos (0UL) +#define BSEC_SCRATCHRx_SDATA_Msk (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_SCRATCHRx_SDATA BSEC_SCRATCHRx_SDATA_Msk /*!< Scratch data */ + +/****************** Bit definition for BSEC_LOCKR register ******************/ +#define BSEC_LOCKR_GWLOCK_Pos (0UL) +#define BSEC_LOCKR_GWLOCK_Msk (0x1UL << BSEC_LOCKR_GWLOCK_Pos) /*!< 0x00000001 */ +#define BSEC_LOCKR_GWLOCK BSEC_LOCKR_GWLOCK_Msk /*!< Global write lock */ +#define BSEC_LOCKR_HKLOCK_Pos (2UL) +#define BSEC_LOCKR_HKLOCK_Msk (0x1UL << BSEC_LOCKR_HKLOCK_Pos) /*!< 0x00000004 */ +#define BSEC_LOCKR_HKLOCK BSEC_LOCKR_HKLOCK_Msk /*!< Hardware key lock */ + +/***************** Bit definition for BSEC_JTAGINR register *****************/ +#define BSEC_JTAGINR_JDATAIN_Pos (0UL) +#define BSEC_JTAGINR_JDATAIN_Msk (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGINR_JDATAIN BSEC_JTAGINR_JDATAIN_Msk /*!< JTAG input data */ + +/**************** Bit definition for BSEC_JTAGOUTR register *****************/ +#define BSEC_JTAGOUTR_JDATAOUT_Pos (0UL) +#define BSEC_JTAGOUTR_JDATAOUT_Msk (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_JTAGOUTR_JDATAOUT BSEC_JTAGOUTR_JDATAOUT_Msk /*!< JTAG output data */ + +/***************** Bit definition for BSEC_UNMAPR register ******************/ +#define BSEC_UNMAPR_UNMAP_Pos (0UL) +#define BSEC_UNMAPR_UNMAP_Msk (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_UNMAPR_UNMAP BSEC_UNMAPR_UNMAP_Msk /*!< Unmap key */ + +/******************* Bit definition for BSEC_SR register ********************/ +#define BSEC_SR_HVALID_Pos (1UL) +#define BSEC_SR_HVALID_Msk (0x1UL << BSEC_SR_HVALID_Pos) /*!< 0x00000002 */ +#define BSEC_SR_HVALID BSEC_SR_HVALID_Msk /*!< Hardware key valid */ +#define BSEC_SR_DBGREQ_Pos (16UL) +#define BSEC_SR_DBGREQ_Msk (0x1UL << BSEC_SR_DBGREQ_Pos) /*!< 0x00010000 */ +#define BSEC_SR_DBGREQ BSEC_SR_DBGREQ_Msk /*!< Debug request */ +#define BSEC_SR_NVSTATE_Pos (26UL) +#define BSEC_SR_NVSTATE_Msk (0x3FUL << BSEC_SR_NVSTATE_Pos) /*!< 0xFC000000 */ +#define BSEC_SR_NVSTATE BSEC_SR_NVSTATE_Msk /*!< Non-volatile state */ + +/****************** Bit definition for BSEC_OTPSR register ******************/ +#define BSEC_OTPSR_BUSY_Pos (0UL) +#define BSEC_OTPSR_BUSY_Msk (0x1UL << BSEC_OTPSR_BUSY_Pos) /*!< 0x00000001 */ +#define BSEC_OTPSR_BUSY BSEC_OTPSR_BUSY_Msk /*!< Busy flag */ +#define BSEC_OTPSR_INIT_DONE_Pos (1UL) +#define BSEC_OTPSR_INIT_DONE_Msk (0x1UL << BSEC_OTPSR_INIT_DONE_Pos) /*!< 0x00000002 */ +#define BSEC_OTPSR_INIT_DONE BSEC_OTPSR_INIT_DONE_Msk /*!< Initialization done */ +#define BSEC_OTPSR_HIDEUP_Pos (2UL) +#define BSEC_OTPSR_HIDEUP_Msk (0x1UL << BSEC_OTPSR_HIDEUP_Pos) /*!< 0x00000004 */ +#define BSEC_OTPSR_HIDEUP BSEC_OTPSR_HIDEUP_Msk /*!< Hide upper fuse words */ +#define BSEC_OTPSR_OTPNVIR_Pos (4UL) +#define BSEC_OTPSR_OTPNVIR_Msk (0x1UL << BSEC_OTPSR_OTPNVIR_Pos) /*!< 0x00000010 */ +#define BSEC_OTPSR_OTPNVIR BSEC_OTPSR_OTPNVIR_Msk /*!< OTP not virgin */ +#define BSEC_OTPSR_OTPERR_Pos (5UL) +#define BSEC_OTPSR_OTPERR_Msk (0x1UL << BSEC_OTPSR_OTPERR_Pos) /*!< 0x00000020 */ +#define BSEC_OTPSR_OTPERR BSEC_OTPSR_OTPERR_Msk /*!< OTP with error */ +#define BSEC_OTPSR_OTPSEC_Pos (6UL) +#define BSEC_OTPSR_OTPSEC_Msk (0x1UL << BSEC_OTPSR_OTPSEC_Pos) /*!< 0x00000040 */ +#define BSEC_OTPSR_OTPSEC BSEC_OTPSR_OTPSEC_Msk /*!< OTP with single error correction */ +#define BSEC_OTPSR_PROGFAIL_Pos (16UL) +#define BSEC_OTPSR_PROGFAIL_Msk (0x1UL << BSEC_OTPSR_PROGFAIL_Pos) /*!< 0x00010000 */ +#define BSEC_OTPSR_PROGFAIL BSEC_OTPSR_PROGFAIL_Msk /*!< Programming failed */ +#define BSEC_OTPSR_DISTURBF_Pos (17UL) +#define BSEC_OTPSR_DISTURBF_Msk (0x1UL << BSEC_OTPSR_DISTURBF_Pos) /*!< 0x00020000 */ +#define BSEC_OTPSR_DISTURBF BSEC_OTPSR_DISTURBF_Msk /*!< Disturb flag */ +#define BSEC_OTPSR_DEDF_Pos (18UL) +#define BSEC_OTPSR_DEDF_Msk (0x1UL << BSEC_OTPSR_DEDF_Pos) /*!< 0x00040000 */ +#define BSEC_OTPSR_DEDF BSEC_OTPSR_DEDF_Msk /*!< Double error detection flag */ +#define BSEC_OTPSR_SECF_Pos (19UL) +#define BSEC_OTPSR_SECF_Msk (0x1UL << BSEC_OTPSR_SECF_Pos) /*!< 0x00080000 */ +#define BSEC_OTPSR_SECF BSEC_OTPSR_SECF_Msk /*!< Single error correction flag */ +#define BSEC_OTPSR_PPLF_Pos (20UL) +#define BSEC_OTPSR_PPLF_Msk (0x1UL << BSEC_OTPSR_PPLF_Pos) /*!< 0x00100000 */ +#define BSEC_OTPSR_PPLF BSEC_OTPSR_PPLF_Msk /*!< Permanent programming lock flag */ +#define BSEC_OTPSR_PPLMF_Pos (21UL) +#define BSEC_OTPSR_PPLMF_Msk (0x1UL << BSEC_OTPSR_PPLMF_Pos) /*!< 0x00200000 */ +#define BSEC_OTPSR_PPLMF BSEC_OTPSR_PPLMF_Msk /*!< Permanent programming lock mismatch flag */ +#define BSEC_OTPSR_AMEF_Pos (22UL) +#define BSEC_OTPSR_AMEF_Msk (0x1UL << BSEC_OTPSR_AMEF_Pos) /*!< 0x00400000 */ +#define BSEC_OTPSR_AMEF BSEC_OTPSR_AMEF_Msk /*!< Addresses mismatch error flag */ + +/***************** Bit definition for BSEC_EPOCHRx register *****************/ +#define BSEC_EPOCHRx_EPOCH_Pos (0UL) +#define BSEC_EPOCHRx_EPOCH_Msk (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_EPOCHRx_EPOCH BSEC_EPOCHRx_EPOCH_Msk /*!< Epoch */ + +/**************** Bit definition for BSEC_EPOCHSELR register ****************/ +#define BSEC_EPOCHSELR_EPSEL_Pos (0UL) +#define BSEC_EPOCHSELR_EPSEL_Msk (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos) /*!< 0x00000001 */ +#define BSEC_EPOCHSELR_EPSEL BSEC_EPOCHSELR_EPSEL_Msk /*!< Epoch selection */ + +/****************** Bit definition for BSEC_DBGCR register ******************/ +#define BSEC_DBGCR_UNLOCK_Pos (8UL) +#define BSEC_DBGCR_UNLOCK_Msk (0xFFUL << BSEC_DBGCR_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define BSEC_DBGCR_UNLOCK BSEC_DBGCR_UNLOCK_Msk /*!< Non-secure debug authorization */ +#define BSEC_DBGCR_AUTH_HDPL_Pos (16UL) +#define BSEC_DBGCR_AUTH_HDPL_Msk (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define BSEC_DBGCR_AUTH_HDPL BSEC_DBGCR_AUTH_HDPL_Msk /*!< Level at which debug may be opened */ +#define BSEC_DBGCR_AUTH_SEC_Pos (24UL) +#define BSEC_DBGCR_AUTH_SEC_Msk (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define BSEC_DBGCR_AUTH_SEC BSEC_DBGCR_AUTH_SEC_Msk /*!< Secure debug authorization */ + +/*************** Bit definition for BSEC_AP_UNLOCK register *****************/ +#define BSEC_AP_UNLOCK_UNLOCK_Pos (0UL) +#define BSEC_AP_UNLOCK_UNLOCK_Msk (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos) /*!< 0x000000FF */ +#define BSEC_AP_UNLOCK_UNLOCK BSEC_AP_UNLOCK_UNLOCK_Msk /*!< Unlock DBG_MCU AP interface */ + +/***************** Bit definition for BSEC_HDPLSR register ******************/ +#define BSEC_HDPLSR_HDPL_Pos (0UL) +#define BSEC_HDPLSR_HDPL_Msk (0xFFUL << BSEC_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define BSEC_HDPLSR_HDPL BSEC_HDPLSR_HDPL_Msk /*!< Current HDPL */ + +/***************** Bit definition for BSEC_HDPLCR register ******************/ +#define BSEC_HDPLCR_INCR_HDPL_Pos (0UL) +#define BSEC_HDPLCR_INCR_HDPL_Msk (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HDPLCR_INCR_HDPL BSEC_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL */ + +/***************** Bit definition for BSEC_NEXTLR register ******************/ +#define BSEC_NEXTLR_INCR_Pos (0UL) +#define BSEC_NEXTLR_INCR_Msk (0x3UL << BSEC_NEXTLR_INCR_Pos) /*!< 0x00000003 */ +#define BSEC_NEXTLR_INCR BSEC_NEXTLR_INCR_Msk /*!< Increment */ + +/***************** Bit definition for BSEC_WOSCRx register ******************/ +#define BSEC_WOSCRx_WOSDATA_Pos (0UL) +#define BSEC_WOSCRx_WOSDATA_Msk (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WOSCRx_WOSDATA BSEC_WOSCRx_WOSDATA_Msk /*!< Write once scratch data */ + +/****************** Bit definition for BSEC_HRCR register *******************/ +#define BSEC_HRCR_HRC_Pos (0UL) +#define BSEC_HRCR_HRC_Msk (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_HRCR_HRC BSEC_HRCR_HRC_Msk /*!< Hot reset counter */ + +/****************** Bit definition for BSEC_WRCR register *******************/ +#define BSEC_WRCR_WRC_Pos (0UL) +#define BSEC_WRCR_WRC_Msk (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos) /*!< 0xFFFFFFFF */ +#define BSEC_WRCR_WRC BSEC_WRCR_WRC_Msk /*!< Warm reset counter */ + + +/******************************************************************************/ +/* */ +/* CACHEAXI */ +/* */ +/******************************************************************************/ +/**************** Bit definition for CACHEAXI_CR1 register ******************/ +#define CACHEAXI_CR1_EN_Pos (0UL) +#define CACHEAXI_CR1_EN_Msk (0x1UL << CACHEAXI_CR1_EN_Pos) /*!< 0x00000001 */ +#define CACHEAXI_CR1_EN CACHEAXI_CR1_EN_Msk /*!< Enable */ +#define CACHEAXI_CR1_CACHEINV_Pos (1UL) +#define CACHEAXI_CR1_CACHEINV_Msk (0x1UL << CACHEAXI_CR1_CACHEINV_Pos) /*!< 0x00000002 */ +#define CACHEAXI_CR1_CACHEINV CACHEAXI_CR1_CACHEINV_Msk /*!< Cache invalidation */ +#define CACHEAXI_CR1_RHITMEN_Pos (16UL) +#define CACHEAXI_CR1_RHITMEN_Msk (0x1UL << CACHEAXI_CR1_RHITMEN_Pos) /*!< 0x00010000 */ +#define CACHEAXI_CR1_RHITMEN CACHEAXI_CR1_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define CACHEAXI_CR1_RMISSMEN_Pos (17UL) +#define CACHEAXI_CR1_RMISSMEN_Msk (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos) /*!< 0x00020000 */ +#define CACHEAXI_CR1_RMISSMEN CACHEAXI_CR1_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define CACHEAXI_CR1_RHITMRST_Pos (18UL) +#define CACHEAXI_CR1_RHITMRST_Msk (0x1UL << CACHEAXI_CR1_RHITMRST_Pos) /*!< 0x00040000 */ +#define CACHEAXI_CR1_RHITMRST CACHEAXI_CR1_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define CACHEAXI_CR1_RMISSMRST_Pos (19UL) +#define CACHEAXI_CR1_RMISSMRST_Msk (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos) /*!< 0x00080000 */ +#define CACHEAXI_CR1_RMISSMRST CACHEAXI_CR1_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define CACHEAXI_CR1_WHITMEN_Pos (20UL) +#define CACHEAXI_CR1_WHITMEN_Msk (0x1UL << CACHEAXI_CR1_WHITMEN_Pos) /*!< 0x00100000 */ +#define CACHEAXI_CR1_WHITMEN CACHEAXI_CR1_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define CACHEAXI_CR1_WMISSMEN_Pos (21UL) +#define CACHEAXI_CR1_WMISSMEN_Msk (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos) /*!< 0x00200000 */ +#define CACHEAXI_CR1_WMISSMEN CACHEAXI_CR1_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define CACHEAXI_CR1_WHITMRST_Pos (22UL) +#define CACHEAXI_CR1_WHITMRST_Msk (0x1UL << CACHEAXI_CR1_WHITMRST_Pos) /*!< 0x00400000 */ +#define CACHEAXI_CR1_WHITMRST CACHEAXI_CR1_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define CACHEAXI_CR1_WMISSMRST_Pos (23UL) +#define CACHEAXI_CR1_WMISSMRST_Msk (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos) /*!< 0x00800000 */ +#define CACHEAXI_CR1_WMISSMRST CACHEAXI_CR1_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define CACHEAXI_CR1_RAMMEN_Pos (24UL) +#define CACHEAXI_CR1_RAMMEN_Msk (0x1UL << CACHEAXI_CR1_RAMMEN_Pos) /*!< 0x01000000 */ +#define CACHEAXI_CR1_RAMMEN CACHEAXI_CR1_RAMMEN_Msk /*!< Read-allocate miss monitor enable */ +#define CACHEAXI_CR1_WAMMEN_Pos (25UL) +#define CACHEAXI_CR1_WAMMEN_Msk (0x1UL << CACHEAXI_CR1_WAMMEN_Pos) /*!< 0x02000000 */ +#define CACHEAXI_CR1_WAMMEN CACHEAXI_CR1_WAMMEN_Msk /*!< Write-allocate miss monitor enable */ +#define CACHEAXI_CR1_RAMMRST_Pos (26UL) +#define CACHEAXI_CR1_RAMMRST_Msk (0x1UL << CACHEAXI_CR1_RAMMRST_Pos) /*!< 0x04000000 */ +#define CACHEAXI_CR1_RAMMRST CACHEAXI_CR1_RAMMRST_Msk /*!< Read-allocate miss monitor reset */ +#define CACHEAXI_CR1_WAMMRST_Pos (27UL) +#define CACHEAXI_CR1_WAMMRST_Msk (0x1UL << CACHEAXI_CR1_WAMMRST_Pos) /*!< 0x08000000 */ +#define CACHEAXI_CR1_WAMMRST CACHEAXI_CR1_WAMMRST_Msk /*!< Write-allocate miss monitor reset */ +#define CACHEAXI_CR1_WTMEN_Pos (28UL) +#define CACHEAXI_CR1_WTMEN_Msk (0x1UL << CACHEAXI_CR1_WTMEN_Pos) /*!< 0x10000000 */ +#define CACHEAXI_CR1_WTMEN CACHEAXI_CR1_WTMEN_Msk /*!< Write-through monitor enable */ +#define CACHEAXI_CR1_EVIMEN_Pos (29UL) +#define CACHEAXI_CR1_EVIMEN_Msk (0x1UL << CACHEAXI_CR1_EVIMEN_Pos) /*!< 0x20000000 */ +#define CACHEAXI_CR1_EVIMEN CACHEAXI_CR1_EVIMEN_Msk /*!< Eviction monitor enable */ +#define CACHEAXI_CR1_WTMRST_Pos (30UL) +#define CACHEAXI_CR1_WTMRST_Msk (0x1UL << CACHEAXI_CR1_WTMRST_Pos) /*!< 0x40000000 */ +#define CACHEAXI_CR1_WTMRST CACHEAXI_CR1_WTMRST_Msk /*!< Write-through monitor reset */ +#define CACHEAXI_CR1_EVIMRST_Pos (31UL) +#define CACHEAXI_CR1_EVIMRST_Msk (0x1UL << CACHEAXI_CR1_EVIMRST_Pos) /*!< 0x80000000 */ +#define CACHEAXI_CR1_EVIMRST CACHEAXI_CR1_EVIMRST_Msk /*!< Eviction monitor reset */ + +/****************** Bit definition for CACHEAXI_SR register *******************/ +#define CACHEAXI_SR_BUSYF_Pos (0UL) +#define CACHEAXI_SR_BUSYF_Msk (0x1UL << CACHEAXI_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define CACHEAXI_SR_BUSYF CACHEAXI_SR_BUSYF_Msk /*!< Busy flag */ +#define CACHEAXI_SR_BSYENDF_Pos (1UL) +#define CACHEAXI_SR_BSYENDF_Msk (0x1UL << CACHEAXI_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define CACHEAXI_SR_BSYENDF CACHEAXI_SR_BSYENDF_Msk /*!< Busy end flag */ +#define CACHEAXI_SR_ERRF_Pos (2UL) +#define CACHEAXI_SR_ERRF_Msk (0x1UL << CACHEAXI_SR_ERRF_Pos) /*!< 0x00000004 */ +#define CACHEAXI_SR_ERRF CACHEAXI_SR_ERRF_Msk /*!< Cache error flag */ +#define CACHEAXI_SR_BUSYCMDF_Pos (3UL) +#define CACHEAXI_SR_BUSYCMDF_Msk (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define CACHEAXI_SR_BUSYCMDF CACHEAXI_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define CACHEAXI_SR_CMDENDF_Pos (4UL) +#define CACHEAXI_SR_CMDENDF_Msk (0x1UL << CACHEAXI_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define CACHEAXI_SR_CMDENDF CACHEAXI_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for CACHEAXI_IER register ******************/ +#define CACHEAXI_IER_BSYENDIE_Pos (1UL) +#define CACHEAXI_IER_BSYENDIE_Msk (0x1UL << CACHEAXI_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define CACHEAXI_IER_BSYENDIE CACHEAXI_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define CACHEAXI_IER_ERRIE_Pos (2UL) +#define CACHEAXI_IER_ERRIE_Msk (0x1UL << CACHEAXI_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define CACHEAXI_IER_ERRIE CACHEAXI_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define CACHEAXI_IER_CMDENDIE_Pos (4UL) +#define CACHEAXI_IER_CMDENDIE_Msk (0x1UL << CACHEAXI_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define CACHEAXI_IER_CMDENDIE CACHEAXI_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for CACHEAXI_FCR register ******************/ +#define CACHEAXI_FCR_CBSYENDF_Pos (1UL) +#define CACHEAXI_FCR_CBSYENDF_Msk (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define CACHEAXI_FCR_CBSYENDF CACHEAXI_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define CACHEAXI_FCR_CERRF_Pos (2UL) +#define CACHEAXI_FCR_CERRF_Msk (0x1UL << CACHEAXI_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define CACHEAXI_FCR_CERRF CACHEAXI_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define CACHEAXI_FCR_CCMDENDF_Pos (4UL) +#define CACHEAXI_FCR_CCMDENDF_Msk (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define CACHEAXI_FCR_CCMDENDF CACHEAXI_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for CACHEAXI_RHMONR register ****************/ +#define CACHEAXI_RHMONR_RHITMON_Pos (0UL) +#define CACHEAXI_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RHMONR_RHITMON CACHEAXI_RHMONR_RHITMON_Msk /*!< Cache read hit monitor register */ + +/****************** Bit definition for CACHEAXI_RMMONR register ****************/ +#define CACHEAXI_RMMONR_RMISSMON_Pos (0UL) +#define CACHEAXI_RMMONR_RMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RMMONR_RMISSMON CACHEAXI_RMMONR_RMISSMON_Msk /*!< Cache read miss monitor register */ + +/****************** Bit definition for CACHEAXI_RAMMONR register ****************/ +#define CACHEAXI_RAMMONR_RAMMON_Pos (0UL) +#define CACHEAXI_RAMMONR_RAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_RAMMONR_RAMMON CACHEAXI_RAMMONR_RAMMON_Msk /*!< Cache read-allocate miss monitor counter */ + +/****************** Bit definition for CACHEAXI_EVIMONR register ****************/ +#define CACHEAXI_EVIMONR_EVIMON_Pos (0UL) +#define CACHEAXI_EVIMONR_EVIMON_Msk (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_EVIMONR_EVIMON CACHEAXI_EVIMONR_EVIMON_Msk /*!< Cache eviction monitor counter */ + +/****************** Bit definition for CACHEAXI_WHMONR register ****************/ +#define CACHEAXI_WHMONR_WHITMON_Pos (0UL) +#define CACHEAXI_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WHMONR_WHITMON CACHEAXI_WHMONR_WHITMON_Msk /*!< Cache write hit monitor register */ + +/****************** Bit definition for CACHEAXI_WMMONR register ****************/ +#define CACHEAXI_WMMONR_WMISSMON_Pos (0UL) +#define CACHEAXI_WMMONR_WMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WMMONR_WMISSMON CACHEAXI_WMMONR_WMISSMON_Msk /*!< Cache write miss monitor register */ + +/****************** Bit definition for CACHEAXI_WAMMONR register ****************/ +#define CACHEAXI_WAMMONR_WAMMON_Pos (0UL) +#define CACHEAXI_WAMMONR_WAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WAMMONR_WAMMON CACHEAXI_WAMMONR_WAMMON_Msk /*!< Cache write-allocate miss monitor register */ + +/****************** Bit definition for CACHEAXI_WTMONR register ****************/ +#define CACHEAXI_WTMONR_WTMON_Pos (0UL) +#define CACHEAXI_WTMONR_WTMON_Msk (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos) /*!< 0xFFFFFFFF */ +#define CACHEAXI_WTMONR_WTMON CACHEAXI_WTMONR_WTMON_Msk /*!< Cache write-through monitor register */ + +/**************** Bit definition for CACHEAXI_CR2 register ******************/ +#define CACHEAXI_CR2_STARTCMD_Pos (0UL) +#define CACHEAXI_CR2_STARTCMD_Msk (0x1UL << CACHEAXI_CR2_STARTCMD_Pos) /*!< 0x00000001 */ +#define CACHEAXI_CR2_STARTCMD CACHEAXI_CR2_STARTCMD_Msk /*!< Starts maintenance range command */ +#define CACHEAXI_CR2_CACHECMD_Pos (1UL) +#define CACHEAXI_CR2_CACHECMD_Msk (0x3UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000006 */ +#define CACHEAXI_CR2_CACHECMD CACHEAXI_CR2_CACHECMD_Msk /*!< Cache command maintenance operation */ +#define CACHEAXI_CR2_CACHECMD_0 (0x1UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000002 */ +#define CACHEAXI_CR2_CACHECMD_1 (0x2UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000004 */ + +/****************** Bit definition for CACHEAXI_CMDRSADDRR register ****************/ +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos (0UL) +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */ +#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for CACHEAXI_CMDREADDRR register ****************/ +#define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos (0UL) +#define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFC0 */ +#define CACHEAXI_CMDREADDRR_CMDENDADDR CACHEAXI_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ +#define CRC_CR_RTYPE_IN_Pos (9UL) +#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ +#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ +#define CRC_CR_RTYPE_OUT_Pos (10UL) +#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ +#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Cryp Processor */ +/* */ +/******************************************************************************/ +/******************* Bits definition for CRYP_CR register ********************/ +#define CRYP_CR_ALGODIR_Pos (2UL) +#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */ +#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk /*!< Algorithm direction (Encrypt/Decrypt) */ + +#define CRYP_CR_ALGOMODE_Pos (3UL) +#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */ +#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk /*!< Algorithm mode */ +#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ +#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ +#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ +#define CRYP_CR_ALGOMODE_3 (0x10000UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080000 */ +#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5UL) +#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */ +#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk +#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */ +#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk +#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4UL) +#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */ +#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk +#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */ +#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk +#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19UL) +#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */ +#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk +#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3UL) +#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */ +#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk + +#define CRYP_CR_DATATYPE_Pos (6UL) +#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */ +#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk /*!< Data Type selection */ +#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */ +#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */ +#define CRYP_CR_KEYSIZE_Pos (8UL) +#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */ +#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk /*!< Key Size selection */ +#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */ +#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */ +#define CRYP_CR_FFLUSH_Pos (14UL) +#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */ +#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk /*!< CRYP FIFO Flush */ +#define CRYP_CR_CRYPEN_Pos (15UL) +#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */ +#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk /*!< CRYP processor enable */ + +#define CRYP_CR_GCM_CCMPH_Pos (16UL) +#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */ +#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk /*!< GCM or CCM Phase selection */ +#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ +#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ + +#define CRYP_CR_NPBLB_Pos (20UL) +#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk /*!< Number of Padding Bytes in Last Block of payload */ + +#define CRYP_CR_KMOD_Pos (24UL) +#define CRYP_CR_KMOD_Msk (0x3UL << CRYP_CR_KMOD_Pos) /*!< 0x03000000 */ +#define CRYP_CR_KMOD CRYP_CR_KMOD_Msk /*!< Key mode selection */ +#define CRYP_CR_KMOD_0 (0x1UL << CRYP_CR_KMOD_Pos) /*!< 0x01000000 */ +#define CRYP_CR_KMOD_1 (0x2UL << CRYP_CR_KMOD_Pos) /*!< 0x02000000 */ + +#define CRYP_CR_IPRST_Pos (31UL) +#define CRYP_CR_IPRST_Msk (0x1UL << CRYP_CR_IPRST_Pos) /*!< 0x80000000 */ +#define CRYP_CR_IPRST CRYP_CR_IPRST_Msk /*!< CRYP peripheral software reset */ + +/****************** Bits definition for CRYP_SR register *********************/ +#define CRYP_SR_IFEM_Pos (0UL) +#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */ +#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk /*!< Input FIFO empty flag */ +#define CRYP_SR_IFNF_Pos (1UL) +#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */ +#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk /*!< Input FIFO not full flag */ +#define CRYP_SR_OFNE_Pos (2UL) +#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */ +#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk /*!< Output FIFO not empty flag */ +#define CRYP_SR_OFFU_Pos (3UL) +#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */ +#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk /*!< Output FIFO full flag */ +#define CRYP_SR_BUSY_Pos (4UL) +#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */ +#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk /*!< Busy bit */ +#define CRYP_SR_KERF_Pos (6UL) +#define CRYP_SR_KERF_Msk (0x1UL << CRYP_SR_KERF_Pos) /*!< 0x00000040 */ +#define CRYP_SR_KERF CRYP_SR_KERF_Msk /*!< Key error flag */ +#define CRYP_SR_KEYVALID_Pos (7UL) +#define CRYP_SR_KEYVALID_Msk (0x1UL << CRYP_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define CRYP_SR_KEYVALID CRYP_SR_KEYVALID_Msk /*!< Key valid flag */ + +/******************* Bit definition for CRYP_DIN register *******************/ +#define CRYP_DIN_DATAIN_Pos (0UL) +#define CRYP_DIN_DATAIN_Msk (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_DIN_DATAIN CRYP_DIN_DATAIN_Msk /*!< CRYP Data Input */ + +/******************* Bit definition for CRYP_DIN register *******************/ +#define CRYP_DOUT_DATAOUT_Pos (0UL) +#define CRYP_DOUT_DATAOUT_Msk (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_DOUT_DATAOUT CRYP_DOUT_DATAOUT_Msk /*!< CRYP Data Output */ + +/****************** Bits definition for CRYP_DMACR register ******************/ +#define CRYP_DMACR_DIEN_Pos (0UL) +#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */ +#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk /*!< DMA Input Enable */ +#define CRYP_DMACR_DOEN_Pos (1UL) +#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */ +#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk /*!< DMA Output Enable */ + +/***************** Bits definition for CRYP_IMSCR register ******************/ +#define CRYP_IMSCR_INIM_Pos (0UL) +#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */ +#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk /*!< Input FIFO service interrupt mask */ +#define CRYP_IMSCR_OUTIM_Pos (1UL) +#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */ +#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk /*!< Output FIFO service interrupt mask */ + +/****************** Bits definition for CRYP_RISR register *******************/ +#define CRYP_RISR_INRIS_Pos (0UL) +#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */ +#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk /*!< Input FIFO service raw interrupt status */ +#define CRYP_RISR_OUTRIS_Pos (1UL) +#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */ +#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk /*!< Output FIFO service raw interrupt mask */ + +/****************** Bits definition for CRYP_MISR register *******************/ +#define CRYP_MISR_INMIS_Pos (0UL) +#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */ +#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk /*!< Input FIFO service masked interrupt status */ +#define CRYP_MISR_OUTMIS_Pos (1UL) +#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */ +#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk /*!< Output FIFO service masked interrupt status */ + +/******************* Bit definition for CRYP_K0LR register ******************/ +#define CRYP_K0LR_K_Pos (0UL) +#define CRYP_K0LR_K_Msk (0xFFFFFFFFUL << CRYP_K0LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K0LR_K CRYP_K0LR_K_Msk /*!< AES key bit x (x= 224 to 255) */ + +/******************* Bit definition for CRYP_K0RR register ******************/ +#define CRYP_K0RR_K_Pos (0UL) +#define CRYP_K0RR_K_Msk (0xFFFFFFFFUL << CRYP_K0RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K0RR_K CRYP_K0RR_K_Msk /*!< AES key bit x (x= 192 to 223) */ + +/******************* Bit definition for CRYP_IV1LR register ******************/ +#define CRYP_IV1LR_K_Pos (0UL) +#define CRYP_IV1LR_K_Msk (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1LR_K CRYP_IV1LR_K_Msk /*!< AES key bit x (x= 160 to 291) */ + +/******************* Bit definition for CRYP_IV1RR register ******************/ +#define CRYP_IV1RR_K_Pos (0UL) +#define CRYP_IV1RR_K_Msk (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1RR_K CRYP_IV1RR_K_Msk /*!< AES key bit x (x= 128 to 159) */ + +/******************* Bit definition for CRYP_K2LR register ******************/ +#define CRYP_K2LR_K_Pos (0UL) +#define CRYP_K2LR_K_Msk (0xFFFFFFFFUL << CRYP_K2LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K2LR_K CRYP_K2LR_K_Msk /*!< AES key bit x (x= 96 to 127) */ + +/******************* Bit definition for CRYP_K2RR register ******************/ +#define CRYP_K2RR_K_Pos (0UL) +#define CRYP_K2RR_K_Msk (0xFFFFFFFFUL << CRYP_K2RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K2RR_K CRYP_K2RR_K_Msk /*!< AES key bit x (x= 64 to 95) */ + +/******************* Bit definition for CRYP_K3LR register ******************/ +#define CRYP_K3LR_K_Pos (0UL) +#define CRYP_K3LR_K_Msk (0xFFFFFFFFUL << CRYP_K3LR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K3LR_K CRYP_K3LR_K_Msk /*!< AES key bit x (x= 32 to 63) */ + +/******************* Bit definition for CRYP_K3RR register ******************/ +#define CRYP_K3RR_K_Pos (0UL) +#define CRYP_K3RR_K_Msk (0xFFFFFFFFUL << CRYP_K3RR_K_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_K3RR_K CRYP_K3RR_K_Msk /*!< AES key bit x (x= 0 to 31) */ + +/******************* Bit definition for CRYP_IV0LR register ******************/ +#define CRYP_IV0LR_IV_Pos (0UL) +#define CRYP_IV0LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV0LR_IV CRYP_IV0LR_IV_Msk /*!< Initialization vector bit x (x= 0 to 31) */ + +/******************* Bit definition for CRYP_IV0RR register ******************/ +#define CRYP_IV0RR_IV_Pos (0UL) +#define CRYP_IV0RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV0RR_IV CRYP_IV0RR_IV_Msk /*!< Initialization vector bit x (x= 32 to 63) */ + +/******************* Bit definition for CRYP_IV1LR register ******************/ +#define CRYP_IV1LR_IV_Pos (0UL) +#define CRYP_IV1LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1LR_IV CRYP_IV1LR_IV_Msk /*!< Initialization vector bit x (x= 64 to 95) */ + +/******************* Bit definition for CRYP_IV1RR register ******************/ +#define CRYP_IV1RR_IV_Pos (0UL) +#define CRYP_IV1RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_IV1RR_IV CRYP_IV1RR_IV_Msk /*!< Initialization vector bit x (x= 96 to 127) */ + +/******************* Bit definition for CRYP_CSGCMCCM0R register ******************/ +#define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos (0UL) +#define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM0R_CSGCMCCM0 CRYP_CSGCMCCM0R_CSGCMCCM0_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM1R register ******************/ +#define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos (0UL) +#define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM1R_CSGCMCCM1 CRYP_CSGCMCCM1R_CSGCMCCM1_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM2R register ******************/ +#define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos (0UL) +#define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM2R_CSGCMCCM2 CRYP_CSGCMCCM2R_CSGCMCCM2_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM3R register ******************/ +#define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos (0UL) +#define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM3R_CSGCMCCM3 CRYP_CSGCMCCM3R_CSGCMCCM3_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM4R register ******************/ +#define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos (0UL) +#define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM4R_CSGCMCCM4 CRYP_CSGCMCCM4R_CSGCMCCM4_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM5R register ******************/ +#define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos (0UL) +#define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM5R_CSGCMCCM5 CRYP_CSGCMCCM5R_CSGCMCCM5_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM6R register ******************/ +#define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos (0UL) +#define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM6R_CSGCMCCM6 CRYP_CSGCMCCM6R_CSGCMCCM6_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCMCCM7R register ******************/ +#define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos (0UL) +#define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCMCCM7R_CSGCMCCM7 CRYP_CSGCMCCM7R_CSGCMCCM7_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */ + +/******************* Bit definition for CRYP_CSGCM0R register ******************/ +#define CRYP_CSGCM0R_CSGCM0_Pos (0UL) +#define CRYP_CSGCM0R_CSGCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM0R_CSGCM0 CRYP_CSGCM0R_CSGCM0_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM1R register ******************/ +#define CRYP_CSGCM1R_CSGCM1_Pos (0UL) +#define CRYP_CSGCM1R_CSGCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM1R_CSGCM1 CRYP_CSGCM1R_CSGCM1_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM2R register ******************/ +#define CRYP_CSGCM2R_CSGCM2_Pos (0UL) +#define CRYP_CSGCM2R_CSGCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM2R_CSGCM2 CRYP_CSGCM2R_CSGCM2_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM3R register ******************/ +#define CRYP_CSGCM3R_CSGCM3_Pos (0UL) +#define CRYP_CSGCM3R_CSGCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM3R_CSGCM3 CRYP_CSGCM3R_CSGCM3_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM4R register ******************/ +#define CRYP_CSGCM4R_CSGCM4_Pos (0UL) +#define CRYP_CSGCM4R_CSGCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM4R_CSGCM4 CRYP_CSGCM4R_CSGCM4_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM5R register ******************/ +#define CRYP_CSGCM5R_CSGCM5_Pos (0UL) +#define CRYP_CSGCM5R_CSGCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM5R_CSGCM5 CRYP_CSGCM5R_CSGCM5_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM6R register ******************/ +#define CRYP_CSGCM6R_CSGCM6_Pos (0UL) +#define CRYP_CSGCM6R_CSGCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM6R_CSGCM6 CRYP_CSGCM6R_CSGCM6_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + +/******************* Bit definition for CRYP_CSGCM7R register ******************/ +#define CRYP_CSGCM7R_CSGCM7_Pos (0UL) +#define CRYP_CSGCM7R_CSGCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */ +#define CRYP_CSGCM7R_CSGCM7 CRYP_CSGCM7R_CSGCM7_Msk /*!< CRYP internal state registers for GCM and GMAC modes */ + + +/******************************************************************************/ +/* */ +/* (CSI) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CSI_CR register ********************/ +#define CSI_CR_CSIEN_Pos (0UL) +#define CSI_CR_CSIEN_Msk (0x1UL << CSI_CR_CSIEN_Pos) /*!< 0x00000001 */ +#define CSI_CR_CSIEN CSI_CR_CSIEN_Msk /*!< CSI-2 enable */ +#define CSI_CR_VC0START_Pos (2UL) +#define CSI_CR_VC0START_Msk (0x1UL << CSI_CR_VC0START_Pos) /*!< 0x00000004 */ +#define CSI_CR_VC0START CSI_CR_VC0START_Msk /*!< Virtual channel 0 start */ +#define CSI_CR_VC0STOP_Pos (3UL) +#define CSI_CR_VC0STOP_Msk (0x1UL << CSI_CR_VC0STOP_Pos) /*!< 0x00000008 */ +#define CSI_CR_VC0STOP CSI_CR_VC0STOP_Msk /*!< Virtual channel 0 stop */ +#define CSI_CR_VC1START_Pos (6UL) +#define CSI_CR_VC1START_Msk (0x1UL << CSI_CR_VC1START_Pos) /*!< 0x00000040 */ +#define CSI_CR_VC1START CSI_CR_VC1START_Msk /*!< Virtual channel 1 start */ +#define CSI_CR_VC1STOP_Pos (7UL) +#define CSI_CR_VC1STOP_Msk (0x1UL << CSI_CR_VC1STOP_Pos) /*!< 0x00000080 */ +#define CSI_CR_VC1STOP CSI_CR_VC1STOP_Msk /*!< Virtual channel 1 stop */ +#define CSI_CR_VC2START_Pos (10UL) +#define CSI_CR_VC2START_Msk (0x1UL << CSI_CR_VC2START_Pos) /*!< 0x00000400 */ +#define CSI_CR_VC2START CSI_CR_VC2START_Msk /*!< Virtual channel 2 start */ +#define CSI_CR_VC2STOP_Pos (11UL) +#define CSI_CR_VC2STOP_Msk (0x1UL << CSI_CR_VC2STOP_Pos) /*!< 0x00000800 */ +#define CSI_CR_VC2STOP CSI_CR_VC2STOP_Msk /*!< Virtual channel 2 stop */ +#define CSI_CR_VC3START_Pos (14UL) +#define CSI_CR_VC3START_Msk (0x1UL << CSI_CR_VC3START_Pos) /*!< 0x00004000 */ +#define CSI_CR_VC3START CSI_CR_VC3START_Msk /*!< Virtual channel 3 start */ +#define CSI_CR_VC3STOP_Pos (15UL) +#define CSI_CR_VC3STOP_Msk (0x1UL << CSI_CR_VC3STOP_Pos) /*!< 0x00008000 */ +#define CSI_CR_VC3STOP CSI_CR_VC3STOP_Msk /*!< Virtual channel 3 stop */ + +/******************* Bit definition for CSI_PCR register ********************/ +#define CSI_PCR_NPWRDOWN_Pos (0UL) +#define CSI_PCR_NPWRDOWN_Msk (0x1UL << CSI_PCR_NPWRDOWN_Pos) /*!< 0x00000001 */ +#define CSI_PCR_NPWRDOWN CSI_PCR_NPWRDOWN_Msk /*!< Virtual channel 3 start */ +#define CSI_PCR_CLEN_Pos (1UL) +#define CSI_PCR_CLEN_Msk (0x1UL << CSI_PCR_CLEN_Pos) /*!< 0x00000002 */ +#define CSI_PCR_CLEN CSI_PCR_CLEN_Msk /*!< Clock lane enable */ +#define CSI_PCR_DL0EN_Pos (2UL) +#define CSI_PCR_DL0EN_Msk (0x1UL << CSI_PCR_DL0EN_Pos) /*!< 0x00000004 */ +#define CSI_PCR_DL0EN CSI_PCR_DL0EN_Msk /*!< D-PHY_RX data lane 0 enable */ +#define CSI_PCR_DL1EN_Pos (3UL) +#define CSI_PCR_DL1EN_Msk (0x1UL << CSI_PCR_DL1EN_Pos) /*!< 0x00000008 */ +#define CSI_PCR_DL1EN CSI_PCR_DL1EN_Msk /*!< D-PHY_RX data lane 1 enable */ + +/***************** Bit definition for CSI_VC0CFGR1 register *****************/ +#define CSI_VC0CFGR1_ALLDT_Pos (0UL) +#define CSI_VC0CFGR1_ALLDT_Msk (0x1UL << CSI_VC0CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC0CFGR1_ALLDT CSI_VC0CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC0CFGR1_DT0EN_Pos (1UL) +#define CSI_VC0CFGR1_DT0EN_Msk (0x1UL << CSI_VC0CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC0CFGR1_DT0EN CSI_VC0CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC0CFGR1_DT1EN_Pos (2UL) +#define CSI_VC0CFGR1_DT1EN_Msk (0x1UL << CSI_VC0CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC0CFGR1_DT1EN CSI_VC0CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC0CFGR1_DT2EN_Pos (3UL) +#define CSI_VC0CFGR1_DT2EN_Msk (0x1UL << CSI_VC0CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC0CFGR1_DT2EN CSI_VC0CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC0CFGR1_DT3EN_Pos (4UL) +#define CSI_VC0CFGR1_DT3EN_Msk (0x1UL << CSI_VC0CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC0CFGR1_DT3EN CSI_VC0CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC0CFGR1_DT4EN_Pos (5UL) +#define CSI_VC0CFGR1_DT4EN_Msk (0x1UL << CSI_VC0CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC0CFGR1_DT4EN CSI_VC0CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC0CFGR1_DT5EN_Pos (6UL) +#define CSI_VC0CFGR1_DT5EN_Msk (0x1UL << CSI_VC0CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC0CFGR1_DT5EN CSI_VC0CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC0CFGR1_DT6EN_Pos (7UL) +#define CSI_VC0CFGR1_DT6EN_Msk (0x1UL << CSI_VC0CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC0CFGR1_DT6EN CSI_VC0CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC0CFGR1_CDTFT_Pos (8UL) +#define CSI_VC0CFGR1_CDTFT_Msk (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR1_CDTFT CSI_VC0CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC0CFGR1_DT0_Pos (16UL) +#define CSI_VC0CFGR1_DT0_Msk (0x3FUL << CSI_VC0CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR1_DT0 CSI_VC0CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC0CFGR1_DT0FT_Pos (24UL) +#define CSI_VC0CFGR1_DT0FT_Msk (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR1_DT0FT CSI_VC0CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC0CFGR2 register *****************/ +#define CSI_VC0CFGR2_DT1_Pos (0UL) +#define CSI_VC0CFGR2_DT1_Msk (0x3FUL << CSI_VC0CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR2_DT1 CSI_VC0CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT1FT_Pos (8UL) +#define CSI_VC0CFGR2_DT1FT_Msk (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR2_DT1FT CSI_VC0CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC0CFGR2_DT2_Pos (16UL) +#define CSI_VC0CFGR2_DT2_Msk (0x3FUL << CSI_VC0CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR2_DT2 CSI_VC0CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC0CFGR2_DT2FT_Pos (24UL) +#define CSI_VC0CFGR2_DT2FT_Msk (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR2_DT2FT CSI_VC0CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC0CFGR3 register *****************/ +#define CSI_VC0CFGR3_DT3_Pos (0UL) +#define CSI_VC0CFGR3_DT3_Msk (0x3FUL << CSI_VC0CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR3_DT3 CSI_VC0CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT3FT_Pos (8UL) +#define CSI_VC0CFGR3_DT3FT_Msk (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR3_DT3FT CSI_VC0CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC0CFGR3_DT4_Pos (16UL) +#define CSI_VC0CFGR3_DT4_Msk (0x3FUL << CSI_VC0CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR3_DT4 CSI_VC0CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC0CFGR3_DT4FT_Pos (24UL) +#define CSI_VC0CFGR3_DT4FT_Msk (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR3_DT4FT CSI_VC0CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC0CFGR4 register *****************/ +#define CSI_VC0CFGR4_DT5_Pos (0UL) +#define CSI_VC0CFGR4_DT5_Msk (0x3FUL << CSI_VC0CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC0CFGR4_DT5 CSI_VC0CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT5FT_Pos (8UL) +#define CSI_VC0CFGR4_DT5FT_Msk (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC0CFGR4_DT5FT CSI_VC0CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC0CFGR4_DT6_Pos (16UL) +#define CSI_VC0CFGR4_DT6_Msk (0x3FUL << CSI_VC0CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC0CFGR4_DT6 CSI_VC0CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC0CFGR4_DT6FT_Pos (24UL) +#define CSI_VC0CFGR4_DT6FT_Msk (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC0CFGR4_DT6FT CSI_VC0CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC1CFGR1 register *****************/ +#define CSI_VC1CFGR1_ALLDT_Pos (0UL) +#define CSI_VC1CFGR1_ALLDT_Msk (0x1UL << CSI_VC1CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC1CFGR1_ALLDT CSI_VC1CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC1CFGR1_DT0EN_Pos (1UL) +#define CSI_VC1CFGR1_DT0EN_Msk (0x1UL << CSI_VC1CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC1CFGR1_DT0EN CSI_VC1CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC1CFGR1_DT1EN_Pos (2UL) +#define CSI_VC1CFGR1_DT1EN_Msk (0x1UL << CSI_VC1CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC1CFGR1_DT1EN CSI_VC1CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC1CFGR1_DT2EN_Pos (3UL) +#define CSI_VC1CFGR1_DT2EN_Msk (0x1UL << CSI_VC1CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC1CFGR1_DT2EN CSI_VC1CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC1CFGR1_DT3EN_Pos (4UL) +#define CSI_VC1CFGR1_DT3EN_Msk (0x1UL << CSI_VC1CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC1CFGR1_DT3EN CSI_VC1CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC1CFGR1_DT4EN_Pos (5UL) +#define CSI_VC1CFGR1_DT4EN_Msk (0x1UL << CSI_VC1CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC1CFGR1_DT4EN CSI_VC1CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC1CFGR1_DT5EN_Pos (6UL) +#define CSI_VC1CFGR1_DT5EN_Msk (0x1UL << CSI_VC1CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC1CFGR1_DT5EN CSI_VC1CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC1CFGR1_DT6EN_Pos (7UL) +#define CSI_VC1CFGR1_DT6EN_Msk (0x1UL << CSI_VC1CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC1CFGR1_DT6EN CSI_VC1CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC1CFGR1_CDTFT_Pos (8UL) +#define CSI_VC1CFGR1_CDTFT_Msk (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR1_CDTFT CSI_VC1CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC1CFGR1_DT0_Pos (16UL) +#define CSI_VC1CFGR1_DT0_Msk (0x3FUL << CSI_VC1CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR1_DT0 CSI_VC1CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC1CFGR1_DT0FT_Pos (24UL) +#define CSI_VC1CFGR1_DT0FT_Msk (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR1_DT0FT CSI_VC1CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC1CFGR2 register *****************/ +#define CSI_VC1CFGR2_DT1_Pos (0UL) +#define CSI_VC1CFGR2_DT1_Msk (0x3FUL << CSI_VC1CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR2_DT1 CSI_VC1CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT1FT_Pos (8UL) +#define CSI_VC1CFGR2_DT1FT_Msk (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR2_DT1FT CSI_VC1CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC1CFGR2_DT2_Pos (16UL) +#define CSI_VC1CFGR2_DT2_Msk (0x3FUL << CSI_VC1CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR2_DT2 CSI_VC1CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC1CFGR2_DT2FT_Pos (24UL) +#define CSI_VC1CFGR2_DT2FT_Msk (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR2_DT2FT CSI_VC1CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC1CFGR3 register *****************/ +#define CSI_VC1CFGR3_DT3_Pos (0UL) +#define CSI_VC1CFGR3_DT3_Msk (0x3FUL << CSI_VC1CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR3_DT3 CSI_VC1CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT3FT_Pos (8UL) +#define CSI_VC1CFGR3_DT3FT_Msk (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR3_DT3FT CSI_VC1CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC1CFGR3_DT4_Pos (16UL) +#define CSI_VC1CFGR3_DT4_Msk (0x3FUL << CSI_VC1CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR3_DT4 CSI_VC1CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC1CFGR3_DT4FT_Pos (24UL) +#define CSI_VC1CFGR3_DT4FT_Msk (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR3_DT4FT CSI_VC1CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC1CFGR4 register *****************/ +#define CSI_VC1CFGR4_DT5_Pos (0UL) +#define CSI_VC1CFGR4_DT5_Msk (0x3FUL << CSI_VC1CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC1CFGR4_DT5 CSI_VC1CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT5FT_Pos (8UL) +#define CSI_VC1CFGR4_DT5FT_Msk (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC1CFGR4_DT5FT CSI_VC1CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC1CFGR4_DT6_Pos (16UL) +#define CSI_VC1CFGR4_DT6_Msk (0x3FUL << CSI_VC1CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC1CFGR4_DT6 CSI_VC1CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC1CFGR4_DT6FT_Pos (24UL) +#define CSI_VC1CFGR4_DT6FT_Msk (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC1CFGR4_DT6FT CSI_VC1CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC2CFGR1 register *****************/ +#define CSI_VC2CFGR1_ALLDT_Pos (0UL) +#define CSI_VC2CFGR1_ALLDT_Msk (0x1UL << CSI_VC2CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC2CFGR1_ALLDT CSI_VC2CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC2CFGR1_DT0EN_Pos (1UL) +#define CSI_VC2CFGR1_DT0EN_Msk (0x1UL << CSI_VC2CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC2CFGR1_DT0EN CSI_VC2CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC2CFGR1_DT1EN_Pos (2UL) +#define CSI_VC2CFGR1_DT1EN_Msk (0x1UL << CSI_VC2CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC2CFGR1_DT1EN CSI_VC2CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC2CFGR1_DT2EN_Pos (3UL) +#define CSI_VC2CFGR1_DT2EN_Msk (0x1UL << CSI_VC2CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC2CFGR1_DT2EN CSI_VC2CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC2CFGR1_DT3EN_Pos (4UL) +#define CSI_VC2CFGR1_DT3EN_Msk (0x1UL << CSI_VC2CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC2CFGR1_DT3EN CSI_VC2CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC2CFGR1_DT4EN_Pos (5UL) +#define CSI_VC2CFGR1_DT4EN_Msk (0x1UL << CSI_VC2CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC2CFGR1_DT4EN CSI_VC2CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC2CFGR1_DT5EN_Pos (6UL) +#define CSI_VC2CFGR1_DT5EN_Msk (0x1UL << CSI_VC2CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC2CFGR1_DT5EN CSI_VC2CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC2CFGR1_DT6EN_Pos (7UL) +#define CSI_VC2CFGR1_DT6EN_Msk (0x1UL << CSI_VC2CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC2CFGR1_DT6EN CSI_VC2CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC2CFGR1_CDTFT_Pos (8UL) +#define CSI_VC2CFGR1_CDTFT_Msk (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR1_CDTFT CSI_VC2CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC2CFGR1_DT0_Pos (16UL) +#define CSI_VC2CFGR1_DT0_Msk (0x3FUL << CSI_VC2CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR1_DT0 CSI_VC2CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC2CFGR1_DT0FT_Pos (24UL) +#define CSI_VC2CFGR1_DT0FT_Msk (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR1_DT0FT CSI_VC2CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC2CFGR2 register *****************/ +#define CSI_VC2CFGR2_DT1_Pos (0UL) +#define CSI_VC2CFGR2_DT1_Msk (0x3FUL << CSI_VC2CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR2_DT1 CSI_VC2CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT1FT_Pos (8UL) +#define CSI_VC2CFGR2_DT1FT_Msk (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR2_DT1FT CSI_VC2CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC2CFGR2_DT2_Pos (16UL) +#define CSI_VC2CFGR2_DT2_Msk (0x3FUL << CSI_VC2CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR2_DT2 CSI_VC2CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC2CFGR2_DT2FT_Pos (24UL) +#define CSI_VC2CFGR2_DT2FT_Msk (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR2_DT2FT CSI_VC2CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC2CFGR3 register *****************/ +#define CSI_VC2CFGR3_DT3_Pos (0UL) +#define CSI_VC2CFGR3_DT3_Msk (0x3FUL << CSI_VC2CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR3_DT3 CSI_VC2CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT3FT_Pos (8UL) +#define CSI_VC2CFGR3_DT3FT_Msk (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR3_DT3FT CSI_VC2CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC2CFGR3_DT4_Pos (16UL) +#define CSI_VC2CFGR3_DT4_Msk (0x3FUL << CSI_VC2CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR3_DT4 CSI_VC2CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC2CFGR3_DT4FT_Pos (24UL) +#define CSI_VC2CFGR3_DT4FT_Msk (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR3_DT4FT CSI_VC2CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC2CFGR4 register *****************/ +#define CSI_VC2CFGR4_DT5_Pos (0UL) +#define CSI_VC2CFGR4_DT5_Msk (0x3FUL << CSI_VC2CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC2CFGR4_DT5 CSI_VC2CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT5FT_Pos (8UL) +#define CSI_VC2CFGR4_DT5FT_Msk (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC2CFGR4_DT5FT CSI_VC2CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC2CFGR4_DT6_Pos (16UL) +#define CSI_VC2CFGR4_DT6_Msk (0x3FUL << CSI_VC2CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC2CFGR4_DT6 CSI_VC2CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC2CFGR4_DT6FT_Pos (24UL) +#define CSI_VC2CFGR4_DT6FT_Msk (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC2CFGR4_DT6FT CSI_VC2CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_VC3CFGR1 register *****************/ +#define CSI_VC3CFGR1_ALLDT_Pos (0UL) +#define CSI_VC3CFGR1_ALLDT_Msk (0x1UL << CSI_VC3CFGR1_ALLDT_Pos) /*!< 0x00000001 */ +#define CSI_VC3CFGR1_ALLDT CSI_VC3CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */ +#define CSI_VC3CFGR1_DT0EN_Pos (1UL) +#define CSI_VC3CFGR1_DT0EN_Msk (0x1UL << CSI_VC3CFGR1_DT0EN_Pos) /*!< 0x00000002 */ +#define CSI_VC3CFGR1_DT0EN CSI_VC3CFGR1_DT0EN_Msk /*!< Data type 0 enable */ +#define CSI_VC3CFGR1_DT1EN_Pos (2UL) +#define CSI_VC3CFGR1_DT1EN_Msk (0x1UL << CSI_VC3CFGR1_DT1EN_Pos) /*!< 0x00000004 */ +#define CSI_VC3CFGR1_DT1EN CSI_VC3CFGR1_DT1EN_Msk /*!< Data type 1 enable */ +#define CSI_VC3CFGR1_DT2EN_Pos (3UL) +#define CSI_VC3CFGR1_DT2EN_Msk (0x1UL << CSI_VC3CFGR1_DT2EN_Pos) /*!< 0x00000008 */ +#define CSI_VC3CFGR1_DT2EN CSI_VC3CFGR1_DT2EN_Msk /*!< Data type 2 enable */ +#define CSI_VC3CFGR1_DT3EN_Pos (4UL) +#define CSI_VC3CFGR1_DT3EN_Msk (0x1UL << CSI_VC3CFGR1_DT3EN_Pos) /*!< 0x00000010 */ +#define CSI_VC3CFGR1_DT3EN CSI_VC3CFGR1_DT3EN_Msk /*!< Data type 3 enable */ +#define CSI_VC3CFGR1_DT4EN_Pos (5UL) +#define CSI_VC3CFGR1_DT4EN_Msk (0x1UL << CSI_VC3CFGR1_DT4EN_Pos) /*!< 0x00000020 */ +#define CSI_VC3CFGR1_DT4EN CSI_VC3CFGR1_DT4EN_Msk /*!< Data type 4 enable */ +#define CSI_VC3CFGR1_DT5EN_Pos (6UL) +#define CSI_VC3CFGR1_DT5EN_Msk (0x1UL << CSI_VC3CFGR1_DT5EN_Pos) /*!< 0x00000040 */ +#define CSI_VC3CFGR1_DT5EN CSI_VC3CFGR1_DT5EN_Msk /*!< Data type 5 enable */ +#define CSI_VC3CFGR1_DT6EN_Pos (7UL) +#define CSI_VC3CFGR1_DT6EN_Msk (0x1UL << CSI_VC3CFGR1_DT6EN_Pos) /*!< 0x00000080 */ +#define CSI_VC3CFGR1_DT6EN CSI_VC3CFGR1_DT6EN_Msk /*!< Data type 6 enable */ +#define CSI_VC3CFGR1_CDTFT_Pos (8UL) +#define CSI_VC3CFGR1_CDTFT_Msk (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR1_CDTFT CSI_VC3CFGR1_CDTFT_Msk /*!< Common format for all data types */ +#define CSI_VC3CFGR1_DT0_Pos (16UL) +#define CSI_VC3CFGR1_DT0_Msk (0x3FUL << CSI_VC3CFGR1_DT0_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR1_DT0 CSI_VC3CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */ +#define CSI_VC3CFGR1_DT0FT_Pos (24UL) +#define CSI_VC3CFGR1_DT0FT_Msk (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR1_DT0FT CSI_VC3CFGR1_DT0FT_Msk /*!< Data type 0 format */ + +/***************** Bit definition for CSI_VC3CFGR2 register *****************/ +#define CSI_VC3CFGR2_DT1_Pos (0UL) +#define CSI_VC3CFGR2_DT1_Msk (0x3FUL << CSI_VC3CFGR2_DT1_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR2_DT1 CSI_VC3CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT1FT_Pos (8UL) +#define CSI_VC3CFGR2_DT1FT_Msk (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR2_DT1FT CSI_VC3CFGR2_DT1FT_Msk /*!< Data type 1 format */ +#define CSI_VC3CFGR2_DT2_Pos (16UL) +#define CSI_VC3CFGR2_DT2_Msk (0x3FUL << CSI_VC3CFGR2_DT2_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR2_DT2 CSI_VC3CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */ +#define CSI_VC3CFGR2_DT2FT_Pos (24UL) +#define CSI_VC3CFGR2_DT2FT_Msk (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR2_DT2FT CSI_VC3CFGR2_DT2FT_Msk /*!< Data type 2 format */ + +/***************** Bit definition for CSI_VC3CFGR3 register *****************/ +#define CSI_VC3CFGR3_DT3_Pos (0UL) +#define CSI_VC3CFGR3_DT3_Msk (0x3FUL << CSI_VC3CFGR3_DT3_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR3_DT3 CSI_VC3CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT3FT_Pos (8UL) +#define CSI_VC3CFGR3_DT3FT_Msk (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR3_DT3FT CSI_VC3CFGR3_DT3FT_Msk /*!< Data type 3 format */ +#define CSI_VC3CFGR3_DT4_Pos (16UL) +#define CSI_VC3CFGR3_DT4_Msk (0x3FUL << CSI_VC3CFGR3_DT4_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR3_DT4 CSI_VC3CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */ +#define CSI_VC3CFGR3_DT4FT_Pos (24UL) +#define CSI_VC3CFGR3_DT4FT_Msk (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR3_DT4FT CSI_VC3CFGR3_DT4FT_Msk /*!< Data type 4 format */ + +/***************** Bit definition for CSI_VC3CFGR4 register *****************/ +#define CSI_VC3CFGR4_DT5_Pos (0UL) +#define CSI_VC3CFGR4_DT5_Msk (0x3FUL << CSI_VC3CFGR4_DT5_Pos) /*!< 0x0000003F */ +#define CSI_VC3CFGR4_DT5 CSI_VC3CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT5FT_Pos (8UL) +#define CSI_VC3CFGR4_DT5FT_Msk (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos) /*!< 0x00001F00 */ +#define CSI_VC3CFGR4_DT5FT CSI_VC3CFGR4_DT5FT_Msk /*!< Data type 5 format */ +#define CSI_VC3CFGR4_DT6_Pos (16UL) +#define CSI_VC3CFGR4_DT6_Msk (0x3FUL << CSI_VC3CFGR4_DT6_Pos) /*!< 0x003F0000 */ +#define CSI_VC3CFGR4_DT6 CSI_VC3CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */ +#define CSI_VC3CFGR4_DT6FT_Pos (24UL) +#define CSI_VC3CFGR4_DT6FT_Msk (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos) /*!< 0x1F000000 */ +#define CSI_VC3CFGR4_DT6FT CSI_VC3CFGR4_DT6FT_Msk /*!< Data type 6 format */ + +/***************** Bit definition for CSI_LB0CFGR register ******************/ +#define CSI_LB0CFGR_BYTECNT_Pos (0UL) +#define CSI_LB0CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB0CFGR_BYTECNT CSI_LB0CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB0CFGR_LINECNT_Pos (16UL) +#define CSI_LB0CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB0CFGR_LINECNT CSI_LB0CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB1CFGR register ******************/ +#define CSI_LB1CFGR_BYTECNT_Pos (0UL) +#define CSI_LB1CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB1CFGR_BYTECNT CSI_LB1CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB1CFGR_LINECNT_Pos (16UL) +#define CSI_LB1CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB1CFGR_LINECNT CSI_LB1CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB2CFGR register ******************/ +#define CSI_LB2CFGR_BYTECNT_Pos (0UL) +#define CSI_LB2CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB2CFGR_BYTECNT CSI_LB2CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB2CFGR_LINECNT_Pos (16UL) +#define CSI_LB2CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB2CFGR_LINECNT CSI_LB2CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_LB3CFGR register ******************/ +#define CSI_LB3CFGR_BYTECNT_Pos (0UL) +#define CSI_LB3CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */ +#define CSI_LB3CFGR_BYTECNT CSI_LB3CFGR_BYTECNT_Msk /*!< Byte counter */ +#define CSI_LB3CFGR_LINECNT_Pos (16UL) +#define CSI_LB3CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */ +#define CSI_LB3CFGR_LINECNT CSI_LB3CFGR_LINECNT_Msk /*!< Line counter */ + +/***************** Bit definition for CSI_TIM0CFGR register *****************/ +#define CSI_TIM0CFGR_COUNT_Pos (0UL) +#define CSI_TIM0CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM0CFGR_COUNT CSI_TIM0CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM1CFGR register *****************/ +#define CSI_TIM1CFGR_COUNT_Pos (0UL) +#define CSI_TIM1CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM1CFGR_COUNT CSI_TIM1CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM2CFGR register *****************/ +#define CSI_TIM2CFGR_COUNT_Pos (0UL) +#define CSI_TIM2CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM2CFGR_COUNT CSI_TIM2CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/***************** Bit definition for CSI_TIM3CFGR register *****************/ +#define CSI_TIM3CFGR_COUNT_Pos (0UL) +#define CSI_TIM3CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos) /*!< 0x01FFFFFF */ +#define CSI_TIM3CFGR_COUNT CSI_TIM3CFGR_COUNT_Msk /*!< Clock cycle counter */ + +/****************** Bit definition for CSI_LMCFGR register ******************/ +#define CSI_LMCFGR_LANENB_Pos (8UL) +#define CSI_LMCFGR_LANENB_Msk (0x7UL << CSI_LMCFGR_LANENB_Pos) /*!< 0x00000700 */ +#define CSI_LMCFGR_LANENB CSI_LMCFGR_LANENB_Msk /*!< Number of lanes */ +#define CSI_LMCFGR_DL0MAP_Pos (16UL) +#define CSI_LMCFGR_DL0MAP_Msk (0x7UL << CSI_LMCFGR_DL0MAP_Pos) /*!< 0x00070000 */ +#define CSI_LMCFGR_DL0MAP CSI_LMCFGR_DL0MAP_Msk /*!< Physical mapping of logical data lane 0 */ +#define CSI_LMCFGR_DL1MAP_Pos (20UL) +#define CSI_LMCFGR_DL1MAP_Msk (0x7UL << CSI_LMCFGR_DL1MAP_Pos) /*!< 0x00700000 */ +#define CSI_LMCFGR_DL1MAP CSI_LMCFGR_DL1MAP_Msk /*!< Physical mapping of logical data lane 1 */ + +/****************** Bit definition for CSI_PRGITR register ******************/ +#define CSI_PRGITR_LB0VC_Pos (0UL) +#define CSI_PRGITR_LB0VC_Msk (0x3UL << CSI_PRGITR_LB0VC_Pos) /*!< 0x00000003 */ +#define CSI_PRGITR_LB0VC CSI_PRGITR_LB0VC_Msk /*!< Line/Byte counter 0 linked to a virtual channel */ +#define CSI_PRGITR_LB0EN_Pos (3UL) +#define CSI_PRGITR_LB0EN_Msk (0x1UL << CSI_PRGITR_LB0EN_Pos) /*!< 0x00000008 */ +#define CSI_PRGITR_LB0EN CSI_PRGITR_LB0EN_Msk /*!< Line/Byte 0counter enable */ +#define CSI_PRGITR_LB1VC_Pos (4UL) +#define CSI_PRGITR_LB1VC_Msk (0x3UL << CSI_PRGITR_LB1VC_Pos) /*!< 0x00000030 */ +#define CSI_PRGITR_LB1VC CSI_PRGITR_LB1VC_Msk /*!< Line/Byte counter 1 linked to a virtual channel */ +#define CSI_PRGITR_LB1EN_Pos (7UL) +#define CSI_PRGITR_LB1EN_Msk (0x1UL << CSI_PRGITR_LB1EN_Pos) /*!< 0x00000080 */ +#define CSI_PRGITR_LB1EN CSI_PRGITR_LB1EN_Msk /*!< Line/Byte 1 counter enable */ +#define CSI_PRGITR_LB2VC_Pos (8UL) +#define CSI_PRGITR_LB2VC_Msk (0x3UL << CSI_PRGITR_LB2VC_Pos) /*!< 0x00000300 */ +#define CSI_PRGITR_LB2VC CSI_PRGITR_LB2VC_Msk /*!< Line/Byte counter 2 linked to a virtual channel */ +#define CSI_PRGITR_LB2EN_Pos (11UL) +#define CSI_PRGITR_LB2EN_Msk (0x1UL << CSI_PRGITR_LB2EN_Pos) /*!< 0x00000800 */ +#define CSI_PRGITR_LB2EN CSI_PRGITR_LB2EN_Msk /*!< Line/Byte 2 counter enable */ +#define CSI_PRGITR_LB3VC_Pos (12UL) +#define CSI_PRGITR_LB3VC_Msk (0x3UL << CSI_PRGITR_LB3VC_Pos) /*!< 0x00003000 */ +#define CSI_PRGITR_LB3VC CSI_PRGITR_LB3VC_Msk /*!< Line/Byte counter 3 linked to a virtual channel */ +#define CSI_PRGITR_LB3EN_Pos (15UL) +#define CSI_PRGITR_LB3EN_Msk (0x1UL << CSI_PRGITR_LB3EN_Pos) /*!< 0x00008000 */ +#define CSI_PRGITR_LB3EN CSI_PRGITR_LB3EN_Msk /*!< Line/Byte 3 counter enable */ +#define CSI_PRGITR_TIM0VC_Pos (16UL) +#define CSI_PRGITR_TIM0VC_Msk (0x3UL << CSI_PRGITR_TIM0VC_Pos) /*!< 0x00030000 */ +#define CSI_PRGITR_TIM0VC CSI_PRGITR_TIM0VC_Msk /*!< TIM0 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM0EOF_Pos (18UL) +#define CSI_PRGITR_TIM0EOF_Msk (0x1UL << CSI_PRGITR_TIM0EOF_Pos) /*!< 0x00040000 */ +#define CSI_PRGITR_TIM0EOF CSI_PRGITR_TIM0EOF_Msk /*!< TIM0 base time starting from the end of frame */ +#define CSI_PRGITR_TIM0EN_Pos (19UL) +#define CSI_PRGITR_TIM0EN_Msk (0x1UL << CSI_PRGITR_TIM0EN_Pos) /*!< 0x00080000 */ +#define CSI_PRGITR_TIM0EN CSI_PRGITR_TIM0EN_Msk /*!< TIM0 base time enable */ +#define CSI_PRGITR_TIM1VC_Pos (20UL) +#define CSI_PRGITR_TIM1VC_Msk (0x3UL << CSI_PRGITR_TIM1VC_Pos) /*!< 0x00300000 */ +#define CSI_PRGITR_TIM1VC CSI_PRGITR_TIM1VC_Msk /*!< TIM1 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM1EOF_Pos (22UL) +#define CSI_PRGITR_TIM1EOF_Msk (0x1UL << CSI_PRGITR_TIM1EOF_Pos) /*!< 0x00400000 */ +#define CSI_PRGITR_TIM1EOF CSI_PRGITR_TIM1EOF_Msk /*!< TIM1 base time starting from the end of frame */ +#define CSI_PRGITR_TIM1EN_Pos (23UL) +#define CSI_PRGITR_TIM1EN_Msk (0x1UL << CSI_PRGITR_TIM1EN_Pos) /*!< 0x00800000 */ +#define CSI_PRGITR_TIM1EN CSI_PRGITR_TIM1EN_Msk /*!< TIM1 base time enable */ +#define CSI_PRGITR_TIM2VC_Pos (24UL) +#define CSI_PRGITR_TIM2VC_Msk (0x3UL << CSI_PRGITR_TIM2VC_Pos) /*!< 0x03000000 */ +#define CSI_PRGITR_TIM2VC CSI_PRGITR_TIM2VC_Msk /*!< TIM2 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM2EOF_Pos (26UL) +#define CSI_PRGITR_TIM2EOF_Msk (0x1UL << CSI_PRGITR_TIM2EOF_Pos) /*!< 0x04000000 */ +#define CSI_PRGITR_TIM2EOF CSI_PRGITR_TIM2EOF_Msk /*!< TIM2 base time starting from the end of frame */ +#define CSI_PRGITR_TIM2EN_Pos (27UL) +#define CSI_PRGITR_TIM2EN_Msk (0x1UL << CSI_PRGITR_TIM2EN_Pos) /*!< 0x08000000 */ +#define CSI_PRGITR_TIM2EN CSI_PRGITR_TIM2EN_Msk /*!< TIM2 base time enable */ +#define CSI_PRGITR_TIM3VC_Pos (28UL) +#define CSI_PRGITR_TIM3VC_Msk (0x3UL << CSI_PRGITR_TIM3VC_Pos) /*!< 0x30000000 */ +#define CSI_PRGITR_TIM3VC CSI_PRGITR_TIM3VC_Msk /*!< TIM3 base time linked to a virtual channel */ +#define CSI_PRGITR_TIM3EOF_Pos (30UL) +#define CSI_PRGITR_TIM3EOF_Msk (0x1UL << CSI_PRGITR_TIM3EOF_Pos) /*!< 0x40000000 */ +#define CSI_PRGITR_TIM3EOF CSI_PRGITR_TIM3EOF_Msk /*!< TIM3 base time starting from the end of frame */ +#define CSI_PRGITR_TIM3EN_Pos (31UL) +#define CSI_PRGITR_TIM3EN_Msk (0x1UL << CSI_PRGITR_TIM3EN_Pos) /*!< 0x80000000 */ +#define CSI_PRGITR_TIM3EN CSI_PRGITR_TIM3EN_Msk /*!< TIM3 base time enable */ + +/******************* Bit definition for CSI_WDR register ********************/ +#define CSI_WDR_CNT_Pos (0UL) +#define CSI_WDR_CNT_Msk (0xFFFFFFFFUL << CSI_WDR_CNT_Pos) /*!< 0xFFFFFFFF */ +#define CSI_WDR_CNT CSI_WDR_CNT_Msk /*!< Watchdog counter */ + +/******************* Bit definition for CSI_IER0 register *******************/ +#define CSI_IER0_LB0IE_Pos (0UL) +#define CSI_IER0_LB0IE_Msk (0x1UL << CSI_IER0_LB0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER0_LB0IE CSI_IER0_LB0IE_Msk /*!< Line byte counter 0 interrupt enable */ +#define CSI_IER0_LB1IE_Pos (1UL) +#define CSI_IER0_LB1IE_Msk (0x1UL << CSI_IER0_LB1IE_Pos) /*!< 0x00000002 */ +#define CSI_IER0_LB1IE CSI_IER0_LB1IE_Msk /*!< Line byte counter 1 interrupt enable */ +#define CSI_IER0_LB2IE_Pos (2UL) +#define CSI_IER0_LB2IE_Msk (0x1UL << CSI_IER0_LB2IE_Pos) /*!< 0x00000004 */ +#define CSI_IER0_LB2IE CSI_IER0_LB2IE_Msk /*!< Line byte counter 2 interrupt enable */ +#define CSI_IER0_LB3IE_Pos (3UL) +#define CSI_IER0_LB3IE_Msk (0x1UL << CSI_IER0_LB3IE_Pos) /*!< 0x00000008 */ +#define CSI_IER0_LB3IE CSI_IER0_LB3IE_Msk /*!< Line byte counter 3 interrupt enable */ +#define CSI_IER0_TIM0IE_Pos (4UL) +#define CSI_IER0_TIM0IE_Msk (0x1UL << CSI_IER0_TIM0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER0_TIM0IE CSI_IER0_TIM0IE_Msk /*!< Timer 0 interrupt enable */ +#define CSI_IER0_TIM1IE_Pos (5UL) +#define CSI_IER0_TIM1IE_Msk (0x1UL << CSI_IER0_TIM1IE_Pos) /*!< 0x00000020 */ +#define CSI_IER0_TIM1IE CSI_IER0_TIM1IE_Msk /*!< Timer 1 interrupt enable */ +#define CSI_IER0_TIM2IE_Pos (6UL) +#define CSI_IER0_TIM2IE_Msk (0x1UL << CSI_IER0_TIM2IE_Pos) /*!< 0x00000040 */ +#define CSI_IER0_TIM2IE CSI_IER0_TIM2IE_Msk /*!< Timer 2 interrupt enable */ +#define CSI_IER0_TIM3IE_Pos (7UL) +#define CSI_IER0_TIM3IE_Msk (0x1UL << CSI_IER0_TIM3IE_Pos) /*!< 0x00000080 */ +#define CSI_IER0_TIM3IE CSI_IER0_TIM3IE_Msk /*!< Timer 3 interrupt enable */ +#define CSI_IER0_SOF0IE_Pos (8UL) +#define CSI_IER0_SOF0IE_Msk (0x1UL << CSI_IER0_SOF0IE_Pos) /*!< 0x00000100 */ +#define CSI_IER0_SOF0IE CSI_IER0_SOF0IE_Msk /*!< Start of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_SOF1IE_Pos (9UL) +#define CSI_IER0_SOF1IE_Msk (0x1UL << CSI_IER0_SOF1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER0_SOF1IE CSI_IER0_SOF1IE_Msk /*!< Start of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_SOF2IE_Pos (10UL) +#define CSI_IER0_SOF2IE_Msk (0x1UL << CSI_IER0_SOF2IE_Pos) /*!< 0x00000400 */ +#define CSI_IER0_SOF2IE CSI_IER0_SOF2IE_Msk /*!< Start of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_SOF3IE_Pos (11UL) +#define CSI_IER0_SOF3IE_Msk (0x1UL << CSI_IER0_SOF3IE_Pos) /*!< 0x00000800 */ +#define CSI_IER0_SOF3IE CSI_IER0_SOF3IE_Msk /*!< Start of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_EOF0IE_Pos (12UL) +#define CSI_IER0_EOF0IE_Msk (0x1UL << CSI_IER0_EOF0IE_Pos) /*!< 0x00001000 */ +#define CSI_IER0_EOF0IE CSI_IER0_EOF0IE_Msk /*!< End of frame for virtual channel 0 interrupt enable */ +#define CSI_IER0_EOF1IE_Pos (13UL) +#define CSI_IER0_EOF1IE_Msk (0x1UL << CSI_IER0_EOF1IE_Pos) /*!< 0x00002000 */ +#define CSI_IER0_EOF1IE CSI_IER0_EOF1IE_Msk /*!< End of frame for virtual channel 1 interrupt enable */ +#define CSI_IER0_EOF2IE_Pos (14UL) +#define CSI_IER0_EOF2IE_Msk (0x1UL << CSI_IER0_EOF2IE_Pos) /*!< 0x00004000 */ +#define CSI_IER0_EOF2IE CSI_IER0_EOF2IE_Msk /*!< End of frame for virtual channel 2 interrupt enable */ +#define CSI_IER0_EOF3IE_Pos (15UL) +#define CSI_IER0_EOF3IE_Msk (0x1UL << CSI_IER0_EOF3IE_Pos) /*!< 0x00008000 */ +#define CSI_IER0_EOF3IE CSI_IER0_EOF3IE_Msk /*!< End of frame for virtual channel 3 interrupt enable */ +#define CSI_IER0_SPKTIE_Pos (16UL) +#define CSI_IER0_SPKTIE_Msk (0x1UL << CSI_IER0_SPKTIE_Pos) /*!< 0x00010000 */ +#define CSI_IER0_SPKTIE CSI_IER0_SPKTIE_Msk /*!< Short packet interrupt enable */ +#define CSI_IER0_CCFIFOFIE_Pos (21UL) +#define CSI_IER0_CCFIFOFIE_Msk (0x1UL << CSI_IER0_CCFIFOFIE_Pos) /*!< 0x00200000 */ +#define CSI_IER0_CCFIFOFIE CSI_IER0_CCFIFOFIE_Msk /*!< Clock changer FIFO full interrupt enable */ +#define CSI_IER0_CRCERRIE_Pos (24UL) +#define CSI_IER0_CRCERRIE_Msk (0x1UL << CSI_IER0_CRCERRIE_Pos) /*!< 0x01000000 */ +#define CSI_IER0_CRCERRIE CSI_IER0_CRCERRIE_Msk /*!< CRC error interrupt enable */ +#define CSI_IER0_ECCERRIE_Pos (25UL) +#define CSI_IER0_ECCERRIE_Msk (0x1UL << CSI_IER0_ECCERRIE_Pos) /*!< 0x02000000 */ +#define CSI_IER0_ECCERRIE CSI_IER0_ECCERRIE_Msk /*!< ECC error interrupt enable */ +#define CSI_IER0_CECCERRIE_Pos (26UL) +#define CSI_IER0_CECCERRIE_Msk (0x1UL << CSI_IER0_CECCERRIE_Pos) /*!< 0x04000000 */ +#define CSI_IER0_CECCERRIE CSI_IER0_CECCERRIE_Msk /*!< Corrected ECC error interrupt enable */ +#define CSI_IER0_IDERRIE_Pos (27UL) +#define CSI_IER0_IDERRIE_Msk (0x1UL << CSI_IER0_IDERRIE_Pos) /*!< 0x08000000 */ +#define CSI_IER0_IDERRIE CSI_IER0_IDERRIE_Msk /*!< Data type ID error interrupt enable */ +#define CSI_IER0_SPKTERRIE_Pos (28UL) +#define CSI_IER0_SPKTERRIE_Msk (0x1UL << CSI_IER0_SPKTERRIE_Pos) /*!< 0x10000000 */ +#define CSI_IER0_SPKTERRIE CSI_IER0_SPKTERRIE_Msk /*!< Short packet error interrupt enable */ +#define CSI_IER0_WDERRIE_Pos (29UL) +#define CSI_IER0_WDERRIE_Msk (0x1UL << CSI_IER0_WDERRIE_Pos) /*!< 0x20000000 */ +#define CSI_IER0_WDERRIE CSI_IER0_WDERRIE_Msk /*!< Watchdog error interrupt enable */ +#define CSI_IER0_SYNCERRIE_Pos (30UL) +#define CSI_IER0_SYNCERRIE_Msk (0x1UL << CSI_IER0_SYNCERRIE_Pos) /*!< 0x40000000 */ +#define CSI_IER0_SYNCERRIE CSI_IER0_SYNCERRIE_Msk /*!< Invalid synchronization error interrupt enable */ + +/******************* Bit definition for CSI_IER1 register *******************/ +#define CSI_IER1_ESOTDL0IE_Pos (0UL) +#define CSI_IER1_ESOTDL0IE_Msk (0x1UL << CSI_IER1_ESOTDL0IE_Pos) /*!< 0x00000001 */ +#define CSI_IER1_ESOTDL0IE CSI_IER1_ESOTDL0IE_Msk /*!< Start of transmission error interrupt enable on lane 0 */ +#define CSI_IER1_ESOTSYNCDL0IE_Pos (1UL) +#define CSI_IER1_ESOTSYNCDL0IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos) /*!< 0x00000002 */ +#define CSI_IER1_ESOTSYNCDL0IE CSI_IER1_ESOTSYNCDL0IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 0 */ +#define CSI_IER1_EESCDL0IE_Pos (2UL) +#define CSI_IER1_EESCDL0IE_Msk (0x1UL << CSI_IER1_EESCDL0IE_Pos) /*!< 0x00000004 */ +#define CSI_IER1_EESCDL0IE CSI_IER1_EESCDL0IE_Msk /*!< D-PHY_RX lane 0 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL0IE_Pos (3UL) +#define CSI_IER1_ESYNCESCDL0IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos) /*!< 0x00000008 */ +#define CSI_IER1_ESYNCESCDL0IE CSI_IER1_ESYNCESCDL0IE_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL0IE_Pos (4UL) +#define CSI_IER1_ECTRLDL0IE_Msk (0x1UL << CSI_IER1_ECTRLDL0IE_Pos) /*!< 0x00000010 */ +#define CSI_IER1_ECTRLDL0IE CSI_IER1_ECTRLDL0IE_Msk /*!< D-PHY_RX lane 0 control error interrupt enable */ +#define CSI_IER1_ESOTDL1IE_Pos (8UL) +#define CSI_IER1_ESOTDL1IE_Msk (0x1UL << CSI_IER1_ESOTDL1IE_Pos) /*!< 0x00000100 */ +#define CSI_IER1_ESOTDL1IE CSI_IER1_ESOTDL1IE_Msk /*!< Start of transmission error interrupt enable on lane 1 */ +#define CSI_IER1_ESOTSYNCDL1IE_Pos (9UL) +#define CSI_IER1_ESOTSYNCDL1IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos) /*!< 0x00000200 */ +#define CSI_IER1_ESOTSYNCDL1IE CSI_IER1_ESOTSYNCDL1IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 1 */ +#define CSI_IER1_EESCDL1IE_Pos (10UL) +#define CSI_IER1_EESCDL1IE_Msk (0x1UL << CSI_IER1_EESCDL1IE_Pos) /*!< 0x00000400 */ +#define CSI_IER1_EESCDL1IE CSI_IER1_EESCDL1IE_Msk /*!< D-PHY_RX lane 1 escape entry error interrupt enable */ +#define CSI_IER1_ESYNCESCDL1IE_Pos (11UL) +#define CSI_IER1_ESYNCESCDL1IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos) /*!< 0x00000800 */ +#define CSI_IER1_ESYNCESCDL1IE CSI_IER1_ESYNCESCDL1IE_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */ +#define CSI_IER1_ECTRLDL1IE_Pos (12UL) +#define CSI_IER1_ECTRLDL1IE_Msk (0x1UL << CSI_IER1_ECTRLDL1IE_Pos) /*!< 0x00001000 */ +#define CSI_IER1_ECTRLDL1IE CSI_IER1_ECTRLDL1IE_Msk /*!< D-PHY_RX lane 1 control error interrupt enable */ + +/******************* Bit definition for CSI_SR0 register ********************/ +#define CSI_SR0_LB0F_Pos (0UL) +#define CSI_SR0_LB0F_Msk (0x1UL << CSI_SR0_LB0F_Pos) /*!< 0x00000001 */ +#define CSI_SR0_LB0F CSI_SR0_LB0F_Msk /*!< Line byte counter 0 flag */ +#define CSI_SR0_LB1F_Pos (1UL) +#define CSI_SR0_LB1F_Msk (0x1UL << CSI_SR0_LB1F_Pos) /*!< 0x00000002 */ +#define CSI_SR0_LB1F CSI_SR0_LB1F_Msk /*!< Line byte counter 1 flag */ +#define CSI_SR0_LB2F_Pos (2UL) +#define CSI_SR0_LB2F_Msk (0x1UL << CSI_SR0_LB2F_Pos) /*!< 0x00000004 */ +#define CSI_SR0_LB2F CSI_SR0_LB2F_Msk /*!< Line byte counter 2 flag */ +#define CSI_SR0_LB3F_Pos (3UL) +#define CSI_SR0_LB3F_Msk (0x1UL << CSI_SR0_LB3F_Pos) /*!< 0x00000008 */ +#define CSI_SR0_LB3F CSI_SR0_LB3F_Msk /*!< Line byte counter 3 flag */ +#define CSI_SR0_TIM0F_Pos (4UL) +#define CSI_SR0_TIM0F_Msk (0x1UL << CSI_SR0_TIM0F_Pos) /*!< 0x00000010 */ +#define CSI_SR0_TIM0F CSI_SR0_TIM0F_Msk /*!< Timer 0 flag */ +#define CSI_SR0_TIM1F_Pos (5UL) +#define CSI_SR0_TIM1F_Msk (0x1UL << CSI_SR0_TIM1F_Pos) /*!< 0x00000020 */ +#define CSI_SR0_TIM1F CSI_SR0_TIM1F_Msk /*!< Timer 1 flag */ +#define CSI_SR0_TIM2F_Pos (6UL) +#define CSI_SR0_TIM2F_Msk (0x1UL << CSI_SR0_TIM2F_Pos) /*!< 0x00000040 */ +#define CSI_SR0_TIM2F CSI_SR0_TIM2F_Msk /*!< Timer 2 flag */ +#define CSI_SR0_TIM3F_Pos (7UL) +#define CSI_SR0_TIM3F_Msk (0x1UL << CSI_SR0_TIM3F_Pos) /*!< 0x00000080 */ +#define CSI_SR0_TIM3F CSI_SR0_TIM3F_Msk /*!< Timer 3 flag */ +#define CSI_SR0_SOF0F_Pos (8UL) +#define CSI_SR0_SOF0F_Msk (0x1UL << CSI_SR0_SOF0F_Pos) /*!< 0x00000100 */ +#define CSI_SR0_SOF0F CSI_SR0_SOF0F_Msk /*!< Start of frame flag for virtual channel 0 */ +#define CSI_SR0_SOF1F_Pos (9UL) +#define CSI_SR0_SOF1F_Msk (0x1UL << CSI_SR0_SOF1F_Pos) /*!< 0x00000200 */ +#define CSI_SR0_SOF1F CSI_SR0_SOF1F_Msk /*!< Start of frame flag for virtual channel 1 */ +#define CSI_SR0_SOF2F_Pos (10UL) +#define CSI_SR0_SOF2F_Msk (0x1UL << CSI_SR0_SOF2F_Pos) /*!< 0x00000400 */ +#define CSI_SR0_SOF2F CSI_SR0_SOF2F_Msk /*!< Start of frame flag for virtual channel 2 */ +#define CSI_SR0_SOF3F_Pos (11UL) +#define CSI_SR0_SOF3F_Msk (0x1UL << CSI_SR0_SOF3F_Pos) /*!< 0x00000800 */ +#define CSI_SR0_SOF3F CSI_SR0_SOF3F_Msk /*!< Start of frame flag for virtual channel 3 */ +#define CSI_SR0_EOF0F_Pos (12UL) +#define CSI_SR0_EOF0F_Msk (0x1UL << CSI_SR0_EOF0F_Pos) /*!< 0x00001000 */ +#define CSI_SR0_EOF0F CSI_SR0_EOF0F_Msk /*!< End of frame flag for virtual channel 0 */ +#define CSI_SR0_EOF1F_Pos (13UL) +#define CSI_SR0_EOF1F_Msk (0x1UL << CSI_SR0_EOF1F_Pos) /*!< 0x00002000 */ +#define CSI_SR0_EOF1F CSI_SR0_EOF1F_Msk /*!< End of frame flag for virtual channel 1 */ +#define CSI_SR0_EOF2F_Pos (14UL) +#define CSI_SR0_EOF2F_Msk (0x1UL << CSI_SR0_EOF2F_Pos) /*!< 0x00004000 */ +#define CSI_SR0_EOF2F CSI_SR0_EOF2F_Msk /*!< End of frame flag for virtual channel 2 */ +#define CSI_SR0_EOF3F_Pos (15UL) +#define CSI_SR0_EOF3F_Msk (0x1UL << CSI_SR0_EOF3F_Pos) /*!< 0x00008000 */ +#define CSI_SR0_EOF3F CSI_SR0_EOF3F_Msk /*!< End of frame flag for virtual channel 3 */ +#define CSI_SR0_SPKTF_Pos (16UL) +#define CSI_SR0_SPKTF_Msk (0x1UL << CSI_SR0_SPKTF_Pos) /*!< 0x00010000 */ +#define CSI_SR0_SPKTF CSI_SR0_SPKTF_Msk /*!< Short packet flag */ +#define CSI_SR0_VC0STATEF_Pos (17UL) +#define CSI_SR0_VC0STATEF_Msk (0x1UL << CSI_SR0_VC0STATEF_Pos) /*!< 0x00020000 */ +#define CSI_SR0_VC0STATEF CSI_SR0_VC0STATEF_Msk /*!< Virtual channel 0 state flag */ +#define CSI_SR0_VC1STATEF_Pos (18UL) +#define CSI_SR0_VC1STATEF_Msk (0x1UL << CSI_SR0_VC1STATEF_Pos) /*!< 0x00040000 */ +#define CSI_SR0_VC1STATEF CSI_SR0_VC1STATEF_Msk /*!< Virtual channel 1 state flag */ +#define CSI_SR0_VC2STATEF_Pos (19UL) +#define CSI_SR0_VC2STATEF_Msk (0x1UL << CSI_SR0_VC2STATEF_Pos) /*!< 0x00080000 */ +#define CSI_SR0_VC2STATEF CSI_SR0_VC2STATEF_Msk /*!< Virtual channel 2 state flag */ +#define CSI_SR0_VC3STATEF_Pos (20UL) +#define CSI_SR0_VC3STATEF_Msk (0x1UL << CSI_SR0_VC3STATEF_Pos) /*!< 0x00100000 */ +#define CSI_SR0_VC3STATEF CSI_SR0_VC3STATEF_Msk /*!< Virtual channel 3 state flag */ +#define CSI_SR0_CCFIFOFF_Pos (21UL) +#define CSI_SR0_CCFIFOFF_Msk (0x1UL << CSI_SR0_CCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_SR0_CCFIFOFF CSI_SR0_CCFIFOFF_Msk /*!< Clock changer FIFO full flag */ +#define CSI_SR0_CRCERRF_Pos (24UL) +#define CSI_SR0_CRCERRF_Msk (0x1UL << CSI_SR0_CRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_SR0_CRCERRF CSI_SR0_CRCERRF_Msk /*!< CRC error flag */ +#define CSI_SR0_ECCERRF_Pos (25UL) +#define CSI_SR0_ECCERRF_Msk (0x1UL << CSI_SR0_ECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_SR0_ECCERRF CSI_SR0_ECCERRF_Msk /*!< ECC error flag */ +#define CSI_SR0_CECCERRF_Pos (26UL) +#define CSI_SR0_CECCERRF_Msk (0x1UL << CSI_SR0_CECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_SR0_CECCERRF CSI_SR0_CECCERRF_Msk /*!< Corrected ECC error flag */ +#define CSI_SR0_IDERRF_Pos (27UL) +#define CSI_SR0_IDERRF_Msk (0x1UL << CSI_SR0_IDERRF_Pos) /*!< 0x08000000 */ +#define CSI_SR0_IDERRF CSI_SR0_IDERRF_Msk /*!< Data type ID error flag */ +#define CSI_SR0_SPKTERRF_Pos (28UL) +#define CSI_SR0_SPKTERRF_Msk (0x1UL << CSI_SR0_SPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_SR0_SPKTERRF CSI_SR0_SPKTERRF_Msk /*!< Short packet error flag */ +#define CSI_SR0_WDERRF_Pos (29UL) +#define CSI_SR0_WDERRF_Msk (0x1UL << CSI_SR0_WDERRF_Pos) /*!< 0x20000000 */ +#define CSI_SR0_WDERRF CSI_SR0_WDERRF_Msk /*!< Watchdog error flag */ +#define CSI_SR0_SYNCERRF_Pos (30UL) +#define CSI_SR0_SYNCERRF_Msk (0x1UL << CSI_SR0_SYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_SR0_SYNCERRF CSI_SR0_SYNCERRF_Msk /*!< Invalid synchronization error flag */ + +/******************* Bit definition for CSI_SR1 register ********************/ +#define CSI_SR1_ESOTDL0F_Pos (0UL) +#define CSI_SR1_ESOTDL0F_Msk (0x1UL << CSI_SR1_ESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_SR1_ESOTDL0F CSI_SR1_ESOTDL0F_Msk /*!< Start of transmission error flag on lane 0 */ +#define CSI_SR1_ESOTSYNCDL0F_Pos (1UL) +#define CSI_SR1_ESOTSYNCDL0F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_SR1_ESOTSYNCDL0F CSI_SR1_ESOTSYNCDL0F_Msk /*!< Start of transmission synchronization error flag on lane 0 */ +#define CSI_SR1_EESCDL0F_Pos (2UL) +#define CSI_SR1_EESCDL0F_Msk (0x1UL << CSI_SR1_EESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_SR1_EESCDL0F CSI_SR1_EESCDL0F_Msk /*!< D-PHY_RX lane 0 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL0F_Pos (3UL) +#define CSI_SR1_ESYNCESCDL0F_Msk (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_SR1_ESYNCESCDL0F CSI_SR1_ESYNCESCDL0F_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL0F_Pos (4UL) +#define CSI_SR1_ECTRLDL0F_Msk (0x1UL << CSI_SR1_ECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_SR1_ECTRLDL0F CSI_SR1_ECTRLDL0F_Msk /*!< D-PHY_RX lane 0 control error flag */ +#define CSI_SR1_ESOTDL1F_Pos (8UL) +#define CSI_SR1_ESOTDL1F_Msk (0x1UL << CSI_SR1_ESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_SR1_ESOTDL1F CSI_SR1_ESOTDL1F_Msk /*!< Start of transmission error flag on lane 1 */ +#define CSI_SR1_ESOTSYNCDL1F_Pos (9UL) +#define CSI_SR1_ESOTSYNCDL1F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_SR1_ESOTSYNCDL1F CSI_SR1_ESOTSYNCDL1F_Msk /*!< Start of transmission synchronization error flag on lane 1 */ +#define CSI_SR1_EESCDL1F_Pos (10UL) +#define CSI_SR1_EESCDL1F_Msk (0x1UL << CSI_SR1_EESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_SR1_EESCDL1F CSI_SR1_EESCDL1F_Msk /*!< D-PHY_RX lane 1 escape entry error flag */ +#define CSI_SR1_ESYNCESCDL1F_Pos (11UL) +#define CSI_SR1_ESYNCESCDL1F_Msk (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_SR1_ESYNCESCDL1F CSI_SR1_ESYNCESCDL1F_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_SR1_ECTRLDL1F_Pos (12UL) +#define CSI_SR1_ECTRLDL1F_Msk (0x1UL << CSI_SR1_ECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_SR1_ECTRLDL1F CSI_SR1_ECTRLDL1F_Msk /*!< D-PHY_RX lane 1 control error flag */ +#define CSI_SR1_ACTDL0F_Pos (16UL) +#define CSI_SR1_ACTDL0F_Msk (0x1UL << CSI_SR1_ACTDL0F_Pos) /*!< 0x00010000 */ +#define CSI_SR1_ACTDL0F CSI_SR1_ACTDL0F_Msk /*!< D-PHY_RX lane 0 High speed reception active */ +#define CSI_SR1_SYNCDL0F_Pos (17UL) +#define CSI_SR1_SYNCDL0F_Msk (0x1UL << CSI_SR1_SYNCDL0F_Pos) /*!< 0x00020000 */ +#define CSI_SR1_SYNCDL0F CSI_SR1_SYNCDL0F_Msk /*!< D-PHY_RX lane 0 receiver synchronization observed */ +#define CSI_SR1_SKCALDL0F_Pos (18UL) +#define CSI_SR1_SKCALDL0F_Msk (0x1UL << CSI_SR1_SKCALDL0F_Pos) /*!< 0x00040000 */ +#define CSI_SR1_SKCALDL0F CSI_SR1_SKCALDL0F_Msk /*!< D-PHY_RX lane 0 High speed skew calibration */ +#define CSI_SR1_STOPDL0F_Pos (19UL) +#define CSI_SR1_STOPDL0F_Msk (0x1UL << CSI_SR1_STOPDL0F_Pos) /*!< 0x00080000 */ +#define CSI_SR1_STOPDL0F CSI_SR1_STOPDL0F_Msk /*!< D-PHY_RX receiver data lane 0 in stop state */ +#define CSI_SR1_ULPNDL0F_Pos (20UL) +#define CSI_SR1_ULPNDL0F_Msk (0x1UL << CSI_SR1_ULPNDL0F_Pos) /*!< 0x00100000 */ +#define CSI_SR1_ULPNDL0F CSI_SR1_ULPNDL0F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */ +#define CSI_SR1_ACTDL1F_Pos (22UL) +#define CSI_SR1_ACTDL1F_Msk (0x1UL << CSI_SR1_ACTDL1F_Pos) /*!< 0x00400000 */ +#define CSI_SR1_ACTDL1F CSI_SR1_ACTDL1F_Msk /*!< D-PHY_RX lane 1 High speed reception active */ +#define CSI_SR1_SYNCDL1F_Pos (23UL) +#define CSI_SR1_SYNCDL1F_Msk (0x1UL << CSI_SR1_SYNCDL1F_Pos) /*!< 0x00800000 */ +#define CSI_SR1_SYNCDL1F CSI_SR1_SYNCDL1F_Msk /*!< D-PHY_RX lane 1 receiver synchronization observed */ +#define CSI_SR1_SKCALDL1F_Pos (24UL) +#define CSI_SR1_SKCALDL1F_Msk (0x1UL << CSI_SR1_SKCALDL1F_Pos) /*!< 0x01000000 */ +#define CSI_SR1_SKCALDL1F CSI_SR1_SKCALDL1F_Msk /*!< D-PHY_RX lane 1 High speed skew calibration */ +#define CSI_SR1_STOPDL1F_Pos (25UL) +#define CSI_SR1_STOPDL1F_Msk (0x1UL << CSI_SR1_STOPDL1F_Pos) /*!< 0x02000000 */ +#define CSI_SR1_STOPDL1F CSI_SR1_STOPDL1F_Msk /*!< D-PHY_RX receiver data lane 1 in stop state */ +#define CSI_SR1_ULPNDL1F_Pos (26UL) +#define CSI_SR1_ULPNDL1F_Msk (0x1UL << CSI_SR1_ULPNDL1F_Pos) /*!< 0x04000000 */ +#define CSI_SR1_ULPNDL1F CSI_SR1_ULPNDL1F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */ +#define CSI_SR1_STOPCLF_Pos (28UL) +#define CSI_SR1_STOPCLF_Msk (0x1UL << CSI_SR1_STOPCLF_Pos) /*!< 0x10000000 */ +#define CSI_SR1_STOPCLF CSI_SR1_STOPCLF_Msk /*!< D-PHY_RX receiver in stop state for the clock lane */ +#define CSI_SR1_ULPNACTF_Pos (29UL) +#define CSI_SR1_ULPNACTF_Msk (0x1UL << CSI_SR1_ULPNACTF_Pos) /*!< 0x20000000 */ +#define CSI_SR1_ULPNACTF CSI_SR1_ULPNACTF_Msk /*!< D-PHY_RX receiver ULP state (not) active */ +#define CSI_SR1_ULPNCLF_Pos (30UL) +#define CSI_SR1_ULPNCLF_Msk (0x1UL << CSI_SR1_ULPNCLF_Pos) /*!< 0x40000000 */ +#define CSI_SR1_ULPNCLF CSI_SR1_ULPNCLF_Msk /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */ +#define CSI_SR1_ACTCLF_Pos (31UL) +#define CSI_SR1_ACTCLF_Msk (0x1UL << CSI_SR1_ACTCLF_Pos) /*!< 0x80000000 */ +#define CSI_SR1_ACTCLF CSI_SR1_ACTCLF_Msk /*!< D-PHY_RX receiver clock active flag */ + +/******************* Bit definition for CSI_FCR0 register *******************/ +#define CSI_FCR0_CLB0F_Pos (0UL) +#define CSI_FCR0_CLB0F_Msk (0x1UL << CSI_FCR0_CLB0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR0_CLB0F CSI_FCR0_CLB0F_Msk /*!< Clear Line byte counter 0 flag */ +#define CSI_FCR0_CLB1F_Pos (1UL) +#define CSI_FCR0_CLB1F_Msk (0x1UL << CSI_FCR0_CLB1F_Pos) /*!< 0x00000002 */ +#define CSI_FCR0_CLB1F CSI_FCR0_CLB1F_Msk /*!< Clear Line byte counter 1 flag */ +#define CSI_FCR0_CLB2F_Pos (2UL) +#define CSI_FCR0_CLB2F_Msk (0x1UL << CSI_FCR0_CLB2F_Pos) /*!< 0x00000004 */ +#define CSI_FCR0_CLB2F CSI_FCR0_CLB2F_Msk /*!< Clear Line byte counter 2 flag */ +#define CSI_FCR0_CLB3F_Pos (3UL) +#define CSI_FCR0_CLB3F_Msk (0x1UL << CSI_FCR0_CLB3F_Pos) /*!< 0x00000008 */ +#define CSI_FCR0_CLB3F CSI_FCR0_CLB3F_Msk /*!< Clear Line byte counter 3 flag */ +#define CSI_FCR0_CTIM0F_Pos (4UL) +#define CSI_FCR0_CTIM0F_Msk (0x1UL << CSI_FCR0_CTIM0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR0_CTIM0F CSI_FCR0_CTIM0F_Msk /*!< Clear Timer 0 flag */ +#define CSI_FCR0_CTIM1F_Pos (5UL) +#define CSI_FCR0_CTIM1F_Msk (0x1UL << CSI_FCR0_CTIM1F_Pos) /*!< 0x00000020 */ +#define CSI_FCR0_CTIM1F CSI_FCR0_CTIM1F_Msk /*!< Clear Timer 1 flag */ +#define CSI_FCR0_CTIM2F_Pos (6UL) +#define CSI_FCR0_CTIM2F_Msk (0x1UL << CSI_FCR0_CTIM2F_Pos) /*!< 0x00000040 */ +#define CSI_FCR0_CTIM2F CSI_FCR0_CTIM2F_Msk /*!< Clear Timer 2 flag */ +#define CSI_FCR0_CTIM3F_Pos (7UL) +#define CSI_FCR0_CTIM3F_Msk (0x1UL << CSI_FCR0_CTIM3F_Pos) /*!< 0x00000080 */ +#define CSI_FCR0_CTIM3F CSI_FCR0_CTIM3F_Msk /*!< Clear Timer 3 flag */ +#define CSI_FCR0_CSOF0F_Pos (8UL) +#define CSI_FCR0_CSOF0F_Msk (0x1UL << CSI_FCR0_CSOF0F_Pos) /*!< 0x00000100 */ +#define CSI_FCR0_CSOF0F CSI_FCR0_CSOF0F_Msk /*!< Clear Start of frame flag for virtual channel 0 */ +#define CSI_FCR0_CSOF1F_Pos (9UL) +#define CSI_FCR0_CSOF1F_Msk (0x1UL << CSI_FCR0_CSOF1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR0_CSOF1F CSI_FCR0_CSOF1F_Msk /*!< Clear Start of frame flag for virtual channel 1 */ +#define CSI_FCR0_CSOF2F_Pos (10UL) +#define CSI_FCR0_CSOF2F_Msk (0x1UL << CSI_FCR0_CSOF2F_Pos) /*!< 0x00000400 */ +#define CSI_FCR0_CSOF2F CSI_FCR0_CSOF2F_Msk /*!< Clear Start of frame flag for virtual channel 2 */ +#define CSI_FCR0_CSOF3F_Pos (11UL) +#define CSI_FCR0_CSOF3F_Msk (0x1UL << CSI_FCR0_CSOF3F_Pos) /*!< 0x00000800 */ +#define CSI_FCR0_CSOF3F CSI_FCR0_CSOF3F_Msk /*!< Clear Start of frame flag for virtual channel 3 */ +#define CSI_FCR0_CEOF0F_Pos (12UL) +#define CSI_FCR0_CEOF0F_Msk (0x1UL << CSI_FCR0_CEOF0F_Pos) /*!< 0x00001000 */ +#define CSI_FCR0_CEOF0F CSI_FCR0_CEOF0F_Msk /*!< Clear End of frame flag for virtual channel 0 */ +#define CSI_FCR0_CEOF1F_Pos (13UL) +#define CSI_FCR0_CEOF1F_Msk (0x1UL << CSI_FCR0_CEOF1F_Pos) /*!< 0x00002000 */ +#define CSI_FCR0_CEOF1F CSI_FCR0_CEOF1F_Msk /*!< Clear End of frame flag for virtual channel 1 */ +#define CSI_FCR0_CEOF2F_Pos (14UL) +#define CSI_FCR0_CEOF2F_Msk (0x1UL << CSI_FCR0_CEOF2F_Pos) /*!< 0x00004000 */ +#define CSI_FCR0_CEOF2F CSI_FCR0_CEOF2F_Msk /*!< Clear End of frame flag for virtual channel 2 */ +#define CSI_FCR0_CEOF3F_Pos (15UL) +#define CSI_FCR0_CEOF3F_Msk (0x1UL << CSI_FCR0_CEOF3F_Pos) /*!< 0x00008000 */ +#define CSI_FCR0_CEOF3F CSI_FCR0_CEOF3F_Msk /*!< Clear End of frame flag for virtual channel 3 */ +#define CSI_FCR0_CSPKTF_Pos (16UL) +#define CSI_FCR0_CSPKTF_Msk (0x1UL << CSI_FCR0_CSPKTF_Pos) /*!< 0x00010000 */ +#define CSI_FCR0_CSPKTF CSI_FCR0_CSPKTF_Msk /*!< Clear Short packet flag */ +#define CSI_FCR0_CCCFIFOFF_Pos (21UL) +#define CSI_FCR0_CCCFIFOFF_Msk (0x1UL << CSI_FCR0_CCCFIFOFF_Pos) /*!< 0x00200000 */ +#define CSI_FCR0_CCCFIFOFF CSI_FCR0_CCCFIFOFF_Msk /*!< Clear Clock changer FIFO full flag */ +#define CSI_FCR0_CCRCERRF_Pos (24UL) +#define CSI_FCR0_CCRCERRF_Msk (0x1UL << CSI_FCR0_CCRCERRF_Pos) /*!< 0x01000000 */ +#define CSI_FCR0_CCRCERRF CSI_FCR0_CCRCERRF_Msk /*!< Clear CRC error flag */ +#define CSI_FCR0_CECCERRF_Pos (25UL) +#define CSI_FCR0_CECCERRF_Msk (0x1UL << CSI_FCR0_CECCERRF_Pos) /*!< 0x02000000 */ +#define CSI_FCR0_CECCERRF CSI_FCR0_CECCERRF_Msk /*!< Clear ECC error flag */ +#define CSI_FCR0_CCECCERRF_Pos (26UL) +#define CSI_FCR0_CCECCERRF_Msk (0x1UL << CSI_FCR0_CCECCERRF_Pos) /*!< 0x04000000 */ +#define CSI_FCR0_CCECCERRF CSI_FCR0_CCECCERRF_Msk /*!< Clear Corrected ECC error flag */ +#define CSI_FCR0_CIDERRF_Pos (27UL) +#define CSI_FCR0_CIDERRF_Msk (0x1UL << CSI_FCR0_CIDERRF_Pos) /*!< 0x08000000 */ +#define CSI_FCR0_CIDERRF CSI_FCR0_CIDERRF_Msk /*!< Clear Data type ID error flag */ +#define CSI_FCR0_CSPKTERRF_Pos (28UL) +#define CSI_FCR0_CSPKTERRF_Msk (0x1UL << CSI_FCR0_CSPKTERRF_Pos) /*!< 0x10000000 */ +#define CSI_FCR0_CSPKTERRF CSI_FCR0_CSPKTERRF_Msk /*!< Clear Short packet error flag */ +#define CSI_FCR0_CWDERRF_Pos (29UL) +#define CSI_FCR0_CWDERRF_Msk (0x1UL << CSI_FCR0_CWDERRF_Pos) /*!< 0x20000000 */ +#define CSI_FCR0_CWDERRF CSI_FCR0_CWDERRF_Msk /*!< Clear Watchdog error flag */ +#define CSI_FCR0_CSYNCERRF_Pos (30UL) +#define CSI_FCR0_CSYNCERRF_Msk (0x1UL << CSI_FCR0_CSYNCERRF_Pos) /*!< 0x40000000 */ +#define CSI_FCR0_CSYNCERRF CSI_FCR0_CSYNCERRF_Msk /*!< Clear Invalid synchronization error flag */ + +/******************* Bit definition for CSI_FCR1 register *******************/ +#define CSI_FCR1_CESOTDL0F_Pos (0UL) +#define CSI_FCR1_CESOTDL0F_Msk (0x1UL << CSI_FCR1_CESOTDL0F_Pos) /*!< 0x00000001 */ +#define CSI_FCR1_CESOTDL0F CSI_FCR1_CESOTDL0F_Msk /*!< Clear Start of transmission error flag on lane 0 */ +#define CSI_FCR1_CESOTSYNCDL0F_Pos (1UL) +#define CSI_FCR1_CESOTSYNCDL0F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos) /*!< 0x00000002 */ +#define CSI_FCR1_CESOTSYNCDL0F CSI_FCR1_CESOTSYNCDL0F_Msk /*!< Clear Start of transmission synchronization error flag on lane 0 */ +#define CSI_FCR1_CEESCDL0F_Pos (2UL) +#define CSI_FCR1_CEESCDL0F_Msk (0x1UL << CSI_FCR1_CEESCDL0F_Pos) /*!< 0x00000004 */ +#define CSI_FCR1_CEESCDL0F CSI_FCR1_CEESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL0F_Pos (3UL) +#define CSI_FCR1_CESYNCESCDL0F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos) /*!< 0x00000008 */ +#define CSI_FCR1_CESYNCESCDL0F CSI_FCR1_CESYNCESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL0F_Pos (4UL) +#define CSI_FCR1_CECTRLDL0F_Msk (0x1UL << CSI_FCR1_CECTRLDL0F_Pos) /*!< 0x00000010 */ +#define CSI_FCR1_CECTRLDL0F CSI_FCR1_CECTRLDL0F_Msk /*!< Clear D-PHY_RX lane 0 control error flag */ +#define CSI_FCR1_CESOTDL1F_Pos (8UL) +#define CSI_FCR1_CESOTDL1F_Msk (0x1UL << CSI_FCR1_CESOTDL1F_Pos) /*!< 0x00000100 */ +#define CSI_FCR1_CESOTDL1F CSI_FCR1_CESOTDL1F_Msk /*!< Clear Start of transmission error flag on lane 1 */ +#define CSI_FCR1_CESOTSYNCDL1F_Pos (9UL) +#define CSI_FCR1_CESOTSYNCDL1F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos) /*!< 0x00000200 */ +#define CSI_FCR1_CESOTSYNCDL1F CSI_FCR1_CESOTSYNCDL1F_Msk /*!< Clear Start of transmission synchronization error flag on lane 1 */ +#define CSI_FCR1_CEESCDL1F_Pos (10UL) +#define CSI_FCR1_CEESCDL1F_Msk (0x1UL << CSI_FCR1_CEESCDL1F_Pos) /*!< 0x00000400 */ +#define CSI_FCR1_CEESCDL1F CSI_FCR1_CEESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 escape entry error flag */ +#define CSI_FCR1_CESYNCESCDL1F_Pos (11UL) +#define CSI_FCR1_CESYNCESCDL1F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos) /*!< 0x00000800 */ +#define CSI_FCR1_CESYNCESCDL1F CSI_FCR1_CESYNCESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */ +#define CSI_FCR1_CECTRLDL1F_Pos (12UL) +#define CSI_FCR1_CECTRLDL1F_Msk (0x1UL << CSI_FCR1_CECTRLDL1F_Pos) /*!< 0x00001000 */ +#define CSI_FCR1_CECTRLDL1F CSI_FCR1_CECTRLDL1F_Msk /*!< Clear D-PHY_RX lane 1 control error flag */ + +/****************** Bit definition for CSI_SPDFR register *******************/ +#define CSI_SPDFR_DATAFIELD_Pos (0UL) +#define CSI_SPDFR_DATAFIELD_Msk (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos) /*!< 0x0000FFFF */ +#define CSI_SPDFR_DATAFIELD CSI_SPDFR_DATAFIELD_Msk /*!< Data field */ +#define CSI_SPDFR_DATATYPE_Pos (16UL) +#define CSI_SPDFR_DATATYPE_Msk (0x3FUL << CSI_SPDFR_DATATYPE_Pos) /*!< 0x003F0000 */ +#define CSI_SPDFR_DATATYPE CSI_SPDFR_DATATYPE_Msk /*!< Data type class */ +#define CSI_SPDFR_VCHANNEL_Pos (22UL) +#define CSI_SPDFR_VCHANNEL_Msk (0x3UL << CSI_SPDFR_VCHANNEL_Pos) /*!< 0x00C00000 */ +#define CSI_SPDFR_VCHANNEL CSI_SPDFR_VCHANNEL_Msk /*!< Virtual channel */ + +/******************* Bit definition for CSI_ERR1 register *******************/ +#define CSI_ERR1_CRCDTERR_Pos (0UL) +#define CSI_ERR1_CRCDTERR_Msk (0x3FUL << CSI_ERR1_CRCDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR1_CRCDTERR CSI_ERR1_CRCDTERR_Msk /*!< Data type having a CRC error */ +#define CSI_ERR1_CRCVCERR_Pos (6UL) +#define CSI_ERR1_CRCVCERR_Msk (0x3UL << CSI_ERR1_CRCVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR1_CRCVCERR CSI_ERR1_CRCVCERR_Msk /*!< Virtual channel having a CRC error */ +#define CSI_ERR1_CECCDTERR_Pos (8UL) +#define CSI_ERR1_CECCDTERR_Msk (0x3FUL << CSI_ERR1_CECCDTERR_Pos) /*!< 0x00003F00 */ +#define CSI_ERR1_CECCDTERR CSI_ERR1_CECCDTERR_Msk /*!< Data type having a corrected ECC error */ +#define CSI_ERR1_CECCVCERR_Pos (14UL) +#define CSI_ERR1_CECCVCERR_Msk (0x3UL << CSI_ERR1_CECCVCERR_Pos) /*!< 0x0000C000 */ +#define CSI_ERR1_CECCVCERR CSI_ERR1_CECCVCERR_Msk /*!< Virtual channel having a corrected ECC error */ +#define CSI_ERR1_IDDTERR_Pos (16UL) +#define CSI_ERR1_IDDTERR_Msk (0x3FUL << CSI_ERR1_IDDTERR_Pos) /*!< 0x003F0000 */ +#define CSI_ERR1_IDDTERR CSI_ERR1_IDDTERR_Msk /*!< Data type in error */ +#define CSI_ERR1_IDVCERR_Pos (22UL) +#define CSI_ERR1_IDVCERR_Msk (0x3UL << CSI_ERR1_IDVCERR_Pos) /*!< 0x00C00000 */ +#define CSI_ERR1_IDVCERR CSI_ERR1_IDVCERR_Msk /*!< Virtual channel having ID error */ + +/******************* Bit definition for CSI_ERR2 register *******************/ +#define CSI_ERR2_SPKTDTERR_Pos (0UL) +#define CSI_ERR2_SPKTDTERR_Msk (0x3FUL << CSI_ERR2_SPKTDTERR_Pos) /*!< 0x0000003F */ +#define CSI_ERR2_SPKTDTERR CSI_ERR2_SPKTDTERR_Msk /*!< Data type having a short packet error */ +#define CSI_ERR2_SPKTVCERR_Pos (6UL) +#define CSI_ERR2_SPKTVCERR_Msk (0x3UL << CSI_ERR2_SPKTVCERR_Pos) /*!< 0x000000C0 */ +#define CSI_ERR2_SPKTVCERR CSI_ERR2_SPKTVCERR_Msk /*!< Virtual channel having a short packet error */ +#define CSI_ERR2_WDVCERR_Pos (16UL) +#define CSI_ERR2_WDVCERR_Msk (0x3UL << CSI_ERR2_WDVCERR_Pos) /*!< 0x00030000 */ +#define CSI_ERR2_WDVCERR CSI_ERR2_WDVCERR_Msk /*!< Virtual channel having a watchdog error */ +#define CSI_ERR2_SYNCVCERR_Pos (18UL) +#define CSI_ERR2_SYNCVCERR_Msk (0x3UL << CSI_ERR2_SYNCVCERR_Pos) /*!< 0x000C0000 */ +#define CSI_ERR2_SYNCVCERR CSI_ERR2_SYNCVCERR_Msk /*!< Virtual channel having synchronization error */ + +/******************* Bit definition for CSI_PRCR register *******************/ +#define CSI_PRCR_PEN_Pos (1UL) +#define CSI_PRCR_PEN_Msk (0x1UL << CSI_PRCR_PEN_Pos) /*!< 0x00000002 */ +#define CSI_PRCR_PEN CSI_PRCR_PEN_Msk /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */ + +/******************* Bit definition for CSI_PMCR register *******************/ +#define CSI_PMCR_FRXMDL0_Pos (0UL) +#define CSI_PMCR_FRXMDL0_Msk (0x1UL << CSI_PMCR_FRXMDL0_Pos) /*!< 0x00000001 */ +#define CSI_PMCR_FRXMDL0 CSI_PMCR_FRXMDL0_Msk /*!< Force to Rx Mode the Data Lane 0 */ +#define CSI_PMCR_FRXMDL1_Pos (1UL) +#define CSI_PMCR_FRXMDL1_Msk (0x1UL << CSI_PMCR_FRXMDL1_Pos) /*!< 0x00000002 */ +#define CSI_PMCR_FRXMDL1 CSI_PMCR_FRXMDL1_Msk /*!< Force to Rx Mode the Data Lane 1 */ +#define CSI_PMCR_FTXSMDL0_Pos (2UL) +#define CSI_PMCR_FTXSMDL0_Msk (0x1UL << CSI_PMCR_FTXSMDL0_Pos) /*!< 0x00000004 */ +#define CSI_PMCR_FTXSMDL0 CSI_PMCR_FTXSMDL0_Msk /*!< Force to Tx Stop Mode the Data Lane 0 */ +#define CSI_PMCR_DTDL_Pos (4UL) +#define CSI_PMCR_DTDL_Msk (0x1UL << CSI_PMCR_DTDL_Pos) /*!< 0x00000010 */ +#define CSI_PMCR_DTDL CSI_PMCR_DTDL_Msk /*!< Disable Turn-around Data Lane 0 */ +#define CSI_PMCR_RTDL0_Pos (8UL) +#define CSI_PMCR_RTDL0_Msk (0x1UL << CSI_PMCR_RTDL0_Pos) /*!< 0x00000100 */ +#define CSI_PMCR_RTDL0 CSI_PMCR_RTDL0_Msk /*!< Turn-around Request Data Lane 0 */ +#define CSI_PMCR_TUESDL0_Pos (12UL) +#define CSI_PMCR_TUESDL0_Msk (0x1UL << CSI_PMCR_TUESDL0_Pos) /*!< 0x00001000 */ +#define CSI_PMCR_TUESDL0 CSI_PMCR_TUESDL0_Msk /*!< Tx ULP Escape-mode Data Lane 0 */ +#define CSI_PMCR_TUEXDL0_Pos (16UL) +#define CSI_PMCR_TUEXDL0_Msk (0x1UL << CSI_PMCR_TUEXDL0_Pos) /*!< 0x00010000 */ +#define CSI_PMCR_TUEXDL0 CSI_PMCR_TUEXDL0_Msk /*!< Tx ULP Exit-sequence Data Lane 0 */ + +/******************* Bit definition for CSI_PFCR register *******************/ +#define CSI_PFCR_CCFR_Pos (0UL) +#define CSI_PFCR_CCFR_Msk (0x3FUL << CSI_PFCR_CCFR_Pos) /*!< 0x0000003F */ +#define CSI_PFCR_CCFR CSI_PFCR_CCFR_Msk /*!< Configuration Clock Frequency Range selection */ +#define CSI_PFCR_HSFR_Pos (8UL) +#define CSI_PFCR_HSFR_Msk (0x7FUL << CSI_PFCR_HSFR_Pos) /*!< 0x00007F00 */ +#define CSI_PFCR_HSFR CSI_PFCR_HSFR_Msk /*!< PHY-high-speed Frequency Range selection */ +#define CSI_PFCR_DLD_Pos (16UL) +#define CSI_PFCR_DLD_Msk (0x1UL << CSI_PFCR_DLD_Pos) /*!< 0x00010000 */ +#define CSI_PFCR_DLD CSI_PFCR_DLD_Msk /*!< Data Lane Direction of lane0 */ + +/****************** Bit definition for CSI_PTCR0 register *******************/ +#define CSI_PTCR0_TCKEN_Pos (0UL) +#define CSI_PTCR0_TCKEN_Msk (0x1UL << CSI_PTCR0_TCKEN_Pos) /*!< 0x00000001 */ +#define CSI_PTCR0_TCKEN CSI_PTCR0_TCKEN_Msk /*!< Test-interface Clock Enable for the TDI bus into the PHY */ +#define CSI_PTCR0_TRSEN_Pos (1UL) +#define CSI_PTCR0_TRSEN_Msk (0x1UL << CSI_PTCR0_TRSEN_Pos) /*!< 0x00000002 */ +#define CSI_PTCR0_TRSEN CSI_PTCR0_TRSEN_Msk /*!< Test-interface Reset Enable for the TDI bus into the PHY */ + +/****************** Bit definition for CSI_PTCR1 register *******************/ +#define CSI_PTCR1_TDI_Pos (0UL) +#define CSI_PTCR1_TDI_Msk (0xFFUL << CSI_PTCR1_TDI_Pos) /*!< 0x000000FF */ +#define CSI_PTCR1_TDI CSI_PTCR1_TDI_Msk /*!< Test-interface Data In */ +#define CSI_PTCR1_TWM_Pos (16UL) +#define CSI_PTCR1_TWM_Msk (0x1UL << CSI_PTCR1_TWM_Pos) /*!< 0x00010000 */ +#define CSI_PTCR1_TWM CSI_PTCR1_TWM_Msk /*!< Test-interface Write Mode selector */ + +/******************* Bit definition for CSI_PTSR register *******************/ +#define CSI_PTSR_TDO_Pos (0UL) +#define CSI_PTSR_TDO_Msk (0xFFUL << CSI_PTSR_TDO_Pos) /*!< 0x000000FF */ +#define CSI_PTSR_TDO CSI_PTSR_TDO_Msk /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */ + + +/*********************************************************************************/ +/* */ +/* DBGMCU */ +/* */ +/*********************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register ****************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0UL) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device ID */ +#define DBGMCU_IDCODE_REV_ID_Pos (16UL) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision ID */ + +/******************** Bit definition for DBGMCU_CR register ********************/ +#define DBGMCU_CR_DBG_SLEEP_Pos (0UL) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Allow debug in Sleep mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1UL) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Allow debug in Stop mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2UL) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Allow debug in Standby mode */ +#define DBGMCU_CR_DBGCLKEN_Pos (20UL) +#define DBGMCU_CR_DBGCLKEN_Msk (0x1UL << DBGMCU_CR_DBGCLKEN_Pos) /*!< 0x00100000 */ +#define DBGMCU_CR_DBGCLKEN DBGMCU_CR_DBGCLKEN_Msk /*!< Debug clock enable through software */ +#define DBGMCU_CR_TRACECLKEN_Pos (21UL) +#define DBGMCU_CR_TRACECLKEN_Msk (0x1UL << DBGMCU_CR_TRACECLKEN_Pos) /*!< 0x00200000 */ +#define DBGMCU_CR_TRACECLKEN DBGMCU_CR_TRACECLKEN_Msk /*!< TPIU export clock enable through software */ +#define DBGMCU_CR_DBTRGOEN_Pos (28UL) +#define DBGMCU_CR_DBTRGOEN_Msk (0x1UL << DBGMCU_CR_DBTRGOEN_Pos) /*!< 0x10000000 */ +#define DBGMCU_CR_DBTRGOEN DBGMCU_CR_DBTRGOEN_Msk /*!< DBTRGIO connection control */ +#define DBGMCU_CR_HLT_TSGEN_EN_Pos (31UL) +#define DBGMCU_CR_HLT_TSGEN_EN_Msk (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos) /*!< 0x80000000 */ +#define DBGMCU_CR_HLT_TSGEN_EN DBGMCU_CR_HLT_TSGEN_EN_Msk /*!< TSGEN halt enable */ + +/******************** Bit definition for DBGMCU_APB1LFZ1 register ***************/ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos (0UL) +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk /*!< TIM2 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos (1UL) +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk /*!< TIM3 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos (2UL) +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk /*!< TIM4 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos (3UL) +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk /*!< TIM5 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos (4UL) +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk /*!< TIM6 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos (5UL) +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk /*!< TIM7 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos (6UL) +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk /*!< TIM12 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos (7UL) +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk /*!< TIM13 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos (8UL) +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk /*!< TIM14 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos (9UL) +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos (11UL) +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk /*!< WWDG1 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos (12UL) +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk /*!< TIM10 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos (13UL) +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk /*!< TIM11 stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos (21UL) +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos (22UL) +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos (23UL) +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos (24UL) +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos) /*!< 0x01000000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk /*!< I3C1 SMBUS timeout stop in debug */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos (25UL) +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk /*!< I3C2 SMBUS timeout stop in debug */ + +/******************** Bit definition for DBGMCU_APB1HFZ1 register ***************/ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos (8UL) +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk /*!< FDCAN stop in debug */ + +/******************** Bit definition for DBGMCU_APB2FZ1 register ***************/ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos (0UL) +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB2FZ1_DBG_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk /*!< TIM1 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos (1UL) +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB2FZ1_DBG_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk /*!< TIM8 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos (15UL) +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB2FZ1_DBG_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk /*!< TIM18 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos (16UL) +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2FZ1_DBG_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk /*!< TIM15 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos (17UL) +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2FZ1_DBG_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk /*!< TIM16 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos (18UL) +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2FZ1_DBG_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk /*!< TIM17 stop in debug */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos (19UL) +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_APB2FZ1_DBG_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk /*!< TIM9 stop in debug */ + +/******************** Bit definition for DBGMCU_APB4FZ1 register ***************/ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos (8UL) +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB4FZ1_DBG_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk /*!< I2C4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos (9UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk /*!< LPTIM2 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos (10UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk /*!< LPTIM3 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos (11UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk /*!< LPTIM4 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos (12UL) +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk /*!< LPTIM5 stop in debug */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos (16UL) +#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB4FZ1_DBG_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk /*!< RTC stop in debug */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos (18UL) +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB4FZ1_DBG_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk /*!< IWDG stop in debug */ + +/******************** Bit definition for DBGMCU_APB5FZ1 register ***************/ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos (4UL) +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk /*!< GFXTIM stop in debug */ + +/******************** Bit definition for DBGMCU_AHB1FZ1 register ***************/ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk /*!< GPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk /*!< GPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk /*!< GPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk /*!< GPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk /*!< GPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk /*!< GPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk /*!< GPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk /*!< GPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk /*!< GPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk /*!< GPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk /*!< GPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk /*!< GPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk /*!< GPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk /*!< GPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk /*!< GPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk /*!< GPDMA1_CH15 suspend in debug */ + +/******************** Bit definition for DBGMCU_AHB5FZ1 register ***************/ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk /*!< HPDMA1_CH0 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk /*!< HPDMA1_CH1 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk /*!< HPDMA1_CH2 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk /*!< HPDMA1_CH3 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk /*!< HPDMA1_CH4 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk /*!< HPDMA1_CH5 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk /*!< HPDMA1_CH6 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk /*!< HPDMA1_CH7 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos (8UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk /*!< HPDMA1_CH8 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos (9UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk /*!< HPDMA1_CH9 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos (10UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk /*!< HPDMA1_CH10 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos (11UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk /*!< HPDMA1_CH11 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos (12UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk /*!< HPDMA1_CH12 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos (13UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk /*!< HPDMA1_CH13 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos (14UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk /*!< HPDMA1_CH14 suspend in debug */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos (15UL) +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk /*!< HPDMA1_CH15 suspend in debug */ +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos (16UL) +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos) /*!< 0x00010000 */ +#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk /*!< NPU stop in debug mode */ + +/******************** Bit definition for DBGMCU_SR register ***************/ +#define DBGMCU_SR_AP0_PRESENT_Pos (0UL) +#define DBGMCU_SR_AP0_PRESENT_Msk (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos) /*!< 0x00000001 */ +#define DBGMCU_SR_AP0_PRESENT DBGMCU_SR_AP0_PRESENT_Msk /*!< Access point 0 presence */ +#define DBGMCU_SR_AP1_PRESENT_Pos (1UL) +#define DBGMCU_SR_AP1_PRESENT_Msk (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos) /*!< 0x00000002 */ +#define DBGMCU_SR_AP1_PRESENT DBGMCU_SR_AP1_PRESENT_Msk /*!< Access point 1 presence */ +#define DBGMCU_SR_AP0_ENABLE_Pos (16UL) +#define DBGMCU_SR_AP0_ENABLE_Msk (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos) /*!< 0x00010000 */ +#define DBGMCU_SR_AP0_ENABLE DBGMCU_SR_AP0_ENABLE_Msk /*!< Access point 0 enable */ +#define DBGMCU_SR_AP1_ENABLE_Pos (17UL) +#define DBGMCU_SR_AP1_ENABLE_Msk (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos) /*!< 0x00020000 */ +#define DBGMCU_SR_AP1_ENABLE DBGMCU_SR_AP1_ENABLE_Msk /*!< Access point 1 enable */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_HOST register **********************/ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_HOST_MESSAGE DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk /*!< Message[31:0] */ + +/****************** Bit definition for DBGMCU_DBG_AUTH_DEV register ***********/ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos (0UL) +#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_DBG_AUTH_DEV_MESSAGE DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk /*!< Message[31:0] */ + +/******************** Bit definition for DBGMCU_DBG_AUTH_ACK register ***************/ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos (0UL) +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos) /*!< 0x00000001 */ +#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk /*!< Access status to DBG_AUTH_HOST register */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos (1UL) +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos) /*!< 0x00000002 */ +#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk /*!< Access status to DBG_AUTH_DEV register */ + + +/******************************************************************************/ +/* */ +/* DCMI */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DCMI_CR register ******************/ +#define DCMI_CR_CAPTURE_Pos (0UL) +#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ +#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk +#define DCMI_CR_CM_Pos (1UL) +#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */ +#define DCMI_CR_CM DCMI_CR_CM_Msk +#define DCMI_CR_CROP_Pos (2UL) +#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ +#define DCMI_CR_CROP DCMI_CR_CROP_Msk +#define DCMI_CR_JPEG_Pos (3UL) +#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ +#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk +#define DCMI_CR_ESS_Pos (4UL) +#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ +#define DCMI_CR_ESS DCMI_CR_ESS_Msk +#define DCMI_CR_PCKPOL_Pos (5UL) +#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk +#define DCMI_CR_HSPOL_Pos (6UL) +#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk +#define DCMI_CR_VSPOL_Pos (7UL) +#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk +#define DCMI_CR_FCRC_Pos (8UL) +#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */ +#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */ +#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */ +#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */ +#define DCMI_CR_EDM_Pos (10UL) +#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */ +#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */ +#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */ +#define DCMI_CR_ENABLE_Pos (14UL) +#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk +#define DCMI_CR_BSM_Pos (16UL) +#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */ +#define DCMI_CR_BSM DCMI_CR_BSM_Msk +#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */ +#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */ +#define DCMI_CR_OEBS_Pos (18UL) +#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ +#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk +#define DCMI_CR_LSM_Pos (19UL) +#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ +#define DCMI_CR_LSM DCMI_CR_LSM_Msk +#define DCMI_CR_OELS_Pos (20UL) +#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ +#define DCMI_CR_OELS DCMI_CR_OELS_Msk +#define DCMI_CR_PSDM_Pos (31UL) +#define DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) /*!< 0x00000000 */ +#define DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/ + +/******************** Bits definition for DCMI_SR register ******************/ +#define DCMI_SR_HSYNC_Pos (0UL) +#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ +#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk +#define DCMI_SR_VSYNC_Pos (1UL) +#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ +#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk +#define DCMI_SR_FNE_Pos (2UL) +#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ +#define DCMI_SR_FNE DCMI_SR_FNE_Msk + +/******************** Bits definition for DCMI_RIS register ****************/ +#define DCMI_RIS_FRAME_RIS_Pos (0UL) +#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ +#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk +#define DCMI_RIS_OVR_RIS_Pos (1UL) +#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk +#define DCMI_RIS_ERR_RIS_Pos (2UL) +#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ +#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk +#define DCMI_RIS_VSYNC_RIS_Pos (3UL) +#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ +#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk +#define DCMI_RIS_LINE_RIS_Pos (4UL) +#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ +#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk + +/******************** Bits definition for DCMI_IER register *****************/ +#define DCMI_IER_FRAME_IE_Pos (0UL) +#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ +#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk +#define DCMI_IER_OVR_IE_Pos (1UL) +#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk +#define DCMI_IER_ERR_IE_Pos (2UL) +#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ +#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk +#define DCMI_IER_VSYNC_IE_Pos (3UL) +#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ +#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk +#define DCMI_IER_LINE_IE_Pos (4UL) +#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ +#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk + +/******************** Bits definition for DCMI_MIS register *****************/ +#define DCMI_MIS_FRAME_MIS_Pos (0UL) +#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ +#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk +#define DCMI_MIS_OVR_MIS_Pos (1UL) +#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk +#define DCMI_MIS_ERR_MIS_Pos (2UL) +#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ +#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk +#define DCMI_MIS_VSYNC_MIS_Pos (3UL) +#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ +#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk +#define DCMI_MIS_LINE_MIS_Pos (4UL) +#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ +#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk + +/******************** Bits definition for DCMI_ICR register *****************/ +#define DCMI_ICR_FRAME_ISC_Pos (0UL) +#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ +#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk +#define DCMI_ICR_OVR_ISC_Pos (1UL) +#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk +#define DCMI_ICR_ERR_ISC_Pos (2UL) +#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ +#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk +#define DCMI_ICR_VSYNC_ISC_Pos (3UL) +#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ +#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk +#define DCMI_ICR_LINE_ISC_Pos (4UL) +#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ +#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk + +/******************** Bits definition for DCMI_ESCR register ******************/ +#define DCMI_ESCR_FSC_Pos (0UL) +#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk +#define DCMI_ESCR_LSC_Pos (8UL) +#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk +#define DCMI_ESCR_LEC_Pos (16UL) +#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk +#define DCMI_ESCR_FEC_Pos (24UL) +#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk + +/******************** Bits definition for DCMI_ESUR register ******************/ +#define DCMI_ESUR_FSU_Pos (0UL) +#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk +#define DCMI_ESUR_LSU_Pos (8UL) +#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk +#define DCMI_ESUR_LEU_Pos (16UL) +#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk +#define DCMI_ESUR_FEU_Pos (24UL) +#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk + +/******************** Bits definition for DCMI_CWSTRT register ******************/ +#define DCMI_CWSTRT_HOFFCNT_Pos (0UL) +#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk +#define DCMI_CWSTRT_VST_Pos (16UL) +#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ +#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk + +/******************** Bits definition for DCMI_CWSIZE register ******************/ +#define DCMI_CWSIZE_CAPCNT_Pos (0UL) +#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk +#define DCMI_CWSIZE_VLINE_Pos (16UL) +#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ +#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk + +/******************** Bits definition for DCMI_DR register ******************/ +#define DCMI_DR_BYTE0_Pos (0UL) +#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ +#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk +#define DCMI_DR_BYTE1_Pos (8UL) +#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ +#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk +#define DCMI_DR_BYTE2_Pos (16UL) +#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ +#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk +#define DCMI_DR_BYTE3_Pos (24UL) +#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ +#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk + + +/******************************************************************************/ +/* */ +/* DCMIPP */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DCMIPP_IPGR1 register *****************/ +#define DCMIPP_IPGR1_MEMORYPAGE_Pos (0UL) +#define DCMIPP_IPGR1_MEMORYPAGE_Msk (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPGR1_MEMORYPAGE DCMIPP_IPGR1_MEMORYPAGE_Msk /*!< Memory page size, as power of 2 of 64-byte units: */ +#define DCMIPP_IPGR1_QOS_MODE_Pos (24UL) +#define DCMIPP_IPGR1_QOS_MODE_Msk (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos) /*!< 0x01000000 */ +#define DCMIPP_IPGR1_QOS_MODE DCMIPP_IPGR1_QOS_MODE_Msk /*!< Quality of service */ + +/***************** Bit definition for DCMIPP_IPGR2 register *****************/ +#define DCMIPP_IPGR2_PSTART_Pos (0UL) +#define DCMIPP_IPGR2_PSTART_Msk (0x1UL << DCMIPP_IPGR2_PSTART_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< Request to lock the IP-Plug, to allow reconfiguration */ + +/***************** Bit definition for DCMIPP_IPGR3 register *****************/ +#define DCMIPP_IPGR3_IDLE_Pos (0UL) +#define DCMIPP_IPGR3_IDLE_Msk (0x1UL << DCMIPP_IPGR3_IDLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< Status of IP-Plug */ + +/***************** Bit definition for DCMIPP_IPGR8 register *****************/ +#define DCMIPP_IPGR8_DID_Pos (0UL) +#define DCMIPP_IPGR8_DID_Msk (0x3FUL << DCMIPP_IPGR8_DID_Pos) /*!< 0x0000003F */ +#define DCMIPP_IPGR8_DID DCMIPP_IPGR8_DID_Msk /*!< Division identifier (0x14) */ +#define DCMIPP_IPGR8_REVID_Pos (8UL) +#define DCMIPP_IPGR8_REVID_Msk (0x1FUL << DCMIPP_IPGR8_REVID_Pos) /*!< 0x00001F00 */ +#define DCMIPP_IPGR8_REVID DCMIPP_IPGR8_REVID_Msk /*!< Revision identifier (0x03) */ +#define DCMIPP_IPGR8_ARCHIID_Pos (16UL) +#define DCMIPP_IPGR8_ARCHIID_Msk (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos) /*!< 0x001F0000 */ +#define DCMIPP_IPGR8_ARCHIID DCMIPP_IPGR8_ARCHIID_Msk /*!< Architecture identifier (0x04) */ +#define DCMIPP_IPGR8_IPPID_Pos (24UL) +#define DCMIPP_IPGR8_IPPID_Msk (0xFFUL << DCMIPP_IPGR8_IPPID_Pos) /*!< 0xFF000000 */ +#define DCMIPP_IPGR8_IPPID DCMIPP_IPGR8_IPPID_Msk /*!< IP identifier (0xAA) */ + +/**************** Bit definition for DCMIPP_IPC1R1 register *****************/ +#define DCMIPP_IPC1R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC1R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC1R1_TRAFFIC DCMIPP_IPC1R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC1R1_OTR_Pos (8UL) +#define DCMIPP_IPC1R1_OTR_Msk (0xFUL << DCMIPP_IPC1R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC1R1_OTR DCMIPP_IPC1R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC1R2 register *****************/ +#define DCMIPP_IPC1R2_WLRU_Pos (16UL) +#define DCMIPP_IPC1R2_WLRU_Msk (0xFUL << DCMIPP_IPC1R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC1R2_WLRU DCMIPP_IPC1R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC1R3 register *****************/ +#define DCMIPP_IPC1R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC1R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC1R3_DPREGSTART DCMIPP_IPC1R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC1R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC1R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC1R3_DPREGEND DCMIPP_IPC1R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC2R1 register *****************/ +#define DCMIPP_IPC2R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC2R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC2R1_TRAFFIC DCMIPP_IPC2R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC2R1_OTR_Pos (8UL) +#define DCMIPP_IPC2R1_OTR_Msk (0xFUL << DCMIPP_IPC2R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC2R1_OTR DCMIPP_IPC2R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC2R2 register *****************/ +#define DCMIPP_IPC2R2_WLRU_Pos (16UL) +#define DCMIPP_IPC2R2_WLRU_Msk (0xFUL << DCMIPP_IPC2R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC2R2_WLRU DCMIPP_IPC2R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC2R3 register *****************/ +#define DCMIPP_IPC2R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC2R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC2R3_DPREGSTART DCMIPP_IPC2R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC2R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC2R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC2R3_DPREGEND DCMIPP_IPC2R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC3R1 register *****************/ +#define DCMIPP_IPC3R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC3R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC3R1_TRAFFIC DCMIPP_IPC3R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC3R1_OTR_Pos (8UL) +#define DCMIPP_IPC3R1_OTR_Msk (0xFUL << DCMIPP_IPC3R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC3R1_OTR DCMIPP_IPC3R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC3R2 register *****************/ +#define DCMIPP_IPC3R2_WLRU_Pos (16UL) +#define DCMIPP_IPC3R2_WLRU_Msk (0xFUL << DCMIPP_IPC3R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC3R2_WLRU DCMIPP_IPC3R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC3R3 register *****************/ +#define DCMIPP_IPC3R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC3R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC3R3_DPREGSTART DCMIPP_IPC3R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC3R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC3R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC3R3_DPREGEND DCMIPP_IPC3R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC4R1 register *****************/ +#define DCMIPP_IPC4R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC4R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC4R1_TRAFFIC DCMIPP_IPC4R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC4R1_OTR_Pos (8UL) +#define DCMIPP_IPC4R1_OTR_Msk (0xFUL << DCMIPP_IPC4R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC4R1_OTR DCMIPP_IPC4R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC4R2 register *****************/ +#define DCMIPP_IPC4R2_WLRU_Pos (16UL) +#define DCMIPP_IPC4R2_WLRU_Msk (0xFUL << DCMIPP_IPC4R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC4R2_WLRU DCMIPP_IPC4R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC4R3 register *****************/ +#define DCMIPP_IPC4R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC4R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC4R3_DPREGSTART DCMIPP_IPC4R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC4R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC4R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC4R3_DPREGEND DCMIPP_IPC4R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/**************** Bit definition for DCMIPP_IPC5R1 register *****************/ +#define DCMIPP_IPC5R1_TRAFFIC_Pos (0UL) +#define DCMIPP_IPC5R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos) /*!< 0x00000007 */ +#define DCMIPP_IPC5R1_TRAFFIC DCMIPP_IPC5R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */ +#define DCMIPP_IPC5R1_OTR_Pos (8UL) +#define DCMIPP_IPC5R1_OTR_Msk (0xFUL << DCMIPP_IPC5R1_OTR_Pos) /*!< 0x00000F00 */ +#define DCMIPP_IPC5R1_OTR DCMIPP_IPC5R1_OTR_Msk /*!< max outstanding transactions: */ + +/**************** Bit definition for DCMIPP_IPC5R2 register *****************/ +#define DCMIPP_IPC5R2_WLRU_Pos (16UL) +#define DCMIPP_IPC5R2_WLRU_Msk (0xFUL << DCMIPP_IPC5R2_WLRU_Pos) /*!< 0x000F0000 */ +#define DCMIPP_IPC5R2_WLRU DCMIPP_IPC5R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */ + +/**************** Bit definition for DCMIPP_IPC5R3 register *****************/ +#define DCMIPP_IPC5R3_DPREGSTART_Pos (0UL) +#define DCMIPP_IPC5R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos) /*!< 0x000003FF */ +#define DCMIPP_IPC5R3_DPREGSTART DCMIPP_IPC5R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */ +#define DCMIPP_IPC5R3_DPREGEND_Pos (16UL) +#define DCMIPP_IPC5R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_IPC5R3_DPREGEND DCMIPP_IPC5R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */ + +/*************** Bit definition for DCMIPP_PRHWCFGR register ****************/ + +/***************** Bit definition for DCMIPP_PRCR register ******************/ +#define DCMIPP_PRCR_ESS_Pos (4UL) +#define DCMIPP_PRCR_ESS_Msk (0x1UL << DCMIPP_PRCR_ESS_Pos) /*!< 0x00000010 */ +#define DCMIPP_PRCR_ESS DCMIPP_PRCR_ESS_Msk /*!< Embedded synchronization select */ +#define DCMIPP_PRCR_PCKPOL_Pos (5UL) +#define DCMIPP_PRCR_PCKPOL_Msk (0x1UL << DCMIPP_PRCR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMIPP_PRCR_PCKPOL DCMIPP_PRCR_PCKPOL_Msk /*!< Pixel clock polarity */ +#define DCMIPP_PRCR_HSPOL_Pos (6UL) +#define DCMIPP_PRCR_HSPOL_Msk (0x1UL << DCMIPP_PRCR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRCR_HSPOL DCMIPP_PRCR_HSPOL_Msk /*!< Horizontal synchronization polarity */ +#define DCMIPP_PRCR_VSPOL_Pos (7UL) +#define DCMIPP_PRCR_VSPOL_Msk (0x1UL << DCMIPP_PRCR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMIPP_PRCR_VSPOL DCMIPP_PRCR_VSPOL_Msk /*!< Vertical synchronization polarity */ +#define DCMIPP_PRCR_EDM_Pos (10UL) +#define DCMIPP_PRCR_EDM_Msk (0x7UL << DCMIPP_PRCR_EDM_Pos) /*!< 0x00001C00 */ +#define DCMIPP_PRCR_EDM DCMIPP_PRCR_EDM_Msk /*!< Extended data mode */ +#define DCMIPP_PRCR_ENABLE_Pos (14UL) +#define DCMIPP_PRCR_ENABLE_Msk (0x1UL << DCMIPP_PRCR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMIPP_PRCR_ENABLE DCMIPP_PRCR_ENABLE_Msk /*!< Parallel interface enable */ +#define DCMIPP_PRCR_FORMAT_Pos (16UL) +#define DCMIPP_PRCR_FORMAT_Msk (0xFFUL << DCMIPP_PRCR_FORMAT_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRCR_FORMAT DCMIPP_PRCR_FORMAT_Msk /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */ +#define DCMIPP_PRCR_SWAPCYCLES_Pos (25UL) +#define DCMIPP_PRCR_SWAPCYCLES_Msk (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos) /*!< 0x02000000 */ +#define DCMIPP_PRCR_SWAPCYCLES DCMIPP_PRCR_SWAPCYCLES_Msk /*!< Swap data from cycle 0 vs */ +#define DCMIPP_PRCR_SWAPBITS_Pos (26UL) +#define DCMIPP_PRCR_SWAPBITS_Msk (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos) /*!< 0x04000000 */ +#define DCMIPP_PRCR_SWAPBITS DCMIPP_PRCR_SWAPBITS_Msk /*!< Swap LSB vs */ + +/**************** Bit definition for DCMIPP_PRESCR register *****************/ +#define DCMIPP_PRESCR_FSC_Pos (0UL) +#define DCMIPP_PRESCR_FSC_Msk (0xFFUL << DCMIPP_PRESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESCR_FSC DCMIPP_PRESCR_FSC_Msk /*!< Frame start delimiter code */ +#define DCMIPP_PRESCR_LSC_Pos (8UL) +#define DCMIPP_PRESCR_LSC_Msk (0xFFUL << DCMIPP_PRESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESCR_LSC DCMIPP_PRESCR_LSC_Msk /*!< Line start delimiter code */ +#define DCMIPP_PRESCR_LEC_Pos (16UL) +#define DCMIPP_PRESCR_LEC_Msk (0xFFUL << DCMIPP_PRESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESCR_LEC DCMIPP_PRESCR_LEC_Msk /*!< Line end delimiter code */ +#define DCMIPP_PRESCR_FEC_Pos (24UL) +#define DCMIPP_PRESCR_FEC_Msk (0xFFUL << DCMIPP_PRESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESCR_FEC DCMIPP_PRESCR_FEC_Msk /*!< Frame end delimiter code */ + +/**************** Bit definition for DCMIPP_PRESUR register *****************/ +#define DCMIPP_PRESUR_FSU_Pos (0UL) +#define DCMIPP_PRESUR_FSU_Msk (0xFFUL << DCMIPP_PRESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMIPP_PRESUR_FSU DCMIPP_PRESUR_FSU_Msk /*!< Frame start delimiter unmask */ +#define DCMIPP_PRESUR_LSU_Pos (8UL) +#define DCMIPP_PRESUR_LSU_Msk (0xFFUL << DCMIPP_PRESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_PRESUR_LSU DCMIPP_PRESUR_LSU_Msk /*!< Line start delimiter unmask */ +#define DCMIPP_PRESUR_LEU_Pos (16UL) +#define DCMIPP_PRESUR_LEU_Msk (0xFFUL << DCMIPP_PRESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_PRESUR_LEU DCMIPP_PRESUR_LEU_Msk /*!< Line end delimiter unmask */ +#define DCMIPP_PRESUR_FEU_Pos (24UL) +#define DCMIPP_PRESUR_FEU_Msk (0xFFUL << DCMIPP_PRESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMIPP_PRESUR_FEU DCMIPP_PRESUR_FEU_Msk /*!< Frame end delimiter unmask */ + +/***************** Bit definition for DCMIPP_PRIER register *****************/ +#define DCMIPP_PRIER_ERRIE_Pos (6UL) +#define DCMIPP_PRIER_ERRIE_Msk (0x1UL << DCMIPP_PRIER_ERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRIER_ERRIE DCMIPP_PRIER_ERRIE_Msk /*!< Synchronization error interrupt enable */ + +/***************** Bit definition for DCMIPP_PRSR register ******************/ +#define DCMIPP_PRSR_ERRF_Pos (6UL) +#define DCMIPP_PRSR_ERRF_Msk (0x1UL << DCMIPP_PRSR_ERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRSR_ERRF DCMIPP_PRSR_ERRF_Msk /*!< Synchronization error raw interrupt status */ +#define DCMIPP_PRSR_HSYNC_Pos (16UL) +#define DCMIPP_PRSR_HSYNC_Msk (0x1UL << DCMIPP_PRSR_HSYNC_Pos) /*!< 0x00010000 */ +#define DCMIPP_PRSR_HSYNC DCMIPP_PRSR_HSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */ +#define DCMIPP_PRSR_VSYNC_Pos (17UL) +#define DCMIPP_PRSR_VSYNC_Msk (0x1UL << DCMIPP_PRSR_VSYNC_Pos) /*!< 0x00020000 */ +#define DCMIPP_PRSR_VSYNC DCMIPP_PRSR_VSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */ + +/***************** Bit definition for DCMIPP_PRFCR register *****************/ +#define DCMIPP_PRFCR_CERRF_Pos (6UL) +#define DCMIPP_PRFCR_CERRF_Msk (0x1UL << DCMIPP_PRFCR_CERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_PRFCR_CERRF DCMIPP_PRFCR_CERRF_Msk /*!< Synchronization error interrupt status clear */ + +/***************** Bit definition for DCMIPP_CMCR register ******************/ +#define DCMIPP_CMCR_INSEL_Pos (0UL) +#define DCMIPP_CMCR_INSEL_Msk (0x1UL << DCMIPP_CMCR_INSEL_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMCR_INSEL DCMIPP_CMCR_INSEL_Msk /*!< input selection */ +#define DCMIPP_CMCR_PSFC_Pos (1UL) +#define DCMIPP_CMCR_PSFC_Msk (0x3UL << DCMIPP_CMCR_PSFC_Pos) /*!< 0x00000006 */ +#define DCMIPP_CMCR_PSFC DCMIPP_CMCR_PSFC_Msk /*!< Pipe selection for the frame counter */ +#define DCMIPP_CMCR_CFC_Pos (4UL) +#define DCMIPP_CMCR_CFC_Msk (0x1UL << DCMIPP_CMCR_CFC_Pos) /*!< 0x00000010 */ +#define DCMIPP_CMCR_CFC DCMIPP_CMCR_CFC_Msk /*!< Clear frame counter */ +#define DCMIPP_CMCR_SWAPRB_Pos (7UL) +#define DCMIPP_CMCR_SWAPRB_Msk (0x1UL << DCMIPP_CMCR_SWAPRB_Pos) /*!< 0x00000080 */ +#define DCMIPP_CMCR_SWAPRB DCMIPP_CMCR_SWAPRB_Msk /*!< Swap R/U and B/V */ + +/**************** Bit definition for DCMIPP_CMFRCR register *****************/ +#define DCMIPP_CMFRCR_FRMCNT_Pos (0UL) +#define DCMIPP_CMFRCR_FRMCNT_Msk (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_CMFRCR_FRMCNT DCMIPP_CMFRCR_FRMCNT_Msk /*!< Frame counter, read-only, loops around */ + +/***************** Bit definition for DCMIPP_CMIER register *****************/ +#define DCMIPP_CMIER_ATXERRIE_Pos (5UL) +#define DCMIPP_CMIER_ATXERRIE_Msk (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMIER_ATXERRIE DCMIPP_CMIER_ATXERRIE_Msk /*!< AXI Transfer error interrupt enable for IPPLUG */ +#define DCMIPP_CMIER_PRERRIE_Pos (6UL) +#define DCMIPP_CMIER_PRERRIE_Msk (0x1UL << DCMIPP_CMIER_PRERRIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMIER_PRERRIE DCMIPP_CMIER_PRERRIE_Msk /*!< limit interrupt enable for the Parallel Interface */ +#define DCMIPP_CMIER_P0LINEIE_Pos (8UL) +#define DCMIPP_CMIER_P0LINEIE_Msk (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0FRAMEIE_Pos (9UL) +#define DCMIPP_CMIER_P0FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMIER_P0FRAMEIE DCMIPP_CMIER_P0FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0VSYNCIE_Pos (10UL) +#define DCMIPP_CMIER_P0VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMIER_P0VSYNCIE DCMIPP_CMIER_P0VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0LIMITIE_Pos (14UL) +#define DCMIPP_CMIER_P0LIMITIE_Msk (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMIER_P0LIMITIE DCMIPP_CMIER_P0LIMITIE_Msk /*!< limit interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P0OVRIE_Pos (15UL) +#define DCMIPP_CMIER_P0OVRIE_Msk (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMIER_P0OVRIE DCMIPP_CMIER_P0OVRIE_Msk /*!< Overrun interrupt enable for the Pipe0 */ +#define DCMIPP_CMIER_P1LINEIE_Pos (16UL) +#define DCMIPP_CMIER_P1LINEIE_Msk (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMIER_P1LINEIE DCMIPP_CMIER_P1LINEIE_Msk /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */ +#define DCMIPP_CMIER_P1FRAMEIE_Pos (17UL) +#define DCMIPP_CMIER_P1FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMIER_P1FRAMEIE DCMIPP_CMIER_P1FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1VSYNCIE_Pos (18UL) +#define DCMIPP_CMIER_P1VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMIER_P1VSYNCIE DCMIPP_CMIER_P1VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P1OVRIE_Pos (23UL) +#define DCMIPP_CMIER_P1OVRIE_Msk (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMIER_P1OVRIE DCMIPP_CMIER_P1OVRIE_Msk /*!< Overrun interrupt enable for the Pipe1 */ +#define DCMIPP_CMIER_P2LINEIE_Pos (24UL) +#define DCMIPP_CMIER_P2LINEIE_Msk (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMIER_P2LINEIE DCMIPP_CMIER_P2LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2FRAMEIE_Pos (25UL) +#define DCMIPP_CMIER_P2FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMIER_P2FRAMEIE DCMIPP_CMIER_P2FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2VSYNCIE_Pos (26UL) +#define DCMIPP_CMIER_P2VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMIER_P2VSYNCIE DCMIPP_CMIER_P2VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe2 */ +#define DCMIPP_CMIER_P2OVRIE_Pos (31UL) +#define DCMIPP_CMIER_P2OVRIE_Msk (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMIER_P2OVRIE DCMIPP_CMIER_P2OVRIE_Msk /*!< Overrun interrupt status enable for the Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR1 register *****************/ +#define DCMIPP_CMSR1_PRHSYNC_Pos (0UL) +#define DCMIPP_CMSR1_PRHSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos) /*!< 0x00000001 */ +#define DCMIPP_CMSR1_PRHSYNC DCMIPP_CMSR1_PRHSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_PRVSYNC_Pos (1UL) +#define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */ +#define DCMIPP_CMSR1_PRVSYNC DCMIPP_CMSR1_PRVSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */ +#define DCMIPP_CMSR1_P0LSTLINE_Pos (8UL) +#define DCMIPP_CMSR1_P0LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR1_P0LSTLINE DCMIPP_CMSR1_P0LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0LSTFRM_Pos (9UL) +#define DCMIPP_CMSR1_P0LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR1_P0LSTFRM DCMIPP_CMSR1_P0LSTFRM_Msk /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */ +#define DCMIPP_CMSR1_P0CPTACT_Pos (15UL) +#define DCMIPP_CMSR1_P0CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR1_P0CPTACT DCMIPP_CMSR1_P0CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */ +#define DCMIPP_CMSR1_P1LSTLINE_Pos (16UL) +#define DCMIPP_CMSR1_P1LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR1_P1LSTLINE DCMIPP_CMSR1_P1LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1LSTFRM_Pos (17UL) +#define DCMIPP_CMSR1_P1LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR1_P1LSTFRM DCMIPP_CMSR1_P1LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */ +#define DCMIPP_CMSR1_P1CPTACT_Pos (23UL) +#define DCMIPP_CMSR1_P1CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR1_P1CPTACT DCMIPP_CMSR1_P1CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */ +#define DCMIPP_CMSR1_P2LSTLINE_Pos (24UL) +#define DCMIPP_CMSR1_P2LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR1_P2LSTLINE DCMIPP_CMSR1_P2LSTLINE_Msk /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2LSTFRM_Pos (25UL) +#define DCMIPP_CMSR1_P2LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR1_P2LSTFRM DCMIPP_CMSR1_P2LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */ +#define DCMIPP_CMSR1_P2CPTACT_Pos (31UL) +#define DCMIPP_CMSR1_P2CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR1_P2CPTACT DCMIPP_CMSR1_P2CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMSR2 register *****************/ +#define DCMIPP_CMSR2_ATXERRF_Pos (5UL) +#define DCMIPP_CMSR2_ATXERRF_Msk (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMSR2_ATXERRF DCMIPP_CMSR2_ATXERRF_Msk /*!< AXI transfer error interrupt status flag for the IPPLUG */ +#define DCMIPP_CMSR2_PRERRF_Pos (6UL) +#define DCMIPP_CMSR2_PRERRF_Msk (0x1UL << DCMIPP_CMSR2_PRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMSR2_PRERRF DCMIPP_CMSR2_PRERRF_Msk /*!< Synchronization error raw interrupt status for the parallel interface */ +#define DCMIPP_CMSR2_P0LINEF_Pos (8UL) +#define DCMIPP_CMSR2_P0LINEF_Msk (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0FRAMEF_Pos (9UL) +#define DCMIPP_CMSR2_P0FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMSR2_P0FRAMEF DCMIPP_CMSR2_P0FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0VSYNCF_Pos (10UL) +#define DCMIPP_CMSR2_P0VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMSR2_P0VSYNCF DCMIPP_CMSR2_P0VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0LIMITF_Pos (14UL) +#define DCMIPP_CMSR2_P0LIMITF_Msk (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMSR2_P0LIMITF DCMIPP_CMSR2_P0LIMITF_Msk /*!< Limit raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P0OVRF_Pos (15UL) +#define DCMIPP_CMSR2_P0OVRF_Msk (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMSR2_P0OVRF DCMIPP_CMSR2_P0OVRF_Msk /*!< Overrun raw interrupt status for Pipe0 */ +#define DCMIPP_CMSR2_P1LINEF_Pos (16UL) +#define DCMIPP_CMSR2_P1LINEF_Msk (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMSR2_P1LINEF DCMIPP_CMSR2_P1LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1FRAMEF_Pos (17UL) +#define DCMIPP_CMSR2_P1FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMSR2_P1FRAMEF DCMIPP_CMSR2_P1FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1VSYNCF_Pos (18UL) +#define DCMIPP_CMSR2_P1VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMSR2_P1VSYNCF DCMIPP_CMSR2_P1VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P1OVRF_Pos (23UL) +#define DCMIPP_CMSR2_P1OVRF_Msk (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMSR2_P1OVRF DCMIPP_CMSR2_P1OVRF_Msk /*!< Overrun raw interrupt status for Pipe1 */ +#define DCMIPP_CMSR2_P2LINEF_Pos (24UL) +#define DCMIPP_CMSR2_P2LINEF_Msk (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMSR2_P2LINEF DCMIPP_CMSR2_P2LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2FRAMEF_Pos (25UL) +#define DCMIPP_CMSR2_P2FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMSR2_P2FRAMEF DCMIPP_CMSR2_P2FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2VSYNCF_Pos (26UL) +#define DCMIPP_CMSR2_P2VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMSR2_P2VSYNCF DCMIPP_CMSR2_P2VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe2 */ +#define DCMIPP_CMSR2_P2OVRF_Pos (31UL) +#define DCMIPP_CMSR2_P2OVRF_Msk (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMSR2_P2OVRF DCMIPP_CMSR2_P2OVRF_Msk /*!< Overrun raw interrupt status for Pipe2 */ + +/***************** Bit definition for DCMIPP_CMFCR register *****************/ +#define DCMIPP_CMFCR_CATXERRF_Pos (5UL) +#define DCMIPP_CMFCR_CATXERRF_Msk (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos) /*!< 0x00000020 */ +#define DCMIPP_CMFCR_CATXERRF DCMIPP_CMFCR_CATXERRF_Msk /*!< AXI Transfer error interrupt status clear */ +#define DCMIPP_CMFCR_CPRERRF_Pos (6UL) +#define DCMIPP_CMFCR_CPRERRF_Msk (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos) /*!< 0x00000040 */ +#define DCMIPP_CMFCR_CPRERRF DCMIPP_CMFCR_CPRERRF_Msk /*!< Synchronization error interrupt status clear */ +#define DCMIPP_CMFCR_CP0LINEF_Pos (8UL) +#define DCMIPP_CMFCR_CP0LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos) /*!< 0x00000100 */ +#define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0FRAMEF_Pos (9UL) +#define DCMIPP_CMFCR_CP0FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos) /*!< 0x00000200 */ +#define DCMIPP_CMFCR_CP0FRAMEF DCMIPP_CMFCR_CP0FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP0VSYNCF_Pos (10UL) +#define DCMIPP_CMFCR_CP0VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos) /*!< 0x00000400 */ +#define DCMIPP_CMFCR_CP0VSYNCF DCMIPP_CMFCR_CP0VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP0LIMITF_Pos (14UL) +#define DCMIPP_CMFCR_CP0LIMITF_Msk (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos) /*!< 0x00004000 */ +#define DCMIPP_CMFCR_CP0LIMITF DCMIPP_CMFCR_CP0LIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_CMFCR_CP0OVRF_Pos (15UL) +#define DCMIPP_CMFCR_CP0OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos) /*!< 0x00008000 */ +#define DCMIPP_CMFCR_CP0OVRF DCMIPP_CMFCR_CP0OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP1LINEF_Pos (16UL) +#define DCMIPP_CMFCR_CP1LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos) /*!< 0x00010000 */ +#define DCMIPP_CMFCR_CP1LINEF DCMIPP_CMFCR_CP1LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1FRAMEF_Pos (17UL) +#define DCMIPP_CMFCR_CP1FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos) /*!< 0x00020000 */ +#define DCMIPP_CMFCR_CP1FRAMEF DCMIPP_CMFCR_CP1FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP1VSYNCF_Pos (18UL) +#define DCMIPP_CMFCR_CP1VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos) /*!< 0x00040000 */ +#define DCMIPP_CMFCR_CP1VSYNCF DCMIPP_CMFCR_CP1VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP1OVRF_Pos (23UL) +#define DCMIPP_CMFCR_CP1OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos) /*!< 0x00800000 */ +#define DCMIPP_CMFCR_CP1OVRF DCMIPP_CMFCR_CP1OVRF_Msk /*!< Overrun interrupt status clear */ +#define DCMIPP_CMFCR_CP2LINEF_Pos (24UL) +#define DCMIPP_CMFCR_CP2LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos) /*!< 0x01000000 */ +#define DCMIPP_CMFCR_CP2LINEF DCMIPP_CMFCR_CP2LINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2FRAMEF_Pos (25UL) +#define DCMIPP_CMFCR_CP2FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos) /*!< 0x02000000 */ +#define DCMIPP_CMFCR_CP2FRAMEF DCMIPP_CMFCR_CP2FRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_CMFCR_CP2VSYNCF_Pos (26UL) +#define DCMIPP_CMFCR_CP2VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos) /*!< 0x04000000 */ +#define DCMIPP_CMFCR_CP2VSYNCF DCMIPP_CMFCR_CP2VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_CMFCR_CP2OVRF_Pos (31UL) +#define DCMIPP_CMFCR_CP2OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos) /*!< 0x80000000 */ +#define DCMIPP_CMFCR_CP2OVRF DCMIPP_CMFCR_CP2OVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0FSCR register *****************/ +#define DCMIPP_P0FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0FSCR_DTIDA DCMIPP_P0FSCR_DTIDA_Msk /*!< Data type selection ID A */ +#define DCMIPP_P0FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0FSCR_DTIDB DCMIPP_P0FSCR_DTIDB_Msk /*!< Data type selection ID B */ +#define DCMIPP_P0FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0FSCR_DTMODE_Msk (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0FSCR_DTMODE DCMIPP_P0FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_VC_Pos (19UL) +#define DCMIPP_P0FSCR_VC_Msk (0x3UL << DCMIPP_P0FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0FSCR_VC DCMIPP_P0FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P0FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0FSCR_PIPEN_Msk (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0FSCR_PIPEN DCMIPP_P0FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P0FCTCR register ****************/ +#define DCMIPP_P0FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0FCTCR_FRATE DCMIPP_P0FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCTCR_CPTMODE DCMIPP_P0FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0FCTCR_CPTREQ DCMIPP_P0FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P0SCSTR register ****************/ +#define DCMIPP_P0SCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0SCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSTR_HSTART DCMIPP_P0SCSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0SCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0SCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSTR_VSTART DCMIPP_P0SCSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P0SCSZR register ****************/ +#define DCMIPP_P0SCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0SCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0SCSZR_HSIZE DCMIPP_P0SCSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0SCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0SCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0SCSZR_VSIZE DCMIPP_P0SCSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0SCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0SCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0SCSZR_POSNEG DCMIPP_P0SCSZR_POSNEG_Msk /*!< This bit is set and cleared by software */ +#define DCMIPP_P0SCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0SCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0SCSZR_ENABLE DCMIPP_P0SCSZR_ENABLE_Msk /*!< This bit is set and cleared by software */ + +/*************** Bit definition for DCMIPP_P0DCCNTR register ****************/ +#define DCMIPP_P0DCCNTR_CNT_Pos (0UL) +#define DCMIPP_P0DCCNTR_CNT_Msk (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */ +#define DCMIPP_P0DCCNTR_CNT DCMIPP_P0DCCNTR_CNT_Msk /*!< Number of data dumped during the frame */ + +/*************** Bit definition for DCMIPP_P0DCLMTR register ****************/ +#define DCMIPP_P0DCLMTR_LIMIT_Pos (0UL) +#define DCMIPP_P0DCLMTR_LIMIT_Msk (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P0DCLMTR_LIMIT DCMIPP_P0DCLMTR_LIMIT_Msk /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */ +#define DCMIPP_P0DCLMTR_ENABLE_Pos (31UL) +#define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0DCLMTR_ENABLE DCMIPP_P0DCLMTR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P0PPCR register *****************/ +#define DCMIPP_P0PPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0PPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0PPCR_SWAPYUV DCMIPP_P0PPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0PPCR_PAD_Pos (5UL) +#define DCMIPP_P0PPCR_PAD_Msk (0x1UL << DCMIPP_P0PPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0PPCR_PAD DCMIPP_P0PPCR_PAD_Msk /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0PPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0PPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0PPCR_HEADEREN DCMIPP_P0PPCR_HEADEREN_Msk /*!< CSI header dump enable */ +#define DCMIPP_P0PPCR_BSM_Pos (7UL) +#define DCMIPP_P0PPCR_BSM_Msk (0x3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0PPCR_BSM DCMIPP_P0PPCR_BSM_Msk /*!< Byte select mode */ +#define DCMIPP_P0PPCR_OEBS_Pos (9UL) +#define DCMIPP_P0PPCR_OEBS_Msk (0x1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0PPCR_OEBS DCMIPP_P0PPCR_OEBS_Msk /*!< Odd/even byte select (byte select start) */ +#define DCMIPP_P0PPCR_LSM_Pos (10UL) +#define DCMIPP_P0PPCR_LSM_Msk (0x1UL << DCMIPP_P0PPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0PPCR_LSM DCMIPP_P0PPCR_LSM_Msk /*!< Line select mode */ +#define DCMIPP_P0PPCR_OELS_Pos (11UL) +#define DCMIPP_P0PPCR_OELS_Msk (0x1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0PPCR_OELS DCMIPP_P0PPCR_OELS_Msk /*!< Odd/even line select (line select start) */ +#define DCMIPP_P0PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0PPCR_LINEMULT DCMIPP_P0PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0PPCR_DBM_Pos (16UL) +#define DCMIPP_P0PPCR_DBM_Msk (0x1UL << DCMIPP_P0PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0PPCR_DBM DCMIPP_P0PPCR_DBM_Msk /*!< Double buffer mode */ + +/*************** Bit definition for DCMIPP_P0PPM0AR1 register ***************/ +#define DCMIPP_P0PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR1_M0A DCMIPP_P0PPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P0PPM0AR2 register ***************/ +#define DCMIPP_P0PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P0PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0PPM0AR2_M0A DCMIPP_P0PPM0AR2_M0A_Msk /*!< Memory0 address */ + +/***************** Bit definition for DCMIPP_P0IER register *****************/ +#define DCMIPP_P0IER_LINEIE_Pos (0UL) +#define DCMIPP_P0IER_LINEIE_Msk (0x1UL << DCMIPP_P0IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P0IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P0IER_FRAMEIE_Msk (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0IER_FRAMEIE DCMIPP_P0IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P0IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P0IER_VSYNCIE_Msk (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0IER_VSYNCIE DCMIPP_P0IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P0IER_LIMITIE_Pos (6UL) +#define DCMIPP_P0IER_LIMITIE_Msk (0x1UL << DCMIPP_P0IER_LIMITIE_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0IER_LIMITIE DCMIPP_P0IER_LIMITIE_Msk /*!< Limit interrupt enable */ +#define DCMIPP_P0IER_OVRIE_Pos (7UL) +#define DCMIPP_P0IER_OVRIE_Msk (0x1UL << DCMIPP_P0IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0IER_OVRIE DCMIPP_P0IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P0SR register ******************/ +#define DCMIPP_P0SR_LINEF_Pos (0UL) +#define DCMIPP_P0SR_LINEF_Msk (0x1UL << DCMIPP_P0SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P0SR_FRAMEF_Pos (1UL) +#define DCMIPP_P0SR_FRAMEF_Msk (0x1UL << DCMIPP_P0SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0SR_FRAMEF DCMIPP_P0SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P0SR_VSYNCF_Pos (2UL) +#define DCMIPP_P0SR_VSYNCF_Msk (0x1UL << DCMIPP_P0SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0SR_VSYNCF DCMIPP_P0SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P0SR_LIMITF_Pos (6UL) +#define DCMIPP_P0SR_LIMITF_Msk (0x1UL << DCMIPP_P0SR_LIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0SR_LIMITF DCMIPP_P0SR_LIMITF_Msk /*!< Limit raw interrupt status */ +#define DCMIPP_P0SR_OVRF_Pos (7UL) +#define DCMIPP_P0SR_OVRF_Msk (0x1UL << DCMIPP_P0SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0SR_OVRF DCMIPP_P0SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P0SR_LSTLINE_Pos (16UL) +#define DCMIPP_P0SR_LSTLINE_Msk (0x1UL << DCMIPP_P0SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0SR_LSTLINE DCMIPP_P0SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_LSTFRM_Pos (17UL) +#define DCMIPP_P0SR_LSTFRM_Msk (0x1UL << DCMIPP_P0SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P0SR_LSTFRM DCMIPP_P0SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P0SR_CPTACT_Pos (23UL) +#define DCMIPP_P0SR_CPTACT_Msk (0x1UL << DCMIPP_P0SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P0SR_CPTACT DCMIPP_P0SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P0FCR register *****************/ +#define DCMIPP_P0FCR_CLINEF_Pos (0UL) +#define DCMIPP_P0FCR_CLINEF_Msk (0x1UL << DCMIPP_P0FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P0FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P0FCR_CFRAMEF DCMIPP_P0FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P0FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P0FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0FCR_CVSYNCF DCMIPP_P0FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P0FCR_CLIMITF_Pos (6UL) +#define DCMIPP_P0FCR_CLIMITF_Msk (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0FCR_CLIMITF DCMIPP_P0FCR_CLIMITF_Msk /*!< limit interrupt status clear */ +#define DCMIPP_P0FCR_COVRF_Pos (7UL) +#define DCMIPP_P0FCR_COVRF_Msk (0x1UL << DCMIPP_P0FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P0FCR_COVRF DCMIPP_P0FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P0CFSCR register ****************/ +#define DCMIPP_P0CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P0CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P0CFSCR_DTIDA DCMIPP_P0CFSCR_DTIDA_Msk /*!< Current Data type selection ID A */ +#define DCMIPP_P0CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P0CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P0CFSCR_DTIDB DCMIPP_P0CFSCR_DTIDB_Msk /*!< Current Data type selection ID B */ +#define DCMIPP_P0CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P0CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P0CFSCR_DTMODE DCMIPP_P0CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P0CFSCR_VC_Pos (19UL) +#define DCMIPP_P0CFSCR_VC_Msk (0x3UL << DCMIPP_P0CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P0CFSCR_VC DCMIPP_P0CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P0CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P0CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CFSCR_PIPEN DCMIPP_P0CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P0CFCTCR register ****************/ +#define DCMIPP_P0CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P0CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P0CFCTCR_FRATE DCMIPP_P0CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P0CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P0CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P0CFCTCR_CPTMODE DCMIPP_P0CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P0CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P0CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P0CFCTCR_CPTREQ DCMIPP_P0CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P0CSCSTR register ****************/ +#define DCMIPP_P0CSCSTR_HSTART_Pos (0UL) +#define DCMIPP_P0CSCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSTR_HSTART DCMIPP_P0CSCSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 words wide */ +#define DCMIPP_P0CSCSTR_VSTART_Pos (16UL) +#define DCMIPP_P0CSCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSTR_VSTART DCMIPP_P0CSCSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P0CSCSZR register ****************/ +#define DCMIPP_P0CSCSZR_HSIZE_Pos (0UL) +#define DCMIPP_P0CSCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P0CSCSZR_HSIZE DCMIPP_P0CSCSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */ +#define DCMIPP_P0CSCSZR_VSIZE_Pos (16UL) +#define DCMIPP_P0CSCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P0CSCSZR_VSIZE DCMIPP_P0CSCSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P0CSCSZR_POSNEG_Pos (30UL) +#define DCMIPP_P0CSCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos) /*!< 0x40000000 */ +#define DCMIPP_P0CSCSZR_POSNEG DCMIPP_P0CSCSZR_POSNEG_Msk /*!< Current value of the POSNEG bit */ +#define DCMIPP_P0CSCSZR_ENABLE_Pos (31UL) +#define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P0CSCSZR_ENABLE DCMIPP_P0CSCSZR_ENABLE_Msk /*!< Current value of the ENABLE bit */ + +/**************** Bit definition for DCMIPP_P0CPPCR register ****************/ +#define DCMIPP_P0CPPCR_SWAPYUV_Pos (0UL) +#define DCMIPP_P0CPPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos) /*!< 0x00000001 */ +#define DCMIPP_P0CPPCR_SWAPYUV DCMIPP_P0CPPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */ +#define DCMIPP_P0CPPCR_PAD_Pos (5UL) +#define DCMIPP_P0CPPCR_PAD_Msk (0x1UL << DCMIPP_P0CPPCR_PAD_Pos) /*!< 0x00000020 */ +#define DCMIPP_P0CPPCR_PAD DCMIPP_P0CPPCR_PAD_Msk /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */ +#define DCMIPP_P0CPPCR_HEADEREN_Pos (6UL) +#define DCMIPP_P0CPPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos) /*!< 0x00000040 */ +#define DCMIPP_P0CPPCR_HEADEREN DCMIPP_P0CPPCR_HEADEREN_Msk /*!< Current CSI header dump enable */ +#define DCMIPP_P0CPPCR_BSM_Pos (7UL) +#define DCMIPP_P0CPPCR_BSM_Msk (0x3UL << DCMIPP_P0CPPCR_BSM_Pos) /*!< 0x00000180 */ +#define DCMIPP_P0CPPCR_BSM DCMIPP_P0CPPCR_BSM_Msk /*!< Current Byte select mode */ +#define DCMIPP_P0CPPCR_OEBS_Pos (9UL) +#define DCMIPP_P0CPPCR_OEBS_Msk (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos) /*!< 0x00000200 */ +#define DCMIPP_P0CPPCR_OEBS DCMIPP_P0CPPCR_OEBS_Msk /*!< Current odd/even byte select (Byte select start) */ +#define DCMIPP_P0CPPCR_LSM_Pos (10UL) +#define DCMIPP_P0CPPCR_LSM_Msk (0x1UL << DCMIPP_P0CPPCR_LSM_Pos) /*!< 0x00000400 */ +#define DCMIPP_P0CPPCR_LSM DCMIPP_P0CPPCR_LSM_Msk /*!< Current Line select mode */ +#define DCMIPP_P0CPPCR_OELS_Pos (11UL) +#define DCMIPP_P0CPPCR_OELS_Msk (0x1UL << DCMIPP_P0CPPCR_OELS_Pos) /*!< 0x00000800 */ +#define DCMIPP_P0CPPCR_OELS DCMIPP_P0CPPCR_OELS_Msk /*!< Current odd/even line select (Line select start) */ +#define DCMIPP_P0CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P0CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P0CPPCR_LINEMULT DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Current amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P0CPPCR_DBM_Pos (16UL) +#define DCMIPP_P0CPPCR_DBM_Msk (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x00010000 */ +#define DCMIPP_P0CPPCR_DBM DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Double buffer mode */ + +/************** Bit definition for DCMIPP_P0CPPM0AR1 register ***************/ +#define DCMIPP_P0CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P0CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P0CPPM0AR1_M0A DCMIPP_P0CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/**************** Bit definition for DCMIPP_P1FSCR register *****************/ +#define DCMIPP_P1FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1FSCR_DTIDA DCMIPP_P1FSCR_DTIDA_Msk /*!< Data type ID A */ +#define DCMIPP_P1FSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1FSCR_DTIDB DCMIPP_P1FSCR_DTIDB_Msk /*!< Data type ID B */ +#define DCMIPP_P1FSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1FSCR_DTMODE_Msk (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1FSCR_DTMODE DCMIPP_P1FSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1FSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1FSCR_PIPEDIFF DCMIPP_P1FSCR_PIPEDIFF_Msk /*!< Differentiates Pipe2 vs */ +#define DCMIPP_P1FSCR_VC_Pos (19UL) +#define DCMIPP_P1FSCR_VC_Msk (0x3UL << DCMIPP_P1FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1FSCR_VC DCMIPP_P1FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P1FSCR_FDTF_Pos (24UL) +#define DCMIPP_P1FSCR_FDTF_Msk (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1FSCR_FDTF DCMIPP_P1FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P1FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1FSCR_FDTFEN DCMIPP_P1FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P1FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1FSCR_PIPEN_Msk (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1FSCR_PIPEN DCMIPP_P1FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P1SRCR register *****************/ +#define DCMIPP_P1SRCR_LASTLINE_Pos (0UL) +#define DCMIPP_P1SRCR_LASTLINE_Msk (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1SRCR_LASTLINE DCMIPP_P1SRCR_LASTLINE_Msk /*!< Number of the last line to be kept when CROPEN = 1 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos (12UL) +#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1SRCR_FIRSTLINEDEL DCMIPP_P1SRCR_FIRSTLINEDEL_Msk /*!< Number of lines to be deleted when CROPEN = 1 */ +#define DCMIPP_P1SRCR_CROPEN_Pos (15UL) +#define DCMIPP_P1SRCR_CROPEN_Msk (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos) /*!< 0x00008000 */ +#define DCMIPP_P1SRCR_CROPEN DCMIPP_P1SRCR_CROPEN_Msk /*!< Crop line enable */ + +/**************** Bit definition for DCMIPP_P1BPRCR register ****************/ +#define DCMIPP_P1BPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BPRCR_ENABLE DCMIPP_P1BPRCR_ENABLE_Msk /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */ +#define DCMIPP_P1BPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1BPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1BPRCR_STRENGTH DCMIPP_P1BPRCR_STRENGTH_Msk /*!< Strength (aggressivity) of the bad pixel detection: */ + +/**************** Bit definition for DCMIPP_P1BPRSR register ****************/ +#define DCMIPP_P1BPRSR_BADCNT_Pos (0UL) +#define DCMIPP_P1BPRSR_BADCNT_Msk (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1BPRSR_BADCNT DCMIPP_P1BPRSR_BADCNT_Msk /*!< Amount of detected bad pixels */ + +/**************** Bit definition for DCMIPP_P1DECR register *****************/ +#define DCMIPP_P1DECR_ENABLE_Pos (0UL) +#define DCMIPP_P1DECR_ENABLE_Msk (0x1UL << DCMIPP_P1DECR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DECR_ENABLE DCMIPP_P1DECR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DECR_HDEC_Pos (1UL) +#define DCMIPP_P1DECR_HDEC_Msk (0x3UL << DCMIPP_P1DECR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DECR_HDEC DCMIPP_P1DECR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DECR_VDEC_Pos (3UL) +#define DCMIPP_P1DECR_VDEC_Msk (0x3UL << DCMIPP_P1DECR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DECR_VDEC DCMIPP_P1DECR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1BLCCR register ****************/ +#define DCMIPP_P1BLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1BLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1BLCCR_ENABLE DCMIPP_P1BLCCR_ENABLE_Msk /*!< Black level calibration */ +#define DCMIPP_P1BLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1BLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1BLCCR_BLCB DCMIPP_P1BLCCR_BLCB_Msk /*!< Black level calibration - Blue */ +#define DCMIPP_P1BLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1BLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1BLCCR_BLCG DCMIPP_P1BLCCR_BLCG_Msk /*!< Black level calibration - Green */ +#define DCMIPP_P1BLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1BLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1BLCCR_BLCR DCMIPP_P1BLCCR_BLCR_Msk /*!< Black level calibration - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR1 register ****************/ +#define DCMIPP_P1EXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1EXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1EXCR1_ENABLE DCMIPP_P1EXCR1_ENABLE_Msk /*!< Exposure control (multiplication and shift) of all red, green and blue */ +#define DCMIPP_P1EXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1EXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR1_MULTR DCMIPP_P1EXCR1_MULTR_Msk /*!< Exposure multiplier - Red */ +#define DCMIPP_P1EXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1EXCR1_SHFR_Msk (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR1_SHFR DCMIPP_P1EXCR1_SHFR_Msk /*!< Exposure shift - Red */ + +/**************** Bit definition for DCMIPP_P1EXCR2 register ****************/ +#define DCMIPP_P1EXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1EXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1EXCR2_MULTB DCMIPP_P1EXCR2_MULTB_Msk /*!< Exposure multiplier - Blue */ +#define DCMIPP_P1EXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1EXCR2_SHFB_Msk (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1EXCR2_SHFB DCMIPP_P1EXCR2_SHFB_Msk /*!< Exposure shift - Blue */ +#define DCMIPP_P1EXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1EXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1EXCR2_MULTG DCMIPP_P1EXCR2_MULTG_Msk /*!< Exposure multiplier - Green */ +#define DCMIPP_P1EXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1EXCR2_SHFG_Msk (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1EXCR2_SHFG DCMIPP_P1EXCR2_SHFG_Msk /*!< Exposure shift - Green */ + +/**************** Bit definition for DCMIPP_P1ST1CR register ****************/ +#define DCMIPP_P1ST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST1CR_ENABLE DCMIPP_P1ST1CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST1CR_BINS_Pos (2UL) +#define DCMIPP_P1ST1CR_BINS_Msk (0x3UL << DCMIPP_P1ST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST1CR_BINS DCMIPP_P1ST1CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST1CR_SRC_Pos (4UL) +#define DCMIPP_P1ST1CR_SRC_Msk (0x7UL << DCMIPP_P1ST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST1CR_SRC DCMIPP_P1ST1CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST1CR_MODE_Pos (7UL) +#define DCMIPP_P1ST1CR_MODE_Msk (0x1UL << DCMIPP_P1ST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST1CR_MODE DCMIPP_P1ST1CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST2CR register ****************/ +#define DCMIPP_P1ST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST2CR_ENABLE DCMIPP_P1ST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST2CR_BINS_Pos (2UL) +#define DCMIPP_P1ST2CR_BINS_Msk (0x3UL << DCMIPP_P1ST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST2CR_BINS DCMIPP_P1ST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST2CR_SRC_Pos (4UL) +#define DCMIPP_P1ST2CR_SRC_Msk (0x7UL << DCMIPP_P1ST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST2CR_SRC DCMIPP_P1ST2CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST2CR_MODE_Pos (7UL) +#define DCMIPP_P1ST2CR_MODE_Msk (0x1UL << DCMIPP_P1ST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST2CR_MODE DCMIPP_P1ST2CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1ST3CR register ****************/ +#define DCMIPP_P1ST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1ST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1ST3CR_ENABLE DCMIPP_P1ST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1ST3CR_BINS_Pos (2UL) +#define DCMIPP_P1ST3CR_BINS_Msk (0x3UL << DCMIPP_P1ST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1ST3CR_BINS DCMIPP_P1ST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1ST3CR_SRC_Pos (4UL) +#define DCMIPP_P1ST3CR_SRC_Msk (0x7UL << DCMIPP_P1ST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1ST3CR_SRC DCMIPP_P1ST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1ST3CR_MODE_Pos (7UL) +#define DCMIPP_P1ST3CR_MODE_Msk (0x1UL << DCMIPP_P1ST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1ST3CR_MODE DCMIPP_P1ST3CR_MODE_Msk /*!< Statistics mode */ + +/**************** Bit definition for DCMIPP_P1STSTR register ****************/ +#define DCMIPP_P1STSTR_HSTART_Pos (0UL) +#define DCMIPP_P1STSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSTR_HSTART DCMIPP_P1STSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSTR_VSTART_Pos (16UL) +#define DCMIPP_P1STSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSTR_VSTART DCMIPP_P1STSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1STSZR register ****************/ +#define DCMIPP_P1STSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1STSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1STSZR_HSIZE DCMIPP_P1STSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1STSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1STSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1STSZR_VSIZE DCMIPP_P1STSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1STSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1STSZR_CROPEN_Msk (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1STSZR_CROPEN DCMIPP_P1STSZR_CROPEN_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1ST1SR register ****************/ +#define DCMIPP_P1ST1SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST1SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST1SR_ACCU DCMIPP_P1ST1SR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST2SR register ****************/ +#define DCMIPP_P1ST2SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST2SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST2SR_ACCU DCMIPP_P1ST2SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1ST3SR register ****************/ +#define DCMIPP_P1ST3SR_ACCU_Pos (0UL) +#define DCMIPP_P1ST3SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos) /*!< 0x00FFFFFF */ +#define DCMIPP_P1ST3SR_ACCU DCMIPP_P1ST3SR_ACCU_Msk /*!< accumulation result, divided by 256 */ + +/**************** Bit definition for DCMIPP_P1DMCR register *****************/ +#define DCMIPP_P1DMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DMCR_ENABLE_Msk (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DMCR_ENABLE DCMIPP_P1DMCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1DMCR_TYPE_Pos (1UL) +#define DCMIPP_P1DMCR_TYPE_Msk (0x3UL << DCMIPP_P1DMCR_TYPE_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DMCR_TYPE DCMIPP_P1DMCR_TYPE_Msk /*!< Raw Bayer type */ +#define DCMIPP_P1DMCR_PEAK_Pos (16UL) +#define DCMIPP_P1DMCR_PEAK_Msk (0x7UL << DCMIPP_P1DMCR_PEAK_Pos) /*!< 0x00070000 */ +#define DCMIPP_P1DMCR_PEAK DCMIPP_P1DMCR_PEAK_Msk /*!< Strength of the peak detection */ +#define DCMIPP_P1DMCR_LINEV_Pos (20UL) +#define DCMIPP_P1DMCR_LINEV_Msk (0x7UL << DCMIPP_P1DMCR_LINEV_Pos) /*!< 0x00700000 */ +#define DCMIPP_P1DMCR_LINEV DCMIPP_P1DMCR_LINEV_Msk /*!< Strength of the vertical line detection */ +#define DCMIPP_P1DMCR_LINEH_Pos (24UL) +#define DCMIPP_P1DMCR_LINEH_Msk (0x7UL << DCMIPP_P1DMCR_LINEH_Pos) /*!< 0x07000000 */ +#define DCMIPP_P1DMCR_LINEH DCMIPP_P1DMCR_LINEH_Msk /*!< Strength of the horizontal line detection */ +#define DCMIPP_P1DMCR_EDGE_Pos (28UL) +#define DCMIPP_P1DMCR_EDGE_Msk (0x7UL << DCMIPP_P1DMCR_EDGE_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1DMCR_EDGE DCMIPP_P1DMCR_EDGE_Msk /*!< Strength of the edge detection */ + +/**************** Bit definition for DCMIPP_P1CCCR register *****************/ +#define DCMIPP_P1CCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCR_ENABLE DCMIPP_P1CCCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCR_TYPE DCMIPP_P1CCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCR_CLAMP DCMIPP_P1CCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/**************** Bit definition for DCMIPP_P1CCRR1 register ****************/ +#define DCMIPP_P1CCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR1_RR DCMIPP_P1CCRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCRR1_RG DCMIPP_P1CCRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCRR2 register ****************/ +#define DCMIPP_P1CCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCRR2_RB DCMIPP_P1CCRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCRR2_RA DCMIPP_P1CCRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCGR1 register ****************/ +#define DCMIPP_P1CCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR1_GR DCMIPP_P1CCGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCGR1_GG DCMIPP_P1CCGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCGR2 register ****************/ +#define DCMIPP_P1CCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCGR2_GB DCMIPP_P1CCGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCGR2_GA DCMIPP_P1CCGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CCBR1 register ****************/ +#define DCMIPP_P1CCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR1_BR DCMIPP_P1CCBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCBR1_BG DCMIPP_P1CCBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/**************** Bit definition for DCMIPP_P1CCBR2 register ****************/ +#define DCMIPP_P1CCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCBR2_BB DCMIPP_P1CCBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCBR2_BA DCMIPP_P1CCBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1CTCR1 register ****************/ +#define DCMIPP_P1CTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CTCR1_ENABLE DCMIPP_P1CTCR1_ENABLE_Msk /*!< */ +#define DCMIPP_P1CTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR1_LUM0 DCMIPP_P1CTCR1_LUM0_Msk /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR2 register ****************/ +#define DCMIPP_P1CTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR2_LUM4 DCMIPP_P1CTCR2_LUM4_Msk /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR2_LUM3 DCMIPP_P1CTCR2_LUM3_Msk /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR2_LUM2 DCMIPP_P1CTCR2_LUM2_Msk /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR2_LUM1 DCMIPP_P1CTCR2_LUM1_Msk /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1CTCR3 register ****************/ +#define DCMIPP_P1CTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CTCR3_LUM8 DCMIPP_P1CTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CTCR3_LUM7 DCMIPP_P1CTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CTCR3_LUM6 DCMIPP_P1CTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CTCR3_LUM5 DCMIPP_P1CTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/**************** Bit definition for DCMIPP_P1FCTCR register ****************/ +#define DCMIPP_P1FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1FCTCR_FRATE_Msk (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1FCTCR_FRATE DCMIPP_P1FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCTCR_CPTMODE DCMIPP_P1FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1FCTCR_CPTREQ DCMIPP_P1FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P1CRSTR register ****************/ +#define DCMIPP_P1CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSTR_HSTART DCMIPP_P1CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSTR_VSTART DCMIPP_P1CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CRSZR register ****************/ +#define DCMIPP_P1CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CRSZR_HSIZE DCMIPP_P1CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CRSZR_VSIZE DCMIPP_P1CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CRSZR_ENABLE DCMIPP_P1CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P1DCCR register *****************/ +#define DCMIPP_P1DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1DCCR_ENABLE_Msk (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1DCCR_ENABLE DCMIPP_P1DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1DCCR_HDEC_Pos (1UL) +#define DCMIPP_P1DCCR_HDEC_Msk (0x3UL << DCMIPP_P1DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1DCCR_HDEC DCMIPP_P1DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1DCCR_VDEC_Pos (3UL) +#define DCMIPP_P1DCCR_VDEC_Msk (0x3UL << DCMIPP_P1DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1DCCR_VDEC DCMIPP_P1DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1DSCR register *****************/ +#define DCMIPP_P1DSCR_HDIV_Pos (0UL) +#define DCMIPP_P1DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1DSCR_HDIV DCMIPP_P1DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_VDIV_Pos (16UL) +#define DCMIPP_P1DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1DSCR_VDIV DCMIPP_P1DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1DSCR_ENABLE_Msk (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1DSCR_ENABLE DCMIPP_P1DSCR_ENABLE_Msk /*!< Downscaler Enable */ + +/*************** Bit definition for DCMIPP_P1DSRTIOR register ***************/ +#define DCMIPP_P1DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1DSRTIOR_HRATIO DCMIPP_P1DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1DSRTIOR_VRATIO DCMIPP_P1DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P1DSSZR register ****************/ +#define DCMIPP_P1DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1DSSZR_HSIZE DCMIPP_P1DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1DSSZR_VSIZE DCMIPP_P1DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CMRICR register ***************/ +#define DCMIPP_P1CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P1CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CMRICR_ROILSZ DCMIPP_P1CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P1CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P1CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1CMRICR_ROI1EN DCMIPP_P1CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P1CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P1CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1CMRICR_ROI2EN DCMIPP_P1CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P1CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P1CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CMRICR_ROI3EN DCMIPP_P1CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P1CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P1CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P1CMRICR_ROI4EN DCMIPP_P1CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P1CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P1CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1CMRICR_ROI5EN DCMIPP_P1CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P1CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P1CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P1CMRICR_ROI6EN DCMIPP_P1CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P1CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P1CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P1CMRICR_ROI7EN DCMIPP_P1CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P1CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P1CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1CMRICR_ROI8EN DCMIPP_P1CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P1RIxCR1 register ***************/ +#define DCMIPP_P1RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P1RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR1_HSTART DCMIPP_P1RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P1RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P1RIxCR1_CLB_Msk (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P1RIxCR1_CLB DCMIPP_P1RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P1RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P1RIxCR1_CLG_Msk (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P1RIxCR1_CLG DCMIPP_P1RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P1RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P1RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1RIxCR1_VSTART DCMIPP_P1RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P1RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P1RIxCR1_CLR_Msk (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P1RIxCR1_CLR DCMIPP_P1RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P1RIxCR2 register ***************/ +#define DCMIPP_P1RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P1RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1RIxCR2_VSIZE DCMIPP_P1RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P1RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P1RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P1RIxCR2_HSIZE DCMIPP_P1RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P1GMCR register *****************/ +#define DCMIPP_P1GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P1GMCR_ENABLE_Msk (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1GMCR_ENABLE DCMIPP_P1GMCR_ENABLE_Msk /*!< Gamma enable*/ + +/**************** Bit definition for DCMIPP_P1YUVCR register ****************/ +#define DCMIPP_P1YUVCR_ENABLE_Pos (0UL) +#define DCMIPP_P1YUVCR_ENABLE_Msk (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1YUVCR_ENABLE DCMIPP_P1YUVCR_ENABLE_Msk /*!< */ +#define DCMIPP_P1YUVCR_TYPE_Pos (1UL) +#define DCMIPP_P1YUVCR_TYPE_Msk (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1YUVCR_TYPE DCMIPP_P1YUVCR_TYPE_Msk /*!< Output samples type used while CLAMP is activated */ +#define DCMIPP_P1YUVCR_CLAMP_Pos (2UL) +#define DCMIPP_P1YUVCR_CLAMP_Msk (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1YUVCR_CLAMP DCMIPP_P1YUVCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1YUVRR1 register ****************/ +#define DCMIPP_P1YUVRR1_RR_Pos (0UL) +#define DCMIPP_P1YUVRR1_RR_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR1_RR DCMIPP_P1YUVRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1YUVRR1_RG_Pos (16UL) +#define DCMIPP_P1YUVRR1_RG_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVRR1_RG DCMIPP_P1YUVRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVRR2 register ****************/ +#define DCMIPP_P1YUVRR2_RB_Pos (0UL) +#define DCMIPP_P1YUVRR2_RB_Msk (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVRR2_RB DCMIPP_P1YUVRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1YUVRR2_RA_Pos (16UL) +#define DCMIPP_P1YUVRR2_RA_Msk (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVRR2_RA DCMIPP_P1YUVRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVGR1 register ****************/ +#define DCMIPP_P1YUVGR1_GR_Pos (0UL) +#define DCMIPP_P1YUVGR1_GR_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR1_GR DCMIPP_P1YUVGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1YUVGR1_GG_Pos (16UL) +#define DCMIPP_P1YUVGR1_GG_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVGR1_GG DCMIPP_P1YUVGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVGR2 register ****************/ +#define DCMIPP_P1YUVGR2_GB_Pos (0UL) +#define DCMIPP_P1YUVGR2_GB_Msk (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVGR2_GB DCMIPP_P1YUVGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1YUVGR2_GA_Pos (16UL) +#define DCMIPP_P1YUVGR2_GA_Msk (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVGR2_GA DCMIPP_P1YUVGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1YUVBR1 register ****************/ +#define DCMIPP_P1YUVBR1_BR_Pos (0UL) +#define DCMIPP_P1YUVBR1_BR_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR1_BR DCMIPP_P1YUVBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1YUVBR1_BG_Pos (16UL) +#define DCMIPP_P1YUVBR1_BG_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1YUVBR1_BG DCMIPP_P1YUVBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1YUVBR2 register ****************/ +#define DCMIPP_P1YUVBR2_BB_Pos (0UL) +#define DCMIPP_P1YUVBR2_BB_Msk (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1YUVBR2_BB DCMIPP_P1YUVBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1YUVBR2_BA_Pos (16UL) +#define DCMIPP_P1YUVBR2_BA_Msk (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1YUVBR2_BA DCMIPP_P1YUVBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */ + +/**************** Bit definition for DCMIPP_P1PPCR register *****************/ +#define DCMIPP_P1PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1PPCR_FORMAT_Msk (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1PPCR_FORMAT DCMIPP_P1PPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1PPCR_SWAPRB DCMIPP_P1PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1PPCR_LINEMULT DCMIPP_P1PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P1PPCR_DBM_Pos (16UL) +#define DCMIPP_P1PPCR_DBM_Msk (0x1UL << DCMIPP_P1PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1PPCR_DBM DCMIPP_P1PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P1PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P1PPCR_LMAWM_Msk (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P1PPCR_LMAWM DCMIPP_P1PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P1PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P1PPCR_LMAWE_Msk (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P1PPCR_LMAWE DCMIPP_P1PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P1PPM0AR1 register ***************/ +#define DCMIPP_P1PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR1_M0A DCMIPP_P1PPM0AR1_M0A_Msk /*!< Memory0 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM0AR2 register ***************/ +#define DCMIPP_P1PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P1PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM0AR2_M0A DCMIPP_P1PPM0AR2_M0A_Msk /*!< Memory0 address register 2 */ + +/*************** Bit definition for DCMIPP_P1PPM0PR register ****************/ +#define DCMIPP_P1PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM0PR_PITCH DCMIPP_P1PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1PPM1AR1 register ***************/ +#define DCMIPP_P1PPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR1_M1A DCMIPP_P1PPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1AR2 register ***************/ +#define DCMIPP_P1PPM1AR2_M1A_Pos (0UL) +#define DCMIPP_P1PPM1AR2_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM1AR2_M1A DCMIPP_P1PPM1AR2_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1PPM1PR register ****************/ +#define DCMIPP_P1PPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1PPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1PPM1PR_PITCH DCMIPP_P1PPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P1STM1AR register ****************/ +#define DCMIPP_P1STM1AR_M1A_Pos (0UL) +#define DCMIPP_P1STM1AR_M1A_Msk (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM1AR_M1A DCMIPP_P1STM1AR_M1A_Msk /*!< status Memory1 address register */ + +/*************** Bit definition for DCMIPP_P1PPM2AR1 register ***************/ +#define DCMIPP_P1PPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR1_M2A DCMIPP_P1PPM2AR1_M2A_Msk /*!< Memory2 address register 1*/ + +/*************** Bit definition for DCMIPP_P1PPM2AR2 register ***************/ +#define DCMIPP_P1PPM2AR2_M2A_Pos (0UL) +#define DCMIPP_P1PPM2AR2_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1PPM2AR2_M2A DCMIPP_P1PPM2AR2_M2A_Msk /*!< Memory2 address register 2 */ + +/*************** Bit definition for DCMIPP_P1STM2AR register ****************/ +#define DCMIPP_P1STM2AR_M2A_Pos (0UL) +#define DCMIPP_P1STM2AR_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1STM2AR_M2A DCMIPP_P1STM2AR_M2A_Msk /*!< status Memory2 address register */ + +/***************** Bit definition for DCMIPP_P1IER register *****************/ +#define DCMIPP_P1IER_LINEIE_Pos (0UL) +#define DCMIPP_P1IER_LINEIE_Msk (0x1UL << DCMIPP_P1IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1IER_LINEIE DCMIPP_P1IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P1IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P1IER_FRAMEIE_Msk (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1IER_FRAMEIE DCMIPP_P1IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P1IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P1IER_VSYNCIE_Msk (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1IER_VSYNCIE DCMIPP_P1IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P1IER_OVRIE_Pos (7UL) +#define DCMIPP_P1IER_OVRIE_Msk (0x1UL << DCMIPP_P1IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1IER_OVRIE DCMIPP_P1IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P1SR register ******************/ +#define DCMIPP_P1SR_LINEF_Pos (0UL) +#define DCMIPP_P1SR_LINEF_Msk (0x1UL << DCMIPP_P1SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1SR_LINEF DCMIPP_P1SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P1SR_FRAMEF_Pos (1UL) +#define DCMIPP_P1SR_FRAMEF_Msk (0x1UL << DCMIPP_P1SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1SR_FRAMEF DCMIPP_P1SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P1SR_VSYNCF_Pos (2UL) +#define DCMIPP_P1SR_VSYNCF_Msk (0x1UL << DCMIPP_P1SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1SR_VSYNCF DCMIPP_P1SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P1SR_OVRF_Pos (7UL) +#define DCMIPP_P1SR_OVRF_Msk (0x1UL << DCMIPP_P1SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1SR_OVRF DCMIPP_P1SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P1SR_LSTLINE_Pos (16UL) +#define DCMIPP_P1SR_LSTLINE_Msk (0x1UL << DCMIPP_P1SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P1SR_LSTLINE DCMIPP_P1SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_LSTFRM_Pos (17UL) +#define DCMIPP_P1SR_LSTFRM_Msk (0x1UL << DCMIPP_P1SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P1SR_LSTFRM DCMIPP_P1SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P1SR_CPTACT_Pos (23UL) +#define DCMIPP_P1SR_CPTACT_Msk (0x1UL << DCMIPP_P1SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P1SR_CPTACT DCMIPP_P1SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P1FCR register *****************/ +#define DCMIPP_P1FCR_CLINEF_Pos (0UL) +#define DCMIPP_P1FCR_CLINEF_Msk (0x1UL << DCMIPP_P1FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1FCR_CLINEF DCMIPP_P1FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P1FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1FCR_CFRAMEF DCMIPP_P1FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P1FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P1FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1FCR_CVSYNCF DCMIPP_P1FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P1FCR_COVRF_Pos (7UL) +#define DCMIPP_P1FCR_COVRF_Msk (0x1UL << DCMIPP_P1FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1FCR_COVRF DCMIPP_P1FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P1CFSCR register ****************/ +#define DCMIPP_P1CFSCR_DTIDA_Pos (0UL) +#define DCMIPP_P1CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P1CFSCR_DTIDA DCMIPP_P1CFSCR_DTIDA_Msk /*!< Current Data type ID A */ +#define DCMIPP_P1CFSCR_DTIDB_Pos (8UL) +#define DCMIPP_P1CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos) /*!< 0x00003F00 */ +#define DCMIPP_P1CFSCR_DTIDB DCMIPP_P1CFSCR_DTIDB_Msk /*!< Current Data type ID B */ +#define DCMIPP_P1CFSCR_DTMODE_Pos (16UL) +#define DCMIPP_P1CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos) /*!< 0x00030000 */ +#define DCMIPP_P1CFSCR_DTMODE DCMIPP_P1CFSCR_DTMODE_Msk /*!< Flow selection mode */ +#define DCMIPP_P1CFSCR_PIPEDIFF_Pos (18UL) +#define DCMIPP_P1CFSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos) /*!< 0x00040000 */ +#define DCMIPP_P1CFSCR_PIPEDIFF DCMIPP_P1CFSCR_PIPEDIFF_Msk /*!< Current differentiates Pipe2 vs */ +#define DCMIPP_P1CFSCR_VC_Pos (19UL) +#define DCMIPP_P1CFSCR_VC_Msk (0x3UL << DCMIPP_P1CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P1CFSCR_VC DCMIPP_P1CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P1CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P1CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P1CFSCR_FDTF DCMIPP_P1CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P1CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P1CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P1CFSCR_FDTFEN DCMIPP_P1CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P1CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P1CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CFSCR_PIPEN DCMIPP_P1CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P1CBPRCR register ****************/ +#define DCMIPP_P1CBPRCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBPRCR_ENABLE DCMIPP_P1CBPRCR_ENABLE_Msk /*!< Current status of enable bit */ +#define DCMIPP_P1CBPRCR_STRENGTH_Pos (1UL) +#define DCMIPP_P1CBPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos) /*!< 0x0000000E */ +#define DCMIPP_P1CBPRCR_STRENGTH DCMIPP_P1CBPRCR_STRENGTH_Msk /*!< Current strength (aggressivity) of the bad pixel detection: */ + +/*************** Bit definition for DCMIPP_P1CBLCCR register ****************/ +#define DCMIPP_P1CBLCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CBLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CBLCCR_ENABLE DCMIPP_P1CBLCCR_ENABLE_Msk /*!< For current black level calibration */ +#define DCMIPP_P1CBLCCR_BLCB_Pos (8UL) +#define DCMIPP_P1CBLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos) /*!< 0x0000FF00 */ +#define DCMIPP_P1CBLCCR_BLCB DCMIPP_P1CBLCCR_BLCB_Msk /*!< Current black level calibration - Blue */ +#define DCMIPP_P1CBLCCR_BLCG_Pos (16UL) +#define DCMIPP_P1CBLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos) /*!< 0x00FF0000 */ +#define DCMIPP_P1CBLCCR_BLCG DCMIPP_P1CBLCCR_BLCG_Msk /*!< Current black level calibration - Green */ +#define DCMIPP_P1CBLCCR_BLCR_Pos (24UL) +#define DCMIPP_P1CBLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos) /*!< 0xFF000000 */ +#define DCMIPP_P1CBLCCR_BLCR DCMIPP_P1CBLCCR_BLCR_Msk /*!< Current black level calibration - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR1 register ****************/ +#define DCMIPP_P1CEXCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CEXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CEXCR1_ENABLE DCMIPP_P1CEXCR1_ENABLE_Msk /*!< for exposure control (multiplication and shift) */ +#define DCMIPP_P1CEXCR1_MULTR_Pos (20UL) +#define DCMIPP_P1CEXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR1_MULTR DCMIPP_P1CEXCR1_MULTR_Msk /*!< Current exposure multiplier - Red */ +#define DCMIPP_P1CEXCR1_SHFR_Pos (28UL) +#define DCMIPP_P1CEXCR1_SHFR_Msk (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR1_SHFR DCMIPP_P1CEXCR1_SHFR_Msk /*!< Current exposure shift - Red */ + +/*************** Bit definition for DCMIPP_P1CEXCR2 register ****************/ +#define DCMIPP_P1CEXCR2_MULTB_Pos (4UL) +#define DCMIPP_P1CEXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos) /*!< 0x00000FF0 */ +#define DCMIPP_P1CEXCR2_MULTB DCMIPP_P1CEXCR2_MULTB_Msk /*!< Current exposure multiplier - Blue */ +#define DCMIPP_P1CEXCR2_SHFB_Pos (12UL) +#define DCMIPP_P1CEXCR2_SHFB_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos) /*!< 0x00007000 */ +#define DCMIPP_P1CEXCR2_SHFB DCMIPP_P1CEXCR2_SHFB_Msk /*!< Current exposure shift - Blue */ +#define DCMIPP_P1CEXCR2_MULTG_Pos (20UL) +#define DCMIPP_P1CEXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos) /*!< 0x0FF00000 */ +#define DCMIPP_P1CEXCR2_MULTG DCMIPP_P1CEXCR2_MULTG_Msk /*!< Current exposure multiplier - Green */ +#define DCMIPP_P1CEXCR2_SHFG_Pos (28UL) +#define DCMIPP_P1CEXCR2_SHFG_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos) /*!< 0x70000000 */ +#define DCMIPP_P1CEXCR2_SHFG DCMIPP_P1CEXCR2_SHFG_Msk /*!< Current exposure shift - Green */ + +/*************** Bit definition for DCMIPP_P1CST1CR register ****************/ +#define DCMIPP_P1CST1CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST1CR_ENABLE DCMIPP_P1CST1CR_ENABLE_Msk /*!< Current enable bit value */ +#define DCMIPP_P1CST1CR_BINS_Pos (2UL) +#define DCMIPP_P1CST1CR_BINS_Msk (0x3UL << DCMIPP_P1CST1CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST1CR_BINS DCMIPP_P1CST1CR_BINS_Msk /*!< Current bin definition */ +#define DCMIPP_P1CST1CR_SRC_Pos (4UL) +#define DCMIPP_P1CST1CR_SRC_Msk (0x7UL << DCMIPP_P1CST1CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST1CR_SRC DCMIPP_P1CST1CR_SRC_Msk /*!< Current source of statistics */ +#define DCMIPP_P1CST1CR_MODE_Pos (7UL) +#define DCMIPP_P1CST1CR_MODE_Msk (0x1UL << DCMIPP_P1CST1CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST1CR_MODE DCMIPP_P1CST1CR_MODE_Msk /*!< Current statistics mode */ +#define DCMIPP_P1CST1CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST1CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST1CR_ACCU DCMIPP_P1CST1CR_ACCU_Msk /*!< Current accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST2CR register ****************/ +#define DCMIPP_P1CST2CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST2CR_ENABLE DCMIPP_P1CST2CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST2CR_BINS_Pos (2UL) +#define DCMIPP_P1CST2CR_BINS_Msk (0x3UL << DCMIPP_P1CST2CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST2CR_BINS DCMIPP_P1CST2CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST2CR_SRC_Pos (4UL) +#define DCMIPP_P1CST2CR_SRC_Msk (0x7UL << DCMIPP_P1CST2CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST2CR_SRC DCMIPP_P1CST2CR_SRC_Msk /*!< source of stat */ +#define DCMIPP_P1CST2CR_MODE_Pos (7UL) +#define DCMIPP_P1CST2CR_MODE_Msk (0x1UL << DCMIPP_P1CST2CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST2CR_MODE DCMIPP_P1CST2CR_MODE_Msk /*!< statistics mode */ +#define DCMIPP_P1CST2CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST2CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST2CR_ACCU DCMIPP_P1CST2CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CST3CR register ****************/ +#define DCMIPP_P1CST3CR_ENABLE_Pos (0UL) +#define DCMIPP_P1CST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CST3CR_ENABLE DCMIPP_P1CST3CR_ENABLE_Msk /*!< */ +#define DCMIPP_P1CST3CR_BINS_Pos (2UL) +#define DCMIPP_P1CST3CR_BINS_Msk (0x3UL << DCMIPP_P1CST3CR_BINS_Pos) /*!< 0x0000000C */ +#define DCMIPP_P1CST3CR_BINS DCMIPP_P1CST3CR_BINS_Msk /*!< Bin definition */ +#define DCMIPP_P1CST3CR_SRC_Pos (4UL) +#define DCMIPP_P1CST3CR_SRC_Msk (0x7UL << DCMIPP_P1CST3CR_SRC_Pos) /*!< 0x00000070 */ +#define DCMIPP_P1CST3CR_SRC DCMIPP_P1CST3CR_SRC_Msk /*!< Statistics source */ +#define DCMIPP_P1CST3CR_MODE_Pos (7UL) +#define DCMIPP_P1CST3CR_MODE_Msk (0x1UL << DCMIPP_P1CST3CR_MODE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P1CST3CR_MODE DCMIPP_P1CST3CR_MODE_Msk /*!< Statistics mode */ +#define DCMIPP_P1CST3CR_ACCU_Pos (8UL) +#define DCMIPP_P1CST3CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos) /*!< 0xFFFFFF00 */ +#define DCMIPP_P1CST3CR_ACCU DCMIPP_P1CST3CR_ACCU_Msk /*!< Accumulation result, divided by 256 */ + +/*************** Bit definition for DCMIPP_P1CSTSTR register ****************/ +#define DCMIPP_P1CSTSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CSTSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSTR_HSTART DCMIPP_P1CSTSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CSTSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSTR_VSTART DCMIPP_P1CSTSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CSTSZR register ****************/ +#define DCMIPP_P1CSTSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CSTSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CSTSZR_HSIZE DCMIPP_P1CSTSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CSTSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CSTSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CSTSZR_VSIZE DCMIPP_P1CSTSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CSTSZR_CROPEN_Pos (31UL) +#define DCMIPP_P1CSTSZR_CROPEN_Msk (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CSTSZR_CROPEN DCMIPP_P1CSTSZR_CROPEN_Msk /*!< Current CROPEN bit value */ + +/**************** Bit definition for DCMIPP_P1CCCCR register ****************/ +#define DCMIPP_P1CCCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CCCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCCCR_ENABLE DCMIPP_P1CCCCR_ENABLE_Msk /*!< This bit indicates the current value applied */ +#define DCMIPP_P1CCCCR_TYPE_Pos (1UL) +#define DCMIPP_P1CCCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P1CCCCR_TYPE DCMIPP_P1CCCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */ +#define DCMIPP_P1CCCCR_CLAMP_Pos (2UL) +#define DCMIPP_P1CCCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CCCCR_CLAMP DCMIPP_P1CCCCR_CLAMP_Msk /*!< Clamp the output samples */ + +/*************** Bit definition for DCMIPP_P1CCCRR1 register ****************/ +#define DCMIPP_P1CCCRR1_RR_Pos (0UL) +#define DCMIPP_P1CCCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR1_RR DCMIPP_P1CCCRR1_RR_Msk /*!< Current coefficient row 1 column 1 of the matrix */ +#define DCMIPP_P1CCCRR1_RG_Pos (16UL) +#define DCMIPP_P1CCCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCRR1_RG DCMIPP_P1CCCRR1_RG_Msk /*!< Current coefficient row 1 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCRR2 register ****************/ +#define DCMIPP_P1CCCRR2_RB_Pos (0UL) +#define DCMIPP_P1CCCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCRR2_RB DCMIPP_P1CCCRR2_RB_Msk /*!< Current coefficient row 1 column 3 of the matrix */ +#define DCMIPP_P1CCCRR2_RA_Pos (16UL) +#define DCMIPP_P1CCCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCRR2_RA DCMIPP_P1CCCRR2_RA_Msk /*!< Current coefficient row 1 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCGR1 register ****************/ +#define DCMIPP_P1CCCGR1_GR_Pos (0UL) +#define DCMIPP_P1CCCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR1_GR DCMIPP_P1CCCGR1_GR_Msk /*!< Current coefficient row 2 column 1 of the matrix */ +#define DCMIPP_P1CCCGR1_GG_Pos (16UL) +#define DCMIPP_P1CCCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCGR1_GG DCMIPP_P1CCCGR1_GG_Msk /*!< Current coefficient row 2 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCGR2 register ****************/ +#define DCMIPP_P1CCCGR2_GB_Pos (0UL) +#define DCMIPP_P1CCCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCGR2_GB DCMIPP_P1CCCGR2_GB_Msk /*!< Current coefficient row 2 column 3 of the matrix */ +#define DCMIPP_P1CCCGR2_GA_Pos (16UL) +#define DCMIPP_P1CCCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCGR2_GA DCMIPP_P1CCCGR2_GA_Msk /*!< Current coefficient row 2 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCCBR1 register ****************/ +#define DCMIPP_P1CCCBR1_BR_Pos (0UL) +#define DCMIPP_P1CCCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR1_BR DCMIPP_P1CCCBR1_BR_Msk /*!< Current coefficient row 3 column 1 of the matrix */ +#define DCMIPP_P1CCCBR1_BG_Pos (16UL) +#define DCMIPP_P1CCCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos) /*!< 0x07FF0000 */ +#define DCMIPP_P1CCCBR1_BG DCMIPP_P1CCCBR1_BG_Msk /*!< Current coefficient row 3 column 2 of the matrix */ + +/*************** Bit definition for DCMIPP_P1CCCBR2 register ****************/ +#define DCMIPP_P1CCCBR2_BB_Pos (0UL) +#define DCMIPP_P1CCCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos) /*!< 0x000007FF */ +#define DCMIPP_P1CCCBR2_BB DCMIPP_P1CCCBR2_BB_Msk /*!< Current coefficient row 3 column 3 of the matrix */ +#define DCMIPP_P1CCCBR2_BA_Pos (16UL) +#define DCMIPP_P1CCCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CCCBR2_BA DCMIPP_P1CCCBR2_BA_Msk /*!< Current coefficient row 3 of the added column (signed integer value) */ + +/*************** Bit definition for DCMIPP_P1CCTCR1 register ****************/ +#define DCMIPP_P1CCTCR1_ENABLE_Pos (0UL) +#define DCMIPP_P1CCTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CCTCR1_ENABLE DCMIPP_P1CCTCR1_ENABLE_Msk /*!< Current ENABLE bit value */ +#define DCMIPP_P1CCTCR1_LUM0_Pos (9UL) +#define DCMIPP_P1CCTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR1_LUM0 DCMIPP_P1CCTCR1_LUM0_Msk /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR2 register ****************/ +#define DCMIPP_P1CCTCR2_LUM4_Pos (1UL) +#define DCMIPP_P1CCTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR2_LUM4 DCMIPP_P1CCTCR2_LUM4_Msk /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM3_Pos (9UL) +#define DCMIPP_P1CCTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR2_LUM3 DCMIPP_P1CCTCR2_LUM3_Msk /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM2_Pos (17UL) +#define DCMIPP_P1CCTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR2_LUM2 DCMIPP_P1CCTCR2_LUM2_Msk /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR2_LUM1_Pos (25UL) +#define DCMIPP_P1CCTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR2_LUM1 DCMIPP_P1CCTCR2_LUM1_Msk /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CCTCR3 register ****************/ +#define DCMIPP_P1CCTCR3_LUM8_Pos (1UL) +#define DCMIPP_P1CCTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos) /*!< 0x0000007E */ +#define DCMIPP_P1CCTCR3_LUM8 DCMIPP_P1CCTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM7_Pos (9UL) +#define DCMIPP_P1CCTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos) /*!< 0x00007E00 */ +#define DCMIPP_P1CCTCR3_LUM7 DCMIPP_P1CCTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM6_Pos (17UL) +#define DCMIPP_P1CCTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos) /*!< 0x007E0000 */ +#define DCMIPP_P1CCTCR3_LUM6 DCMIPP_P1CCTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */ +#define DCMIPP_P1CCTCR3_LUM5_Pos (25UL) +#define DCMIPP_P1CCTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos) /*!< 0x7E000000 */ +#define DCMIPP_P1CCTCR3_LUM5 DCMIPP_P1CCTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */ + +/*************** Bit definition for DCMIPP_P1CFCTCR register ****************/ +#define DCMIPP_P1CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P1CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P1CFCTCR_FRATE DCMIPP_P1CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P1CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P1CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P1CFCTCR_CPTMODE DCMIPP_P1CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P1CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P1CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P1CFCTCR_CPTREQ DCMIPP_P1CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P1CCRSTR register ****************/ +#define DCMIPP_P1CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P1CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSTR_HSTART DCMIPP_P1CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P1CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSTR_VSTART DCMIPP_P1CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P1CCRSZR register ****************/ +#define DCMIPP_P1CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CCRSZR_HSIZE DCMIPP_P1CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CCRSZR_VSIZE DCMIPP_P1CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P1CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P1CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CCRSZR_ENABLE DCMIPP_P1CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P1CDCCR register *****************/ +#define DCMIPP_P1CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P1CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P1CDCCR_ENABLE DCMIPP_P1CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P1CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P1CDCCR_HDEC_Msk (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P1CDCCR_HDEC DCMIPP_P1CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P1CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P1CDCCR_VDEC_Msk (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P1CDCCR_VDEC DCMIPP_P1CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P1CDSCR register ****************/ +#define DCMIPP_P1CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P1CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P1CDSCR_HDIV DCMIPP_P1CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P1CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P1CDSCR_VDIV DCMIPP_P1CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P1CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P1CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P1CDSCR_ENABLE DCMIPP_P1CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P1CDSRTIOR register ***************/ +#define DCMIPP_P1CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P1CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P1CDSRTIOR_HRATIO DCMIPP_P1CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P1CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P1CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P1CDSRTIOR_VRATIO DCMIPP_P1CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P1CDSSZR register ****************/ +#define DCMIPP_P1CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P1CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P1CDSSZR_HSIZE DCMIPP_P1CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P1CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P1CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P1CDSSZR_VSIZE DCMIPP_P1CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P1CPPCR register ****************/ +#define DCMIPP_P1CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P1CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P1CPPCR_FORMAT DCMIPP_P1CPPCR_FORMAT_Msk /*!< Memory format */ +#define DCMIPP_P1CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P1CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P1CPPCR_SWAPRB DCMIPP_P1CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */ +#define DCMIPP_P1CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P1CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P1CPPCR_LINEMULT DCMIPP_P1CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ + +/************** Bit definition for DCMIPP_P1CPPM0AR1 register ***************/ +#define DCMIPP_P1CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P1CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM0AR1_M0A DCMIPP_P1CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/*************** Bit definition for DCMIPP_P1CPPM0PR register ***************/ +#define DCMIPP_P1CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM0PR_PITCH DCMIPP_P1CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM1AR1 register ***************/ +#define DCMIPP_P1CPPM1AR1_M1A_Pos (0UL) +#define DCMIPP_P1CPPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM1AR1_M1A DCMIPP_P1CPPM1AR1_M1A_Msk /*!< Memory1 address */ + +/*************** Bit definition for DCMIPP_P1CPPM1PR register ***************/ +#define DCMIPP_P1CPPM1PR_PITCH_Pos (0UL) +#define DCMIPP_P1CPPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P1CPPM1PR_PITCH DCMIPP_P1CPPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/************** Bit definition for DCMIPP_P1CPPM2AR1 register ***************/ +#define DCMIPP_P1CPPM2AR1_M2A_Pos (0UL) +#define DCMIPP_P1CPPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P1CPPM2AR1_M2A DCMIPP_P1CPPM2AR1_M2A_Msk /*!< Memory 2 address */ + +/**************** Bit definition for DCMIPP_P2FSCR register *****************/ +#define DCMIPP_P2FSCR_DTIDA_Pos (0UL) +#define DCMIPP_P2FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2FSCR_DTIDA DCMIPP_P2FSCR_DTIDA_Msk /*!< Data type ID */ +#define DCMIPP_P2FSCR_VC_Pos (19UL) +#define DCMIPP_P2FSCR_VC_Msk (0x3UL << DCMIPP_P2FSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2FSCR_VC DCMIPP_P2FSCR_VC_Msk /*!< Flow selection mode */ +#define DCMIPP_P2FSCR_FDTF_Pos (24UL) +#define DCMIPP_P2FSCR_FDTF_Msk (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2FSCR_FDTF DCMIPP_P2FSCR_FDTF_Msk /*!< Force Data type format */ +#define DCMIPP_P2FSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2FSCR_FDTFEN DCMIPP_P2FSCR_FDTFEN_Msk /*!< Force Data type format enable */ +#define DCMIPP_P2FSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2FSCR_PIPEN_Msk (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2FSCR_PIPEN DCMIPP_P2FSCR_PIPEN_Msk /*!< Activation of PipeN */ + +/**************** Bit definition for DCMIPP_P2FCTCR register ****************/ +#define DCMIPP_P2FCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2FCTCR_FRATE_Msk (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2FCTCR_FRATE DCMIPP_P2FCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2FCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCTCR_CPTMODE DCMIPP_P2FCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2FCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2FCTCR_CPTREQ DCMIPP_P2FCTCR_CPTREQ_Msk /*!< Capture requested */ + +/**************** Bit definition for DCMIPP_P2CRSTR register ****************/ +#define DCMIPP_P2CRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSTR_HSTART DCMIPP_P2CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSTR_VSTART DCMIPP_P2CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CRSZR register ****************/ +#define DCMIPP_P2CRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CRSZR_HSIZE DCMIPP_P2CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CRSZR_VSIZE DCMIPP_P2CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CRSZR_ENABLE DCMIPP_P2CRSZR_ENABLE_Msk /*!< */ + +/**************** Bit definition for DCMIPP_P2DCCR register *****************/ +#define DCMIPP_P2DCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2DCCR_ENABLE_Msk (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2DCCR_ENABLE DCMIPP_P2DCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2DCCR_HDEC_Pos (1UL) +#define DCMIPP_P2DCCR_HDEC_Msk (0x3UL << DCMIPP_P2DCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2DCCR_HDEC DCMIPP_P2DCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2DCCR_VDEC_Pos (3UL) +#define DCMIPP_P2DCCR_VDEC_Msk (0x3UL << DCMIPP_P2DCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2DCCR_VDEC DCMIPP_P2DCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2DSCR register *****************/ +#define DCMIPP_P2DSCR_HDIV_Pos (0UL) +#define DCMIPP_P2DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2DSCR_HDIV DCMIPP_P2DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_VDIV_Pos (16UL) +#define DCMIPP_P2DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2DSCR_VDIV DCMIPP_P2DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2DSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2DSCR_ENABLE_Msk (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2DSCR_ENABLE DCMIPP_P2DSCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2DSRTIOR register ***************/ +#define DCMIPP_P2DSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2DSRTIOR_HRATIO DCMIPP_P2DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2DSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2DSRTIOR_VRATIO DCMIPP_P2DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/**************** Bit definition for DCMIPP_P2DSSZR register ****************/ +#define DCMIPP_P2DSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2DSSZR_HSIZE DCMIPP_P2DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2DSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2DSSZR_VSIZE DCMIPP_P2DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2GMCR register *****************/ +#define DCMIPP_P2GMCR_ENABLE_Pos (0UL) +#define DCMIPP_P2GMCR_ENABLE_Msk (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2GMCR_ENABLE DCMIPP_P2GMCR_ENABLE_Msk /*!< */ + +/*************** Bit definition for DCMIPP_P2CMRICR register ***************/ +#define DCMIPP_P2CMRICR_ROILSZ_Pos (0UL) +#define DCMIPP_P2CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CMRICR_ROILSZ DCMIPP_P2CMRICR_ROILSZ_Msk /*!< Region of interest line size width */ +#define DCMIPP_P2CMRICR_ROI1EN_Pos (16UL) +#define DCMIPP_P2CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CMRICR_ROI1EN DCMIPP_P2CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */ +#define DCMIPP_P2CMRICR_ROI2EN_Pos (17UL) +#define DCMIPP_P2CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2CMRICR_ROI2EN DCMIPP_P2CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */ +#define DCMIPP_P2CMRICR_ROI3EN_Pos (18UL) +#define DCMIPP_P2CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos) /*!< 0x00040000 */ +#define DCMIPP_P2CMRICR_ROI3EN DCMIPP_P2CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */ +#define DCMIPP_P2CMRICR_ROI4EN_Pos (19UL) +#define DCMIPP_P2CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos) /*!< 0x00080000 */ +#define DCMIPP_P2CMRICR_ROI4EN DCMIPP_P2CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */ +#define DCMIPP_P2CMRICR_ROI5EN_Pos (20UL) +#define DCMIPP_P2CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CMRICR_ROI5EN DCMIPP_P2CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */ +#define DCMIPP_P2CMRICR_ROI6EN_Pos (21UL) +#define DCMIPP_P2CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos) /*!< 0x00200000 */ +#define DCMIPP_P2CMRICR_ROI6EN DCMIPP_P2CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */ +#define DCMIPP_P2CMRICR_ROI7EN_Pos (22UL) +#define DCMIPP_P2CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos) /*!< 0x00400000 */ +#define DCMIPP_P2CMRICR_ROI7EN DCMIPP_P2CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */ +#define DCMIPP_P2CMRICR_ROI8EN_Pos (23UL) +#define DCMIPP_P2CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2CMRICR_ROI8EN DCMIPP_P2CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */ + +/*************** Bit definition for DCMIPP_P2RIxCR1 register ***************/ +#define DCMIPP_P2RIxCR1_HSTART_Pos (0UL) +#define DCMIPP_P2RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR1_HSTART DCMIPP_P2RIxCR1_HSTART_Msk /*!< Horizontal start */ +#define DCMIPP_P2RIxCR1_CLB_Pos (12UL) +#define DCMIPP_P2RIxCR1_CLB_Msk (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos) /*!< 0x00003000 */ +#define DCMIPP_P2RIxCR1_CLB DCMIPP_P2RIxCR1_CLB_Msk /*!< Color line blue */ +#define DCMIPP_P2RIxCR1_CLG_Pos (14UL) +#define DCMIPP_P2RIxCR1_CLG_Msk (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos) /*!< 0x0000C000 */ +#define DCMIPP_P2RIxCR1_CLG DCMIPP_P2RIxCR1_CLG_Msk /*!< Color line green */ +#define DCMIPP_P2RIxCR1_VSTART_Pos (16UL) +#define DCMIPP_P2RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2RIxCR1_VSTART DCMIPP_P2RIxCR1_VSTART_Msk /*!< Vertical start */ +#define DCMIPP_P2RIxCR1_CLR_Pos (28UL) +#define DCMIPP_P2RIxCR1_CLR_Msk (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos) /*!< 0x30000000 */ +#define DCMIPP_P2RIxCR1_CLR DCMIPP_P2RIxCR1_CLR_Msk /*!< Color line red */ + +/*************** Bit definition for DCMIPP_P2RIxCR2 register ***************/ +#define DCMIPP_P2RIxCR2_VSIZE_Pos (0UL) +#define DCMIPP_P2RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2RIxCR2_VSIZE DCMIPP_P2RIxCR2_VSIZE_Msk /*!< Vertical Size */ +#define DCMIPP_P2RIxCR2_HSIZE_Pos (16UL) +#define DCMIPP_P2RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */ +#define DCMIPP_P2RIxCR2_HSIZE DCMIPP_P2RIxCR2_HSIZE_Msk /*!< Horizontal Size */ + +/**************** Bit definition for DCMIPP_P2PPCR register *****************/ +#define DCMIPP_P2PPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2PPCR_FORMAT_Msk (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2PPCR_FORMAT DCMIPP_P2PPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2PPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2PPCR_SWAPRB DCMIPP_P2PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2PPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2PPCR_LINEMULT DCMIPP_P2PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2PPCR_DBM_Pos (16UL) +#define DCMIPP_P2PPCR_DBM_Msk (0x1UL << DCMIPP_P2PPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2PPCR_DBM DCMIPP_P2PPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2PPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2PPCR_LMAWM_Msk (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2PPCR_LMAWM DCMIPP_P2PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2PPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2PPCR_LMAWE_Msk (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2PPCR_LMAWE DCMIPP_P2PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/*************** Bit definition for DCMIPP_P2PPM0AR1 register ***************/ +#define DCMIPP_P2PPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR1_M0A DCMIPP_P2PPM0AR1_M0A_Msk /*!< Memory0 address register 1 */ + +/*************** Bit definition for DCMIPP_P2PPM0AR2 register ***************/ +#define DCMIPP_P2PPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2PPM0AR2_M0A DCMIPP_P2PPM0AR2_M0A_Msk /*!< Memory0 address register 2*/ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2PPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2PPM0PR_PITCH DCMIPP_P2PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/ +#define DCMIPP_P2STM0AR_Pos (0UL) +#define DCMIPP_P2STM0AR_Msk (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2STM0AR DCMIPP_P2STM0AR_Msk /*!< Pipe2 status Memory0 address register */ + +/***************** Bit definition for DCMIPP_P2IER register *****************/ +#define DCMIPP_P2IER_LINEIE_Pos (0UL) +#define DCMIPP_P2IER_LINEIE_Msk (0x1UL << DCMIPP_P2IER_LINEIE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2IER_LINEIE DCMIPP_P2IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */ +#define DCMIPP_P2IER_FRAMEIE_Pos (1UL) +#define DCMIPP_P2IER_FRAMEIE_Msk (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2IER_FRAMEIE DCMIPP_P2IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */ +#define DCMIPP_P2IER_VSYNCIE_Pos (2UL) +#define DCMIPP_P2IER_VSYNCIE_Msk (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2IER_VSYNCIE DCMIPP_P2IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */ +#define DCMIPP_P2IER_OVRIE_Pos (7UL) +#define DCMIPP_P2IER_OVRIE_Msk (0x1UL << DCMIPP_P2IER_OVRIE_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2IER_OVRIE DCMIPP_P2IER_OVRIE_Msk /*!< Overrun interrupt enable */ + +/***************** Bit definition for DCMIPP_P2SR register ******************/ +#define DCMIPP_P2SR_LINEF_Pos (0UL) +#define DCMIPP_P2SR_LINEF_Msk (0x1UL << DCMIPP_P2SR_LINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2SR_LINEF DCMIPP_P2SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */ +#define DCMIPP_P2SR_FRAMEF_Pos (1UL) +#define DCMIPP_P2SR_FRAMEF_Msk (0x1UL << DCMIPP_P2SR_FRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2SR_FRAMEF DCMIPP_P2SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */ +#define DCMIPP_P2SR_VSYNCF_Pos (2UL) +#define DCMIPP_P2SR_VSYNCF_Msk (0x1UL << DCMIPP_P2SR_VSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2SR_VSYNCF DCMIPP_P2SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */ +#define DCMIPP_P2SR_OVRF_Pos (7UL) +#define DCMIPP_P2SR_OVRF_Msk (0x1UL << DCMIPP_P2SR_OVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2SR_OVRF DCMIPP_P2SR_OVRF_Msk /*!< Overrun raw interrupt status */ +#define DCMIPP_P2SR_LSTLINE_Pos (16UL) +#define DCMIPP_P2SR_LSTLINE_Msk (0x1UL << DCMIPP_P2SR_LSTLINE_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2SR_LSTLINE DCMIPP_P2SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_LSTFRM_Pos (17UL) +#define DCMIPP_P2SR_LSTFRM_Msk (0x1UL << DCMIPP_P2SR_LSTFRM_Pos) /*!< 0x00020000 */ +#define DCMIPP_P2SR_LSTFRM DCMIPP_P2SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */ +#define DCMIPP_P2SR_CPTACT_Pos (23UL) +#define DCMIPP_P2SR_CPTACT_Msk (0x1UL << DCMIPP_P2SR_CPTACT_Pos) /*!< 0x00800000 */ +#define DCMIPP_P2SR_CPTACT DCMIPP_P2SR_CPTACT_Msk /*!< Capture immediate status */ + +/***************** Bit definition for DCMIPP_P2FCR register *****************/ +#define DCMIPP_P2FCR_CLINEF_Pos (0UL) +#define DCMIPP_P2FCR_CLINEF_Msk (0x1UL << DCMIPP_P2FCR_CLINEF_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2FCR_CLINEF DCMIPP_P2FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CFRAMEF_Pos (1UL) +#define DCMIPP_P2FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos) /*!< 0x00000002 */ +#define DCMIPP_P2FCR_CFRAMEF DCMIPP_P2FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */ +#define DCMIPP_P2FCR_CVSYNCF_Pos (2UL) +#define DCMIPP_P2FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2FCR_CVSYNCF DCMIPP_P2FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */ +#define DCMIPP_P2FCR_COVRF_Pos (7UL) +#define DCMIPP_P2FCR_COVRF_Msk (0x1UL << DCMIPP_P2FCR_COVRF_Pos) /*!< 0x00000080 */ +#define DCMIPP_P2FCR_COVRF DCMIPP_P2FCR_COVRF_Msk /*!< Overrun interrupt status clear */ + +/**************** Bit definition for DCMIPP_P2CFSCR register ****************/ +#define DCMIPP_P2CFSCR_DTID_Pos (0UL) +#define DCMIPP_P2CFSCR_DTID_Msk (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos) /*!< 0x0000003F */ +#define DCMIPP_P2CFSCR_DTID DCMIPP_P2CFSCR_DTID_Msk /*!< Current Data type ID */ +#define DCMIPP_P2CFSCR_VC_Pos (19UL) +#define DCMIPP_P2CFSCR_VC_Msk (0x3UL << DCMIPP_P2CFSCR_VC_Pos) /*!< 0x00180000 */ +#define DCMIPP_P2CFSCR_VC DCMIPP_P2CFSCR_VC_Msk /*!< Current flow selection mode */ +#define DCMIPP_P2CFSCR_FDTF_Pos (24UL) +#define DCMIPP_P2CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos) /*!< 0x3F000000 */ +#define DCMIPP_P2CFSCR_FDTF DCMIPP_P2CFSCR_FDTF_Msk /*!< Current force Data type format */ +#define DCMIPP_P2CFSCR_FDTFEN_Pos (30UL) +#define DCMIPP_P2CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos) /*!< 0x40000000 */ +#define DCMIPP_P2CFSCR_FDTFEN DCMIPP_P2CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */ +#define DCMIPP_P2CFSCR_PIPEN_Pos (31UL) +#define DCMIPP_P2CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CFSCR_PIPEN DCMIPP_P2CFSCR_PIPEN_Msk /*!< Current activation of PipeN */ + +/*************** Bit definition for DCMIPP_P2CFCTCR register ****************/ +#define DCMIPP_P2CFCTCR_FRATE_Pos (0UL) +#define DCMIPP_P2CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos) /*!< 0x00000003 */ +#define DCMIPP_P2CFCTCR_FRATE DCMIPP_P2CFCTCR_FRATE_Msk /*!< Frame capture rate control */ +#define DCMIPP_P2CFCTCR_CPTMODE_Pos (2UL) +#define DCMIPP_P2CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */ +#define DCMIPP_P2CFCTCR_CPTMODE DCMIPP_P2CFCTCR_CPTMODE_Msk /*!< Capture mode */ +#define DCMIPP_P2CFCTCR_CPTREQ_Pos (3UL) +#define DCMIPP_P2CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */ +#define DCMIPP_P2CFCTCR_CPTREQ DCMIPP_P2CFCTCR_CPTREQ_Msk /*!< Capture requested */ + +/*************** Bit definition for DCMIPP_P2CCRSTR register ****************/ +#define DCMIPP_P2CCRSTR_HSTART_Pos (0UL) +#define DCMIPP_P2CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSTR_HSTART DCMIPP_P2CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSTR_VSTART_Pos (16UL) +#define DCMIPP_P2CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSTR_VSTART DCMIPP_P2CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */ + +/*************** Bit definition for DCMIPP_P2CCRSZR register ****************/ +#define DCMIPP_P2CCRSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CCRSZR_HSIZE DCMIPP_P2CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CCRSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CCRSZR_VSIZE DCMIPP_P2CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ +#define DCMIPP_P2CCRSZR_ENABLE_Pos (31UL) +#define DCMIPP_P2CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CCRSZR_ENABLE DCMIPP_P2CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */ + +/**************** Bit definition for DCMIPP_P2CDCCR register *****************/ +#define DCMIPP_P2CDCCR_ENABLE_Pos (0UL) +#define DCMIPP_P2CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos) /*!< 0x00000001 */ +#define DCMIPP_P2CDCCR_ENABLE DCMIPP_P2CDCCR_ENABLE_Msk /*!< Decimation enable */ +#define DCMIPP_P2CDCCR_HDEC_Pos (1UL) +#define DCMIPP_P2CDCCR_HDEC_Msk (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos) /*!< 0x00000006 */ +#define DCMIPP_P2CDCCR_HDEC DCMIPP_P2CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */ +#define DCMIPP_P2CDCCR_VDEC_Pos (3UL) +#define DCMIPP_P2CDCCR_VDEC_Msk (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos) /*!< 0x00000018 */ +#define DCMIPP_P2CDCCR_VDEC DCMIPP_P2CDCCR_VDEC_Msk /*!< Vertical decimation ratio */ + +/**************** Bit definition for DCMIPP_P2CDSCR register ****************/ +#define DCMIPP_P2CDSCR_HDIV_Pos (0UL) +#define DCMIPP_P2CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos) /*!< 0x000003FF */ +#define DCMIPP_P2CDSCR_HDIV DCMIPP_P2CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_VDIV_Pos (16UL) +#define DCMIPP_P2CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos) /*!< 0x03FF0000 */ +#define DCMIPP_P2CDSCR_VDIV DCMIPP_P2CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */ +#define DCMIPP_P2CDSCR_ENABLE_Pos (31UL) +#define DCMIPP_P2CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos) /*!< 0x80000000 */ +#define DCMIPP_P2CDSCR_ENABLE DCMIPP_P2CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */ + +/************** Bit definition for DCMIPP_P2CDSRTIOR register ***************/ +#define DCMIPP_P2CDSRTIOR_HRATIO_Pos (0UL) +#define DCMIPP_P2CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */ +#define DCMIPP_P2CDSRTIOR_HRATIO DCMIPP_P2CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */ +#define DCMIPP_P2CDSRTIOR_VRATIO_Pos (16UL) +#define DCMIPP_P2CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */ +#define DCMIPP_P2CDSRTIOR_VRATIO DCMIPP_P2CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */ + +/*************** Bit definition for DCMIPP_P2CDSSZR register ****************/ +#define DCMIPP_P2CDSSZR_HSIZE_Pos (0UL) +#define DCMIPP_P2CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */ +#define DCMIPP_P2CDSSZR_HSIZE DCMIPP_P2CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */ +#define DCMIPP_P2CDSSZR_VSIZE_Pos (16UL) +#define DCMIPP_P2CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */ +#define DCMIPP_P2CDSSZR_VSIZE DCMIPP_P2CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */ + +/**************** Bit definition for DCMIPP_P2CPPCR register ****************/ +#define DCMIPP_P2CPPCR_FORMAT_Pos (0UL) +#define DCMIPP_P2CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos) /*!< 0x0000000F */ +#define DCMIPP_P2CPPCR_FORMAT DCMIPP_P2CPPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */ +#define DCMIPP_P2CPPCR_SWAPRB_Pos (4UL) +#define DCMIPP_P2CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos) /*!< 0x00000010 */ +#define DCMIPP_P2CPPCR_SWAPRB DCMIPP_P2CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */ +#define DCMIPP_P2CPPCR_LINEMULT_Pos (13UL) +#define DCMIPP_P2CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */ +#define DCMIPP_P2CPPCR_LINEMULT DCMIPP_P2CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */ +#define DCMIPP_P2CPPCR_DBM_Pos (16UL) +#define DCMIPP_P2CPPCR_DBM_Msk (0x1UL << DCMIPP_P2CPPCR_DBM_Pos) /*!< 0x00010000 */ +#define DCMIPP_P2CPPCR_DBM DCMIPP_P2CPPCR_DBM_Msk /*!< Double buffer mode */ +#define DCMIPP_P2CPPCR_LMAWM_Pos (17UL) +#define DCMIPP_P2CPPCR_LMAWM_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos) /*!< 0x000E0000 */ +#define DCMIPP_P2CPPCR_LMAWM DCMIPP_P2CPPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */ +#define DCMIPP_P2CPPCR_LMAWE_Pos (20UL) +#define DCMIPP_P2CPPCR_LMAWE_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos) /*!< 0x00100000 */ +#define DCMIPP_P2CPPCR_LMAWE DCMIPP_P2CPPCR_LMAWE_Msk /*!< Line multi address wrapping enable */ + +/************** Bit definition for DCMIPP_P2CPPM0AR1 register ***************/ +#define DCMIPP_P2CPPM0AR1_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR1_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address */ + +/************** Bit definition for DCMIPP_P2CPPM0AR2 register ***************/ +#define DCMIPP_P2CPPM0AR2_M0A_Pos (0UL) +#define DCMIPP_P2CPPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_P2CPPM0AR2_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address Register 2 */ + +/*************** Bit definition for DCMIPP_P2CPPM0PR register ***************/ +#define DCMIPP_P2CPPM0PR_PITCH_Pos (0UL) +#define DCMIPP_P2CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */ +#define DCMIPP_P2CPPM0PR_PITCH DCMIPP_P2CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */ + +/**************** Bit definition for DCMIPP_HWCFGR2 register ****************/ +#define DCMIPP_HWCFGR2_VPFT_Pos (0UL) +#define DCMIPP_HWCFGR2_VPFT_Msk (0x7U << DCMIPP_HWCFGR2_VPFT_Pos) /*!< 0x00000007 */ +#define DCMIPP_HWCFGR2_VPFT DCMIPP_HWCFGR2_VPFT_Msk /*!< Virtual pipe function */ +#define DCMIPP_HWCFGR2_DBMFT_Pos (4UL) +#define DCMIPP_HWCFGR2_DBMFT_Msk (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos) /*!< 0x00000010 */ +#define DCMIPP_HWCFGR2_DBMFT DCMIPP_HWCFGR2_DBMFT_Msk /*!< Double buffer mode featured */ +#define DCMIPP_HWCFGR2_PROCCLK_Pos (8UL) +#define DCMIPP_HWCFGR2_PROCCLK_Msk (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR2_PROCCLK DCMIPP_HWCFGR2_PROCCLK_Msk /*!< Processing clock linked to AXI clock featured */ +#define DCMIPP_HWCFGR2_ADDMOD_Pos (12UL) +#define DCMIPP_HWCFGR2_ADDMOD_Msk (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR2_ADDMOD DCMIPP_HWCFGR2_ADDMOD_Msk /*!< Address modulo computation to access a small buffer in streaming featured */ +#define DCMIPP_HWCFGR2_DEC1_Pos (16UL) +#define DCMIPP_HWCFGR2_DEC1_Msk (0x1U << DCMIPP_HWCFGR2_DEC1_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR2_DEC1 DCMIPP_HWCFGR2_DEC1_Msk /*!< Decimation on Pipe1 before downsize */ +#define DCMIPP_HWCFGR2_DEC2_Pos (17UL) +#define DCMIPP_HWCFGR2_DEC2_Msk (0x1U << DCMIPP_HWCFGR2_DEC2_Pos) /*!< 0x00020000 */ +#define DCMIPP_HWCFGR2_DEC2 DCMIPP_HWCFGR2_DEC2_Msk /*!< Decimation on Pipe2 before downsize */ +#define DCMIPP_HWCFGR2_MCU_Pos (20UL) +#define DCMIPP_HWCFGR2_MCU_Msk (0x1U << DCMIPP_HWCFGR2_MCU_Pos) /*!< 0x00100000 */ +#define DCMIPP_HWCFGR2_MCU DCMIPP_HWCFGR2_MCU_Msk /*!< Macroblock unit as pixel format */ +#define DCMIPP_HWCFGR2_TPG_Pos (24UL) +#define DCMIPP_HWCFGR2_TPG_Msk (0x1U << DCMIPP_HWCFGR2_TPG_Pos) /*!< 0x01000000 */ +#define DCMIPP_HWCFGR2_TPG DCMIPP_HWCFGR2_TPG_Msk /*!< Test Pattern Generator */ +#define DCMIPP_HWCFGR2_STV_Pos (28UL) +#define DCMIPP_HWCFGR2_STV_Msk (0x1U << DCMIPP_HWCFGR2_STV_Pos) /*!< 0x10000000 */ +#define DCMIPP_HWCFGR2_STV DCMIPP_HWCFGR2_STV_Msk /*!< Statistic Version */ + +/**************** Bit definition for DCMIPP_HWCFGR1 register ****************/ +#define DCMIPP_HWCFGR1_CSIFT_Pos (0UL) +#define DCMIPP_HWCFGR1_CSIFT_Msk (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos) /*!< 0x00000001 */ +#define DCMIPP_HWCFGR1_CSIFT DCMIPP_HWCFGR1_CSIFT_Msk /*!< CSI2 host protocol compliant */ +#define DCMIPP_HWCFGR1_PIPENB_Pos (4UL) +#define DCMIPP_HWCFGR1_PIPENB_Msk (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos) /*!< 0x00000030 */ +#define DCMIPP_HWCFGR1_PIPENB DCMIPP_HWCFGR1_PIPENB_Msk /*!< Number of pipes */ +#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos (8UL) +#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos) /*!< 0x00000100 */ +#define DCMIPP_HWCFGR1_IPPLUGCFG DCMIPP_HWCFGR1_IPPLUGCFG_Msk /*!< IP-Plug configuration */ +#define DCMIPP_HWCFGR1_DSP1FT_Pos (12UL) +#define DCMIPP_HWCFGR1_DSP1FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos) /*!< 0x00001000 */ +#define DCMIPP_HWCFGR1_DSP1FT DCMIPP_HWCFGR1_DSP1FT_Msk /*!< Down-sampling feature for the pixel Pipe1 */ +#define DCMIPP_HWCFGR1_DSP2FT_Pos (13UL) +#define DCMIPP_HWCFGR1_DSP2FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos) /*!< 0x00002000 */ +#define DCMIPP_HWCFGR1_DSP2FT DCMIPP_HWCFGR1_DSP2FT_Msk /*!< Down-sampling feature for the pixel Pipe2 */ +#define DCMIPP_HWCFGR1_RB2RGB_Pos (16UL) +#define DCMIPP_HWCFGR1_RB2RGB_Msk (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos) /*!< 0x00010000 */ +#define DCMIPP_HWCFGR1_RB2RGB DCMIPP_HWCFGR1_RB2RGB_Msk /*!< Raw Bayer to RGB feature (demosaicer) */ +#define DCMIPP_HWCFGR1_PLANARFT_Pos (20UL) +#define DCMIPP_HWCFGR1_PLANARFT_Msk (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos) /*!< 0x00300000 */ +#define DCMIPP_HWCFGR1_PLANARFT DCMIPP_HWCFGR1_PLANARFT_Msk /*!< Buffer features for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI1NB_Pos (24UL) +#define DCMIPP_HWCFGR1_ROI1NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos) /*!< 0x0F000000 */ +#define DCMIPP_HWCFGR1_ROI1NB DCMIPP_HWCFGR1_ROI1NB_Msk /*!< Number of ROIs for Pipe1 */ +#define DCMIPP_HWCFGR1_ROI2NB_Pos (28UL) +#define DCMIPP_HWCFGR1_ROI2NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos) /*!< 0xF0000000 */ +#define DCMIPP_HWCFGR1_ROI2NB DCMIPP_HWCFGR1_ROI2NB_Msk /*!< Number of ROIs for Pipe2 */ + +/***************** Bit definition for DCMIPP_VERR register ******************/ +#define DCMIPP_VERR_MINREV_Pos (0UL) +#define DCMIPP_VERR_MINREV_Msk (0xFU << DCMIPP_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define DCMIPP_VERR_MINREV DCMIPP_VERR_MINREV_Msk /*!< DCMIPP minor revision */ +#define DCMIPP_VERR_MAJREV_Pos (4UL) +#define DCMIPP_VERR_MAJREV_Msk (0xFU << DCMIPP_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define DCMIPP_VERR_MAJREV DCMIPP_VERR_MAJREV_Msk /*!< DCMIPP major revision */ + +/***************** Bit definition for DCMIPP_IPIDR register *****************/ +#define DCMIPP_IPIDR_IDR_Pos (0UL) +#define DCMIPP_IPIDR_IDR_Msk (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_IPIDR_IDR DCMIPP_IPIDR_IDR_Msk /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */ + +/***************** Bit definition for DCMIPP_SIDR register ******************/ +#define DCMIPP_SIDR_SID_Pos (0UL) +#define DCMIPP_SIDR_SID_Msk (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define DCMIPP_SIDR_SID DCMIPP_SIDR_SID_Msk /*!< 4-Kbyte decoding space */ + +/******************************************************************************/ +/* */ +/* Delay Block Interface (DLYBSD) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DLYBSD_CFGR register ********************/ +#define DLYB_CFGR_SDMMC_DLL_EN_Pos (0UL) +#define DLYB_CFGR_SDMMC_DLL_EN_Msk (0x1UL << DLYB_CFGR_SDMMC_DLL_EN_Pos) /*!< 0x00000001 */ +#define DLYB_CFGR_SDMMC_DLL_EN DLYB_CFGR_SDMMC_DLL_EN_Msk /*!= AAW[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWHPCR_WHSPPOS_Pos (16UL) +#define LTDC_LxWHPCR_WHSPPOS_Msk (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos) +#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxWVPCR register */ +#define LTDC_LxWVPCR_WVSTPOS_Pos (0UL) +#define LTDC_LxWVPCR_WVSTPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos) +#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */ +#define LTDC_LxWVPCR_WVSPPOS_Pos (16UL) +#define LTDC_LxWVPCR_WVSPPOS_Msk (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos) +#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */ + +/* Bit fields for LTDC_LxCKCR register */ +#define LTDC_LxCKCR_CKBLUE_Pos (0UL) +#define LTDC_LxCKCR_CKBLUE_Msk (0xffUL << LTDC_LxCKCR_CKBLUE_Pos) +#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< color key blue value */ +#define LTDC_LxCKCR_CKGREEN_Pos (8UL) +#define LTDC_LxCKCR_CKGREEN_Msk (0xffUL << LTDC_LxCKCR_CKGREEN_Pos) +#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< color key green value */ +#define LTDC_LxCKCR_CKRED_Pos (16UL) +#define LTDC_LxCKCR_CKRED_Msk (0xffUL << LTDC_LxCKCR_CKRED_Pos) +#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< color key red value */ + +/* Bit fields for LTDC_LxPFCR register */ +#define LTDC_LxPFCR_PF_Pos (0UL) +#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) +#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */ + +/* Bit fields for LTDC_LxCACR register */ +#define LTDC_LxCACR_CONSTA_Pos (0UL) +#define LTDC_LxCACR_CONSTA_Msk (0xffUL << LTDC_LxCACR_CONSTA_Pos) +#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */ + +/* Bit fields for LTDC_LxDCCR register */ +#define LTDC_LxDCCR_DCBLUE_Pos (0UL) +#define LTDC_LxDCCR_DCBLUE_Msk (0xffUL << LTDC_LxDCCR_DCBLUE_Pos) +#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< default color blueThese bits configure the default blue value. */ +#define LTDC_LxDCCR_DCGREEN_Pos (8UL) +#define LTDC_LxDCCR_DCGREEN_Msk (0xffUL << LTDC_LxDCCR_DCGREEN_Pos) +#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< default color greenThese bits configure the default green value. */ +#define LTDC_LxDCCR_DCRED_Pos (16UL) +#define LTDC_LxDCCR_DCRED_Msk (0xffUL << LTDC_LxDCCR_DCRED_Pos) +#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< default color redThese bits configure the default red value. */ +#define LTDC_LxDCCR_DCALPHA_Pos (24UL) +#define LTDC_LxDCCR_DCALPHA_Msk (0xffUL << LTDC_LxDCCR_DCALPHA_Pos) +#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< default color alphaThese bits configure the default alpha value. */ + +/* Bit fields for LTDC_LxBFCR register */ +#define LTDC_LxBFCR_BF2_Pos (0UL) +#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) +#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */ +#define LTDC_LxBFCR_BF1_Pos (8UL) +#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) +#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */ +#define LTDC_LxBFCR_BOR_Pos (16UL) +#define LTDC_LxBFCR_BOR_Msk (0x1UL << LTDC_LxBFCR_BOR_Pos) +#define LTDC_LxBFCR_BOR LTDC_LxBFCR_BOR_Msk /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */ + +/* Bit fields for LTDC_LxBLCR register */ +#define LTDC_LxBLCR_BL_Pos (0UL) +#define LTDC_LxBLCR_BL_Msk (0x1fUL << LTDC_LxBLCR_BL_Pos) +#define LTDC_LxBLCR_BL LTDC_LxBLCR_BL_Msk /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */ + +/* Bit fields for LTDC_LxPCR register */ +#define LTDC_LxPCR_YCEN_Pos (3UL) +#define LTDC_LxPCR_YCEN_Msk (0x1UL << LTDC_LxPCR_YCEN_Pos) +#define LTDC_LxPCR_YCEN LTDC_LxPCR_YCEN_Msk /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */ +#define LTDC_LxPCR_YCM_Pos (4UL) +#define LTDC_LxPCR_YCM_Msk (0x3UL << LTDC_LxPCR_YCM_Pos) +#define LTDC_LxPCR_YCM LTDC_LxPCR_YCM_Msk /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */ +#define LTDC_LxPCR_YF_Pos (6UL) +#define LTDC_LxPCR_YF_Msk (0x1UL << LTDC_LxPCR_YF_Pos) +#define LTDC_LxPCR_YF LTDC_LxPCR_YF_Msk /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */ +#define LTDC_LxPCR_CBF_Pos (7UL) +#define LTDC_LxPCR_CBF_Msk (0x1UL << LTDC_LxPCR_CBF_Pos) +#define LTDC_LxPCR_CBF LTDC_LxPCR_CBF_Msk /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */ +#define LTDC_LxPCR_OF_Pos (8UL) +#define LTDC_LxPCR_OF_Msk (0x1UL << LTDC_LxPCR_OF_Pos) +#define LTDC_LxPCR_OF LTDC_LxPCR_OF_Msk /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */ +#define LTDC_LxPCR_YREN_Pos (9UL) +#define LTDC_LxPCR_YREN_Msk (0x1UL << LTDC_LxPCR_YREN_Pos) +#define LTDC_LxPCR_YREN LTDC_LxPCR_YREN_Msk /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */ + +/* Bit fields for LTDC_LxCFBAR register */ +#define LTDC_LxCFBAR_CFBADD_Pos (0UL) +#define LTDC_LxCFBAR_CFBADD_Msk (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos) +#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxCFBLR register */ +#define LTDC_LxCFBLR_CFBLL_Pos (0UL) +#define LTDC_LxCFBLR_CFBLL_Msk (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos) +#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_LxCFBLR_CFBP_Pos (16UL) +#define LTDC_LxCFBLR_CFBP_Msk (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos) +#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxCFBLNR register */ +#define LTDC_LxCFBLNR_CFBLNBR_Pos (0UL) +#define LTDC_LxCFBLNR_CFBLNBR_Msk (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos) +#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_L1AFBA0R register */ +#define LTDC_L1AFBA0R_AFBADD0_Pos (0UL) +#define LTDC_L1AFBA0R_AFBADD0_Msk (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos) +#define LTDC_L1AFBA0R_AFBADD0 LTDC_L1AFBA0R_AFBADD0_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBA1R register */ +#define LTDC_L1AFBA1R_AFBADD1_Pos (0UL) +#define LTDC_L1AFBA1R_AFBADD1_Msk (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos) +#define LTDC_L1AFBA1R_AFBADD1 LTDC_L1AFBA1R_AFBADD1_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */ + +/* Bit fields for LTDC_LxAFBLR register */ +#define LTDC_L1AFBLR_AFBLL_Pos (0UL) +#define LTDC_L1AFBLR_AFBLL_Msk (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos) +#define LTDC_L1AFBLR_AFBLL LTDC_L1AFBLR_AFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */ +#define LTDC_L1AFBLR_AFBP_Pos (16UL) +#define LTDC_L1AFBLR_AFBP_Msk (0xffffUL << LTDC_L1AFBLR_AFBP_Pos) +#define LTDC_L1AFBLR_AFBP LTDC_L1AFBLR_AFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */ + +/* Bit fields for LTDC_LxAFBLNR register */ +#define LTDC_L1AFBLNR_AFBLNBR_Pos (0UL) +#define LTDC_L1AFBLNR_AFBLNBR_Msk (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos) +#define LTDC_L1AFBLNR_AFBLNBR LTDC_L1AFBLNR_AFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */ + +/* Bit fields for LTDC_LxCLUTWR register */ +#define LTDC_LxCLUTWR_BLUE_Pos (0UL) +#define LTDC_LxCLUTWR_BLUE_Msk (0xffUL << LTDC_LxCLUTWR_BLUE_Pos) +#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< blue valueThese bits configure the blue value. */ +#define LTDC_LxCLUTWR_GREEN_Pos (8UL) +#define LTDC_LxCLUTWR_GREEN_Msk (0xffUL << LTDC_LxCLUTWR_GREEN_Pos) +#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< green valueThese bits configure the green value. */ +#define LTDC_LxCLUTWR_RED_Pos (16UL) +#define LTDC_LxCLUTWR_RED_Msk (0xffUL << LTDC_LxCLUTWR_RED_Pos) +#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< red valueThese bits configure the red value. */ +#define LTDC_LxCLUTWR_CLUTADD_Pos (24UL) +#define LTDC_LxCLUTWR_CLUTADD_Msk (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos) +#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */ + +/* Bit fields for LTDC_LxCYR0R register */ +#define LTDC_LxCYR0R_CR2R_Pos (0UL) +#define LTDC_LxCYR0R_CR2R_Msk (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos) +#define LTDC_LxCYR0R_CR2R LTDC_LxCYR0R_CR2R_Msk /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR0R_CB2B_Pos (16UL) +#define LTDC_LxCYR0R_CB2B_Msk (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos) +#define LTDC_LxCYR0R_CB2B LTDC_LxCYR0R_CB2B_Msk /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxCYR1R register */ +#define LTDC_LxCYR1R_CR2G_Pos (0UL) +#define LTDC_LxCYR1R_CR2G_Msk (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos) +#define LTDC_LxCYR1R_CR2G LTDC_LxCYR1R_CR2G_Msk /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ +#define LTDC_LxCYR1R_CB2G_Pos (16UL) +#define LTDC_LxCYR1R_CB2G_Msk (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos) +#define LTDC_LxCYR1R_CB2G LTDC_LxCYR1R_CB2G_Msk /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */ + +/* Bit fields for LTDC_LxFPF0R register */ +#define LTDC_LxFPF0R_APOS_Pos (0UL) +#define LTDC_LxFPF0R_APOS_Msk (0x1fUL << LTDC_LxFPF0R_APOS_Pos) +#define LTDC_LxFPF0R_APOS LTDC_LxFPF0R_APOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_ALEN_Pos (5UL) +#define LTDC_LxFPF0R_ALEN_Msk (0xfUL << LTDC_LxFPF0R_ALEN_Pos) +#define LTDC_LxFPF0R_ALEN LTDC_LxFPF0R_ALEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF0R_RPOS_Pos (9UL) +#define LTDC_LxFPF0R_RPOS_Msk (0x1fUL << LTDC_LxFPF0R_RPOS_Pos) +#define LTDC_LxFPF0R_RPOS LTDC_LxFPF0R_RPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF0R_RLEN_Pos (14UL) +#define LTDC_LxFPF0R_RLEN_Msk (0xfUL << LTDC_LxFPF0R_RLEN_Pos) +#define LTDC_LxFPF0R_RLEN LTDC_LxFPF0R_RLEN_Msk /*!< Width of the red component (in bits). */ + +/* Bit fields for LTDC_LxFPF1R register */ +#define LTDC_LxFPF1R_GPOS_Pos (0UL) +#define LTDC_LxFPF1R_GPOS_Msk (0x1fUL << LTDC_LxFPF1R_GPOS_Pos) +#define LTDC_LxFPF1R_GPOS LTDC_LxFPF1R_GPOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_GLEN_Pos (5UL) +#define LTDC_LxFPF1R_GLEN_Msk (0xfUL << LTDC_LxFPF1R_GLEN_Pos) +#define LTDC_LxFPF1R_GLEN LTDC_LxFPF1R_GLEN_Msk /*!< Width of the alpha component (in bits). */ + +#define LTDC_LxFPF1R_BPOS_Pos (9UL) +#define LTDC_LxFPF1R_BPOS_Msk (0x1fUL << LTDC_LxFPF1R_BPOS_Pos) +#define LTDC_LxFPF1R_BPOS LTDC_LxFPF1R_BPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */ + +#define LTDC_LxFPF1R_BLEN_Pos (14UL) +#define LTDC_LxFPF1R_BLEN_Msk (0xfUL << LTDC_LxFPF1R_BLEN_Pos) +#define LTDC_LxFPF1R_BLEN LTDC_LxFPF1R_BLEN_Msk /*!< Width of the red component (in bits). */ + +#define LTDC_LxFPF1R_PSIZE_Pos (18UL) +#define LTDC_LxFPF1R_PSIZE_Msk (0x7UL << LTDC_LxFPF1R_PSIZE_Pos) +#define LTDC_LxFPF1R_PSIZE LTDC_LxFPF1R_PSIZE_Msk /*!< Width of the red component (in bits). */ + + +/******************************************************************************/ +/* */ +/* Memory Cipher Engine (MCE) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for MCE_CR register ********************/ +#define MCE_CR_GLOCK_Pos (0UL) +#define MCE_CR_GLOCK_Msk (0x1UL << MCE_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define MCE_CR_GLOCK MCE_CR_GLOCK_Msk /*!< MCE global lock */ +#define MCE_CR_MKLOCK_Pos (1UL) +#define MCE_CR_MKLOCK_Msk (0x1UL << MCE_CR_MKLOCK_Pos) /*!< 0x00000002 */ +#define MCE_CR_MKLOCK MCE_CR_MKLOCK_Msk /*!< MCE master and fast master keys lock */ +#define MCE_CR_CIPHERSEL_Pos (4UL) +#define MCE_CR_CIPHERSEL_Msk (0x3UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000030 */ +#define MCE_CR_CIPHERSEL MCE_CR_CIPHERSEL_Msk /*!< MCE Cipher selection */ +#define MCE_CR_CIPHERSEL_0 (0x1UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000010 */ +#define MCE_CR_CIPHERSEL_1 (0x2UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000020 */ + +/******************** Bit definition for MCE_SR register ********************/ +#define MCE_SR_MKVALID_Pos (0UL) +#define MCE_SR_MKVALID_Msk (0x1UL << MCE_SR_MKVALID_Pos) /*!< 0x00000001 */ +#define MCE_SR_MKVALID MCE_SR_MKVALID_Msk /*!< MCE master key valid flag */ +#define MCE_SR_FMKVALID_Pos (2UL) +#define MCE_SR_FMKVALID_Msk (0x1UL << MCE_SR_FMKVALID_Pos) /*!< 0x00000004 */ +#define MCE_SR_FMKVALID MCE_SR_FMKVALID_Msk /*!< MCE fast master key valid flag */ +#define MCE_SR_ENCDIS_Pos (4UL) +#define MCE_SR_ENCDIS_Msk (0x1UL << MCE_SR_ENCDIS_Pos) /*!< 0x00000010 */ +#define MCE_SR_ENCDIS MCE_SR_ENCDIS_Msk /*!< MCE encryption disabled flag */ + +/******************** Bit definition for MCE_IASR register ******************/ +#define MCE_IASR_IAEF_Pos (1UL) +#define MCE_IASR_IAEF_Msk (0x1UL << MCE_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define MCE_IASR_IAEF MCE_IASR_IAEF_Msk /*!< MCE illegal access error flag */ + +/******************** Bit definition for MCE_IACR register ******************/ +#define MCE_IACR_IAEF_Pos (1UL) +#define MCE_IACR_IAEF_Msk (0x1UL << MCE_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define MCE_IACR_IAEF MCE_IACR_IAEF_Msk /*!< MCE illegal access error clear bit */ + +/******************** Bit definition for MCE_IAIER register *****************/ +#define MCE_IAIER_IAEIE_Pos (1UL) +#define MCE_IAIER_IAEIE_Msk (0x1UL << MCE_IAIER_IAEIE_Pos) /*!< 0x00000002 */ +#define MCE_IAIER_IAEIE MCE_IAIER_IAEIE_Msk /*!< MCE illegal access error interrupt enable */ + +/******************** Bit definition for MCE_IADDR register *****************/ +#define MCE_IADDR_IADD_Pos (0UL) +#define MCE_IADDR_IADD_Msk (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define MCE_IADDR_IADD MCE_IADDR_IADD_Msk /*!< MCE illegal access */ + +/******************** Bit definition for MCE_REGCR register *****************/ +#define MCE_REGCR_BREN_Pos (0UL) +#define MCE_REGCR_BREN_Msk (0x1UL << MCE_REGCR_BREN_Pos) /*!< 0x00000001 */ +#define MCE_REGCR_BREN MCE_REGCR_BREN_Msk /*!< MCE base region enable */ +#define MCE_REGCR_CTXID_Pos (9UL) +#define MCE_REGCR_CTXID_Msk (0x3UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000600 */ +#define MCE_REGCR_CTXID MCE_REGCR_CTXID_Msk /*!< MCE context ID */ +#define MCE_REGCR_CTXID_0 (0x1UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000200 */ +#define MCE_REGCR_CTXID_1 (0x2UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000400 */ +#define MCE_REGCR_ENC_Pos (14UL) +#define MCE_REGCR_ENC_Msk (0x3UL << MCE_REGCR_ENC_Pos) /*!< 0x0000C000 */ +#define MCE_REGCR_ENC MCE_REGCR_ENC_Msk /*!< MCE encrypted region */ +#define MCE_REGCR_ENC_0 (0x1UL << MCE_REGCR_ENC_Pos) /*!< 0x00004000 */ +#define MCE_REGCR_ENC_1 (0x2UL << MCE_REGCR_ENC_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for MCE_SADDR register *****************/ +#define MCE_SADDR_BADDSTART_Pos (12UL) +#define MCE_SADDR_BADDSTART_Msk (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos) /*!< 0xFFFFF000 */ +#define MCE_SADDR_BADDSTART MCE_SADDR_BADDSTART_Msk /*!< MCE region address start */ + +/******************** Bit definition for MCE_EADDR register *****************/ +#define MCE_EADDR_BADDEND_Pos (12UL) +#define MCE_EADDR_BADDEND_Msk (0xFFFFFUL << MCE_EADDR_BADDEND_Pos) /*!< 0xFFFFF000 */ +#define MCE_EADDR_BADDEND MCE_EADDR_BADDEND_Msk /*!< MCE region address end */ + +/******************** Bit definition for MCE_MKEYR0 register ****************/ +#define MCE_MKEYR0_MKEY_Pos (0UL) +#define MCE_MKEYR0_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR0_MKEY MCE_MKEYR0_MKEY_Msk /*!< MCE master key, bits [31:0] */ + +/******************** Bit definition for MCE_MKEYR1 register ****************/ +#define MCE_MKEYR1_MKEY_Pos (0UL) +#define MCE_MKEYR1_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR1_MKEY MCE_MKEYR1_MKEY_Msk /*!< MCE master key, bits [63:32] */ + +/******************** Bit definition for MCE_MKEYR2 register ****************/ +#define MCE_MKEYR2_MKEY_Pos (0UL) +#define MCE_MKEYR2_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR2_MKEY MCE_MKEYR2_MKEY_Msk /*!< MCE master key, bits [95:64] */ + +/******************** Bit definition for MCE_MKEYR3 register ****************/ +#define MCE_MKEYR3_MKEY_Pos (0UL) +#define MCE_MKEYR3_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR3_MKEY MCE_MKEYR3_MKEY_Msk /*!< MCE master key, bits [127:96] */ + +/******************** Bit definition for MCE_MKEYR4 register ****************/ +#define MCE_MKEYR4_MKEY_Pos (0UL) +#define MCE_MKEYR4_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR4_MKEY MCE_MKEYR4_MKEY_Msk /*!< MCE master key, bits [159:128] */ + +/******************** Bit definition for MCE_MKEYR5 register ****************/ +#define MCE_MKEYR5_MKEY_Pos (0UL) +#define MCE_MKEYR5_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR5_MKEY MCE_MKEYR5_MKEY_Msk /*!< MCE master key, bits [191:160] */ + +/******************** Bit definition for MCE_MKEYR6 register ****************/ +#define MCE_MKEYR6_MKEY_Pos (0UL) +#define MCE_MKEYR6_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR6_MKEY MCE_MKEYR6_MKEY_Msk /*!< MCE master key, bits [223:192] */ + +/******************** Bit definition for MCE_MKEYR7 register ****************/ +#define MCE_MKEYR7_MKEY_Pos (0UL) +#define MCE_MKEYR7_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_MKEYR7_MKEY MCE_MKEYR7_MKEY_Msk /*!< MCE master key, bits [255:224] */ + +/******************** Bit definition for MCE_FMKEYR0 register ***************/ +#define MCE_FMKEYR0_FMKEY_Pos (0UL) +#define MCE_FMKEYR0_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR0_FMKEY MCE_FMKEYR0_FMKEY_Msk /*!< MCE fast master key, bits [31:0] */ + +/******************** Bit definition for MCE_FMKEYR1 register ***************/ +#define MCE_FMKEYR1_FMKEY_Pos (0UL) +#define MCE_FMKEYR1_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR1_FMKEY MCE_FMKEYR1_FMKEY_Msk /*!< MCE fast master key, bits [63:32] */ + +/******************** Bit definition for MCE_FMKEYR2 register ***************/ +#define MCE_FMKEYR2_FMKEY_Pos (0UL) +#define MCE_FMKEYR2_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR2_FMKEY MCE_FMKEYR2_FMKEY_Msk /*!< MCE fast master key, bits [95:64] */ + +/******************** Bit definition for MCE_FMKEYR3 register ***************/ +#define MCE_FMKEYR3_FMKEY_Pos (0UL) +#define MCE_FMKEYR3_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR3_FMKEY MCE_FMKEYR3_FMKEY_Msk /*!< MCE fast master key, bits [127:96] */ + +/******************** Bit definition for MCE_FMKEYR4 register ****************/ +#define MCE_FMKEYR4_FMKEY_Pos (0UL) +#define MCE_FMKEYR4_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR4_FMKEY MCE_FMKEYR4_FMKEY_Msk /*!< MCE fast master key, bits [159:128] */ + +/******************** Bit definition for MCE_FMKEYR5 register ****************/ +#define MCE_FMKEYR5_FMKEY_Pos (0UL) +#define MCE_FMKEYR5_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR5_FMKEY MCE_FMKEYR5_FMKEY_Msk /*!< MCE fast master key, bits [191:160] */ + +/******************** Bit definition for MCE_FMKEYR6 register ****************/ +#define MCE_FMKEYR6_FMKEY_Pos (0UL) +#define MCE_FMKEYR6_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR6_FMKEY MCE_FMKEYR6_FMKEY_Msk /*!< MCE fast master key, bits [223:192] */ + +/******************** Bit definition for MCE_FMKEYR7 register ****************/ +#define MCE_FMKEYR7_FMKEY_Pos (0UL) +#define MCE_FMKEYR7_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_FMKEYR7_FMKEY MCE_FMKEYR7_FMKEY_Msk /*!< MCE fast master key, bits [255:224] */ + +/******************** Bit definition for MCE_CCCFGR register ****************/ +#define MCE_CCCFGR_CCEN_Pos (0UL) +#define MCE_CCCFGR_CCEN_Msk (0x1UL << MCE_CCCFGR_CCEN_Pos) /*!< 0x00000001 */ +#define MCE_CCCFGR_CCEN MCE_CCCFGR_CCEN_Msk /*!< MCE cipher context enable */ +#define MCE_CCCFGR_CCLOCK_Pos (1UL) +#define MCE_CCCFGR_CCLOCK_Msk (0x1UL << MCE_CCCFGR_CCLOCK_Pos) /*!< 0x00000002 */ +#define MCE_CCCFGR_CCLOCK MCE_CCCFGR_CCLOCK_Msk /*!< MCE cipher context lock */ +#define MCE_CCCFGR_KEYLOCK_Pos (2UL) +#define MCE_CCCFGR_KEYLOCK_Msk (0x1UL << MCE_CCCFGR_KEYLOCK_Pos) /*!< 0x00000004 */ +#define MCE_CCCFGR_KEYLOCK MCE_CCCFGR_KEYLOCK_Msk /*!< MCE cipher context key lock */ +#define MCE_CCCFGR_MODE_Pos (4UL) +#define MCE_CCCFGR_MODE_Msk (0x3UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000030 */ +#define MCE_CCCFGR_MODE MCE_CCCFGR_MODE_Msk /*!< MCE authorized cipher mode */ +#define MCE_CCCFGR_MODE_0 (0x1UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000010 */ +#define MCE_CCCFGR_MODE_1 (0x2UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000020 */ +#define MCE_CCCFGR_KEYCRC_Pos (8UL) +#define MCE_CCCFGR_KEYCRC_Msk (0xFFUL << MCE_CCCFGR_KEYCRC_Pos) /*!< 0x0000FF00 */ +#define MCE_CCCFGR_KEYCRC MCE_CCCFGR_KEYCRC_Msk /*!< MCE cipher context key CRC */ +#define MCE_CCCFGR_VERSION_Pos (16UL) +#define MCE_CCCFGR_VERSION_Msk (0xFFFFUL << MCE_CCCFGR_VERSION_Pos) /*!< 0xFFFF0000 */ +#define MCE_CCCFGR_VERSION MCE_CCCFGR_VERSION_Msk /*!< MCE cipher context version */ + +/******************** Bit definition for MCE_CCNR0 register *****************/ +#define MCE_CCNR0_SCNONCE_Pos (0UL) +#define MCE_CCNR0_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCNR0_SCNONCE MCE_CCNR0_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [31:0] */ + +/******************** Bit definition for MCE_CCNR1 register ****************/ +#define MCE_CCNR1_SCNONCE_Pos (0UL) +#define MCE_CCNR1_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCNR1_SCNONCE MCE_CCNR1_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [63:32] */ + +/******************** Bit definition for MCE_CCKEYR0 register ***************/ +#define MCE_CCKEYR0_KEY_Pos (0UL) +#define MCE_CCKEYR0_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR0_KEY MCE_CCKEYR0_KEY_Msk /*!< MCE cipher context key, bits [31:0] */ + +/******************** Bit definition for MCE_CCKEYR1 register ***************/ +#define MCE_CCKEYR1_KEY_Pos (0UL) +#define MCE_CCKEYR1_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR1_KEY MCE_CCKEYR1_KEY_Msk /*!< MCE fast master key, bits [63:32] */ + +/******************** Bit definition for MCE_CCKEYR2 register ***************/ +#define MCE_CCKEYR2_KEY_Pos (0UL) +#define MCE_CCKEYR2_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR2_KEY MCE_CCKEYR2_KEY_Msk /*!< MCE fast master key, bits [95:64] */ + +/******************** Bit definition for MCE_CCKEYR3 register ***************/ +#define MCE_CCKEYR3_KEY_Pos (0UL) +#define MCE_CCKEYR3_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos) /*!< 0xFFFFFFFF */ +#define MCE_CCKEYR3_KEY MCE_CCKEYR3_KEY_Msk /*!< MCE fast master key, bits [127:96] */ + + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ****************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*!< Trigger output control */ +#define MDF_GCR_ILVNB_Pos (4UL) +#define MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) /*!< 0x000000F0 */ +#define MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk /*!< Interleaved Number */ + +/******************* Bit definition for MDF/ADF_CKGCR register ********************/ +#define MDF_CKGCR_CKDEN_Pos (0UL) +#define MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) /*!< 0x00000001 */ +#define MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5UL) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6UL) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8UL) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10UL) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14UL) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18UL) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29UL) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30UL) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31UL) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2UL) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3UL) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register *******************/ +#define PSSI_RIS_OVR_RIS_Pos (1UL) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register *******************/ +#define PSSI_IER_OVR_IE_Pos (1UL) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register *******************/ +#define PSSI_MIS_OVR_MIS_Pos (1UL) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register *******************/ +#define PSSI_ICR_OVR_ISC_Pos (1UL) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0UL) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************* Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_SDEN_Pos (2UL) +#define PWR_CR1_SDEN_Msk (0x1UL << PWR_CR1_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CR1_SDEN PWR_CR1_SDEN_Msk /*!< SMPS step-down converter enable */ +#define PWR_CR1_MODE_PDN_Pos (4UL) +#define PWR_CR1_MODE_PDN_Msk (0x1UL << PWR_CR1_MODE_PDN_Pos) /*!< 0x00000010 */ +#define PWR_CR1_MODE_PDN PWR_CR1_MODE_PDN_Msk /*!< Pull down on output voltage during power down mode */ +#define PWR_CR1_LPDS08V_Pos (5UL) +#define PWR_CR1_LPDS08V_Msk (0x1UL << PWR_CR1_LPDS08V_Pos) /*!< 0x00000020 */ +#define PWR_CR1_LPDS08V PWR_CR1_LPDS08V_Msk /*!< SMPS Low power mode enable (SVOS high only) */ +#define PWR_CR1_VDD18SMPSVMEN_Pos (8UL) +#define PWR_CR1_VDD18SMPSVMEN_Msk (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos) /*!< 0x00000100 */ +#define PWR_CR1_VDD18SMPSVMEN PWR_CR1_VDD18SMPSVMEN_Msk /*!< VDD18SMPS voltage monitor enable */ +#define PWR_CR1_VDD18SMPSRDY_Pos (15UL) +#define PWR_CR1_VDD18SMPSRDY_Msk (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos) /*!< 0x00008000 */ +#define PWR_CR1_VDD18SMPSRDY PWR_CR1_VDD18SMPSRDY_Msk /*!< VDD18SMPS ready */ +#define PWR_CR1_POPL_Pos (16UL) +#define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */ +#define PWR_CR1_POPL PWR_CR1_POPL_Msk /*!< pwr_on pulse low configuration */ +#define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */ +#define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */ +#define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */ +#define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */ +#define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */ + +/******************* Bit definition for PWR_CR2 register ********************/ +#define PWR_CR2_PVDEN_Pos (0UL) +#define PWR_CR2_PVDEN_Msk (0x1UL << PWR_CR2_PVDEN_Pos) /*!< 0x00000001 */ +#define PWR_CR2_PVDEN PWR_CR2_PVDEN_Msk /*!< Programmable Voltage detector enable */ +#define PWR_CR2_PVDO_Pos (8UL) +#define PWR_CR2_PVDO_Msk (0x1UL << PWR_CR2_PVDO_Pos) /*!< 0x00000100 */ +#define PWR_CR2_PVDO PWR_CR2_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +/******************* Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_VCOREMONEN_Pos (0UL) +#define PWR_CR3_VCOREMONEN_Msk (0x1UL << PWR_CR3_VCOREMONEN_Pos) /*!< 0x00000001 */ +#define PWR_CR3_VCOREMONEN PWR_CR3_VCOREMONEN_Msk /*!< VDDCORE monitoring enable */ +#define PWR_CR3_VCORELLS_Pos (4UL) +#define PWR_CR3_VCORELLS_Msk (0x1UL << PWR_CR3_VCORELLS_Pos) /*!< 0x00000010 */ +#define PWR_CR3_VCORELLS PWR_CR3_VCORELLS_Msk /*!< VDDCORE Voltage Detector low level selection */ +#define PWR_CR3_VCOREL_Pos (8UL) +#define PWR_CR3_VCOREL_Msk (0x1UL << PWR_CR3_VCOREL_Pos) /*!< 0x00000100 */ +#define PWR_CR3_VCOREL PWR_CR3_VCOREL_Msk /*!< Monitored VDDCORE level above low threshold */ +#define PWR_CR3_VCOREH_Pos (9UL) +#define PWR_CR3_VCOREH_Msk (0x1UL << PWR_CR3_VCOREH_Pos) /*!< 0x00000200 */ +#define PWR_CR3_VCOREH PWR_CR3_VCOREH_Msk /*!< Monitored VDDCORE level above high threshold */ + +/******************* Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_TCMRBSEN_Pos (0UL) +#define PWR_CR4_TCMRBSEN_Msk (0x1UL << PWR_CR4_TCMRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_CR4_TCMRBSEN PWR_CR4_TCMRBSEN_Msk /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */ +#define PWR_CR4_TCMFLXRBSEN_Pos (4UL) +#define PWR_CR4_TCMFLXRBSEN_Msk (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos) /*!< 0x00000010 */ +#define PWR_CR4_TCMFLXRBSEN PWR_CR4_TCMFLXRBSEN_Msk /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */ + +/****************** Bit definition for PWR_VOSCR register *******************/ +#define PWR_VOSCR_VOS_Pos (0UL) +#define PWR_VOSCR_VOS_Msk (0x1UL << PWR_VOSCR_VOS_Pos) /*!< 0x00000001 */ +#define PWR_VOSCR_VOS PWR_VOSCR_VOS_Msk /*!< Voltage scaling selection according to performance */ +#define PWR_VOSCR_VOSRDY_Pos (1UL) +#define PWR_VOSCR_VOSRDY_Msk (0x1UL << PWR_VOSCR_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_VOSCR_VOSRDY PWR_VOSCR_VOSRDY_Msk /*!< VOS Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSCR_ACTVOS_Pos (16UL) +#define PWR_VOSCR_ACTVOS_Msk (0x1UL << PWR_VOSCR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSCR_ACTVOS PWR_VOSCR_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ +#define PWR_VOSCR_ACTVOSRDY_Pos (17UL) +#define PWR_VOSCR_ACTVOSRDY_Msk (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos) /*!< 0x00020000 */ +#define PWR_VOSCR_ACTVOSRDY PWR_VOSCR_ACTVOSRDY_Msk /*!< Voltage levels ready bit for currently used ACTVOS */ + +/****************** Bit definition for PWR_BDCR1 register *******************/ +#define PWR_BDCR1_MONEN_Pos (0UL) +#define PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ +#define PWR_BDCR1_VBATL_Pos (16UL) +#define PWR_BDCR1_VBATL_Msk (0x1UL << PWR_BDCR1_VBATL_Pos) /*!< 0x00010000 */ +#define PWR_BDCR1_VBATL PWR_BDCR1_VBATL_Msk /*!< VBAT level monitoring versus low threshold */ +#define PWR_BDCR1_VBATH_Pos (17UL) +#define PWR_BDCR1_VBATH_Msk (0x1UL << PWR_BDCR1_VBATH_Pos) /*!< 0x00020000 */ +#define PWR_BDCR1_VBATH PWR_BDCR1_VBATH_Msk /*!< VBAT level monitoring versus high threshold */ +#define PWR_BDCR1_TEMPL_Pos (18UL) +#define PWR_BDCR1_TEMPL_Msk (0x1UL << PWR_BDCR1_TEMPL_Pos) /*!< 0x00040000 */ +#define PWR_BDCR1_TEMPL PWR_BDCR1_TEMPL_Msk /*!< Temperature level monitoring versus low threshold */ +#define PWR_BDCR1_TEMPH_Pos (19UL) +#define PWR_BDCR1_TEMPH_Msk (0x1UL << PWR_BDCR1_TEMPH_Pos) /*!< 0x00080000 */ +#define PWR_BDCR1_TEMPH PWR_BDCR1_TEMPH_Msk /*!< Temperature level monitoring versus high threshold */ + +/****************** Bit definition for PWR_BDCR2 register *******************/ +#define PWR_BDCR2_BKPRBSEN_Pos (0UL) +#define PWR_BDCR2_BKPRBSEN_Msk (0x1UL << PWR_BDCR2_BKPRBSEN_Pos) /*!< 0x00000001 */ +#define PWR_BDCR2_BKPRBSEN PWR_BDCR2_BKPRBSEN_Msk /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */ + +/****************** Bit definition for PWR_DBPCR register *******************/ +#define PWR_DBPCR_DBP_Pos (0UL) +#define PWR_DBPCR_DBP_Msk (0x1UL << PWR_DBPCR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPCR_DBP PWR_DBPCR_DBP_Msk /*!< Disable backup domain write protection */ + +/****************** Bit definition for PWR_CPUCR register *******************/ +#define PWR_CPUCR_PDDS_Pos (0UL) +#define PWR_CPUCR_PDDS_Msk (0x1UL << PWR_CPUCR_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CPUCR_PDDS PWR_CPUCR_PDDS_Msk /*!< Power Down Deepsleep selection */ +#define PWR_CPUCR_CSSF_Pos (1UL) +#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear Standby and Stop flags (always read as 0) */ +#define PWR_CPUCR_STOPF_Pos (8UL) +#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000100 */ +#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP flag */ +#define PWR_CPUCR_SBF_Pos (9UL) +#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000200 */ +#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System Standby flag */ +#define PWR_CPUCR_SVOS_Pos (16UL) +#define PWR_CPUCR_SVOS_Msk (0x1UL << PWR_CPUCR_SVOS_Pos) /*!< 0x00010000 */ +#define PWR_CPUCR_SVOS PWR_CPUCR_SVOS_Msk /*!< System Stop mode voltage scaling selection */ + +/****************** Bit definition for PWR_SVMCR1 register ******************/ +#define PWR_SVMCR1_VDDIO4VMEN_Pos (0UL) +#define PWR_SVMCR1_VDDIO4VMEN_Msk (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR1_VDDIO4VMEN PWR_SVMCR1_VDDIO4VMEN_Msk /*!< VDDOI4 Independent I/Os voltage monitor enable */ +#define PWR_SVMCR1_VDDIO4SV_Pos (8UL) +#define PWR_SVMCR1_VDDIO4SV_Msk (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR1_VDDIO4SV PWR_SVMCR1_VDDIO4SV_Msk /*!< VDDIO4 Independent I/Os supply valid */ +#define PWR_SVMCR1_VDDIO4RDY_Pos (16UL) +#define PWR_SVMCR1_VDDIO4RDY_Msk (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR1_VDDIO4RDY PWR_SVMCR1_VDDIO4RDY_Msk /*!< VDDIO4 ready */ +#define PWR_SVMCR1_VDDIO4VRSEL_Pos (24UL) +#define PWR_SVMCR1_VDDIO4VRSEL_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR1_VDDIO4VRSEL PWR_SVMCR1_VDDIO4VRSEL_Msk /*!< VDDIO4 IO voltage range selection */ +#define PWR_SVMCR1_VDDIO4VRSTBY_Pos (25UL) +#define PWR_SVMCR1_VDDIO4VRSTBY_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR1_VDDIO4VRSTBY PWR_SVMCR1_VDDIO4VRSTBY_Msk /*!< VDDIO4 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR2 register ******************/ +#define PWR_SVMCR2_VDDIO5VMEN_Pos (0UL) +#define PWR_SVMCR2_VDDIO5VMEN_Msk (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR2_VDDIO5VMEN PWR_SVMCR2_VDDIO5VMEN_Msk /*!< VDDIO5 Independent voltage monitor enable */ +#define PWR_SVMCR2_VDDIO5SV_Pos (8UL) +#define PWR_SVMCR2_VDDIO5SV_Msk (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR2_VDDIO5SV PWR_SVMCR2_VDDIO5SV_Msk /*!< VDDIO5 Independent supply valid */ +#define PWR_SVMCR2_VDDIO5RDY_Pos (16UL) +#define PWR_SVMCR2_VDDIO5RDY_Msk (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR2_VDDIO5RDY PWR_SVMCR2_VDDIO5RDY_Msk /*!< VDDIO5 ready */ +#define PWR_SVMCR2_VDDIO5VRSEL_Pos (24UL) +#define PWR_SVMCR2_VDDIO5VRSEL_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR2_VDDIO5VRSEL PWR_SVMCR2_VDDIO5VRSEL_Msk /*!< VDDIO5 IO voltage range selection */ +#define PWR_SVMCR2_VDDIO5VRSTBY_Pos (25UL) +#define PWR_SVMCR2_VDDIO5VRSTBY_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR2_VDDIO5VRSTBY PWR_SVMCR2_VDDIO5VRSTBY_Msk /*!< VDDIO5 IO voltage range standby mode */ + +/****************** Bit definition for PWR_SVMCR3 register ******************/ +#define PWR_SVMCR3_VDDIO2VMEN_Pos (0UL) +#define PWR_SVMCR3_VDDIO2VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos) /*!< 0x00000001 */ +#define PWR_SVMCR3_VDDIO2VMEN PWR_SVMCR3_VDDIO2VMEN_Msk /*!< VDDIO2 Independent voltage monitor enable */ +#define PWR_SVMCR3_VDDIO3VMEN_Pos (1UL) +#define PWR_SVMCR3_VDDIO3VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos) /*!< 0x00000002 */ +#define PWR_SVMCR3_VDDIO3VMEN PWR_SVMCR3_VDDIO3VMEN_Msk /*!< VDDIO3 Independent voltage monitor enable */ +#define PWR_SVMCR3_USB33VMEN_Pos (2UL) +#define PWR_SVMCR3_USB33VMEN_Msk (0x1UL << PWR_SVMCR3_USB33VMEN_Pos) /*!< 0x00000004 */ +#define PWR_SVMCR3_USB33VMEN PWR_SVMCR3_USB33VMEN_Msk /*!< VDD33USB Independent USB 33 voltage monitor enable */ +#define PWR_SVMCR3_AVMEN_Pos (4UL) +#define PWR_SVMCR3_AVMEN_Msk (0x1UL << PWR_SVMCR3_AVMEN_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR3_AVMEN PWR_SVMCR3_AVMEN_Msk /*!< VDDA18ADC Independent ADC voltage monitor enable */ +#define PWR_SVMCR3_VDDIO2SV_Pos (8UL) +#define PWR_SVMCR3_VDDIO2SV_Msk (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos) /*!< 0x00000100 */ +#define PWR_SVMCR3_VDDIO2SV PWR_SVMCR3_VDDIO2SV_Msk /*!< VDDIO2 Independent supply valid */ +#define PWR_SVMCR3_VDDIO3SV_Pos (9UL) +#define PWR_SVMCR3_VDDIO3SV_Msk (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos) /*!< 0x00000200 */ +#define PWR_SVMCR3_VDDIO3SV PWR_SVMCR3_VDDIO3SV_Msk /*!< VDDIO3 Independent supply valid */ +#define PWR_SVMCR3_USB33SV_Pos (10UL) +#define PWR_SVMCR3_USB33SV_Msk (0x1UL << PWR_SVMCR3_USB33SV_Pos) /*!< 0x00000400 */ +#define PWR_SVMCR3_USB33SV PWR_SVMCR3_USB33SV_Msk /*!< VDD33USB Independent supply valid */ +#define PWR_SVMCR3_ASV_Pos (12UL) +#define PWR_SVMCR3_ASV_Msk (0x1UL << PWR_SVMCR3_ASV_Pos) /*!< 0x00001000 */ +#define PWR_SVMCR3_ASV PWR_SVMCR3_ASV_Msk /*!< VDDA18ADC Independent supply valid */ +#define PWR_SVMCR3_VDDIO2RDY_Pos (16UL) +#define PWR_SVMCR3_VDDIO2RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos) /*!< 0x00010000 */ +#define PWR_SVMCR3_VDDIO2RDY PWR_SVMCR3_VDDIO2RDY_Msk /*!< VDDIO2 ready */ +#define PWR_SVMCR3_VDDIO3RDY_Pos (17UL) +#define PWR_SVMCR3_VDDIO3RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos) /*!< 0x00020000 */ +#define PWR_SVMCR3_VDDIO3RDY PWR_SVMCR3_VDDIO3RDY_Msk /*!< VDDIO3 ready */ +#define PWR_SVMCR3_USB33RDY_Pos (18UL) +#define PWR_SVMCR3_USB33RDY_Msk (0x1UL << PWR_SVMCR3_USB33RDY_Pos) /*!< 0x00040000 */ +#define PWR_SVMCR3_USB33RDY PWR_SVMCR3_USB33RDY_Msk /*!< VDD33USB ready */ +#define PWR_SVMCR3_ARDY_Pos (20UL) +#define PWR_SVMCR3_ARDY_Msk (0x1UL << PWR_SVMCR3_ARDY_Pos) /*!< 0x00100000 */ +#define PWR_SVMCR3_ARDY PWR_SVMCR3_ARDY_Msk /*!< VDDA18ADC ready */ +#define PWR_SVMCR3_VDDIOVRSEL_Pos (24UL) +#define PWR_SVMCR3_VDDIOVRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos) /*!< 0x01000000 */ +#define PWR_SVMCR3_VDDIOVRSEL PWR_SVMCR3_VDDIOVRSEL_Msk /*!< VDD IO voltage range selection */ +#define PWR_SVMCR3_VDDIO2VRSEL_Pos (25UL) +#define PWR_SVMCR3_VDDIO2VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos) /*!< 0x02000000 */ +#define PWR_SVMCR3_VDDIO2VRSEL PWR_SVMCR3_VDDIO2VRSEL_Msk /*!< VDDIO2 IO voltage range selection */ +#define PWR_SVMCR3_VDDIO3VRSEL_Pos (26UL) +#define PWR_SVMCR3_VDDIO3VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos) /*!< 0x04000000 */ +#define PWR_SVMCR3_VDDIO3VRSEL PWR_SVMCR3_VDDIO3VRSEL_Msk /*!< VDDIO3 IO voltage range selection */ + +/***************** Bit definition for PWR_WKUPCR register *******************/ +#define PWR_WKUPCR_WKUPC1_Pos (0UL) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPCR_WKUPC2_Pos (1UL) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPCR_WKUPC3_Pos (2UL) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPCR_WKUPC4_Pos (3UL) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Flag for WKUP4 pin */ +#define PWR_WKUPCR_WKUPC_Pos (0UL) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Flag 1 to 4 */ + +/***************** Bit definition for PWR_WKUPSR register *******************/ +#define PWR_WKUPSR_WKUPF1_Pos (0UL) +#define PWR_WKUPSR_WKUPF1_Msk (0x1UL << PWR_WKUPSR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPSR_WKUPF1 PWR_WKUPSR_WKUPF1_Msk /*!< Wakeup Flag for WKUP1 pin */ +#define PWR_WKUPSR_WKUPF2_Pos (1UL) +#define PWR_WKUPSR_WKUPF2_Msk (0x1UL << PWR_WKUPSR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPSR_WKUPF2 PWR_WKUPSR_WKUPF2_Msk /*!< Wakeup Flag for WKUP2 pin */ +#define PWR_WKUPSR_WKUPF3_Pos (2UL) +#define PWR_WKUPSR_WKUPF3_Msk (0x1UL << PWR_WKUPSR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPSR_WKUPF3 PWR_WKUPSR_WKUPF3_Msk /*!< Wakeup Flag for WKUP3 pin */ +#define PWR_WKUPSR_WKUPF4_Pos (3UL) +#define PWR_WKUPSR_WKUPF4_Msk (0x1UL << PWR_WKUPSR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPSR_WKUPF4 PWR_WKUPSR_WKUPF4_Msk /*!< Wakeup Flag for WKUP4 pin */ + +/***************** Bit definition for PWR_WKUPEPR register *******************/ +#define PWR_WKUPEPR_WKUPEN1_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1UL) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2UL) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3UL) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup pin WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8UL) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Polarity bit for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPP2_Pos (9UL) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Polarity bit for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPP3_Pos (10UL) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Polarity bit for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPP4_Pos (11UL) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Polarity bit for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPP_Pos (8UL) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000300F */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16UL) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup pull configuration for WKUP1 pin */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18UL) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup pull configuration for WKUP2 pin */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20UL) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup pull configuration for WKUP3 pin */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22UL) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup pull configuration for WKUP4 pin */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ +#define PWR_WKUPEPR_WKUPEN_Pos (0UL) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ + +/***************** Bit definition for PWR_SECCFGR register ******************/ +#define PWR_SECCFGR_SEC0_Pos (0UL) +#define PWR_SECCFGR_SEC0_Msk (0x1UL << PWR_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_SEC0 PWR_SECCFGR_SEC0_Msk /*!< System supply configuration secure protection */ +#define PWR_SECCFGR_SEC1_Pos (1UL) +#define PWR_SECCFGR_SEC1_Msk (0x1UL << PWR_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_SEC1 PWR_SECCFGR_SEC1_Msk /*!< Programmable voltage detector secure protection */ +#define PWR_SECCFGR_SEC2_Pos (2UL) +#define PWR_SECCFGR_SEC2_Msk (0x1UL << PWR_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_SEC2 PWR_SECCFGR_SEC2_Msk /*!< VDDCORE monitor secure protection */ +#define PWR_SECCFGR_SEC3_Pos (3UL) +#define PWR_SECCFGR_SEC3_Msk (0x1UL << PWR_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_SEC3 PWR_SECCFGR_SEC3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */ +#define PWR_SECCFGR_SEC4_Pos (4UL) +#define PWR_SECCFGR_SEC4_Msk (0x1UL << PWR_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_SEC4 PWR_SECCFGR_SEC4_Msk /*!< Voltage scaling selection secure protection */ +#define PWR_SECCFGR_SEC5_Pos (5UL) +#define PWR_SECCFGR_SEC5_Msk (0x1UL << PWR_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_SEC5 PWR_SECCFGR_SEC5_Msk /*!< Backup domain secure protection */ +#define PWR_SECCFGR_SEC6_Pos (6UL) +#define PWR_SECCFGR_SEC6_Msk (0x1UL << PWR_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_SEC6 PWR_SECCFGR_SEC6_Msk /*!< CPU power control secure protection */ +#define PWR_SECCFGR_SEC7_Pos (7UL) +#define PWR_SECCFGR_SEC7_Msk (0x1UL << PWR_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_SEC7 PWR_SECCFGR_SEC7_Msk /*!< Peripheral voltage monitor secure protection */ +#define PWR_SECCFGR_WKUPSEC1_Pos (16UL) +#define PWR_SECCFGR_WKUPSEC1_Msk (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos) /*!< 0x00010000 */ +#define PWR_SECCFGR_WKUPSEC1 PWR_SECCFGR_WKUPSEC1_Msk /*!< WKUP1 secure protection */ +#define PWR_SECCFGR_WKUPSEC2_Pos (17UL) +#define PWR_SECCFGR_WKUPSEC2_Msk (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos) /*!< 0x00020000 */ +#define PWR_SECCFGR_WKUPSEC2 PWR_SECCFGR_WKUPSEC2_Msk /*!< WKUP2 secure protection */ +#define PWR_SECCFGR_WKUPSEC3_Pos (18UL) +#define PWR_SECCFGR_WKUPSEC3_Msk (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos) /*!< 0x00040000 */ +#define PWR_SECCFGR_WKUPSEC3 PWR_SECCFGR_WKUPSEC3_Msk /*!< WKUP3 secure protection */ +#define PWR_SECCFGR_WKUPSEC4_Pos (19UL) +#define PWR_SECCFGR_WKUPSEC4_Msk (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos) /*!< 0x00080000 */ +#define PWR_SECCFGR_WKUPSEC4 PWR_SECCFGR_WKUPSEC4_Msk /*!< WKUP4 secure protection */ + +/***************** Bit definition for PWR_PRIVCFGR register *****************/ +#define PWR_PRIVCFGR_PRIV0_Pos (0UL) +#define PWR_PRIVCFGR_PRIV0_Msk (0x1UL << PWR_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_PRIV0 PWR_PRIVCFGR_PRIV0_Msk /*!< System supply configuration privileged protection */ +#define PWR_PRIVCFGR_PRIV1_Pos (1UL) +#define PWR_PRIVCFGR_PRIV1_Msk (0x1UL << PWR_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_PRIV1 PWR_PRIVCFGR_PRIV1_Msk /*!< Programmable voltage detector privileged protection */ +#define PWR_PRIVCFGR_PRIV2_Pos (2UL) +#define PWR_PRIVCFGR_PRIV2_Msk (0x1UL << PWR_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define PWR_PRIVCFGR_PRIV2 PWR_PRIVCFGR_PRIV2_Msk /*!< VDDCORE monitor privileged protection */ +#define PWR_PRIVCFGR_PRIV3_Pos (3UL) +#define PWR_PRIVCFGR_PRIV3_Msk (0x1UL << PWR_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define PWR_PRIVCFGR_PRIV3 PWR_PRIVCFGR_PRIV3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */ +#define PWR_PRIVCFGR_PRIV4_Pos (4UL) +#define PWR_PRIVCFGR_PRIV4_Msk (0x1UL << PWR_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define PWR_PRIVCFGR_PRIV4 PWR_PRIVCFGR_PRIV4_Msk /*!< Voltage scaling selection privileged protection */ +#define PWR_PRIVCFGR_PRIV5_Pos (5UL) +#define PWR_PRIVCFGR_PRIV5_Msk (0x1UL << PWR_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define PWR_PRIVCFGR_PRIV5 PWR_PRIVCFGR_PRIV5_Msk /*!< Backup domain privileged protection */ +#define PWR_PRIVCFGR_PRIV6_Pos (6UL) +#define PWR_PRIVCFGR_PRIV6_Msk (0x1UL << PWR_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define PWR_PRIVCFGR_PRIV6 PWR_PRIVCFGR_PRIV6_Msk /*!< CPU power control privileged protection */ +#define PWR_PRIVCFGR_PRIV7_Pos (7UL) +#define PWR_PRIVCFGR_PRIV7_Msk (0x1UL << PWR_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define PWR_PRIVCFGR_PRIV7 PWR_PRIVCFGR_PRIV7_Msk /*!< Peripheral voltage monitor privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV1_Pos (16UL) +#define PWR_PRIVCFGR_WKUPPRIV1_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos) /*!< 0x00010000 */ +#define PWR_PRIVCFGR_WKUPPRIV1 PWR_PRIVCFGR_WKUPPRIV1_Msk /*!< WKUP1 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV2_Pos (17UL) +#define PWR_PRIVCFGR_WKUPPRIV2_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos) /*!< 0x00020000 */ +#define PWR_PRIVCFGR_WKUPPRIV2 PWR_PRIVCFGR_WKUPPRIV2_Msk /*!< WKUP2 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV3_Pos (18UL) +#define PWR_PRIVCFGR_WKUPPRIV3_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos) /*!< 0x00040000 */ +#define PWR_PRIVCFGR_WKUPPRIV3 PWR_PRIVCFGR_WKUPPRIV3_Msk /*!< WKUP3 privileged protection */ +#define PWR_PRIVCFGR_WKUPPRIV4_Pos (19UL) +#define PWR_PRIVCFGR_WKUPPRIV4_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos) /*!< 0x00080000 */ +#define PWR_PRIVCFGR_WKUPPRIV4 PWR_PRIVCFGR_WKUPPRIV4_Msk /*!< WKUP4 privileged protection */ + + +/******************************************************************************/ +/* */ +/* RAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_CR register ******************/ +#define RAMCFG_CR_ECCE_Pos (0UL) +#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */ +#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC Enable */ +#define RAMCFG_CR_ALE_Pos (4UL) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8UL) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_SRAMHWERDIS_Pos (12UL) +#define RAMCFG_CR_SRAMHWERDIS_Msk (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos) /*!< 0x00001000 */ +#define RAMCFG_CR_SRAMHWERDIS RAMCFG_CR_SRAMHWERDIS_Msk /*!< SRAM hardware erase disable */ +#define RAMCFG_CR_ITCMCFG_Pos (16UL) +#define RAMCFG_CR_ITCMCFG_Msk (0x3UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00030000 */ +#define RAMCFG_CR_ITCMCFG RAMCFG_CR_ITCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ +#define RAMCFG_CR_ITCMCFG_0 (0x1UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_ITCMCFG_1 (0x2UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_SRAMSD_Pos (20UL) +#define RAMCFG_CR_SRAMSD_Msk (0x1UL << RAMCFG_CR_SRAMSD_Pos) /*!< 0x00100000 */ +#define RAMCFG_CR_SRAMSD RAMCFG_CR_SRAMSD_Msk /*!< Shutdown AXISRAMx */ +#define RAMCFG_CR_DTCMCFG_Pos (24UL) +#define RAMCFG_CR_DTCMCFG_Msk (0x1UL << RAMCFG_CR_DTCMCFG_Pos) /*!< 0x01000000 */ +#define RAMCFG_CR_DTCMCFG RAMCFG_CR_DTCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */ + +/******************* Bit definition for RAMCFG_IER register *****************/ +#define RAMCFG_IER_SEIE_Pos (0UL) +#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< Single Error Interrupt Enable */ +#define RAMCFG_IER_DEIE_Pos (1UL) +#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */ +#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< Double Error Interrupt Enable */ + +/******************* Bit definition for RAMCFG_ISR register *****************/ +#define RAMCFG_ISR_SEDC_Pos (0UL) +#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< Single Error Detected and Corrected flag */ +#define RAMCFG_ISR_DED_Pos (1UL) +#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< Double Error Detected flag */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8UL) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy flag */ + +/******************* Bit definition for RAMCFG_ESEAR register ****************/ +#define RAMCFG_ESEAR_ESEA_Pos (0UL) +#define RAMCFG_ESEAR_ESEA_Msk (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_ESEAR_ESEA RAMCFG_ESEAR_ESEA_Msk /*!< ECC Single Error Address */ + +/******************* Bit definition for RAMCFG_EDEAR register ****************/ +#define RAMCFG_EDEAR_EDEA_Pos (0UL) +#define RAMCFG_EDEAR_EDEA_Msk (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos) /*!< 0x000007FF */ +#define RAMCFG_EDEAR_EDEA RAMCFG_EDEAR_EDEA_Msk /*!< ECC Double Error Address */ + +/******************* Bit definition for RAMCFG_ICR register *****************/ +#define RAMCFG_ICR_CSEDC_Pos (0UL) +#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */ +#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC Single Error Detected and Corrected Flag */ +#define RAMCFG_ICR_CDED_Pos (1UL) +#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC Double Error Detected Flag*/ + +/***************** Bit definition for RAMCFG_ECCKEYR register ***************/ +#define RAMCFG_ECCKEYR_ECCKEY_Pos (0UL) +#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC Write Protection Key */ + +/***************** Bit definition for RAMCFG_ERKEYR register ****************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0UL) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase Write Protection Key */ + + +/******************************************************************************/ +/* */ +/* (RCC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_LSION_Pos (0UL) +#define RCC_CR_LSION_Msk (0x1UL << RCC_CR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_LSION RCC_CR_LSION_Msk /*!< LSI oscillator enable */ +#define RCC_CR_LSEON_Pos (1UL) +#define RCC_CR_LSEON_Msk (0x1UL << RCC_CR_LSEON_Pos) /*!< 0x00000002 */ +#define RCC_CR_LSEON RCC_CR_LSEON_Msk /*!< LSE oscillator enable */ +#define RCC_CR_MSION_Pos (2UL) +#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000004 */ +#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< MSI oscillator enable */ +#define RCC_CR_HSION_Pos (3UL) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< HSI oscillator enable */ +#define RCC_CR_HSEON_Pos (4UL) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< HSE oscillator enable */ +#define RCC_CR_PLL1ON_Pos (8UL) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x00000100 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< PLL1 enable */ +#define RCC_CR_PLL2ON_Pos (9UL) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x00000200 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ +#define RCC_CR_PLL3ON_Pos (10UL) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x00000400 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ +#define RCC_CR_PLL4ON_Pos (11UL) +#define RCC_CR_PLL4ON_Msk (0x1UL << RCC_CR_PLL4ON_Pos) /*!< 0x00000800 */ +#define RCC_CR_PLL4ON RCC_CR_PLL4ON_Msk /*!< PLL4 enable */ + +/******************** Bit definition for RCC_SR register ********************/ +#define RCC_SR_LSIRDY_Pos (0UL) +#define RCC_SR_LSIRDY_Msk (0x1UL << RCC_SR_LSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_SR_LSIRDY RCC_SR_LSIRDY_Msk /*!< LSI clock ready flag */ +#define RCC_SR_LSERDY_Pos (1UL) +#define RCC_SR_LSERDY_Msk (0x1UL << RCC_SR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_SR_LSERDY RCC_SR_LSERDY_Msk /*!< LSE clock ready flag */ +#define RCC_SR_MSIRDY_Pos (2UL) +#define RCC_SR_MSIRDY_Msk (0x1UL << RCC_SR_MSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_SR_MSIRDY RCC_SR_MSIRDY_Msk /*!< MSI clock ready flag */ +#define RCC_SR_HSIRDY_Pos (3UL) +#define RCC_SR_HSIRDY_Msk (0x1UL << RCC_SR_HSIRDY_Pos) /*!< 0x00000008 */ +#define RCC_SR_HSIRDY RCC_SR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_SR_HSERDY_Pos (4UL) +#define RCC_SR_HSERDY_Msk (0x1UL << RCC_SR_HSERDY_Pos) /*!< 0x00000010 */ +#define RCC_SR_HSERDY RCC_SR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_SR_PLL1RDY_Pos (8UL) +#define RCC_SR_PLL1RDY_Msk (0x1UL << RCC_SR_PLL1RDY_Pos) /*!< 0x00000100 */ +#define RCC_SR_PLL1RDY RCC_SR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_SR_PLL2RDY_Pos (9UL) +#define RCC_SR_PLL2RDY_Msk (0x1UL << RCC_SR_PLL2RDY_Pos) /*!< 0x00000200 */ +#define RCC_SR_PLL2RDY RCC_SR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_SR_PLL3RDY_Pos (10UL) +#define RCC_SR_PLL3RDY_Msk (0x1UL << RCC_SR_PLL3RDY_Pos) /*!< 0x00000400 */ +#define RCC_SR_PLL3RDY RCC_SR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_SR_PLL4RDY_Pos (11UL) +#define RCC_SR_PLL4RDY_Msk (0x1UL << RCC_SR_PLL4RDY_Pos) /*!< 0x00000800 */ +#define RCC_SR_PLL4RDY RCC_SR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ + +/****************** Bit definition for RCC_STOPCR register ******************/ +#define RCC_STOPCR_MSISTOPEN_Pos (0UL) +#define RCC_STOPCR_MSISTOPEN_Msk (0x1UL << RCC_STOPCR_MSISTOPEN_Pos) /*!< 0x00000001 */ +#define RCC_STOPCR_MSISTOPEN RCC_STOPCR_MSISTOPEN_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCR_HSISTOPEN_Pos (1UL) +#define RCC_STOPCR_HSISTOPEN_Msk (0x1UL << RCC_STOPCR_HSISTOPEN_Pos) /*!< 0x00000002 */ +#define RCC_STOPCR_HSISTOPEN RCC_STOPCR_HSISTOPEN_Msk /*!< HSI oscillator enable */ + +/****************** Bit definition for RCC_CFGR1 register *******************/ +#define RCC_CFGR1_STOPWUCK_Pos (0UL) +#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a wake up from system stop */ +#define RCC_CFGR1_CPUSW_Pos (16UL) +#define RCC_CFGR1_CPUSW_Msk (0x3UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00030000 */ +#define RCC_CFGR1_CPUSW RCC_CFGR1_CPUSW_Msk /*!< CPU clock switch selection */ +#define RCC_CFGR1_CPUSW_0 (0x1UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00010000 */ +#define RCC_CFGR1_CPUSW_1 (0x2UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00020000 */ +#define RCC_CFGR1_CPUSWS_Pos (20UL) +#define RCC_CFGR1_CPUSWS_Msk (0x3UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00300000 */ +#define RCC_CFGR1_CPUSWS RCC_CFGR1_CPUSWS_Msk /*!< CPU clock switch status */ +#define RCC_CFGR1_CPUSWS_0 (0x1UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00100000 */ +#define RCC_CFGR1_CPUSWS_1 (0x2UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00200000 */ +#define RCC_CFGR1_SYSSW_Pos (24UL) +#define RCC_CFGR1_SYSSW_Msk (0x3UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x03000000 */ +#define RCC_CFGR1_SYSSW RCC_CFGR1_SYSSW_Msk /*!< System clock switch selection */ +#define RCC_CFGR1_SYSSW_0 (0x1UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_SYSSW_1 (0x2UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_SYSSWS_Pos (28UL) +#define RCC_CFGR1_SYSSWS_Msk (0x3UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x30000000 */ +#define RCC_CFGR1_SYSSWS RCC_CFGR1_SYSSWS_Msk /*!< System clock switch status */ +#define RCC_CFGR1_SYSSWS_0 (0x1UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_SYSSWS_1 (0x2UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for RCC_CFGR2 register *******************/ +#define RCC_CFGR2_PPRE1_Pos (0UL) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< CPU domain APB1 prescaler */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE2_Pos (4UL) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< CPU domain APB2 prescaler */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE4_Pos (12UL) +#define RCC_CFGR2_PPRE4_Msk (0x7UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00007000 */ +#define RCC_CFGR2_PPRE4 RCC_CFGR2_PPRE4_Msk /*!< CPU domain APB4 prescaler */ +#define RCC_CFGR2_PPRE4_0 (0x1UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00001000 */ +#define RCC_CFGR2_PPRE4_1 (0x2UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00002000 */ +#define RCC_CFGR2_PPRE4_2 (0x4UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00004000 */ +#define RCC_CFGR2_PPRE5_Pos (16UL) +#define RCC_CFGR2_PPRE5_Msk (0x7UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00070000 */ +#define RCC_CFGR2_PPRE5 RCC_CFGR2_PPRE5_Msk /*!< CPU domain APB5 prescaler */ +#define RCC_CFGR2_PPRE5_0 (0x1UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00010000 */ +#define RCC_CFGR2_PPRE5_1 (0x2UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00020000 */ +#define RCC_CFGR2_PPRE5_2 (0x4UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00040000 */ +#define RCC_CFGR2_HPRE_Pos (20UL) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00700000 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB clock prescaler */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR2_TIMPRE_Pos (24UL) +#define RCC_CFGR2_TIMPRE_Msk (0x3UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x03000000 */ +#define RCC_CFGR2_TIMPRE RCC_CFGR2_TIMPRE_Msk /*!< Timer clock prescaler selection */ +#define RCC_CFGR2_TIMPRE_0 (0x1UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x01000000 */ +#define RCC_CFGR2_TIMPRE_1 (0x2UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x02000000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_VSWRST_Pos (31UL) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< Vswitch (VSW) domain software reset */ + +/****************** Bit definition for RCC_HWRSR register *******************/ +#define RCC_HWRSR_RMVF_Pos (16UL) +#define RCC_HWRSR_RMVF_Msk (0x1UL << RCC_HWRSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_HWRSR_RMVF RCC_HWRSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_HWRSR_LCKRSTF_Pos (17UL) +#define RCC_HWRSR_LCKRSTF_Msk (0x1UL << RCC_HWRSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_HWRSR_LCKRSTF RCC_HWRSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_HWRSR_BORRSTF_Pos (21UL) +#define RCC_HWRSR_BORRSTF_Msk (0x1UL << RCC_HWRSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_HWRSR_BORRSTF RCC_HWRSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_HWRSR_PINRSTF_Pos (22UL) +#define RCC_HWRSR_PINRSTF_Msk (0x1UL << RCC_HWRSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_HWRSR_PINRSTF RCC_HWRSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_HWRSR_PORRSTF_Pos (23UL) +#define RCC_HWRSR_PORRSTF_Msk (0x1UL << RCC_HWRSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_HWRSR_PORRSTF RCC_HWRSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_HWRSR_SFTRSTF_Pos (24UL) +#define RCC_HWRSR_SFTRSTF_Msk (0x1UL << RCC_HWRSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_HWRSR_SFTRSTF RCC_HWRSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_HWRSR_IWDGRSTF_Pos (26UL) +#define RCC_HWRSR_IWDGRSTF_Msk (0x1UL << RCC_HWRSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_HWRSR_IWDGRSTF RCC_HWRSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_HWRSR_WWDGRSTF_Pos (28UL) +#define RCC_HWRSR_WWDGRSTF_Msk (0x1UL << RCC_HWRSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_HWRSR_WWDGRSTF RCC_HWRSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_HWRSR_LPWRRSTF_Pos (30UL) +#define RCC_HWRSR_LPWRRSTF_Msk (0x1UL << RCC_HWRSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_HWRSR_LPWRRSTF RCC_HWRSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/******************* Bit definition for RCC_RSR register ********************/ +#define RCC_RSR_RMVF_Pos (16UL) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_RSR_LCKRSTF_Pos (17UL) +#define RCC_RSR_LCKRSTF_Msk (0x1UL << RCC_RSR_LCKRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_LCKRSTF RCC_RSR_LCKRSTF_Msk /*!< CPU lockup reset flag */ +#define RCC_RSR_BORRSTF_Pos (21UL) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_RSR_PINRSTF_Pos (22UL) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */ +#define RCC_RSR_PORRSTF_Pos (23UL) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF_Pos (24UL) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< Software system reset flag */ +#define RCC_RSR_IWDGRSTF_Pos (26UL) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */ +#define RCC_RSR_WWDGRSTF_Pos (28UL) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF_Pos (30UL) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */ + +/***************** Bit definition for RCC_LSECFGR register ******************/ +#define RCC_LSECFGR_LSECSSON_Pos (7UL) +#define RCC_LSECFGR_LSECSSON_Msk (0x1UL << RCC_LSECFGR_LSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_LSECFGR_LSECSSON RCC_LSECFGR_LSECSSON_Msk /*!< LSE clock security system (CSS) enable */ +#define RCC_LSECFGR_LSECSSRA_Pos (8UL) +#define RCC_LSECFGR_LSECSSRA_Msk (0x1UL << RCC_LSECFGR_LSECSSRA_Pos) /*!< 0x00000100 */ +#define RCC_LSECFGR_LSECSSRA RCC_LSECFGR_LSECSSRA_Msk /*!< LSE clock security system (CSS) rearm function */ +#define RCC_LSECFGR_LSECSSD_Pos (9UL) +#define RCC_LSECFGR_LSECSSD_Msk (0x1UL << RCC_LSECFGR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_LSECFGR_LSECSSD RCC_LSECFGR_LSECSSD_Msk /*!< LSE clock security system (CSS) failure detection */ +#define RCC_LSECFGR_LSEBYP_Pos (15UL) +#define RCC_LSECFGR_LSEBYP_Msk (0x1UL << RCC_LSECFGR_LSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_LSECFGR_LSEBYP RCC_LSECFGR_LSEBYP_Msk /*!< LSE clock bypass */ +#define RCC_LSECFGR_LSEEXT_Pos (16UL) +#define RCC_LSECFGR_LSEEXT_Msk (0x1UL << RCC_LSECFGR_LSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_LSECFGR_LSEEXT RCC_LSECFGR_LSEEXT_Msk /*!< LSE clock type in bypass mode */ +#define RCC_LSECFGR_LSEGFON_Pos (17UL) +#define RCC_LSECFGR_LSEGFON_Msk (0x1UL << RCC_LSECFGR_LSEGFON_Pos) /*!< 0x00020000 */ +#define RCC_LSECFGR_LSEGFON RCC_LSECFGR_LSEGFON_Msk /*!< LSE clock glitch filter enable */ +#define RCC_LSECFGR_LSEDRV_Pos (18UL) +#define RCC_LSECFGR_LSEDRV_Msk (0x3UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x000C0000 */ +#define RCC_LSECFGR_LSEDRV RCC_LSECFGR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_LSECFGR_LSEDRV_0 (0x1UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00040000 */ +#define RCC_LSECFGR_LSEDRV_1 (0x2UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for RCC_MSICFGR register ******************/ +#define RCC_MSICFGR_MSIFREQSEL_Pos (9UL) +#define RCC_MSICFGR_MSIFREQSEL_Msk (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */ +#define RCC_MSICFGR_MSIFREQSEL RCC_MSICFGR_MSIFREQSEL_Msk /*!< MSI oscillator frequency selection */ +#define RCC_MSICFGR_MSITRIM_Pos (16UL) +#define RCC_MSICFGR_MSITRIM_Msk (0x1FUL << RCC_MSICFGR_MSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_MSICFGR_MSITRIM RCC_MSICFGR_MSITRIM_Msk /*!< MSI clock trimming */ +#define RCC_MSICFGR_MSICAL_Pos (23UL) +#define RCC_MSICFGR_MSICAL_Msk (0xFFUL << RCC_MSICFGR_MSICAL_Pos) /*!< 0x7F800000 */ +#define RCC_MSICFGR_MSICAL RCC_MSICFGR_MSICAL_Msk /*!< MSI clock calibration */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (7UL) +#define RCC_HSICFGR_HSIDIV_Msk (0x3UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000180 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_Pos (16UL) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x007F0000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSICAL_Pos (23UL) +#define RCC_HSICFGR_HSICAL_Msk (0x1FFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0xFF800000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ + +/****************** Bit definition for RCC_HSIMCR register ******************/ +#define RCC_HSIMCR_HSIREF_Pos (0UL) +#define RCC_HSIMCR_HSIREF_Msk (0x7FFUL << RCC_HSIMCR_HSIREF_Pos) /*!< 0x000007FF */ +#define RCC_HSIMCR_HSIREF RCC_HSIMCR_HSIREF_Msk /*!< HSI clock-cycle counter reference value */ +#define RCC_HSIMCR_HSIDEV_Pos (16UL) +#define RCC_HSIMCR_HSIDEV_Msk (0x3FUL << RCC_HSIMCR_HSIDEV_Pos) /*!< 0x003F0000 */ +#define RCC_HSIMCR_HSIDEV RCC_HSIMCR_HSIDEV_Msk /*!< HSI clock count deviation value */ +#define RCC_HSIMCR_HSIMONEN_Pos (31UL) +#define RCC_HSIMCR_HSIMONEN_Msk (0x1UL << RCC_HSIMCR_HSIMONEN_Pos) /*!< 0x80000000 */ +#define RCC_HSIMCR_HSIMONEN RCC_HSIMCR_HSIMONEN_Msk /*!< HSI clock period monitor enable */ + +/****************** Bit definition for RCC_HSIMSR register ******************/ +#define RCC_HSIMSR_HSIVAL_Pos (0UL) +#define RCC_HSIMSR_HSIVAL_Msk (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos) /*!< 0x000007FF */ +#define RCC_HSIMSR_HSIVAL RCC_HSIMSR_HSIVAL_Msk /*!< HSI clock-cycle counter measured value */ + +/***************** Bit definition for RCC_HSECFGR register ******************/ +#define RCC_HSECFGR_HSEDIV2SEL_Pos (6UL) +#define RCC_HSECFGR_HSEDIV2SEL_Msk (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */ +#define RCC_HSECFGR_HSEDIV2SEL RCC_HSECFGR_HSEDIV2SEL_Msk /*!< HSE div2 clock source select */ +#define RCC_HSECFGR_HSECSSON_Pos (7UL) +#define RCC_HSECFGR_HSECSSON_Msk (0x1UL << RCC_HSECFGR_HSECSSON_Pos) /*!< 0x00000080 */ +#define RCC_HSECFGR_HSECSSON RCC_HSECFGR_HSECSSON_Msk /*!< HSE CSS enable */ +#define RCC_HSECFGR_HSECSSD_Pos (9UL) +#define RCC_HSECFGR_HSECSSD_Msk (0x1UL << RCC_HSECFGR_HSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_HSECFGR_HSECSSD RCC_HSECFGR_HSECSSD_Msk /*!< HSE CSS failure detection */ +#define RCC_HSECFGR_HSECSSBYP_Pos (10UL) +#define RCC_HSECFGR_HSECSSBYP_Msk (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos) /*!< 0x00000400 */ +#define RCC_HSECFGR_HSECSSBYP RCC_HSECFGR_HSECSSBYP_Msk /*!< HSE CSS bypass enable */ +#define RCC_HSECFGR_HSECSSBPRE_Pos (11UL) +#define RCC_HSECFGR_HSECSSBPRE_Msk (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */ +#define RCC_HSECFGR_HSECSSBPRE RCC_HSECFGR_HSECSSBPRE_Msk /*!< HSE CSS bypass divider */ +#define RCC_HSECFGR_HSECSSBPRE_0 (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */ +#define RCC_HSECFGR_HSECSSBPRE_1 (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */ +#define RCC_HSECFGR_HSECSSBPRE_2 (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */ +#define RCC_HSECFGR_HSECSSBPRE_3 (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */ +#define RCC_HSECFGR_HSEBYP_Pos (15UL) +#define RCC_HSECFGR_HSEBYP_Msk (0x1UL << RCC_HSECFGR_HSEBYP_Pos) /*!< 0x00008000 */ +#define RCC_HSECFGR_HSEBYP RCC_HSECFGR_HSEBYP_Msk /*!< HSE clock bypass */ +#define RCC_HSECFGR_HSEEXT_Pos (16UL) +#define RCC_HSECFGR_HSEEXT_Msk (0x1UL << RCC_HSECFGR_HSEEXT_Pos) /*!< 0x00010000 */ +#define RCC_HSECFGR_HSEEXT RCC_HSECFGR_HSEEXT_Msk /*!< HSE clock type in bypass mode */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_PLL1DIVN_Pos (8UL) +#define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 integer part for the VCO multiplication factor */ +#define RCC_PLL1CFGR1_PLL1DIVM_Pos (20UL) +#define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 reference input clock divide frequency ratio */ +#define RCC_PLL1CFGR1_PLL1BYP_Pos (27UL) +#define RCC_PLL1CFGR1_PLL1BYP_Msk (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CFGR1_PLL1BYP RCC_PLL1CFGR1_PLL1BYP_Msk /*!< PLL1 bypass */ +#define RCC_PLL1CFGR1_PLL1SEL_Pos (28UL) +#define RCC_PLL1CFGR1_PLL1SEL_Msk (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL1CFGR1_PLL1SEL RCC_PLL1CFGR1_PLL1SEL_Msk /*!< PLL1 source selection of the reference clock */ +#define RCC_PLL1CFGR1_PLL1SEL_0 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_1 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CFGR1_PLL1SEL_2 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos (0UL) +#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL1CFGR2_PLL1DIVNFRAC RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk /*!< PLL1 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL1CFGR3 register *****************/ +#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos (0UL) +#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR3_PLL1MODSSRST RCC_PLL1CFGR3_PLL1MODSSRST_Msk /*!< PLL1 modulation spread spectrum reset */ +#define RCC_PLL1CFGR3_PLL1DACEN_Pos (1UL) +#define RCC_PLL1CFGR3_PLL1DACEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL1CFGR3_PLL1DACEN RCC_PLL1CFGR3_PLL1DACEN_Msk /*!< PLL1 noise canceling DAC enable in fractional mode */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos (2UL) +#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR3_PLL1MODSSDIS RCC_PLL1CFGR3_PLL1MODSSDIS_Msk /*!< PLL1 modulation spread spectrum disable */ +#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos (3UL) +#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR3_PLL1MODDSEN RCC_PLL1CFGR3_PLL1MODDSEN_Msk /*!< PLL1 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos (4UL) +#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR3_PLL1MODSPRDW RCC_PLL1CFGR3_PLL1MODSPRDW_Msk /*!< PLL1 modulation spread spectrum down */ +#define RCC_PLL1CFGR3_PLL1MODDIV_Pos (8UL) +#define RCC_PLL1CFGR3_PLL1MODDIV_Msk (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL1CFGR3_PLL1MODDIV RCC_PLL1CFGR3_PLL1MODDIV_Msk /*!< PLL1 modulation division frequency adjustment */ +#define RCC_PLL1CFGR3_PLL1MODSPR_Pos (16UL) +#define RCC_PLL1CFGR3_PLL1MODSPR_Msk (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL1CFGR3_PLL1MODSPR RCC_PLL1CFGR3_PLL1MODSPR_Msk /*!< PLL1 modulation spread depth adjustment */ +#define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24UL) +#define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO frequency divider level 2 */ +#define RCC_PLL1CFGR3_PLL1PDIV1_Pos (27UL) +#define RCC_PLL1CFGR3_PLL1PDIV1_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL1CFGR3_PLL1PDIV1 RCC_PLL1CFGR3_PLL1PDIV1_Msk /*!< PLL1 VCO frequency divider level 1 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos (30UL) +#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_PLL2DIVN_Pos (8UL) +#define RCC_PLL2CFGR1_PLL2DIVN_Msk (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL2CFGR1_PLL2DIVN RCC_PLL2CFGR1_PLL2DIVN_Msk /*!< PLL2 integer part for the VCO multiplication factor */ +#define RCC_PLL2CFGR1_PLL2DIVM_Pos (20UL) +#define RCC_PLL2CFGR1_PLL2DIVM_Msk (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL2CFGR1_PLL2DIVM RCC_PLL2CFGR1_PLL2DIVM_Msk /*!< PLL2 reference input clock divide frequency ratio */ +#define RCC_PLL2CFGR1_PLL2BYP_Pos (27UL) +#define RCC_PLL2CFGR1_PLL2BYP_Msk (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CFGR1_PLL2BYP RCC_PLL2CFGR1_PLL2BYP_Msk /*!< PLL2 bypass */ +#define RCC_PLL2CFGR1_PLL2SEL_Pos (28UL) +#define RCC_PLL2CFGR1_PLL2SEL_Msk (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL2CFGR1_PLL2SEL RCC_PLL2CFGR1_PLL2SEL_Msk /*!< PLL2 source selection of the reference clock */ +#define RCC_PLL2CFGR1_PLL2SEL_0 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_1 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CFGR1_PLL2SEL_2 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos (0UL) +#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL2CFGR2_PLL2DIVNFRAC RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk /*!< PLL2 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL2CFGR3 register *****************/ +#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos (0UL) +#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR3_PLL2MODSSRST RCC_PLL2CFGR3_PLL2MODSSRST_Msk /*!< PLL2 modulation spread spectrum reset */ +#define RCC_PLL2CFGR3_PLL2DACEN_Pos (1UL) +#define RCC_PLL2CFGR3_PLL2DACEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL2CFGR3_PLL2DACEN RCC_PLL2CFGR3_PLL2DACEN_Msk /*!< PLL2 noise canceling DAC enable in fractional mode */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos (2UL) +#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR3_PLL2MODSSDIS RCC_PLL2CFGR3_PLL2MODSSDIS_Msk /*!< PLL2 modulation spread spectrum disable */ +#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos (3UL) +#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR3_PLL2MODDSEN RCC_PLL2CFGR3_PLL2MODDSEN_Msk /*!< PLL2 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos (4UL) +#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR3_PLL2MODSPRDW RCC_PLL2CFGR3_PLL2MODSPRDW_Msk /*!< PLL2 modulation down spread */ +#define RCC_PLL2CFGR3_PLL2MODDIV_Pos (8UL) +#define RCC_PLL2CFGR3_PLL2MODDIV_Msk (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL2CFGR3_PLL2MODDIV RCC_PLL2CFGR3_PLL2MODDIV_Msk /*!< PLL2 modulation division frequency adjustment */ +#define RCC_PLL2CFGR3_PLL2MODSPR_Pos (16UL) +#define RCC_PLL2CFGR3_PLL2MODSPR_Msk (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL2CFGR3_PLL2MODSPR RCC_PLL2CFGR3_PLL2MODSPR_Msk /*!< PLL2 modulation spread depth adjustment */ +#define RCC_PLL2CFGR3_PLL2PDIV2_Pos (24UL) +#define RCC_PLL2CFGR3_PLL2PDIV2_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV2 RCC_PLL2CFGR3_PLL2PDIV2_Msk /*!< PLL2 VCO frequency divider level 2 */ +#define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27UL) +#define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL2CFGR3_PLL2PDIV1 RCC_PLL2CFGR3_PLL2PDIV1_Msk /*!< PLL2 VCO frequency divider level 1 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos (30UL) +#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL2CFGR3_PLL2PDIVEN RCC_PLL2CFGR3_PLL2PDIVEN_Msk /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_PLL3DIVN_Pos (8UL) +#define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL3CFGR1_PLL3DIVN RCC_PLL3CFGR1_PLL3DIVN_Msk /*!< PLL3 Integer part for the VCO multiplication factor */ +#define RCC_PLL3CFGR1_PLL3DIVM_Pos (20UL) +#define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL3CFGR1_PLL3DIVM RCC_PLL3CFGR1_PLL3DIVM_Msk /*!< PLL3 reference input clock divide frequency ratio */ +#define RCC_PLL3CFGR1_PLL3BYP_Pos (27UL) +#define RCC_PLL3CFGR1_PLL3BYP_Msk (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3CFGR1_PLL3BYP RCC_PLL3CFGR1_PLL3BYP_Msk /*!< PLL3 bypass */ +#define RCC_PLL3CFGR1_PLL3SEL_Pos (28UL) +#define RCC_PLL3CFGR1_PLL3SEL_Msk (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL3CFGR1_PLL3SEL RCC_PLL3CFGR1_PLL3SEL_Msk /*!< PLL3 source selection of the reference clock */ +#define RCC_PLL3CFGR1_PLL3SEL_0 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_1 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL3CFGR1_PLL3SEL_2 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos (0UL) +#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL3CFGR2_PLL3DIVNFRAC RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk /*!< PLL3 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL3CFGR3 register *****************/ +#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos (0UL) +#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR3_PLL3MODSSRST RCC_PLL3CFGR3_PLL3MODSSRST_Msk /*!< PLL3 modulation spread spectrum reset */ +#define RCC_PLL3CFGR3_PLL3DACEN_Pos (1UL) +#define RCC_PLL3CFGR3_PLL3DACEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL3CFGR3_PLL3DACEN RCC_PLL3CFGR3_PLL3DACEN_Msk /*!< PLL3 noise canceling DAC enable in fractional mode */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos (2UL) +#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR3_PLL3MODSSDIS RCC_PLL3CFGR3_PLL3MODSSDIS_Msk /*!< PLL3 modulation spread spectrum disable */ +#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos (3UL) +#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR3_PLL3MODDSEN RCC_PLL3CFGR3_PLL3MODDSEN_Msk /*!< PLL3 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos (4UL) +#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR3_PLL3MODSPRDW RCC_PLL3CFGR3_PLL3MODSPRDW_Msk /*!< PLL3 modulation down spread */ +#define RCC_PLL3CFGR3_PLL3MODDIV_Pos (8UL) +#define RCC_PLL3CFGR3_PLL3MODDIV_Msk (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL3CFGR3_PLL3MODDIV RCC_PLL3CFGR3_PLL3MODDIV_Msk /*!< PLL3 modulation division frequency adjustment */ +#define RCC_PLL3CFGR3_PLL3MODSPR_Pos (16UL) +#define RCC_PLL3CFGR3_PLL3MODSPR_Msk (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL3CFGR3_PLL3MODSPR RCC_PLL3CFGR3_PLL3MODSPR_Msk /*!< PLL3 modulation spread depth adjustment */ +#define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24UL) +#define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV2 RCC_PLL3CFGR3_PLL3PDIV2_Msk /*!< PLL3 VCO frequency divider level 2 */ +#define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27UL) +#define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL3CFGR3_PLL3PDIV1 RCC_PLL3CFGR3_PLL3PDIV1_Msk /*!< PLL3 VCO frequency divider level 1 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos (30UL) +#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL3CFGR3_PLL3PDIVEN RCC_PLL3CFGR3_PLL3PDIVEN_Msk /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_PLL4DIVN_Pos (8UL) +#define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */ +#define RCC_PLL4CFGR1_PLL4DIVN RCC_PLL4CFGR1_PLL4DIVN_Msk /*!< PLL4 integer part for the VCO multiplication factor */ +#define RCC_PLL4CFGR1_PLL4DIVM_Pos (20UL) +#define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */ +#define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 reference input clock divide frequency ratio */ +#define RCC_PLL4CFGR1_PLL4BYP_Pos (27UL) +#define RCC_PLL4CFGR1_PLL4BYP_Msk (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos) /*!< 0x08000000 */ +#define RCC_PLL4CFGR1_PLL4BYP RCC_PLL4CFGR1_PLL4BYP_Msk /*!< PLL4 bypass */ +#define RCC_PLL4CFGR1_PLL4SEL_Pos (28UL) +#define RCC_PLL4CFGR1_PLL4SEL_Msk (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x70000000 */ +#define RCC_PLL4CFGR1_PLL4SEL RCC_PLL4CFGR1_PLL4SEL_Msk /*!< PLL4 source selection of the reference clock */ +#define RCC_PLL4CFGR1_PLL4SEL_0 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_1 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */ +#define RCC_PLL4CFGR1_PLL4SEL_2 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos (0UL) +#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos) /*!< 0x00FFFFFF */ +#define RCC_PLL4CFGR2_PLL4DIVNFRAC RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk /*!< PLL4 fractional part of the VCO multiplication factor */ + +/**************** Bit definition for RCC_PLL4CFGR3 register *****************/ +#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos (0UL) +#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR3_PLL4MODSSRST RCC_PLL4CFGR3_PLL4MODSSRST_Msk /*!< PLL4 modulation spread spectrum reset */ +#define RCC_PLL4CFGR3_PLL4DACEN_Pos (1UL) +#define RCC_PLL4CFGR3_PLL4DACEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */ +#define RCC_PLL4CFGR3_PLL4DACEN RCC_PLL4CFGR3_PLL4DACEN_Msk /*!< PLL4 noise canceling DAC enable in fractional mode */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos (2UL) +#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR3_PLL4MODSSDIS RCC_PLL4CFGR3_PLL4MODSSDIS_Msk /*!< PLL4 modulation spread spectrum disable */ +#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos (3UL) +#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR3_PLL4MODDSEN RCC_PLL4CFGR3_PLL4MODDSEN_Msk /*!< PLL4 modulation spread spectrum (and fractional divide) enable */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos (4UL) +#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR3_PLL4MODSPRDW RCC_PLL4CFGR3_PLL4MODSPRDW_Msk /*!< PLL4 modulation down spread */ +#define RCC_PLL4CFGR3_PLL4MODDIV_Pos (8UL) +#define RCC_PLL4CFGR3_PLL4MODDIV_Msk (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */ +#define RCC_PLL4CFGR3_PLL4MODDIV RCC_PLL4CFGR3_PLL4MODDIV_Msk /*!< PLL4 modulation division frequency adjustment */ +#define RCC_PLL4CFGR3_PLL4MODSPR_Pos (16UL) +#define RCC_PLL4CFGR3_PLL4MODSPR_Msk (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos) /*!< 0x001F0000 */ +#define RCC_PLL4CFGR3_PLL4MODSPR RCC_PLL4CFGR3_PLL4MODSPR_Msk /*!< PLL4 modulation spread depth adjustment */ +#define RCC_PLL4CFGR3_PLL4PDIV2_Pos (24UL) +#define RCC_PLL4CFGR3_PLL4PDIV2_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO frequency divider level 2 */ +#define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27UL) +#define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */ +#define RCC_PLL4CFGR3_PLL4PDIV1 RCC_PLL4CFGR3_PLL4PDIV1_Msk /*!< PLL4 VCO frequency divider level 1 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos (30UL) +#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */ +#define RCC_PLL4CFGR3_PLL4PDIVEN RCC_PLL4CFGR3_PLL4PDIVEN_Msk /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */ + +/***************** Bit definition for RCC_IC1CFGR register ******************/ +#define RCC_IC1CFGR_IC1INT_Pos (16UL) +#define RCC_IC1CFGR_IC1INT_Msk (0xFFUL << RCC_IC1CFGR_IC1INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC1CFGR_IC1INT RCC_IC1CFGR_IC1INT_Msk /*!< Divider IC1 integer division factor */ +#define RCC_IC1CFGR_IC1SEL_Pos (28UL) +#define RCC_IC1CFGR_IC1SEL_Msk (0x3UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC1CFGR_IC1SEL RCC_IC1CFGR_IC1SEL_Msk /*!< Divider IC1 source selection */ +#define RCC_IC1CFGR_IC1SEL_0 (0x1UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC1CFGR_IC1SEL_1 (0x2UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC2CFGR register ******************/ +#define RCC_IC2CFGR_IC2INT_Pos (16UL) +#define RCC_IC2CFGR_IC2INT_Msk (0xFFUL << RCC_IC2CFGR_IC2INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC2CFGR_IC2INT RCC_IC2CFGR_IC2INT_Msk /*!< Divider IC2 integer division factor */ +#define RCC_IC2CFGR_IC2SEL_Pos (28UL) +#define RCC_IC2CFGR_IC2SEL_Msk (0x3UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC2CFGR_IC2SEL RCC_IC2CFGR_IC2SEL_Msk /*!< Divider IC2 source selection */ +#define RCC_IC2CFGR_IC2SEL_0 (0x1UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC2CFGR_IC2SEL_1 (0x2UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC3CFGR register ******************/ +#define RCC_IC3CFGR_IC3INT_Pos (16UL) +#define RCC_IC3CFGR_IC3INT_Msk (0xFFUL << RCC_IC3CFGR_IC3INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC3CFGR_IC3INT RCC_IC3CFGR_IC3INT_Msk /*!< Divider IC3 integer division factor */ +#define RCC_IC3CFGR_IC3SEL_Pos (28UL) +#define RCC_IC3CFGR_IC3SEL_Msk (0x3UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC3CFGR_IC3SEL RCC_IC3CFGR_IC3SEL_Msk /*!< Divider IC3 source selection */ +#define RCC_IC3CFGR_IC3SEL_0 (0x1UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC3CFGR_IC3SEL_1 (0x2UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC4CFGR register ******************/ +#define RCC_IC4CFGR_IC4INT_Pos (16UL) +#define RCC_IC4CFGR_IC4INT_Msk (0xFFUL << RCC_IC4CFGR_IC4INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC4CFGR_IC4INT RCC_IC4CFGR_IC4INT_Msk /*!< Divider IC4 integer division factor */ +#define RCC_IC4CFGR_IC4SEL_Pos (28UL) +#define RCC_IC4CFGR_IC4SEL_Msk (0x3UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC4CFGR_IC4SEL RCC_IC4CFGR_IC4SEL_Msk /*!< Divider IC4 source selection */ +#define RCC_IC4CFGR_IC4SEL_0 (0x1UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC4CFGR_IC4SEL_1 (0x2UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC5CFGR register ******************/ +#define RCC_IC5CFGR_IC5INT_Pos (16UL) +#define RCC_IC5CFGR_IC5INT_Msk (0xFFUL << RCC_IC5CFGR_IC5INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC5CFGR_IC5INT RCC_IC5CFGR_IC5INT_Msk /*!< Divider IC5 integer division factor */ +#define RCC_IC5CFGR_IC5SEL_Pos (28UL) +#define RCC_IC5CFGR_IC5SEL_Msk (0x3UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC5CFGR_IC5SEL RCC_IC5CFGR_IC5SEL_Msk /*!< Divider IC5 source selection */ +#define RCC_IC5CFGR_IC5SEL_0 (0x1UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC5CFGR_IC5SEL_1 (0x2UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC6CFGR register ******************/ +#define RCC_IC6CFGR_IC6INT_Pos (16UL) +#define RCC_IC6CFGR_IC6INT_Msk (0xFFUL << RCC_IC6CFGR_IC6INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC6CFGR_IC6INT RCC_IC6CFGR_IC6INT_Msk /*!< Divider IC6 integer division factor */ +#define RCC_IC6CFGR_IC6SEL_Pos (28UL) +#define RCC_IC6CFGR_IC6SEL_Msk (0x3UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC6CFGR_IC6SEL RCC_IC6CFGR_IC6SEL_Msk /*!< Divider IC6 source selection */ +#define RCC_IC6CFGR_IC6SEL_0 (0x1UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC6CFGR_IC6SEL_1 (0x2UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC7CFGR register ******************/ +#define RCC_IC7CFGR_IC7INT_Pos (16UL) +#define RCC_IC7CFGR_IC7INT_Msk (0xFFUL << RCC_IC7CFGR_IC7INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC7CFGR_IC7INT RCC_IC7CFGR_IC7INT_Msk /*!< Divider IC7 integer division factor */ +#define RCC_IC7CFGR_IC7SEL_Pos (28UL) +#define RCC_IC7CFGR_IC7SEL_Msk (0x3UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC7CFGR_IC7SEL RCC_IC7CFGR_IC7SEL_Msk /*!< Divider IC7 source selection */ +#define RCC_IC7CFGR_IC7SEL_0 (0x1UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC7CFGR_IC7SEL_1 (0x2UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC8CFGR register ******************/ +#define RCC_IC8CFGR_IC8INT_Pos (16UL) +#define RCC_IC8CFGR_IC8INT_Msk (0xFFUL << RCC_IC8CFGR_IC8INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC8CFGR_IC8INT RCC_IC8CFGR_IC8INT_Msk /*!< Divider IC8 integer division factor */ +#define RCC_IC8CFGR_IC8SEL_Pos (28UL) +#define RCC_IC8CFGR_IC8SEL_Msk (0x3UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC8CFGR_IC8SEL RCC_IC8CFGR_IC8SEL_Msk /*!< Divider IC8 source selection */ +#define RCC_IC8CFGR_IC8SEL_0 (0x1UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC8CFGR_IC8SEL_1 (0x2UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC9CFGR register ******************/ +#define RCC_IC9CFGR_IC9INT_Pos (16UL) +#define RCC_IC9CFGR_IC9INT_Msk (0xFFUL << RCC_IC9CFGR_IC9INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC9CFGR_IC9INT RCC_IC9CFGR_IC9INT_Msk /*!< Divider IC9 integer division factor */ +#define RCC_IC9CFGR_IC9SEL_Pos (28UL) +#define RCC_IC9CFGR_IC9SEL_Msk (0x3UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC9CFGR_IC9SEL RCC_IC9CFGR_IC9SEL_Msk /*!< Divider IC9 source selection */ +#define RCC_IC9CFGR_IC9SEL_0 (0x1UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC9CFGR_IC9SEL_1 (0x2UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC10CFGR register *****************/ +#define RCC_IC10CFGR_IC10INT_Pos (16UL) +#define RCC_IC10CFGR_IC10INT_Msk (0xFFUL << RCC_IC10CFGR_IC10INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC10CFGR_IC10INT RCC_IC10CFGR_IC10INT_Msk /*!< Divider IC10 integer division factor */ +#define RCC_IC10CFGR_IC10SEL_Pos (28UL) +#define RCC_IC10CFGR_IC10SEL_Msk (0x3UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC10CFGR_IC10SEL RCC_IC10CFGR_IC10SEL_Msk /*!< Divider IC10 source selection */ +#define RCC_IC10CFGR_IC10SEL_0 (0x1UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC10CFGR_IC10SEL_1 (0x2UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC11CFGR register *****************/ +#define RCC_IC11CFGR_IC11INT_Pos (16UL) +#define RCC_IC11CFGR_IC11INT_Msk (0xFFUL << RCC_IC11CFGR_IC11INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC11CFGR_IC11INT RCC_IC11CFGR_IC11INT_Msk /*!< Divider IC11 integer division factor */ +#define RCC_IC11CFGR_IC11SEL_Pos (28UL) +#define RCC_IC11CFGR_IC11SEL_Msk (0x3UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC11CFGR_IC11SEL RCC_IC11CFGR_IC11SEL_Msk /*!< Divider IC11 source selection */ +#define RCC_IC11CFGR_IC11SEL_0 (0x1UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC11CFGR_IC11SEL_1 (0x2UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC12CFGR register *****************/ +#define RCC_IC12CFGR_IC12INT_Pos (16UL) +#define RCC_IC12CFGR_IC12INT_Msk (0xFFUL << RCC_IC12CFGR_IC12INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC12CFGR_IC12INT RCC_IC12CFGR_IC12INT_Msk /*!< Divider IC12 integer division factor */ +#define RCC_IC12CFGR_IC12SEL_Pos (28UL) +#define RCC_IC12CFGR_IC12SEL_Msk (0x3UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC12CFGR_IC12SEL RCC_IC12CFGR_IC12SEL_Msk /*!< Divider IC12 source selection */ +#define RCC_IC12CFGR_IC12SEL_0 (0x1UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC12CFGR_IC12SEL_1 (0x2UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC13CFGR register *****************/ +#define RCC_IC13CFGR_IC13INT_Pos (16UL) +#define RCC_IC13CFGR_IC13INT_Msk (0xFFUL << RCC_IC13CFGR_IC13INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC13CFGR_IC13INT RCC_IC13CFGR_IC13INT_Msk /*!< Divider IC13 integer division factor */ +#define RCC_IC13CFGR_IC13SEL_Pos (28UL) +#define RCC_IC13CFGR_IC13SEL_Msk (0x3UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC13CFGR_IC13SEL RCC_IC13CFGR_IC13SEL_Msk /*!< Divider IC13 source selection */ +#define RCC_IC13CFGR_IC13SEL_0 (0x1UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC13CFGR_IC13SEL_1 (0x2UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC14CFGR register *****************/ +#define RCC_IC14CFGR_IC14INT_Pos (16UL) +#define RCC_IC14CFGR_IC14INT_Msk (0xFFUL << RCC_IC14CFGR_IC14INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC14CFGR_IC14INT RCC_IC14CFGR_IC14INT_Msk /*!< Divider IC14 integer division factor */ +#define RCC_IC14CFGR_IC14SEL_Pos (28UL) +#define RCC_IC14CFGR_IC14SEL_Msk (0x3UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC14CFGR_IC14SEL RCC_IC14CFGR_IC14SEL_Msk /*!< Divider IC14 source selection */ +#define RCC_IC14CFGR_IC14SEL_0 (0x1UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC14CFGR_IC14SEL_1 (0x2UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC15CFGR register *****************/ +#define RCC_IC15CFGR_IC15INT_Pos (16UL) +#define RCC_IC15CFGR_IC15INT_Msk (0xFFUL << RCC_IC15CFGR_IC15INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC15CFGR_IC15INT RCC_IC15CFGR_IC15INT_Msk /*!< Divider IC15 integer division factor */ +#define RCC_IC15CFGR_IC15SEL_Pos (28UL) +#define RCC_IC15CFGR_IC15SEL_Msk (0x3UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC15CFGR_IC15SEL RCC_IC15CFGR_IC15SEL_Msk /*!< Divider IC15 source selection */ +#define RCC_IC15CFGR_IC15SEL_0 (0x1UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC15CFGR_IC15SEL_1 (0x2UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC16CFGR register *****************/ +#define RCC_IC16CFGR_IC16INT_Pos (16UL) +#define RCC_IC16CFGR_IC16INT_Msk (0xFFUL << RCC_IC16CFGR_IC16INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC16CFGR_IC16INT RCC_IC16CFGR_IC16INT_Msk /*!< Divider IC16 integer division factor */ +#define RCC_IC16CFGR_IC16SEL_Pos (28UL) +#define RCC_IC16CFGR_IC16SEL_Msk (0x3UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC16CFGR_IC16SEL RCC_IC16CFGR_IC16SEL_Msk /*!< Divider IC16 source selection */ +#define RCC_IC16CFGR_IC16SEL_0 (0x1UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC16CFGR_IC16SEL_1 (0x2UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC17CFGR register *****************/ +#define RCC_IC17CFGR_IC17INT_Pos (16UL) +#define RCC_IC17CFGR_IC17INT_Msk (0xFFUL << RCC_IC17CFGR_IC17INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC17CFGR_IC17INT RCC_IC17CFGR_IC17INT_Msk /*!< Divider IC17 integer division factor */ +#define RCC_IC17CFGR_IC17SEL_Pos (28UL) +#define RCC_IC17CFGR_IC17SEL_Msk (0x3UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC17CFGR_IC17SEL RCC_IC17CFGR_IC17SEL_Msk /*!< Divider IC17 source selection */ +#define RCC_IC17CFGR_IC17SEL_0 (0x1UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC17CFGR_IC17SEL_1 (0x2UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC18CFGR register *****************/ +#define RCC_IC18CFGR_IC18INT_Pos (16UL) +#define RCC_IC18CFGR_IC18INT_Msk (0xFFUL << RCC_IC18CFGR_IC18INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC18CFGR_IC18INT RCC_IC18CFGR_IC18INT_Msk /*!< Divider IC18 integer division factor */ +#define RCC_IC18CFGR_IC18SEL_Pos (28UL) +#define RCC_IC18CFGR_IC18SEL_Msk (0x3UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC18CFGR_IC18SEL RCC_IC18CFGR_IC18SEL_Msk /*!< Divider IC18 source selection */ +#define RCC_IC18CFGR_IC18SEL_0 (0x1UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC18CFGR_IC18SEL_1 (0x2UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC19CFGR register *****************/ +#define RCC_IC19CFGR_IC19INT_Pos (16UL) +#define RCC_IC19CFGR_IC19INT_Msk (0xFFUL << RCC_IC19CFGR_IC19INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC19CFGR_IC19INT RCC_IC19CFGR_IC19INT_Msk /*!< Divider IC19 integer division factor */ +#define RCC_IC19CFGR_IC19SEL_Pos (28UL) +#define RCC_IC19CFGR_IC19SEL_Msk (0x3UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC19CFGR_IC19SEL RCC_IC19CFGR_IC19SEL_Msk /*!< Divider IC19 source selection */ +#define RCC_IC19CFGR_IC19SEL_0 (0x1UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC19CFGR_IC19SEL_1 (0x2UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x20000000 */ + +/***************** Bit definition for RCC_IC20CFGR register *****************/ +#define RCC_IC20CFGR_IC20INT_Pos (16UL) +#define RCC_IC20CFGR_IC20INT_Msk (0xFFUL << RCC_IC20CFGR_IC20INT_Pos) /*!< 0x00FF0000 */ +#define RCC_IC20CFGR_IC20INT RCC_IC20CFGR_IC20INT_Msk /*!< Divider IC20 integer division factor */ +#define RCC_IC20CFGR_IC20SEL_Pos (28UL) +#define RCC_IC20CFGR_IC20SEL_Msk (0x3UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x30000000 */ +#define RCC_IC20CFGR_IC20SEL RCC_IC20CFGR_IC20SEL_Msk /*!< Divider IC20 source selection */ +#define RCC_IC20CFGR_IC20SEL_0 (0x1UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x10000000 */ +#define RCC_IC20CFGR_IC20SEL_1 (0x2UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for RCC_CIER register *******************/ +#define RCC_CIER_LSIRDYIE_Pos (0UL) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE_Pos (1UL) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */ +#define RCC_CIER_MSIRDYIE_Pos (2UL) +#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI ready interrupt enable */ +#define RCC_CIER_HSIRDYIE_Pos (3UL) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI ready interrupt enable */ +#define RCC_CIER_HSERDYIE_Pos (4UL) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */ +#define RCC_CIER_PLL1RDYIE_Pos (8UL) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk /*!< PLL1 ready interrupt enable */ +#define RCC_CIER_PLL2RDYIE_Pos (9UL) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk /*!< PLL2 ready interrupt enable */ +#define RCC_CIER_PLL3RDYIE_Pos (10UL) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk /*!< PLL3 ready interrupt enable */ +#define RCC_CIER_PLL4RDYIE_Pos (11UL) +#define RCC_CIER_PLL4RDYIE_Msk (0x1UL << RCC_CIER_PLL4RDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIER_PLL4RDYIE RCC_CIER_PLL4RDYIE_Msk /*!< PLL4 ready interrupt enable */ +#define RCC_CIER_LSECSSIE_Pos (16UL) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /*!< LSE CSS interrupt enable */ +#define RCC_CIER_HSECSSIE_Pos (17UL) +#define RCC_CIER_HSECSSIE_Msk (0x1UL << RCC_CIER_HSECSSIE_Pos) /*!< 0x00020000 */ +#define RCC_CIER_HSECSSIE RCC_CIER_HSECSSIE_Msk /*!< HSE CSS interrupt enable */ +#define RCC_CIER_WKUPIE_Pos (24UL) +#define RCC_CIER_WKUPIE_Msk (0x1UL << RCC_CIER_WKUPIE_Pos) /*!< 0x01000000 */ +#define RCC_CIER_WKUPIE RCC_CIER_WKUPIE_Msk /*!< CPU wake-up from Stop interrupt enable */ + +/******************* Bit definition for RCC_CIFR register *******************/ +#define RCC_CIFR_LSIRDYF_Pos (0UL) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF_Pos (1UL) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_MSIRDYF_Pos (2UL) +#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI ready interrupt flag */ +#define RCC_CIFR_HSIRDYF_Pos (3UL) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI ready interrupt flag */ +#define RCC_CIFR_HSERDYF_Pos (4UL) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_PLL1RDYF_Pos (8UL) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk /*!< PLL1 ready interrupt flag */ +#define RCC_CIFR_PLL2RDYF_Pos (9UL) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk /*!< PLL2 ready interrupt flag */ +#define RCC_CIFR_PLL3RDYF_Pos (10UL) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk /*!< PLL3 ready interrupt flag */ +#define RCC_CIFR_PLL4RDYF_Pos (11UL) +#define RCC_CIFR_PLL4RDYF_Msk (0x1UL << RCC_CIFR_PLL4RDYF_Pos) /*!< 0x00000800 */ +#define RCC_CIFR_PLL4RDYF RCC_CIFR_PLL4RDYF_Msk /*!< PLL4 ready interrupt flag */ +#define RCC_CIFR_LSECSSF_Pos (16UL) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE ready interrupt flag */ +#define RCC_CIFR_HSECSSF_Pos (17UL) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00020000 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE ready interrupt flag */ +#define RCC_CIFR_WKUPF_Pos (24UL) +#define RCC_CIFR_WKUPF_Msk (0x1UL << RCC_CIFR_WKUPF_Pos) /*!< 0x01000000 */ +#define RCC_CIFR_WKUPF RCC_CIFR_WKUPF_Msk /*!< CPU wake-up from Stop interrupt flag */ + +/******************* Bit definition for RCC_CICR register *******************/ +#define RCC_CICR_LSIRDYC_Pos (0UL) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC_Pos (1UL) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_MSIRDYC_Pos (2UL) +#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI ready interrupt clear */ +#define RCC_CICR_HSIRDYC_Pos (3UL) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI ready interrupt clear */ +#define RCC_CICR_HSERDYC_Pos (4UL) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_PLL1RDYC_Pos (8UL) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk /*!< PLL1 ready interrupt clear */ +#define RCC_CICR_PLL2RDYC_Pos (9UL) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk /*!< PLL2 ready interrupt clear */ +#define RCC_CICR_PLL3RDYC_Pos (10UL) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk /*!< PLL3 ready interrupt clear */ +#define RCC_CICR_PLL4RDYC_Pos (11UL) +#define RCC_CICR_PLL4RDYC_Msk (0x1UL << RCC_CICR_PLL4RDYC_Pos) /*!< 0x00000800 */ +#define RCC_CICR_PLL4RDYC RCC_CICR_PLL4RDYC_Msk /*!< PLL4 ready interrupt clear */ +#define RCC_CICR_LSECSSC_Pos (16UL) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE ready interrupt clear */ +#define RCC_CICR_HSECSSC_Pos (17UL) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00020000 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE ready interrupt clear */ +#define RCC_CICR_WKUPFC_Pos (24UL) +#define RCC_CICR_WKUPFC_Msk (0x1UL << RCC_CICR_WKUPFC_Pos) /*!< 0x01000000 */ +#define RCC_CICR_WKUPFC RCC_CICR_WKUPFC_Msk /*!< CPU wake-up ready interrupt clear */ + +/****************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_ADF1SEL_Pos (0UL) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk /*!< Source selection for the ADF1 kernel clock */ +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_ADC12SEL_Pos (4UL) +#define RCC_CCIPR1_ADC12SEL_Msk (0x7UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR1_ADC12SEL RCC_CCIPR1_ADC12SEL_Msk /*!< Source selection for the ADC12 kernel clock */ +#define RCC_CCIPR1_ADC12SEL_0 (0x1UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_ADC12SEL_1 (0x2UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_ADC12SEL_2 (0x4UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_ADCPRE_Pos (8UL) +#define RCC_CCIPR1_ADCPRE_Msk (0xFFUL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x0000FF00 */ +#define RCC_CCIPR1_ADCPRE RCC_CCIPR1_ADCPRE_Msk /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */ +#define RCC_CCIPR1_ADCPRE_0 (0x1UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_ADCPRE_1 (0x2UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_ADCPRE_2 (0x4UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_ADCPRE_3 (0x8UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_ADCPRE_4 (0x10UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_ADCPRE_5 (0x20UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_ADCPRE_6 (0x40UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_ADCPRE_7 (0x80UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_DCMIPPSEL_Pos (20UL) +#define RCC_CCIPR1_DCMIPPSEL_Msk (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_DCMIPPSEL RCC_CCIPR1_DCMIPPSEL_Msk /*!< Source selection for the DCMIPP kernel clock */ +#define RCC_CCIPR1_DCMIPPSEL_0 (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_DCMIPPSEL_1 (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00200000 */ + +/****************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_ETH1PTPSEL_Pos (0UL) +#define RCC_CCIPR2_ETH1PTPSEL_Msk (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR2_ETH1PTPSEL RCC_CCIPR2_ETH1PTPSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1PTPSEL_0 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_ETH1PTPSEL_1 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_ETH1PTPDIV_Pos (4UL) +#define RCC_CCIPR2_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR2_ETH1PTPDIV RCC_CCIPR2_ETH1PTPDIV_Msk /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */ +#define RCC_CCIPR2_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos (8UL) +#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_ETH1PWRDOWNACK RCC_CCIPR2_ETH1PWRDOWNACK_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1CLKSEL_Pos (12UL) +#define RCC_CCIPR2_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_ETH1CLKSEL RCC_CCIPR2_ETH1CLKSEL_Msk /*!< Source selection for the ETH1 kernel clock */ +#define RCC_CCIPR2_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR2_ETH1SEL_Pos (16UL) +#define RCC_CCIPR2_ETH1SEL_Msk (0x7UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_ETH1SEL RCC_CCIPR2_ETH1SEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1SEL_0 (0x1UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_ETH1SEL_1 (0x2UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_ETH1SEL_2 (0x4UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL_Pos (20UL) +#define RCC_CCIPR2_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_ETH1REFCLKSEL RCC_CCIPR2_ETH1REFCLKSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos (24UL) +#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_ETH1GTXCLKSEL RCC_CCIPR2_ETH1GTXCLKSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR3 register ******************/ +#define RCC_CCIPR3_FDCANSEL_Pos (0UL) +#define RCC_CCIPR3_FDCANSEL_Msk (0x3UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_FDCANSEL RCC_CCIPR3_FDCANSEL_Msk /*!< Source selection for the FDCAN kernel clock */ +#define RCC_CCIPR3_FDCANSEL_0 (0x1UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_FDCANSEL_1 (0x2UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_FMCSEL_Pos (4UL) +#define RCC_CCIPR3_FMCSEL_Msk (0x3UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR3_FMCSEL RCC_CCIPR3_FMCSEL_Msk /*!< Source selection for the FMC kernel clock */ +#define RCC_CCIPR3_FMCSEL_0 (0x1UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_FMCSEL_1 (0x2UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_DFTSEL_Pos (8UL) +#define RCC_CCIPR3_DFTSEL_Msk (0x1UL << RCC_CCIPR3_DFTSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_DFTSEL RCC_CCIPR3_DFTSEL_Msk /*!< Source selection for the DFT kernel clock */ + +/****************** Bit definition for RCC_CCIPR4 register ******************/ +#define RCC_CCIPR4_I2C1SEL_Pos (0UL) +#define RCC_CCIPR4_I2C1SEL_Msk (0x7UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_I2C1SEL RCC_CCIPR4_I2C1SEL_Msk /*!< Source selection for the I2C1 kernel clock */ +#define RCC_CCIPR4_I2C1SEL_0 (0x1UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_I2C1SEL_1 (0x2UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_I2C1SEL_2 (0x4UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR4_I2C2SEL_Pos (4UL) +#define RCC_CCIPR4_I2C2SEL_Msk (0x7UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_I2C2SEL RCC_CCIPR4_I2C2SEL_Msk /*!< Source selection for the I2C2 kernel clock */ +#define RCC_CCIPR4_I2C2SEL_0 (0x1UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_I2C2SEL_1 (0x2UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_I2C2SEL_2 (0x4UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR4_I2C3SEL_Pos (8UL) +#define RCC_CCIPR4_I2C3SEL_Msk (0x7UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_I2C3SEL RCC_CCIPR4_I2C3SEL_Msk /*!< Source selection for the I2C3 kernel clock */ +#define RCC_CCIPR4_I2C3SEL_0 (0x1UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_I2C3SEL_1 (0x2UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_I2C3SEL_2 (0x4UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR4_I2C4SEL_Pos (12UL) +#define RCC_CCIPR4_I2C4SEL_Msk (0x7UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_I2C4SEL RCC_CCIPR4_I2C4SEL_Msk /*!< Source selection for the I2C4 kernel clock */ +#define RCC_CCIPR4_I2C4SEL_0 (0x1UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_I2C4SEL_1 (0x2UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_I2C4SEL_2 (0x4UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR4_I3C1SEL_Pos (16UL) +#define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR4_I3C1SEL RCC_CCIPR4_I3C1SEL_Msk /*!< Source selection for the I3C1 kernel clock */ +#define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR4_I3C2SEL_Pos (20UL) +#define RCC_CCIPR4_I3C2SEL_Msk (0x7UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR4_I3C2SEL RCC_CCIPR4_I3C2SEL_Msk /*!< Source selection for the I3C2 kernel clock */ +#define RCC_CCIPR4_I3C2SEL_0 (0x1UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR4_I3C2SEL_1 (0x2UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR4_I3C2SEL_2 (0x4UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR4_LTDCSEL_Pos (24UL) +#define RCC_CCIPR4_LTDCSEL_Msk (0x3UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR4_LTDCSEL RCC_CCIPR4_LTDCSEL_Msk /*!< Source selection for the LTDC kernel clock */ +#define RCC_CCIPR4_LTDCSEL_0 (0x1UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR4_LTDCSEL_1 (0x2UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x02000000 */ + +/****************** Bit definition for RCC_CCIPR5 register ******************/ +#define RCC_CCIPR5_MCO1SEL_Pos (0UL) +#define RCC_CCIPR5_MCO1SEL_Msk (0x7UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR5_MCO1SEL RCC_CCIPR5_MCO1SEL_Msk /*!< Source selection for the MCO1 kernel clock */ +#define RCC_CCIPR5_MCO1SEL_0 (0x1UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR5_MCO1SEL_1 (0x2UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR5_MCO1SEL_2 (0x4UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR5_MCO1PRE_Pos (4UL) +#define RCC_CCIPR5_MCO1PRE_Msk (0xFUL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x000000F0 */ +#define RCC_CCIPR5_MCO1PRE RCC_CCIPR5_MCO1PRE_Msk /*!< MCO1 Kernel clock divider selection (for clock MCO1) */ +#define RCC_CCIPR5_MCO1PRE_0 (0x1UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR5_MCO1PRE_1 (0x2UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR5_MCO1PRE_2 (0x4UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR5_MCO1PRE_3 (0x8UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR5_MCO2SEL_Pos (8UL) +#define RCC_CCIPR5_MCO2SEL_Msk (0x7UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR5_MCO2SEL RCC_CCIPR5_MCO2SEL_Msk /*!< Source selection for the MCO2 kernel clock */ +#define RCC_CCIPR5_MCO2SEL_0 (0x1UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR5_MCO2SEL_1 (0x2UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR5_MCO2SEL_2 (0x4UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR5_MCO2PRE_Pos (12UL) +#define RCC_CCIPR5_MCO2PRE_Msk (0xFUL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x0000F000 */ +#define RCC_CCIPR5_MCO2PRE RCC_CCIPR5_MCO2PRE_Msk /*!< MCO2 Kernel clock divider selection (for clock MCO2) */ +#define RCC_CCIPR5_MCO2PRE_0 (0x1UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR5_MCO2PRE_1 (0x2UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR5_MCO2PRE_2 (0x4UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR5_MCO2PRE_3 (0x8UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR5_MDF1SEL_Pos (16UL) +#define RCC_CCIPR5_MDF1SEL_Msk (0x7UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR5_MDF1SEL RCC_CCIPR5_MDF1SEL_Msk /*!< Source selection for the MDF1 kernel clock */ +#define RCC_CCIPR5_MDF1SEL_0 (0x1UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR5_MDF1SEL_1 (0x2UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR5_MDF1SEL_2 (0x4UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for RCC_CCIPR6 register ******************/ +#define RCC_CCIPR6_XSPI1SEL_Pos (0UL) +#define RCC_CCIPR6_XSPI1SEL_Msk (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR6_XSPI1SEL RCC_CCIPR6_XSPI1SEL_Msk /*!< Source selection for the XSPI1 kernel clock */ +#define RCC_CCIPR6_XSPI1SEL_0 (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR6_XSPI1SEL_1 (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR6_XSPI2SEL_Pos (4UL) +#define RCC_CCIPR6_XSPI2SEL_Msk (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR6_XSPI2SEL RCC_CCIPR6_XSPI2SEL_Msk /*!< Source selection for the XSPI2 kernel clock */ +#define RCC_CCIPR6_XSPI2SEL_0 (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR6_XSPI2SEL_1 (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR6_XSPI3SEL_Pos (8UL) +#define RCC_CCIPR6_XSPI3SEL_Msk (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR6_XSPI3SEL RCC_CCIPR6_XSPI3SEL_Msk /*!< Source selection for the XSPI3 kernel clock */ +#define RCC_CCIPR6_XSPI3SEL_0 (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR6_XSPI3SEL_1 (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR6_OTGPHY1SEL_Pos (12UL) +#define RCC_CCIPR6_OTGPHY1SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR6_OTGPHY1SEL RCC_CCIPR6_OTGPHY1SEL_Msk /*!< Source selection for the OTGPHY1 kernel clock */ +#define RCC_CCIPR6_OTGPHY1SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR6_OTGPHY1SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos (16UL) +#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR6_OTGPHY1CKREFSEL RCC_CCIPR6_OTGPHY1CKREFSEL_Msk /*!< Set and reset by software */ +#define RCC_CCIPR6_OTGPHY2SEL_Pos (20UL) +#define RCC_CCIPR6_OTGPHY2SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR6_OTGPHY2SEL RCC_CCIPR6_OTGPHY2SEL_Msk /*!< Source selection for the OTGPHY2 kernel clock */ +#define RCC_CCIPR6_OTGPHY2SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR6_OTGPHY2SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos (24UL) +#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR6_OTGPHY2CKREFSEL RCC_CCIPR6_OTGPHY2CKREFSEL_Msk /*!< Set and reset by software */ + +/****************** Bit definition for RCC_CCIPR7 register ******************/ +#define RCC_CCIPR7_PERSEL_Pos (0UL) +#define RCC_CCIPR7_PERSEL_Msk (0x7UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR7_PERSEL RCC_CCIPR7_PERSEL_Msk /*!< Source selection for the PER kernel clock */ +#define RCC_CCIPR7_PERSEL_0 (0x1UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR7_PERSEL_1 (0x2UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR7_PERSEL_2 (0x4UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR7_PSSISEL_Pos (4UL) +#define RCC_CCIPR7_PSSISEL_Msk (0x3UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR7_PSSISEL RCC_CCIPR7_PSSISEL_Msk /*!< Source selection for the PSSI kernel clock */ +#define RCC_CCIPR7_PSSISEL_0 (0x1UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR7_PSSISEL_1 (0x2UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR7_RTCSEL_Pos (8UL) +#define RCC_CCIPR7_RTCSEL_Msk (0x3UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR7_RTCSEL RCC_CCIPR7_RTCSEL_Msk /*!< Source selection for the RTC kernel clock */ +#define RCC_CCIPR7_RTCSEL_0 (0x1UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR7_RTCSEL_1 (0x2UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR7_RTCPRE_Pos (12UL) +#define RCC_CCIPR7_RTCPRE_Msk (0x3FUL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x0003F000 */ +#define RCC_CCIPR7_RTCPRE RCC_CCIPR7_RTCPRE_Msk /*!< RTC OSC clock divider selection (for clock hse_ck) */ +#define RCC_CCIPR7_RTCPRE_0 (0x1UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR7_RTCPRE_1 (0x2UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR7_RTCPRE_2 (0x4UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR7_RTCPRE_3 (0x8UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR7_RTCPRE_4 (0x10UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR7_RTCPRE_5 (0x20UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR7_SAI1SEL_Pos (20UL) +#define RCC_CCIPR7_SAI1SEL_Msk (0x7UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR7_SAI1SEL RCC_CCIPR7_SAI1SEL_Msk /*!< Source selection for the SAI1 kernel clock */ +#define RCC_CCIPR7_SAI1SEL_0 (0x1UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR7_SAI1SEL_1 (0x2UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR7_SAI1SEL_2 (0x4UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR7_SAI2SEL_Pos (24UL) +#define RCC_CCIPR7_SAI2SEL_Msk (0x7UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR7_SAI2SEL RCC_CCIPR7_SAI2SEL_Msk /*!< Source selection for the SAI2 kernel clock */ +#define RCC_CCIPR7_SAI2SEL_0 (0x1UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR7_SAI2SEL_1 (0x2UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR7_SAI2SEL_2 (0x4UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x04000000 */ + +/****************** Bit definition for RCC_CCIPR8 register ******************/ +#define RCC_CCIPR8_SDMMC1SEL_Pos (0UL) +#define RCC_CCIPR8_SDMMC1SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR8_SDMMC1SEL RCC_CCIPR8_SDMMC1SEL_Msk /*!< Source selection for the SDMMC1 kernel clock */ +#define RCC_CCIPR8_SDMMC1SEL_0 (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR8_SDMMC1SEL_1 (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR8_SDMMC2SEL_Pos (4UL) +#define RCC_CCIPR8_SDMMC2SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR8_SDMMC2SEL RCC_CCIPR8_SDMMC2SEL_Msk /*!< Source selection for the SDMMC2 kernel clock */ +#define RCC_CCIPR8_SDMMC2SEL_0 (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR8_SDMMC2SEL_1 (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000020 */ + +/****************** Bit definition for RCC_CCIPR9 register ******************/ +#define RCC_CCIPR9_SPDIFRX1SEL_Pos (0UL) +#define RCC_CCIPR9_SPDIFRX1SEL_Msk (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR9_SPDIFRX1SEL RCC_CCIPR9_SPDIFRX1SEL_Msk /*!< Source selection for the SPDIFRX1 kernel clock */ +#define RCC_CCIPR9_SPDIFRX1SEL_0 (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR9_SPDIFRX1SEL_1 (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR9_SPDIFRX1SEL_2 (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR9_SPI1SEL_Pos (4UL) +#define RCC_CCIPR9_SPI1SEL_Msk (0x7UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR9_SPI1SEL RCC_CCIPR9_SPI1SEL_Msk /*!< Source selection for the SPI1 kernel clock */ +#define RCC_CCIPR9_SPI1SEL_0 (0x1UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR9_SPI1SEL_1 (0x2UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR9_SPI1SEL_2 (0x4UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR9_SPI2SEL_Pos (8UL) +#define RCC_CCIPR9_SPI2SEL_Msk (0x7UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR9_SPI2SEL RCC_CCIPR9_SPI2SEL_Msk /*!< Source selection for the SPI2 kernel clock */ +#define RCC_CCIPR9_SPI2SEL_0 (0x1UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR9_SPI2SEL_1 (0x2UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR9_SPI2SEL_2 (0x4UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR9_SPI3SEL_Pos (12UL) +#define RCC_CCIPR9_SPI3SEL_Msk (0x7UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR9_SPI3SEL RCC_CCIPR9_SPI3SEL_Msk /*!< Source selection for the SPI3 kernel clock */ +#define RCC_CCIPR9_SPI3SEL_0 (0x1UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR9_SPI3SEL_1 (0x2UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR9_SPI3SEL_2 (0x4UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR9_SPI4SEL_Pos (16UL) +#define RCC_CCIPR9_SPI4SEL_Msk (0x7UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR9_SPI4SEL RCC_CCIPR9_SPI4SEL_Msk /*!< Source selection for the SPI4 kernel clock */ +#define RCC_CCIPR9_SPI4SEL_0 (0x1UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR9_SPI4SEL_1 (0x2UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR9_SPI4SEL_2 (0x4UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR9_SPI5SEL_Pos (20UL) +#define RCC_CCIPR9_SPI5SEL_Msk (0x7UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR9_SPI5SEL RCC_CCIPR9_SPI5SEL_Msk /*!< Source selection for the SPI5 kernel clock */ +#define RCC_CCIPR9_SPI5SEL_0 (0x1UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR9_SPI5SEL_1 (0x2UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR9_SPI5SEL_2 (0x4UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR9_SPI6SEL_Pos (24UL) +#define RCC_CCIPR9_SPI6SEL_Msk (0x7UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR9_SPI6SEL RCC_CCIPR9_SPI6SEL_Msk /*!< Source selection for the SPI6 kernel clock */ +#define RCC_CCIPR9_SPI6SEL_0 (0x1UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR9_SPI6SEL_1 (0x2UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR9_SPI6SEL_2 (0x4UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR12 register ******************/ +#define RCC_CCIPR12_LPTIM1SEL_Pos (8UL) +#define RCC_CCIPR12_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR12_LPTIM1SEL RCC_CCIPR12_LPTIM1SEL_Msk /*!< Source selection for the LPTIM1 kernel clock */ +#define RCC_CCIPR12_LPTIM1SEL_0 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR12_LPTIM1SEL_1 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR12_LPTIM1SEL_2 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR12_LPTIM2SEL_Pos (12UL) +#define RCC_CCIPR12_LPTIM2SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR12_LPTIM2SEL RCC_CCIPR12_LPTIM2SEL_Msk /*!< Source selection for the LPTIM2 kernel clock */ +#define RCC_CCIPR12_LPTIM2SEL_0 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR12_LPTIM2SEL_1 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR12_LPTIM2SEL_2 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR12_LPTIM3SEL_Pos (16UL) +#define RCC_CCIPR12_LPTIM3SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR12_LPTIM3SEL RCC_CCIPR12_LPTIM3SEL_Msk /*!< Source selection for the LPTIM3 kernel clock */ +#define RCC_CCIPR12_LPTIM3SEL_0 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR12_LPTIM3SEL_1 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR12_LPTIM3SEL_2 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR12_LPTIM4SEL_Pos (20UL) +#define RCC_CCIPR12_LPTIM4SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR12_LPTIM4SEL RCC_CCIPR12_LPTIM4SEL_Msk /*!< Source selection for the LPTIM4 kernel clock */ +#define RCC_CCIPR12_LPTIM4SEL_0 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR12_LPTIM4SEL_1 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR12_LPTIM4SEL_2 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR12_LPTIM5SEL_Pos (24UL) +#define RCC_CCIPR12_LPTIM5SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR12_LPTIM5SEL RCC_CCIPR12_LPTIM5SEL_Msk /*!< Source selection for the LPTIM5 kernel clock */ +#define RCC_CCIPR12_LPTIM5SEL_0 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR12_LPTIM5SEL_1 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR12_LPTIM5SEL_2 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for RCC_CCIPR13 register ******************/ +#define RCC_CCIPR13_USART1SEL_Pos (0UL) +#define RCC_CCIPR13_USART1SEL_Msk (0x7UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR13_USART1SEL RCC_CCIPR13_USART1SEL_Msk /*!< Source selection for the USART1 kernel clock */ +#define RCC_CCIPR13_USART1SEL_0 (0x1UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR13_USART1SEL_1 (0x2UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR13_USART1SEL_2 (0x4UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR13_USART2SEL_Pos (4UL) +#define RCC_CCIPR13_USART2SEL_Msk (0x7UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR13_USART2SEL RCC_CCIPR13_USART2SEL_Msk /*!< Source selection for the USART2 kernel clock */ +#define RCC_CCIPR13_USART2SEL_0 (0x1UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR13_USART2SEL_1 (0x2UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR13_USART2SEL_2 (0x4UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR13_USART3SEL_Pos (8UL) +#define RCC_CCIPR13_USART3SEL_Msk (0x7UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR13_USART3SEL RCC_CCIPR13_USART3SEL_Msk /*!< Source selection for the USART3 kernel clock */ +#define RCC_CCIPR13_USART3SEL_0 (0x1UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR13_USART3SEL_1 (0x2UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR13_USART3SEL_2 (0x4UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR13_UART4SEL_Pos (12UL) +#define RCC_CCIPR13_UART4SEL_Msk (0x7UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR13_UART4SEL RCC_CCIPR13_UART4SEL_Msk /*!< Source selection for the UART4 kernel clock */ +#define RCC_CCIPR13_UART4SEL_0 (0x1UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR13_UART4SEL_1 (0x2UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR13_UART4SEL_2 (0x4UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR13_UART5SEL_Pos (16UL) +#define RCC_CCIPR13_UART5SEL_Msk (0x7UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR13_UART5SEL RCC_CCIPR13_UART5SEL_Msk /*!< Source selection for the UART5 kernel clock */ +#define RCC_CCIPR13_UART5SEL_0 (0x1UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR13_UART5SEL_1 (0x2UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR13_UART5SEL_2 (0x4UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR13_USART6SEL_Pos (20UL) +#define RCC_CCIPR13_USART6SEL_Msk (0x7UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR13_USART6SEL RCC_CCIPR13_USART6SEL_Msk /*!< Source selection for the USART6 kernel clock */ +#define RCC_CCIPR13_USART6SEL_0 (0x1UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR13_USART6SEL_1 (0x2UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR13_USART6SEL_2 (0x4UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR13_UART7SEL_Pos (24UL) +#define RCC_CCIPR13_UART7SEL_Msk (0x7UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x07000000 */ +#define RCC_CCIPR13_UART7SEL RCC_CCIPR13_UART7SEL_Msk /*!< Source selection for the UART7 kernel clock */ +#define RCC_CCIPR13_UART7SEL_0 (0x1UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR13_UART7SEL_1 (0x2UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x02000000 */ +#define RCC_CCIPR13_UART7SEL_2 (0x4UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x04000000 */ +#define RCC_CCIPR13_UART8SEL_Pos (28UL) +#define RCC_CCIPR13_UART8SEL_Msk (0x7UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x70000000 */ +#define RCC_CCIPR13_UART8SEL RCC_CCIPR13_UART8SEL_Msk /*!< Source selection for the UART8 kernel clock */ +#define RCC_CCIPR13_UART8SEL_0 (0x1UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR13_UART8SEL_1 (0x2UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR13_UART8SEL_2 (0x4UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x40000000 */ + +/***************** Bit definition for RCC_CCIPR14 register ******************/ +#define RCC_CCIPR14_UART9SEL_Pos (0UL) +#define RCC_CCIPR14_UART9SEL_Msk (0x7UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR14_UART9SEL RCC_CCIPR14_UART9SEL_Msk /*!< Source selection for the UART9 kernel clock */ +#define RCC_CCIPR14_UART9SEL_0 (0x1UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR14_UART9SEL_1 (0x2UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR14_UART9SEL_2 (0x4UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR14_USART10SEL_Pos (4UL) +#define RCC_CCIPR14_USART10SEL_Msk (0x7UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR14_USART10SEL RCC_CCIPR14_USART10SEL_Msk /*!< Source selection for the USART10 kernel clock */ +#define RCC_CCIPR14_USART10SEL_0 (0x1UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR14_USART10SEL_1 (0x2UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR14_USART10SEL_2 (0x4UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR14_LPUART1SEL_Pos (8UL) +#define RCC_CCIPR14_LPUART1SEL_Msk (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR14_LPUART1SEL RCC_CCIPR14_LPUART1SEL_Msk /*!< Source selection for the LPUART1 kernel clock */ +#define RCC_CCIPR14_LPUART1SEL_0 (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR14_LPUART1SEL_1 (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR14_LPUART1SEL_2 (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000400 */ + +/***************** Bit definition for RCC_MISCRSTR register *****************/ +#define RCC_MISCRSTR_DBGRST_Pos (0UL) +#define RCC_MISCRSTR_DBGRST_Msk (0x1UL << RCC_MISCRSTR_DBGRST_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTR_DBGRST RCC_MISCRSTR_DBGRST_Msk /*!< DBG reset */ +#define RCC_MISCRSTR_XSPIPHY1RST_Pos (4UL) +#define RCC_MISCRSTR_XSPIPHY1RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTR_XSPIPHY1RST RCC_MISCRSTR_XSPIPHY1RST_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTR_XSPIPHY2RST_Pos (5UL) +#define RCC_MISCRSTR_XSPIPHY2RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTR_XSPIPHY2RST RCC_MISCRSTR_XSPIPHY2RST_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTR_SDMMC1DLLRST_Pos (7UL) +#define RCC_MISCRSTR_SDMMC1DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTR_SDMMC1DLLRST RCC_MISCRSTR_SDMMC1DLLRST_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTR_SDMMC2DLLRST_Pos (8UL) +#define RCC_MISCRSTR_SDMMC2DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTR_SDMMC2DLLRST RCC_MISCRSTR_SDMMC2DLLRST_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTR register ******************/ +#define RCC_MEMRSTR_AXISRAM3RST_Pos (0UL) +#define RCC_MEMRSTR_AXISRAM3RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */ +#define RCC_MEMRSTR_AXISRAM3RST RCC_MEMRSTR_AXISRAM3RST_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTR_AXISRAM4RST_Pos (1UL) +#define RCC_MEMRSTR_AXISRAM4RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */ +#define RCC_MEMRSTR_AXISRAM4RST RCC_MEMRSTR_AXISRAM4RST_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTR_AXISRAM5RST_Pos (2UL) +#define RCC_MEMRSTR_AXISRAM5RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */ +#define RCC_MEMRSTR_AXISRAM5RST RCC_MEMRSTR_AXISRAM5RST_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTR_AXISRAM6RST_Pos (3UL) +#define RCC_MEMRSTR_AXISRAM6RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */ +#define RCC_MEMRSTR_AXISRAM6RST RCC_MEMRSTR_AXISRAM6RST_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTR_AHBSRAM1RST_Pos (4UL) +#define RCC_MEMRSTR_AHBSRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */ +#define RCC_MEMRSTR_AHBSRAM1RST RCC_MEMRSTR_AHBSRAM1RST_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTR_AHBSRAM2RST_Pos (5UL) +#define RCC_MEMRSTR_AHBSRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */ +#define RCC_MEMRSTR_AHBSRAM2RST RCC_MEMRSTR_AHBSRAM2RST_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTR_AXISRAM1RST_Pos (7UL) +#define RCC_MEMRSTR_AXISRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */ +#define RCC_MEMRSTR_AXISRAM1RST RCC_MEMRSTR_AXISRAM1RST_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTR_AXISRAM2RST_Pos (8UL) +#define RCC_MEMRSTR_AXISRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */ +#define RCC_MEMRSTR_AXISRAM2RST RCC_MEMRSTR_AXISRAM2RST_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTR_FLEXRAMRST_Pos (9UL) +#define RCC_MEMRSTR_FLEXRAMRST_Msk (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTR_FLEXRAMRST RCC_MEMRSTR_FLEXRAMRST_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTR_CACHEAXIRAMRST_Pos (10UL) +#define RCC_MEMRSTR_CACHEAXIRAMRST_Msk (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTR_CACHEAXIRAMRST RCC_MEMRSTR_CACHEAXIRAMRST_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTR_VENCRAMRST_Pos (11UL) +#define RCC_MEMRSTR_VENCRAMRST_Msk (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTR_VENCRAMRST RCC_MEMRSTR_VENCRAMRST_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTR_BOOTROMRST_Pos (12UL) +#define RCC_MEMRSTR_BOOTROMRST_Msk (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTR_BOOTROMRST RCC_MEMRSTR_BOOTROMRST_Msk /*!< Boot ROM reset */ + +/***************** Bit definition for RCC_AHB1RSTR register *****************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4UL) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTR_ADC12RST_Pos (5UL) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk /*!< ADC12 reset */ + +/***************** Bit definition for RCC_AHB2RSTR register *****************/ +#define RCC_AHB2RSTR_RAMCFGRST_Pos (12UL) +#define RCC_AHB2RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTR_RAMCFGRST RCC_AHB2RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTR_MDF1RST_Pos (16UL) +#define RCC_AHB2RSTR_MDF1RST_Msk (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_MDF1RST RCC_AHB2RSTR_MDF1RST_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTR_ADF1RST_Pos (17UL) +#define RCC_AHB2RSTR_ADF1RST_Msk (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_ADF1RST RCC_AHB2RSTR_ADF1RST_Msk /*!< ADF1 reset */ + +/***************** Bit definition for RCC_AHB3RSTR register *****************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0UL) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk /*!< RNG reset */ +#define RCC_AHB3RSTR_HASHRST_Pos (1UL) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk /*!< HASH reset */ +#define RCC_AHB3RSTR_CRYPRST_Pos (2UL) +#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTR_SAESRST_Pos (4UL) +#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk /*!< SAES reset */ +#define RCC_AHB3RSTR_PKARST_Pos (8UL) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk /*!< PKA reset */ +#define RCC_AHB3RSTR_IACRST_Pos (10UL) +#define RCC_AHB3RSTR_IACRST_Msk (0x1UL << RCC_AHB3RSTR_IACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTR_IACRST RCC_AHB3RSTR_IACRST_Msk /*!< IAC reset */ + +/***************** Bit definition for RCC_AHB4RSTR register *****************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0UL) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTR_GPIOBRST_Pos (1UL) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTR_GPIOCRST_Pos (2UL) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTR_GPIODRST_Pos (3UL) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTR_GPIOERST_Pos (4UL) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTR_GPIOFRST_Pos (5UL) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTR_GPIOGRST_Pos (6UL) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTR_GPIOHRST_Pos (7UL) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTR_GPIONRST_Pos (13UL) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTR_GPIOORST_Pos (14UL) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTR_GPIOPRST_Pos (15UL) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTR_GPIOQRST_Pos (16UL) +#define RCC_AHB4RSTR_GPIOQRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB4RSTR_GPIOQRST RCC_AHB4RSTR_GPIOQRST_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTR_PWRRST_Pos (18UL) +#define RCC_AHB4RSTR_PWRRST_Msk (0x1UL << RCC_AHB4RSTR_PWRRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTR_PWRRST RCC_AHB4RSTR_PWRRST_Msk /*!< PWR reset */ +#define RCC_AHB4RSTR_CRCRST_Pos (19UL) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk /*!< CRC reset */ + +/***************** Bit definition for RCC_AHB5RSTR register *****************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0UL) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTR_DMA2DRST_Pos (1UL) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTR_JPEGRST_Pos (3UL) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTR_FMCRST_Pos (4UL) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk /*!< FMC reset */ +#define RCC_AHB5RSTR_XSPI1RST_Pos (5UL) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTR_PSSIRST_Pos (6UL) +#define RCC_AHB5RSTR_PSSIRST_Msk (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTR_PSSIRST RCC_AHB5RSTR_PSSIRST_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTR_SDMMC2RST_Pos (7UL) +#define RCC_AHB5RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTR_SDMMC2RST RCC_AHB5RSTR_SDMMC2RST_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8UL) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTR_XSPI2RST_Pos (12UL) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTR_XSPIMRST_Pos (13UL) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTR_XSPI3RST_Pos (17UL) +#define RCC_AHB5RSTR_XSPI3RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB5RSTR_XSPI3RST RCC_AHB5RSTR_XSPI3RST_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTR_GFXMMURST_Pos (19UL) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTR_GPU2DRST_Pos (20UL) +#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos (23UL) +#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTR_OTG1PHYCTLRST RCC_AHB5RSTR_OTG1PHYCTLRST_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos (24UL) +#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTR_OTG2PHYCTLRST RCC_AHB5RSTR_OTG2PHYCTLRST_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTR_ETH1RST_Pos (25UL) +#define RCC_AHB5RSTR_ETH1RST_Msk (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTR_ETH1RST RCC_AHB5RSTR_ETH1RST_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTR_OTG1RST_Pos (26UL) +#define RCC_AHB5RSTR_OTG1RST_Msk (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTR_OTG1RST RCC_AHB5RSTR_OTG1RST_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTR_OTGPHY1RST_Pos (27UL) +#define RCC_AHB5RSTR_OTGPHY1RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */ +#define RCC_AHB5RSTR_OTGPHY1RST RCC_AHB5RSTR_OTGPHY1RST_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTR_OTGPHY2RST_Pos (28UL) +#define RCC_AHB5RSTR_OTGPHY2RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */ +#define RCC_AHB5RSTR_OTGPHY2RST RCC_AHB5RSTR_OTGPHY2RST_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTR_OTG2RST_Pos (29UL) +#define RCC_AHB5RSTR_OTG2RST_Msk (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTR_OTG2RST RCC_AHB5RSTR_OTG2RST_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTR_CACHEAXIRST_Pos (30UL) +#define RCC_AHB5RSTR_CACHEAXIRST_Msk (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTR_CACHEAXIRST RCC_AHB5RSTR_CACHEAXIRST_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTR_NPURST_Pos (31UL) +#define RCC_AHB5RSTR_NPURST_Msk (0x1UL << RCC_AHB5RSTR_NPURST_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTR_NPURST RCC_AHB5RSTR_NPURST_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTR1 register *****************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0UL) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTR1_TIM3RST_Pos (1UL) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTR1_TIM4RST_Pos (2UL) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTR1_TIM5RST_Pos (3UL) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTR1_TIM6RST_Pos (4UL) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTR1_TIM7RST_Pos (5UL) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTR1_TIM12RST_Pos (6UL) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTR1_TIM13RST_Pos (7UL) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTR1_TIM14RST_Pos (8UL) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9UL) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTR1_WWDGRST_Pos (11UL) +#define RCC_APB1RSTR1_WWDGRST_Msk (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR1_WWDGRST RCC_APB1RSTR1_WWDGRST_Msk /*!< WWDG reset */ +#define RCC_APB1RSTR1_TIM10RST_Pos (12UL) +#define RCC_APB1RSTR1_TIM10RST_Msk (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTR1_TIM10RST RCC_APB1RSTR1_TIM10RST_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTR1_TIM11RST_Pos (13UL) +#define RCC_APB1RSTR1_TIM11RST_Msk (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTR1_TIM11RST RCC_APB1RSTR1_TIM11RST_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTR1_SPI2RST_Pos (14UL) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTR1_SPI3RST_Pos (15UL) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTR1_SPDIFRX1RST_Pos (16UL) +#define RCC_APB1RSTR1_SPDIFRX1RST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRX1RST RCC_APB1RSTR1_SPDIFRX1RST_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTR1_USART2RST_Pos (17UL) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk /*!< USART2 reset */ +#define RCC_APB1RSTR1_USART3RST_Pos (18UL) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk /*!< USART3 reset */ +#define RCC_APB1RSTR1_UART4RST_Pos (19UL) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk /*!< UART4 reset */ +#define RCC_APB1RSTR1_UART5RST_Pos (20UL) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk /*!< UART5 reset */ +#define RCC_APB1RSTR1_I2C1RST_Pos (21UL) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTR1_I2C2RST_Pos (22UL) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTR1_I2C3RST_Pos (23UL) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTR1_I3C1RST_Pos (24UL) +#define RCC_APB1RSTR1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTR1_I3C1RST RCC_APB1RSTR1_I3C1RST_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTR1_I3C2RST_Pos (25UL) +#define RCC_APB1RSTR1_I3C2RST_Msk (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR1_I3C2RST RCC_APB1RSTR1_I3C2RST_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTR1_UART7RST_Pos (30UL) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk /*!< UART7 reset */ +#define RCC_APB1RSTR1_UART8RST_Pos (31UL) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTR2 register *****************/ +#define RCC_APB1RSTR2_MDIOSRST_Pos (5UL) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTR2_FDCANRST_Pos (8UL) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTR2_UCPD1RST_Pos (18UL) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk /*!< UCPD1 reset */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0UL) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (1UL) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (4UL) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ +#define RCC_APB2RSTR_USART6RST_Pos (5UL) +#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ +#define RCC_APB2RSTR_UART9RST_Pos (6UL) +#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk /*!< UART9 reset */ +#define RCC_APB2RSTR_USART10RST_Pos (7UL) +#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */ +#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk /*!< USART10 reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12UL) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST_Pos (13UL) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTR_TIM18RST_Pos (15UL) +#define RCC_APB2RSTR_TIM18RST_Msk (0x1UL << RCC_APB2RSTR_TIM18RST_Pos) /*!< 0x00008000 */ +#define RCC_APB2RSTR_TIM18RST RCC_APB2RSTR_TIM18RST_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTR_TIM15RST_Pos (16UL) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST_Pos (17UL) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST_Pos (18UL) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTR_TIM9RST_Pos (19UL) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTR_SPI5RST_Pos (20UL) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTR_SAI1RST_Pos (21UL) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST_Pos (22UL) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTR1 register *****************/ +#define RCC_APB4RSTR1_HDPRST_Pos (2UL) +#define RCC_APB4RSTR1_HDPRST_Msk (0x1UL << RCC_APB4RSTR1_HDPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR1_HDPRST RCC_APB4RSTR1_HDPRST_Msk /*!< HDP reset */ +#define RCC_APB4RSTR1_LPUART1RST_Pos (3UL) +#define RCC_APB4RSTR1_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR1_LPUART1RST RCC_APB4RSTR1_LPUART1RST_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTR1_SPI6RST_Pos (5UL) +#define RCC_APB4RSTR1_SPI6RST_Msk (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR1_SPI6RST RCC_APB4RSTR1_SPI6RST_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTR1_I2C4RST_Pos (7UL) +#define RCC_APB4RSTR1_I2C4RST_Msk (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos) /*!< 0x00000080 */ +#define RCC_APB4RSTR1_I2C4RST RCC_APB4RSTR1_I2C4RST_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTR1_LPTIM2RST_Pos (9UL) +#define RCC_APB4RSTR1_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */ +#define RCC_APB4RSTR1_LPTIM2RST RCC_APB4RSTR1_LPTIM2RST_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTR1_LPTIM3RST_Pos (10UL) +#define RCC_APB4RSTR1_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */ +#define RCC_APB4RSTR1_LPTIM3RST RCC_APB4RSTR1_LPTIM3RST_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTR1_LPTIM4RST_Pos (11UL) +#define RCC_APB4RSTR1_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */ +#define RCC_APB4RSTR1_LPTIM4RST RCC_APB4RSTR1_LPTIM4RST_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTR1_LPTIM5RST_Pos (12UL) +#define RCC_APB4RSTR1_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */ +#define RCC_APB4RSTR1_LPTIM5RST RCC_APB4RSTR1_LPTIM5RST_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTR1_VREFBUFRST_Pos (15UL) +#define RCC_APB4RSTR1_VREFBUFRST_Msk (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR1_VREFBUFRST RCC_APB4RSTR1_VREFBUFRST_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTR1_RTCRST_Pos (16UL) +#define RCC_APB4RSTR1_RTCRST_Msk (0x1UL << RCC_APB4RSTR1_RTCRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTR1_RTCRST RCC_APB4RSTR1_RTCRST_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTR2 register *****************/ +#define RCC_APB4RSTR2_SYSCFGRST_Pos (0UL) +#define RCC_APB4RSTR2_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */ +#define RCC_APB4RSTR2_SYSCFGRST RCC_APB4RSTR2_SYSCFGRST_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTR2_DTSRST_Pos (2UL) +#define RCC_APB4RSTR2_DTSRST_Msk (0x1UL << RCC_APB4RSTR2_DTSRST_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTR2_DTSRST RCC_APB4RSTR2_DTSRST_Msk /*!< DTS reset */ + +/***************** Bit definition for RCC_APB5RSTR register *****************/ +#define RCC_APB5RSTR_LTDCRST_Pos (1UL) +#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk /*!< LTDC reset */ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2UL) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTR_GFXTIMRST_Pos (4UL) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTR_VENCRST_Pos (5UL) +#define RCC_APB5RSTR_VENCRST_Msk (0x1UL << RCC_APB5RSTR_VENCRST_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTR_VENCRST RCC_APB5RSTR_VENCRST_Msk /*!< VENC reset */ +#define RCC_APB5RSTR_CSIRST_Pos (6UL) +#define RCC_APB5RSTR_CSIRST_Msk (0x1UL << RCC_APB5RSTR_CSIRST_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTR_CSIRST RCC_APB5RSTR_CSIRST_Msk /*!< CSI reset */ + +/****************** Bit definition for RCC_DIVENR register ******************/ +#define RCC_DIVENR_IC1EN_Pos (0UL) +#define RCC_DIVENR_IC1EN_Msk (0x1UL << RCC_DIVENR_IC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DIVENR_IC1EN RCC_DIVENR_IC1EN_Msk /*!< IC1 enable */ +#define RCC_DIVENR_IC2EN_Pos (1UL) +#define RCC_DIVENR_IC2EN_Msk (0x1UL << RCC_DIVENR_IC2EN_Pos) /*!< 0x00000002 */ +#define RCC_DIVENR_IC2EN RCC_DIVENR_IC2EN_Msk /*!< IC2 enable */ +#define RCC_DIVENR_IC3EN_Pos (2UL) +#define RCC_DIVENR_IC3EN_Msk (0x1UL << RCC_DIVENR_IC3EN_Pos) /*!< 0x00000004 */ +#define RCC_DIVENR_IC3EN RCC_DIVENR_IC3EN_Msk /*!< IC3 enable */ +#define RCC_DIVENR_IC4EN_Pos (3UL) +#define RCC_DIVENR_IC4EN_Msk (0x1UL << RCC_DIVENR_IC4EN_Pos) /*!< 0x00000008 */ +#define RCC_DIVENR_IC4EN RCC_DIVENR_IC4EN_Msk /*!< IC4 enable */ +#define RCC_DIVENR_IC5EN_Pos (4UL) +#define RCC_DIVENR_IC5EN_Msk (0x1UL << RCC_DIVENR_IC5EN_Pos) /*!< 0x00000010 */ +#define RCC_DIVENR_IC5EN RCC_DIVENR_IC5EN_Msk /*!< IC5 enable */ +#define RCC_DIVENR_IC6EN_Pos (5UL) +#define RCC_DIVENR_IC6EN_Msk (0x1UL << RCC_DIVENR_IC6EN_Pos) /*!< 0x00000020 */ +#define RCC_DIVENR_IC6EN RCC_DIVENR_IC6EN_Msk /*!< IC6 enable */ +#define RCC_DIVENR_IC7EN_Pos (6UL) +#define RCC_DIVENR_IC7EN_Msk (0x1UL << RCC_DIVENR_IC7EN_Pos) /*!< 0x00000040 */ +#define RCC_DIVENR_IC7EN RCC_DIVENR_IC7EN_Msk /*!< IC7 enable */ +#define RCC_DIVENR_IC8EN_Pos (7UL) +#define RCC_DIVENR_IC8EN_Msk (0x1UL << RCC_DIVENR_IC8EN_Pos) /*!< 0x00000080 */ +#define RCC_DIVENR_IC8EN RCC_DIVENR_IC8EN_Msk /*!< IC8 enable */ +#define RCC_DIVENR_IC9EN_Pos (8UL) +#define RCC_DIVENR_IC9EN_Msk (0x1UL << RCC_DIVENR_IC9EN_Pos) /*!< 0x00000100 */ +#define RCC_DIVENR_IC9EN RCC_DIVENR_IC9EN_Msk /*!< IC9 enable */ +#define RCC_DIVENR_IC10EN_Pos (9UL) +#define RCC_DIVENR_IC10EN_Msk (0x1UL << RCC_DIVENR_IC10EN_Pos) /*!< 0x00000200 */ +#define RCC_DIVENR_IC10EN RCC_DIVENR_IC10EN_Msk /*!< IC10 enable */ +#define RCC_DIVENR_IC11EN_Pos (10UL) +#define RCC_DIVENR_IC11EN_Msk (0x1UL << RCC_DIVENR_IC11EN_Pos) /*!< 0x00000400 */ +#define RCC_DIVENR_IC11EN RCC_DIVENR_IC11EN_Msk /*!< IC11 enable */ +#define RCC_DIVENR_IC12EN_Pos (11UL) +#define RCC_DIVENR_IC12EN_Msk (0x1UL << RCC_DIVENR_IC12EN_Pos) /*!< 0x00000800 */ +#define RCC_DIVENR_IC12EN RCC_DIVENR_IC12EN_Msk /*!< IC12 enable */ +#define RCC_DIVENR_IC13EN_Pos (12UL) +#define RCC_DIVENR_IC13EN_Msk (0x1UL << RCC_DIVENR_IC13EN_Pos) /*!< 0x00001000 */ +#define RCC_DIVENR_IC13EN RCC_DIVENR_IC13EN_Msk /*!< IC13 enable */ +#define RCC_DIVENR_IC14EN_Pos (13UL) +#define RCC_DIVENR_IC14EN_Msk (0x1UL << RCC_DIVENR_IC14EN_Pos) /*!< 0x00002000 */ +#define RCC_DIVENR_IC14EN RCC_DIVENR_IC14EN_Msk /*!< IC14 enable */ +#define RCC_DIVENR_IC15EN_Pos (14UL) +#define RCC_DIVENR_IC15EN_Msk (0x1UL << RCC_DIVENR_IC15EN_Pos) /*!< 0x00004000 */ +#define RCC_DIVENR_IC15EN RCC_DIVENR_IC15EN_Msk /*!< IC15 enable */ +#define RCC_DIVENR_IC16EN_Pos (15UL) +#define RCC_DIVENR_IC16EN_Msk (0x1UL << RCC_DIVENR_IC16EN_Pos) /*!< 0x00008000 */ +#define RCC_DIVENR_IC16EN RCC_DIVENR_IC16EN_Msk /*!< IC16 enable */ +#define RCC_DIVENR_IC17EN_Pos (16UL) +#define RCC_DIVENR_IC17EN_Msk (0x1UL << RCC_DIVENR_IC17EN_Pos) /*!< 0x00010000 */ +#define RCC_DIVENR_IC17EN RCC_DIVENR_IC17EN_Msk /*!< IC17 enable */ +#define RCC_DIVENR_IC18EN_Pos (17UL) +#define RCC_DIVENR_IC18EN_Msk (0x1UL << RCC_DIVENR_IC18EN_Pos) /*!< 0x00020000 */ +#define RCC_DIVENR_IC18EN RCC_DIVENR_IC18EN_Msk /*!< IC18 enable */ +#define RCC_DIVENR_IC19EN_Pos (18UL) +#define RCC_DIVENR_IC19EN_Msk (0x1UL << RCC_DIVENR_IC19EN_Pos) /*!< 0x00040000 */ +#define RCC_DIVENR_IC19EN RCC_DIVENR_IC19EN_Msk /*!< IC19 enable */ +#define RCC_DIVENR_IC20EN_Pos (19UL) +#define RCC_DIVENR_IC20EN_Msk (0x1UL << RCC_DIVENR_IC20EN_Pos) /*!< 0x00080000 */ +#define RCC_DIVENR_IC20EN RCC_DIVENR_IC20EN_Msk /*!< IC20 enable */ + +/****************** Bit definition for RCC_BUSENR register ******************/ +#define RCC_BUSENR_ACLKNEN_Pos (0UL) +#define RCC_BUSENR_ACLKNEN_Msk (0x1UL << RCC_BUSENR_ACLKNEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSENR_ACLKNEN RCC_BUSENR_ACLKNEN_Msk /*!< ACLKN enable */ +#define RCC_BUSENR_ACLKNCEN_Pos (1UL) +#define RCC_BUSENR_ACLKNCEN_Msk (0x1UL << RCC_BUSENR_ACLKNCEN_Pos) /*!< 0x00000002 */ +#define RCC_BUSENR_ACLKNCEN RCC_BUSENR_ACLKNCEN_Msk /*!< ACLKNC enable */ +#define RCC_BUSENR_AHBMEN_Pos (2UL) +#define RCC_BUSENR_AHBMEN_Msk (0x1UL << RCC_BUSENR_AHBMEN_Pos) /*!< 0x00000004 */ +#define RCC_BUSENR_AHBMEN RCC_BUSENR_AHBMEN_Msk /*!< AHBM enable */ +#define RCC_BUSENR_AHB1EN_Pos (3UL) +#define RCC_BUSENR_AHB1EN_Msk (0x1UL << RCC_BUSENR_AHB1EN_Pos) /*!< 0x00000008 */ +#define RCC_BUSENR_AHB1EN RCC_BUSENR_AHB1EN_Msk /*!< AHB1 enable */ +#define RCC_BUSENR_AHB2EN_Pos (4UL) +#define RCC_BUSENR_AHB2EN_Msk (0x1UL << RCC_BUSENR_AHB2EN_Pos) /*!< 0x00000010 */ +#define RCC_BUSENR_AHB2EN RCC_BUSENR_AHB2EN_Msk /*!< AHB2 enable */ +#define RCC_BUSENR_AHB3EN_Pos (5UL) +#define RCC_BUSENR_AHB3EN_Msk (0x1UL << RCC_BUSENR_AHB3EN_Pos) /*!< 0x00000020 */ +#define RCC_BUSENR_AHB3EN RCC_BUSENR_AHB3EN_Msk /*!< AHB3 enable */ +#define RCC_BUSENR_AHB4EN_Pos (6UL) +#define RCC_BUSENR_AHB4EN_Msk (0x1UL << RCC_BUSENR_AHB4EN_Pos) /*!< 0x00000040 */ +#define RCC_BUSENR_AHB4EN RCC_BUSENR_AHB4EN_Msk /*!< AHB4 enable */ +#define RCC_BUSENR_AHB5EN_Pos (7UL) +#define RCC_BUSENR_AHB5EN_Msk (0x1UL << RCC_BUSENR_AHB5EN_Pos) /*!< 0x00000080 */ +#define RCC_BUSENR_AHB5EN RCC_BUSENR_AHB5EN_Msk /*!< AHB5 enable */ +#define RCC_BUSENR_APB1EN_Pos (8UL) +#define RCC_BUSENR_APB1EN_Msk (0x1UL << RCC_BUSENR_APB1EN_Pos) /*!< 0x00000100 */ +#define RCC_BUSENR_APB1EN RCC_BUSENR_APB1EN_Msk /*!< APB1 enable */ +#define RCC_BUSENR_APB2EN_Pos (9UL) +#define RCC_BUSENR_APB2EN_Msk (0x1UL << RCC_BUSENR_APB2EN_Pos) /*!< 0x00000200 */ +#define RCC_BUSENR_APB2EN RCC_BUSENR_APB2EN_Msk /*!< APB2 enable */ +#define RCC_BUSENR_APB3EN_Pos (10UL) +#define RCC_BUSENR_APB3EN_Msk (0x1UL << RCC_BUSENR_APB3EN_Pos) /*!< 0x00000400 */ +#define RCC_BUSENR_APB3EN RCC_BUSENR_APB3EN_Msk /*!< APB3 enable */ +#define RCC_BUSENR_APB4EN_Pos (11UL) +#define RCC_BUSENR_APB4EN_Msk (0x1UL << RCC_BUSENR_APB4EN_Pos) /*!< 0x00000800 */ +#define RCC_BUSENR_APB4EN RCC_BUSENR_APB4EN_Msk /*!< APB4 enable */ +#define RCC_BUSENR_APB5EN_Pos (12UL) +#define RCC_BUSENR_APB5EN_Msk (0x1UL << RCC_BUSENR_APB5EN_Pos) /*!< 0x00001000 */ +#define RCC_BUSENR_APB5EN RCC_BUSENR_APB5EN_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENR register ******************/ +#define RCC_MISCENR_DBGEN_Pos (0UL) +#define RCC_MISCENR_DBGEN_Msk (0x1UL << RCC_MISCENR_DBGEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCENR_DBGEN RCC_MISCENR_DBGEN_Msk /*!< DBG enable */ +#define RCC_MISCENR_MCO1EN_Pos (1UL) +#define RCC_MISCENR_MCO1EN_Msk (0x1UL << RCC_MISCENR_MCO1EN_Pos) /*!< 0x00000002 */ +#define RCC_MISCENR_MCO1EN RCC_MISCENR_MCO1EN_Msk /*!< MCO1 enable */ +#define RCC_MISCENR_MCO2EN_Pos (2UL) +#define RCC_MISCENR_MCO2EN_Msk (0x1UL << RCC_MISCENR_MCO2EN_Pos) /*!< 0x00000004 */ +#define RCC_MISCENR_MCO2EN RCC_MISCENR_MCO2EN_Msk /*!< MCO2 enable */ +#define RCC_MISCENR_XSPIPHYCOMPEN_Pos (3UL) +#define RCC_MISCENR_XSPIPHYCOMPEN_Msk (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCENR_XSPIPHYCOMPEN RCC_MISCENR_XSPIPHYCOMPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENR_PEREN_Pos (6UL) +#define RCC_MISCENR_PEREN_Msk (0x1UL << RCC_MISCENR_PEREN_Pos) /*!< 0x00000040 */ +#define RCC_MISCENR_PEREN RCC_MISCENR_PEREN_Msk /*!< PER enable */ + +/****************** Bit definition for RCC_MEMENR register ******************/ +#define RCC_MEMENR_AXISRAM3EN_Pos (0UL) +#define RCC_MEMENR_AXISRAM3EN_Msk (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos) /*!< 0x00000001 */ +#define RCC_MEMENR_AXISRAM3EN RCC_MEMENR_AXISRAM3EN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENR_AXISRAM4EN_Pos (1UL) +#define RCC_MEMENR_AXISRAM4EN_Msk (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos) /*!< 0x00000002 */ +#define RCC_MEMENR_AXISRAM4EN RCC_MEMENR_AXISRAM4EN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENR_AXISRAM5EN_Pos (2UL) +#define RCC_MEMENR_AXISRAM5EN_Msk (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos) /*!< 0x00000004 */ +#define RCC_MEMENR_AXISRAM5EN RCC_MEMENR_AXISRAM5EN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENR_AXISRAM6EN_Pos (3UL) +#define RCC_MEMENR_AXISRAM6EN_Msk (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos) /*!< 0x00000008 */ +#define RCC_MEMENR_AXISRAM6EN RCC_MEMENR_AXISRAM6EN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENR_AHBSRAM1EN_Pos (4UL) +#define RCC_MEMENR_AHBSRAM1EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos) /*!< 0x00000010 */ +#define RCC_MEMENR_AHBSRAM1EN RCC_MEMENR_AHBSRAM1EN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENR_AHBSRAM2EN_Pos (5UL) +#define RCC_MEMENR_AHBSRAM2EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos) /*!< 0x00000020 */ +#define RCC_MEMENR_AHBSRAM2EN RCC_MEMENR_AHBSRAM2EN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENR_BKPSRAMEN_Pos (6UL) +#define RCC_MEMENR_BKPSRAMEN_Msk (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMENR_BKPSRAMEN RCC_MEMENR_BKPSRAMEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENR_AXISRAM1EN_Pos (7UL) +#define RCC_MEMENR_AXISRAM1EN_Msk (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos) /*!< 0x00000080 */ +#define RCC_MEMENR_AXISRAM1EN RCC_MEMENR_AXISRAM1EN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENR_AXISRAM2EN_Pos (8UL) +#define RCC_MEMENR_AXISRAM2EN_Msk (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos) /*!< 0x00000100 */ +#define RCC_MEMENR_AXISRAM2EN RCC_MEMENR_AXISRAM2EN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENR_FLEXRAMEN_Pos (9UL) +#define RCC_MEMENR_FLEXRAMEN_Msk (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMENR_FLEXRAMEN RCC_MEMENR_FLEXRAMEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENR_CACHEAXIRAMEN_Pos (10UL) +#define RCC_MEMENR_CACHEAXIRAMEN_Msk (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */ +#define RCC_MEMENR_CACHEAXIRAMEN RCC_MEMENR_CACHEAXIRAMEN_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENR_VENCRAMEN_Pos (11UL) +#define RCC_MEMENR_VENCRAMEN_Msk (0x1UL << RCC_MEMENR_VENCRAMEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMENR_VENCRAMEN RCC_MEMENR_VENCRAMEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMENR_BOOTROMEN_Pos (12UL) +#define RCC_MEMENR_BOOTROMEN_Msk (0x1UL << RCC_MEMENR_BOOTROMEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMENR_BOOTROMEN RCC_MEMENR_BOOTROMEN_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENR register ******************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4UL) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENR_ADC12EN_Pos (5UL) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENR register ******************/ +#define RCC_AHB2ENR_RAMCFGEN_Pos (12UL) +#define RCC_AHB2ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENR_RAMCFGEN RCC_AHB2ENR_RAMCFGEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENR_MDF1EN_Pos (16UL) +#define RCC_AHB2ENR_MDF1EN_Msk (0x1UL << RCC_AHB2ENR_MDF1EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_MDF1EN RCC_AHB2ENR_MDF1EN_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENR_ADF1EN_Pos (17UL) +#define RCC_AHB2ENR_ADF1EN_Msk (0x1UL << RCC_AHB2ENR_ADF1EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_ADF1EN RCC_AHB2ENR_ADF1EN_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENR register ******************/ +#define RCC_AHB3ENR_RNGEN_Pos (0UL) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk /*!< RNG enable */ +#define RCC_AHB3ENR_HASHEN_Pos (1UL) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk /*!< HASH enable */ +#define RCC_AHB3ENR_CRYPEN_Pos (2UL) +#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk /*!< CRYP enable */ +#define RCC_AHB3ENR_SAESEN_Pos (4UL) +#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk /*!< SAES enable */ +#define RCC_AHB3ENR_PKAEN_Pos (8UL) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk /*!< PKA enable */ +#define RCC_AHB3ENR_RIFSCEN_Pos (9UL) +#define RCC_AHB3ENR_RIFSCEN_Msk (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENR_RIFSCEN RCC_AHB3ENR_RIFSCEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENR_IACEN_Pos (10UL) +#define RCC_AHB3ENR_IACEN_Msk (0x1UL << RCC_AHB3ENR_IACEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENR_IACEN RCC_AHB3ENR_IACEN_Msk /*!< IAC enable */ +#define RCC_AHB3ENR_RISAFEN_Pos (14UL) +#define RCC_AHB3ENR_RISAFEN_Msk (0x1UL << RCC_AHB3ENR_RISAFEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENR_RISAFEN RCC_AHB3ENR_RISAFEN_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENR register ******************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0UL) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENR_GPIOBEN_Pos (1UL) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENR_GPIOCEN_Pos (2UL) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENR_GPIODEN_Pos (3UL) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENR_GPIOEEN_Pos (4UL) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENR_GPIOFEN_Pos (5UL) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENR_GPIOGEN_Pos (6UL) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENR_GPIOHEN_Pos (7UL) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENR_GPIONEN_Pos (13UL) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENR_GPIOOEN_Pos (14UL) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENR_GPIOPEN_Pos (15UL) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENR_GPIOQEN_Pos (16UL) +#define RCC_AHB4ENR_GPIOQEN_Msk (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENR_GPIOQEN RCC_AHB4ENR_GPIOQEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENR_PWREN_Pos (18UL) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk /*!< PWR enable */ +#define RCC_AHB4ENR_CRCEN_Pos (19UL) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENR register ******************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0UL) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENR_DMA2DEN_Pos (1UL) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENR_JPEGEN_Pos (3UL) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk /*!< JPEG enable */ +#define RCC_AHB5ENR_FMCEN_Pos (4UL) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk /*!< FMC enable */ +#define RCC_AHB5ENR_XSPI1EN_Pos (5UL) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENR_PSSIEN_Pos (6UL) +#define RCC_AHB5ENR_PSSIEN_Msk (0x1UL << RCC_AHB5ENR_PSSIEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENR_PSSIEN RCC_AHB5ENR_PSSIEN_Msk /*!< PSSI enable */ +#define RCC_AHB5ENR_SDMMC2EN_Pos (7UL) +#define RCC_AHB5ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENR_SDMMC2EN RCC_AHB5ENR_SDMMC2EN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENR_SDMMC1EN_Pos (8UL) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENR_XSPI2EN_Pos (12UL) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENR_XSPIMEN_Pos (13UL) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENR_MCE1EN_Pos (14UL) +#define RCC_AHB5ENR_MCE1EN_Msk (0x1UL << RCC_AHB5ENR_MCE1EN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_MCE1EN RCC_AHB5ENR_MCE1EN_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENR_MCE2EN_Pos (15UL) +#define RCC_AHB5ENR_MCE2EN_Msk (0x1UL << RCC_AHB5ENR_MCE2EN_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENR_MCE2EN RCC_AHB5ENR_MCE2EN_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENR_MCE3EN_Pos (16UL) +#define RCC_AHB5ENR_MCE3EN_Msk (0x1UL << RCC_AHB5ENR_MCE3EN_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENR_MCE3EN RCC_AHB5ENR_MCE3EN_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENR_XSPI3EN_Pos (17UL) +#define RCC_AHB5ENR_XSPI3EN_Msk (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENR_XSPI3EN RCC_AHB5ENR_XSPI3EN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENR_MCE4EN_Pos (18UL) +#define RCC_AHB5ENR_MCE4EN_Msk (0x1UL << RCC_AHB5ENR_MCE4EN_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENR_MCE4EN RCC_AHB5ENR_MCE4EN_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENR_GFXMMUEN_Pos (19UL) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENR_GPU2DEN_Pos (20UL) +#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENR_ETH1MACEN_Pos (22UL) +#define RCC_AHB5ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5ENR_ETH1MACEN RCC_AHB5ENR_ETH1MACEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENR_ETH1TXEN_Pos (23UL) +#define RCC_AHB5ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENR_ETH1TXEN RCC_AHB5ENR_ETH1TXEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENR_ETH1RXEN_Pos (24UL) +#define RCC_AHB5ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENR_ETH1RXEN RCC_AHB5ENR_ETH1RXEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENR_ETH1EN_Pos (25UL) +#define RCC_AHB5ENR_ETH1EN_Msk (0x1UL << RCC_AHB5ENR_ETH1EN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENR_ETH1EN RCC_AHB5ENR_ETH1EN_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENR_OTG1EN_Pos (26UL) +#define RCC_AHB5ENR_OTG1EN_Msk (0x1UL << RCC_AHB5ENR_OTG1EN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENR_OTG1EN RCC_AHB5ENR_OTG1EN_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENR_OTGPHY1EN_Pos (27UL) +#define RCC_AHB5ENR_OTGPHY1EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5ENR_OTGPHY1EN RCC_AHB5ENR_OTGPHY1EN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENR_OTGPHY2EN_Pos (28UL) +#define RCC_AHB5ENR_OTGPHY2EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5ENR_OTGPHY2EN RCC_AHB5ENR_OTGPHY2EN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENR_OTG2EN_Pos (29UL) +#define RCC_AHB5ENR_OTG2EN_Msk (0x1UL << RCC_AHB5ENR_OTG2EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENR_OTG2EN RCC_AHB5ENR_OTG2EN_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENR_CACHEAXIEN_Pos (30UL) +#define RCC_AHB5ENR_CACHEAXIEN_Msk (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENR_CACHEAXIEN RCC_AHB5ENR_CACHEAXIEN_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENR_NPUEN_Pos (31UL) +#define RCC_AHB5ENR_NPUEN_Msk (0x1UL << RCC_AHB5ENR_NPUEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENR_NPUEN RCC_AHB5ENR_NPUEN_Msk /*!< NPU enable */ + +/***************** Bit definition for RCC_APB1ENR1 register *****************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0UL) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk /*!< TIM2 enable */ +#define RCC_APB1ENR1_TIM3EN_Pos (1UL) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk /*!< TIM3 enable */ +#define RCC_APB1ENR1_TIM4EN_Pos (2UL) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk /*!< TIM4 enable */ +#define RCC_APB1ENR1_TIM5EN_Pos (3UL) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk /*!< TIM5 enable */ +#define RCC_APB1ENR1_TIM6EN_Pos (4UL) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk /*!< TIM6 enable */ +#define RCC_APB1ENR1_TIM7EN_Pos (5UL) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk /*!< TIM7 enable */ +#define RCC_APB1ENR1_TIM12EN_Pos (6UL) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk /*!< TIM12 enable */ +#define RCC_APB1ENR1_TIM13EN_Pos (7UL) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk /*!< TIM13 enable */ +#define RCC_APB1ENR1_TIM14EN_Pos (8UL) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk /*!< TIM14 enable */ +#define RCC_APB1ENR1_LPTIM1EN_Pos (9UL) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENR1_WWDGEN_Pos (11UL) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk /*!< WWDG enable */ +#define RCC_APB1ENR1_TIM10EN_Pos (12UL) +#define RCC_APB1ENR1_TIM10EN_Msk (0x1UL << RCC_APB1ENR1_TIM10EN_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENR1_TIM10EN RCC_APB1ENR1_TIM10EN_Msk /*!< TIM10 enable */ +#define RCC_APB1ENR1_TIM11EN_Pos (13UL) +#define RCC_APB1ENR1_TIM11EN_Msk (0x1UL << RCC_APB1ENR1_TIM11EN_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENR1_TIM11EN RCC_APB1ENR1_TIM11EN_Msk /*!< TIM11 enable */ +#define RCC_APB1ENR1_SPI2EN_Pos (14UL) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk /*!< SPI2 enable */ +#define RCC_APB1ENR1_SPI3EN_Pos (15UL) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk /*!< SPI3 enable */ +#define RCC_APB1ENR1_SPDIFRX1EN_Pos (16UL) +#define RCC_APB1ENR1_SPDIFRX1EN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRX1EN RCC_APB1ENR1_SPDIFRX1EN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENR1_USART2EN_Pos (17UL) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk /*!< USART2 enable */ +#define RCC_APB1ENR1_USART3EN_Pos (18UL) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk /*!< USART3 enable */ +#define RCC_APB1ENR1_UART4EN_Pos (19UL) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk /*!< UART4 enable */ +#define RCC_APB1ENR1_UART5EN_Pos (20UL) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk /*!< UART5 enable */ +#define RCC_APB1ENR1_I2C1EN_Pos (21UL) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk /*!< I2C1 enable */ +#define RCC_APB1ENR1_I2C2EN_Pos (22UL) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk /*!< I2C2 enable */ +#define RCC_APB1ENR1_I2C3EN_Pos (23UL) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk /*!< I2C3 enable */ +#define RCC_APB1ENR1_I3C1EN_Pos (24UL) +#define RCC_APB1ENR1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I3C1EN_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENR1_I3C1EN RCC_APB1ENR1_I3C1EN_Msk /*!< I3C1 enable */ +#define RCC_APB1ENR1_I3C2EN_Pos (25UL) +#define RCC_APB1ENR1_I3C2EN_Msk (0x1UL << RCC_APB1ENR1_I3C2EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR1_I3C2EN RCC_APB1ENR1_I3C2EN_Msk /*!< I3C2 enable */ +#define RCC_APB1ENR1_UART7EN_Pos (30UL) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk /*!< UART7 enable */ +#define RCC_APB1ENR1_UART8EN_Pos (31UL) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk /*!< UART8 enable */ + +/***************** Bit definition for RCC_APB1ENR2 register *****************/ +#define RCC_APB1ENR2_MDIOSEN_Pos (5UL) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk /*!< MDIOS enable */ +#define RCC_APB1ENR2_FDCANEN_Pos (8UL) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk /*!< FDCAN enable */ +#define RCC_APB1ENR2_UCPD1EN_Pos (18UL) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENR register ******************/ +#define RCC_APB2ENR_TIM1EN_Pos (0UL) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 enable */ +#define RCC_APB2ENR_TIM8EN_Pos (1UL) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 enable */ +#define RCC_APB2ENR_USART1EN_Pos (4UL) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 enable */ +#define RCC_APB2ENR_USART6EN_Pos (5UL) +#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 enable */ +#define RCC_APB2ENR_UART9EN_Pos (6UL) +#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk /*!< UART9 enable */ +#define RCC_APB2ENR_USART10EN_Pos (7UL) +#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk /*!< USART10 enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12UL) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 enable */ +#define RCC_APB2ENR_SPI4EN_Pos (13UL) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 enable */ +#define RCC_APB2ENR_TIM18EN_Pos (15UL) +#define RCC_APB2ENR_TIM18EN_Msk (0x1UL << RCC_APB2ENR_TIM18EN_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENR_TIM18EN RCC_APB2ENR_TIM18EN_Msk /*!< TIM18 enable */ +#define RCC_APB2ENR_TIM15EN_Pos (16UL) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 enable */ +#define RCC_APB2ENR_TIM16EN_Pos (17UL) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 enable */ +#define RCC_APB2ENR_TIM17EN_Pos (18UL) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 enable */ +#define RCC_APB2ENR_TIM9EN_Pos (19UL) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 enable */ +#define RCC_APB2ENR_SPI5EN_Pos (20UL) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /*!< SPI5 enable */ +#define RCC_APB2ENR_SAI1EN_Pos (21UL) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk /*!< SAI1 enable */ +#define RCC_APB2ENR_SAI2EN_Pos (22UL) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENR register ******************/ +#define RCC_APB3ENR_DFTEN_Pos (2UL) +#define RCC_APB3ENR_DFTEN_Msk (0x1UL << RCC_APB3ENR_DFTEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENR_DFTEN RCC_APB3ENR_DFTEN_Msk /*!< DFT enable */ + +/***************** Bit definition for RCC_APB4ENR1 register *****************/ +#define RCC_APB4ENR1_HDPEN_Pos (2UL) +#define RCC_APB4ENR1_HDPEN_Msk (0x1UL << RCC_APB4ENR1_HDPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR1_HDPEN RCC_APB4ENR1_HDPEN_Msk /*!< HDP enable */ +#define RCC_APB4ENR1_LPUART1EN_Pos (3UL) +#define RCC_APB4ENR1_LPUART1EN_Msk (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR1_LPUART1EN RCC_APB4ENR1_LPUART1EN_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENR1_SPI6EN_Pos (5UL) +#define RCC_APB4ENR1_SPI6EN_Msk (0x1UL << RCC_APB4ENR1_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR1_SPI6EN RCC_APB4ENR1_SPI6EN_Msk /*!< SPI6 enable */ +#define RCC_APB4ENR1_I2C4EN_Pos (7UL) +#define RCC_APB4ENR1_I2C4EN_Msk (0x1UL << RCC_APB4ENR1_I2C4EN_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENR1_I2C4EN RCC_APB4ENR1_I2C4EN_Msk /*!< I2C4 enable */ +#define RCC_APB4ENR1_LPTIM2EN_Pos (9UL) +#define RCC_APB4ENR1_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR1_LPTIM2EN RCC_APB4ENR1_LPTIM2EN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENR1_LPTIM3EN_Pos (10UL) +#define RCC_APB4ENR1_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR1_LPTIM3EN RCC_APB4ENR1_LPTIM3EN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENR1_LPTIM4EN_Pos (11UL) +#define RCC_APB4ENR1_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR1_LPTIM4EN RCC_APB4ENR1_LPTIM4EN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENR1_LPTIM5EN_Pos (12UL) +#define RCC_APB4ENR1_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR1_LPTIM5EN RCC_APB4ENR1_LPTIM5EN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENR1_VREFBUFEN_Pos (15UL) +#define RCC_APB4ENR1_VREFBUFEN_Msk (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR1_VREFBUFEN RCC_APB4ENR1_VREFBUFEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENR1_RTCEN_Pos (16UL) +#define RCC_APB4ENR1_RTCEN_Msk (0x1UL << RCC_APB4ENR1_RTCEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR1_RTCEN RCC_APB4ENR1_RTCEN_Msk /*!< RTC enable */ +#define RCC_APB4ENR1_RTCAPBEN_Pos (17UL) +#define RCC_APB4ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4ENR1_RTCAPBEN RCC_APB4ENR1_RTCAPBEN_Msk /*!< RTCAPB enable */ + +/***************** Bit definition for RCC_APB4ENR2 register *****************/ +#define RCC_APB4ENR2_SYSCFGEN_Pos (0UL) +#define RCC_APB4ENR2_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4ENR2_SYSCFGEN RCC_APB4ENR2_SYSCFGEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENR2_BSECEN_Pos (1UL) +#define RCC_APB4ENR2_BSECEN_Msk (0x1UL << RCC_APB4ENR2_BSECEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR2_BSECEN RCC_APB4ENR2_BSECEN_Msk /*!< BSEC enable */ +#define RCC_APB4ENR2_DTSEN_Pos (2UL) +#define RCC_APB4ENR2_DTSEN_Msk (0x1UL << RCC_APB4ENR2_DTSEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENR2_DTSEN RCC_APB4ENR2_DTSEN_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENR register ******************/ +#define RCC_APB5ENR_LTDCEN_Pos (1UL) +#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk /*!< LTDC enable */ +#define RCC_APB5ENR_DCMIPPEN_Pos (2UL) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENR_GFXTIMEN_Pos (4UL) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENR_VENCEN_Pos (5UL) +#define RCC_APB5ENR_VENCEN_Msk (0x1UL << RCC_APB5ENR_VENCEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENR_VENCEN RCC_APB5ENR_VENCEN_Msk /*!< VENC enable */ +#define RCC_APB5ENR_CSIEN_Pos (6UL) +#define RCC_APB5ENR_CSIEN_Msk (0x1UL << RCC_APB5ENR_CSIEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENR_CSIEN RCC_APB5ENR_CSIEN_Msk /*!< CSI enable */ + +/***************** Bit definition for RCC_BUSLPENR register *****************/ +#define RCC_BUSLPENR_ACLKNLPEN_Pos (0UL) +#define RCC_BUSLPENR_ACLKNLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENR_ACLKNLPEN RCC_BUSLPENR_ACLKNLPEN_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENR_ACLKNCLPEN_Pos (1UL) +#define RCC_BUSLPENR_ACLKNCLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */ +#define RCC_BUSLPENR_ACLKNCLPEN RCC_BUSLPENR_ACLKNCLPEN_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENR register *****************/ +#define RCC_MISCLPENR_DBGLPEN_Pos (0UL) +#define RCC_MISCLPENR_DBGLPEN_Msk (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MISCLPENR_DBGLPEN RCC_MISCLPENR_DBGLPEN_Msk /*!< DBG enable */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos (3UL) +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENR_XSPIPHYCOMPLPEN RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENR_PERLPEN_Pos (6UL) +#define RCC_MISCLPENR_PERLPEN_Msk (0x1UL << RCC_MISCLPENR_PERLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MISCLPENR_PERLPEN RCC_MISCLPENR_PERLPEN_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMLPENR register *****************/ +#define RCC_MEMLPENR_AXISRAM3LPEN_Pos (0UL) +#define RCC_MEMLPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENR_AXISRAM3LPEN RCC_MEMLPENR_AXISRAM3LPEN_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENR_AXISRAM4LPEN_Pos (1UL) +#define RCC_MEMLPENR_AXISRAM4LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENR_AXISRAM4LPEN RCC_MEMLPENR_AXISRAM4LPEN_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENR_AXISRAM5LPEN_Pos (2UL) +#define RCC_MEMLPENR_AXISRAM5LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENR_AXISRAM5LPEN RCC_MEMLPENR_AXISRAM5LPEN_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENR_AXISRAM6LPEN_Pos (3UL) +#define RCC_MEMLPENR_AXISRAM6LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENR_AXISRAM6LPEN RCC_MEMLPENR_AXISRAM6LPEN_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos (4UL) +#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENR_AHBSRAM1LPEN RCC_MEMLPENR_AHBSRAM1LPEN_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos (5UL) +#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENR_AHBSRAM2LPEN RCC_MEMLPENR_AHBSRAM2LPEN_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENR_BKPSRAMLPEN_Pos (6UL) +#define RCC_MEMLPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENR_BKPSRAMLPEN RCC_MEMLPENR_BKPSRAMLPEN_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENR_AXISRAM1LPEN_Pos (7UL) +#define RCC_MEMLPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENR_AXISRAM1LPEN RCC_MEMLPENR_AXISRAM1LPEN_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENR_AXISRAM2LPEN_Pos (8UL) +#define RCC_MEMLPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENR_AXISRAM2LPEN RCC_MEMLPENR_AXISRAM2LPEN_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENR_FLEXRAMLPEN_Pos (9UL) +#define RCC_MEMLPENR_FLEXRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENR_FLEXRAMLPEN RCC_MEMLPENR_FLEXRAMLPEN_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos (10UL) +#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENR_CACHEAXIRAMLPEN RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMLPENR_VENCRAMLPEN_Pos (11UL) +#define RCC_MEMLPENR_VENCRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENR_VENCRAMLPEN RCC_MEMLPENR_VENCRAMLPEN_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENR_BOOTROMLPEN_Pos (12UL) +#define RCC_MEMLPENR_BOOTROMLPEN_Msk (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENR_BOOTROMLPEN RCC_MEMLPENR_BOOTROMLPEN_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENR register *****************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4UL) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5UL) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENR register *****************/ +#define RCC_AHB2LPENR_RAMCFGLPEN_Pos (12UL) +#define RCC_AHB2LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENR_RAMCFGLPEN RCC_AHB2LPENR_RAMCFGLPEN_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENR_MDF1LPEN_Pos (16UL) +#define RCC_AHB2LPENR_MDF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENR_MDF1LPEN RCC_AHB2LPENR_MDF1LPEN_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENR_ADF1LPEN_Pos (17UL) +#define RCC_AHB2LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENR_ADF1LPEN RCC_AHB2LPENR_ADF1LPEN_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENR register *****************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0UL) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk /*!< RNG enable */ +#define RCC_AHB3LPENR_HASHLPEN_Pos (1UL) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk /*!< HASH enable */ +#define RCC_AHB3LPENR_CRYPLPEN_Pos (2UL) +#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk /*!< CRYP enable */ +#define RCC_AHB3LPENR_SAESLPEN_Pos (4UL) +#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk /*!< SAES enable */ +#define RCC_AHB3LPENR_PKALPEN_Pos (8UL) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk /*!< PKA enable */ +#define RCC_AHB3LPENR_RIFSCLPEN_Pos (9UL) +#define RCC_AHB3LPENR_RIFSCLPEN_Msk (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */ +#define RCC_AHB3LPENR_RIFSCLPEN RCC_AHB3LPENR_RIFSCLPEN_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENR_IACLPEN_Pos (10UL) +#define RCC_AHB3LPENR_IACLPEN_Msk (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_AHB3LPENR_IACLPEN RCC_AHB3LPENR_IACLPEN_Msk /*!< IAC enable */ +#define RCC_AHB3LPENR_RISAFLPEN_Pos (14UL) +#define RCC_AHB3LPENR_RISAFLPEN_Msk (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB3LPENR_RISAFLPEN RCC_AHB3LPENR_RISAFLPEN_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENR register *****************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0UL) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1UL) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2UL) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3UL) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4UL) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5UL) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6UL) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7UL) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13UL) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14UL) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15UL) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENR_GPIOQLPEN_Pos (16UL) +#define RCC_AHB4LPENR_GPIOQLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */ +#define RCC_AHB4LPENR_GPIOQLPEN RCC_AHB4LPENR_GPIOQLPEN_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENR_PWRLPEN_Pos (18UL) +#define RCC_AHB4LPENR_PWRLPEN_Msk (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB4LPENR_PWRLPEN RCC_AHB4LPENR_PWRLPEN_Msk /*!< PWR enable */ +#define RCC_AHB4LPENR_CRCLPEN_Pos (19UL) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENR register *****************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0UL) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1UL) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3UL) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENR_FMCLPEN_Pos (4UL) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk /*!< FMC enable */ +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5UL) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENR_PSSILPEN_Pos (6UL) +#define RCC_AHB5LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENR_PSSILPEN RCC_AHB5LPENR_PSSILPEN_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENR_SDMMC2LPEN_Pos (7UL) +#define RCC_AHB5LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENR_SDMMC2LPEN RCC_AHB5LPENR_SDMMC2LPEN_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8UL) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12UL) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (13UL) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENR_MCE1LPEN_Pos (14UL) +#define RCC_AHB5LPENR_MCE1LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_MCE1LPEN RCC_AHB5LPENR_MCE1LPEN_Msk /*!< MCE1 enable */ +#define RCC_AHB5LPENR_MCE2LPEN_Pos (15UL) +#define RCC_AHB5LPENR_MCE2LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENR_MCE2LPEN RCC_AHB5LPENR_MCE2LPEN_Msk /*!< MCE2 enable */ +#define RCC_AHB5LPENR_MCE3LPEN_Pos (16UL) +#define RCC_AHB5LPENR_MCE3LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENR_MCE3LPEN RCC_AHB5LPENR_MCE3LPEN_Msk /*!< MCE3 enable */ +#define RCC_AHB5LPENR_XSPI3LPEN_Pos (17UL) +#define RCC_AHB5LPENR_XSPI3LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */ +#define RCC_AHB5LPENR_XSPI3LPEN RCC_AHB5LPENR_XSPI3LPEN_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENR_MCE4LPEN_Pos (18UL) +#define RCC_AHB5LPENR_MCE4LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENR_MCE4LPEN RCC_AHB5LPENR_MCE4LPEN_Msk /*!< MCE4 enable */ +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19UL) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20UL) +#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */ +#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENR_ETH1MACLPEN_Pos (22UL) +#define RCC_AHB5LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENR_ETH1MACLPEN RCC_AHB5LPENR_ETH1MACLPEN_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENR_ETH1TXLPEN_Pos (23UL) +#define RCC_AHB5LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENR_ETH1TXLPEN RCC_AHB5LPENR_ETH1TXLPEN_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENR_ETH1RXLPEN_Pos (24UL) +#define RCC_AHB5LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENR_ETH1RXLPEN RCC_AHB5LPENR_ETH1RXLPEN_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENR_ETH1LPEN_Pos (25UL) +#define RCC_AHB5LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENR_ETH1LPEN RCC_AHB5LPENR_ETH1LPEN_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENR_OTG1LPEN_Pos (26UL) +#define RCC_AHB5LPENR_OTG1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENR_OTG1LPEN RCC_AHB5LPENR_OTG1LPEN_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos (27UL) +#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENR_OTGPHY1LPEN RCC_AHB5LPENR_OTGPHY1LPEN_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos (28UL) +#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_OTGPHY2LPEN RCC_AHB5LPENR_OTGPHY2LPEN_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENR_OTG2LPEN_Pos (29UL) +#define RCC_AHB5LPENR_OTG2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_OTG2LPEN RCC_AHB5LPENR_OTG2LPEN_Msk /*!< OTG2 enable */ +#define RCC_AHB5LPENR_CACHEAXILPEN_Pos (30UL) +#define RCC_AHB5LPENR_CACHEAXILPEN_Msk (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_CACHEAXILPEN RCC_AHB5LPENR_CACHEAXILPEN_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5LPENR_NPULPEN_Pos (31UL) +#define RCC_AHB5LPENR_NPULPEN_Msk (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_NPULPEN RCC_AHB5LPENR_NPULPEN_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1LPENR1 register ****************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0UL) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1UL) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2UL) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3UL) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4UL) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5UL) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6UL) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7UL) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8UL) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9UL) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11UL) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk /*!< WWDG enable */ +#define RCC_APB1LPENR1_TIM10LPEN_Pos (12UL) +#define RCC_APB1LPENR1_TIM10LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENR1_TIM10LPEN RCC_APB1LPENR1_TIM10LPEN_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENR1_TIM11LPEN_Pos (13UL) +#define RCC_APB1LPENR1_TIM11LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENR1_TIM11LPEN RCC_APB1LPENR1_TIM11LPEN_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14UL) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15UL) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos (16UL) +#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRX1LPEN RCC_APB1LPENR1_SPDIFRX1LPEN_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENR1_USART2LPEN_Pos (17UL) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk /*!< USART2 enable */ +#define RCC_APB1LPENR1_USART3LPEN_Pos (18UL) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk /*!< USART3 enable */ +#define RCC_APB1LPENR1_UART4LPEN_Pos (19UL) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk /*!< UART4 enable */ +#define RCC_APB1LPENR1_UART5LPEN_Pos (20UL) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk /*!< UART5 enable */ +#define RCC_APB1LPENR1_I2C1LPEN_Pos (21UL) +#define RCC_APB1LPENR1_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1LPEN RCC_APB1LPENR1_I2C1LPEN_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22UL) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23UL) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENR1_I3C1LPEN_Pos (24UL) +#define RCC_APB1LPENR1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */ +#define RCC_APB1LPENR1_I3C1LPEN RCC_APB1LPENR1_I3C1LPEN_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENR1_I3C2LPEN_Pos (25UL) +#define RCC_APB1LPENR1_I3C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */ +#define RCC_APB1LPENR1_I3C2LPEN RCC_APB1LPENR1_I3C2LPEN_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENR1_UART7LPEN_Pos (30UL) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk /*!< UART7 enable */ +#define RCC_APB1LPENR1_UART8LPEN_Pos (31UL) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1LPENR2 register ****************/ +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5UL) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk /*!< MDIOS enable in Sleep mode */ +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8UL) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk /*!< FDCAN enablein Sleep mode */ +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (18UL) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk /*!< UCPD1 enable in Sleep mode */ + +/**************** Bit definition for RCC_APB2LPENR register *****************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0UL) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENR_TIM8LPEN_Pos (1UL) +#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENR_USART1LPEN_Pos (4UL) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 enable */ +#define RCC_APB2LPENR_USART6LPEN_Pos (5UL) +#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk /*!< USART6 enable */ +#define RCC_APB2LPENR_UART9LPEN_Pos (6UL) +#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */ +#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk /*!< UART9 enable */ +#define RCC_APB2LPENR_USART10LPEN_Pos (7UL) +#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk /*!< USART10 enable */ +#define RCC_APB2LPENR_SPI1LPEN_Pos (12UL) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENR_SPI4LPEN_Pos (13UL) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENR_TIM18LPEN_Pos (15UL) +#define RCC_APB2LPENR_TIM18LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */ +#define RCC_APB2LPENR_TIM18LPEN RCC_APB2LPENR_TIM18LPEN_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENR_TIM15LPEN_Pos (16UL) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENR_TIM16LPEN_Pos (17UL) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENR_TIM17LPEN_Pos (18UL) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENR_TIM9LPEN_Pos (19UL) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENR_SPI5LPEN_Pos (20UL) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENR_SAI1LPEN_Pos (21UL) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENR_SAI2LPEN_Pos (22UL) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENR register *****************/ +#define RCC_APB3LPENR_DFTLPEN_Pos (2UL) +#define RCC_APB3LPENR_DFTLPEN_Msk (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB3LPENR_DFTLPEN RCC_APB3LPENR_DFTLPEN_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4LPENR1 register ****************/ +#define RCC_APB4LPENR1_HDPLPEN_Pos (2UL) +#define RCC_APB4LPENR1_HDPLPEN_Msk (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR1_HDPLPEN RCC_APB4LPENR1_HDPLPEN_Msk /*!< HDP enable */ +#define RCC_APB4LPENR1_LPUART1LPEN_Pos (3UL) +#define RCC_APB4LPENR1_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENR1_LPUART1LPEN RCC_APB4LPENR1_LPUART1LPEN_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENR1_SPI6LPEN_Pos (5UL) +#define RCC_APB4LPENR1_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */ +#define RCC_APB4LPENR1_SPI6LPEN RCC_APB4LPENR1_SPI6LPEN_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENR1_I2C4LPEN_Pos (7UL) +#define RCC_APB4LPENR1_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */ +#define RCC_APB4LPENR1_I2C4LPEN RCC_APB4LPENR1_I2C4LPEN_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENR1_LPTIM2LPEN_Pos (9UL) +#define RCC_APB4LPENR1_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR1_LPTIM2LPEN RCC_APB4LPENR1_LPTIM2LPEN_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENR1_LPTIM3LPEN_Pos (10UL) +#define RCC_APB4LPENR1_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR1_LPTIM3LPEN RCC_APB4LPENR1_LPTIM3LPEN_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENR1_LPTIM4LPEN_Pos (11UL) +#define RCC_APB4LPENR1_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR1_LPTIM4LPEN RCC_APB4LPENR1_LPTIM4LPEN_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENR1_LPTIM5LPEN_Pos (12UL) +#define RCC_APB4LPENR1_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR1_LPTIM5LPEN RCC_APB4LPENR1_LPTIM5LPEN_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENR1_VREFBUFLPEN_Pos (15UL) +#define RCC_APB4LPENR1_VREFBUFLPEN_Msk (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR1_VREFBUFLPEN RCC_APB4LPENR1_VREFBUFLPEN_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENR1_RTCLPEN_Pos (16UL) +#define RCC_APB4LPENR1_RTCLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR1_RTCLPEN RCC_APB4LPENR1_RTCLPEN_Msk /*!< RTC enable */ +#define RCC_APB4LPENR1_RTCAPBLPEN_Pos (17UL) +#define RCC_APB4LPENR1_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENR1_RTCAPBLPEN RCC_APB4LPENR1_RTCAPBLPEN_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4LPENR2 register ****************/ +#define RCC_APB4LPENR2_SYSCFGLPEN_Pos (0UL) +#define RCC_APB4LPENR2_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENR2_SYSCFGLPEN RCC_APB4LPENR2_SYSCFGLPEN_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENR2_BSECLPEN_Pos (1UL) +#define RCC_APB4LPENR2_BSECLPEN_Msk (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */ +#define RCC_APB4LPENR2_BSECLPEN RCC_APB4LPENR2_BSECLPEN_Msk /*!< BSEC enable */ +#define RCC_APB4LPENR2_DTSLPEN_Pos (2UL) +#define RCC_APB4LPENR2_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENR2_DTSLPEN RCC_APB4LPENR2_DTSLPEN_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENR register *****************/ +#define RCC_APB5LPENR_LTDCLPEN_Pos (1UL) +#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk /*!< LTDC enable */ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2UL) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4UL) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENR_VENCLPEN_Pos (5UL) +#define RCC_APB5LPENR_VENCLPEN_Msk (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENR_VENCLPEN RCC_APB5LPENR_VENCLPEN_Msk /*!< VENC enable */ +#define RCC_APB5LPENR_CSILPEN_Pos (6UL) +#define RCC_APB5LPENR_CSILPEN_Msk (0x1UL << RCC_APB5LPENR_CSILPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB5LPENR_CSILPEN RCC_APB5LPENR_CSILPEN_Msk /*!< CSI enable */ + +/******************* Bit definition for RCC_RDCR register *******************/ +#define RCC_RDCR_MRD_Pos (16UL) +#define RCC_RDCR_MRD_Msk (0x1FUL << RCC_RDCR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDCR_MRD RCC_RDCR_MRD_Msk /*!< Minimum reset duration */ + +/***************** Bit definition for RCC_SECCFGR0 register *****************/ +#define RCC_SECCFGR0_LSISEC_Pos (0UL) +#define RCC_SECCFGR0_LSISEC_Msk (0x1UL << RCC_SECCFGR0_LSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR0_LSISEC RCC_SECCFGR0_LSISEC_Msk /*!< Secure protection of LSI oscillator configuration bits */ +#define RCC_SECCFGR0_LSESEC_Pos (1UL) +#define RCC_SECCFGR0_LSESEC_Msk (0x1UL << RCC_SECCFGR0_LSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR0_LSESEC RCC_SECCFGR0_LSESEC_Msk /*!< Secure protection of LSE oscillator configuration bits */ +#define RCC_SECCFGR0_MSISEC_Pos (2UL) +#define RCC_SECCFGR0_MSISEC_Msk (0x1UL << RCC_SECCFGR0_MSISEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR0_MSISEC RCC_SECCFGR0_MSISEC_Msk /*!< Secure protection of MSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSISEC_Pos (3UL) +#define RCC_SECCFGR0_HSISEC_Msk (0x1UL << RCC_SECCFGR0_HSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR0_HSISEC RCC_SECCFGR0_HSISEC_Msk /*!< Secure protection of HSI oscillator configuration bits */ +#define RCC_SECCFGR0_HSESEC_Pos (4UL) +#define RCC_SECCFGR0_HSESEC_Msk (0x1UL << RCC_SECCFGR0_HSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR0_HSESEC RCC_SECCFGR0_HSESEC_Msk /*!< Secure protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR0 register *****************/ +#define RCC_PRIVCFGR0_LSIPRIV_Pos (0UL) +#define RCC_PRIVCFGR0_LSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR0_LSIPRIV RCC_PRIVCFGR0_LSIPRIV_Msk /*!< Privileged protection of LSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_LSEPRIV_Pos (1UL) +#define RCC_PRIVCFGR0_LSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR0_LSEPRIV RCC_PRIVCFGR0_LSEPRIV_Msk /*!< Privileged protection of LSE oscillator configuration bits */ +#define RCC_PRIVCFGR0_MSIPRIV_Pos (2UL) +#define RCC_PRIVCFGR0_MSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR0_MSIPRIV RCC_PRIVCFGR0_MSIPRIV_Msk /*!< Privileged protection of MSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSIPRIV_Pos (3UL) +#define RCC_PRIVCFGR0_HSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR0_HSIPRIV RCC_PRIVCFGR0_HSIPRIV_Msk /*!< Privileged protection of HSI oscillator configuration bits */ +#define RCC_PRIVCFGR0_HSEPRIV_Pos (4UL) +#define RCC_PRIVCFGR0_HSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR0_HSEPRIV RCC_PRIVCFGR0_HSEPRIV_Msk /*!< Privileged protection of HSE oscillator configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR0 register *****************/ +#define RCC_LOCKCFGR0_LSILOCK_Pos (0UL) +#define RCC_LOCKCFGR0_LSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR0_LSILOCK RCC_LOCKCFGR0_LSILOCK_Msk /*!< Locked protection of LSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_LSELOCK_Pos (1UL) +#define RCC_LOCKCFGR0_LSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR0_LSELOCK RCC_LOCKCFGR0_LSELOCK_Msk /*!< Locked protection of LSE oscillator configuration bits */ +#define RCC_LOCKCFGR0_MSILOCK_Pos (2UL) +#define RCC_LOCKCFGR0_MSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR0_MSILOCK RCC_LOCKCFGR0_MSILOCK_Msk /*!< Locked protection of MSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSILOCK_Pos (3UL) +#define RCC_LOCKCFGR0_HSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR0_HSILOCK RCC_LOCKCFGR0_HSILOCK_Msk /*!< Locked protection of HSI oscillator configuration bits */ +#define RCC_LOCKCFGR0_HSELOCK_Pos (4UL) +#define RCC_LOCKCFGR0_HSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR0_HSELOCK RCC_LOCKCFGR0_HSELOCK_Msk /*!< Locked protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR0 register *****************/ +#define RCC_PUBCFGR0_LSIPUB_Pos (0UL) +#define RCC_PUBCFGR0_LSIPUB_Msk (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR0_LSIPUB RCC_PUBCFGR0_LSIPUB_Msk /*!< Public protection of LSI oscillator configuration bits */ +#define RCC_PUBCFGR0_LSEPUB_Pos (1UL) +#define RCC_PUBCFGR0_LSEPUB_Msk (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR0_LSEPUB RCC_PUBCFGR0_LSEPUB_Msk /*!< Public protection of LSE oscillator configuration bits */ +#define RCC_PUBCFGR0_MSIPUB_Pos (2UL) +#define RCC_PUBCFGR0_MSIPUB_Msk (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR0_MSIPUB RCC_PUBCFGR0_MSIPUB_Msk /*!< Public protection of MSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSIPUB_Pos (3UL) +#define RCC_PUBCFGR0_HSIPUB_Msk (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR0_HSIPUB RCC_PUBCFGR0_HSIPUB_Msk /*!< Public protection of HSI oscillator configuration bits */ +#define RCC_PUBCFGR0_HSEPUB_Pos (4UL) +#define RCC_PUBCFGR0_HSEPUB_Msk (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR0_HSEPUB RCC_PUBCFGR0_HSEPUB_Msk /*!< Public protection of HSE oscillator configuration bits */ + +/***************** Bit definition for RCC_SECCFGR1 register *****************/ +#define RCC_SECCFGR1_PLL1SEC_Pos (0UL) +#define RCC_SECCFGR1_PLL1SEC_Msk (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR1_PLL1SEC RCC_SECCFGR1_PLL1SEC_Msk /*!< Secure protection of PLL1 configuration bits */ +#define RCC_SECCFGR1_PLL2SEC_Pos (1UL) +#define RCC_SECCFGR1_PLL2SEC_Msk (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR1_PLL2SEC RCC_SECCFGR1_PLL2SEC_Msk /*!< Secure protection of PLL2 configuration bits */ +#define RCC_SECCFGR1_PLL3SEC_Pos (2UL) +#define RCC_SECCFGR1_PLL3SEC_Msk (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR1_PLL3SEC RCC_SECCFGR1_PLL3SEC_Msk /*!< Secure protection of PLL3 configuration bits */ +#define RCC_SECCFGR1_PLL4SEC_Pos (3UL) +#define RCC_SECCFGR1_PLL4SEC_Msk (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR1_PLL4SEC RCC_SECCFGR1_PLL4SEC_Msk /*!< Secure protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR1 register *****************/ +#define RCC_PRIVCFGR1_PLL1PRIV_Pos (0UL) +#define RCC_PRIVCFGR1_PLL1PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR1_PLL1PRIV RCC_PRIVCFGR1_PLL1PRIV_Msk /*!< Privileged protection of PLL1 configuration bits */ +#define RCC_PRIVCFGR1_PLL2PRIV_Pos (1UL) +#define RCC_PRIVCFGR1_PLL2PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR1_PLL2PRIV RCC_PRIVCFGR1_PLL2PRIV_Msk /*!< Privileged protection of PLL2 configuration bits */ +#define RCC_PRIVCFGR1_PLL3PRIV_Pos (2UL) +#define RCC_PRIVCFGR1_PLL3PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR1_PLL3PRIV RCC_PRIVCFGR1_PLL3PRIV_Msk /*!< Privileged protection of PLL3 configuration bits */ +#define RCC_PRIVCFGR1_PLL4PRIV_Pos (3UL) +#define RCC_PRIVCFGR1_PLL4PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR1_PLL4PRIV RCC_PRIVCFGR1_PLL4PRIV_Msk /*!< Privileged protection of PLL4 configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR1 register *****************/ +#define RCC_LOCKCFGR1_PLL1LOCK_Pos (0UL) +#define RCC_LOCKCFGR1_PLL1LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR1_PLL1LOCK RCC_LOCKCFGR1_PLL1LOCK_Msk /*!< Locked protection of PLL1 configuration bits */ +#define RCC_LOCKCFGR1_PLL2LOCK_Pos (1UL) +#define RCC_LOCKCFGR1_PLL2LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR1_PLL2LOCK RCC_LOCKCFGR1_PLL2LOCK_Msk /*!< Locked protection of PLL2 configuration bits */ +#define RCC_LOCKCFGR1_PLL3LOCK_Pos (2UL) +#define RCC_LOCKCFGR1_PLL3LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR1_PLL3LOCK RCC_LOCKCFGR1_PLL3LOCK_Msk /*!< Locked protection of PLL3 configuration bits */ +#define RCC_LOCKCFGR1_PLL4LOCK_Pos (3UL) +#define RCC_LOCKCFGR1_PLL4LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR1_PLL4LOCK RCC_LOCKCFGR1_PLL4LOCK_Msk /*!< Locked protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR1 register *****************/ +#define RCC_PUBCFGR1_PLL1PUB_Pos (0UL) +#define RCC_PUBCFGR1_PLL1PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR1_PLL1PUB RCC_PUBCFGR1_PLL1PUB_Msk /*!< Public protection of PLL1 configuration bits */ +#define RCC_PUBCFGR1_PLL2PUB_Pos (1UL) +#define RCC_PUBCFGR1_PLL2PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR1_PLL2PUB RCC_PUBCFGR1_PLL2PUB_Msk /*!< Public protection of PLL2 configuration bits */ +#define RCC_PUBCFGR1_PLL3PUB_Pos (2UL) +#define RCC_PUBCFGR1_PLL3PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR1_PLL3PUB RCC_PUBCFGR1_PLL3PUB_Msk /*!< Public protection of PLL3 configuration bits */ +#define RCC_PUBCFGR1_PLL4PUB_Pos (3UL) +#define RCC_PUBCFGR1_PLL4PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR1_PLL4PUB RCC_PUBCFGR1_PLL4PUB_Msk /*!< Public protection of PLL4 configuration bits */ + +/***************** Bit definition for RCC_SECCFGR2 register *****************/ +#define RCC_SECCFGR2_IC1SEC_Pos (0UL) +#define RCC_SECCFGR2_IC1SEC_Msk (0x1UL << RCC_SECCFGR2_IC1SEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR2_IC1SEC RCC_SECCFGR2_IC1SEC_Msk /*!< Secure protection of IC1 divider configuration bits */ +#define RCC_SECCFGR2_IC2SEC_Pos (1UL) +#define RCC_SECCFGR2_IC2SEC_Msk (0x1UL << RCC_SECCFGR2_IC2SEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR2_IC2SEC RCC_SECCFGR2_IC2SEC_Msk /*!< Secure protection of IC2 divider configuration bits */ +#define RCC_SECCFGR2_IC3SEC_Pos (2UL) +#define RCC_SECCFGR2_IC3SEC_Msk (0x1UL << RCC_SECCFGR2_IC3SEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR2_IC3SEC RCC_SECCFGR2_IC3SEC_Msk /*!< Secure protection of IC3 divider configuration bits */ +#define RCC_SECCFGR2_IC4SEC_Pos (3UL) +#define RCC_SECCFGR2_IC4SEC_Msk (0x1UL << RCC_SECCFGR2_IC4SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR2_IC4SEC RCC_SECCFGR2_IC4SEC_Msk /*!< Secure protection of IC4 divider configuration bits */ +#define RCC_SECCFGR2_IC5SEC_Pos (4UL) +#define RCC_SECCFGR2_IC5SEC_Msk (0x1UL << RCC_SECCFGR2_IC5SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR2_IC5SEC RCC_SECCFGR2_IC5SEC_Msk /*!< Secure protection of IC5 divider configuration bits */ +#define RCC_SECCFGR2_IC6SEC_Pos (5UL) +#define RCC_SECCFGR2_IC6SEC_Msk (0x1UL << RCC_SECCFGR2_IC6SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR2_IC6SEC RCC_SECCFGR2_IC6SEC_Msk /*!< Secure protection of IC6 divider configuration bits */ +#define RCC_SECCFGR2_IC7SEC_Pos (6UL) +#define RCC_SECCFGR2_IC7SEC_Msk (0x1UL << RCC_SECCFGR2_IC7SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR2_IC7SEC RCC_SECCFGR2_IC7SEC_Msk /*!< Secure protection of IC7 divider configuration bits */ +#define RCC_SECCFGR2_IC8SEC_Pos (7UL) +#define RCC_SECCFGR2_IC8SEC_Msk (0x1UL << RCC_SECCFGR2_IC8SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR2_IC8SEC RCC_SECCFGR2_IC8SEC_Msk /*!< Secure protection of IC8 divider configuration bits */ +#define RCC_SECCFGR2_IC9SEC_Pos (8UL) +#define RCC_SECCFGR2_IC9SEC_Msk (0x1UL << RCC_SECCFGR2_IC9SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR2_IC9SEC RCC_SECCFGR2_IC9SEC_Msk /*!< Secure protection of IC9 divider configuration bits */ +#define RCC_SECCFGR2_IC10SEC_Pos (9UL) +#define RCC_SECCFGR2_IC10SEC_Msk (0x1UL << RCC_SECCFGR2_IC10SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR2_IC10SEC RCC_SECCFGR2_IC10SEC_Msk /*!< Secure protection of IC10 divider configuration bits */ +#define RCC_SECCFGR2_IC11SEC_Pos (10UL) +#define RCC_SECCFGR2_IC11SEC_Msk (0x1UL << RCC_SECCFGR2_IC11SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR2_IC11SEC RCC_SECCFGR2_IC11SEC_Msk /*!< Secure protection of IC11 divider configuration bits */ +#define RCC_SECCFGR2_IC12SEC_Pos (11UL) +#define RCC_SECCFGR2_IC12SEC_Msk (0x1UL << RCC_SECCFGR2_IC12SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR2_IC12SEC RCC_SECCFGR2_IC12SEC_Msk /*!< Secure protection of IC12 divider configuration bits */ +#define RCC_SECCFGR2_IC13SEC_Pos (12UL) +#define RCC_SECCFGR2_IC13SEC_Msk (0x1UL << RCC_SECCFGR2_IC13SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR2_IC13SEC RCC_SECCFGR2_IC13SEC_Msk /*!< Secure protection of IC13 divider configuration bits */ +#define RCC_SECCFGR2_IC14SEC_Pos (13UL) +#define RCC_SECCFGR2_IC14SEC_Msk (0x1UL << RCC_SECCFGR2_IC14SEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR2_IC14SEC RCC_SECCFGR2_IC14SEC_Msk /*!< Secure protection of IC14 divider configuration bits */ +#define RCC_SECCFGR2_IC15SEC_Pos (14UL) +#define RCC_SECCFGR2_IC15SEC_Msk (0x1UL << RCC_SECCFGR2_IC15SEC_Pos) /*!< 0x00004000 */ +#define RCC_SECCFGR2_IC15SEC RCC_SECCFGR2_IC15SEC_Msk /*!< Secure protection of IC15 divider configuration bits */ +#define RCC_SECCFGR2_IC16SEC_Pos (15UL) +#define RCC_SECCFGR2_IC16SEC_Msk (0x1UL << RCC_SECCFGR2_IC16SEC_Pos) /*!< 0x00008000 */ +#define RCC_SECCFGR2_IC16SEC RCC_SECCFGR2_IC16SEC_Msk /*!< Secure protection of IC16 divider configuration bits */ +#define RCC_SECCFGR2_IC17SEC_Pos (16UL) +#define RCC_SECCFGR2_IC17SEC_Msk (0x1UL << RCC_SECCFGR2_IC17SEC_Pos) /*!< 0x00010000 */ +#define RCC_SECCFGR2_IC17SEC RCC_SECCFGR2_IC17SEC_Msk /*!< Secure protection of IC17 divider configuration bits */ +#define RCC_SECCFGR2_IC18SEC_Pos (17UL) +#define RCC_SECCFGR2_IC18SEC_Msk (0x1UL << RCC_SECCFGR2_IC18SEC_Pos) /*!< 0x00020000 */ +#define RCC_SECCFGR2_IC18SEC RCC_SECCFGR2_IC18SEC_Msk /*!< Secure protection of IC18 divider configuration bits */ +#define RCC_SECCFGR2_IC19SEC_Pos (18UL) +#define RCC_SECCFGR2_IC19SEC_Msk (0x1UL << RCC_SECCFGR2_IC19SEC_Pos) /*!< 0x00040000 */ +#define RCC_SECCFGR2_IC19SEC RCC_SECCFGR2_IC19SEC_Msk /*!< Secure protection of IC19 divider configuration bits */ +#define RCC_SECCFGR2_IC20SEC_Pos (19UL) +#define RCC_SECCFGR2_IC20SEC_Msk (0x1UL << RCC_SECCFGR2_IC20SEC_Pos) /*!< 0x00080000 */ +#define RCC_SECCFGR2_IC20SEC RCC_SECCFGR2_IC20SEC_Msk /*!< Secure protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR2 register *****************/ +#define RCC_PRIVCFGR2_IC1PRIV_Pos (0UL) +#define RCC_PRIVCFGR2_IC1PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR2_IC1PRIV RCC_PRIVCFGR2_IC1PRIV_Msk /*!< Privileged protection of IC1 divider configuration bits */ +#define RCC_PRIVCFGR2_IC2PRIV_Pos (1UL) +#define RCC_PRIVCFGR2_IC2PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR2_IC2PRIV RCC_PRIVCFGR2_IC2PRIV_Msk /*!< Privileged protection of IC2 divider configuration bits */ +#define RCC_PRIVCFGR2_IC3PRIV_Pos (2UL) +#define RCC_PRIVCFGR2_IC3PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR2_IC3PRIV RCC_PRIVCFGR2_IC3PRIV_Msk /*!< Privileged protection of IC3 divider configuration bits */ +#define RCC_PRIVCFGR2_IC4PRIV_Pos (3UL) +#define RCC_PRIVCFGR2_IC4PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR2_IC4PRIV RCC_PRIVCFGR2_IC4PRIV_Msk /*!< Privileged protection of IC4 divider configuration bits */ +#define RCC_PRIVCFGR2_IC5PRIV_Pos (4UL) +#define RCC_PRIVCFGR2_IC5PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR2_IC5PRIV RCC_PRIVCFGR2_IC5PRIV_Msk /*!< Privileged protection of IC5 divider configuration bits */ +#define RCC_PRIVCFGR2_IC6PRIV_Pos (5UL) +#define RCC_PRIVCFGR2_IC6PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR2_IC6PRIV RCC_PRIVCFGR2_IC6PRIV_Msk /*!< Privileged protection of IC6 divider configuration bits */ +#define RCC_PRIVCFGR2_IC7PRIV_Pos (6UL) +#define RCC_PRIVCFGR2_IC7PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR2_IC7PRIV RCC_PRIVCFGR2_IC7PRIV_Msk /*!< Privileged protection of IC7 divider configuration bits */ +#define RCC_PRIVCFGR2_IC8PRIV_Pos (7UL) +#define RCC_PRIVCFGR2_IC8PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR2_IC8PRIV RCC_PRIVCFGR2_IC8PRIV_Msk /*!< Privileged protection of IC8 divider configuration bits */ +#define RCC_PRIVCFGR2_IC9PRIV_Pos (8UL) +#define RCC_PRIVCFGR2_IC9PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR2_IC9PRIV RCC_PRIVCFGR2_IC9PRIV_Msk /*!< Privileged protection of IC9 divider configuration bits */ +#define RCC_PRIVCFGR2_IC10PRIV_Pos (9UL) +#define RCC_PRIVCFGR2_IC10PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR2_IC10PRIV RCC_PRIVCFGR2_IC10PRIV_Msk /*!< Privileged protection of IC10 divider configuration bits */ +#define RCC_PRIVCFGR2_IC11PRIV_Pos (10UL) +#define RCC_PRIVCFGR2_IC11PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR2_IC11PRIV RCC_PRIVCFGR2_IC11PRIV_Msk /*!< Privileged protection of IC11 divider configuration bits */ +#define RCC_PRIVCFGR2_IC12PRIV_Pos (11UL) +#define RCC_PRIVCFGR2_IC12PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR2_IC12PRIV RCC_PRIVCFGR2_IC12PRIV_Msk /*!< Privileged protection of IC12 divider configuration bits */ +#define RCC_PRIVCFGR2_IC13PRIV_Pos (12UL) +#define RCC_PRIVCFGR2_IC13PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR2_IC13PRIV RCC_PRIVCFGR2_IC13PRIV_Msk /*!< Privileged protection of IC13 divider configuration bits */ +#define RCC_PRIVCFGR2_IC14PRIV_Pos (13UL) +#define RCC_PRIVCFGR2_IC14PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR2_IC14PRIV RCC_PRIVCFGR2_IC14PRIV_Msk /*!< Privileged protection of IC14 divider configuration bits */ +#define RCC_PRIVCFGR2_IC15PRIV_Pos (14UL) +#define RCC_PRIVCFGR2_IC15PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGR2_IC15PRIV RCC_PRIVCFGR2_IC15PRIV_Msk /*!< Privileged protection of IC15 divider configuration bits */ +#define RCC_PRIVCFGR2_IC16PRIV_Pos (15UL) +#define RCC_PRIVCFGR2_IC16PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGR2_IC16PRIV RCC_PRIVCFGR2_IC16PRIV_Msk /*!< Privileged protection of IC16 divider configuration bits */ +#define RCC_PRIVCFGR2_IC17PRIV_Pos (16UL) +#define RCC_PRIVCFGR2_IC17PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGR2_IC17PRIV RCC_PRIVCFGR2_IC17PRIV_Msk /*!< Privileges protection of IC17 divider configuration bits */ +#define RCC_PRIVCFGR2_IC18PRIV_Pos (17UL) +#define RCC_PRIVCFGR2_IC18PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGR2_IC18PRIV RCC_PRIVCFGR2_IC18PRIV_Msk /*!< Privilege protection of IC18 divider configuration bits */ +#define RCC_PRIVCFGR2_IC19PRIV_Pos (18UL) +#define RCC_PRIVCFGR2_IC19PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGR2_IC19PRIV RCC_PRIVCFGR2_IC19PRIV_Msk /*!< Privileged protection of IC19 divider configuration bits */ +#define RCC_PRIVCFGR2_IC20PRIV_Pos (19UL) +#define RCC_PRIVCFGR2_IC20PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGR2_IC20PRIV RCC_PRIVCFGR2_IC20PRIV_Msk /*!< Privileged protection of IC20 divider configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR2 register *****************/ +#define RCC_LOCKCFGR2_IC1LOCK_Pos (0UL) +#define RCC_LOCKCFGR2_IC1LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR2_IC1LOCK RCC_LOCKCFGR2_IC1LOCK_Msk /*!< Locked protection of IC1 divider configuration bits */ +#define RCC_LOCKCFGR2_IC2LOCK_Pos (1UL) +#define RCC_LOCKCFGR2_IC2LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR2_IC2LOCK RCC_LOCKCFGR2_IC2LOCK_Msk /*!< Locked protection of IC2 divider configuration bits */ +#define RCC_LOCKCFGR2_IC3LOCK_Pos (2UL) +#define RCC_LOCKCFGR2_IC3LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR2_IC3LOCK RCC_LOCKCFGR2_IC3LOCK_Msk /*!< Locked protection of IC3 divider configuration bits */ +#define RCC_LOCKCFGR2_IC4LOCK_Pos (3UL) +#define RCC_LOCKCFGR2_IC4LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR2_IC4LOCK RCC_LOCKCFGR2_IC4LOCK_Msk /*!< Locked protection of IC4 divider configuration bits */ +#define RCC_LOCKCFGR2_IC5LOCK_Pos (4UL) +#define RCC_LOCKCFGR2_IC5LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR2_IC5LOCK RCC_LOCKCFGR2_IC5LOCK_Msk /*!< Locked protection of IC5 divider configuration bits */ +#define RCC_LOCKCFGR2_IC6LOCK_Pos (5UL) +#define RCC_LOCKCFGR2_IC6LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR2_IC6LOCK RCC_LOCKCFGR2_IC6LOCK_Msk /*!< Locked protection of IC6 divider configuration bits */ +#define RCC_LOCKCFGR2_IC7LOCK_Pos (6UL) +#define RCC_LOCKCFGR2_IC7LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR2_IC7LOCK RCC_LOCKCFGR2_IC7LOCK_Msk /*!< Locked protection of IC7 divider configuration bits */ +#define RCC_LOCKCFGR2_IC8LOCK_Pos (7UL) +#define RCC_LOCKCFGR2_IC8LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR2_IC8LOCK RCC_LOCKCFGR2_IC8LOCK_Msk /*!< Locked protection of IC8 divider configuration bits */ +#define RCC_LOCKCFGR2_IC9LOCK_Pos (8UL) +#define RCC_LOCKCFGR2_IC9LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR2_IC9LOCK RCC_LOCKCFGR2_IC9LOCK_Msk /*!< Locked protection of IC9 divider configuration bits */ +#define RCC_LOCKCFGR2_IC10LOCK_Pos (9UL) +#define RCC_LOCKCFGR2_IC10LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR2_IC10LOCK RCC_LOCKCFGR2_IC10LOCK_Msk /*!< Locked protection of IC10 divider configuration bits */ +#define RCC_LOCKCFGR2_IC11LOCK_Pos (10UL) +#define RCC_LOCKCFGR2_IC11LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR2_IC11LOCK RCC_LOCKCFGR2_IC11LOCK_Msk /*!< Locked protection of IC11 divider configuration bits */ +#define RCC_LOCKCFGR2_IC12LOCK_Pos (11UL) +#define RCC_LOCKCFGR2_IC12LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR2_IC12LOCK RCC_LOCKCFGR2_IC12LOCK_Msk /*!< Locked protection of IC12 divider configuration bits */ +#define RCC_LOCKCFGR2_IC13LOCK_Pos (12UL) +#define RCC_LOCKCFGR2_IC13LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR2_IC13LOCK RCC_LOCKCFGR2_IC13LOCK_Msk /*!< Locked protection of IC13 divider configuration bits */ +#define RCC_LOCKCFGR2_IC14LOCK_Pos (13UL) +#define RCC_LOCKCFGR2_IC14LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR2_IC14LOCK RCC_LOCKCFGR2_IC14LOCK_Msk /*!< Locked protection of IC14 divider configuration bits */ +#define RCC_LOCKCFGR2_IC15LOCK_Pos (14UL) +#define RCC_LOCKCFGR2_IC15LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */ +#define RCC_LOCKCFGR2_IC15LOCK RCC_LOCKCFGR2_IC15LOCK_Msk /*!< Locked protection of IC15 divider configuration bits */ +#define RCC_LOCKCFGR2_IC16LOCK_Pos (15UL) +#define RCC_LOCKCFGR2_IC16LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */ +#define RCC_LOCKCFGR2_IC16LOCK RCC_LOCKCFGR2_IC16LOCK_Msk /*!< Locked protection of IC16 divider configuration bits */ +#define RCC_LOCKCFGR2_IC17LOCK_Pos (16UL) +#define RCC_LOCKCFGR2_IC17LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */ +#define RCC_LOCKCFGR2_IC17LOCK RCC_LOCKCFGR2_IC17LOCK_Msk /*!< Locked protection of IC17 divider configuration bits */ +#define RCC_LOCKCFGR2_IC18LOCK_Pos (17UL) +#define RCC_LOCKCFGR2_IC18LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */ +#define RCC_LOCKCFGR2_IC18LOCK RCC_LOCKCFGR2_IC18LOCK_Msk /*!< Locked protection of IC18 divider configuration bits */ +#define RCC_LOCKCFGR2_IC19LOCK_Pos (18UL) +#define RCC_LOCKCFGR2_IC19LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */ +#define RCC_LOCKCFGR2_IC19LOCK RCC_LOCKCFGR2_IC19LOCK_Msk /*!< Locked protection of IC19 divider configuration bits */ +#define RCC_LOCKCFGR2_IC20LOCK_Pos (19UL) +#define RCC_LOCKCFGR2_IC20LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */ +#define RCC_LOCKCFGR2_IC20LOCK RCC_LOCKCFGR2_IC20LOCK_Msk /*!< Locked protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR2 register *****************/ +#define RCC_PUBCFGR2_IC1PUB_Pos (0UL) +#define RCC_PUBCFGR2_IC1PUB_Msk (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR2_IC1PUB RCC_PUBCFGR2_IC1PUB_Msk /*!< Public protection of IC1 divider configuration bits */ +#define RCC_PUBCFGR2_IC2PUB_Pos (1UL) +#define RCC_PUBCFGR2_IC2PUB_Msk (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR2_IC2PUB RCC_PUBCFGR2_IC2PUB_Msk /*!< Public protection of IC2 divider configuration bits */ +#define RCC_PUBCFGR2_IC3PUB_Pos (2UL) +#define RCC_PUBCFGR2_IC3PUB_Msk (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR2_IC3PUB RCC_PUBCFGR2_IC3PUB_Msk /*!< Public protection of IC3 divider configuration bits */ +#define RCC_PUBCFGR2_IC4PUB_Pos (3UL) +#define RCC_PUBCFGR2_IC4PUB_Msk (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR2_IC4PUB RCC_PUBCFGR2_IC4PUB_Msk /*!< Public protection of IC4 divider configuration bits */ +#define RCC_PUBCFGR2_IC5PUB_Pos (4UL) +#define RCC_PUBCFGR2_IC5PUB_Msk (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR2_IC5PUB RCC_PUBCFGR2_IC5PUB_Msk /*!< Public protection of IC5 divider configuration bits */ +#define RCC_PUBCFGR2_IC6PUB_Pos (5UL) +#define RCC_PUBCFGR2_IC6PUB_Msk (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR2_IC6PUB RCC_PUBCFGR2_IC6PUB_Msk /*!< Public protection of IC6 divider configuration bits */ +#define RCC_PUBCFGR2_IC7PUB_Pos (6UL) +#define RCC_PUBCFGR2_IC7PUB_Msk (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR2_IC7PUB RCC_PUBCFGR2_IC7PUB_Msk /*!< Public protection of IC7 divider configuration bits */ +#define RCC_PUBCFGR2_IC8PUB_Pos (7UL) +#define RCC_PUBCFGR2_IC8PUB_Msk (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR2_IC8PUB RCC_PUBCFGR2_IC8PUB_Msk /*!< Public protection of IC8 divider configuration bits */ +#define RCC_PUBCFGR2_IC9PUB_Pos (8UL) +#define RCC_PUBCFGR2_IC9PUB_Msk (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR2_IC9PUB RCC_PUBCFGR2_IC9PUB_Msk /*!< Public protection of IC9 divider configuration bits */ +#define RCC_PUBCFGR2_IC10PUB_Pos (9UL) +#define RCC_PUBCFGR2_IC10PUB_Msk (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR2_IC10PUB RCC_PUBCFGR2_IC10PUB_Msk /*!< Public protection of IC10 divider configuration bits */ +#define RCC_PUBCFGR2_IC11PUB_Pos (10UL) +#define RCC_PUBCFGR2_IC11PUB_Msk (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR2_IC11PUB RCC_PUBCFGR2_IC11PUB_Msk /*!< Public protection of IC11 divider configuration bits */ +#define RCC_PUBCFGR2_IC12PUB_Pos (11UL) +#define RCC_PUBCFGR2_IC12PUB_Msk (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR2_IC12PUB RCC_PUBCFGR2_IC12PUB_Msk /*!< Public protection of IC12 divider configuration bits */ +#define RCC_PUBCFGR2_IC13PUB_Pos (12UL) +#define RCC_PUBCFGR2_IC13PUB_Msk (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR2_IC13PUB RCC_PUBCFGR2_IC13PUB_Msk /*!< Public protection of IC13 divider configuration bits */ +#define RCC_PUBCFGR2_IC14PUB_Pos (13UL) +#define RCC_PUBCFGR2_IC14PUB_Msk (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR2_IC14PUB RCC_PUBCFGR2_IC14PUB_Msk /*!< Public protection of IC14 divider configuration bits */ +#define RCC_PUBCFGR2_IC15PUB_Pos (14UL) +#define RCC_PUBCFGR2_IC15PUB_Msk (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGR2_IC15PUB RCC_PUBCFGR2_IC15PUB_Msk /*!< Public protection of IC15 divider configuration bits */ +#define RCC_PUBCFGR2_IC16PUB_Pos (15UL) +#define RCC_PUBCFGR2_IC16PUB_Msk (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGR2_IC16PUB RCC_PUBCFGR2_IC16PUB_Msk /*!< Public protection of IC16 divider configuration bits */ +#define RCC_PUBCFGR2_IC17PUB_Pos (16UL) +#define RCC_PUBCFGR2_IC17PUB_Msk (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGR2_IC17PUB RCC_PUBCFGR2_IC17PUB_Msk /*!< Public protection of IC17 divider configuration bits */ +#define RCC_PUBCFGR2_IC18PUB_Pos (17UL) +#define RCC_PUBCFGR2_IC18PUB_Msk (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGR2_IC18PUB RCC_PUBCFGR2_IC18PUB_Msk /*!< Public protection of IC18 divider configuration bits */ +#define RCC_PUBCFGR2_IC19PUB_Pos (18UL) +#define RCC_PUBCFGR2_IC19PUB_Msk (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGR2_IC19PUB RCC_PUBCFGR2_IC19PUB_Msk /*!< Public protection of IC19 divider configuration bits */ +#define RCC_PUBCFGR2_IC20PUB_Pos (19UL) +#define RCC_PUBCFGR2_IC20PUB_Msk (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGR2_IC20PUB RCC_PUBCFGR2_IC20PUB_Msk /*!< Public protection of IC20 divider configuration bits */ + +/***************** Bit definition for RCC_SECCFGR3 register *****************/ +#define RCC_SECCFGR3_MODSEC_Pos (0UL) +#define RCC_SECCFGR3_MODSEC_Msk (0x1UL << RCC_SECCFGR3_MODSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR3_MODSEC RCC_SECCFGR3_MODSEC_Msk /*!< Secure protection of MOD system configuration bits */ +#define RCC_SECCFGR3_SYSSEC_Pos (1UL) +#define RCC_SECCFGR3_SYSSEC_Msk (0x1UL << RCC_SECCFGR3_SYSSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR3_SYSSEC RCC_SECCFGR3_SYSSEC_Msk /*!< Secure protection of SYS system configuration bit */ +#define RCC_SECCFGR3_BUSSEC_Pos (2UL) +#define RCC_SECCFGR3_BUSSEC_Msk (0x1UL << RCC_SECCFGR3_BUSSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR3_BUSSEC RCC_SECCFGR3_BUSSEC_Msk /*!< Secure protection of BUS system configuration bits */ +#define RCC_SECCFGR3_PERSEC_Pos (3UL) +#define RCC_SECCFGR3_PERSEC_Msk (0x1UL << RCC_SECCFGR3_PERSEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR3_PERSEC RCC_SECCFGR3_PERSEC_Msk /*!< Secure protection of PER system configuration bits */ +#define RCC_SECCFGR3_INTSEC_Pos (4UL) +#define RCC_SECCFGR3_INTSEC_Msk (0x1UL << RCC_SECCFGR3_INTSEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR3_INTSEC RCC_SECCFGR3_INTSEC_Msk /*!< Secure protection of INT system configuration bits */ +#define RCC_SECCFGR3_RSTSEC_Pos (5UL) +#define RCC_SECCFGR3_RSTSEC_Msk (0x1UL << RCC_SECCFGR3_RSTSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR3_RSTSEC RCC_SECCFGR3_RSTSEC_Msk /*!< Secure protection of RST system configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR3 register *****************/ +#define RCC_PRIVCFGR3_MODPRIV_Pos (0UL) +#define RCC_PRIVCFGR3_MODPRIV_Msk (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR3_MODPRIV RCC_PRIVCFGR3_MODPRIV_Msk /*!< Privileged protection of MOD system configuration bits */ +#define RCC_PRIVCFGR3_SYSPRIV_Pos (1UL) +#define RCC_PRIVCFGR3_SYSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR3_SYSPRIV RCC_PRIVCFGR3_SYSPRIV_Msk /*!< Privileged protection of SYS system configuration bits */ +#define RCC_PRIVCFGR3_BUSPRIV_Pos (2UL) +#define RCC_PRIVCFGR3_BUSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR3_BUSPRIV RCC_PRIVCFGR3_BUSPRIV_Msk /*!< Privileged protection of BUS system configuration bits */ +#define RCC_PRIVCFGR3_PERPRIV_Pos (3UL) +#define RCC_PRIVCFGR3_PERPRIV_Msk (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR3_PERPRIV RCC_PRIVCFGR3_PERPRIV_Msk /*!< Privileged protection of PER system configuration bits */ +#define RCC_PRIVCFGR3_INTPRIV_Pos (4UL) +#define RCC_PRIVCFGR3_INTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR3_INTPRIV RCC_PRIVCFGR3_INTPRIV_Msk /*!< Privileged protection of INT system configuration bits */ +#define RCC_PRIVCFGR3_RSTPRIV_Pos (5UL) +#define RCC_PRIVCFGR3_RSTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR3_RSTPRIV RCC_PRIVCFGR3_RSTPRIV_Msk /*!< Privileged protection of RST system configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR3 register *****************/ +#define RCC_LOCKCFGR3_MODLOCK_Pos (0UL) +#define RCC_LOCKCFGR3_MODLOCK_Msk (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos) /*!< 0x00000001 */ +#define RCC_LOCKCFGR3_MODLOCK RCC_LOCKCFGR3_MODLOCK_Msk /*!< Locked protection of MOD system configuration bits */ +#define RCC_LOCKCFGR3_SYSLOCK_Pos (1UL) +#define RCC_LOCKCFGR3_SYSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR3_SYSLOCK RCC_LOCKCFGR3_SYSLOCK_Msk /*!< Locked protection of SYS system configuration bits */ +#define RCC_LOCKCFGR3_BUSLOCK_Pos (2UL) +#define RCC_LOCKCFGR3_BUSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR3_BUSLOCK RCC_LOCKCFGR3_BUSLOCK_Msk /*!< Locked protection of BUS system configuration bits */ +#define RCC_LOCKCFGR3_PERLOCK_Pos (3UL) +#define RCC_LOCKCFGR3_PERLOCK_Msk (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR3_PERLOCK RCC_LOCKCFGR3_PERLOCK_Msk /*!< Locked protection of PER system configuration bits */ +#define RCC_LOCKCFGR3_INTLOCK_Pos (4UL) +#define RCC_LOCKCFGR3_INTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR3_INTLOCK RCC_LOCKCFGR3_INTLOCK_Msk /*!< Locked protection of INT system configuration bits */ +#define RCC_LOCKCFGR3_RSTLOCK_Pos (5UL) +#define RCC_LOCKCFGR3_RSTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR3_RSTLOCK RCC_LOCKCFGR3_RSTLOCK_Msk /*!< Locked protection of RST system configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR3 register *****************/ +#define RCC_PUBCFGR3_MODPUB_Pos (0UL) +#define RCC_PUBCFGR3_MODPUB_Msk (0x1UL << RCC_PUBCFGR3_MODPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR3_MODPUB RCC_PUBCFGR3_MODPUB_Msk /*!< Public protection of MOD system configuration bits */ +#define RCC_PUBCFGR3_SYSPUB_Pos (1UL) +#define RCC_PUBCFGR3_SYSPUB_Msk (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR3_SYSPUB RCC_PUBCFGR3_SYSPUB_Msk /*!< Public protection of SYS system configuration bits */ +#define RCC_PUBCFGR3_BUSPUB_Pos (2UL) +#define RCC_PUBCFGR3_BUSPUB_Msk (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR3_BUSPUB RCC_PUBCFGR3_BUSPUB_Msk /*!< Public protection of BUS system configuration bits */ +#define RCC_PUBCFGR3_PERPUB_Pos (3UL) +#define RCC_PUBCFGR3_PERPUB_Msk (0x1UL << RCC_PUBCFGR3_PERPUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR3_PERPUB RCC_PUBCFGR3_PERPUB_Msk /*!< Public protection of PER system configuration bits */ +#define RCC_PUBCFGR3_INTPUB_Pos (4UL) +#define RCC_PUBCFGR3_INTPUB_Msk (0x1UL << RCC_PUBCFGR3_INTPUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR3_INTPUB RCC_PUBCFGR3_INTPUB_Msk /*!< Public protection of INT system configuration bits */ +#define RCC_PUBCFGR3_RSTPUB_Pos (5UL) +#define RCC_PUBCFGR3_RSTPUB_Msk (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR3_RSTPUB RCC_PUBCFGR3_RSTPUB_Msk /*!< Public protection of RST system configuration bits */ + +/***************** Bit definition for RCC_SECCFGR4 register *****************/ +#define RCC_SECCFGR4_ACLKNSEC_Pos (0UL) +#define RCC_SECCFGR4_ACLKNSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR4_ACLKNSEC RCC_SECCFGR4_ACLKNSEC_Msk /*!< Secure protection of ACLKN bus configuration bits */ +#define RCC_SECCFGR4_ACLKNCSEC_Pos (1UL) +#define RCC_SECCFGR4_ACLKNCSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR4_ACLKNCSEC RCC_SECCFGR4_ACLKNCSEC_Msk /*!< Secure protection of ACLKNC bus configuration bits */ +#define RCC_SECCFGR4_AHBMSEC_Pos (2UL) +#define RCC_SECCFGR4_AHBMSEC_Msk (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos) /*!< 0x00000004 */ +#define RCC_SECCFGR4_AHBMSEC RCC_SECCFGR4_AHBMSEC_Msk /*!< Secure protection of AHBM bus configuration bits */ +#define RCC_SECCFGR4_AHB1SEC_Pos (3UL) +#define RCC_SECCFGR4_AHB1SEC_Msk (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR4_AHB1SEC RCC_SECCFGR4_AHB1SEC_Msk /*!< Secure protection of AHB1 bus configuration bits */ +#define RCC_SECCFGR4_AHB2SEC_Pos (4UL) +#define RCC_SECCFGR4_AHB2SEC_Msk (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR4_AHB2SEC RCC_SECCFGR4_AHB2SEC_Msk /*!< Secure protection of AHB2 bus configuration bits */ +#define RCC_SECCFGR4_AHB3SEC_Pos (5UL) +#define RCC_SECCFGR4_AHB3SEC_Msk (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR4_AHB3SEC RCC_SECCFGR4_AHB3SEC_Msk /*!< Secure protection of AHB3 bus configuration bits */ +#define RCC_SECCFGR4_AHB4SEC_Pos (6UL) +#define RCC_SECCFGR4_AHB4SEC_Msk (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR4_AHB4SEC RCC_SECCFGR4_AHB4SEC_Msk /*!< Secure protection of AHB4 bus configuration bits */ +#define RCC_SECCFGR4_AHB5SEC_Pos (7UL) +#define RCC_SECCFGR4_AHB5SEC_Msk (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR4_AHB5SEC RCC_SECCFGR4_AHB5SEC_Msk /*!< Secure protection of AHB5 bus configuration bits */ +#define RCC_SECCFGR4_APB1SEC_Pos (8UL) +#define RCC_SECCFGR4_APB1SEC_Msk (0x1UL << RCC_SECCFGR4_APB1SEC_Pos) /*!< 0x00000100 */ +#define RCC_SECCFGR4_APB1SEC RCC_SECCFGR4_APB1SEC_Msk /*!< Secure protection of APB1 bus configuration bits */ +#define RCC_SECCFGR4_APB2SEC_Pos (9UL) +#define RCC_SECCFGR4_APB2SEC_Msk (0x1UL << RCC_SECCFGR4_APB2SEC_Pos) /*!< 0x00000200 */ +#define RCC_SECCFGR4_APB2SEC RCC_SECCFGR4_APB2SEC_Msk /*!< Secure protection of APB2 bus configuration bits */ +#define RCC_SECCFGR4_APB3SEC_Pos (10UL) +#define RCC_SECCFGR4_APB3SEC_Msk (0x1UL << RCC_SECCFGR4_APB3SEC_Pos) /*!< 0x00000400 */ +#define RCC_SECCFGR4_APB3SEC RCC_SECCFGR4_APB3SEC_Msk /*!< Secure protection of APB3 bus configuration bits */ +#define RCC_SECCFGR4_APB4SEC_Pos (11UL) +#define RCC_SECCFGR4_APB4SEC_Msk (0x1UL << RCC_SECCFGR4_APB4SEC_Pos) /*!< 0x00000800 */ +#define RCC_SECCFGR4_APB4SEC RCC_SECCFGR4_APB4SEC_Msk /*!< Secure protection of APB4 bus configuration bits */ +#define RCC_SECCFGR4_APB5SEC_Pos (12UL) +#define RCC_SECCFGR4_APB5SEC_Msk (0x1UL << RCC_SECCFGR4_APB5SEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR4_APB5SEC RCC_SECCFGR4_APB5SEC_Msk /*!< Secure protection of APB5 bus configuration bits */ +#define RCC_SECCFGR4_NOCSEC_Pos (13UL) +#define RCC_SECCFGR4_NOCSEC_Msk (0x1UL << RCC_SECCFGR4_NOCSEC_Pos) /*!< 0x00002000 */ +#define RCC_SECCFGR4_NOCSEC RCC_SECCFGR4_NOCSEC_Msk /*!< Secure protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_PRIVCFGR4 register *****************/ +#define RCC_PRIVCFGR4_ACLKNPRIV_Pos (0UL) +#define RCC_PRIVCFGR4_ACLKNPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGR4_ACLKNPRIV RCC_PRIVCFGR4_ACLKNPRIV_Msk /*!< Privileged protection of ACLKN bus configuration bits */ +#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos (1UL) +#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR4_ACLKNCPRIV RCC_PRIVCFGR4_ACLKNCPRIV_Msk /*!< Privileged protection of ACLKNC bus configuration bits */ +#define RCC_PRIVCFGR4_AHBMPRIV_Pos (2UL) +#define RCC_PRIVCFGR4_AHBMPRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGR4_AHBMPRIV RCC_PRIVCFGR4_AHBMPRIV_Msk /*!< Privileged protection of AHBM bus configuration bits */ +#define RCC_PRIVCFGR4_AHB1PRIV_Pos (3UL) +#define RCC_PRIVCFGR4_AHB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGR4_AHB1PRIV RCC_PRIVCFGR4_AHB1PRIV_Msk /*!< Privileged protection of AHB1 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB2PRIV_Pos (4UL) +#define RCC_PRIVCFGR4_AHB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGR4_AHB2PRIV RCC_PRIVCFGR4_AHB2PRIV_Msk /*!< Privileged protection of AHB2 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB3PRIV_Pos (5UL) +#define RCC_PRIVCFGR4_AHB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGR4_AHB3PRIV RCC_PRIVCFGR4_AHB3PRIV_Msk /*!< Privileged protection of AHB3 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB4PRIV_Pos (6UL) +#define RCC_PRIVCFGR4_AHB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGR4_AHB4PRIV RCC_PRIVCFGR4_AHB4PRIV_Msk /*!< Privileged protection of AHB4 bus configuration bits */ +#define RCC_PRIVCFGR4_AHB5PRIV_Pos (7UL) +#define RCC_PRIVCFGR4_AHB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGR4_AHB5PRIV RCC_PRIVCFGR4_AHB5PRIV_Msk /*!< Privileged protection of AHB5 bus configuration bits */ +#define RCC_PRIVCFGR4_APB1PRIV_Pos (8UL) +#define RCC_PRIVCFGR4_APB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGR4_APB1PRIV RCC_PRIVCFGR4_APB1PRIV_Msk /*!< Privileged protection of APB1 bus configuration bits */ +#define RCC_PRIVCFGR4_APB2PRIV_Pos (9UL) +#define RCC_PRIVCFGR4_APB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGR4_APB2PRIV RCC_PRIVCFGR4_APB2PRIV_Msk /*!< Privileged protection of APB2 bus configuration bits */ +#define RCC_PRIVCFGR4_APB3PRIV_Pos (10UL) +#define RCC_PRIVCFGR4_APB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGR4_APB3PRIV RCC_PRIVCFGR4_APB3PRIV_Msk /*!< Privileged protection of APB3 bus configuration bits */ +#define RCC_PRIVCFGR4_APB4PRIV_Pos (11UL) +#define RCC_PRIVCFGR4_APB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGR4_APB4PRIV RCC_PRIVCFGR4_APB4PRIV_Msk /*!< Privileged protection of APB4 bus configuration bits */ +#define RCC_PRIVCFGR4_APB5PRIV_Pos (12UL) +#define RCC_PRIVCFGR4_APB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGR4_APB5PRIV RCC_PRIVCFGR4_APB5PRIV_Msk /*!< Privileged protection of APB5 bus configuration bits */ +#define RCC_PRIVCFGR4_NOCPRIV_Pos (13UL) +#define RCC_PRIVCFGR4_NOCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGR4_NOCPRIV RCC_PRIVCFGR4_NOCPRIV_Msk /*!< Privileged protection of NOC bus configuration bits */ + +/**************** Bit definition for RCC_LOCKCFGR4 register *****************/ +#define RCC_LOCKCFGR4_ACLKNLOCK_Pos (0UL) +#define RCC_LOCKCFGR4_ACLKNLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */ +#define RCC_LOCKCFGR4_ACLKNLOCK RCC_LOCKCFGR4_ACLKNLOCK_Msk /*!< Locked protection of ACLKN bus configuration bits */ +#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos (1UL) +#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */ +#define RCC_LOCKCFGR4_ACLKNCLOCK RCC_LOCKCFGR4_ACLKNCLOCK_Msk /*!< Locked protection of ACLKNC bus configuration bits */ +#define RCC_LOCKCFGR4_AHBMLOCK_Pos (2UL) +#define RCC_LOCKCFGR4_AHBMLOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */ +#define RCC_LOCKCFGR4_AHBMLOCK RCC_LOCKCFGR4_AHBMLOCK_Msk /*!< Locked protection of AHBM bus configuration bits */ +#define RCC_LOCKCFGR4_AHB1LOCK_Pos (3UL) +#define RCC_LOCKCFGR4_AHB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */ +#define RCC_LOCKCFGR4_AHB1LOCK RCC_LOCKCFGR4_AHB1LOCK_Msk /*!< Locked protection of AHB1 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB2LOCK_Pos (4UL) +#define RCC_LOCKCFGR4_AHB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */ +#define RCC_LOCKCFGR4_AHB2LOCK RCC_LOCKCFGR4_AHB2LOCK_Msk /*!< Locked protection of AHB2 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB3LOCK_Pos (5UL) +#define RCC_LOCKCFGR4_AHB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */ +#define RCC_LOCKCFGR4_AHB3LOCK RCC_LOCKCFGR4_AHB3LOCK_Msk /*!< Locked protection of AHB3 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB4LOCK_Pos (6UL) +#define RCC_LOCKCFGR4_AHB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */ +#define RCC_LOCKCFGR4_AHB4LOCK RCC_LOCKCFGR4_AHB4LOCK_Msk /*!< Locked protection of AHB4 bus configuration bits */ +#define RCC_LOCKCFGR4_AHB5LOCK_Pos (7UL) +#define RCC_LOCKCFGR4_AHB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */ +#define RCC_LOCKCFGR4_AHB5LOCK RCC_LOCKCFGR4_AHB5LOCK_Msk /*!< Locked protection of AHB5 bus configuration bits */ +#define RCC_LOCKCFGR4_APB1LOCK_Pos (8UL) +#define RCC_LOCKCFGR4_APB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */ +#define RCC_LOCKCFGR4_APB1LOCK RCC_LOCKCFGR4_APB1LOCK_Msk /*!< Locked protection of APB1 bus configuration bits */ +#define RCC_LOCKCFGR4_APB2LOCK_Pos (9UL) +#define RCC_LOCKCFGR4_APB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */ +#define RCC_LOCKCFGR4_APB2LOCK RCC_LOCKCFGR4_APB2LOCK_Msk /*!< Locked protection of APB2 bus configuration bits */ +#define RCC_LOCKCFGR4_APB3LOCK_Pos (10UL) +#define RCC_LOCKCFGR4_APB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */ +#define RCC_LOCKCFGR4_APB3LOCK RCC_LOCKCFGR4_APB3LOCK_Msk /*!< Locked protection of APB3 bus configuration bits */ +#define RCC_LOCKCFGR4_APB4LOCK_Pos (11UL) +#define RCC_LOCKCFGR4_APB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */ +#define RCC_LOCKCFGR4_APB4LOCK RCC_LOCKCFGR4_APB4LOCK_Msk /*!< Locked protection of APB4 bus configuration bits */ +#define RCC_LOCKCFGR4_APB5LOCK_Pos (12UL) +#define RCC_LOCKCFGR4_APB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */ +#define RCC_LOCKCFGR4_APB5LOCK RCC_LOCKCFGR4_APB5LOCK_Msk /*!< Locked protection of APB5 bus configuration bits */ +#define RCC_LOCKCFGR4_NOCLOCK_Pos (13UL) +#define RCC_LOCKCFGR4_NOCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos) /*!< 0x00002000 */ +#define RCC_LOCKCFGR4_NOCLOCK RCC_LOCKCFGR4_NOCLOCK_Msk /*!< Locked protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR4 register *****************/ +#define RCC_PUBCFGR4_ACLKNPUB_Pos (0UL) +#define RCC_PUBCFGR4_ACLKNPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR4_ACLKNPUB RCC_PUBCFGR4_ACLKNPUB_Msk /*!< Public protection of the ACLKN bus configuration bits */ +#define RCC_PUBCFGR4_ACLKNCPUB_Pos (1UL) +#define RCC_PUBCFGR4_ACLKNCPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR4_ACLKNCPUB RCC_PUBCFGR4_ACLKNCPUB_Msk /*!< Public protection of ACLKNC bus configuration bits */ +#define RCC_PUBCFGR4_AHBMPUB_Pos (2UL) +#define RCC_PUBCFGR4_AHBMPUB_Msk (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR4_AHBMPUB RCC_PUBCFGR4_AHBMPUB_Msk /*!< Public protection of AHBM bus configuration bits */ +#define RCC_PUBCFGR4_AHB1PUB_Pos (3UL) +#define RCC_PUBCFGR4_AHB1PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR4_AHB1PUB RCC_PUBCFGR4_AHB1PUB_Msk /*!< Public protection of AHB1 bus configuration bits */ +#define RCC_PUBCFGR4_AHB2PUB_Pos (4UL) +#define RCC_PUBCFGR4_AHB2PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR4_AHB2PUB RCC_PUBCFGR4_AHB2PUB_Msk /*!< Public protection of AHB2 bus configuration bits */ +#define RCC_PUBCFGR4_AHB3PUB_Pos (5UL) +#define RCC_PUBCFGR4_AHB3PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR4_AHB3PUB RCC_PUBCFGR4_AHB3PUB_Msk /*!< Public protection of AHB3 bus configuration bits */ +#define RCC_PUBCFGR4_AHB4PUB_Pos (6UL) +#define RCC_PUBCFGR4_AHB4PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGR4_AHB4PUB RCC_PUBCFGR4_AHB4PUB_Msk /*!< Public protection of AHB4 bus configuration bits */ +#define RCC_PUBCFGR4_AHB5PUB_Pos (7UL) +#define RCC_PUBCFGR4_AHB5PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR4_AHB5PUB RCC_PUBCFGR4_AHB5PUB_Msk /*!< Public protection of AHB5 bus configuration bits */ +#define RCC_PUBCFGR4_APB1PUB_Pos (8UL) +#define RCC_PUBCFGR4_APB1PUB_Msk (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR4_APB1PUB RCC_PUBCFGR4_APB1PUB_Msk /*!< Public protection of APB1 bus configuration bits */ +#define RCC_PUBCFGR4_APB2PUB_Pos (9UL) +#define RCC_PUBCFGR4_APB2PUB_Msk (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGR4_APB2PUB RCC_PUBCFGR4_APB2PUB_Msk /*!< Public protection of APB2 bus configuration bits */ +#define RCC_PUBCFGR4_APB3PUB_Pos (10UL) +#define RCC_PUBCFGR4_APB3PUB_Msk (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR4_APB3PUB RCC_PUBCFGR4_APB3PUB_Msk /*!< Public protection of APB3 bus configuration bits */ +#define RCC_PUBCFGR4_APB4PUB_Pos (11UL) +#define RCC_PUBCFGR4_APB4PUB_Msk (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGR4_APB4PUB RCC_PUBCFGR4_APB4PUB_Msk /*!< Public protection of APB4 bus configuration bits */ +#define RCC_PUBCFGR4_APB5PUB_Pos (12UL) +#define RCC_PUBCFGR4_APB5PUB_Msk (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGR4_APB5PUB RCC_PUBCFGR4_APB5PUB_Msk /*!< Public protection of APB5 bus configuration bits */ +#define RCC_PUBCFGR4_NOCPUB_Pos (13UL) +#define RCC_PUBCFGR4_NOCPUB_Msk (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGR4_NOCPUB RCC_PUBCFGR4_NOCPUB_Msk /*!< Public protection of NOC bus configuration bits */ + +/***************** Bit definition for RCC_PUBCFGR5 register *****************/ +#define RCC_PUBCFGR5_AXISRAM3PUB_Pos (0UL) +#define RCC_PUBCFGR5_AXISRAM3PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGR5_AXISRAM3PUB RCC_PUBCFGR5_AXISRAM3PUB_Msk /*!< Public protection of AXISRAM3 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM4PUB_Pos (1UL) +#define RCC_PUBCFGR5_AXISRAM4PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGR5_AXISRAM4PUB RCC_PUBCFGR5_AXISRAM4PUB_Msk /*!< Public protection of AXISRAM4 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM5PUB_Pos (2UL) +#define RCC_PUBCFGR5_AXISRAM5PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGR5_AXISRAM5PUB RCC_PUBCFGR5_AXISRAM5PUB_Msk /*!< Public protection of AXISRAM5 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM6PUB_Pos (3UL) +#define RCC_PUBCFGR5_AXISRAM6PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGR5_AXISRAM6PUB RCC_PUBCFGR5_AXISRAM6PUB_Msk /*!< Public protection of AXISRAM6 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos (4UL) +#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGR5_AHBSRAM1PUB RCC_PUBCFGR5_AHBSRAM1PUB_Msk /*!< Public protection of AHBSRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos (5UL) +#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGR5_AHBSRAM2PUB RCC_PUBCFGR5_AHBSRAM2PUB_Msk /*!< Public protection of AHBSRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_BKPSRAMPUB_Pos (6UL) +#define RCC_PUBCFGR5_BKPSRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */ +#define RCC_PUBCFGR5_BKPSRAMPUB RCC_PUBCFGR5_BKPSRAMPUB_Msk /*!< Public protection of BKPSRAM bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM1PUB_Pos (7UL) +#define RCC_PUBCFGR5_AXISRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGR5_AXISRAM1PUB RCC_PUBCFGR5_AXISRAM1PUB_Msk /*!< Public protection of AXISRAM1 bus configuration bits */ +#define RCC_PUBCFGR5_AXISRAM2PUB_Pos (8UL) +#define RCC_PUBCFGR5_AXISRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGR5_AXISRAM2PUB RCC_PUBCFGR5_AXISRAM2PUB_Msk /*!< Public protection of AXISRAM2 bus configuration bits */ +#define RCC_PUBCFGR5_FLEXRAMPUB_Pos (9UL) +#define RCC_PUBCFGR5_FLEXRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */ +#define RCC_PUBCFGR5_FLEXRAMPUB RCC_PUBCFGR5_FLEXRAMPUB_Msk /*!< Public protection of FLEXRAM bus configuration bits */ +#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos (10UL) +#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGR5_CACHEAXIRAMPUB RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk /*!< Public protection of CACHEAXIRAM bus configuration bits */ +#define RCC_PUBCFGR5_VENCRAMPUB_Pos (11UL) +#define RCC_PUBCFGR5_VENCRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */ +#define RCC_PUBCFGR5_VENCRAMPUB RCC_PUBCFGR5_VENCRAMPUB_Msk /*!< Public protection of VENCRAM bus configuration bits */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSIONS_Pos (0UL) +#define RCC_CSR_LSIONS_Msk (0x1UL << RCC_CSR_LSIONS_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSIONS RCC_CSR_LSIONS_Msk /*!< LSI oscillator enable */ +#define RCC_CSR_LSEONS_Pos (1UL) +#define RCC_CSR_LSEONS_Msk (0x1UL << RCC_CSR_LSEONS_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSEONS RCC_CSR_LSEONS_Msk /*!< LSE oscillator enable */ +#define RCC_CSR_MSIONS_Pos (2UL) +#define RCC_CSR_MSIONS_Msk (0x1UL << RCC_CSR_MSIONS_Pos) /*!< 0x00000004 */ +#define RCC_CSR_MSIONS RCC_CSR_MSIONS_Msk /*!< MSI oscillator enable */ +#define RCC_CSR_HSIONS_Pos (3UL) +#define RCC_CSR_HSIONS_Msk (0x1UL << RCC_CSR_HSIONS_Pos) /*!< 0x00000008 */ +#define RCC_CSR_HSIONS RCC_CSR_HSIONS_Msk /*!< HSI oscillator enable */ +#define RCC_CSR_HSEONS_Pos (4UL) +#define RCC_CSR_HSEONS_Msk (0x1UL << RCC_CSR_HSEONS_Pos) /*!< 0x00000010 */ +#define RCC_CSR_HSEONS RCC_CSR_HSEONS_Msk /*!< HSE oscillator enable */ +#define RCC_CSR_PLL1ONS_Pos (8UL) +#define RCC_CSR_PLL1ONS_Msk (0x1UL << RCC_CSR_PLL1ONS_Pos) /*!< 0x00000100 */ +#define RCC_CSR_PLL1ONS RCC_CSR_PLL1ONS_Msk /*!< PLL1 oscillator enable */ +#define RCC_CSR_PLL2ONS_Pos (9UL) +#define RCC_CSR_PLL2ONS_Msk (0x1UL << RCC_CSR_PLL2ONS_Pos) /*!< 0x00000200 */ +#define RCC_CSR_PLL2ONS RCC_CSR_PLL2ONS_Msk /*!< PLL2 oscillator enable */ +#define RCC_CSR_PLL3ONS_Pos (10UL) +#define RCC_CSR_PLL3ONS_Msk (0x1UL << RCC_CSR_PLL3ONS_Pos) /*!< 0x00000400 */ +#define RCC_CSR_PLL3ONS RCC_CSR_PLL3ONS_Msk /*!< PLL3 oscillator enable */ +#define RCC_CSR_PLL4ONS_Pos (11UL) +#define RCC_CSR_PLL4ONS_Msk (0x1UL << RCC_CSR_PLL4ONS_Pos) /*!< 0x00000800 */ +#define RCC_CSR_PLL4ONS RCC_CSR_PLL4ONS_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCSR register ******************/ +#define RCC_STOPCSR_MSISTOPENS_Pos (0UL) +#define RCC_STOPCSR_MSISTOPENS_Msk (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */ +#define RCC_STOPCSR_MSISTOPENS RCC_STOPCSR_MSISTOPENS_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCSR_HSISTOPENS_Pos (1UL) +#define RCC_STOPCSR_HSISTOPENS_Msk (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */ +#define RCC_STOPCSR_HSISTOPENS RCC_STOPCSR_HSISTOPENS_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTSR register *****************/ +#define RCC_MISCRSTSR_DBGRSTS_Pos (0UL) +#define RCC_MISCRSTSR_DBGRSTS_Msk (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTSR_DBGRSTS RCC_MISCRSTSR_DBGRSTS_Msk /*!< DBG reset */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos (4UL) +#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTSR_XSPIPHY1RSTS RCC_MISCRSTSR_XSPIPHY1RSTS_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos (5UL) +#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTSR_XSPIPHY2RSTS RCC_MISCRSTSR_XSPIPHY2RSTS_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos (7UL) +#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTSR_SDMMC1DLLRSTS RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos (8UL) +#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTSR_SDMMC2DLLRSTS RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTSR register *****************/ +#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos (0UL) +#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTSR_AXISRAM3RSTS RCC_MEMRSTSR_AXISRAM3RSTS_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos (1UL) +#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTSR_AXISRAM4RSTS RCC_MEMRSTSR_AXISRAM4RSTS_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos (2UL) +#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTSR_AXISRAM5RSTS RCC_MEMRSTSR_AXISRAM5RSTS_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos (3UL) +#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTSR_AXISRAM6RSTS RCC_MEMRSTSR_AXISRAM6RSTS_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos (4UL) +#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTSR_AHBSRAM1RSTS RCC_MEMRSTSR_AHBSRAM1RSTS_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos (5UL) +#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTSR_AHBSRAM2RSTS RCC_MEMRSTSR_AHBSRAM2RSTS_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos (7UL) +#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTSR_AXISRAM1RSTS RCC_MEMRSTSR_AXISRAM1RSTS_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos (8UL) +#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTSR_AXISRAM2RSTS RCC_MEMRSTSR_AXISRAM2RSTS_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos (9UL) +#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTSR_FLEXRAMRSTS RCC_MEMRSTSR_FLEXRAMRSTS_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos (10UL) +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTSR_CACHEAXIRAMRSTS RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTSR_VENCRAMRSTS_Pos (11UL) +#define RCC_MEMRSTSR_VENCRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTSR_VENCRAMRSTS RCC_MEMRSTSR_VENCRAMRSTS_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTSR_BOOTROMRSTS_Pos (12UL) +#define RCC_MEMRSTSR_BOOTROMRSTS_Msk (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTSR_BOOTROMRSTS RCC_MEMRSTSR_BOOTROMRSTS_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTSR register *****************/ +#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos (4UL) +#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTSR_GPDMA1RSTS RCC_AHB1RSTSR_GPDMA1RSTS_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTSR_ADC12RSTS_Pos (5UL) +#define RCC_AHB1RSTSR_ADC12RSTS_Msk (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTSR_ADC12RSTS RCC_AHB1RSTSR_ADC12RSTS_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTSR register *****************/ +#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos (12UL) +#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTSR_RAMCFGRSTS RCC_AHB2RSTSR_RAMCFGRSTS_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTSR_MDF1RSTS_Pos (16UL) +#define RCC_AHB2RSTSR_MDF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSR_MDF1RSTS RCC_AHB2RSTSR_MDF1RSTS_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTSR_ADF1RSTS_Pos (17UL) +#define RCC_AHB2RSTSR_ADF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTSR_ADF1RSTS RCC_AHB2RSTSR_ADF1RSTS_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTSR register *****************/ +#define RCC_AHB3RSTSR_RNGRSTS_Pos (0UL) +#define RCC_AHB3RSTSR_RNGRSTS_Msk (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSR_RNGRSTS RCC_AHB3RSTSR_RNGRSTS_Msk /*!< RNG reset */ +#define RCC_AHB3RSTSR_HASHRSTS_Pos (1UL) +#define RCC_AHB3RSTSR_HASHRSTS_Msk (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTSR_HASHRSTS RCC_AHB3RSTSR_HASHRSTS_Msk /*!< HASH reset */ +#define RCC_AHB3RSTSR_CRYPRSTS_Pos (2UL) +#define RCC_AHB3RSTSR_CRYPRSTS_Msk (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTSR_CRYPRSTS RCC_AHB3RSTSR_CRYPRSTS_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTSR_SAESRSTS_Pos (4UL) +#define RCC_AHB3RSTSR_SAESRSTS_Msk (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSR_SAESRSTS RCC_AHB3RSTSR_SAESRSTS_Msk /*!< SAES reset */ +#define RCC_AHB3RSTSR_PKARSTS_Pos (8UL) +#define RCC_AHB3RSTSR_PKARSTS_Msk (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTSR_PKARSTS RCC_AHB3RSTSR_PKARSTS_Msk /*!< PKA reset */ +#define RCC_AHB3RSTSR_IACRSTS_Pos (10UL) +#define RCC_AHB3RSTSR_IACRSTS_Msk (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTSR_IACRSTS RCC_AHB3RSTSR_IACRSTS_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTSR register *****************/ +#define RCC_AHB4RSTSR_GPIOARSTS_Pos (0UL) +#define RCC_AHB4RSTSR_GPIOARSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTSR_GPIOARSTS RCC_AHB4RSTSR_GPIOARSTS_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTSR_GPIOBRSTS_Pos (1UL) +#define RCC_AHB4RSTSR_GPIOBRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTSR_GPIOBRSTS RCC_AHB4RSTSR_GPIOBRSTS_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTSR_GPIOCRSTS_Pos (2UL) +#define RCC_AHB4RSTSR_GPIOCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTSR_GPIOCRSTS RCC_AHB4RSTSR_GPIOCRSTS_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTSR_GPIODRSTS_Pos (3UL) +#define RCC_AHB4RSTSR_GPIODRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTSR_GPIODRSTS RCC_AHB4RSTSR_GPIODRSTS_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTSR_GPIOERSTS_Pos (4UL) +#define RCC_AHB4RSTSR_GPIOERSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTSR_GPIOERSTS RCC_AHB4RSTSR_GPIOERSTS_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTSR_GPIOFRSTS_Pos (5UL) +#define RCC_AHB4RSTSR_GPIOFRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTSR_GPIOFRSTS RCC_AHB4RSTSR_GPIOFRSTS_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTSR_GPIOGRSTS_Pos (6UL) +#define RCC_AHB4RSTSR_GPIOGRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTSR_GPIOGRSTS RCC_AHB4RSTSR_GPIOGRSTS_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTSR_GPIOHRSTS_Pos (7UL) +#define RCC_AHB4RSTSR_GPIOHRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTSR_GPIOHRSTS RCC_AHB4RSTSR_GPIOHRSTS_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTSR_GPIONRSTS_Pos (13UL) +#define RCC_AHB4RSTSR_GPIONRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTSR_GPIONRSTS RCC_AHB4RSTSR_GPIONRSTS_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTSR_GPIOORSTS_Pos (14UL) +#define RCC_AHB4RSTSR_GPIOORSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTSR_GPIOORSTS RCC_AHB4RSTSR_GPIOORSTS_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTSR_GPIOPRSTS_Pos (15UL) +#define RCC_AHB4RSTSR_GPIOPRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTSR_GPIOPRSTS RCC_AHB4RSTSR_GPIOPRSTS_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTSR_GPIOQRSTS_Pos (16UL) +#define RCC_AHB4RSTSR_GPIOQRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTSR_GPIOQRSTS RCC_AHB4RSTSR_GPIOQRSTS_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTSR_PWRRSTS_Pos (18UL) +#define RCC_AHB4RSTSR_PWRRSTS_Msk (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTSR_PWRRSTS RCC_AHB4RSTSR_PWRRSTS_Msk /*!< PWR reset */ +#define RCC_AHB4RSTSR_CRCRSTS_Pos (19UL) +#define RCC_AHB4RSTSR_CRCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTSR_CRCRSTS RCC_AHB4RSTSR_CRCRSTS_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTSR register *****************/ +#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos (0UL) +#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSR_HPDMA1RSTS RCC_AHB5RSTSR_HPDMA1RSTS_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTSR_DMA2DRSTS_Pos (1UL) +#define RCC_AHB5RSTSR_DMA2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTSR_DMA2DRSTS RCC_AHB5RSTSR_DMA2DRSTS_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTSR_JPEGRSTS_Pos (3UL) +#define RCC_AHB5RSTSR_JPEGRSTS_Msk (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTSR_JPEGRSTS RCC_AHB5RSTSR_JPEGRSTS_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTSR_FMCRSTS_Pos (4UL) +#define RCC_AHB5RSTSR_FMCRSTS_Msk (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSR_FMCRSTS RCC_AHB5RSTSR_FMCRSTS_Msk /*!< FMC reset */ +#define RCC_AHB5RSTSR_XSPI1RSTS_Pos (5UL) +#define RCC_AHB5RSTSR_XSPI1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTSR_XSPI1RSTS RCC_AHB5RSTSR_XSPI1RSTS_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTSR_PSSIRSTS_Pos (6UL) +#define RCC_AHB5RSTSR_PSSIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSR_PSSIRSTS RCC_AHB5RSTSR_PSSIRSTS_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos (7UL) +#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTSR_SDMMC2RSTS RCC_AHB5RSTSR_SDMMC2RSTS_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos (8UL) +#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTSR_SDMMC1RSTS RCC_AHB5RSTSR_SDMMC1RSTS_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTSR_XSPI2RSTS_Pos (12UL) +#define RCC_AHB5RSTSR_XSPI2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTSR_XSPI2RSTS RCC_AHB5RSTSR_XSPI2RSTS_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTSR_XSPIMRSTS_Pos (13UL) +#define RCC_AHB5RSTSR_XSPIMRSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTSR_XSPIMRSTS RCC_AHB5RSTSR_XSPIMRSTS_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTSR_XSPI3RSTS_Pos (17UL) +#define RCC_AHB5RSTSR_XSPI3RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTSR_XSPI3RSTS RCC_AHB5RSTSR_XSPI3RSTS_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTSR_GFXMMURSTS_Pos (19UL) +#define RCC_AHB5RSTSR_GFXMMURSTS_Msk (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTSR_GFXMMURSTS RCC_AHB5RSTSR_GFXMMURSTS_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTSR_GPU2DRSTS_Pos (20UL) +#define RCC_AHB5RSTSR_GPU2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTSR_GPU2DRSTS RCC_AHB5RSTSR_GPU2DRSTS_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos (23UL) +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos (24UL) +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTSR_ETH1RSTS_Pos (25UL) +#define RCC_AHB5RSTSR_ETH1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTSR_ETH1RSTS RCC_AHB5RSTSR_ETH1RSTS_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTSR_OTG1RSTS_Pos (26UL) +#define RCC_AHB5RSTSR_OTG1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTSR_OTG1RSTS RCC_AHB5RSTSR_OTG1RSTS_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos (27UL) +#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTSR_OTGPHY1RSTS RCC_AHB5RSTSR_OTGPHY1RSTS_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos (28UL) +#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTSR_OTGPHY2RSTS RCC_AHB5RSTSR_OTGPHY2RSTS_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTSR_OTG2RSTS_Pos (29UL) +#define RCC_AHB5RSTSR_OTG2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTSR_OTG2RSTS RCC_AHB5RSTSR_OTG2RSTS_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos (30UL) +#define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTSR_CACHEAXIRSTS RCC_AHB5RSTSR_CACHEAXIRSTS_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTSR_NPURSTS_Pos (31UL) +#define RCC_AHB5RSTSR_NPURSTS_Msk (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTSR_NPURSTS RCC_AHB5RSTSR_NPURSTS_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTSR1 register ****************/ +#define RCC_APB1RSTSR1_TIM2RSTS_Pos (0UL) +#define RCC_APB1RSTSR1_TIM2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTSR1_TIM2RSTS RCC_APB1RSTSR1_TIM2RSTS_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTSR1_TIM3RSTS_Pos (1UL) +#define RCC_APB1RSTSR1_TIM3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTSR1_TIM3RSTS RCC_APB1RSTSR1_TIM3RSTS_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTSR1_TIM4RSTS_Pos (2UL) +#define RCC_APB1RSTSR1_TIM4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTSR1_TIM4RSTS RCC_APB1RSTSR1_TIM4RSTS_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTSR1_TIM5RSTS_Pos (3UL) +#define RCC_APB1RSTSR1_TIM5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTSR1_TIM5RSTS RCC_APB1RSTSR1_TIM5RSTS_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTSR1_TIM6RSTS_Pos (4UL) +#define RCC_APB1RSTSR1_TIM6RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTSR1_TIM6RSTS RCC_APB1RSTSR1_TIM6RSTS_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTSR1_TIM7RSTS_Pos (5UL) +#define RCC_APB1RSTSR1_TIM7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTSR1_TIM7RSTS RCC_APB1RSTSR1_TIM7RSTS_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTSR1_TIM12RSTS_Pos (6UL) +#define RCC_APB1RSTSR1_TIM12RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSR1_TIM12RSTS RCC_APB1RSTSR1_TIM12RSTS_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTSR1_TIM13RSTS_Pos (7UL) +#define RCC_APB1RSTSR1_TIM13RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSR1_TIM13RSTS RCC_APB1RSTSR1_TIM13RSTS_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTSR1_TIM14RSTS_Pos (8UL) +#define RCC_APB1RSTSR1_TIM14RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR1_TIM14RSTS RCC_APB1RSTSR1_TIM14RSTS_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos (9UL) +#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSR1_LPTIM1RSTS RCC_APB1RSTSR1_LPTIM1RSTS_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTSR1_WWDGRSTS_Pos (11UL) +#define RCC_APB1RSTSR1_WWDGRSTS_Msk (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTSR1_WWDGRSTS RCC_APB1RSTSR1_WWDGRSTS_Msk /*!< WWDG reset */ +#define RCC_APB1RSTSR1_TIM10RSTS_Pos (12UL) +#define RCC_APB1RSTSR1_TIM10RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSR1_TIM10RSTS RCC_APB1RSTSR1_TIM10RSTS_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTSR1_TIM11RSTS_Pos (13UL) +#define RCC_APB1RSTSR1_TIM11RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTSR1_TIM11RSTS RCC_APB1RSTSR1_TIM11RSTS_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTSR1_SPI2RSTS_Pos (14UL) +#define RCC_APB1RSTSR1_SPI2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTSR1_SPI2RSTS RCC_APB1RSTSR1_SPI2RSTS_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTSR1_SPI3RSTS_Pos (15UL) +#define RCC_APB1RSTSR1_SPI3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTSR1_SPI3RSTS RCC_APB1RSTSR1_SPI3RSTS_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos (16UL) +#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSR1_SPDIFRX1RSTS RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTSR1_USART2RSTS_Pos (17UL) +#define RCC_APB1RSTSR1_USART2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSR1_USART2RSTS RCC_APB1RSTSR1_USART2RSTS_Msk /*!< USART2 reset */ +#define RCC_APB1RSTSR1_USART3RSTS_Pos (18UL) +#define RCC_APB1RSTSR1_USART3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR1_USART3RSTS RCC_APB1RSTSR1_USART3RSTS_Msk /*!< USART3 reset */ +#define RCC_APB1RSTSR1_UART4RSTS_Pos (19UL) +#define RCC_APB1RSTSR1_UART4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSR1_UART4RSTS RCC_APB1RSTSR1_UART4RSTS_Msk /*!< UART4 reset */ +#define RCC_APB1RSTSR1_UART5RSTS_Pos (20UL) +#define RCC_APB1RSTSR1_UART5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTSR1_UART5RSTS RCC_APB1RSTSR1_UART5RSTS_Msk /*!< UART5 reset */ +#define RCC_APB1RSTSR1_I2C1RSTS_Pos (21UL) +#define RCC_APB1RSTSR1_I2C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTSR1_I2C1RSTS RCC_APB1RSTSR1_I2C1RSTS_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTSR1_I2C2RSTS_Pos (22UL) +#define RCC_APB1RSTSR1_I2C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTSR1_I2C2RSTS RCC_APB1RSTSR1_I2C2RSTS_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTSR1_I2C3RSTS_Pos (23UL) +#define RCC_APB1RSTSR1_I2C3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTSR1_I2C3RSTS RCC_APB1RSTSR1_I2C3RSTS_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTSR1_I3C1RSTS_Pos (24UL) +#define RCC_APB1RSTSR1_I3C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTSR1_I3C1RSTS RCC_APB1RSTSR1_I3C1RSTS_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTSR1_I3C2RSTS_Pos (25UL) +#define RCC_APB1RSTSR1_I3C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTSR1_I3C2RSTS RCC_APB1RSTSR1_I3C2RSTS_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTSR1_UART7RSTS_Pos (30UL) +#define RCC_APB1RSTSR1_UART7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTSR1_UART7RSTS RCC_APB1RSTSR1_UART7RSTS_Msk /*!< UART7 reset */ +#define RCC_APB1RSTSR1_UART8RSTS_Pos (31UL) +#define RCC_APB1RSTSR1_UART8RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSR1_UART8RSTS RCC_APB1RSTSR1_UART8RSTS_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTSR2 register ****************/ +#define RCC_APB1RSTSR2_MDIOSRSTS_Pos (5UL) +#define RCC_APB1RSTSR2_MDIOSRSTS_Msk (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSR2_MDIOSRSTS RCC_APB1RSTSR2_MDIOSRSTS_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTSR2_FDCANRSTS_Pos (8UL) +#define RCC_APB1RSTSR2_FDCANRSTS_Msk (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSR2_FDCANRSTS RCC_APB1RSTSR2_FDCANRSTS_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTSR2_UCPD1RSTS_Pos (18UL) +#define RCC_APB1RSTSR2_UCPD1RSTS_Msk (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSR2_UCPD1RSTS RCC_APB1RSTSR2_UCPD1RSTS_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTSR register *****************/ +#define RCC_APB2RSTSR_TIM1RSTS_Pos (0UL) +#define RCC_APB2RSTSR_TIM1RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSR_TIM1RSTS RCC_APB2RSTSR_TIM1RSTS_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTSR_TIM8RSTS_Pos (1UL) +#define RCC_APB2RSTSR_TIM8RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSR_TIM8RSTS RCC_APB2RSTSR_TIM8RSTS_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTSR_USART1RSTS_Pos (4UL) +#define RCC_APB2RSTSR_USART1RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSR_USART1RSTS RCC_APB2RSTSR_USART1RSTS_Msk /*!< USART1 reset */ +#define RCC_APB2RSTSR_USART6RSTS_Pos (5UL) +#define RCC_APB2RSTSR_USART6RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTSR_USART6RSTS RCC_APB2RSTSR_USART6RSTS_Msk /*!< USART6 reset */ +#define RCC_APB2RSTSR_UART9RSTS_Pos (6UL) +#define RCC_APB2RSTSR_UART9RSTS_Msk (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTSR_UART9RSTS RCC_APB2RSTSR_UART9RSTS_Msk /*!< UART9 reset */ +#define RCC_APB2RSTSR_USART10RSTS_Pos (7UL) +#define RCC_APB2RSTSR_USART10RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTSR_USART10RSTS RCC_APB2RSTSR_USART10RSTS_Msk /*!< USART10 reset */ +#define RCC_APB2RSTSR_SPI1RSTS_Pos (12UL) +#define RCC_APB2RSTSR_SPI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTSR_SPI1RSTS RCC_APB2RSTSR_SPI1RSTS_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTSR_SPI4RSTS_Pos (13UL) +#define RCC_APB2RSTSR_SPI4RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSR_SPI4RSTS RCC_APB2RSTSR_SPI4RSTS_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTSR_TIM18RSTS_Pos (15UL) +#define RCC_APB2RSTSR_TIM18RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTSR_TIM18RSTS RCC_APB2RSTSR_TIM18RSTS_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTSR_TIM15RSTS_Pos (16UL) +#define RCC_APB2RSTSR_TIM15RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTSR_TIM15RSTS RCC_APB2RSTSR_TIM15RSTS_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTSR_TIM16RSTS_Pos (17UL) +#define RCC_APB2RSTSR_TIM16RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTSR_TIM16RSTS RCC_APB2RSTSR_TIM16RSTS_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTSR_TIM17RSTS_Pos (18UL) +#define RCC_APB2RSTSR_TIM17RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTSR_TIM17RSTS RCC_APB2RSTSR_TIM17RSTS_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTSR_TIM9RSTS_Pos (19UL) +#define RCC_APB2RSTSR_TIM9RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTSR_TIM9RSTS RCC_APB2RSTSR_TIM9RSTS_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTSR_SPI5RSTS_Pos (20UL) +#define RCC_APB2RSTSR_SPI5RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSR_SPI5RSTS RCC_APB2RSTSR_SPI5RSTS_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTSR_SAI1RSTS_Pos (21UL) +#define RCC_APB2RSTSR_SAI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTSR_SAI1RSTS RCC_APB2RSTSR_SAI1RSTS_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTSR_SAI2RSTS_Pos (22UL) +#define RCC_APB2RSTSR_SAI2RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTSR_SAI2RSTS RCC_APB2RSTSR_SAI2RSTS_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTSR1 register ****************/ +#define RCC_APB4RSTSR1_HDPRSTS_Pos (2UL) +#define RCC_APB4RSTSR1_HDPRSTS_Msk (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR1_HDPRSTS RCC_APB4RSTSR1_HDPRSTS_Msk /*!< HDP reset */ +#define RCC_APB4RSTSR1_LPUART1RSTS_Pos (3UL) +#define RCC_APB4RSTSR1_LPUART1RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTSR1_LPUART1RSTS RCC_APB4RSTSR1_LPUART1RSTS_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTSR1_SPI6RSTS_Pos (5UL) +#define RCC_APB4RSTSR1_SPI6RSTS_Msk (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTSR1_SPI6RSTS RCC_APB4RSTSR1_SPI6RSTS_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTSR1_I2C4RSTS_Pos (7UL) +#define RCC_APB4RSTSR1_I2C4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTSR1_I2C4RSTS RCC_APB4RSTSR1_I2C4RSTS_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos (9UL) +#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTSR1_LPTIM2RSTS RCC_APB4RSTSR1_LPTIM2RSTS_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos (10UL) +#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTSR1_LPTIM3RSTS RCC_APB4RSTSR1_LPTIM3RSTS_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos (11UL) +#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTSR1_LPTIM4RSTS RCC_APB4RSTSR1_LPTIM4RSTS_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos (12UL) +#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTSR1_LPTIM5RSTS RCC_APB4RSTSR1_LPTIM5RSTS_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos (15UL) +#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTSR1_VREFBUFRSTS RCC_APB4RSTSR1_VREFBUFRSTS_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTSR1_RTCRSTS_Pos (16UL) +#define RCC_APB4RSTSR1_RTCRSTS_Msk (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSR1_RTCRSTS RCC_APB4RSTSR1_RTCRSTS_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTSR2 register ****************/ +#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos (0UL) +#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSR2_SYSCFGRSTS RCC_APB4RSTSR2_SYSCFGRSTS_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTSR2_DTSRSTS_Pos (2UL) +#define RCC_APB4RSTSR2_DTSRSTS_Msk (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTSR2_DTSRSTS RCC_APB4RSTSR2_DTSRSTS_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTSR register *****************/ +#define RCC_APB5RSTSR_LTDCRSTS_Pos (1UL) +#define RCC_APB5RSTSR_LTDCRSTS_Msk (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTSR_LTDCRSTS RCC_APB5RSTSR_LTDCRSTS_Msk /*!< LTDC reset */ +#define RCC_APB5RSTSR_DCMIPPRSTS_Pos (2UL) +#define RCC_APB5RSTSR_DCMIPPRSTS_Msk (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSR_DCMIPPRSTS RCC_APB5RSTSR_DCMIPPRSTS_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTSR_GFXTIMRSTS_Pos (4UL) +#define RCC_APB5RSTSR_GFXTIMRSTS_Msk (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSR_GFXTIMRSTS RCC_APB5RSTSR_GFXTIMRSTS_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTSR_VENCRSTS_Pos (5UL) +#define RCC_APB5RSTSR_VENCRSTS_Msk (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTSR_VENCRSTS RCC_APB5RSTSR_VENCRSTS_Msk /*!< VENC reset */ +#define RCC_APB5RSTSR_CSIRSTS_Pos (6UL) +#define RCC_APB5RSTSR_CSIRSTS_Msk (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTSR_CSIRSTS RCC_APB5RSTSR_CSIRSTS_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENSR register ******************/ +#define RCC_DIVENSR_IC1ENS_Pos (0UL) +#define RCC_DIVENSR_IC1ENS_Msk (0x1UL << RCC_DIVENSR_IC1ENS_Pos) /*!< 0x00000001 */ +#define RCC_DIVENSR_IC1ENS RCC_DIVENSR_IC1ENS_Msk /*!< IC1 enable */ +#define RCC_DIVENSR_IC2ENS_Pos (1UL) +#define RCC_DIVENSR_IC2ENS_Msk (0x1UL << RCC_DIVENSR_IC2ENS_Pos) /*!< 0x00000002 */ +#define RCC_DIVENSR_IC2ENS RCC_DIVENSR_IC2ENS_Msk /*!< IC2 enable */ +#define RCC_DIVENSR_IC3ENS_Pos (2UL) +#define RCC_DIVENSR_IC3ENS_Msk (0x1UL << RCC_DIVENSR_IC3ENS_Pos) /*!< 0x00000004 */ +#define RCC_DIVENSR_IC3ENS RCC_DIVENSR_IC3ENS_Msk /*!< IC3 enable */ +#define RCC_DIVENSR_IC4ENS_Pos (3UL) +#define RCC_DIVENSR_IC4ENS_Msk (0x1UL << RCC_DIVENSR_IC4ENS_Pos) /*!< 0x00000008 */ +#define RCC_DIVENSR_IC4ENS RCC_DIVENSR_IC4ENS_Msk /*!< IC4 enable */ +#define RCC_DIVENSR_IC5ENS_Pos (4UL) +#define RCC_DIVENSR_IC5ENS_Msk (0x1UL << RCC_DIVENSR_IC5ENS_Pos) /*!< 0x00000010 */ +#define RCC_DIVENSR_IC5ENS RCC_DIVENSR_IC5ENS_Msk /*!< IC5 enable */ +#define RCC_DIVENSR_IC6ENS_Pos (5UL) +#define RCC_DIVENSR_IC6ENS_Msk (0x1UL << RCC_DIVENSR_IC6ENS_Pos) /*!< 0x00000020 */ +#define RCC_DIVENSR_IC6ENS RCC_DIVENSR_IC6ENS_Msk /*!< IC6 enable */ +#define RCC_DIVENSR_IC7ENS_Pos (6UL) +#define RCC_DIVENSR_IC7ENS_Msk (0x1UL << RCC_DIVENSR_IC7ENS_Pos) /*!< 0x00000040 */ +#define RCC_DIVENSR_IC7ENS RCC_DIVENSR_IC7ENS_Msk /*!< IC7 enable */ +#define RCC_DIVENSR_IC8ENS_Pos (7UL) +#define RCC_DIVENSR_IC8ENS_Msk (0x1UL << RCC_DIVENSR_IC8ENS_Pos) /*!< 0x00000080 */ +#define RCC_DIVENSR_IC8ENS RCC_DIVENSR_IC8ENS_Msk /*!< IC8 enable */ +#define RCC_DIVENSR_IC9ENS_Pos (8UL) +#define RCC_DIVENSR_IC9ENS_Msk (0x1UL << RCC_DIVENSR_IC9ENS_Pos) /*!< 0x00000100 */ +#define RCC_DIVENSR_IC9ENS RCC_DIVENSR_IC9ENS_Msk /*!< IC9 enable */ +#define RCC_DIVENSR_IC10ENS_Pos (9UL) +#define RCC_DIVENSR_IC10ENS_Msk (0x1UL << RCC_DIVENSR_IC10ENS_Pos) /*!< 0x00000200 */ +#define RCC_DIVENSR_IC10ENS RCC_DIVENSR_IC10ENS_Msk /*!< IC10 enable */ +#define RCC_DIVENSR_IC11ENS_Pos (10UL) +#define RCC_DIVENSR_IC11ENS_Msk (0x1UL << RCC_DIVENSR_IC11ENS_Pos) /*!< 0x00000400 */ +#define RCC_DIVENSR_IC11ENS RCC_DIVENSR_IC11ENS_Msk /*!< IC11 enable */ +#define RCC_DIVENSR_IC12ENS_Pos (11UL) +#define RCC_DIVENSR_IC12ENS_Msk (0x1UL << RCC_DIVENSR_IC12ENS_Pos) /*!< 0x00000800 */ +#define RCC_DIVENSR_IC12ENS RCC_DIVENSR_IC12ENS_Msk /*!< IC12 enable */ +#define RCC_DIVENSR_IC13ENS_Pos (12UL) +#define RCC_DIVENSR_IC13ENS_Msk (0x1UL << RCC_DIVENSR_IC13ENS_Pos) /*!< 0x00001000 */ +#define RCC_DIVENSR_IC13ENS RCC_DIVENSR_IC13ENS_Msk /*!< IC13 enable */ +#define RCC_DIVENSR_IC14ENS_Pos (13UL) +#define RCC_DIVENSR_IC14ENS_Msk (0x1UL << RCC_DIVENSR_IC14ENS_Pos) /*!< 0x00002000 */ +#define RCC_DIVENSR_IC14ENS RCC_DIVENSR_IC14ENS_Msk /*!< IC14 enable */ +#define RCC_DIVENSR_IC15ENS_Pos (14UL) +#define RCC_DIVENSR_IC15ENS_Msk (0x1UL << RCC_DIVENSR_IC15ENS_Pos) /*!< 0x00004000 */ +#define RCC_DIVENSR_IC15ENS RCC_DIVENSR_IC15ENS_Msk /*!< IC15 enable */ +#define RCC_DIVENSR_IC16ENS_Pos (15UL) +#define RCC_DIVENSR_IC16ENS_Msk (0x1UL << RCC_DIVENSR_IC16ENS_Pos) /*!< 0x00008000 */ +#define RCC_DIVENSR_IC16ENS RCC_DIVENSR_IC16ENS_Msk /*!< IC16 enable */ +#define RCC_DIVENSR_IC17ENS_Pos (16UL) +#define RCC_DIVENSR_IC17ENS_Msk (0x1UL << RCC_DIVENSR_IC17ENS_Pos) /*!< 0x00010000 */ +#define RCC_DIVENSR_IC17ENS RCC_DIVENSR_IC17ENS_Msk /*!< IC17 enable */ +#define RCC_DIVENSR_IC18ENS_Pos (17UL) +#define RCC_DIVENSR_IC18ENS_Msk (0x1UL << RCC_DIVENSR_IC18ENS_Pos) /*!< 0x00020000 */ +#define RCC_DIVENSR_IC18ENS RCC_DIVENSR_IC18ENS_Msk /*!< IC18 enable */ +#define RCC_DIVENSR_IC19ENS_Pos (18UL) +#define RCC_DIVENSR_IC19ENS_Msk (0x1UL << RCC_DIVENSR_IC19ENS_Pos) /*!< 0x00040000 */ +#define RCC_DIVENSR_IC19ENS RCC_DIVENSR_IC19ENS_Msk /*!< IC19 enable */ +#define RCC_DIVENSR_IC20ENS_Pos (19UL) +#define RCC_DIVENSR_IC20ENS_Msk (0x1UL << RCC_DIVENSR_IC20ENS_Pos) /*!< 0x00080000 */ +#define RCC_DIVENSR_IC20ENS RCC_DIVENSR_IC20ENS_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENSR register ******************/ +#define RCC_BUSENSR_ACLKNENS_Pos (0UL) +#define RCC_BUSENSR_ACLKNENS_Msk (0x1UL << RCC_BUSENSR_ACLKNENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSENSR_ACLKNENS RCC_BUSENSR_ACLKNENS_Msk /*!< ACLKN enable */ +#define RCC_BUSENSR_ACLKNCENS_Pos (1UL) +#define RCC_BUSENSR_ACLKNCENS_Msk (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSENSR_ACLKNCENS RCC_BUSENSR_ACLKNCENS_Msk /*!< ACLKNC enable */ +#define RCC_BUSENSR_AHBMENS_Pos (2UL) +#define RCC_BUSENSR_AHBMENS_Msk (0x1UL << RCC_BUSENSR_AHBMENS_Pos) /*!< 0x00000004 */ +#define RCC_BUSENSR_AHBMENS RCC_BUSENSR_AHBMENS_Msk /*!< AHBM enable */ +#define RCC_BUSENSR_AHB1ENS_Pos (3UL) +#define RCC_BUSENSR_AHB1ENS_Msk (0x1UL << RCC_BUSENSR_AHB1ENS_Pos) /*!< 0x00000008 */ +#define RCC_BUSENSR_AHB1ENS RCC_BUSENSR_AHB1ENS_Msk /*!< AHB1 enable */ +#define RCC_BUSENSR_AHB2ENS_Pos (4UL) +#define RCC_BUSENSR_AHB2ENS_Msk (0x1UL << RCC_BUSENSR_AHB2ENS_Pos) /*!< 0x00000010 */ +#define RCC_BUSENSR_AHB2ENS RCC_BUSENSR_AHB2ENS_Msk /*!< AHB2 enable */ +#define RCC_BUSENSR_AHB3ENS_Pos (5UL) +#define RCC_BUSENSR_AHB3ENS_Msk (0x1UL << RCC_BUSENSR_AHB3ENS_Pos) /*!< 0x00000020 */ +#define RCC_BUSENSR_AHB3ENS RCC_BUSENSR_AHB3ENS_Msk /*!< AHB3 enable */ +#define RCC_BUSENSR_AHB4ENS_Pos (6UL) +#define RCC_BUSENSR_AHB4ENS_Msk (0x1UL << RCC_BUSENSR_AHB4ENS_Pos) /*!< 0x00000040 */ +#define RCC_BUSENSR_AHB4ENS RCC_BUSENSR_AHB4ENS_Msk /*!< AHB4 enable */ +#define RCC_BUSENSR_AHB5ENS_Pos (7UL) +#define RCC_BUSENSR_AHB5ENS_Msk (0x1UL << RCC_BUSENSR_AHB5ENS_Pos) /*!< 0x00000080 */ +#define RCC_BUSENSR_AHB5ENS RCC_BUSENSR_AHB5ENS_Msk /*!< AHB5 enable */ +#define RCC_BUSENSR_APB1ENS_Pos (8UL) +#define RCC_BUSENSR_APB1ENS_Msk (0x1UL << RCC_BUSENSR_APB1ENS_Pos) /*!< 0x00000100 */ +#define RCC_BUSENSR_APB1ENS RCC_BUSENSR_APB1ENS_Msk /*!< APB1 enable */ +#define RCC_BUSENSR_APB2ENS_Pos (9UL) +#define RCC_BUSENSR_APB2ENS_Msk (0x1UL << RCC_BUSENSR_APB2ENS_Pos) /*!< 0x00000200 */ +#define RCC_BUSENSR_APB2ENS RCC_BUSENSR_APB2ENS_Msk /*!< APB2 enable */ +#define RCC_BUSENSR_APB3ENS_Pos (10UL) +#define RCC_BUSENSR_APB3ENS_Msk (0x1UL << RCC_BUSENSR_APB3ENS_Pos) /*!< 0x00000400 */ +#define RCC_BUSENSR_APB3ENS RCC_BUSENSR_APB3ENS_Msk /*!< APB3 enable */ +#define RCC_BUSENSR_APB4ENS_Pos (11UL) +#define RCC_BUSENSR_APB4ENS_Msk (0x1UL << RCC_BUSENSR_APB4ENS_Pos) /*!< 0x00000800 */ +#define RCC_BUSENSR_APB4ENS RCC_BUSENSR_APB4ENS_Msk /*!< APB4 enable */ +#define RCC_BUSENSR_APB5ENS_Pos (12UL) +#define RCC_BUSENSR_APB5ENS_Msk (0x1UL << RCC_BUSENSR_APB5ENS_Pos) /*!< 0x00001000 */ +#define RCC_BUSENSR_APB5ENS RCC_BUSENSR_APB5ENS_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENSR register *****************/ +#define RCC_MISCENSR_DBGENS_Pos (0UL) +#define RCC_MISCENSR_DBGENS_Msk (0x1UL << RCC_MISCENSR_DBGENS_Pos) /*!< 0x00000001 */ +#define RCC_MISCENSR_DBGENS RCC_MISCENSR_DBGENS_Msk /*!< DBG enable */ +#define RCC_MISCENSR_MCO1ENS_Pos (1UL) +#define RCC_MISCENSR_MCO1ENS_Msk (0x1UL << RCC_MISCENSR_MCO1ENS_Pos) /*!< 0x00000002 */ +#define RCC_MISCENSR_MCO1ENS RCC_MISCENSR_MCO1ENS_Msk /*!< MCO1 enable */ +#define RCC_MISCENSR_MCO2ENS_Pos (2UL) +#define RCC_MISCENSR_MCO2ENS_Msk (0x1UL << RCC_MISCENSR_MCO2ENS_Pos) /*!< 0x00000004 */ +#define RCC_MISCENSR_MCO2ENS RCC_MISCENSR_MCO2ENS_Msk /*!< MCO2 enable */ +#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos (3UL) +#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCENSR_XSPIPHYCOMPENS RCC_MISCENSR_XSPIPHYCOMPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENSR_PERENS_Pos (6UL) +#define RCC_MISCENSR_PERENS_Msk (0x1UL << RCC_MISCENSR_PERENS_Pos) /*!< 0x00000040 */ +#define RCC_MISCENSR_PERENS RCC_MISCENSR_PERENS_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENSR register ******************/ +#define RCC_MEMENSR_AXISRAM3ENS_Pos (0UL) +#define RCC_MEMENSR_AXISRAM3ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */ +#define RCC_MEMENSR_AXISRAM3ENS RCC_MEMENSR_AXISRAM3ENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENSR_AXISRAM4ENS_Pos (1UL) +#define RCC_MEMENSR_AXISRAM4ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */ +#define RCC_MEMENSR_AXISRAM4ENS RCC_MEMENSR_AXISRAM4ENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENSR_AXISRAM5ENS_Pos (2UL) +#define RCC_MEMENSR_AXISRAM5ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */ +#define RCC_MEMENSR_AXISRAM5ENS RCC_MEMENSR_AXISRAM5ENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENSR_AXISRAM6ENS_Pos (3UL) +#define RCC_MEMENSR_AXISRAM6ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */ +#define RCC_MEMENSR_AXISRAM6ENS RCC_MEMENSR_AXISRAM6ENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENSR_AHBSRAM1ENS_Pos (4UL) +#define RCC_MEMENSR_AHBSRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */ +#define RCC_MEMENSR_AHBSRAM1ENS RCC_MEMENSR_AHBSRAM1ENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENSR_AHBSRAM2ENS_Pos (5UL) +#define RCC_MEMENSR_AHBSRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */ +#define RCC_MEMENSR_AHBSRAM2ENS RCC_MEMENSR_AHBSRAM2ENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENSR_BKPSRAMENS_Pos (6UL) +#define RCC_MEMENSR_BKPSRAMENS_Msk (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMENSR_BKPSRAMENS RCC_MEMENSR_BKPSRAMENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENSR_AXISRAM1ENS_Pos (7UL) +#define RCC_MEMENSR_AXISRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */ +#define RCC_MEMENSR_AXISRAM1ENS RCC_MEMENSR_AXISRAM1ENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENSR_AXISRAM2ENS_Pos (8UL) +#define RCC_MEMENSR_AXISRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */ +#define RCC_MEMENSR_AXISRAM2ENS RCC_MEMENSR_AXISRAM2ENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENSR_FLEXRAMENS_Pos (9UL) +#define RCC_MEMENSR_FLEXRAMENS_Msk (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMENSR_FLEXRAMENS RCC_MEMENSR_FLEXRAMENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENSR_CACHEAXIRAMENS_Pos (10UL) +#define RCC_MEMENSR_CACHEAXIRAMENS_Msk (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos) /*!< 0x00000400 */ +#define RCC_MEMENSR_CACHEAXIRAMENS RCC_MEMENSR_CACHEAXIRAMENS_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENSR_VENCRAMENS_Pos (11UL) +#define RCC_MEMENSR_VENCRAMENS_Msk (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMENSR_VENCRAMENS RCC_MEMENSR_VENCRAMENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMENSR_BOOTROMENS_Pos (12UL) +#define RCC_MEMENSR_BOOTROMENS_Msk (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMENSR_BOOTROMENS RCC_MEMENSR_BOOTROMENS_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENSR register *****************/ +#define RCC_AHB1ENSR_GPDMA1ENS_Pos (4UL) +#define RCC_AHB1ENSR_GPDMA1ENS_Msk (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENSR_GPDMA1ENS RCC_AHB1ENSR_GPDMA1ENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENSR_ADC12ENS_Pos (5UL) +#define RCC_AHB1ENSR_ADC12ENS_Msk (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENSR_ADC12ENS RCC_AHB1ENSR_ADC12ENS_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENSR register *****************/ +#define RCC_AHB2ENSR_RAMCFGENS_Pos (12UL) +#define RCC_AHB2ENSR_RAMCFGENS_Msk (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENSR_RAMCFGENS RCC_AHB2ENSR_RAMCFGENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENSR_MDF1ENS_Pos (16UL) +#define RCC_AHB2ENSR_MDF1ENS_Msk (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENSR_MDF1ENS RCC_AHB2ENSR_MDF1ENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENSR_ADF1ENS_Pos (17UL) +#define RCC_AHB2ENSR_ADF1ENS_Msk (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENSR_ADF1ENS RCC_AHB2ENSR_ADF1ENS_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENSR register *****************/ +#define RCC_AHB3ENSR_RNGENS_Pos (0UL) +#define RCC_AHB3ENSR_RNGENS_Msk (0x1UL << RCC_AHB3ENSR_RNGENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENSR_RNGENS RCC_AHB3ENSR_RNGENS_Msk /*!< RNG enable */ +#define RCC_AHB3ENSR_HASHENS_Pos (1UL) +#define RCC_AHB3ENSR_HASHENS_Msk (0x1UL << RCC_AHB3ENSR_HASHENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENSR_HASHENS RCC_AHB3ENSR_HASHENS_Msk /*!< HASH enable */ +#define RCC_AHB3ENSR_CRYPENS_Pos (2UL) +#define RCC_AHB3ENSR_CRYPENS_Msk (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENSR_CRYPENS RCC_AHB3ENSR_CRYPENS_Msk /*!< CRYP enable */ +#define RCC_AHB3ENSR_SAESENS_Pos (4UL) +#define RCC_AHB3ENSR_SAESENS_Msk (0x1UL << RCC_AHB3ENSR_SAESENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENSR_SAESENS RCC_AHB3ENSR_SAESENS_Msk /*!< SAES enable */ +#define RCC_AHB3ENSR_PKAENS_Pos (8UL) +#define RCC_AHB3ENSR_PKAENS_Msk (0x1UL << RCC_AHB3ENSR_PKAENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENSR_PKAENS RCC_AHB3ENSR_PKAENS_Msk /*!< PKA enable */ +#define RCC_AHB3ENSR_RIFSCENS_Pos (9UL) +#define RCC_AHB3ENSR_RIFSCENS_Msk (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENSR_RIFSCENS RCC_AHB3ENSR_RIFSCENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENSR_IACENS_Pos (10UL) +#define RCC_AHB3ENSR_IACENS_Msk (0x1UL << RCC_AHB3ENSR_IACENS_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENSR_IACENS RCC_AHB3ENSR_IACENS_Msk /*!< IAC enable */ +#define RCC_AHB3ENSR_RISAFENS_Pos (14UL) +#define RCC_AHB3ENSR_RISAFENS_Msk (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENSR_RISAFENS RCC_AHB3ENSR_RISAFENS_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENSR register *****************/ +#define RCC_AHB4ENSR_GPIOAENS_Pos (0UL) +#define RCC_AHB4ENSR_GPIOAENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENSR_GPIOAENS RCC_AHB4ENSR_GPIOAENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENSR_GPIOBENS_Pos (1UL) +#define RCC_AHB4ENSR_GPIOBENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENSR_GPIOBENS RCC_AHB4ENSR_GPIOBENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENSR_GPIOCENS_Pos (2UL) +#define RCC_AHB4ENSR_GPIOCENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENSR_GPIOCENS RCC_AHB4ENSR_GPIOCENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENSR_GPIODENS_Pos (3UL) +#define RCC_AHB4ENSR_GPIODENS_Msk (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENSR_GPIODENS RCC_AHB4ENSR_GPIODENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENSR_GPIOEENS_Pos (4UL) +#define RCC_AHB4ENSR_GPIOEENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENSR_GPIOEENS RCC_AHB4ENSR_GPIOEENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENSR_GPIOFENS_Pos (5UL) +#define RCC_AHB4ENSR_GPIOFENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENSR_GPIOFENS RCC_AHB4ENSR_GPIOFENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENSR_GPIOGENS_Pos (6UL) +#define RCC_AHB4ENSR_GPIOGENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENSR_GPIOGENS RCC_AHB4ENSR_GPIOGENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENSR_GPIOHENS_Pos (7UL) +#define RCC_AHB4ENSR_GPIOHENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENSR_GPIOHENS RCC_AHB4ENSR_GPIOHENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENSR_GPIONENS_Pos (13UL) +#define RCC_AHB4ENSR_GPIONENS_Msk (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENSR_GPIONENS RCC_AHB4ENSR_GPIONENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENSR_GPIOOENS_Pos (14UL) +#define RCC_AHB4ENSR_GPIOOENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENSR_GPIOOENS RCC_AHB4ENSR_GPIOOENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENSR_GPIOPENS_Pos (15UL) +#define RCC_AHB4ENSR_GPIOPENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENSR_GPIOPENS RCC_AHB4ENSR_GPIOPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENSR_GPIOQENS_Pos (16UL) +#define RCC_AHB4ENSR_GPIOQENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENSR_GPIOQENS RCC_AHB4ENSR_GPIOQENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENSR_PWRENS_Pos (18UL) +#define RCC_AHB4ENSR_PWRENS_Msk (0x1UL << RCC_AHB4ENSR_PWRENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENSR_PWRENS RCC_AHB4ENSR_PWRENS_Msk /*!< PWR enable */ +#define RCC_AHB4ENSR_CRCENS_Pos (19UL) +#define RCC_AHB4ENSR_CRCENS_Msk (0x1UL << RCC_AHB4ENSR_CRCENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENSR_CRCENS RCC_AHB4ENSR_CRCENS_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENSR register *****************/ +#define RCC_AHB5ENSR_HPDMA1ENS_Pos (0UL) +#define RCC_AHB5ENSR_HPDMA1ENS_Msk (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENSR_HPDMA1ENS RCC_AHB5ENSR_HPDMA1ENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENSR_DMA2DENS_Pos (1UL) +#define RCC_AHB5ENSR_DMA2DENS_Msk (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENSR_DMA2DENS RCC_AHB5ENSR_DMA2DENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENSR_JPEGENS_Pos (3UL) +#define RCC_AHB5ENSR_JPEGENS_Msk (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENSR_JPEGENS RCC_AHB5ENSR_JPEGENS_Msk /*!< JPEG enable */ +#define RCC_AHB5ENSR_FMCENS_Pos (4UL) +#define RCC_AHB5ENSR_FMCENS_Msk (0x1UL << RCC_AHB5ENSR_FMCENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENSR_FMCENS RCC_AHB5ENSR_FMCENS_Msk /*!< FMC enable */ +#define RCC_AHB5ENSR_XSPI1ENS_Pos (5UL) +#define RCC_AHB5ENSR_XSPI1ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENSR_XSPI1ENS RCC_AHB5ENSR_XSPI1ENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENSR_PSSIENS_Pos (6UL) +#define RCC_AHB5ENSR_PSSIENS_Msk (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENSR_PSSIENS RCC_AHB5ENSR_PSSIENS_Msk /*!< PSSI enable */ +#define RCC_AHB5ENSR_SDMMC2ENS_Pos (7UL) +#define RCC_AHB5ENSR_SDMMC2ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENSR_SDMMC2ENS RCC_AHB5ENSR_SDMMC2ENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENSR_SDMMC1ENS_Pos (8UL) +#define RCC_AHB5ENSR_SDMMC1ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENSR_SDMMC1ENS RCC_AHB5ENSR_SDMMC1ENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENSR_XSPI2ENS_Pos (12UL) +#define RCC_AHB5ENSR_XSPI2ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENSR_XSPI2ENS RCC_AHB5ENSR_XSPI2ENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENSR_XSPIMENS_Pos (13UL) +#define RCC_AHB5ENSR_XSPIMENS_Msk (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENSR_XSPIMENS RCC_AHB5ENSR_XSPIMENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENSR_MCE1ENS_Pos (14UL) +#define RCC_AHB5ENSR_MCE1ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENSR_MCE1ENS RCC_AHB5ENSR_MCE1ENS_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENSR_MCE2ENS_Pos (15UL) +#define RCC_AHB5ENSR_MCE2ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENSR_MCE2ENS RCC_AHB5ENSR_MCE2ENS_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENSR_MCE3ENS_Pos (16UL) +#define RCC_AHB5ENSR_MCE3ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENSR_MCE3ENS RCC_AHB5ENSR_MCE3ENS_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENSR_XSPI3ENS_Pos (17UL) +#define RCC_AHB5ENSR_XSPI3ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENSR_XSPI3ENS RCC_AHB5ENSR_XSPI3ENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENSR_MCE4ENS_Pos (18UL) +#define RCC_AHB5ENSR_MCE4ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENSR_MCE4ENS RCC_AHB5ENSR_MCE4ENS_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENSR_GFXMMUENS_Pos (19UL) +#define RCC_AHB5ENSR_GFXMMUENS_Msk (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENSR_GFXMMUENS RCC_AHB5ENSR_GFXMMUENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENSR_GPU2DENS_Pos (20UL) +#define RCC_AHB5ENSR_GPU2DENS_Msk (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENSR_GPU2DENS RCC_AHB5ENSR_GPU2DENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENSR_ETH1MACENS_Pos (22UL) +#define RCC_AHB5ENSR_ETH1MACENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENSR_ETH1MACENS RCC_AHB5ENSR_ETH1MACENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENSR_ETH1TXENS_Pos (23UL) +#define RCC_AHB5ENSR_ETH1TXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENSR_ETH1TXENS RCC_AHB5ENSR_ETH1TXENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENSR_ETH1RXENS_Pos (24UL) +#define RCC_AHB5ENSR_ETH1RXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENSR_ETH1RXENS RCC_AHB5ENSR_ETH1RXENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENSR_ETH1ENS_Pos (25UL) +#define RCC_AHB5ENSR_ETH1ENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENSR_ETH1ENS RCC_AHB5ENSR_ETH1ENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENSR_OTG1ENS_Pos (26UL) +#define RCC_AHB5ENSR_OTG1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENSR_OTG1ENS RCC_AHB5ENSR_OTG1ENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENSR_OTGPHY1ENS_Pos (27UL) +#define RCC_AHB5ENSR_OTGPHY1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENSR_OTGPHY1ENS RCC_AHB5ENSR_OTGPHY1ENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENSR_OTGPHY2ENS_Pos (28UL) +#define RCC_AHB5ENSR_OTGPHY2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENSR_OTGPHY2ENS RCC_AHB5ENSR_OTGPHY2ENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENSR_OTG2ENS_Pos (29UL) +#define RCC_AHB5ENSR_OTG2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENSR_OTG2ENS RCC_AHB5ENSR_OTG2ENS_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENSR_CACHEAXIENS_Pos (30UL) +#define RCC_AHB5ENSR_CACHEAXIENS_Msk (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENSR_CACHEAXIENS RCC_AHB5ENSR_CACHEAXIENS_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENSR_NPUENS_Pos (31UL) +#define RCC_AHB5ENSR_NPUENS_Msk (0x1UL << RCC_AHB5ENSR_NPUENS_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENSR_NPUENS RCC_AHB5ENSR_NPUENS_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1ENSR1 register *****************/ +#define RCC_APB1ENSR1_TIM2ENS_Pos (0UL) +#define RCC_APB1ENSR1_TIM2ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENSR1_TIM2ENS RCC_APB1ENSR1_TIM2ENS_Msk /*!< TIM2 enable */ +#define RCC_APB1ENSR1_TIM3ENS_Pos (1UL) +#define RCC_APB1ENSR1_TIM3ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENSR1_TIM3ENS RCC_APB1ENSR1_TIM3ENS_Msk /*!< TIM3 enable */ +#define RCC_APB1ENSR1_TIM4ENS_Pos (2UL) +#define RCC_APB1ENSR1_TIM4ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENSR1_TIM4ENS RCC_APB1ENSR1_TIM4ENS_Msk /*!< TIM4 enable */ +#define RCC_APB1ENSR1_TIM5ENS_Pos (3UL) +#define RCC_APB1ENSR1_TIM5ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENSR1_TIM5ENS RCC_APB1ENSR1_TIM5ENS_Msk /*!< TIM5 enable */ +#define RCC_APB1ENSR1_TIM6ENS_Pos (4UL) +#define RCC_APB1ENSR1_TIM6ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENSR1_TIM6ENS RCC_APB1ENSR1_TIM6ENS_Msk /*!< TIM6 enable */ +#define RCC_APB1ENSR1_TIM7ENS_Pos (5UL) +#define RCC_APB1ENSR1_TIM7ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR1_TIM7ENS RCC_APB1ENSR1_TIM7ENS_Msk /*!< TIM7 enable */ +#define RCC_APB1ENSR1_TIM12ENS_Pos (6UL) +#define RCC_APB1ENSR1_TIM12ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENSR1_TIM12ENS RCC_APB1ENSR1_TIM12ENS_Msk /*!< TIM12 enable */ +#define RCC_APB1ENSR1_TIM13ENS_Pos (7UL) +#define RCC_APB1ENSR1_TIM13ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENSR1_TIM13ENS RCC_APB1ENSR1_TIM13ENS_Msk /*!< TIM13 enable */ +#define RCC_APB1ENSR1_TIM14ENS_Pos (8UL) +#define RCC_APB1ENSR1_TIM14ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR1_TIM14ENS RCC_APB1ENSR1_TIM14ENS_Msk /*!< TIM14 enable */ +#define RCC_APB1ENSR1_LPTIM1ENS_Pos (9UL) +#define RCC_APB1ENSR1_LPTIM1ENS_Msk (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENSR1_LPTIM1ENS RCC_APB1ENSR1_LPTIM1ENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENSR1_WWDGENS_Pos (11UL) +#define RCC_APB1ENSR1_WWDGENS_Msk (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENSR1_WWDGENS RCC_APB1ENSR1_WWDGENS_Msk /*!< WWDG enable */ +#define RCC_APB1ENSR1_TIM10ENS_Pos (12UL) +#define RCC_APB1ENSR1_TIM10ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENSR1_TIM10ENS RCC_APB1ENSR1_TIM10ENS_Msk /*!< TIM10 enable */ +#define RCC_APB1ENSR1_TIM11ENS_Pos (13UL) +#define RCC_APB1ENSR1_TIM11ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENSR1_TIM11ENS RCC_APB1ENSR1_TIM11ENS_Msk /*!< TIM11 enable */ +#define RCC_APB1ENSR1_SPI2ENS_Pos (14UL) +#define RCC_APB1ENSR1_SPI2ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENSR1_SPI2ENS RCC_APB1ENSR1_SPI2ENS_Msk /*!< SPI2 enable */ +#define RCC_APB1ENSR1_SPI3ENS_Pos (15UL) +#define RCC_APB1ENSR1_SPI3ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENSR1_SPI3ENS RCC_APB1ENSR1_SPI3ENS_Msk /*!< SPI3 enable */ +#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos (16UL) +#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENSR1_SPDIFRX1ENS RCC_APB1ENSR1_SPDIFRX1ENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENSR1_USART2ENS_Pos (17UL) +#define RCC_APB1ENSR1_USART2ENS_Msk (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENSR1_USART2ENS RCC_APB1ENSR1_USART2ENS_Msk /*!< USART2 enable */ +#define RCC_APB1ENSR1_USART3ENS_Pos (18UL) +#define RCC_APB1ENSR1_USART3ENS_Msk (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENSR1_USART3ENS RCC_APB1ENSR1_USART3ENS_Msk /*!< USART3 enable */ +#define RCC_APB1ENSR1_UART4ENS_Pos (19UL) +#define RCC_APB1ENSR1_UART4ENS_Msk (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENSR1_UART4ENS RCC_APB1ENSR1_UART4ENS_Msk /*!< UART4 enable */ +#define RCC_APB1ENSR1_UART5ENS_Pos (20UL) +#define RCC_APB1ENSR1_UART5ENS_Msk (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENSR1_UART5ENS RCC_APB1ENSR1_UART5ENS_Msk /*!< UART5 enable */ +#define RCC_APB1ENSR1_I2C1ENS_Pos (21UL) +#define RCC_APB1ENSR1_I2C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENSR1_I2C1ENS RCC_APB1ENSR1_I2C1ENS_Msk /*!< I2C1 enable */ +#define RCC_APB1ENSR1_I2C2ENS_Pos (22UL) +#define RCC_APB1ENSR1_I2C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENSR1_I2C2ENS RCC_APB1ENSR1_I2C2ENS_Msk /*!< I2C2 enable */ +#define RCC_APB1ENSR1_I2C3ENS_Pos (23UL) +#define RCC_APB1ENSR1_I2C3ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENSR1_I2C3ENS RCC_APB1ENSR1_I2C3ENS_Msk /*!< I2C3 enable */ +#define RCC_APB1ENSR1_I3C1ENS_Pos (24UL) +#define RCC_APB1ENSR1_I3C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENSR1_I3C1ENS RCC_APB1ENSR1_I3C1ENS_Msk /*!< I3C1 enable */ +#define RCC_APB1ENSR1_I3C2ENS_Pos (25UL) +#define RCC_APB1ENSR1_I3C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENSR1_I3C2ENS RCC_APB1ENSR1_I3C2ENS_Msk /*!< I3C2 enable */ +#define RCC_APB1ENSR1_UART7ENS_Pos (30UL) +#define RCC_APB1ENSR1_UART7ENS_Msk (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENSR1_UART7ENS RCC_APB1ENSR1_UART7ENS_Msk /*!< UART7 enable */ +#define RCC_APB1ENSR1_UART8ENS_Pos (31UL) +#define RCC_APB1ENSR1_UART8ENS_Msk (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENSR1_UART8ENS RCC_APB1ENSR1_UART8ENS_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENSR2 register *****************/ +#define RCC_APB1ENSR2_MDIOSENS_Pos (5UL) +#define RCC_APB1ENSR2_MDIOSENS_Msk (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENSR2_MDIOSENS RCC_APB1ENSR2_MDIOSENS_Msk /*!< MDIOS enable */ +#define RCC_APB1ENSR2_FDCANENS_Pos (8UL) +#define RCC_APB1ENSR2_FDCANENS_Msk (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENSR2_FDCANENS RCC_APB1ENSR2_FDCANENS_Msk /*!< FDCAN enable */ +#define RCC_APB1ENSR2_UCPD1ENS_Pos (18UL) +#define RCC_APB1ENSR2_UCPD1ENS_Msk (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENSR2_UCPD1ENS RCC_APB1ENSR2_UCPD1ENS_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENSR register *****************/ +#define RCC_APB2ENSR_TIM1ENS_Pos (0UL) +#define RCC_APB2ENSR_TIM1ENS_Msk (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENSR_TIM1ENS RCC_APB2ENSR_TIM1ENS_Msk /*!< TIM1 enable */ +#define RCC_APB2ENSR_TIM8ENS_Pos (1UL) +#define RCC_APB2ENSR_TIM8ENS_Msk (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENSR_TIM8ENS RCC_APB2ENSR_TIM8ENS_Msk /*!< TIM8 enable */ +#define RCC_APB2ENSR_USART1ENS_Pos (4UL) +#define RCC_APB2ENSR_USART1ENS_Msk (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENSR_USART1ENS RCC_APB2ENSR_USART1ENS_Msk /*!< USART1 enable */ +#define RCC_APB2ENSR_USART6ENS_Pos (5UL) +#define RCC_APB2ENSR_USART6ENS_Msk (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENSR_USART6ENS RCC_APB2ENSR_USART6ENS_Msk /*!< USART6 enable */ +#define RCC_APB2ENSR_UART9ENS_Pos (6UL) +#define RCC_APB2ENSR_UART9ENS_Msk (0x1UL << RCC_APB2ENSR_UART9ENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENSR_UART9ENS RCC_APB2ENSR_UART9ENS_Msk /*!< UART9 enable */ +#define RCC_APB2ENSR_USART10ENS_Pos (7UL) +#define RCC_APB2ENSR_USART10ENS_Msk (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENSR_USART10ENS RCC_APB2ENSR_USART10ENS_Msk /*!< USART10 enable */ +#define RCC_APB2ENSR_SPI1ENS_Pos (12UL) +#define RCC_APB2ENSR_SPI1ENS_Msk (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENSR_SPI1ENS RCC_APB2ENSR_SPI1ENS_Msk /*!< SPI1 enable */ +#define RCC_APB2ENSR_SPI4ENS_Pos (13UL) +#define RCC_APB2ENSR_SPI4ENS_Msk (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENSR_SPI4ENS RCC_APB2ENSR_SPI4ENS_Msk /*!< SPI4 enable */ +#define RCC_APB2ENSR_TIM18ENS_Pos (15UL) +#define RCC_APB2ENSR_TIM18ENS_Msk (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENSR_TIM18ENS RCC_APB2ENSR_TIM18ENS_Msk /*!< TIM18 enable */ +#define RCC_APB2ENSR_TIM15ENS_Pos (16UL) +#define RCC_APB2ENSR_TIM15ENS_Msk (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENSR_TIM15ENS RCC_APB2ENSR_TIM15ENS_Msk /*!< TIM15 enable */ +#define RCC_APB2ENSR_TIM16ENS_Pos (17UL) +#define RCC_APB2ENSR_TIM16ENS_Msk (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENSR_TIM16ENS RCC_APB2ENSR_TIM16ENS_Msk /*!< TIM16 enable */ +#define RCC_APB2ENSR_TIM17ENS_Pos (18UL) +#define RCC_APB2ENSR_TIM17ENS_Msk (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENSR_TIM17ENS RCC_APB2ENSR_TIM17ENS_Msk /*!< TIM17 enable */ +#define RCC_APB2ENSR_TIM9ENS_Pos (19UL) +#define RCC_APB2ENSR_TIM9ENS_Msk (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENSR_TIM9ENS RCC_APB2ENSR_TIM9ENS_Msk /*!< TIM9 enable */ +#define RCC_APB2ENSR_SPI5ENS_Pos (20UL) +#define RCC_APB2ENSR_SPI5ENS_Msk (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENSR_SPI5ENS RCC_APB2ENSR_SPI5ENS_Msk /*!< SPI5 enable */ +#define RCC_APB2ENSR_SAI1ENS_Pos (21UL) +#define RCC_APB2ENSR_SAI1ENS_Msk (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENSR_SAI1ENS RCC_APB2ENSR_SAI1ENS_Msk /*!< SAI1 enable */ +#define RCC_APB2ENSR_SAI2ENS_Pos (22UL) +#define RCC_APB2ENSR_SAI2ENS_Msk (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENSR_SAI2ENS RCC_APB2ENSR_SAI2ENS_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENSR register *****************/ +#define RCC_APB3ENSR_DFTENS_Pos (2UL) +#define RCC_APB3ENSR_DFTENS_Msk (0x1UL << RCC_APB3ENSR_DFTENS_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENSR_DFTENS RCC_APB3ENSR_DFTENS_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENSR1 register *****************/ +#define RCC_APB4ENSR1_HDPENS_Pos (2UL) +#define RCC_APB4ENSR1_HDPENS_Msk (0x1UL << RCC_APB4ENSR1_HDPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR1_HDPENS RCC_APB4ENSR1_HDPENS_Msk /*!< HDP enable */ +#define RCC_APB4ENSR1_LPUART1ENS_Pos (3UL) +#define RCC_APB4ENSR1_LPUART1ENS_Msk (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENSR1_LPUART1ENS RCC_APB4ENSR1_LPUART1ENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENSR1_SPI6ENS_Pos (5UL) +#define RCC_APB4ENSR1_SPI6ENS_Msk (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENSR1_SPI6ENS RCC_APB4ENSR1_SPI6ENS_Msk /*!< SPI6 enable */ +#define RCC_APB4ENSR1_I2C4ENS_Pos (7UL) +#define RCC_APB4ENSR1_I2C4ENS_Msk (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENSR1_I2C4ENS RCC_APB4ENSR1_I2C4ENS_Msk /*!< I2C4 enable */ +#define RCC_APB4ENSR1_LPTIM2ENS_Pos (9UL) +#define RCC_APB4ENSR1_LPTIM2ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENSR1_LPTIM2ENS RCC_APB4ENSR1_LPTIM2ENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENSR1_LPTIM3ENS_Pos (10UL) +#define RCC_APB4ENSR1_LPTIM3ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENSR1_LPTIM3ENS RCC_APB4ENSR1_LPTIM3ENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENSR1_LPTIM4ENS_Pos (11UL) +#define RCC_APB4ENSR1_LPTIM4ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENSR1_LPTIM4ENS RCC_APB4ENSR1_LPTIM4ENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENSR1_LPTIM5ENS_Pos (12UL) +#define RCC_APB4ENSR1_LPTIM5ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENSR1_LPTIM5ENS RCC_APB4ENSR1_LPTIM5ENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENSR1_VREFBUFENS_Pos (15UL) +#define RCC_APB4ENSR1_VREFBUFENS_Msk (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENSR1_VREFBUFENS RCC_APB4ENSR1_VREFBUFENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENSR1_RTCENS_Pos (16UL) +#define RCC_APB4ENSR1_RTCENS_Msk (0x1UL << RCC_APB4ENSR1_RTCENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENSR1_RTCENS RCC_APB4ENSR1_RTCENS_Msk /*!< RTC enable */ +#define RCC_APB4ENSR1_RTCAPBENS_Pos (17UL) +#define RCC_APB4ENSR1_RTCAPBENS_Msk (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENSR1_RTCAPBENS RCC_APB4ENSR1_RTCAPBENS_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENSR2 register *****************/ +#define RCC_APB4ENSR2_SYSCFGENS_Pos (0UL) +#define RCC_APB4ENSR2_SYSCFGENS_Msk (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENSR2_SYSCFGENS RCC_APB4ENSR2_SYSCFGENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENSR2_BSECENS_Pos (1UL) +#define RCC_APB4ENSR2_BSECENS_Msk (0x1UL << RCC_APB4ENSR2_BSECENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENSR2_BSECENS RCC_APB4ENSR2_BSECENS_Msk /*!< BSEC enable */ +#define RCC_APB4ENSR2_DTSENS_Pos (2UL) +#define RCC_APB4ENSR2_DTSENS_Msk (0x1UL << RCC_APB4ENSR2_DTSENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENSR2_DTSENS RCC_APB4ENSR2_DTSENS_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENSR register *****************/ +#define RCC_APB5ENSR_LTDCENS_Pos (1UL) +#define RCC_APB5ENSR_LTDCENS_Msk (0x1UL << RCC_APB5ENSR_LTDCENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENSR_LTDCENS RCC_APB5ENSR_LTDCENS_Msk /*!< LTDC enable */ +#define RCC_APB5ENSR_DCMIPPENS_Pos (2UL) +#define RCC_APB5ENSR_DCMIPPENS_Msk (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENSR_DCMIPPENS RCC_APB5ENSR_DCMIPPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENSR_GFXTIMENS_Pos (4UL) +#define RCC_APB5ENSR_GFXTIMENS_Msk (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENSR_GFXTIMENS RCC_APB5ENSR_GFXTIMENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENSR_VENCENS_Pos (5UL) +#define RCC_APB5ENSR_VENCENS_Msk (0x1UL << RCC_APB5ENSR_VENCENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENSR_VENCENS RCC_APB5ENSR_VENCENS_Msk /*!< VENC enable */ +#define RCC_APB5ENSR_CSIENS_Pos (6UL) +#define RCC_APB5ENSR_CSIENS_Msk (0x1UL << RCC_APB5ENSR_CSIENS_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENSR_CSIENS RCC_APB5ENSR_CSIENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENSR register *****************/ +#define RCC_BUSLPENSR_ACLKNLPENS_Pos (0UL) +#define RCC_BUSLPENSR_ACLKNLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENSR_ACLKNLPENS RCC_BUSLPENSR_ACLKNLPENS_Msk /*!< ACLKN enable */ +#define RCC_BUSLPENSR_ACLKNCLPENS_Pos (1UL) +#define RCC_BUSLPENSR_ACLKNCLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENSR_ACLKNCLPENS RCC_BUSLPENSR_ACLKNCLPENS_Msk /*!< ACLKNC enable */ + +/**************** Bit definition for RCC_MISCLPENSR register ****************/ +#define RCC_MISCLPENSR_DBGLPENS_Pos (0UL) +#define RCC_MISCLPENSR_DBGLPENS_Msk (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENSR_DBGLPENS RCC_MISCLPENSR_DBGLPENS_Msk /*!< DBG enable */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos (3UL) +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCLPENSR_PERLPENS_Pos (6UL) +#define RCC_MISCLPENSR_PERLPENS_Msk (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENSR_PERLPENS RCC_MISCLPENSR_PERLPENS_Msk /*!< PER enable */ + +/**************** Bit definition for RCC_MEMLPENSR register *****************/ +#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos (0UL) +#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENSR_AXISRAM3LPENS RCC_MEMLPENSR_AXISRAM3LPENS_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos (1UL) +#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENSR_AXISRAM4LPENS RCC_MEMLPENSR_AXISRAM4LPENS_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos (2UL) +#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENSR_AXISRAM5LPENS RCC_MEMLPENSR_AXISRAM5LPENS_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos (3UL) +#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENSR_AXISRAM6LPENS RCC_MEMLPENSR_AXISRAM6LPENS_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos (4UL) +#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENSR_AHBSRAM1LPENS RCC_MEMLPENSR_AHBSRAM1LPENS_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos (5UL) +#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENSR_AHBSRAM2LPENS RCC_MEMLPENSR_AHBSRAM2LPENS_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos (6UL) +#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENSR_BKPSRAMLPENS RCC_MEMLPENSR_BKPSRAMLPENS_Msk /*!< BKPSRAM enable */ +#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos (7UL) +#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENSR_AXISRAM1LPENS RCC_MEMLPENSR_AXISRAM1LPENS_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos (8UL) +#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENSR_AXISRAM2LPENS RCC_MEMLPENSR_AXISRAM2LPENS_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos (9UL) +#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENSR_FLEXRAMLPENS RCC_MEMLPENSR_FLEXRAMLPENS_Msk /*!< FLEXRAM enable */ +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos (10UL) +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENSR_CACHEAXIRAMLPENS RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMLPENSR_VENCRAMLPENS_Pos (11UL) +#define RCC_MEMLPENSR_VENCRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENSR_VENCRAMLPENS RCC_MEMLPENSR_VENCRAMLPENS_Msk /*!< VENCRAM enable */ +#define RCC_MEMLPENSR_BOOTROMLPENS_Pos (12UL) +#define RCC_MEMLPENSR_BOOTROMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENSR_BOOTROMLPENS RCC_MEMLPENSR_BOOTROMLPENS_Msk /*!< Boot ROM enable */ + +/**************** Bit definition for RCC_AHB1LPENSR register ****************/ +#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos (4UL) +#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENSR_GPDMA1LPENS RCC_AHB1LPENSR_GPDMA1LPENS_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1LPENSR_ADC12LPENS_Pos (5UL) +#define RCC_AHB1LPENSR_ADC12LPENS_Msk (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENSR_ADC12LPENS RCC_AHB1LPENSR_ADC12LPENS_Msk /*!< ADC12 enable */ + +/**************** Bit definition for RCC_AHB2LPENSR register ****************/ +#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos (12UL) +#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENSR_RAMCFGLPENS RCC_AHB2LPENSR_RAMCFGLPENS_Msk /*!< RAMCFG enable */ +#define RCC_AHB2LPENSR_MDF1LPENS_Pos (16UL) +#define RCC_AHB2LPENSR_MDF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENSR_MDF1LPENS RCC_AHB2LPENSR_MDF1LPENS_Msk /*!< MDF1 enable */ +#define RCC_AHB2LPENSR_ADF1LPENS_Pos (17UL) +#define RCC_AHB2LPENSR_ADF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENSR_ADF1LPENS RCC_AHB2LPENSR_ADF1LPENS_Msk /*!< ADF1 enable */ + +/**************** Bit definition for RCC_AHB3LPENSR register ****************/ +#define RCC_AHB3LPENSR_RNGLPENS_Pos (0UL) +#define RCC_AHB3LPENSR_RNGLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENSR_RNGLPENS RCC_AHB3LPENSR_RNGLPENS_Msk /*!< RNG enable */ +#define RCC_AHB3LPENSR_HASHLPENS_Pos (1UL) +#define RCC_AHB3LPENSR_HASHLPENS_Msk (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENSR_HASHLPENS RCC_AHB3LPENSR_HASHLPENS_Msk /*!< HASH enable */ +#define RCC_AHB3LPENSR_CRYPLPENS_Pos (2UL) +#define RCC_AHB3LPENSR_CRYPLPENS_Msk (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENSR_CRYPLPENS RCC_AHB3LPENSR_CRYPLPENS_Msk /*!< CRYP enable */ +#define RCC_AHB3LPENSR_SAESLPENS_Pos (4UL) +#define RCC_AHB3LPENSR_SAESLPENS_Msk (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENSR_SAESLPENS RCC_AHB3LPENSR_SAESLPENS_Msk /*!< SAES enable */ +#define RCC_AHB3LPENSR_PKALPENS_Pos (8UL) +#define RCC_AHB3LPENSR_PKALPENS_Msk (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENSR_PKALPENS RCC_AHB3LPENSR_PKALPENS_Msk /*!< PKA enable */ +#define RCC_AHB3LPENSR_RIFSCLPENS_Pos (9UL) +#define RCC_AHB3LPENSR_RIFSCLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENSR_RIFSCLPENS RCC_AHB3LPENSR_RIFSCLPENS_Msk /*!< RIFSC enable */ +#define RCC_AHB3LPENSR_IACLPENS_Pos (10UL) +#define RCC_AHB3LPENSR_IACLPENS_Msk (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENSR_IACLPENS RCC_AHB3LPENSR_IACLPENS_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENSR_RISAFLPENS_Pos (14UL) +#define RCC_AHB3LPENSR_RISAFLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENSR_RISAFLPENS RCC_AHB3LPENSR_RISAFLPENS_Msk /*!< RISAF enable */ + +/**************** Bit definition for RCC_AHB4LPENSR register ****************/ +#define RCC_AHB4LPENSR_GPIOALPENS_Pos (0UL) +#define RCC_AHB4LPENSR_GPIOALPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENSR_GPIOALPENS RCC_AHB4LPENSR_GPIOALPENS_Msk /*!< GPIO A enable */ +#define RCC_AHB4LPENSR_GPIOBLPENS_Pos (1UL) +#define RCC_AHB4LPENSR_GPIOBLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENSR_GPIOBLPENS RCC_AHB4LPENSR_GPIOBLPENS_Msk /*!< GPIO B enable */ +#define RCC_AHB4LPENSR_GPIOCLPENS_Pos (2UL) +#define RCC_AHB4LPENSR_GPIOCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENSR_GPIOCLPENS RCC_AHB4LPENSR_GPIOCLPENS_Msk /*!< GPIO C enable */ +#define RCC_AHB4LPENSR_GPIODLPENS_Pos (3UL) +#define RCC_AHB4LPENSR_GPIODLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENSR_GPIODLPENS RCC_AHB4LPENSR_GPIODLPENS_Msk /*!< GPIO D enable */ +#define RCC_AHB4LPENSR_GPIOELPENS_Pos (4UL) +#define RCC_AHB4LPENSR_GPIOELPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENSR_GPIOELPENS RCC_AHB4LPENSR_GPIOELPENS_Msk /*!< GPIO E enable */ +#define RCC_AHB4LPENSR_GPIOFLPENS_Pos (5UL) +#define RCC_AHB4LPENSR_GPIOFLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENSR_GPIOFLPENS RCC_AHB4LPENSR_GPIOFLPENS_Msk /*!< GPIO F enable */ +#define RCC_AHB4LPENSR_GPIOGLPENS_Pos (6UL) +#define RCC_AHB4LPENSR_GPIOGLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENSR_GPIOGLPENS RCC_AHB4LPENSR_GPIOGLPENS_Msk /*!< GPIO G enable */ +#define RCC_AHB4LPENSR_GPIOHLPENS_Pos (7UL) +#define RCC_AHB4LPENSR_GPIOHLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENSR_GPIOHLPENS RCC_AHB4LPENSR_GPIOHLPENS_Msk /*!< GPIO H enable */ +#define RCC_AHB4LPENSR_GPIONLPENS_Pos (13UL) +#define RCC_AHB4LPENSR_GPIONLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENSR_GPIONLPENS RCC_AHB4LPENSR_GPIONLPENS_Msk /*!< GPIO N enable */ +#define RCC_AHB4LPENSR_GPIOOLPENS_Pos (14UL) +#define RCC_AHB4LPENSR_GPIOOLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENSR_GPIOOLPENS RCC_AHB4LPENSR_GPIOOLPENS_Msk /*!< GPIO O enable */ +#define RCC_AHB4LPENSR_GPIOPLPENS_Pos (15UL) +#define RCC_AHB4LPENSR_GPIOPLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENSR_GPIOPLPENS RCC_AHB4LPENSR_GPIOPLPENS_Msk /*!< GPIO P enable */ +#define RCC_AHB4LPENSR_GPIOQLPENS_Pos (16UL) +#define RCC_AHB4LPENSR_GPIOQLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENSR_GPIOQLPENS RCC_AHB4LPENSR_GPIOQLPENS_Msk /*!< GPIO Q enable */ +#define RCC_AHB4LPENSR_PWRLPENS_Pos (18UL) +#define RCC_AHB4LPENSR_PWRLPENS_Msk (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENSR_PWRLPENS RCC_AHB4LPENSR_PWRLPENS_Msk /*!< PWR enable */ +#define RCC_AHB4LPENSR_CRCLPENS_Pos (19UL) +#define RCC_AHB4LPENSR_CRCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENSR_CRCLPENS RCC_AHB4LPENSR_CRCLPENS_Msk /*!< CRC enable */ + +/**************** Bit definition for RCC_AHB5LPENSR register ****************/ +#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos (0UL) +#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENSR_HPDMA1LPENS RCC_AHB5LPENSR_HPDMA1LPENS_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5LPENSR_DMA2DLPENS_Pos (1UL) +#define RCC_AHB5LPENSR_DMA2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENSR_DMA2DLPENS RCC_AHB5LPENSR_DMA2DLPENS_Msk /*!< DMA2D enable */ +#define RCC_AHB5LPENSR_JPEGLPENS_Pos (3UL) +#define RCC_AHB5LPENSR_JPEGLPENS_Msk (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENSR_JPEGLPENS RCC_AHB5LPENSR_JPEGLPENS_Msk /*!< JPEG enable */ +#define RCC_AHB5LPENSR_FMCLPENS_Pos (4UL) +#define RCC_AHB5LPENSR_FMCLPENS_Msk (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENSR_FMCLPENS RCC_AHB5LPENSR_FMCLPENS_Msk /*!< FMC enable */ +#define RCC_AHB5LPENSR_XSPI1LPENS_Pos (5UL) +#define RCC_AHB5LPENSR_XSPI1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENSR_XSPI1LPENS RCC_AHB5LPENSR_XSPI1LPENS_Msk /*!< XSPI1 enable */ +#define RCC_AHB5LPENSR_PSSILPENS_Pos (6UL) +#define RCC_AHB5LPENSR_PSSILPENS_Msk (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENSR_PSSILPENS RCC_AHB5LPENSR_PSSILPENS_Msk /*!< PSSI enable */ +#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos (7UL) +#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENSR_SDMMC2LPENS RCC_AHB5LPENSR_SDMMC2LPENS_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos (8UL) +#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENSR_SDMMC1LPENS RCC_AHB5LPENSR_SDMMC1LPENS_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5LPENSR_XSPI2LPENS_Pos (12UL) +#define RCC_AHB5LPENSR_XSPI2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENSR_XSPI2LPENS RCC_AHB5LPENSR_XSPI2LPENS_Msk /*!< XSPI2 enable */ +#define RCC_AHB5LPENSR_XSPIMLPENS_Pos (13UL) +#define RCC_AHB5LPENSR_XSPIMLPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENSR_XSPIMLPENS RCC_AHB5LPENSR_XSPIMLPENS_Msk /*!< XSPIM enable */ +#define RCC_AHB5LPENSR_MCE1LPENS_Pos (14UL) +#define RCC_AHB5LPENSR_MCE1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENSR_MCE1LPENS RCC_AHB5LPENSR_MCE1LPENS_Msk /*!< MCE1 enable */ +#define RCC_AHB5LPENSR_MCE2LPENS_Pos (15UL) +#define RCC_AHB5LPENSR_MCE2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENSR_MCE2LPENS RCC_AHB5LPENSR_MCE2LPENS_Msk /*!< MCE2 enable */ +#define RCC_AHB5LPENSR_MCE3LPENS_Pos (16UL) +#define RCC_AHB5LPENSR_MCE3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENSR_MCE3LPENS RCC_AHB5LPENSR_MCE3LPENS_Msk /*!< MCE3 enable */ +#define RCC_AHB5LPENSR_XSPI3LPENS_Pos (17UL) +#define RCC_AHB5LPENSR_XSPI3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENSR_XSPI3LPENS RCC_AHB5LPENSR_XSPI3LPENS_Msk /*!< XSPI3 enable */ +#define RCC_AHB5LPENSR_MCE4LPENS_Pos (18UL) +#define RCC_AHB5LPENSR_MCE4LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENSR_MCE4LPENS RCC_AHB5LPENSR_MCE4LPENS_Msk /*!< MCE4 enable */ +#define RCC_AHB5LPENSR_GFXMMULPENS_Pos (19UL) +#define RCC_AHB5LPENSR_GFXMMULPENS_Msk (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENSR_GFXMMULPENS RCC_AHB5LPENSR_GFXMMULPENS_Msk /*!< GFXMMU enable */ +#define RCC_AHB5LPENSR_GPU2DLPENS_Pos (20UL) +#define RCC_AHB5LPENSR_GPU2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENSR_GPU2DLPENS RCC_AHB5LPENSR_GPU2DLPENS_Msk /*!< GPU2D enable */ +#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos (22UL) +#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENSR_ETH1MACLPENS RCC_AHB5LPENSR_ETH1MACLPENS_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos (23UL) +#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENSR_ETH1TXLPENS RCC_AHB5LPENSR_ETH1TXLPENS_Msk /*!< ETH1TX enable */ +#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos (24UL) +#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENSR_ETH1RXLPENS RCC_AHB5LPENSR_ETH1RXLPENS_Msk /*!< ETH1RX enable */ +#define RCC_AHB5LPENSR_ETH1LPENS_Pos (25UL) +#define RCC_AHB5LPENSR_ETH1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENSR_ETH1LPENS RCC_AHB5LPENSR_ETH1LPENS_Msk /*!< ETH1 enable */ +#define RCC_AHB5LPENSR_OTG1LPENS_Pos (26UL) +#define RCC_AHB5LPENSR_OTG1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENSR_OTG1LPENS RCC_AHB5LPENSR_OTG1LPENS_Msk /*!< OTG1 enable */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos (27UL) +#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENSR_OTGPHY1LPENS RCC_AHB5LPENSR_OTGPHY1LPENS_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos (28UL) +#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENSR_OTGPHY2LPENS RCC_AHB5LPENSR_OTGPHY2LPENS_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5LPENSR_OTG2LPENS_Pos (29UL) +#define RCC_AHB5LPENSR_OTG2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENSR_OTG2LPENS RCC_AHB5LPENSR_OTG2LPENS_Msk /*!< OTG2 enable */ +#define RCC_AHB5LPENSR_CACHEAXILPENS_Pos (30UL) +#define RCC_AHB5LPENSR_CACHEAXILPENS_Msk (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENSR_CACHEAXILPENS RCC_AHB5LPENSR_CACHEAXILPENS_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5LPENSR_NPULPENS_Pos (31UL) +#define RCC_AHB5LPENSR_NPULPENS_Msk (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */ +#define RCC_AHB5LPENSR_NPULPENS RCC_AHB5LPENSR_NPULPENS_Msk /*!< NPU enable */ + +/*************** Bit definition for RCC_APB1LPENSR1 register ****************/ +#define RCC_APB1LPENSR1_TIM2LPENS_Pos (0UL) +#define RCC_APB1LPENSR1_TIM2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENSR1_TIM2LPENS RCC_APB1LPENSR1_TIM2LPENS_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENSR1_TIM3LPENS_Pos (1UL) +#define RCC_APB1LPENSR1_TIM3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENSR1_TIM3LPENS RCC_APB1LPENSR1_TIM3LPENS_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENSR1_TIM4LPENS_Pos (2UL) +#define RCC_APB1LPENSR1_TIM4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENSR1_TIM4LPENS RCC_APB1LPENSR1_TIM4LPENS_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENSR1_TIM5LPENS_Pos (3UL) +#define RCC_APB1LPENSR1_TIM5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENSR1_TIM5LPENS RCC_APB1LPENSR1_TIM5LPENS_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENSR1_TIM6LPENS_Pos (4UL) +#define RCC_APB1LPENSR1_TIM6LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENSR1_TIM6LPENS RCC_APB1LPENSR1_TIM6LPENS_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENSR1_TIM7LPENS_Pos (5UL) +#define RCC_APB1LPENSR1_TIM7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR1_TIM7LPENS RCC_APB1LPENSR1_TIM7LPENS_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENSR1_TIM12LPENS_Pos (6UL) +#define RCC_APB1LPENSR1_TIM12LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENSR1_TIM12LPENS RCC_APB1LPENSR1_TIM12LPENS_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENSR1_TIM13LPENS_Pos (7UL) +#define RCC_APB1LPENSR1_TIM13LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENSR1_TIM13LPENS RCC_APB1LPENSR1_TIM13LPENS_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENSR1_TIM14LPENS_Pos (8UL) +#define RCC_APB1LPENSR1_TIM14LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR1_TIM14LPENS RCC_APB1LPENSR1_TIM14LPENS_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos (9UL) +#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENSR1_LPTIM1LPENS RCC_APB1LPENSR1_LPTIM1LPENS_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENSR1_WWDGLPENS_Pos (11UL) +#define RCC_APB1LPENSR1_WWDGLPENS_Msk (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENSR1_WWDGLPENS RCC_APB1LPENSR1_WWDGLPENS_Msk /*!< WWDG enable */ +#define RCC_APB1LPENSR1_TIM10LPENS_Pos (12UL) +#define RCC_APB1LPENSR1_TIM10LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENSR1_TIM10LPENS RCC_APB1LPENSR1_TIM10LPENS_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENSR1_TIM11LPENS_Pos (13UL) +#define RCC_APB1LPENSR1_TIM11LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENSR1_TIM11LPENS RCC_APB1LPENSR1_TIM11LPENS_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENSR1_SPI2LPENS_Pos (14UL) +#define RCC_APB1LPENSR1_SPI2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENSR1_SPI2LPENS RCC_APB1LPENSR1_SPI2LPENS_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENSR1_SPI3LPENS_Pos (15UL) +#define RCC_APB1LPENSR1_SPI3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENSR1_SPI3LPENS RCC_APB1LPENSR1_SPI3LPENS_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos (16UL) +#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENSR1_SPDIFRX1LPENS RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENSR1_USART2LPENS_Pos (17UL) +#define RCC_APB1LPENSR1_USART2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENSR1_USART2LPENS RCC_APB1LPENSR1_USART2LPENS_Msk /*!< USART2 enable */ +#define RCC_APB1LPENSR1_USART3LPENS_Pos (18UL) +#define RCC_APB1LPENSR1_USART3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR1_USART3LPENS RCC_APB1LPENSR1_USART3LPENS_Msk /*!< USART3 enable */ +#define RCC_APB1LPENSR1_UART4LPENS_Pos (19UL) +#define RCC_APB1LPENSR1_UART4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENSR1_UART4LPENS RCC_APB1LPENSR1_UART4LPENS_Msk /*!< UART4 enable */ +#define RCC_APB1LPENSR1_UART5LPENS_Pos (20UL) +#define RCC_APB1LPENSR1_UART5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENSR1_UART5LPENS RCC_APB1LPENSR1_UART5LPENS_Msk /*!< UART5 enable */ +#define RCC_APB1LPENSR1_I2C1LPENS_Pos (21UL) +#define RCC_APB1LPENSR1_I2C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENSR1_I2C1LPENS RCC_APB1LPENSR1_I2C1LPENS_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENSR1_I2C2LPENS_Pos (22UL) +#define RCC_APB1LPENSR1_I2C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENSR1_I2C2LPENS RCC_APB1LPENSR1_I2C2LPENS_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENSR1_I2C3LPENS_Pos (23UL) +#define RCC_APB1LPENSR1_I2C3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENSR1_I2C3LPENS RCC_APB1LPENSR1_I2C3LPENS_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENSR1_I3C1LPENS_Pos (24UL) +#define RCC_APB1LPENSR1_I3C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENSR1_I3C1LPENS RCC_APB1LPENSR1_I3C1LPENS_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENSR1_I3C2LPENS_Pos (25UL) +#define RCC_APB1LPENSR1_I3C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENSR1_I3C2LPENS RCC_APB1LPENSR1_I3C2LPENS_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENSR1_UART7LPENS_Pos (30UL) +#define RCC_APB1LPENSR1_UART7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENSR1_UART7LPENS RCC_APB1LPENSR1_UART7LPENS_Msk /*!< UART7 enable */ +#define RCC_APB1LPENSR1_UART8LPENS_Pos (31UL) +#define RCC_APB1LPENSR1_UART8LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENSR1_UART8LPENS RCC_APB1LPENSR1_UART8LPENS_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENSR2 register ****************/ +#define RCC_APB1LPENSR2_MDIOSLPENS_Pos (5UL) +#define RCC_APB1LPENSR2_MDIOSLPENS_Msk (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENSR2_MDIOSLPENS RCC_APB1LPENSR2_MDIOSLPENS_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENSR2_FDCANLPENS_Pos (8UL) +#define RCC_APB1LPENSR2_FDCANLPENS_Msk (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENSR2_FDCANLPENS RCC_APB1LPENSR2_FDCANLPENS_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENSR2_UCPD1LPENS_Pos (18UL) +#define RCC_APB1LPENSR2_UCPD1LPENS_Msk (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENSR2_UCPD1LPENS RCC_APB1LPENSR2_UCPD1LPENS_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENSR register ****************/ +#define RCC_APB2LPENSR_TIM1LPENS_Pos (0UL) +#define RCC_APB2LPENSR_TIM1LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENSR_TIM1LPENS RCC_APB2LPENSR_TIM1LPENS_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENSR_TIM8LPENS_Pos (1UL) +#define RCC_APB2LPENSR_TIM8LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENSR_TIM8LPENS RCC_APB2LPENSR_TIM8LPENS_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENSR_USART1LPENS_Pos (4UL) +#define RCC_APB2LPENSR_USART1LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENSR_USART1LPENS RCC_APB2LPENSR_USART1LPENS_Msk /*!< USART1 enable */ +#define RCC_APB2LPENSR_USART6LPENS_Pos (5UL) +#define RCC_APB2LPENSR_USART6LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENSR_USART6LPENS RCC_APB2LPENSR_USART6LPENS_Msk /*!< USART6 enable */ +#define RCC_APB2LPENSR_UART9LPENS_Pos (6UL) +#define RCC_APB2LPENSR_UART9LPENS_Msk (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENSR_UART9LPENS RCC_APB2LPENSR_UART9LPENS_Msk /*!< UART9 enable */ +#define RCC_APB2LPENSR_USART10LPENS_Pos (7UL) +#define RCC_APB2LPENSR_USART10LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENSR_USART10LPENS RCC_APB2LPENSR_USART10LPENS_Msk /*!< USART10 enable */ +#define RCC_APB2LPENSR_SPI1LPENS_Pos (12UL) +#define RCC_APB2LPENSR_SPI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENSR_SPI1LPENS RCC_APB2LPENSR_SPI1LPENS_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENSR_SPI4LPENS_Pos (13UL) +#define RCC_APB2LPENSR_SPI4LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENSR_SPI4LPENS RCC_APB2LPENSR_SPI4LPENS_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENSR_TIM18LPENS_Pos (15UL) +#define RCC_APB2LPENSR_TIM18LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENSR_TIM18LPENS RCC_APB2LPENSR_TIM18LPENS_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENSR_TIM15LPENS_Pos (16UL) +#define RCC_APB2LPENSR_TIM15LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENSR_TIM15LPENS RCC_APB2LPENSR_TIM15LPENS_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENSR_TIM16LPENS_Pos (17UL) +#define RCC_APB2LPENSR_TIM16LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENSR_TIM16LPENS RCC_APB2LPENSR_TIM16LPENS_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENSR_TIM17LPENS_Pos (18UL) +#define RCC_APB2LPENSR_TIM17LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENSR_TIM17LPENS RCC_APB2LPENSR_TIM17LPENS_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENSR_TIM9LPENS_Pos (19UL) +#define RCC_APB2LPENSR_TIM9LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENSR_TIM9LPENS RCC_APB2LPENSR_TIM9LPENS_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENSR_SPI5LPENS_Pos (20UL) +#define RCC_APB2LPENSR_SPI5LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENSR_SPI5LPENS RCC_APB2LPENSR_SPI5LPENS_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENSR_SAI1LPENS_Pos (21UL) +#define RCC_APB2LPENSR_SAI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENSR_SAI1LPENS RCC_APB2LPENSR_SAI1LPENS_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENSR_SAI2LPENS_Pos (22UL) +#define RCC_APB2LPENSR_SAI2LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENSR_SAI2LPENS RCC_APB2LPENSR_SAI2LPENS_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENSR register ****************/ +#define RCC_APB3LPENSR_DFTLPENS_Pos (2UL) +#define RCC_APB3LPENSR_DFTLPENS_Msk (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENSR_DFTLPENS RCC_APB3LPENSR_DFTLPENS_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENSR1 register ****************/ +#define RCC_APB4LPENSR1_HDPLPENS_Pos (2UL) +#define RCC_APB4LPENSR1_HDPLPENS_Msk (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR1_HDPLPENS RCC_APB4LPENSR1_HDPLPENS_Msk /*!< HDP enable */ +#define RCC_APB4LPENSR1_LPUART1LPENS_Pos (3UL) +#define RCC_APB4LPENSR1_LPUART1LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENSR1_LPUART1LPENS RCC_APB4LPENSR1_LPUART1LPENS_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENSR1_SPI6LPENS_Pos (5UL) +#define RCC_APB4LPENSR1_SPI6LPENS_Msk (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENSR1_SPI6LPENS RCC_APB4LPENSR1_SPI6LPENS_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENSR1_I2C4LPENS_Pos (7UL) +#define RCC_APB4LPENSR1_I2C4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENSR1_I2C4LPENS RCC_APB4LPENSR1_I2C4LPENS_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos (9UL) +#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENSR1_LPTIM2LPENS RCC_APB4LPENSR1_LPTIM2LPENS_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos (10UL) +#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENSR1_LPTIM3LPENS RCC_APB4LPENSR1_LPTIM3LPENS_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos (11UL) +#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENSR1_LPTIM4LPENS RCC_APB4LPENSR1_LPTIM4LPENS_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos (12UL) +#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENSR1_LPTIM5LPENS RCC_APB4LPENSR1_LPTIM5LPENS_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos (15UL) +#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENSR1_VREFBUFLPENS RCC_APB4LPENSR1_VREFBUFLPENS_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENSR1_RTCLPENS_Pos (16UL) +#define RCC_APB4LPENSR1_RTCLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENSR1_RTCLPENS RCC_APB4LPENSR1_RTCLPENS_Msk /*!< RTC enable */ +#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos (17UL) +#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENSR1_RTCAPBLPENS RCC_APB4LPENSR1_RTCAPBLPENS_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENSR2 register ****************/ +#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos (0UL) +#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENSR2_SYSCFGLPENS RCC_APB4LPENSR2_SYSCFGLPENS_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENSR2_BSECLPENS_Pos (1UL) +#define RCC_APB4LPENSR2_BSECLPENS_Msk (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENSR2_BSECLPENS RCC_APB4LPENSR2_BSECLPENS_Msk /*!< BSEC enable */ +#define RCC_APB4LPENSR2_DTSLPENS_Pos (2UL) +#define RCC_APB4LPENSR2_DTSLPENS_Msk (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENSR2_DTSLPENS RCC_APB4LPENSR2_DTSLPENS_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENSR register ****************/ +#define RCC_APB5LPENSR_LTDCLPENS_Pos (1UL) +#define RCC_APB5LPENSR_LTDCLPENS_Msk (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENSR_LTDCLPENS RCC_APB5LPENSR_LTDCLPENS_Msk /*!< LTDC enable */ +#define RCC_APB5LPENSR_DCMIPPLPENS_Pos (2UL) +#define RCC_APB5LPENSR_DCMIPPLPENS_Msk (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENSR_DCMIPPLPENS RCC_APB5LPENSR_DCMIPPLPENS_Msk /*!< DCMIPP enable */ +#define RCC_APB5LPENSR_GFXTIMLPENS_Pos (4UL) +#define RCC_APB5LPENSR_GFXTIMLPENS_Msk (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENSR_GFXTIMLPENS RCC_APB5LPENSR_GFXTIMLPENS_Msk /*!< GFXTIM enable */ +#define RCC_APB5LPENSR_VENCLPENS_Pos (5UL) +#define RCC_APB5LPENSR_VENCLPENS_Msk (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENSR_VENCLPENS RCC_APB5LPENSR_VENCLPENS_Msk /*!< VENC enable */ +#define RCC_APB5LPENSR_CSILPENS_Pos (6UL) +#define RCC_APB5LPENSR_CSILPENS_Msk (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENSR_CSILPENS RCC_APB5LPENSR_CSILPENS_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_PRIVCFGSR0 register ****************/ +#define RCC_PRIVCFGSR0_LSIPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR0_LSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR0_LSIPRIVS RCC_PRIVCFGSR0_LSIPRIVS_Msk /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_LSEPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR0_LSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR0_LSEPRIVS RCC_PRIVCFGSR0_LSEPRIVS_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_MSIPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR0_MSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR0_MSIPRIVS RCC_PRIVCFGSR0_MSIPRIVS_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSIPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR0_HSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR0_HSIPRIVS RCC_PRIVCFGSR0_HSIPRIVS_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR0_HSEPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR0_HSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR0_HSEPRIVS RCC_PRIVCFGSR0_HSEPRIVS_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR0 register *****************/ +#define RCC_PUBCFGSR0_LSIPUBS_Pos (0UL) +#define RCC_PUBCFGSR0_LSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR0_LSIPUBS RCC_PUBCFGSR0_LSIPUBS_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_LSEPUBS_Pos (1UL) +#define RCC_PUBCFGSR0_LSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR0_LSEPUBS RCC_PUBCFGSR0_LSEPUBS_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_MSIPUBS_Pos (2UL) +#define RCC_PUBCFGSR0_MSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR0_MSIPUBS RCC_PUBCFGSR0_MSIPUBS_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSIPUBS_Pos (3UL) +#define RCC_PUBCFGSR0_HSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR0_HSIPUBS RCC_PUBCFGSR0_HSIPUBS_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR0_HSEPUBS_Pos (4UL) +#define RCC_PUBCFGSR0_HSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR0_HSEPUBS RCC_PUBCFGSR0_HSEPUBS_Msk /*!< Public protection of he HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR1 register ****************/ +#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR1_PLL1PRIVS RCC_PRIVCFGSR1_PLL1PRIVS_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR1_PLL2PRIVS RCC_PRIVCFGSR1_PLL2PRIVS_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR1_PLL3PRIVS RCC_PRIVCFGSR1_PLL3PRIVS_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR1_PLL4PRIVS RCC_PRIVCFGSR1_PLL4PRIVS_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR1 register *****************/ +#define RCC_PUBCFGSR1_PLL1PUBS_Pos (0UL) +#define RCC_PUBCFGSR1_PLL1PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR1_PLL1PUBS RCC_PUBCFGSR1_PLL1PUBS_Msk /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL2PUBS_Pos (1UL) +#define RCC_PUBCFGSR1_PLL2PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR1_PLL2PUBS RCC_PUBCFGSR1_PLL2PUBS_Msk /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL3PUBS_Pos (2UL) +#define RCC_PUBCFGSR1_PLL3PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR1_PLL3PUBS RCC_PUBCFGSR1_PLL3PUBS_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR1_PLL4PUBS_Pos (3UL) +#define RCC_PUBCFGSR1_PLL4PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR1_PLL4PUBS RCC_PUBCFGSR1_PLL4PUBS_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR2 register ****************/ +#define RCC_PRIVCFGSR2_IC1PRIVS_Pos (0UL) +#define RCC_PRIVCFGSR2_IC1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR2_IC1PRIVS RCC_PRIVCFGSR2_IC1PRIVS_Msk /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC2PRIVS_Pos (1UL) +#define RCC_PRIVCFGSR2_IC2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR2_IC2PRIVS RCC_PRIVCFGSR2_IC2PRIVS_Msk /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC3PRIVS_Pos (2UL) +#define RCC_PRIVCFGSR2_IC3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR2_IC3PRIVS RCC_PRIVCFGSR2_IC3PRIVS_Msk /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC4PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR2_IC4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR2_IC4PRIVS RCC_PRIVCFGSR2_IC4PRIVS_Msk /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC5PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR2_IC5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR2_IC5PRIVS RCC_PRIVCFGSR2_IC5PRIVS_Msk /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC6PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR2_IC6PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR2_IC6PRIVS RCC_PRIVCFGSR2_IC6PRIVS_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC7PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR2_IC7PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGSR2_IC7PRIVS RCC_PRIVCFGSR2_IC7PRIVS_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC8PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR2_IC8PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGSR2_IC8PRIVS RCC_PRIVCFGSR2_IC8PRIVS_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC9PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR2_IC9PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGSR2_IC9PRIVS RCC_PRIVCFGSR2_IC9PRIVS_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC10PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR2_IC10PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR2_IC10PRIVS RCC_PRIVCFGSR2_IC10PRIVS_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC11PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR2_IC11PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR2_IC11PRIVS RCC_PRIVCFGSR2_IC11PRIVS_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC12PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR2_IC12PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR2_IC12PRIVS RCC_PRIVCFGSR2_IC12PRIVS_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC13PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR2_IC13PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR2_IC13PRIVS RCC_PRIVCFGSR2_IC13PRIVS_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC14PRIVS_Pos (13UL) +#define RCC_PRIVCFGSR2_IC14PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGSR2_IC14PRIVS RCC_PRIVCFGSR2_IC14PRIVS_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC15PRIVS_Pos (14UL) +#define RCC_PRIVCFGSR2_IC15PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGSR2_IC15PRIVS RCC_PRIVCFGSR2_IC15PRIVS_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC16PRIVS_Pos (15UL) +#define RCC_PRIVCFGSR2_IC16PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGSR2_IC16PRIVS RCC_PRIVCFGSR2_IC16PRIVS_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC17PRIVS_Pos (16UL) +#define RCC_PRIVCFGSR2_IC17PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGSR2_IC17PRIVS RCC_PRIVCFGSR2_IC17PRIVS_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC18PRIVS_Pos (17UL) +#define RCC_PRIVCFGSR2_IC18PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGSR2_IC18PRIVS RCC_PRIVCFGSR2_IC18PRIVS_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC19PRIVS_Pos (18UL) +#define RCC_PRIVCFGSR2_IC19PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGSR2_IC19PRIVS RCC_PRIVCFGSR2_IC19PRIVS_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR2_IC20PRIVS_Pos (19UL) +#define RCC_PRIVCFGSR2_IC20PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGSR2_IC20PRIVS RCC_PRIVCFGSR2_IC20PRIVS_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR2 register *****************/ +#define RCC_PUBCFGSR2_IC1PUBS_Pos (0UL) +#define RCC_PUBCFGSR2_IC1PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR2_IC1PUBS RCC_PUBCFGSR2_IC1PUBS_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC2PUBS_Pos (1UL) +#define RCC_PUBCFGSR2_IC2PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR2_IC2PUBS RCC_PUBCFGSR2_IC2PUBS_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC3PUBS_Pos (2UL) +#define RCC_PUBCFGSR2_IC3PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR2_IC3PUBS RCC_PUBCFGSR2_IC3PUBS_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC4PUBS_Pos (3UL) +#define RCC_PUBCFGSR2_IC4PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR2_IC4PUBS RCC_PUBCFGSR2_IC4PUBS_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC5PUBS_Pos (4UL) +#define RCC_PUBCFGSR2_IC5PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR2_IC5PUBS RCC_PUBCFGSR2_IC5PUBS_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC6PUBS_Pos (5UL) +#define RCC_PUBCFGSR2_IC6PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR2_IC6PUBS RCC_PUBCFGSR2_IC6PUBS_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC7PUBS_Pos (6UL) +#define RCC_PUBCFGSR2_IC7PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR2_IC7PUBS RCC_PUBCFGSR2_IC7PUBS_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC8PUBS_Pos (7UL) +#define RCC_PUBCFGSR2_IC8PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR2_IC8PUBS RCC_PUBCFGSR2_IC8PUBS_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC9PUBS_Pos (8UL) +#define RCC_PUBCFGSR2_IC9PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR2_IC9PUBS RCC_PUBCFGSR2_IC9PUBS_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC10PUBS_Pos (9UL) +#define RCC_PUBCFGSR2_IC10PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR2_IC10PUBS RCC_PUBCFGSR2_IC10PUBS_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC11PUBS_Pos (10UL) +#define RCC_PUBCFGSR2_IC11PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR2_IC11PUBS RCC_PUBCFGSR2_IC11PUBS_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC12PUBS_Pos (11UL) +#define RCC_PUBCFGSR2_IC12PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR2_IC12PUBS RCC_PUBCFGSR2_IC12PUBS_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC13PUBS_Pos (12UL) +#define RCC_PUBCFGSR2_IC13PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR2_IC13PUBS RCC_PUBCFGSR2_IC13PUBS_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC14PUBS_Pos (13UL) +#define RCC_PUBCFGSR2_IC14PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR2_IC14PUBS RCC_PUBCFGSR2_IC14PUBS_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC15PUBS_Pos (14UL) +#define RCC_PUBCFGSR2_IC15PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGSR2_IC15PUBS RCC_PUBCFGSR2_IC15PUBS_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC16PUBS_Pos (15UL) +#define RCC_PUBCFGSR2_IC16PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGSR2_IC16PUBS RCC_PUBCFGSR2_IC16PUBS_Msk /*!< Public protection of th IC16 configuration bits (enable, ready, divider */ +#define RCC_PUBCFGSR2_IC17PUBS_Pos (16UL) +#define RCC_PUBCFGSR2_IC17PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGSR2_IC17PUBS RCC_PUBCFGSR2_IC17PUBS_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC18PUBS_Pos (17UL) +#define RCC_PUBCFGSR2_IC18PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGSR2_IC18PUBS RCC_PUBCFGSR2_IC18PUBS_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC19PUBS_Pos (18UL) +#define RCC_PUBCFGSR2_IC19PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGSR2_IC19PUBS RCC_PUBCFGSR2_IC19PUBS_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR2_IC20PUBS_Pos (19UL) +#define RCC_PUBCFGSR2_IC20PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGSR2_IC20PUBS RCC_PUBCFGSR2_IC20PUBS_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR3 register ****************/ +#define RCC_PRIVCFGSR3_MODPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR3_MODPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGSR3_MODPRIVS RCC_PRIVCFGSR3_MODPRIVS_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_SYSPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR3_SYSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGSR3_SYSPRIVS RCC_PRIVCFGSR3_SYSPRIVS_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_BUSPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR3_BUSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGSR3_BUSPRIVS RCC_PRIVCFGSR3_BUSPRIVS_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_PERPRIVS_Pos (3UL) +#define RCC_PRIVCFGSR3_PERPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGSR3_PERPRIVS RCC_PRIVCFGSR3_PERPRIVS_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_INTPRIVS_Pos (4UL) +#define RCC_PRIVCFGSR3_INTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGSR3_INTPRIVS RCC_PRIVCFGSR3_INTPRIVS_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR3_RSTPRIVS_Pos (5UL) +#define RCC_PRIVCFGSR3_RSTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGSR3_RSTPRIVS RCC_PRIVCFGSR3_RSTPRIVS_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR3 register *****************/ +#define RCC_PUBCFGSR3_MODPUBS_Pos (0UL) +#define RCC_PUBCFGSR3_MODPUBS_Msk (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR3_MODPUBS RCC_PUBCFGSR3_MODPUBS_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_SYSPUBS_Pos (1UL) +#define RCC_PUBCFGSR3_SYSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR3_SYSPUBS RCC_PUBCFGSR3_SYSPUBS_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_BUSPUBS_Pos (2UL) +#define RCC_PUBCFGSR3_BUSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR3_BUSPUBS RCC_PUBCFGSR3_BUSPUBS_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_PERPUBS_Pos (3UL) +#define RCC_PUBCFGSR3_PERPUBS_Msk (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR3_PERPUBS RCC_PUBCFGSR3_PERPUBS_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_INTPUBS_Pos (4UL) +#define RCC_PUBCFGSR3_INTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR3_INTPUBS RCC_PUBCFGSR3_INTPUBS_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR3_RSTPUBS_Pos (5UL) +#define RCC_PUBCFGSR3_RSTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR3_RSTPUBS RCC_PUBCFGSR3_RSTPUBS_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGSR4 register ****************/ +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos (0UL) +#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGSR4_ACLKNPRIVS RCC_PRIVCFGSR4_ACLKNPRIVS_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos (1UL) +#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGSR4_ACLKNCPRIVS RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos (2UL) +#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGSR4_AHBMPRIVS RCC_PRIVCFGSR4_AHBMPRIVS_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos (3UL) +#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGSR4_AHB1PRIVS RCC_PRIVCFGSR4_AHB1PRIVS_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos (4UL) +#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGSR4_AHB2PRIVS RCC_PRIVCFGSR4_AHB2PRIVS_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos (5UL) +#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGSR4_AHB3PRIVS RCC_PRIVCFGSR4_AHB3PRIVS_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos (6UL) +#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGSR4_AHB4PRIVS RCC_PRIVCFGSR4_AHB4PRIVS_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos (7UL) +#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGSR4_AHB5PRIVS RCC_PRIVCFGSR4_AHB5PRIVS_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB1PRIVS_Pos (8UL) +#define RCC_PRIVCFGSR4_APB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGSR4_APB1PRIVS RCC_PRIVCFGSR4_APB1PRIVS_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB2PRIVS_Pos (9UL) +#define RCC_PRIVCFGSR4_APB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGSR4_APB2PRIVS RCC_PRIVCFGSR4_APB2PRIVS_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB3PRIVS_Pos (10UL) +#define RCC_PRIVCFGSR4_APB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGSR4_APB3PRIVS RCC_PRIVCFGSR4_APB3PRIVS_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB4PRIVS_Pos (11UL) +#define RCC_PRIVCFGSR4_APB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGSR4_APB4PRIVS RCC_PRIVCFGSR4_APB4PRIVS_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_APB5PRIVS_Pos (12UL) +#define RCC_PRIVCFGSR4_APB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGSR4_APB5PRIVS RCC_PRIVCFGSR4_APB5PRIVS_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGSR4_NOCPRIVS_Pos (13UL) +#define RCC_PRIVCFGSR4_NOCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGSR4_NOCPRIVS RCC_PRIVCFGSR4_NOCPRIVS_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR4 register *****************/ +#define RCC_PUBCFGSR4_ACLKNPUBS_Pos (0UL) +#define RCC_PUBCFGSR4_ACLKNPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGSR4_ACLKNPUBS RCC_PUBCFGSR4_ACLKNPUBS_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos (1UL) +#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR4_ACLKNCPUBS RCC_PUBCFGSR4_ACLKNCPUBS_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHBMPUBS_Pos (2UL) +#define RCC_PUBCFGSR4_AHBMPUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR4_AHBMPUBS RCC_PUBCFGSR4_AHBMPUBS_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB1PUBS_Pos (3UL) +#define RCC_PUBCFGSR4_AHB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR4_AHB1PUBS RCC_PUBCFGSR4_AHB1PUBS_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB2PUBS_Pos (4UL) +#define RCC_PUBCFGSR4_AHB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR4_AHB2PUBS RCC_PUBCFGSR4_AHB2PUBS_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB3PUBS_Pos (5UL) +#define RCC_PUBCFGSR4_AHB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR4_AHB3PUBS RCC_PUBCFGSR4_AHB3PUBS_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB4PUBS_Pos (6UL) +#define RCC_PUBCFGSR4_AHB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR4_AHB4PUBS RCC_PUBCFGSR4_AHB4PUBS_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_AHB5PUBS_Pos (7UL) +#define RCC_PUBCFGSR4_AHB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR4_AHB5PUBS RCC_PUBCFGSR4_AHB5PUBS_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB1PUBS_Pos (8UL) +#define RCC_PUBCFGSR4_APB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR4_APB1PUBS RCC_PUBCFGSR4_APB1PUBS_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB2PUBS_Pos (9UL) +#define RCC_PUBCFGSR4_APB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR4_APB2PUBS RCC_PUBCFGSR4_APB2PUBS_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB3PUBS_Pos (10UL) +#define RCC_PUBCFGSR4_APB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR4_APB3PUBS RCC_PUBCFGSR4_APB3PUBS_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB4PUBS_Pos (11UL) +#define RCC_PUBCFGSR4_APB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR4_APB4PUBS RCC_PUBCFGSR4_APB4PUBS_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_APB5PUBS_Pos (12UL) +#define RCC_PUBCFGSR4_APB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGSR4_APB5PUBS RCC_PUBCFGSR4_APB5PUBS_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR4_NOCPUBS_Pos (13UL) +#define RCC_PUBCFGSR4_NOCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGSR4_NOCPUBS RCC_PUBCFGSR4_NOCPUBS_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGSR5 register *****************/ +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos (0UL) +#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGSR5_AXISRAM3PUBS RCC_PUBCFGSR5_AXISRAM3PUBS_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos (1UL) +#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGSR5_AXISRAM4PUBS RCC_PUBCFGSR5_AXISRAM4PUBS_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos (2UL) +#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGSR5_AXISRAM5PUBS RCC_PUBCFGSR5_AXISRAM5PUBS_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos (3UL) +#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGSR5_AXISRAM6PUBS RCC_PUBCFGSR5_AXISRAM6PUBS_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos (4UL) +#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGSR5_AHBSRAM1PUBS RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos (5UL) +#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGSR5_AHBSRAM2PUBS RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos (6UL) +#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGSR5_BKPSRAMPUBS RCC_PUBCFGSR5_BKPSRAMPUBS_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos (7UL) +#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGSR5_AXISRAM1PUBS RCC_PUBCFGSR5_AXISRAM1PUBS_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos (8UL) +#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGSR5_AXISRAM2PUBS RCC_PUBCFGSR5_AXISRAM2PUBS_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos (9UL) +#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGSR5_FLEXRAMPUBS RCC_PUBCFGSR5_FLEXRAMPUBS_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos (10UL) +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos (11UL) +#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGSR5_VENCRAMPUBS RCC_PUBCFGSR5_VENCRAMPUBS_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + +/******************* Bit definition for RCC_CCR register ********************/ +#define RCC_CCR_LSIONC_Pos (0UL) +#define RCC_CCR_LSIONC_Msk (0x1UL << RCC_CCR_LSIONC_Pos) /*!< 0x00000001 */ +#define RCC_CCR_LSIONC RCC_CCR_LSIONC_Msk /*!< LSI oscillator enable */ +#define RCC_CCR_LSEONC_Pos (1UL) +#define RCC_CCR_LSEONC_Msk (0x1UL << RCC_CCR_LSEONC_Pos) /*!< 0x00000002 */ +#define RCC_CCR_LSEONC RCC_CCR_LSEONC_Msk /*!< LSE oscillator enable */ +#define RCC_CCR_MSIONC_Pos (2UL) +#define RCC_CCR_MSIONC_Msk (0x1UL << RCC_CCR_MSIONC_Pos) /*!< 0x00000004 */ +#define RCC_CCR_MSIONC RCC_CCR_MSIONC_Msk /*!< MSI oscillator enable */ +#define RCC_CCR_HSIONC_Pos (3UL) +#define RCC_CCR_HSIONC_Msk (0x1UL << RCC_CCR_HSIONC_Pos) /*!< 0x00000008 */ +#define RCC_CCR_HSIONC RCC_CCR_HSIONC_Msk /*!< HSI oscillator enable */ +#define RCC_CCR_HSEONC_Pos (4UL) +#define RCC_CCR_HSEONC_Msk (0x1UL << RCC_CCR_HSEONC_Pos) /*!< 0x00000010 */ +#define RCC_CCR_HSEONC RCC_CCR_HSEONC_Msk /*!< HSE oscillator enable */ +#define RCC_CCR_PLL1ONC_Pos (8UL) +#define RCC_CCR_PLL1ONC_Msk (0x1UL << RCC_CCR_PLL1ONC_Pos) /*!< 0x00000100 */ +#define RCC_CCR_PLL1ONC RCC_CCR_PLL1ONC_Msk /*!< PLL1 oscillator enable */ +#define RCC_CCR_PLL2ONC_Pos (9UL) +#define RCC_CCR_PLL2ONC_Msk (0x1UL << RCC_CCR_PLL2ONC_Pos) /*!< 0x00000200 */ +#define RCC_CCR_PLL2ONC RCC_CCR_PLL2ONC_Msk /*!< PLL2 oscillator enable */ +#define RCC_CCR_PLL3ONC_Pos (10UL) +#define RCC_CCR_PLL3ONC_Msk (0x1UL << RCC_CCR_PLL3ONC_Pos) /*!< 0x00000400 */ +#define RCC_CCR_PLL3ONC RCC_CCR_PLL3ONC_Msk /*!< PLL3 oscillator enable */ +#define RCC_CCR_PLL4ONC_Pos (11UL) +#define RCC_CCR_PLL4ONC_Msk (0x1UL << RCC_CCR_PLL4ONC_Pos) /*!< 0x00000800 */ +#define RCC_CCR_PLL4ONC RCC_CCR_PLL4ONC_Msk /*!< PLL4 oscillator enable */ + +/***************** Bit definition for RCC_STOPCCR register ******************/ +#define RCC_STOPCCR_MSISTOPENC_Pos (0UL) +#define RCC_STOPCCR_MSISTOPENC_Msk (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */ +#define RCC_STOPCCR_MSISTOPENC RCC_STOPCCR_MSISTOPENC_Msk /*!< MSI oscillator enable */ +#define RCC_STOPCCR_HSISTOPENC_Pos (1UL) +#define RCC_STOPCCR_HSISTOPENC_Msk (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */ +#define RCC_STOPCCR_HSISTOPENC RCC_STOPCCR_HSISTOPENC_Msk /*!< HSI oscillator enable */ + +/**************** Bit definition for RCC_MISCRSTCR register *****************/ +#define RCC_MISCRSTCR_DBGRSTC_Pos (0UL) +#define RCC_MISCRSTCR_DBGRSTC_Msk (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_MISCRSTCR_DBGRSTC RCC_MISCRSTCR_DBGRSTC_Msk /*!< DBG reset */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos (4UL) +#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MISCRSTCR_XSPIPHY1RSTC RCC_MISCRSTCR_XSPIPHY1RSTC_Msk /*!< XSPIPHY1 reset */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos (5UL) +#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MISCRSTCR_XSPIPHY2RSTC RCC_MISCRSTCR_XSPIPHY2RSTC_Msk /*!< XSPIPHY2 reset */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos (7UL) +#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos) /*!< 0x00000080 */ +#define RCC_MISCRSTCR_SDMMC1DLLRSTC RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk /*!< SDMMC1DLL reset */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos (8UL) +#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos) /*!< 0x00000100 */ +#define RCC_MISCRSTCR_SDMMC2DLLRSTC RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk /*!< SDMMC2DLL reset */ + +/***************** Bit definition for RCC_MEMRSTCR register *****************/ +#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos (0UL) +#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos) /*!< 0x00000001 */ +#define RCC_MEMRSTCR_AXISRAM3RSTC RCC_MEMRSTCR_AXISRAM3RSTC_Msk /*!< AXISRAM3 reset */ +#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos (1UL) +#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos) /*!< 0x00000002 */ +#define RCC_MEMRSTCR_AXISRAM4RSTC RCC_MEMRSTCR_AXISRAM4RSTC_Msk /*!< AXISRAM4 reset */ +#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos (2UL) +#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos) /*!< 0x00000004 */ +#define RCC_MEMRSTCR_AXISRAM5RSTC RCC_MEMRSTCR_AXISRAM5RSTC_Msk /*!< AXISRAM5 reset */ +#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos (3UL) +#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos) /*!< 0x00000008 */ +#define RCC_MEMRSTCR_AXISRAM6RSTC RCC_MEMRSTCR_AXISRAM6RSTC_Msk /*!< AXISRAM6 reset */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos (4UL) +#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_MEMRSTCR_AHBSRAM1RSTC RCC_MEMRSTCR_AHBSRAM1RSTC_Msk /*!< AHBSRAM1 reset */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos (5UL) +#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos) /*!< 0x00000020 */ +#define RCC_MEMRSTCR_AHBSRAM2RSTC RCC_MEMRSTCR_AHBSRAM2RSTC_Msk /*!< AHBSRAM2 reset */ +#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos (7UL) +#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos) /*!< 0x00000080 */ +#define RCC_MEMRSTCR_AXISRAM1RSTC RCC_MEMRSTCR_AXISRAM1RSTC_Msk /*!< AXISRAM1 reset */ +#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos (8UL) +#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos) /*!< 0x00000100 */ +#define RCC_MEMRSTCR_AXISRAM2RSTC RCC_MEMRSTCR_AXISRAM2RSTC_Msk /*!< AXISRAM2 reset */ +#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos (9UL) +#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */ +#define RCC_MEMRSTCR_FLEXRAMRSTC RCC_MEMRSTCR_FLEXRAMRSTC_Msk /*!< FLEXRAM reset */ +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos (10UL) +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos) /*!< 0x00000400 */ +#define RCC_MEMRSTCR_CACHEAXIRAMRSTC RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk /*!< CACHEAXIRAM reset */ +#define RCC_MEMRSTCR_VENCRAMRSTC_Pos (11UL) +#define RCC_MEMRSTCR_VENCRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */ +#define RCC_MEMRSTCR_VENCRAMRSTC RCC_MEMRSTCR_VENCRAMRSTC_Msk /*!< VENCRAM reset */ +#define RCC_MEMRSTCR_BOOTROMRSTC_Pos (12UL) +#define RCC_MEMRSTCR_BOOTROMRSTC_Msk (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */ +#define RCC_MEMRSTCR_BOOTROMRSTC RCC_MEMRSTCR_BOOTROMRSTC_Msk /*!< Boot ROM reset */ + +/**************** Bit definition for RCC_AHB1RSTCR register *****************/ +#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos (4UL) +#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTCR_GPDMA1RSTC RCC_AHB1RSTCR_GPDMA1RSTC_Msk /*!< GPDMA1 reset */ +#define RCC_AHB1RSTCR_ADC12RSTC_Pos (5UL) +#define RCC_AHB1RSTCR_ADC12RSTC_Msk (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB1RSTCR_ADC12RSTC RCC_AHB1RSTCR_ADC12RSTC_Msk /*!< ADC12 reset */ + +/**************** Bit definition for RCC_AHB2RSTCR register *****************/ +#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos (12UL) +#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2RSTCR_RAMCFGRSTC RCC_AHB2RSTCR_RAMCFGRSTC_Msk /*!< RAMCFG reset */ +#define RCC_AHB2RSTCR_MDF1RSTC_Pos (16UL) +#define RCC_AHB2RSTCR_MDF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCR_MDF1RSTC RCC_AHB2RSTCR_MDF1RSTC_Msk /*!< MDF1 reset */ +#define RCC_AHB2RSTCR_ADF1RSTC_Pos (17UL) +#define RCC_AHB2RSTCR_ADF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTCR_ADF1RSTC RCC_AHB2RSTCR_ADF1RSTC_Msk /*!< ADF1 reset */ + +/**************** Bit definition for RCC_AHB3RSTCR register *****************/ +#define RCC_AHB3RSTCR_RNGRSTC_Pos (0UL) +#define RCC_AHB3RSTCR_RNGRSTC_Msk (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCR_RNGRSTC RCC_AHB3RSTCR_RNGRSTC_Msk /*!< RNG reset */ +#define RCC_AHB3RSTCR_HASHRSTC_Pos (1UL) +#define RCC_AHB3RSTCR_HASHRSTC_Msk (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTCR_HASHRSTC RCC_AHB3RSTCR_HASHRSTC_Msk /*!< HASH reset */ +#define RCC_AHB3RSTCR_CRYPRSTC_Pos (2UL) +#define RCC_AHB3RSTCR_CRYPRSTC_Msk (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTCR_CRYPRSTC RCC_AHB3RSTCR_CRYPRSTC_Msk /*!< CRYP reset */ +#define RCC_AHB3RSTCR_SAESRSTC_Pos (4UL) +#define RCC_AHB3RSTCR_SAESRSTC_Msk (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCR_SAESRSTC RCC_AHB3RSTCR_SAESRSTC_Msk /*!< SAES reset */ +#define RCC_AHB3RSTCR_PKARSTC_Pos (8UL) +#define RCC_AHB3RSTCR_PKARSTC_Msk (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3RSTCR_PKARSTC RCC_AHB3RSTCR_PKARSTC_Msk /*!< PKA reset */ +#define RCC_AHB3RSTCR_IACRSTC_Pos (10UL) +#define RCC_AHB3RSTCR_IACRSTC_Msk (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3RSTCR_IACRSTC RCC_AHB3RSTCR_IACRSTC_Msk /*!< IAC reset */ + +/**************** Bit definition for RCC_AHB4RSTCR register *****************/ +#define RCC_AHB4RSTCR_GPIOARSTC_Pos (0UL) +#define RCC_AHB4RSTCR_GPIOARSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */ +#define RCC_AHB4RSTCR_GPIOARSTC RCC_AHB4RSTCR_GPIOARSTC_Msk /*!< GPIO A reset */ +#define RCC_AHB4RSTCR_GPIOBRSTC_Pos (1UL) +#define RCC_AHB4RSTCR_GPIOBRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB4RSTCR_GPIOBRSTC RCC_AHB4RSTCR_GPIOBRSTC_Msk /*!< GPIO B reset */ +#define RCC_AHB4RSTCR_GPIOCRSTC_Pos (2UL) +#define RCC_AHB4RSTCR_GPIOCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */ +#define RCC_AHB4RSTCR_GPIOCRSTC RCC_AHB4RSTCR_GPIOCRSTC_Msk /*!< GPIO C reset */ +#define RCC_AHB4RSTCR_GPIODRSTC_Pos (3UL) +#define RCC_AHB4RSTCR_GPIODRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */ +#define RCC_AHB4RSTCR_GPIODRSTC RCC_AHB4RSTCR_GPIODRSTC_Msk /*!< GPIO D reset */ +#define RCC_AHB4RSTCR_GPIOERSTC_Pos (4UL) +#define RCC_AHB4RSTCR_GPIOERSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */ +#define RCC_AHB4RSTCR_GPIOERSTC RCC_AHB4RSTCR_GPIOERSTC_Msk /*!< GPIO E reset */ +#define RCC_AHB4RSTCR_GPIOFRSTC_Pos (5UL) +#define RCC_AHB4RSTCR_GPIOFRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB4RSTCR_GPIOFRSTC RCC_AHB4RSTCR_GPIOFRSTC_Msk /*!< GPIO F reset */ +#define RCC_AHB4RSTCR_GPIOGRSTC_Pos (6UL) +#define RCC_AHB4RSTCR_GPIOGRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */ +#define RCC_AHB4RSTCR_GPIOGRSTC RCC_AHB4RSTCR_GPIOGRSTC_Msk /*!< GPIO G reset */ +#define RCC_AHB4RSTCR_GPIOHRSTC_Pos (7UL) +#define RCC_AHB4RSTCR_GPIOHRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */ +#define RCC_AHB4RSTCR_GPIOHRSTC RCC_AHB4RSTCR_GPIOHRSTC_Msk /*!< GPIO H reset */ +#define RCC_AHB4RSTCR_GPIONRSTC_Pos (13UL) +#define RCC_AHB4RSTCR_GPIONRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB4RSTCR_GPIONRSTC RCC_AHB4RSTCR_GPIONRSTC_Msk /*!< GPIO N reset */ +#define RCC_AHB4RSTCR_GPIOORSTC_Pos (14UL) +#define RCC_AHB4RSTCR_GPIOORSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */ +#define RCC_AHB4RSTCR_GPIOORSTC RCC_AHB4RSTCR_GPIOORSTC_Msk /*!< GPIO O reset */ +#define RCC_AHB4RSTCR_GPIOPRSTC_Pos (15UL) +#define RCC_AHB4RSTCR_GPIOPRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */ +#define RCC_AHB4RSTCR_GPIOPRSTC RCC_AHB4RSTCR_GPIOPRSTC_Msk /*!< GPIO P reset */ +#define RCC_AHB4RSTCR_GPIOQRSTC_Pos (16UL) +#define RCC_AHB4RSTCR_GPIOQRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */ +#define RCC_AHB4RSTCR_GPIOQRSTC RCC_AHB4RSTCR_GPIOQRSTC_Msk /*!< GPIO Q reset */ +#define RCC_AHB4RSTCR_PWRRSTC_Pos (18UL) +#define RCC_AHB4RSTCR_PWRRSTC_Msk (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4RSTCR_PWRRSTC RCC_AHB4RSTCR_PWRRSTC_Msk /*!< PWR reset */ +#define RCC_AHB4RSTCR_CRCRSTC_Pos (19UL) +#define RCC_AHB4RSTCR_CRCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTCR_CRCRSTC RCC_AHB4RSTCR_CRCRSTC_Msk /*!< CRC reset */ + +/**************** Bit definition for RCC_AHB5RSTCR register *****************/ +#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos (0UL) +#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCR_HPDMA1RSTC RCC_AHB5RSTCR_HPDMA1RSTC_Msk /*!< HPDMA1 reset */ +#define RCC_AHB5RSTCR_DMA2DRSTC_Pos (1UL) +#define RCC_AHB5RSTCR_DMA2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */ +#define RCC_AHB5RSTCR_DMA2DRSTC RCC_AHB5RSTCR_DMA2DRSTC_Msk /*!< DMA2D reset */ +#define RCC_AHB5RSTCR_JPEGRSTC_Pos (3UL) +#define RCC_AHB5RSTCR_JPEGRSTC_Msk (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTCR_JPEGRSTC RCC_AHB5RSTCR_JPEGRSTC_Msk /*!< JPEG reset */ +#define RCC_AHB5RSTCR_FMCRSTC_Pos (4UL) +#define RCC_AHB5RSTCR_FMCRSTC_Msk (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCR_FMCRSTC RCC_AHB5RSTCR_FMCRSTC_Msk /*!< FMC reset */ +#define RCC_AHB5RSTCR_XSPI1RSTC_Pos (5UL) +#define RCC_AHB5RSTCR_XSPI1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */ +#define RCC_AHB5RSTCR_XSPI1RSTC RCC_AHB5RSTCR_XSPI1RSTC_Msk /*!< XSPI1 reset */ +#define RCC_AHB5RSTCR_PSSIRSTC_Pos (6UL) +#define RCC_AHB5RSTCR_PSSIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCR_PSSIRSTC RCC_AHB5RSTCR_PSSIRSTC_Msk /*!< PSSI reset */ +#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos (7UL) +#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5RSTCR_SDMMC2RSTC RCC_AHB5RSTCR_SDMMC2RSTC_Msk /*!< SDMMC2 reset */ +#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos (8UL) +#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTCR_SDMMC1RSTC RCC_AHB5RSTCR_SDMMC1RSTC_Msk /*!< SDMMC1 reset */ +#define RCC_AHB5RSTCR_XSPI2RSTC_Pos (12UL) +#define RCC_AHB5RSTCR_XSPI2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */ +#define RCC_AHB5RSTCR_XSPI2RSTC RCC_AHB5RSTCR_XSPI2RSTC_Msk /*!< XSPI2 reset */ +#define RCC_AHB5RSTCR_XSPIMRSTC_Pos (13UL) +#define RCC_AHB5RSTCR_XSPIMRSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */ +#define RCC_AHB5RSTCR_XSPIMRSTC RCC_AHB5RSTCR_XSPIMRSTC_Msk /*!< XSPIM reset */ +#define RCC_AHB5RSTCR_XSPI3RSTC_Pos (17UL) +#define RCC_AHB5RSTCR_XSPI3RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */ +#define RCC_AHB5RSTCR_XSPI3RSTC RCC_AHB5RSTCR_XSPI3RSTC_Msk /*!< XSPI3 reset */ +#define RCC_AHB5RSTCR_GFXMMURSTC_Pos (19UL) +#define RCC_AHB5RSTCR_GFXMMURSTC_Msk (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTCR_GFXMMURSTC RCC_AHB5RSTCR_GFXMMURSTC_Msk /*!< GFXMMU reset */ +#define RCC_AHB5RSTCR_GPU2DRSTC_Pos (20UL) +#define RCC_AHB5RSTCR_GPU2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */ +#define RCC_AHB5RSTCR_GPU2DRSTC RCC_AHB5RSTCR_GPU2DRSTC_Msk /*!< GPU2D reset */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos (23UL) +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk /*!< OTG1PHYCTL reset */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos (24UL) +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk /*!< OTG2PHYCTL reset */ +#define RCC_AHB5RSTCR_ETH1RSTC_Pos (25UL) +#define RCC_AHB5RSTCR_ETH1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5RSTCR_ETH1RSTC RCC_AHB5RSTCR_ETH1RSTC_Msk /*!< ETH1 reset */ +#define RCC_AHB5RSTCR_OTG1RSTC_Pos (26UL) +#define RCC_AHB5RSTCR_OTG1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5RSTCR_OTG1RSTC RCC_AHB5RSTCR_OTG1RSTC_Msk /*!< OTG1 reset */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos (27UL) +#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5RSTCR_OTGPHY1RSTC RCC_AHB5RSTCR_OTGPHY1RSTC_Msk /*!< OTGPHY1 reset */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos (28UL) +#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5RSTCR_OTGPHY2RSTC RCC_AHB5RSTCR_OTGPHY2RSTC_Msk /*!< OTGPHY2 reset */ +#define RCC_AHB5RSTCR_OTG2RSTC_Pos (29UL) +#define RCC_AHB5RSTCR_OTG2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5RSTCR_OTG2RSTC RCC_AHB5RSTCR_OTG2RSTC_Msk /*!< OTG2 reset */ +#define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos (30UL) +#define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5RSTCR_CACHEAXIRSTC RCC_AHB5RSTCR_CACHEAXIRSTC_Msk /*!< CACHEAXI reset */ +#define RCC_AHB5RSTCR_NPURSTC_Pos (31UL) +#define RCC_AHB5RSTCR_NPURSTC_Msk (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos) /*!< 0x80000000 */ +#define RCC_AHB5RSTCR_NPURSTC RCC_AHB5RSTCR_NPURSTC_Msk /*!< NPU reset */ + +/**************** Bit definition for RCC_APB1RSTCR1 register ****************/ +#define RCC_APB1RSTCR1_TIM2RSTC_Pos (0UL) +#define RCC_APB1RSTCR1_TIM2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */ +#define RCC_APB1RSTCR1_TIM2RSTC RCC_APB1RSTCR1_TIM2RSTC_Msk /*!< TIM2 reset */ +#define RCC_APB1RSTCR1_TIM3RSTC_Pos (1UL) +#define RCC_APB1RSTCR1_TIM3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */ +#define RCC_APB1RSTCR1_TIM3RSTC RCC_APB1RSTCR1_TIM3RSTC_Msk /*!< TIM3 reset */ +#define RCC_APB1RSTCR1_TIM4RSTC_Pos (2UL) +#define RCC_APB1RSTCR1_TIM4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */ +#define RCC_APB1RSTCR1_TIM4RSTC RCC_APB1RSTCR1_TIM4RSTC_Msk /*!< TIM4 reset */ +#define RCC_APB1RSTCR1_TIM5RSTC_Pos (3UL) +#define RCC_APB1RSTCR1_TIM5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */ +#define RCC_APB1RSTCR1_TIM5RSTC RCC_APB1RSTCR1_TIM5RSTC_Msk /*!< TIM5 reset */ +#define RCC_APB1RSTCR1_TIM6RSTC_Pos (4UL) +#define RCC_APB1RSTCR1_TIM6RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */ +#define RCC_APB1RSTCR1_TIM6RSTC RCC_APB1RSTCR1_TIM6RSTC_Msk /*!< TIM6 reset */ +#define RCC_APB1RSTCR1_TIM7RSTC_Pos (5UL) +#define RCC_APB1RSTCR1_TIM7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB1RSTCR1_TIM7RSTC RCC_APB1RSTCR1_TIM7RSTC_Msk /*!< TIM7 reset */ +#define RCC_APB1RSTCR1_TIM12RSTC_Pos (6UL) +#define RCC_APB1RSTCR1_TIM12RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCR1_TIM12RSTC RCC_APB1RSTCR1_TIM12RSTC_Msk /*!< TIM12 reset */ +#define RCC_APB1RSTCR1_TIM13RSTC_Pos (7UL) +#define RCC_APB1RSTCR1_TIM13RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCR1_TIM13RSTC RCC_APB1RSTCR1_TIM13RSTC_Msk /*!< TIM13 reset */ +#define RCC_APB1RSTCR1_TIM14RSTC_Pos (8UL) +#define RCC_APB1RSTCR1_TIM14RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR1_TIM14RSTC RCC_APB1RSTCR1_TIM14RSTC_Msk /*!< TIM14 reset */ +#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos (9UL) +#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCR1_LPTIM1RSTC RCC_APB1RSTCR1_LPTIM1RSTC_Msk /*!< LPTIM1 reset */ +#define RCC_APB1RSTCR1_WWDGRSTC_Pos (11UL) +#define RCC_APB1RSTCR1_WWDGRSTC_Msk (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */ +#define RCC_APB1RSTCR1_WWDGRSTC RCC_APB1RSTCR1_WWDGRSTC_Msk /*!< WWDG reset */ +#define RCC_APB1RSTCR1_TIM10RSTC_Pos (12UL) +#define RCC_APB1RSTCR1_TIM10RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCR1_TIM10RSTC RCC_APB1RSTCR1_TIM10RSTC_Msk /*!< TIM10 reset */ +#define RCC_APB1RSTCR1_TIM11RSTC_Pos (13UL) +#define RCC_APB1RSTCR1_TIM11RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB1RSTCR1_TIM11RSTC RCC_APB1RSTCR1_TIM11RSTC_Msk /*!< TIM11 reset */ +#define RCC_APB1RSTCR1_SPI2RSTC_Pos (14UL) +#define RCC_APB1RSTCR1_SPI2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */ +#define RCC_APB1RSTCR1_SPI2RSTC RCC_APB1RSTCR1_SPI2RSTC_Msk /*!< SPI2 reset */ +#define RCC_APB1RSTCR1_SPI3RSTC_Pos (15UL) +#define RCC_APB1RSTCR1_SPI3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB1RSTCR1_SPI3RSTC RCC_APB1RSTCR1_SPI3RSTC_Msk /*!< SPI3 reset */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos (16UL) +#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCR1_SPDIFRX1RSTC RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk /*!< SPDIFRX1 reset */ +#define RCC_APB1RSTCR1_USART2RSTC_Pos (17UL) +#define RCC_APB1RSTCR1_USART2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCR1_USART2RSTC RCC_APB1RSTCR1_USART2RSTC_Msk /*!< USART2 reset */ +#define RCC_APB1RSTCR1_USART3RSTC_Pos (18UL) +#define RCC_APB1RSTCR1_USART3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR1_USART3RSTC RCC_APB1RSTCR1_USART3RSTC_Msk /*!< USART3 reset */ +#define RCC_APB1RSTCR1_UART4RSTC_Pos (19UL) +#define RCC_APB1RSTCR1_UART4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCR1_UART4RSTC RCC_APB1RSTCR1_UART4RSTC_Msk /*!< UART4 reset */ +#define RCC_APB1RSTCR1_UART5RSTC_Pos (20UL) +#define RCC_APB1RSTCR1_UART5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTCR1_UART5RSTC RCC_APB1RSTCR1_UART5RSTC_Msk /*!< UART5 reset */ +#define RCC_APB1RSTCR1_I2C1RSTC_Pos (21UL) +#define RCC_APB1RSTCR1_I2C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */ +#define RCC_APB1RSTCR1_I2C1RSTC RCC_APB1RSTCR1_I2C1RSTC_Msk /*!< I2C1 reset */ +#define RCC_APB1RSTCR1_I2C2RSTC_Pos (22UL) +#define RCC_APB1RSTCR1_I2C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */ +#define RCC_APB1RSTCR1_I2C2RSTC RCC_APB1RSTCR1_I2C2RSTC_Msk /*!< I2C2 reset */ +#define RCC_APB1RSTCR1_I2C3RSTC_Pos (23UL) +#define RCC_APB1RSTCR1_I2C3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */ +#define RCC_APB1RSTCR1_I2C3RSTC RCC_APB1RSTCR1_I2C3RSTC_Msk /*!< I2C3 reset */ +#define RCC_APB1RSTCR1_I3C1RSTC_Pos (24UL) +#define RCC_APB1RSTCR1_I3C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */ +#define RCC_APB1RSTCR1_I3C1RSTC RCC_APB1RSTCR1_I3C1RSTC_Msk /*!< I3C1 reset */ +#define RCC_APB1RSTCR1_I3C2RSTC_Pos (25UL) +#define RCC_APB1RSTCR1_I3C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */ +#define RCC_APB1RSTCR1_I3C2RSTC RCC_APB1RSTCR1_I3C2RSTC_Msk /*!< I3C2 reset */ +#define RCC_APB1RSTCR1_UART7RSTC_Pos (30UL) +#define RCC_APB1RSTCR1_UART7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTCR1_UART7RSTC RCC_APB1RSTCR1_UART7RSTC_Msk /*!< UART7 reset */ +#define RCC_APB1RSTCR1_UART8RSTC_Pos (31UL) +#define RCC_APB1RSTCR1_UART8RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCR1_UART8RSTC RCC_APB1RSTCR1_UART8RSTC_Msk /*!< UART8 reset */ + +/**************** Bit definition for RCC_APB1RSTCR2 register ****************/ +#define RCC_APB1RSTCR2_MDIOSRSTC_Pos (5UL) +#define RCC_APB1RSTCR2_MDIOSRSTC_Msk (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCR2_MDIOSRSTC RCC_APB1RSTCR2_MDIOSRSTC_Msk /*!< MDIOS reset */ +#define RCC_APB1RSTCR2_FDCANRSTC_Pos (8UL) +#define RCC_APB1RSTCR2_FDCANRSTC_Msk (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCR2_FDCANRSTC RCC_APB1RSTCR2_FDCANRSTC_Msk /*!< FDCAN reset */ +#define RCC_APB1RSTCR2_UCPD1RSTC_Pos (18UL) +#define RCC_APB1RSTCR2_UCPD1RSTC_Msk (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCR2_UCPD1RSTC RCC_APB1RSTCR2_UCPD1RSTC_Msk /*!< UCPD1 reset */ + +/**************** Bit definition for RCC_APB2RSTCR register *****************/ +#define RCC_APB2RSTCR_TIM1RSTC_Pos (0UL) +#define RCC_APB2RSTCR_TIM1RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCR_TIM1RSTC RCC_APB2RSTCR_TIM1RSTC_Msk /*!< TIM1 reset */ +#define RCC_APB2RSTCR_TIM8RSTC_Pos (1UL) +#define RCC_APB2RSTCR_TIM8RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCR_TIM8RSTC RCC_APB2RSTCR_TIM8RSTC_Msk /*!< TIM8 reset */ +#define RCC_APB2RSTCR_USART1RSTC_Pos (4UL) +#define RCC_APB2RSTCR_USART1RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCR_USART1RSTC RCC_APB2RSTCR_USART1RSTC_Msk /*!< USART1 reset */ +#define RCC_APB2RSTCR_USART6RSTC_Pos (5UL) +#define RCC_APB2RSTCR_USART6RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTCR_USART6RSTC RCC_APB2RSTCR_USART6RSTC_Msk /*!< USART6 reset */ +#define RCC_APB2RSTCR_UART9RSTC_Pos (6UL) +#define RCC_APB2RSTCR_UART9RSTC_Msk (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */ +#define RCC_APB2RSTCR_UART9RSTC RCC_APB2RSTCR_UART9RSTC_Msk /*!< UART9 reset */ +#define RCC_APB2RSTCR_USART10RSTC_Pos (7UL) +#define RCC_APB2RSTCR_USART10RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTCR_USART10RSTC RCC_APB2RSTCR_USART10RSTC_Msk /*!< USART10 reset */ +#define RCC_APB2RSTCR_SPI1RSTC_Pos (12UL) +#define RCC_APB2RSTCR_SPI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTCR_SPI1RSTC RCC_APB2RSTCR_SPI1RSTC_Msk /*!< SPI1 reset */ +#define RCC_APB2RSTCR_SPI4RSTC_Pos (13UL) +#define RCC_APB2RSTCR_SPI4RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCR_SPI4RSTC RCC_APB2RSTCR_SPI4RSTC_Msk /*!< SPI4 reset */ +#define RCC_APB2RSTCR_TIM18RSTC_Pos (15UL) +#define RCC_APB2RSTCR_TIM18RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */ +#define RCC_APB2RSTCR_TIM18RSTC RCC_APB2RSTCR_TIM18RSTC_Msk /*!< TIM18 reset */ +#define RCC_APB2RSTCR_TIM15RSTC_Pos (16UL) +#define RCC_APB2RSTCR_TIM15RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */ +#define RCC_APB2RSTCR_TIM15RSTC RCC_APB2RSTCR_TIM15RSTC_Msk /*!< TIM15 reset */ +#define RCC_APB2RSTCR_TIM16RSTC_Pos (17UL) +#define RCC_APB2RSTCR_TIM16RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */ +#define RCC_APB2RSTCR_TIM16RSTC RCC_APB2RSTCR_TIM16RSTC_Msk /*!< TIM16 reset */ +#define RCC_APB2RSTCR_TIM17RSTC_Pos (18UL) +#define RCC_APB2RSTCR_TIM17RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */ +#define RCC_APB2RSTCR_TIM17RSTC RCC_APB2RSTCR_TIM17RSTC_Msk /*!< TIM17 reset */ +#define RCC_APB2RSTCR_TIM9RSTC_Pos (19UL) +#define RCC_APB2RSTCR_TIM9RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTCR_TIM9RSTC RCC_APB2RSTCR_TIM9RSTC_Msk /*!< TIM9 reset */ +#define RCC_APB2RSTCR_SPI5RSTC_Pos (20UL) +#define RCC_APB2RSTCR_SPI5RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCR_SPI5RSTC RCC_APB2RSTCR_SPI5RSTC_Msk /*!< SPI5 reset */ +#define RCC_APB2RSTCR_SAI1RSTC_Pos (21UL) +#define RCC_APB2RSTCR_SAI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTCR_SAI1RSTC RCC_APB2RSTCR_SAI1RSTC_Msk /*!< SAI1 reset */ +#define RCC_APB2RSTCR_SAI2RSTC_Pos (22UL) +#define RCC_APB2RSTCR_SAI2RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTCR_SAI2RSTC RCC_APB2RSTCR_SAI2RSTC_Msk /*!< SAI2 reset */ + +/**************** Bit definition for RCC_APB4RSTCR1 register ****************/ +#define RCC_APB4RSTCR1_HDPRSTC_Pos (2UL) +#define RCC_APB4RSTCR1_HDPRSTC_Msk (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR1_HDPRSTC RCC_APB4RSTCR1_HDPRSTC_Msk /*!< HDP reset */ +#define RCC_APB4RSTCR1_LPUART1RSTC_Pos (3UL) +#define RCC_APB4RSTCR1_LPUART1RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTCR1_LPUART1RSTC RCC_APB4RSTCR1_LPUART1RSTC_Msk /*!< LPUART1 reset */ +#define RCC_APB4RSTCR1_SPI6RSTC_Pos (5UL) +#define RCC_APB4RSTCR1_SPI6RSTC_Msk (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */ +#define RCC_APB4RSTCR1_SPI6RSTC RCC_APB4RSTCR1_SPI6RSTC_Msk /*!< SPI6 reset */ +#define RCC_APB4RSTCR1_I2C4RSTC_Pos (7UL) +#define RCC_APB4RSTCR1_I2C4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */ +#define RCC_APB4RSTCR1_I2C4RSTC RCC_APB4RSTCR1_I2C4RSTC_Msk /*!< I2C4 reset */ +#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos (9UL) +#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTCR1_LPTIM2RSTC RCC_APB4RSTCR1_LPTIM2RSTC_Msk /*!< LPTIM2 reset */ +#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos (10UL) +#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTCR1_LPTIM3RSTC RCC_APB4RSTCR1_LPTIM3RSTC_Msk /*!< LPTIM3 reset */ +#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos (11UL) +#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTCR1_LPTIM4RSTC RCC_APB4RSTCR1_LPTIM4RSTC_Msk /*!< LPTIM4 reset */ +#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos (12UL) +#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTCR1_LPTIM5RSTC RCC_APB4RSTCR1_LPTIM5RSTC_Msk /*!< LPTIM5 reset */ +#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos (15UL) +#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTCR1_VREFBUFRSTC RCC_APB4RSTCR1_VREFBUFRSTC_Msk /*!< VREFBUF reset */ +#define RCC_APB4RSTCR1_RTCRSTC_Pos (16UL) +#define RCC_APB4RSTCR1_RTCRSTC_Msk (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCR1_RTCRSTC RCC_APB4RSTCR1_RTCRSTC_Msk /*!< RTC reset */ + +/**************** Bit definition for RCC_APB4RSTCR2 register ****************/ +#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos (0UL) +#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCR2_SYSCFGRSTC RCC_APB4RSTCR2_SYSCFGRSTC_Msk /*!< SYSCFG reset */ +#define RCC_APB4RSTCR2_DTSRSTC_Pos (2UL) +#define RCC_APB4RSTCR2_DTSRSTC_Msk (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB4RSTCR2_DTSRSTC RCC_APB4RSTCR2_DTSRSTC_Msk /*!< DTS reset */ + +/**************** Bit definition for RCC_APB5RSTCR register *****************/ +#define RCC_APB5RSTCR_LTDCRSTC_Pos (1UL) +#define RCC_APB5RSTCR_LTDCRSTC_Msk (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTCR_LTDCRSTC RCC_APB5RSTCR_LTDCRSTC_Msk /*!< LTDC reset */ +#define RCC_APB5RSTCR_DCMIPPRSTC_Pos (2UL) +#define RCC_APB5RSTCR_DCMIPPRSTC_Msk (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCR_DCMIPPRSTC RCC_APB5RSTCR_DCMIPPRSTC_Msk /*!< DCMIPP reset */ +#define RCC_APB5RSTCR_GFXTIMRSTC_Pos (4UL) +#define RCC_APB5RSTCR_GFXTIMRSTC_Msk (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCR_GFXTIMRSTC RCC_APB5RSTCR_GFXTIMRSTC_Msk /*!< GFXTIM reset */ +#define RCC_APB5RSTCR_VENCRSTC_Pos (5UL) +#define RCC_APB5RSTCR_VENCRSTC_Msk (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */ +#define RCC_APB5RSTCR_VENCRSTC RCC_APB5RSTCR_VENCRSTC_Msk /*!< VENC reset */ +#define RCC_APB5RSTCR_CSIRSTC_Pos (6UL) +#define RCC_APB5RSTCR_CSIRSTC_Msk (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos) /*!< 0x00000040 */ +#define RCC_APB5RSTCR_CSIRSTC RCC_APB5RSTCR_CSIRSTC_Msk /*!< CSI reset */ + +/***************** Bit definition for RCC_DIVENCR register ******************/ +#define RCC_DIVENCR_IC1ENC_Pos (0UL) +#define RCC_DIVENCR_IC1ENC_Msk (0x1UL << RCC_DIVENCR_IC1ENC_Pos) /*!< 0x00000001 */ +#define RCC_DIVENCR_IC1ENC RCC_DIVENCR_IC1ENC_Msk /*!< IC1 enable */ +#define RCC_DIVENCR_IC2ENC_Pos (1UL) +#define RCC_DIVENCR_IC2ENC_Msk (0x1UL << RCC_DIVENCR_IC2ENC_Pos) /*!< 0x00000002 */ +#define RCC_DIVENCR_IC2ENC RCC_DIVENCR_IC2ENC_Msk /*!< IC2 enable */ +#define RCC_DIVENCR_IC3ENC_Pos (2UL) +#define RCC_DIVENCR_IC3ENC_Msk (0x1UL << RCC_DIVENCR_IC3ENC_Pos) /*!< 0x00000004 */ +#define RCC_DIVENCR_IC3ENC RCC_DIVENCR_IC3ENC_Msk /*!< IC3 enable */ +#define RCC_DIVENCR_IC4ENC_Pos (3UL) +#define RCC_DIVENCR_IC4ENC_Msk (0x1UL << RCC_DIVENCR_IC4ENC_Pos) /*!< 0x00000008 */ +#define RCC_DIVENCR_IC4ENC RCC_DIVENCR_IC4ENC_Msk /*!< IC4 enable */ +#define RCC_DIVENCR_IC5ENC_Pos (4UL) +#define RCC_DIVENCR_IC5ENC_Msk (0x1UL << RCC_DIVENCR_IC5ENC_Pos) /*!< 0x00000010 */ +#define RCC_DIVENCR_IC5ENC RCC_DIVENCR_IC5ENC_Msk /*!< IC5 enable */ +#define RCC_DIVENCR_IC6ENC_Pos (5UL) +#define RCC_DIVENCR_IC6ENC_Msk (0x1UL << RCC_DIVENCR_IC6ENC_Pos) /*!< 0x00000020 */ +#define RCC_DIVENCR_IC6ENC RCC_DIVENCR_IC6ENC_Msk /*!< IC6 enable */ +#define RCC_DIVENCR_IC7ENC_Pos (6UL) +#define RCC_DIVENCR_IC7ENC_Msk (0x1UL << RCC_DIVENCR_IC7ENC_Pos) /*!< 0x00000040 */ +#define RCC_DIVENCR_IC7ENC RCC_DIVENCR_IC7ENC_Msk /*!< IC7 enable */ +#define RCC_DIVENCR_IC8ENC_Pos (7UL) +#define RCC_DIVENCR_IC8ENC_Msk (0x1UL << RCC_DIVENCR_IC8ENC_Pos) /*!< 0x00000080 */ +#define RCC_DIVENCR_IC8ENC RCC_DIVENCR_IC8ENC_Msk /*!< IC8 enable */ +#define RCC_DIVENCR_IC9ENC_Pos (8UL) +#define RCC_DIVENCR_IC9ENC_Msk (0x1UL << RCC_DIVENCR_IC9ENC_Pos) /*!< 0x00000100 */ +#define RCC_DIVENCR_IC9ENC RCC_DIVENCR_IC9ENC_Msk /*!< IC9 enable */ +#define RCC_DIVENCR_IC10ENC_Pos (9UL) +#define RCC_DIVENCR_IC10ENC_Msk (0x1UL << RCC_DIVENCR_IC10ENC_Pos) /*!< 0x00000200 */ +#define RCC_DIVENCR_IC10ENC RCC_DIVENCR_IC10ENC_Msk /*!< IC10 enable */ +#define RCC_DIVENCR_IC11ENC_Pos (10UL) +#define RCC_DIVENCR_IC11ENC_Msk (0x1UL << RCC_DIVENCR_IC11ENC_Pos) /*!< 0x00000400 */ +#define RCC_DIVENCR_IC11ENC RCC_DIVENCR_IC11ENC_Msk /*!< IC11 enable */ +#define RCC_DIVENCR_IC12ENC_Pos (11UL) +#define RCC_DIVENCR_IC12ENC_Msk (0x1UL << RCC_DIVENCR_IC12ENC_Pos) /*!< 0x00000800 */ +#define RCC_DIVENCR_IC12ENC RCC_DIVENCR_IC12ENC_Msk /*!< IC12 enable */ +#define RCC_DIVENCR_IC13ENC_Pos (12UL) +#define RCC_DIVENCR_IC13ENC_Msk (0x1UL << RCC_DIVENCR_IC13ENC_Pos) /*!< 0x00001000 */ +#define RCC_DIVENCR_IC13ENC RCC_DIVENCR_IC13ENC_Msk /*!< IC13 enable */ +#define RCC_DIVENCR_IC14ENC_Pos (13UL) +#define RCC_DIVENCR_IC14ENC_Msk (0x1UL << RCC_DIVENCR_IC14ENC_Pos) /*!< 0x00002000 */ +#define RCC_DIVENCR_IC14ENC RCC_DIVENCR_IC14ENC_Msk /*!< IC14 enable */ +#define RCC_DIVENCR_IC15ENC_Pos (14UL) +#define RCC_DIVENCR_IC15ENC_Msk (0x1UL << RCC_DIVENCR_IC15ENC_Pos) /*!< 0x00004000 */ +#define RCC_DIVENCR_IC15ENC RCC_DIVENCR_IC15ENC_Msk /*!< IC15 enable */ +#define RCC_DIVENCR_IC16ENC_Pos (15UL) +#define RCC_DIVENCR_IC16ENC_Msk (0x1UL << RCC_DIVENCR_IC16ENC_Pos) /*!< 0x00008000 */ +#define RCC_DIVENCR_IC16ENC RCC_DIVENCR_IC16ENC_Msk /*!< IC16 enable */ +#define RCC_DIVENCR_IC17ENC_Pos (16UL) +#define RCC_DIVENCR_IC17ENC_Msk (0x1UL << RCC_DIVENCR_IC17ENC_Pos) /*!< 0x00010000 */ +#define RCC_DIVENCR_IC17ENC RCC_DIVENCR_IC17ENC_Msk /*!< IC17 enable */ +#define RCC_DIVENCR_IC18ENC_Pos (17UL) +#define RCC_DIVENCR_IC18ENC_Msk (0x1UL << RCC_DIVENCR_IC18ENC_Pos) /*!< 0x00020000 */ +#define RCC_DIVENCR_IC18ENC RCC_DIVENCR_IC18ENC_Msk /*!< IC18 enable */ +#define RCC_DIVENCR_IC19ENC_Pos (18UL) +#define RCC_DIVENCR_IC19ENC_Msk (0x1UL << RCC_DIVENCR_IC19ENC_Pos) /*!< 0x00040000 */ +#define RCC_DIVENCR_IC19ENC RCC_DIVENCR_IC19ENC_Msk /*!< IC19 enable */ +#define RCC_DIVENCR_IC20ENC_Pos (19UL) +#define RCC_DIVENCR_IC20ENC_Msk (0x1UL << RCC_DIVENCR_IC20ENC_Pos) /*!< 0x00080000 */ +#define RCC_DIVENCR_IC20ENC RCC_DIVENCR_IC20ENC_Msk /*!< IC20 enable */ + +/***************** Bit definition for RCC_BUSENCR register ******************/ +#define RCC_BUSENCR_ACLKNENC_Pos (0UL) +#define RCC_BUSENCR_ACLKNENC_Msk (0x1UL << RCC_BUSENCR_ACLKNENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSENCR_ACLKNENC RCC_BUSENCR_ACLKNENC_Msk /*!< ACLKN enable */ +#define RCC_BUSENCR_ACLKNCENC_Pos (1UL) +#define RCC_BUSENCR_ACLKNCENC_Msk (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSENCR_ACLKNCENC RCC_BUSENCR_ACLKNCENC_Msk /*!< ACLKNC enable */ +#define RCC_BUSENCR_AHBMENC_Pos (2UL) +#define RCC_BUSENCR_AHBMENC_Msk (0x1UL << RCC_BUSENCR_AHBMENC_Pos) /*!< 0x00000004 */ +#define RCC_BUSENCR_AHBMENC RCC_BUSENCR_AHBMENC_Msk /*!< AHBM enable */ +#define RCC_BUSENCR_AHB1ENC_Pos (3UL) +#define RCC_BUSENCR_AHB1ENC_Msk (0x1UL << RCC_BUSENCR_AHB1ENC_Pos) /*!< 0x00000008 */ +#define RCC_BUSENCR_AHB1ENC RCC_BUSENCR_AHB1ENC_Msk /*!< AHB1 enable */ +#define RCC_BUSENCR_AHB2ENC_Pos (4UL) +#define RCC_BUSENCR_AHB2ENC_Msk (0x1UL << RCC_BUSENCR_AHB2ENC_Pos) /*!< 0x00000010 */ +#define RCC_BUSENCR_AHB2ENC RCC_BUSENCR_AHB2ENC_Msk /*!< AHB2 enable */ +#define RCC_BUSENCR_AHB3ENC_Pos (5UL) +#define RCC_BUSENCR_AHB3ENC_Msk (0x1UL << RCC_BUSENCR_AHB3ENC_Pos) /*!< 0x00000020 */ +#define RCC_BUSENCR_AHB3ENC RCC_BUSENCR_AHB3ENC_Msk /*!< AHB3 enable */ +#define RCC_BUSENCR_AHB4ENC_Pos (6UL) +#define RCC_BUSENCR_AHB4ENC_Msk (0x1UL << RCC_BUSENCR_AHB4ENC_Pos) /*!< 0x00000040 */ +#define RCC_BUSENCR_AHB4ENC RCC_BUSENCR_AHB4ENC_Msk /*!< AHB4 enable */ +#define RCC_BUSENCR_AHB5ENC_Pos (7UL) +#define RCC_BUSENCR_AHB5ENC_Msk (0x1UL << RCC_BUSENCR_AHB5ENC_Pos) /*!< 0x00000080 */ +#define RCC_BUSENCR_AHB5ENC RCC_BUSENCR_AHB5ENC_Msk /*!< AHB5 enable */ +#define RCC_BUSENCR_APB1ENC_Pos (8UL) +#define RCC_BUSENCR_APB1ENC_Msk (0x1UL << RCC_BUSENCR_APB1ENC_Pos) /*!< 0x00000100 */ +#define RCC_BUSENCR_APB1ENC RCC_BUSENCR_APB1ENC_Msk /*!< APB1 enable */ +#define RCC_BUSENCR_APB2ENC_Pos (9UL) +#define RCC_BUSENCR_APB2ENC_Msk (0x1UL << RCC_BUSENCR_APB2ENC_Pos) /*!< 0x00000200 */ +#define RCC_BUSENCR_APB2ENC RCC_BUSENCR_APB2ENC_Msk /*!< APB2 enable */ +#define RCC_BUSENCR_APB3ENC_Pos (10UL) +#define RCC_BUSENCR_APB3ENC_Msk (0x1UL << RCC_BUSENCR_APB3ENC_Pos) /*!< 0x00000400 */ +#define RCC_BUSENCR_APB3ENC RCC_BUSENCR_APB3ENC_Msk /*!< APB3 enable */ +#define RCC_BUSENCR_APB4ENC_Pos (11UL) +#define RCC_BUSENCR_APB4ENC_Msk (0x1UL << RCC_BUSENCR_APB4ENC_Pos) /*!< 0x00000800 */ +#define RCC_BUSENCR_APB4ENC RCC_BUSENCR_APB4ENC_Msk /*!< APB4 enable */ +#define RCC_BUSENCR_APB5ENC_Pos (12UL) +#define RCC_BUSENCR_APB5ENC_Msk (0x1UL << RCC_BUSENCR_APB5ENC_Pos) /*!< 0x00001000 */ +#define RCC_BUSENCR_APB5ENC RCC_BUSENCR_APB5ENC_Msk /*!< APB5 enable */ + +/***************** Bit definition for RCC_MISCENCR register *****************/ +#define RCC_MISCENCR_DBGENC_Pos (0UL) +#define RCC_MISCENCR_DBGENC_Msk (0x1UL << RCC_MISCENCR_DBGENC_Pos) /*!< 0x00000001 */ +#define RCC_MISCENCR_DBGENC RCC_MISCENCR_DBGENC_Msk /*!< DBG enable */ +#define RCC_MISCENCR_MCO1ENC_Pos (1UL) +#define RCC_MISCENCR_MCO1ENC_Msk (0x1UL << RCC_MISCENCR_MCO1ENC_Pos) /*!< 0x00000002 */ +#define RCC_MISCENCR_MCO1ENC RCC_MISCENCR_MCO1ENC_Msk /*!< MCO1 enable */ +#define RCC_MISCENCR_MCO2ENC_Pos (2UL) +#define RCC_MISCENCR_MCO2ENC_Msk (0x1UL << RCC_MISCENCR_MCO2ENC_Pos) /*!< 0x00000004 */ +#define RCC_MISCENCR_MCO2ENC RCC_MISCENCR_MCO2ENC_Msk /*!< MCO2 enable */ +#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos (3UL) +#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCENCR_XSPIPHYCOMPENC RCC_MISCENCR_XSPIPHYCOMPENC_Msk /*!< XSPIPHYCOMP enable */ +#define RCC_MISCENCR_PERENC_Pos (6UL) +#define RCC_MISCENCR_PERENC_Msk (0x1UL << RCC_MISCENCR_PERENC_Pos) /*!< 0x00000040 */ +#define RCC_MISCENCR_PERENC RCC_MISCENCR_PERENC_Msk /*!< PER enable */ + +/***************** Bit definition for RCC_MEMENCR register ******************/ +#define RCC_MEMENCR_AXISRAM3ENC_Pos (0UL) +#define RCC_MEMENCR_AXISRAM3ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */ +#define RCC_MEMENCR_AXISRAM3ENC RCC_MEMENCR_AXISRAM3ENC_Msk /*!< AXISRAM3 enable */ +#define RCC_MEMENCR_AXISRAM4ENC_Pos (1UL) +#define RCC_MEMENCR_AXISRAM4ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */ +#define RCC_MEMENCR_AXISRAM4ENC RCC_MEMENCR_AXISRAM4ENC_Msk /*!< AXISRAM4 enable */ +#define RCC_MEMENCR_AXISRAM5ENC_Pos (2UL) +#define RCC_MEMENCR_AXISRAM5ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */ +#define RCC_MEMENCR_AXISRAM5ENC RCC_MEMENCR_AXISRAM5ENC_Msk /*!< AXISRAM5 enable */ +#define RCC_MEMENCR_AXISRAM6ENC_Pos (3UL) +#define RCC_MEMENCR_AXISRAM6ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */ +#define RCC_MEMENCR_AXISRAM6ENC RCC_MEMENCR_AXISRAM6ENC_Msk /*!< AXISRAM6 enable */ +#define RCC_MEMENCR_AHBSRAM1ENC_Pos (4UL) +#define RCC_MEMENCR_AHBSRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */ +#define RCC_MEMENCR_AHBSRAM1ENC RCC_MEMENCR_AHBSRAM1ENC_Msk /*!< AHBSRAM1 enable */ +#define RCC_MEMENCR_AHBSRAM2ENC_Pos (5UL) +#define RCC_MEMENCR_AHBSRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */ +#define RCC_MEMENCR_AHBSRAM2ENC RCC_MEMENCR_AHBSRAM2ENC_Msk /*!< AHBSRAM2 enable */ +#define RCC_MEMENCR_BKPSRAMENC_Pos (6UL) +#define RCC_MEMENCR_BKPSRAMENC_Msk (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMENCR_BKPSRAMENC RCC_MEMENCR_BKPSRAMENC_Msk /*!< BKPSRAM enable */ +#define RCC_MEMENCR_AXISRAM1ENC_Pos (7UL) +#define RCC_MEMENCR_AXISRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */ +#define RCC_MEMENCR_AXISRAM1ENC RCC_MEMENCR_AXISRAM1ENC_Msk /*!< AXISRAM1 enable */ +#define RCC_MEMENCR_AXISRAM2ENC_Pos (8UL) +#define RCC_MEMENCR_AXISRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */ +#define RCC_MEMENCR_AXISRAM2ENC RCC_MEMENCR_AXISRAM2ENC_Msk /*!< AXISRAM2 enable */ +#define RCC_MEMENCR_FLEXRAMENC_Pos (9UL) +#define RCC_MEMENCR_FLEXRAMENC_Msk (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMENCR_FLEXRAMENC RCC_MEMENCR_FLEXRAMENC_Msk /*!< FLEXRAM enable */ +#define RCC_MEMENCR_CACHEAXIRAMENC_Pos (10UL) +#define RCC_MEMENCR_CACHEAXIRAMENC_Msk (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos) /*!< 0x00000400 */ +#define RCC_MEMENCR_CACHEAXIRAMENC RCC_MEMENCR_CACHEAXIRAMENC_Msk /*!< CACHEAXIRAM enable */ +#define RCC_MEMENCR_VENCRAMENC_Pos (11UL) +#define RCC_MEMENCR_VENCRAMENC_Msk (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMENCR_VENCRAMENC RCC_MEMENCR_VENCRAMENC_Msk /*!< VENCRAM enable */ +#define RCC_MEMENCR_BOOTROMENC_Pos (12UL) +#define RCC_MEMENCR_BOOTROMENC_Msk (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMENCR_BOOTROMENC RCC_MEMENCR_BOOTROMENC_Msk /*!< Boot ROM enable */ + +/***************** Bit definition for RCC_AHB1ENCR register *****************/ +#define RCC_AHB1ENCR_GPDMA1ENC_Pos (4UL) +#define RCC_AHB1ENCR_GPDMA1ENC_Msk (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENCR_GPDMA1ENC RCC_AHB1ENCR_GPDMA1ENC_Msk /*!< GPDMA1 enable */ +#define RCC_AHB1ENCR_ADC12ENC_Pos (5UL) +#define RCC_AHB1ENCR_ADC12ENC_Msk (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENCR_ADC12ENC RCC_AHB1ENCR_ADC12ENC_Msk /*!< ADC12 enable */ + +/***************** Bit definition for RCC_AHB2ENCR register *****************/ +#define RCC_AHB2ENCR_RAMCFGENC_Pos (12UL) +#define RCC_AHB2ENCR_RAMCFGENC_Msk (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2ENCR_RAMCFGENC RCC_AHB2ENCR_RAMCFGENC_Msk /*!< RAMCFG enable */ +#define RCC_AHB2ENCR_MDF1ENC_Pos (16UL) +#define RCC_AHB2ENCR_MDF1ENC_Msk (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENCR_MDF1ENC RCC_AHB2ENCR_MDF1ENC_Msk /*!< MDF1 enable */ +#define RCC_AHB2ENCR_ADF1ENC_Pos (17UL) +#define RCC_AHB2ENCR_ADF1ENC_Msk (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENCR_ADF1ENC RCC_AHB2ENCR_ADF1ENC_Msk /*!< ADF1 enable */ + +/***************** Bit definition for RCC_AHB3ENCR register *****************/ +#define RCC_AHB3ENCR_RNGENC_Pos (0UL) +#define RCC_AHB3ENCR_RNGENC_Msk (0x1UL << RCC_AHB3ENCR_RNGENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENCR_RNGENC RCC_AHB3ENCR_RNGENC_Msk /*!< RNG enable */ +#define RCC_AHB3ENCR_HASHENC_Pos (1UL) +#define RCC_AHB3ENCR_HASHENC_Msk (0x1UL << RCC_AHB3ENCR_HASHENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENCR_HASHENC RCC_AHB3ENCR_HASHENC_Msk /*!< HASH enable */ +#define RCC_AHB3ENCR_CRYPENC_Pos (2UL) +#define RCC_AHB3ENCR_CRYPENC_Msk (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENCR_CRYPENC RCC_AHB3ENCR_CRYPENC_Msk /*!< CRYP enable */ +#define RCC_AHB3ENCR_SAESENC_Pos (4UL) +#define RCC_AHB3ENCR_SAESENC_Msk (0x1UL << RCC_AHB3ENCR_SAESENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENCR_SAESENC RCC_AHB3ENCR_SAESENC_Msk /*!< SAES enable */ +#define RCC_AHB3ENCR_PKAENC_Pos (8UL) +#define RCC_AHB3ENCR_PKAENC_Msk (0x1UL << RCC_AHB3ENCR_PKAENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB3ENCR_PKAENC RCC_AHB3ENCR_PKAENC_Msk /*!< PKA enable */ +#define RCC_AHB3ENCR_RIFSCENC_Pos (9UL) +#define RCC_AHB3ENCR_RIFSCENC_Msk (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3ENCR_RIFSCENC RCC_AHB3ENCR_RIFSCENC_Msk /*!< RIFSC enable */ +#define RCC_AHB3ENCR_IACENC_Pos (10UL) +#define RCC_AHB3ENCR_IACENC_Msk (0x1UL << RCC_AHB3ENCR_IACENC_Pos) /*!< 0x00000400 */ +#define RCC_AHB3ENCR_IACENC RCC_AHB3ENCR_IACENC_Msk /*!< IAC enable */ +#define RCC_AHB3ENCR_RISAFENC_Pos (14UL) +#define RCC_AHB3ENCR_RISAFENC_Msk (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3ENCR_RISAFENC RCC_AHB3ENCR_RISAFENC_Msk /*!< RISAF enable */ + +/***************** Bit definition for RCC_AHB4ENCR register *****************/ +#define RCC_AHB4ENCR_GPIOAENC_Pos (0UL) +#define RCC_AHB4ENCR_GPIOAENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENCR_GPIOAENC RCC_AHB4ENCR_GPIOAENC_Msk /*!< GPIO A enable */ +#define RCC_AHB4ENCR_GPIOBENC_Pos (1UL) +#define RCC_AHB4ENCR_GPIOBENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENCR_GPIOBENC RCC_AHB4ENCR_GPIOBENC_Msk /*!< GPIO B enable */ +#define RCC_AHB4ENCR_GPIOCENC_Pos (2UL) +#define RCC_AHB4ENCR_GPIOCENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENCR_GPIOCENC RCC_AHB4ENCR_GPIOCENC_Msk /*!< GPIO C enable */ +#define RCC_AHB4ENCR_GPIODENC_Pos (3UL) +#define RCC_AHB4ENCR_GPIODENC_Msk (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENCR_GPIODENC RCC_AHB4ENCR_GPIODENC_Msk /*!< GPIO D enable */ +#define RCC_AHB4ENCR_GPIOEENC_Pos (4UL) +#define RCC_AHB4ENCR_GPIOEENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENCR_GPIOEENC RCC_AHB4ENCR_GPIOEENC_Msk /*!< GPIO E enable */ +#define RCC_AHB4ENCR_GPIOFENC_Pos (5UL) +#define RCC_AHB4ENCR_GPIOFENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENCR_GPIOFENC RCC_AHB4ENCR_GPIOFENC_Msk /*!< GPIO F enable */ +#define RCC_AHB4ENCR_GPIOGENC_Pos (6UL) +#define RCC_AHB4ENCR_GPIOGENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENCR_GPIOGENC RCC_AHB4ENCR_GPIOGENC_Msk /*!< GPIO G enable */ +#define RCC_AHB4ENCR_GPIOHENC_Pos (7UL) +#define RCC_AHB4ENCR_GPIOHENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENCR_GPIOHENC RCC_AHB4ENCR_GPIOHENC_Msk /*!< GPIO H enable */ +#define RCC_AHB4ENCR_GPIONENC_Pos (13UL) +#define RCC_AHB4ENCR_GPIONENC_Msk (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENCR_GPIONENC RCC_AHB4ENCR_GPIONENC_Msk /*!< GPIO N enable */ +#define RCC_AHB4ENCR_GPIOOENC_Pos (14UL) +#define RCC_AHB4ENCR_GPIOOENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENCR_GPIOOENC RCC_AHB4ENCR_GPIOOENC_Msk /*!< GPIO O enable */ +#define RCC_AHB4ENCR_GPIOPENC_Pos (15UL) +#define RCC_AHB4ENCR_GPIOPENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENCR_GPIOPENC RCC_AHB4ENCR_GPIOPENC_Msk /*!< GPIO P enable */ +#define RCC_AHB4ENCR_GPIOQENC_Pos (16UL) +#define RCC_AHB4ENCR_GPIOQENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4ENCR_GPIOQENC RCC_AHB4ENCR_GPIOQENC_Msk /*!< GPIO Q enable */ +#define RCC_AHB4ENCR_PWRENC_Pos (18UL) +#define RCC_AHB4ENCR_PWRENC_Msk (0x1UL << RCC_AHB4ENCR_PWRENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB4ENCR_PWRENC RCC_AHB4ENCR_PWRENC_Msk /*!< PWR enable */ +#define RCC_AHB4ENCR_CRCENC_Pos (19UL) +#define RCC_AHB4ENCR_CRCENC_Msk (0x1UL << RCC_AHB4ENCR_CRCENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENCR_CRCENC RCC_AHB4ENCR_CRCENC_Msk /*!< CRC enable */ + +/***************** Bit definition for RCC_AHB5ENCR register *****************/ +#define RCC_AHB5ENCR_HPDMA1ENC_Pos (0UL) +#define RCC_AHB5ENCR_HPDMA1ENC_Msk (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENCR_HPDMA1ENC RCC_AHB5ENCR_HPDMA1ENC_Msk /*!< HPDMA1 enable */ +#define RCC_AHB5ENCR_DMA2DENC_Pos (1UL) +#define RCC_AHB5ENCR_DMA2DENC_Msk (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENCR_DMA2DENC RCC_AHB5ENCR_DMA2DENC_Msk /*!< DMA2D enable */ +#define RCC_AHB5ENCR_JPEGENC_Pos (3UL) +#define RCC_AHB5ENCR_JPEGENC_Msk (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENCR_JPEGENC RCC_AHB5ENCR_JPEGENC_Msk /*!< JPEG enable */ +#define RCC_AHB5ENCR_FMCENC_Pos (4UL) +#define RCC_AHB5ENCR_FMCENC_Msk (0x1UL << RCC_AHB5ENCR_FMCENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENCR_FMCENC RCC_AHB5ENCR_FMCENC_Msk /*!< FMC enable */ +#define RCC_AHB5ENCR_XSPI1ENC_Pos (5UL) +#define RCC_AHB5ENCR_XSPI1ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENCR_XSPI1ENC RCC_AHB5ENCR_XSPI1ENC_Msk /*!< XSPI1 enable */ +#define RCC_AHB5ENCR_PSSIENC_Pos (6UL) +#define RCC_AHB5ENCR_PSSIENC_Msk (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5ENCR_PSSIENC RCC_AHB5ENCR_PSSIENC_Msk /*!< PSSI enable */ +#define RCC_AHB5ENCR_SDMMC2ENC_Pos (7UL) +#define RCC_AHB5ENCR_SDMMC2ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5ENCR_SDMMC2ENC RCC_AHB5ENCR_SDMMC2ENC_Msk /*!< SDMMC2 enable */ +#define RCC_AHB5ENCR_SDMMC1ENC_Pos (8UL) +#define RCC_AHB5ENCR_SDMMC1ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENCR_SDMMC1ENC RCC_AHB5ENCR_SDMMC1ENC_Msk /*!< SDMMC1 enable */ +#define RCC_AHB5ENCR_XSPI2ENC_Pos (12UL) +#define RCC_AHB5ENCR_XSPI2ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENCR_XSPI2ENC RCC_AHB5ENCR_XSPI2ENC_Msk /*!< XSPI2 enable */ +#define RCC_AHB5ENCR_XSPIMENC_Pos (13UL) +#define RCC_AHB5ENCR_XSPIMENC_Msk (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5ENCR_XSPIMENC RCC_AHB5ENCR_XSPIMENC_Msk /*!< XSPIM enable */ +#define RCC_AHB5ENCR_MCE1ENC_Pos (14UL) +#define RCC_AHB5ENCR_MCE1ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENCR_MCE1ENC RCC_AHB5ENCR_MCE1ENC_Msk /*!< MCE1 enable */ +#define RCC_AHB5ENCR_MCE2ENC_Pos (15UL) +#define RCC_AHB5ENCR_MCE2ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB5ENCR_MCE2ENC RCC_AHB5ENCR_MCE2ENC_Msk /*!< MCE2 enable */ +#define RCC_AHB5ENCR_MCE3ENC_Pos (16UL) +#define RCC_AHB5ENCR_MCE3ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB5ENCR_MCE3ENC RCC_AHB5ENCR_MCE3ENC_Msk /*!< MCE3 enable */ +#define RCC_AHB5ENCR_XSPI3ENC_Pos (17UL) +#define RCC_AHB5ENCR_XSPI3ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5ENCR_XSPI3ENC RCC_AHB5ENCR_XSPI3ENC_Msk /*!< XSPI3 enable */ +#define RCC_AHB5ENCR_MCE4ENC_Pos (18UL) +#define RCC_AHB5ENCR_MCE4ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB5ENCR_MCE4ENC RCC_AHB5ENCR_MCE4ENC_Msk /*!< MCE4 enable */ +#define RCC_AHB5ENCR_GFXMMUENC_Pos (19UL) +#define RCC_AHB5ENCR_GFXMMUENC_Msk (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENCR_GFXMMUENC RCC_AHB5ENCR_GFXMMUENC_Msk /*!< GFXMMU enable */ +#define RCC_AHB5ENCR_GPU2DENC_Pos (20UL) +#define RCC_AHB5ENCR_GPU2DENC_Msk (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENCR_GPU2DENC RCC_AHB5ENCR_GPU2DENC_Msk /*!< GPU2D enable */ +#define RCC_AHB5ENCR_ETH1MACENC_Pos (22UL) +#define RCC_AHB5ENCR_ETH1MACENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */ +#define RCC_AHB5ENCR_ETH1MACENC RCC_AHB5ENCR_ETH1MACENC_Msk /*!< ETH1MAC enable */ +#define RCC_AHB5ENCR_ETH1TXENC_Pos (23UL) +#define RCC_AHB5ENCR_ETH1TXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5ENCR_ETH1TXENC RCC_AHB5ENCR_ETH1TXENC_Msk /*!< ETH1TX enable */ +#define RCC_AHB5ENCR_ETH1RXENC_Pos (24UL) +#define RCC_AHB5ENCR_ETH1RXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5ENCR_ETH1RXENC RCC_AHB5ENCR_ETH1RXENC_Msk /*!< ETH1RX enable */ +#define RCC_AHB5ENCR_ETH1ENC_Pos (25UL) +#define RCC_AHB5ENCR_ETH1ENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5ENCR_ETH1ENC RCC_AHB5ENCR_ETH1ENC_Msk /*!< ETH1 enable */ +#define RCC_AHB5ENCR_OTG1ENC_Pos (26UL) +#define RCC_AHB5ENCR_OTG1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5ENCR_OTG1ENC RCC_AHB5ENCR_OTG1ENC_Msk /*!< OTG1 enable */ +#define RCC_AHB5ENCR_OTGPHY1ENC_Pos (27UL) +#define RCC_AHB5ENCR_OTGPHY1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */ +#define RCC_AHB5ENCR_OTGPHY1ENC RCC_AHB5ENCR_OTGPHY1ENC_Msk /*!< OTGPHY1 enable */ +#define RCC_AHB5ENCR_OTGPHY2ENC_Pos (28UL) +#define RCC_AHB5ENCR_OTGPHY2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */ +#define RCC_AHB5ENCR_OTGPHY2ENC RCC_AHB5ENCR_OTGPHY2ENC_Msk /*!< OTGPHY2 enable */ +#define RCC_AHB5ENCR_OTG2ENC_Pos (29UL) +#define RCC_AHB5ENCR_OTG2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5ENCR_OTG2ENC RCC_AHB5ENCR_OTG2ENC_Msk /*!< OTG2 enable */ +#define RCC_AHB5ENCR_CACHEAXIENC_Pos (30UL) +#define RCC_AHB5ENCR_CACHEAXIENC_Msk (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5ENCR_CACHEAXIENC RCC_AHB5ENCR_CACHEAXIENC_Msk /*!< CACHEAXI enable */ +#define RCC_AHB5ENCR_NPUENC_Pos (31UL) +#define RCC_AHB5ENCR_NPUENC_Msk (0x1UL << RCC_AHB5ENCR_NPUENC_Pos) /*!< 0x80000000 */ +#define RCC_AHB5ENCR_NPUENC RCC_AHB5ENCR_NPUENC_Msk /*!< NPU enable */ + +/**************** Bit definition for RCC_APB1ENCR1 register *****************/ +#define RCC_APB1ENCR1_TIM2ENC_Pos (0UL) +#define RCC_APB1ENCR1_TIM2ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENCR1_TIM2ENC RCC_APB1ENCR1_TIM2ENC_Msk /*!< TIM2 enable */ +#define RCC_APB1ENCR1_TIM3ENC_Pos (1UL) +#define RCC_APB1ENCR1_TIM3ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENCR1_TIM3ENC RCC_APB1ENCR1_TIM3ENC_Msk /*!< TIM3 enable */ +#define RCC_APB1ENCR1_TIM4ENC_Pos (2UL) +#define RCC_APB1ENCR1_TIM4ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENCR1_TIM4ENC RCC_APB1ENCR1_TIM4ENC_Msk /*!< TIM4 enable */ +#define RCC_APB1ENCR1_TIM5ENC_Pos (3UL) +#define RCC_APB1ENCR1_TIM5ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENCR1_TIM5ENC RCC_APB1ENCR1_TIM5ENC_Msk /*!< TIM5 enable */ +#define RCC_APB1ENCR1_TIM6ENC_Pos (4UL) +#define RCC_APB1ENCR1_TIM6ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENCR1_TIM6ENC RCC_APB1ENCR1_TIM6ENC_Msk /*!< TIM6 enable */ +#define RCC_APB1ENCR1_TIM7ENC_Pos (5UL) +#define RCC_APB1ENCR1_TIM7ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR1_TIM7ENC RCC_APB1ENCR1_TIM7ENC_Msk /*!< TIM7 enable */ +#define RCC_APB1ENCR1_TIM12ENC_Pos (6UL) +#define RCC_APB1ENCR1_TIM12ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENCR1_TIM12ENC RCC_APB1ENCR1_TIM12ENC_Msk /*!< TIM12 enable */ +#define RCC_APB1ENCR1_TIM13ENC_Pos (7UL) +#define RCC_APB1ENCR1_TIM13ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENCR1_TIM13ENC RCC_APB1ENCR1_TIM13ENC_Msk /*!< TIM13 enable */ +#define RCC_APB1ENCR1_TIM14ENC_Pos (8UL) +#define RCC_APB1ENCR1_TIM14ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR1_TIM14ENC RCC_APB1ENCR1_TIM14ENC_Msk /*!< TIM14 enable */ +#define RCC_APB1ENCR1_LPTIM1ENC_Pos (9UL) +#define RCC_APB1ENCR1_LPTIM1ENC_Msk (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB1ENCR1_LPTIM1ENC RCC_APB1ENCR1_LPTIM1ENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1ENCR1_TIM10ENC_Pos (12UL) +#define RCC_APB1ENCR1_TIM10ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1ENCR1_TIM10ENC RCC_APB1ENCR1_TIM10ENC_Msk /*!< TIM10 enable */ +#define RCC_APB1ENCR1_TIM11ENC_Pos (13UL) +#define RCC_APB1ENCR1_TIM11ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1ENCR1_TIM11ENC RCC_APB1ENCR1_TIM11ENC_Msk /*!< TIM11 enable */ +#define RCC_APB1ENCR1_SPI2ENC_Pos (14UL) +#define RCC_APB1ENCR1_SPI2ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENCR1_SPI2ENC RCC_APB1ENCR1_SPI2ENC_Msk /*!< SPI2 enable */ +#define RCC_APB1ENCR1_SPI3ENC_Pos (15UL) +#define RCC_APB1ENCR1_SPI3ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENCR1_SPI3ENC RCC_APB1ENCR1_SPI3ENC_Msk /*!< SPI3 enable */ +#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos (16UL) +#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENCR1_SPDIFRX1ENC RCC_APB1ENCR1_SPDIFRX1ENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1ENCR1_USART2ENC_Pos (17UL) +#define RCC_APB1ENCR1_USART2ENC_Msk (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */ +#define RCC_APB1ENCR1_USART2ENC RCC_APB1ENCR1_USART2ENC_Msk /*!< USART2 enable */ +#define RCC_APB1ENCR1_USART3ENC_Pos (18UL) +#define RCC_APB1ENCR1_USART3ENC_Msk (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */ +#define RCC_APB1ENCR1_USART3ENC RCC_APB1ENCR1_USART3ENC_Msk /*!< USART3 enable */ +#define RCC_APB1ENCR1_UART4ENC_Pos (19UL) +#define RCC_APB1ENCR1_UART4ENC_Msk (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENCR1_UART4ENC RCC_APB1ENCR1_UART4ENC_Msk /*!< UART4 enable */ +#define RCC_APB1ENCR1_UART5ENC_Pos (20UL) +#define RCC_APB1ENCR1_UART5ENC_Msk (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENCR1_UART5ENC RCC_APB1ENCR1_UART5ENC_Msk /*!< UART5 enable */ +#define RCC_APB1ENCR1_I2C1ENC_Pos (21UL) +#define RCC_APB1ENCR1_I2C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENCR1_I2C1ENC RCC_APB1ENCR1_I2C1ENC_Msk /*!< I2C1 enable */ +#define RCC_APB1ENCR1_I2C2ENC_Pos (22UL) +#define RCC_APB1ENCR1_I2C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENCR1_I2C2ENC RCC_APB1ENCR1_I2C2ENC_Msk /*!< I2C2 enable */ +#define RCC_APB1ENCR1_I2C3ENC_Pos (23UL) +#define RCC_APB1ENCR1_I2C3ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENCR1_I2C3ENC RCC_APB1ENCR1_I2C3ENC_Msk /*!< I2C3 enable */ +#define RCC_APB1ENCR1_I3C1ENC_Pos (24UL) +#define RCC_APB1ENCR1_I3C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1ENCR1_I3C1ENC RCC_APB1ENCR1_I3C1ENC_Msk /*!< I3C1 enable */ +#define RCC_APB1ENCR1_I3C2ENC_Pos (25UL) +#define RCC_APB1ENCR1_I3C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENCR1_I3C2ENC RCC_APB1ENCR1_I3C2ENC_Msk /*!< I3C2 enable */ +#define RCC_APB1ENCR1_UART7ENC_Pos (30UL) +#define RCC_APB1ENCR1_UART7ENC_Msk (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENCR1_UART7ENC RCC_APB1ENCR1_UART7ENC_Msk /*!< UART7 enable */ +#define RCC_APB1ENCR1_UART8ENC_Pos (31UL) +#define RCC_APB1ENCR1_UART8ENC_Msk (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENCR1_UART8ENC RCC_APB1ENCR1_UART8ENC_Msk /*!< UART8 enable */ + +/**************** Bit definition for RCC_APB1ENCR2 register *****************/ +#define RCC_APB1ENCR2_MDIOSENC_Pos (5UL) +#define RCC_APB1ENCR2_MDIOSENC_Msk (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENCR2_MDIOSENC RCC_APB1ENCR2_MDIOSENC_Msk /*!< MDIOS enable */ +#define RCC_APB1ENCR2_FDCANENC_Pos (8UL) +#define RCC_APB1ENCR2_FDCANENC_Msk (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENCR2_FDCANENC RCC_APB1ENCR2_FDCANENC_Msk /*!< FDCAN enable */ +#define RCC_APB1ENCR2_UCPD1ENC_Pos (18UL) +#define RCC_APB1ENCR2_UCPD1ENC_Msk (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENCR2_UCPD1ENC RCC_APB1ENCR2_UCPD1ENC_Msk /*!< UCPD1 enable */ + +/***************** Bit definition for RCC_APB2ENCR register *****************/ +#define RCC_APB2ENCR_TIM1ENC_Pos (0UL) +#define RCC_APB2ENCR_TIM1ENC_Msk (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENCR_TIM1ENC RCC_APB2ENCR_TIM1ENC_Msk /*!< TIM1 enable */ +#define RCC_APB2ENCR_TIM8ENC_Pos (1UL) +#define RCC_APB2ENCR_TIM8ENC_Msk (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2ENCR_TIM8ENC RCC_APB2ENCR_TIM8ENC_Msk /*!< TIM8 enable */ +#define RCC_APB2ENCR_USART1ENC_Pos (4UL) +#define RCC_APB2ENCR_USART1ENC_Msk (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENCR_USART1ENC RCC_APB2ENCR_USART1ENC_Msk /*!< USART1 enable */ +#define RCC_APB2ENCR_USART6ENC_Pos (5UL) +#define RCC_APB2ENCR_USART6ENC_Msk (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENCR_USART6ENC RCC_APB2ENCR_USART6ENC_Msk /*!< USART6 enable */ +#define RCC_APB2ENCR_UART9ENC_Pos (6UL) +#define RCC_APB2ENCR_UART9ENC_Msk (0x1UL << RCC_APB2ENCR_UART9ENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENCR_UART9ENC RCC_APB2ENCR_UART9ENC_Msk /*!< UART9 enable */ +#define RCC_APB2ENCR_USART10ENC_Pos (7UL) +#define RCC_APB2ENCR_USART10ENC_Msk (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */ +#define RCC_APB2ENCR_USART10ENC RCC_APB2ENCR_USART10ENC_Msk /*!< USART10 enable */ +#define RCC_APB2ENCR_SPI1ENC_Pos (12UL) +#define RCC_APB2ENCR_SPI1ENC_Msk (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENCR_SPI1ENC RCC_APB2ENCR_SPI1ENC_Msk /*!< SPI1 enable */ +#define RCC_APB2ENCR_SPI4ENC_Pos (13UL) +#define RCC_APB2ENCR_SPI4ENC_Msk (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENCR_SPI4ENC RCC_APB2ENCR_SPI4ENC_Msk /*!< SPI4 enable */ +#define RCC_APB2ENCR_TIM18ENC_Pos (15UL) +#define RCC_APB2ENCR_TIM18ENC_Msk (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENCR_TIM18ENC RCC_APB2ENCR_TIM18ENC_Msk /*!< TIM18 enable */ +#define RCC_APB2ENCR_TIM15ENC_Pos (16UL) +#define RCC_APB2ENCR_TIM15ENC_Msk (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENCR_TIM15ENC RCC_APB2ENCR_TIM15ENC_Msk /*!< TIM15 enable */ +#define RCC_APB2ENCR_TIM16ENC_Pos (17UL) +#define RCC_APB2ENCR_TIM16ENC_Msk (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENCR_TIM16ENC RCC_APB2ENCR_TIM16ENC_Msk /*!< TIM16 enable */ +#define RCC_APB2ENCR_TIM17ENC_Pos (18UL) +#define RCC_APB2ENCR_TIM17ENC_Msk (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENCR_TIM17ENC RCC_APB2ENCR_TIM17ENC_Msk /*!< TIM17 enable */ +#define RCC_APB2ENCR_TIM9ENC_Pos (19UL) +#define RCC_APB2ENCR_TIM9ENC_Msk (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENCR_TIM9ENC RCC_APB2ENCR_TIM9ENC_Msk /*!< TIM9 enable */ +#define RCC_APB2ENCR_SPI5ENC_Pos (20UL) +#define RCC_APB2ENCR_SPI5ENC_Msk (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENCR_SPI5ENC RCC_APB2ENCR_SPI5ENC_Msk /*!< SPI5 enable */ +#define RCC_APB2ENCR_SAI1ENC_Pos (21UL) +#define RCC_APB2ENCR_SAI1ENC_Msk (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENCR_SAI1ENC RCC_APB2ENCR_SAI1ENC_Msk /*!< SAI1 enable */ +#define RCC_APB2ENCR_SAI2ENC_Pos (22UL) +#define RCC_APB2ENCR_SAI2ENC_Msk (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENCR_SAI2ENC RCC_APB2ENCR_SAI2ENC_Msk /*!< SAI2 enable */ + +/***************** Bit definition for RCC_APB3ENCR register *****************/ +#define RCC_APB3ENCR_DFTENC_Pos (2UL) +#define RCC_APB3ENCR_DFTENC_Msk (0x1UL << RCC_APB3ENCR_DFTENC_Pos) /*!< 0x00000004 */ +#define RCC_APB3ENCR_DFTENC RCC_APB3ENCR_DFTENC_Msk /*!< DFT enable */ + +/**************** Bit definition for RCC_APB4ENCR1 register *****************/ +#define RCC_APB4ENCR1_HDPENC_Pos (2UL) +#define RCC_APB4ENCR1_HDPENC_Msk (0x1UL << RCC_APB4ENCR1_HDPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR1_HDPENC RCC_APB4ENCR1_HDPENC_Msk /*!< HDP enable */ +#define RCC_APB4ENCR1_LPUART1ENC_Pos (3UL) +#define RCC_APB4ENCR1_LPUART1ENC_Msk (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENCR1_LPUART1ENC RCC_APB4ENCR1_LPUART1ENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4ENCR1_SPI6ENC_Pos (5UL) +#define RCC_APB4ENCR1_SPI6ENC_Msk (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENCR1_SPI6ENC RCC_APB4ENCR1_SPI6ENC_Msk /*!< SPI6 enable */ +#define RCC_APB4ENCR1_I2C4ENC_Pos (7UL) +#define RCC_APB4ENCR1_I2C4ENC_Msk (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4ENCR1_I2C4ENC RCC_APB4ENCR1_I2C4ENC_Msk /*!< I2C4 enable */ +#define RCC_APB4ENCR1_LPTIM2ENC_Pos (9UL) +#define RCC_APB4ENCR1_LPTIM2ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */ +#define RCC_APB4ENCR1_LPTIM2ENC RCC_APB4ENCR1_LPTIM2ENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4ENCR1_LPTIM3ENC_Pos (10UL) +#define RCC_APB4ENCR1_LPTIM3ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */ +#define RCC_APB4ENCR1_LPTIM3ENC RCC_APB4ENCR1_LPTIM3ENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4ENCR1_LPTIM4ENC_Pos (11UL) +#define RCC_APB4ENCR1_LPTIM4ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */ +#define RCC_APB4ENCR1_LPTIM4ENC RCC_APB4ENCR1_LPTIM4ENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4ENCR1_LPTIM5ENC_Pos (12UL) +#define RCC_APB4ENCR1_LPTIM5ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */ +#define RCC_APB4ENCR1_LPTIM5ENC RCC_APB4ENCR1_LPTIM5ENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4ENCR1_VREFBUFENC_Pos (15UL) +#define RCC_APB4ENCR1_VREFBUFENC_Msk (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENCR1_VREFBUFENC RCC_APB4ENCR1_VREFBUFENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4ENCR1_RTCENC_Pos (16UL) +#define RCC_APB4ENCR1_RTCENC_Msk (0x1UL << RCC_APB4ENCR1_RTCENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENCR1_RTCENC RCC_APB4ENCR1_RTCENC_Msk /*!< RTC enable */ +#define RCC_APB4ENCR1_RTCAPBENC_Pos (17UL) +#define RCC_APB4ENCR1_RTCAPBENC_Msk (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */ +#define RCC_APB4ENCR1_RTCAPBENC RCC_APB4ENCR1_RTCAPBENC_Msk /*!< RTCAPB enable */ + +/**************** Bit definition for RCC_APB4ENCR2 register *****************/ +#define RCC_APB4ENCR2_SYSCFGENC_Pos (0UL) +#define RCC_APB4ENCR2_SYSCFGENC_Msk (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */ +#define RCC_APB4ENCR2_SYSCFGENC RCC_APB4ENCR2_SYSCFGENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4ENCR2_BSECENC_Pos (1UL) +#define RCC_APB4ENCR2_BSECENC_Msk (0x1UL << RCC_APB4ENCR2_BSECENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENCR2_BSECENC RCC_APB4ENCR2_BSECENC_Msk /*!< BSEC enable */ +#define RCC_APB4ENCR2_DTSENC_Pos (2UL) +#define RCC_APB4ENCR2_DTSENC_Msk (0x1UL << RCC_APB4ENCR2_DTSENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4ENCR2_DTSENC RCC_APB4ENCR2_DTSENC_Msk /*!< DTS enable */ + +/***************** Bit definition for RCC_APB5ENCR register *****************/ +#define RCC_APB5ENCR_LTDCENC_Pos (1UL) +#define RCC_APB5ENCR_LTDCENC_Msk (0x1UL << RCC_APB5ENCR_LTDCENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENCR_LTDCENC RCC_APB5ENCR_LTDCENC_Msk /*!< LTDC enable */ +#define RCC_APB5ENCR_DCMIPPENC_Pos (2UL) +#define RCC_APB5ENCR_DCMIPPENC_Msk (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENCR_DCMIPPENC RCC_APB5ENCR_DCMIPPENC_Msk /*!< DCMIPP enable */ +#define RCC_APB5ENCR_GFXTIMENC_Pos (4UL) +#define RCC_APB5ENCR_GFXTIMENC_Msk (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENCR_GFXTIMENC RCC_APB5ENCR_GFXTIMENC_Msk /*!< GFXTIM enable */ +#define RCC_APB5ENCR_VENCENC_Pos (5UL) +#define RCC_APB5ENCR_VENCENC_Msk (0x1UL << RCC_APB5ENCR_VENCENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5ENCR_VENCENC RCC_APB5ENCR_VENCENC_Msk /*!< VENC enable */ +#define RCC_APB5ENCR_CSIENC_Pos (6UL) +#define RCC_APB5ENCR_CSIENC_Msk (0x1UL << RCC_APB5ENCR_CSIENC_Pos) /*!< 0x00000040 */ +#define RCC_APB5ENCR_CSIENC RCC_APB5ENCR_CSIENC_Msk /*!< CSI enable */ + +/**************** Bit definition for RCC_BUSLPENCR register *****************/ +#define RCC_BUSLPENCR_ACLKNLPENC_Pos (0UL) +#define RCC_BUSLPENCR_ACLKNLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */ +#define RCC_BUSLPENCR_ACLKNLPENC RCC_BUSLPENCR_ACLKNLPENC_Msk /*!< ACLKN enable in Sleep mode */ +#define RCC_BUSLPENCR_ACLKNCLPENC_Pos (1UL) +#define RCC_BUSLPENCR_ACLKNCLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_BUSLPENCR_ACLKNCLPENC RCC_BUSLPENCR_ACLKNCLPENC_Msk /*!< ACLKNC enable in Sleep mode */ + +/**************** Bit definition for RCC_MISCLPENCR register ****************/ +#define RCC_MISCLPENCR_DBGLPENC_Pos (0UL) +#define RCC_MISCLPENCR_DBGLPENC_Msk (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_MISCLPENCR_DBGLPENC RCC_MISCLPENCR_DBGLPENC_Msk /*!< DBG enable in Sleep mode */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos (3UL) +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos) /*!< 0x00000008 */ +#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk /*!< XSPIPHYCOMP enable in Sleep mode */ +#define RCC_MISCLPENCR_PERLPENC_Pos (6UL) +#define RCC_MISCLPENCR_PERLPENC_Msk (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */ +#define RCC_MISCLPENCR_PERLPENC RCC_MISCLPENCR_PERLPENC_Msk /*!< PER enable in Sleep mode */ + +/**************** Bit definition for RCC_MEMLPENCR register *****************/ +#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos (0UL) +#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos) /*!< 0x00000001 */ +#define RCC_MEMLPENCR_AXISRAM3LPENC RCC_MEMLPENCR_AXISRAM3LPENC_Msk /*!< AXISRAM3 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos (1UL) +#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos) /*!< 0x00000002 */ +#define RCC_MEMLPENCR_AXISRAM4LPENC RCC_MEMLPENCR_AXISRAM4LPENC_Msk /*!< AXISRAM4 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos (2UL) +#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos) /*!< 0x00000004 */ +#define RCC_MEMLPENCR_AXISRAM5LPENC RCC_MEMLPENCR_AXISRAM5LPENC_Msk /*!< AXISRAM5 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos (3UL) +#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos) /*!< 0x00000008 */ +#define RCC_MEMLPENCR_AXISRAM6LPENC RCC_MEMLPENCR_AXISRAM6LPENC_Msk /*!< AXISRAM6 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos (4UL) +#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_MEMLPENCR_AHBSRAM1LPENC RCC_MEMLPENCR_AHBSRAM1LPENC_Msk /*!< AHBSRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos (5UL) +#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos) /*!< 0x00000020 */ +#define RCC_MEMLPENCR_AHBSRAM2LPENC RCC_MEMLPENCR_AHBSRAM2LPENC_Msk /*!< AHBSRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos (6UL) +#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos) /*!< 0x00000040 */ +#define RCC_MEMLPENCR_BKPSRAMLPENC RCC_MEMLPENCR_BKPSRAMLPENC_Msk /*!< BKPSRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos (7UL) +#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos) /*!< 0x00000080 */ +#define RCC_MEMLPENCR_AXISRAM1LPENC RCC_MEMLPENCR_AXISRAM1LPENC_Msk /*!< AXISRAM1 enable in Sleep mode */ +#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos (8UL) +#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos) /*!< 0x00000100 */ +#define RCC_MEMLPENCR_AXISRAM2LPENC RCC_MEMLPENCR_AXISRAM2LPENC_Msk /*!< AXISRAM2 enable in Sleep mode */ +#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos (9UL) +#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos) /*!< 0x00000200 */ +#define RCC_MEMLPENCR_FLEXRAMLPENC RCC_MEMLPENCR_FLEXRAMLPENC_Msk /*!< FLEXRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos (10UL) +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos) /*!< 0x00000400 */ +#define RCC_MEMLPENCR_CACHEAXIRAMLPENC RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk /*!< CACHEAXIRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_VENCRAMLPENC_Pos (11UL) +#define RCC_MEMLPENCR_VENCRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos) /*!< 0x00000800 */ +#define RCC_MEMLPENCR_VENCRAMLPENC RCC_MEMLPENCR_VENCRAMLPENC_Msk /*!< VENCRAM enable in Sleep mode */ +#define RCC_MEMLPENCR_BOOTROMLPENC_Pos (12UL) +#define RCC_MEMLPENCR_BOOTROMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos) /*!< 0x00001000 */ +#define RCC_MEMLPENCR_BOOTROMLPENC RCC_MEMLPENCR_BOOTROMLPENC_Msk /*!< Boot ROM enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB1LPENCR register ****************/ +#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos (4UL) +#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENCR_GPDMA1LPENC RCC_AHB1LPENCR_GPDMA1LPENC_Msk /*!< GPDMA1 enable in Sleep mode */ +#define RCC_AHB1LPENCR_ADC12LPENC_Pos (5UL) +#define RCC_AHB1LPENCR_ADC12LPENC_Msk (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENCR_ADC12LPENC RCC_AHB1LPENCR_ADC12LPENC_Msk /*!< ADC12 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB2LPENCR register ****************/ +#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos (12UL) +#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB2LPENCR_RAMCFGLPENC RCC_AHB2LPENCR_RAMCFGLPENC_Msk /*!< RAMCFG enable in Sleep mode */ +#define RCC_AHB2LPENCR_MDF1LPENC_Pos (16UL) +#define RCC_AHB2LPENCR_MDF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB2LPENCR_MDF1LPENC RCC_AHB2LPENCR_MDF1LPENC_Msk /*!< MDF1 enable in Sleep mode */ +#define RCC_AHB2LPENCR_ADF1LPENC_Pos (17UL) +#define RCC_AHB2LPENCR_ADF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB2LPENCR_ADF1LPENC RCC_AHB2LPENCR_ADF1LPENC_Msk /*!< ADF1 enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB3LPENCR register ****************/ +#define RCC_AHB3LPENCR_RNGLPENC_Pos (0UL) +#define RCC_AHB3LPENCR_RNGLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */ +#define RCC_AHB3LPENCR_RNGLPENC RCC_AHB3LPENCR_RNGLPENC_Msk /*!< RNG enable in Sleep mode */ +#define RCC_AHB3LPENCR_HASHLPENC_Pos (1UL) +#define RCC_AHB3LPENCR_HASHLPENC_Msk (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENCR_HASHLPENC RCC_AHB3LPENCR_HASHLPENC_Msk /*!< HASH enable in Sleep mode */ +#define RCC_AHB3LPENCR_CRYPLPENC_Pos (2UL) +#define RCC_AHB3LPENCR_CRYPLPENC_Msk (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENCR_CRYPLPENC RCC_AHB3LPENCR_CRYPLPENC_Msk /*!< CRYP enable in Sleep mode */ +#define RCC_AHB3LPENCR_SAESLPENC_Pos (4UL) +#define RCC_AHB3LPENCR_SAESLPENC_Msk (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENCR_SAESLPENC RCC_AHB3LPENCR_SAESLPENC_Msk /*!< SAES enable in Sleep mode */ +#define RCC_AHB3LPENCR_PKALPENC_Pos (8UL) +#define RCC_AHB3LPENCR_PKALPENC_Msk (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */ +#define RCC_AHB3LPENCR_PKALPENC RCC_AHB3LPENCR_PKALPENC_Msk /*!< PKA enable in Sleep mode */ +#define RCC_AHB3LPENCR_RIFSCLPENC_Pos (9UL) +#define RCC_AHB3LPENCR_RIFSCLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos) /*!< 0x00000200 */ +#define RCC_AHB3LPENCR_RIFSCLPENC RCC_AHB3LPENCR_RIFSCLPENC_Msk /*!< RIFSC enable in Sleep mode */ +#define RCC_AHB3LPENCR_IACLPENC_Pos (10UL) +#define RCC_AHB3LPENCR_IACLPENC_Msk (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */ +#define RCC_AHB3LPENCR_IACLPENC RCC_AHB3LPENCR_IACLPENC_Msk /*!< IAC enable in Sleep mode */ +#define RCC_AHB3LPENCR_RISAFLPENC_Pos (14UL) +#define RCC_AHB3LPENCR_RISAFLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB3LPENCR_RISAFLPENC RCC_AHB3LPENCR_RISAFLPENC_Msk /*!< RISAF enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB4LPENCR register ****************/ +#define RCC_AHB4LPENCR_GPIOALPENC_Pos (0UL) +#define RCC_AHB4LPENCR_GPIOALPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENCR_GPIOALPENC RCC_AHB4LPENCR_GPIOALPENC_Msk /*!< GPIO A enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOBLPENC_Pos (1UL) +#define RCC_AHB4LPENCR_GPIOBLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENCR_GPIOBLPENC RCC_AHB4LPENCR_GPIOBLPENC_Msk /*!< GPIO B enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOCLPENC_Pos (2UL) +#define RCC_AHB4LPENCR_GPIOCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENCR_GPIOCLPENC RCC_AHB4LPENCR_GPIOCLPENC_Msk /*!< GPIO C enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIODLPENC_Pos (3UL) +#define RCC_AHB4LPENCR_GPIODLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENCR_GPIODLPENC RCC_AHB4LPENCR_GPIODLPENC_Msk /*!< GPIO D enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOELPENC_Pos (4UL) +#define RCC_AHB4LPENCR_GPIOELPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENCR_GPIOELPENC RCC_AHB4LPENCR_GPIOELPENC_Msk /*!< GPIO E enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOFLPENC_Pos (5UL) +#define RCC_AHB4LPENCR_GPIOFLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENCR_GPIOFLPENC RCC_AHB4LPENCR_GPIOFLPENC_Msk /*!< GPIO F enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOGLPENC_Pos (6UL) +#define RCC_AHB4LPENCR_GPIOGLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENCR_GPIOGLPENC RCC_AHB4LPENCR_GPIOGLPENC_Msk /*!< GPIO G enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOHLPENC_Pos (7UL) +#define RCC_AHB4LPENCR_GPIOHLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENCR_GPIOHLPENC RCC_AHB4LPENCR_GPIOHLPENC_Msk /*!< GPIO H enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIONLPENC_Pos (13UL) +#define RCC_AHB4LPENCR_GPIONLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENCR_GPIONLPENC RCC_AHB4LPENCR_GPIONLPENC_Msk /*!< GPIO N enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOOLPENC_Pos (14UL) +#define RCC_AHB4LPENCR_GPIOOLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENCR_GPIOOLPENC RCC_AHB4LPENCR_GPIOOLPENC_Msk /*!< GPIO O enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOPLPENC_Pos (15UL) +#define RCC_AHB4LPENCR_GPIOPLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENCR_GPIOPLPENC RCC_AHB4LPENCR_GPIOPLPENC_Msk /*!< GPIO P enable in Sleep mode */ +#define RCC_AHB4LPENCR_GPIOQLPENC_Pos (16UL) +#define RCC_AHB4LPENCR_GPIOQLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB4LPENCR_GPIOQLPENC RCC_AHB4LPENCR_GPIOQLPENC_Msk /*!< GPIO Q enable in Sleep mode */ +#define RCC_AHB4LPENCR_PWRLPENC_Pos (18UL) +#define RCC_AHB4LPENCR_PWRLPENC_Msk (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */ +#define RCC_AHB4LPENCR_PWRLPENC RCC_AHB4LPENCR_PWRLPENC_Msk /*!< PWR enable in Sleep mode */ +#define RCC_AHB4LPENCR_CRCLPENC_Pos (19UL) +#define RCC_AHB4LPENCR_CRCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */ +#define RCC_AHB4LPENCR_CRCLPENC RCC_AHB4LPENCR_CRCLPENC_Msk /*!< CRC enable in Sleep mode */ + +/**************** Bit definition for RCC_AHB5LPENCR register ****************/ +#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos (0UL) +#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENCR_HPDMA1LPENC RCC_AHB5LPENCR_HPDMA1LPENC_Msk /*!< HPDMA1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_DMA2DLPENC_Pos (1UL) +#define RCC_AHB5LPENCR_DMA2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENCR_DMA2DLPENC RCC_AHB5LPENCR_DMA2DLPENC_Msk /*!< DMA2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_JPEGLPENC_Pos (3UL) +#define RCC_AHB5LPENCR_JPEGLPENC_Msk (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENCR_JPEGLPENC RCC_AHB5LPENCR_JPEGLPENC_Msk /*!< JPEG enable in Sleep mode */ +#define RCC_AHB5LPENCR_FMCLPENC_Pos (4UL) +#define RCC_AHB5LPENCR_FMCLPENC_Msk (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */ +#define RCC_AHB5LPENCR_FMCLPENC RCC_AHB5LPENCR_FMCLPENC_Msk /*!< FMC enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI1LPENC_Pos (5UL) +#define RCC_AHB5LPENCR_XSPI1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENCR_XSPI1LPENC RCC_AHB5LPENCR_XSPI1LPENC_Msk /*!< XSPI1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_PSSILPENC_Pos (6UL) +#define RCC_AHB5LPENCR_PSSILPENC_Msk (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */ +#define RCC_AHB5LPENCR_PSSILPENC RCC_AHB5LPENCR_PSSILPENC_Msk /*!< PSSI enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos (7UL) +#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos) /*!< 0x00000080 */ +#define RCC_AHB5LPENCR_SDMMC2LPENC RCC_AHB5LPENCR_SDMMC2LPENC_Msk /*!< SDMMC2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos (8UL) +#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENCR_SDMMC1LPENC RCC_AHB5LPENCR_SDMMC1LPENC_Msk /*!< SDMMC1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI2LPENC_Pos (12UL) +#define RCC_AHB5LPENCR_XSPI2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENCR_XSPI2LPENC RCC_AHB5LPENCR_XSPI2LPENC_Msk /*!< XSPI2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPIMLPENC_Pos (13UL) +#define RCC_AHB5LPENCR_XSPIMLPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos) /*!< 0x00002000 */ +#define RCC_AHB5LPENCR_XSPIMLPENC RCC_AHB5LPENCR_XSPIMLPENC_Msk /*!< XSPIM enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE1LPENC_Pos (14UL) +#define RCC_AHB5LPENCR_MCE1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENCR_MCE1LPENC RCC_AHB5LPENCR_MCE1LPENC_Msk /*!< MCE1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE2LPENC_Pos (15UL) +#define RCC_AHB5LPENCR_MCE2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */ +#define RCC_AHB5LPENCR_MCE2LPENC RCC_AHB5LPENCR_MCE2LPENC_Msk /*!< MCE2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE3LPENC_Pos (16UL) +#define RCC_AHB5LPENCR_MCE3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */ +#define RCC_AHB5LPENCR_MCE3LPENC RCC_AHB5LPENCR_MCE3LPENC_Msk /*!< MCE3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_XSPI3LPENC_Pos (17UL) +#define RCC_AHB5LPENCR_XSPI3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos) /*!< 0x00020000 */ +#define RCC_AHB5LPENCR_XSPI3LPENC RCC_AHB5LPENCR_XSPI3LPENC_Msk /*!< XSPI3 enable in Sleep mode */ +#define RCC_AHB5LPENCR_MCE4LPENC_Pos (18UL) +#define RCC_AHB5LPENCR_MCE4LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */ +#define RCC_AHB5LPENCR_MCE4LPENC RCC_AHB5LPENCR_MCE4LPENC_Msk /*!< MCE4 enable in Sleep mode */ +#define RCC_AHB5LPENCR_GFXMMULPENC_Pos (19UL) +#define RCC_AHB5LPENCR_GFXMMULPENC_Msk (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENCR_GFXMMULPENC RCC_AHB5LPENCR_GFXMMULPENC_Msk /*!< GFXMMU enable in Sleep mode */ +#define RCC_AHB5LPENCR_GPU2DLPENC_Pos (20UL) +#define RCC_AHB5LPENCR_GPU2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENCR_GPU2DLPENC RCC_AHB5LPENCR_GPU2DLPENC_Msk /*!< GPU2D enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos (22UL) +#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos) /*!< 0x00400000 */ +#define RCC_AHB5LPENCR_ETH1MACLPENC RCC_AHB5LPENCR_ETH1MACLPENC_Msk /*!< ETH1MAC enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos (23UL) +#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos) /*!< 0x00800000 */ +#define RCC_AHB5LPENCR_ETH1TXLPENC RCC_AHB5LPENCR_ETH1TXLPENC_Msk /*!< ETH1TX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos (24UL) +#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos) /*!< 0x01000000 */ +#define RCC_AHB5LPENCR_ETH1RXLPENC RCC_AHB5LPENCR_ETH1RXLPENC_Msk /*!< ETH1RX enable in Sleep mode */ +#define RCC_AHB5LPENCR_ETH1LPENC_Pos (25UL) +#define RCC_AHB5LPENCR_ETH1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */ +#define RCC_AHB5LPENCR_ETH1LPENC RCC_AHB5LPENCR_ETH1LPENC_Msk /*!< ETH1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG1LPENC_Pos (26UL) +#define RCC_AHB5LPENCR_OTG1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */ +#define RCC_AHB5LPENCR_OTG1LPENC RCC_AHB5LPENCR_OTG1LPENC_Msk /*!< OTG1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos (27UL) +#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos) /*!< 0x08000000 */ +#define RCC_AHB5LPENCR_OTGPHY1LPENC RCC_AHB5LPENCR_OTGPHY1LPENC_Msk /*!< OTGPHY1 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos (28UL) +#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENCR_OTGPHY2LPENC RCC_AHB5LPENCR_OTGPHY2LPENC_Msk /*!< OTGPHY2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_OTG2LPENC_Pos (29UL) +#define RCC_AHB5LPENCR_OTG2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENCR_OTG2LPENC RCC_AHB5LPENCR_OTG2LPENC_Msk /*!< OTG2 enable in Sleep mode */ +#define RCC_AHB5LPENCR_CACHEAXILPENC_Pos (30UL) +#define RCC_AHB5LPENCR_CACHEAXILPENC_Msk (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENCR_CACHEAXILPENC RCC_AHB5LPENCR_CACHEAXILPENC_Msk /*!< CACHEAXI enable in Sleep mode */ +#define RCC_AHB5LPENCR_NPULPENC_Pos (31UL) +#define RCC_AHB5LPENCR_NPULPENC_Msk (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */ +#define RCC_AHB5LPENCR_NPULPENC RCC_AHB5LPENCR_NPULPENC_Msk /*!< NPU enable in Sleep mode */ + +/*************** Bit definition for RCC_APB1LPENCR1 register ****************/ +#define RCC_APB1LPENCR1_TIM2LPENC_Pos (0UL) +#define RCC_APB1LPENCR1_TIM2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENCR1_TIM2LPENC RCC_APB1LPENCR1_TIM2LPENC_Msk /*!< TIM2 enable */ +#define RCC_APB1LPENCR1_TIM3LPENC_Pos (1UL) +#define RCC_APB1LPENCR1_TIM3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENCR1_TIM3LPENC RCC_APB1LPENCR1_TIM3LPENC_Msk /*!< TIM3 enable */ +#define RCC_APB1LPENCR1_TIM4LPENC_Pos (2UL) +#define RCC_APB1LPENCR1_TIM4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENCR1_TIM4LPENC RCC_APB1LPENCR1_TIM4LPENC_Msk /*!< TIM4 enable */ +#define RCC_APB1LPENCR1_TIM5LPENC_Pos (3UL) +#define RCC_APB1LPENCR1_TIM5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENCR1_TIM5LPENC RCC_APB1LPENCR1_TIM5LPENC_Msk /*!< TIM5 enable */ +#define RCC_APB1LPENCR1_TIM6LPENC_Pos (4UL) +#define RCC_APB1LPENCR1_TIM6LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENCR1_TIM6LPENC RCC_APB1LPENCR1_TIM6LPENC_Msk /*!< TIM6 enable */ +#define RCC_APB1LPENCR1_TIM7LPENC_Pos (5UL) +#define RCC_APB1LPENCR1_TIM7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR1_TIM7LPENC RCC_APB1LPENCR1_TIM7LPENC_Msk /*!< TIM7 enable */ +#define RCC_APB1LPENCR1_TIM12LPENC_Pos (6UL) +#define RCC_APB1LPENCR1_TIM12LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENCR1_TIM12LPENC RCC_APB1LPENCR1_TIM12LPENC_Msk /*!< TIM12 enable */ +#define RCC_APB1LPENCR1_TIM13LPENC_Pos (7UL) +#define RCC_APB1LPENCR1_TIM13LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENCR1_TIM13LPENC RCC_APB1LPENCR1_TIM13LPENC_Msk /*!< TIM13 enable */ +#define RCC_APB1LPENCR1_TIM14LPENC_Pos (8UL) +#define RCC_APB1LPENCR1_TIM14LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR1_TIM14LPENC RCC_APB1LPENCR1_TIM14LPENC_Msk /*!< TIM14 enable */ +#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos (9UL) +#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB1LPENCR1_LPTIM1LPENC RCC_APB1LPENCR1_LPTIM1LPENC_Msk /*!< LPTIM1 enable */ +#define RCC_APB1LPENCR1_WWDGLPENC_Pos (11UL) +#define RCC_APB1LPENCR1_WWDGLPENC_Msk (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENCR1_WWDGLPENC RCC_APB1LPENCR1_WWDGLPENC_Msk /*!< WWDG enable */ +#define RCC_APB1LPENCR1_TIM10LPENC_Pos (12UL) +#define RCC_APB1LPENCR1_TIM10LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB1LPENCR1_TIM10LPENC RCC_APB1LPENCR1_TIM10LPENC_Msk /*!< TIM10 enable */ +#define RCC_APB1LPENCR1_TIM11LPENC_Pos (13UL) +#define RCC_APB1LPENCR1_TIM11LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB1LPENCR1_TIM11LPENC RCC_APB1LPENCR1_TIM11LPENC_Msk /*!< TIM11 enable */ +#define RCC_APB1LPENCR1_SPI2LPENC_Pos (14UL) +#define RCC_APB1LPENCR1_SPI2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENCR1_SPI2LPENC RCC_APB1LPENCR1_SPI2LPENC_Msk /*!< SPI2 enable */ +#define RCC_APB1LPENCR1_SPI3LPENC_Pos (15UL) +#define RCC_APB1LPENCR1_SPI3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENCR1_SPI3LPENC RCC_APB1LPENCR1_SPI3LPENC_Msk /*!< SPI3 enable */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos (16UL) +#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB1LPENCR1_SPDIFRX1LPENC RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk /*!< SPDIFRX1 enable */ +#define RCC_APB1LPENCR1_USART2LPENC_Pos (17UL) +#define RCC_APB1LPENCR1_USART2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENCR1_USART2LPENC RCC_APB1LPENCR1_USART2LPENC_Msk /*!< USART2 enable */ +#define RCC_APB1LPENCR1_USART3LPENC_Pos (18UL) +#define RCC_APB1LPENCR1_USART3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR1_USART3LPENC RCC_APB1LPENCR1_USART3LPENC_Msk /*!< USART3 enable */ +#define RCC_APB1LPENCR1_UART4LPENC_Pos (19UL) +#define RCC_APB1LPENCR1_UART4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENCR1_UART4LPENC RCC_APB1LPENCR1_UART4LPENC_Msk /*!< UART4 enable */ +#define RCC_APB1LPENCR1_UART5LPENC_Pos (20UL) +#define RCC_APB1LPENCR1_UART5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENCR1_UART5LPENC RCC_APB1LPENCR1_UART5LPENC_Msk /*!< UART5 enable */ +#define RCC_APB1LPENCR1_I2C1LPENC_Pos (21UL) +#define RCC_APB1LPENCR1_I2C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENCR1_I2C1LPENC RCC_APB1LPENCR1_I2C1LPENC_Msk /*!< I2C1 enable */ +#define RCC_APB1LPENCR1_I2C2LPENC_Pos (22UL) +#define RCC_APB1LPENCR1_I2C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENCR1_I2C2LPENC RCC_APB1LPENCR1_I2C2LPENC_Msk /*!< I2C2 enable */ +#define RCC_APB1LPENCR1_I2C3LPENC_Pos (23UL) +#define RCC_APB1LPENCR1_I2C3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENCR1_I2C3LPENC RCC_APB1LPENCR1_I2C3LPENC_Msk /*!< I2C3 enable */ +#define RCC_APB1LPENCR1_I3C1LPENC_Pos (24UL) +#define RCC_APB1LPENCR1_I3C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos) /*!< 0x01000000 */ +#define RCC_APB1LPENCR1_I3C1LPENC RCC_APB1LPENCR1_I3C1LPENC_Msk /*!< I3C1 enable */ +#define RCC_APB1LPENCR1_I3C2LPENC_Pos (25UL) +#define RCC_APB1LPENCR1_I3C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos) /*!< 0x02000000 */ +#define RCC_APB1LPENCR1_I3C2LPENC RCC_APB1LPENCR1_I3C2LPENC_Msk /*!< I3C2 enable */ +#define RCC_APB1LPENCR1_UART7LPENC_Pos (30UL) +#define RCC_APB1LPENCR1_UART7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENCR1_UART7LPENC RCC_APB1LPENCR1_UART7LPENC_Msk /*!< UART7 enable */ +#define RCC_APB1LPENCR1_UART8LPENC_Pos (31UL) +#define RCC_APB1LPENCR1_UART8LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENCR1_UART8LPENC RCC_APB1LPENCR1_UART8LPENC_Msk /*!< UART8 enable */ + +/*************** Bit definition for RCC_APB1LPENCR2 register ****************/ +#define RCC_APB1LPENCR2_MDIOSLPENC_Pos (5UL) +#define RCC_APB1LPENCR2_MDIOSLPENC_Msk (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENCR2_MDIOSLPENC RCC_APB1LPENCR2_MDIOSLPENC_Msk /*!< MDIOS enable */ +#define RCC_APB1LPENCR2_FDCANLPENC_Pos (8UL) +#define RCC_APB1LPENCR2_FDCANLPENC_Msk (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENCR2_FDCANLPENC RCC_APB1LPENCR2_FDCANLPENC_Msk /*!< FDCAN enable */ +#define RCC_APB1LPENCR2_UCPD1LPENC_Pos (18UL) +#define RCC_APB1LPENCR2_UCPD1LPENC_Msk (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB1LPENCR2_UCPD1LPENC RCC_APB1LPENCR2_UCPD1LPENC_Msk /*!< UCPD1 enable */ + +/**************** Bit definition for RCC_APB2LPENCR register ****************/ +#define RCC_APB2LPENCR_TIM1LPENC_Pos (0UL) +#define RCC_APB2LPENCR_TIM1LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENCR_TIM1LPENC RCC_APB2LPENCR_TIM1LPENC_Msk /*!< TIM1 enable */ +#define RCC_APB2LPENCR_TIM8LPENC_Pos (1UL) +#define RCC_APB2LPENCR_TIM8LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB2LPENCR_TIM8LPENC RCC_APB2LPENCR_TIM8LPENC_Msk /*!< TIM8 enable */ +#define RCC_APB2LPENCR_USART1LPENC_Pos (4UL) +#define RCC_APB2LPENCR_USART1LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENCR_USART1LPENC RCC_APB2LPENCR_USART1LPENC_Msk /*!< USART1 enable */ +#define RCC_APB2LPENCR_USART6LPENC_Pos (5UL) +#define RCC_APB2LPENCR_USART6LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENCR_USART6LPENC RCC_APB2LPENCR_USART6LPENC_Msk /*!< USART6 enable */ +#define RCC_APB2LPENCR_UART9LPENC_Pos (6UL) +#define RCC_APB2LPENCR_UART9LPENC_Msk (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos) /*!< 0x00000040 */ +#define RCC_APB2LPENCR_UART9LPENC RCC_APB2LPENCR_UART9LPENC_Msk /*!< UART9 enable */ +#define RCC_APB2LPENCR_USART10LPENC_Pos (7UL) +#define RCC_APB2LPENCR_USART10LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB2LPENCR_USART10LPENC RCC_APB2LPENCR_USART10LPENC_Msk /*!< USART10 enable */ +#define RCC_APB2LPENCR_SPI1LPENC_Pos (12UL) +#define RCC_APB2LPENCR_SPI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENCR_SPI1LPENC RCC_APB2LPENCR_SPI1LPENC_Msk /*!< SPI1 enable */ +#define RCC_APB2LPENCR_SPI4LPENC_Pos (13UL) +#define RCC_APB2LPENCR_SPI4LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENCR_SPI4LPENC RCC_APB2LPENCR_SPI4LPENC_Msk /*!< SPI4 enable */ +#define RCC_APB2LPENCR_TIM18LPENC_Pos (15UL) +#define RCC_APB2LPENCR_TIM18LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB2LPENCR_TIM18LPENC RCC_APB2LPENCR_TIM18LPENC_Msk /*!< TIM18 enable */ +#define RCC_APB2LPENCR_TIM15LPENC_Pos (16UL) +#define RCC_APB2LPENCR_TIM15LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENCR_TIM15LPENC RCC_APB2LPENCR_TIM15LPENC_Msk /*!< TIM15 enable */ +#define RCC_APB2LPENCR_TIM16LPENC_Pos (17UL) +#define RCC_APB2LPENCR_TIM16LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENCR_TIM16LPENC RCC_APB2LPENCR_TIM16LPENC_Msk /*!< TIM16 enable */ +#define RCC_APB2LPENCR_TIM17LPENC_Pos (18UL) +#define RCC_APB2LPENCR_TIM17LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENCR_TIM17LPENC RCC_APB2LPENCR_TIM17LPENC_Msk /*!< TIM17 enable */ +#define RCC_APB2LPENCR_TIM9LPENC_Pos (19UL) +#define RCC_APB2LPENCR_TIM9LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENCR_TIM9LPENC RCC_APB2LPENCR_TIM9LPENC_Msk /*!< TIM9 enable */ +#define RCC_APB2LPENCR_SPI5LPENC_Pos (20UL) +#define RCC_APB2LPENCR_SPI5LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENCR_SPI5LPENC RCC_APB2LPENCR_SPI5LPENC_Msk /*!< SPI5 enable */ +#define RCC_APB2LPENCR_SAI1LPENC_Pos (21UL) +#define RCC_APB2LPENCR_SAI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */ +#define RCC_APB2LPENCR_SAI1LPENC RCC_APB2LPENCR_SAI1LPENC_Msk /*!< SAI1 enable */ +#define RCC_APB2LPENCR_SAI2LPENC_Pos (22UL) +#define RCC_APB2LPENCR_SAI2LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENCR_SAI2LPENC RCC_APB2LPENCR_SAI2LPENC_Msk /*!< SAI2 enable */ + +/**************** Bit definition for RCC_APB3LPENCR register ****************/ +#define RCC_APB3LPENCR_DFTLPENC_Pos (2UL) +#define RCC_APB3LPENCR_DFTLPENC_Msk (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */ +#define RCC_APB3LPENCR_DFTLPENC RCC_APB3LPENCR_DFTLPENC_Msk /*!< DFT enable */ + +/*************** Bit definition for RCC_APB4LPENCR1 register ****************/ +#define RCC_APB4LPENCR1_HDPLPENC_Pos (2UL) +#define RCC_APB4LPENCR1_HDPLPENC_Msk (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR1_HDPLPENC RCC_APB4LPENCR1_HDPLPENC_Msk /*!< HDP enable */ +#define RCC_APB4LPENCR1_LPUART1LPENC_Pos (3UL) +#define RCC_APB4LPENCR1_LPUART1LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos) /*!< 0x00000008 */ +#define RCC_APB4LPENCR1_LPUART1LPENC RCC_APB4LPENCR1_LPUART1LPENC_Msk /*!< LPUART1 enable */ +#define RCC_APB4LPENCR1_SPI6LPENC_Pos (5UL) +#define RCC_APB4LPENCR1_SPI6LPENC_Msk (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENCR1_SPI6LPENC RCC_APB4LPENCR1_SPI6LPENC_Msk /*!< SPI6 enable */ +#define RCC_APB4LPENCR1_I2C4LPENC_Pos (7UL) +#define RCC_APB4LPENCR1_I2C4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos) /*!< 0x00000080 */ +#define RCC_APB4LPENCR1_I2C4LPENC RCC_APB4LPENCR1_I2C4LPENC_Msk /*!< I2C4 enable */ +#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos (9UL) +#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENCR1_LPTIM2LPENC RCC_APB4LPENCR1_LPTIM2LPENC_Msk /*!< LPTIM2 enable */ +#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos (10UL) +#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENCR1_LPTIM3LPENC RCC_APB4LPENCR1_LPTIM3LPENC_Msk /*!< LPTIM3 enable */ +#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos (11UL) +#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENCR1_LPTIM4LPENC RCC_APB4LPENCR1_LPTIM4LPENC_Msk /*!< LPTIM4 enable */ +#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos (12UL) +#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENCR1_LPTIM5LPENC RCC_APB4LPENCR1_LPTIM5LPENC_Msk /*!< LPTIM5 enable */ +#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos (15UL) +#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENCR1_VREFBUFLPENC RCC_APB4LPENCR1_VREFBUFLPENC_Msk /*!< VREFBUF enable */ +#define RCC_APB4LPENCR1_RTCLPENC_Pos (16UL) +#define RCC_APB4LPENCR1_RTCLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENCR1_RTCLPENC RCC_APB4LPENCR1_RTCLPENC_Msk /*!< RTC enable */ +#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos (17UL) +#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos) /*!< 0x00020000 */ +#define RCC_APB4LPENCR1_RTCAPBLPENC RCC_APB4LPENCR1_RTCAPBLPENC_Msk /*!< RTCAPB enable */ + +/*************** Bit definition for RCC_APB4LPENCR2 register ****************/ +#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos (0UL) +#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos) /*!< 0x00000001 */ +#define RCC_APB4LPENCR2_SYSCFGLPENC RCC_APB4LPENCR2_SYSCFGLPENC_Msk /*!< SYSCFG enable */ +#define RCC_APB4LPENCR2_BSECLPENC_Pos (1UL) +#define RCC_APB4LPENCR2_BSECLPENC_Msk (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENCR2_BSECLPENC RCC_APB4LPENCR2_BSECLPENC_Msk /*!< BSEC enable */ +#define RCC_APB4LPENCR2_DTSLPENC_Pos (2UL) +#define RCC_APB4LPENCR2_DTSLPENC_Msk (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB4LPENCR2_DTSLPENC RCC_APB4LPENCR2_DTSLPENC_Msk /*!< DTS enable */ + +/**************** Bit definition for RCC_APB5LPENCR register ****************/ +#define RCC_APB5LPENCR_LTDCLPENC_Pos (1UL) +#define RCC_APB5LPENCR_LTDCLPENC_Msk (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENCR_LTDCLPENC RCC_APB5LPENCR_LTDCLPENC_Msk /*!< LTDC sleep enable */ +#define RCC_APB5LPENCR_DCMIPPLPENC_Pos (2UL) +#define RCC_APB5LPENCR_DCMIPPLPENC_Msk (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENCR_DCMIPPLPENC RCC_APB5LPENCR_DCMIPPLPENC_Msk /*!< DCMIPP sleep enable */ +#define RCC_APB5LPENCR_GFXTIMLPENC_Pos (4UL) +#define RCC_APB5LPENCR_GFXTIMLPENC_Msk (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENCR_GFXTIMLPENC RCC_APB5LPENCR_GFXTIMLPENC_Msk /*!< GFXTIM sleep enable */ +#define RCC_APB5LPENCR_VENCLPENC_Pos (5UL) +#define RCC_APB5LPENCR_VENCLPENC_Msk (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */ +#define RCC_APB5LPENCR_VENCLPENC RCC_APB5LPENCR_VENCLPENC_Msk /*!< VENC sleep enable */ +#define RCC_APB5LPENCR_CSILPENC_Pos (6UL) +#define RCC_APB5LPENCR_CSILPENC_Msk (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */ +#define RCC_APB5LPENCR_CSILPENC RCC_APB5LPENCR_CSILPENC_Msk /*!< CSI sleep enable */ + +/**************** Bit definition for RCC_PRIVCFGCR0 register ****************/ +#define RCC_PRIVCFGCR0_LSIPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR0_LSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR0_LSIPRIVC RCC_PRIVCFGCR0_LSIPRIVC_Msk /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_LSEPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR0_LSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR0_LSEPRIVC RCC_PRIVCFGCR0_LSEPRIVC_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_MSIPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR0_MSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR0_MSIPRIVC RCC_PRIVCFGCR0_MSIPRIVC_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSIPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR0_HSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR0_HSIPRIVC RCC_PRIVCFGCR0_HSIPRIVC_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR0_HSEPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR0_HSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR0_HSEPRIVC RCC_PRIVCFGCR0_HSEPRIVC_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR0 register *****************/ +#define RCC_PUBCFGCR0_LSIPUBC_Pos (0UL) +#define RCC_PUBCFGCR0_LSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR0_LSIPUBC RCC_PUBCFGCR0_LSIPUBC_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_LSEPUBC_Pos (1UL) +#define RCC_PUBCFGCR0_LSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR0_LSEPUBC RCC_PUBCFGCR0_LSEPUBC_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_MSIPUBC_Pos (2UL) +#define RCC_PUBCFGCR0_MSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR0_MSIPUBC RCC_PUBCFGCR0_MSIPUBC_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSIPUBC_Pos (3UL) +#define RCC_PUBCFGCR0_HSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR0_HSIPUBC RCC_PUBCFGCR0_HSIPUBC_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR0_HSEPUBC_Pos (4UL) +#define RCC_PUBCFGCR0_HSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR0_HSEPUBC RCC_PUBCFGCR0_HSEPUBC_Msk /*!< Public protection of HSE configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR1 register ****************/ +#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR1_PLL1PRIVC RCC_PRIVCFGCR1_PLL1PRIVC_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR1_PLL2PRIVC RCC_PRIVCFGCR1_PLL2PRIVC_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR1_PLL3PRIVC RCC_PRIVCFGCR1_PLL3PRIVC_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR1_PLL4PRIVC RCC_PRIVCFGCR1_PLL4PRIVC_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR1 register *****************/ +#define RCC_PUBCFGCR1_PLL1PUBC_Pos (0UL) +#define RCC_PUBCFGCR1_PLL1PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR1_PLL1PUBC RCC_PUBCFGCR1_PLL1PUBC_Msk /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL2PUBC_Pos (1UL) +#define RCC_PUBCFGCR1_PLL2PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR1_PLL2PUBC RCC_PUBCFGCR1_PLL2PUBC_Msk /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL3PUBC_Pos (2UL) +#define RCC_PUBCFGCR1_PLL3PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR1_PLL3PUBC RCC_PUBCFGCR1_PLL3PUBC_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR1_PLL4PUBC_Pos (3UL) +#define RCC_PUBCFGCR1_PLL4PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR1_PLL4PUBC RCC_PUBCFGCR1_PLL4PUBC_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR2 register ****************/ +#define RCC_PRIVCFGCR2_IC1PRIVC_Pos (0UL) +#define RCC_PRIVCFGCR2_IC1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR2_IC1PRIVC RCC_PRIVCFGCR2_IC1PRIVC_Msk /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC2PRIVC_Pos (1UL) +#define RCC_PRIVCFGCR2_IC2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR2_IC2PRIVC RCC_PRIVCFGCR2_IC2PRIVC_Msk /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC3PRIVC_Pos (2UL) +#define RCC_PRIVCFGCR2_IC3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR2_IC3PRIVC RCC_PRIVCFGCR2_IC3PRIVC_Msk /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC4PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR2_IC4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR2_IC4PRIVC RCC_PRIVCFGCR2_IC4PRIVC_Msk /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC5PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR2_IC5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR2_IC5PRIVC RCC_PRIVCFGCR2_IC5PRIVC_Msk /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC6PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR2_IC6PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR2_IC6PRIVC RCC_PRIVCFGCR2_IC6PRIVC_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC7PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR2_IC7PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */ +#define RCC_PRIVCFGCR2_IC7PRIVC RCC_PRIVCFGCR2_IC7PRIVC_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC8PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR2_IC8PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */ +#define RCC_PRIVCFGCR2_IC8PRIVC RCC_PRIVCFGCR2_IC8PRIVC_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC9PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR2_IC9PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */ +#define RCC_PRIVCFGCR2_IC9PRIVC RCC_PRIVCFGCR2_IC9PRIVC_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC10PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR2_IC10PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR2_IC10PRIVC RCC_PRIVCFGCR2_IC10PRIVC_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC11PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR2_IC11PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR2_IC11PRIVC RCC_PRIVCFGCR2_IC11PRIVC_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC12PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR2_IC12PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR2_IC12PRIVC RCC_PRIVCFGCR2_IC12PRIVC_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC13PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR2_IC13PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR2_IC13PRIVC RCC_PRIVCFGCR2_IC13PRIVC_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC14PRIVC_Pos (13UL) +#define RCC_PRIVCFGCR2_IC14PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */ +#define RCC_PRIVCFGCR2_IC14PRIVC RCC_PRIVCFGCR2_IC14PRIVC_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC15PRIVC_Pos (14UL) +#define RCC_PRIVCFGCR2_IC15PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */ +#define RCC_PRIVCFGCR2_IC15PRIVC RCC_PRIVCFGCR2_IC15PRIVC_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC16PRIVC_Pos (15UL) +#define RCC_PRIVCFGCR2_IC16PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */ +#define RCC_PRIVCFGCR2_IC16PRIVC RCC_PRIVCFGCR2_IC16PRIVC_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC17PRIVC_Pos (16UL) +#define RCC_PRIVCFGCR2_IC17PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */ +#define RCC_PRIVCFGCR2_IC17PRIVC RCC_PRIVCFGCR2_IC17PRIVC_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC18PRIVC_Pos (17UL) +#define RCC_PRIVCFGCR2_IC18PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */ +#define RCC_PRIVCFGCR2_IC18PRIVC RCC_PRIVCFGCR2_IC18PRIVC_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC19PRIVC_Pos (18UL) +#define RCC_PRIVCFGCR2_IC19PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */ +#define RCC_PRIVCFGCR2_IC19PRIVC RCC_PRIVCFGCR2_IC19PRIVC_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR2_IC20PRIVC_Pos (19UL) +#define RCC_PRIVCFGCR2_IC20PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */ +#define RCC_PRIVCFGCR2_IC20PRIVC RCC_PRIVCFGCR2_IC20PRIVC_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR2 register *****************/ +#define RCC_PUBCFGCR2_IC1PUBC_Pos (0UL) +#define RCC_PUBCFGCR2_IC1PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR2_IC1PUBC RCC_PUBCFGCR2_IC1PUBC_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC2PUBC_Pos (1UL) +#define RCC_PUBCFGCR2_IC2PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR2_IC2PUBC RCC_PUBCFGCR2_IC2PUBC_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC3PUBC_Pos (2UL) +#define RCC_PUBCFGCR2_IC3PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR2_IC3PUBC RCC_PUBCFGCR2_IC3PUBC_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC4PUBC_Pos (3UL) +#define RCC_PUBCFGCR2_IC4PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR2_IC4PUBC RCC_PUBCFGCR2_IC4PUBC_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC5PUBC_Pos (4UL) +#define RCC_PUBCFGCR2_IC5PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR2_IC5PUBC RCC_PUBCFGCR2_IC5PUBC_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC6PUBC_Pos (5UL) +#define RCC_PUBCFGCR2_IC6PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR2_IC6PUBC RCC_PUBCFGCR2_IC6PUBC_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC7PUBC_Pos (6UL) +#define RCC_PUBCFGCR2_IC7PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR2_IC7PUBC RCC_PUBCFGCR2_IC7PUBC_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC8PUBC_Pos (7UL) +#define RCC_PUBCFGCR2_IC8PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR2_IC8PUBC RCC_PUBCFGCR2_IC8PUBC_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC9PUBC_Pos (8UL) +#define RCC_PUBCFGCR2_IC9PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR2_IC9PUBC RCC_PUBCFGCR2_IC9PUBC_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC10PUBC_Pos (9UL) +#define RCC_PUBCFGCR2_IC10PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR2_IC10PUBC RCC_PUBCFGCR2_IC10PUBC_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC11PUBC_Pos (10UL) +#define RCC_PUBCFGCR2_IC11PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR2_IC11PUBC RCC_PUBCFGCR2_IC11PUBC_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC12PUBC_Pos (11UL) +#define RCC_PUBCFGCR2_IC12PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR2_IC12PUBC RCC_PUBCFGCR2_IC12PUBC_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC13PUBC_Pos (12UL) +#define RCC_PUBCFGCR2_IC13PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR2_IC13PUBC RCC_PUBCFGCR2_IC13PUBC_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC14PUBC_Pos (13UL) +#define RCC_PUBCFGCR2_IC14PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR2_IC14PUBC RCC_PUBCFGCR2_IC14PUBC_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC15PUBC_Pos (14UL) +#define RCC_PUBCFGCR2_IC15PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */ +#define RCC_PUBCFGCR2_IC15PUBC RCC_PUBCFGCR2_IC15PUBC_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC16PUBC_Pos (15UL) +#define RCC_PUBCFGCR2_IC16PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */ +#define RCC_PUBCFGCR2_IC16PUBC RCC_PUBCFGCR2_IC16PUBC_Msk /*!< Public protection of IC16 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC17PUBC_Pos (16UL) +#define RCC_PUBCFGCR2_IC17PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */ +#define RCC_PUBCFGCR2_IC17PUBC RCC_PUBCFGCR2_IC17PUBC_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC18PUBC_Pos (17UL) +#define RCC_PUBCFGCR2_IC18PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */ +#define RCC_PUBCFGCR2_IC18PUBC RCC_PUBCFGCR2_IC18PUBC_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC19PUBC_Pos (18UL) +#define RCC_PUBCFGCR2_IC19PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */ +#define RCC_PUBCFGCR2_IC19PUBC RCC_PUBCFGCR2_IC19PUBC_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR2_IC20PUBC_Pos (19UL) +#define RCC_PUBCFGCR2_IC20PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */ +#define RCC_PUBCFGCR2_IC20PUBC RCC_PUBCFGCR2_IC20PUBC_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR3 register ****************/ +#define RCC_PRIVCFGCR3_MODPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR3_MODPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */ +#define RCC_PRIVCFGCR3_MODPRIVC RCC_PRIVCFGCR3_MODPRIVC_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_SYSPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR3_SYSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */ +#define RCC_PRIVCFGCR3_SYSPRIVC RCC_PRIVCFGCR3_SYSPRIVC_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_BUSPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR3_BUSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */ +#define RCC_PRIVCFGCR3_BUSPRIVC RCC_PRIVCFGCR3_BUSPRIVC_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_PERPRIVC_Pos (3UL) +#define RCC_PRIVCFGCR3_PERPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */ +#define RCC_PRIVCFGCR3_PERPRIVC RCC_PRIVCFGCR3_PERPRIVC_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_INTPRIVC_Pos (4UL) +#define RCC_PRIVCFGCR3_INTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */ +#define RCC_PRIVCFGCR3_INTPRIVC RCC_PRIVCFGCR3_INTPRIVC_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR3_RSTPRIVC_Pos (5UL) +#define RCC_PRIVCFGCR3_RSTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */ +#define RCC_PRIVCFGCR3_RSTPRIVC RCC_PRIVCFGCR3_RSTPRIVC_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR3 register *****************/ +#define RCC_PUBCFGCR3_MODPUBC_Pos (0UL) +#define RCC_PUBCFGCR3_MODPUBC_Msk (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR3_MODPUBC RCC_PUBCFGCR3_MODPUBC_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_SYSPUBC_Pos (1UL) +#define RCC_PUBCFGCR3_SYSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR3_SYSPUBC RCC_PUBCFGCR3_SYSPUBC_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_BUSPUBC_Pos (2UL) +#define RCC_PUBCFGCR3_BUSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR3_BUSPUBC RCC_PUBCFGCR3_BUSPUBC_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_PERPUBC_Pos (3UL) +#define RCC_PUBCFGCR3_PERPUBC_Msk (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR3_PERPUBC RCC_PUBCFGCR3_PERPUBC_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_INTPUBC_Pos (4UL) +#define RCC_PUBCFGCR3_INTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR3_INTPUBC RCC_PUBCFGCR3_INTPUBC_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR3_RSTPUBC_Pos (5UL) +#define RCC_PUBCFGCR3_RSTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR3_RSTPUBC RCC_PUBCFGCR3_RSTPUBC_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PRIVCFGCR4 register ****************/ +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos (0UL) +#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGCR4_ACLKNPRIVC RCC_PRIVCFGCR4_ACLKNPRIVC_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos (1UL) +#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGCR4_ACLKNCPRIVC RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos (2UL) +#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */ +#define RCC_PRIVCFGCR4_AHBMPRIVC RCC_PRIVCFGCR4_AHBMPRIVC_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos (3UL) +#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */ +#define RCC_PRIVCFGCR4_AHB1PRIVC RCC_PRIVCFGCR4_AHB1PRIVC_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos (4UL) +#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */ +#define RCC_PRIVCFGCR4_AHB2PRIVC RCC_PRIVCFGCR4_AHB2PRIVC_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos (5UL) +#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */ +#define RCC_PRIVCFGCR4_AHB3PRIVC RCC_PRIVCFGCR4_AHB3PRIVC_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos (6UL) +#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */ +#define RCC_PRIVCFGCR4_AHB4PRIVC RCC_PRIVCFGCR4_AHB4PRIVC_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos (7UL) +#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */ +#define RCC_PRIVCFGCR4_AHB5PRIVC RCC_PRIVCFGCR4_AHB5PRIVC_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB1PRIVC_Pos (8UL) +#define RCC_PRIVCFGCR4_APB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */ +#define RCC_PRIVCFGCR4_APB1PRIVC RCC_PRIVCFGCR4_APB1PRIVC_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB2PRIVC_Pos (9UL) +#define RCC_PRIVCFGCR4_APB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */ +#define RCC_PRIVCFGCR4_APB2PRIVC RCC_PRIVCFGCR4_APB2PRIVC_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB3PRIVC_Pos (10UL) +#define RCC_PRIVCFGCR4_APB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */ +#define RCC_PRIVCFGCR4_APB3PRIVC RCC_PRIVCFGCR4_APB3PRIVC_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB4PRIVC_Pos (11UL) +#define RCC_PRIVCFGCR4_APB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */ +#define RCC_PRIVCFGCR4_APB4PRIVC RCC_PRIVCFGCR4_APB4PRIVC_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_APB5PRIVC_Pos (12UL) +#define RCC_PRIVCFGCR4_APB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */ +#define RCC_PRIVCFGCR4_APB5PRIVC RCC_PRIVCFGCR4_APB5PRIVC_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PRIVCFGCR4_NOCPRIVC_Pos (13UL) +#define RCC_PRIVCFGCR4_NOCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */ +#define RCC_PRIVCFGCR4_NOCPRIVC RCC_PRIVCFGCR4_NOCPRIVC_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR4 register *****************/ +#define RCC_PUBCFGCR4_ACLKNPUBC_Pos (0UL) +#define RCC_PUBCFGCR4_ACLKNPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */ +#define RCC_PUBCFGCR4_ACLKNPUBC RCC_PUBCFGCR4_ACLKNPUBC_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos (1UL) +#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR4_ACLKNCPUBC RCC_PUBCFGCR4_ACLKNCPUBC_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHBMPUBC_Pos (2UL) +#define RCC_PUBCFGCR4_AHBMPUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR4_AHBMPUBC RCC_PUBCFGCR4_AHBMPUBC_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB1PUBC_Pos (3UL) +#define RCC_PUBCFGCR4_AHB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR4_AHB1PUBC RCC_PUBCFGCR4_AHB1PUBC_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB2PUBC_Pos (4UL) +#define RCC_PUBCFGCR4_AHB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR4_AHB2PUBC RCC_PUBCFGCR4_AHB2PUBC_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB3PUBC_Pos (5UL) +#define RCC_PUBCFGCR4_AHB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR4_AHB3PUBC RCC_PUBCFGCR4_AHB3PUBC_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB4PUBC_Pos (6UL) +#define RCC_PUBCFGCR4_AHB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR4_AHB4PUBC RCC_PUBCFGCR4_AHB4PUBC_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_AHB5PUBC_Pos (7UL) +#define RCC_PUBCFGCR4_AHB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR4_AHB5PUBC RCC_PUBCFGCR4_AHB5PUBC_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB1PUBC_Pos (8UL) +#define RCC_PUBCFGCR4_APB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR4_APB1PUBC RCC_PUBCFGCR4_APB1PUBC_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB2PUBC_Pos (9UL) +#define RCC_PUBCFGCR4_APB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR4_APB2PUBC RCC_PUBCFGCR4_APB2PUBC_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB3PUBC_Pos (10UL) +#define RCC_PUBCFGCR4_APB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR4_APB3PUBC RCC_PUBCFGCR4_APB3PUBC_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB4PUBC_Pos (11UL) +#define RCC_PUBCFGCR4_APB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR4_APB4PUBC RCC_PUBCFGCR4_APB4PUBC_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_APB5PUBC_Pos (12UL) +#define RCC_PUBCFGCR4_APB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */ +#define RCC_PUBCFGCR4_APB5PUBC RCC_PUBCFGCR4_APB5PUBC_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR4_NOCPUBC_Pos (13UL) +#define RCC_PUBCFGCR4_NOCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos) /*!< 0x00002000 */ +#define RCC_PUBCFGCR4_NOCPUBC RCC_PUBCFGCR4_NOCPUBC_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */ + +/**************** Bit definition for RCC_PUBCFGCR5 register *****************/ +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos (0UL) +#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos) /*!< 0x00000001 */ +#define RCC_PUBCFGCR5_AXISRAM3PUBC RCC_PUBCFGCR5_AXISRAM3PUBC_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos (1UL) +#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos) /*!< 0x00000002 */ +#define RCC_PUBCFGCR5_AXISRAM4PUBC RCC_PUBCFGCR5_AXISRAM4PUBC_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos (2UL) +#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos) /*!< 0x00000004 */ +#define RCC_PUBCFGCR5_AXISRAM5PUBC RCC_PUBCFGCR5_AXISRAM5PUBC_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos (3UL) +#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos) /*!< 0x00000008 */ +#define RCC_PUBCFGCR5_AXISRAM6PUBC RCC_PUBCFGCR5_AXISRAM6PUBC_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos (4UL) +#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos) /*!< 0x00000010 */ +#define RCC_PUBCFGCR5_AHBSRAM1PUBC RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos (5UL) +#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos) /*!< 0x00000020 */ +#define RCC_PUBCFGCR5_AHBSRAM2PUBC RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos (6UL) +#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos) /*!< 0x00000040 */ +#define RCC_PUBCFGCR5_BKPSRAMPUBC RCC_PUBCFGCR5_BKPSRAMPUBC_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos (7UL) +#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos) /*!< 0x00000080 */ +#define RCC_PUBCFGCR5_AXISRAM1PUBC RCC_PUBCFGCR5_AXISRAM1PUBC_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos (8UL) +#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos) /*!< 0x00000100 */ +#define RCC_PUBCFGCR5_AXISRAM2PUBC RCC_PUBCFGCR5_AXISRAM2PUBC_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos (9UL) +#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos) /*!< 0x00000200 */ +#define RCC_PUBCFGCR5_FLEXRAMPUBC RCC_PUBCFGCR5_FLEXRAMPUBC_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */ +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos (10UL) +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos) /*!< 0x00000400 */ +#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk /*!< Public protection of CACHEAXIRAM configuration bits */ +#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos (11UL) +#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos) /*!< 0x00000800 */ +#define RCC_PUBCFGCR5_VENCRAMPUBC RCC_PUBCFGCR5_VENCRAMPUBC_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */ + + +/******************************************************************************/ +/* */ +/* Resource Isolation Framework Security Controller (RIFSC) */ +/* */ +/******************************************************************************/ +/**************** Bit definition for RIFSC_RISC_CR register *****************/ +#define RIFSC_RISC_CR_GLOCK_Pos (0UL) +#define RIFSC_RISC_CR_GLOCK_Msk (0x1UL << RIFSC_RISC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_CR_GLOCK RIFSC_RISC_CR_GLOCK_Msk /*!< Global lock */ + +/************* Bit definition for RIFSC_RISC_SECCFGRx register **************/ +#define RIFSC_RISC_SECCFGRx_SEC0_Pos (0UL) +#define RIFSC_RISC_SECCFGRx_SEC0_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_SECCFGRx_SEC0 RIFSC_RISC_SECCFGRx_SEC0_Msk /*!< Security configuration for peripheral 0 */ +#define RIFSC_RISC_SECCFGRx_SEC1_Pos (1UL) +#define RIFSC_RISC_SECCFGRx_SEC1_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_SECCFGRx_SEC1 RIFSC_RISC_SECCFGRx_SEC1_Msk /*!< Security configuration for peripheral 1 */ +#define RIFSC_RISC_SECCFGRx_SEC2_Pos (2UL) +#define RIFSC_RISC_SECCFGRx_SEC2_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_SECCFGRx_SEC2 RIFSC_RISC_SECCFGRx_SEC2_Msk /*!< Security configuration for peripheral 2 */ +#define RIFSC_RISC_SECCFGRx_SEC3_Pos (3UL) +#define RIFSC_RISC_SECCFGRx_SEC3_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_SECCFGRx_SEC3 RIFSC_RISC_SECCFGRx_SEC3_Msk /*!< Security configuration for peripheral 3 */ +#define RIFSC_RISC_SECCFGRx_SEC4_Pos (4UL) +#define RIFSC_RISC_SECCFGRx_SEC4_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_SECCFGRx_SEC4 RIFSC_RISC_SECCFGRx_SEC4_Msk /*!< Security configuration for peripheral 4 */ +#define RIFSC_RISC_SECCFGRx_SEC5_Pos (5UL) +#define RIFSC_RISC_SECCFGRx_SEC5_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_SECCFGRx_SEC5 RIFSC_RISC_SECCFGRx_SEC5_Msk /*!< Security configuration for peripheral 5 */ +#define RIFSC_RISC_SECCFGRx_SEC6_Pos (6UL) +#define RIFSC_RISC_SECCFGRx_SEC6_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_SECCFGRx_SEC6 RIFSC_RISC_SECCFGRx_SEC6_Msk /*!< Security configuration for peripheral 6 */ +#define RIFSC_RISC_SECCFGRx_SEC7_Pos (7UL) +#define RIFSC_RISC_SECCFGRx_SEC7_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_SECCFGRx_SEC7 RIFSC_RISC_SECCFGRx_SEC7_Msk /*!< Security configuration for peripheral 7 */ +#define RIFSC_RISC_SECCFGRx_SEC8_Pos (8UL) +#define RIFSC_RISC_SECCFGRx_SEC8_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_SECCFGRx_SEC8 RIFSC_RISC_SECCFGRx_SEC8_Msk /*!< Security configuration for peripheral 8 */ +#define RIFSC_RISC_SECCFGRx_SEC9_Pos (9UL) +#define RIFSC_RISC_SECCFGRx_SEC9_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_SECCFGRx_SEC9 RIFSC_RISC_SECCFGRx_SEC9_Msk /*!< Security configuration for peripheral 9 */ +#define RIFSC_RISC_SECCFGRx_SEC10_Pos (10UL) +#define RIFSC_RISC_SECCFGRx_SEC10_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_SECCFGRx_SEC10 RIFSC_RISC_SECCFGRx_SEC10_Msk /*!< Security configuration for peripheral 10 */ +#define RIFSC_RISC_SECCFGRx_SEC11_Pos (11UL) +#define RIFSC_RISC_SECCFGRx_SEC11_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_SECCFGRx_SEC11 RIFSC_RISC_SECCFGRx_SEC11_Msk /*!< Security configuration for peripheral 11 */ +#define RIFSC_RISC_SECCFGRx_SEC12_Pos (12UL) +#define RIFSC_RISC_SECCFGRx_SEC12_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_SECCFGRx_SEC12 RIFSC_RISC_SECCFGRx_SEC12_Msk /*!< Security configuration for peripheral 12 */ +#define RIFSC_RISC_SECCFGRx_SEC13_Pos (13UL) +#define RIFSC_RISC_SECCFGRx_SEC13_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_SECCFGRx_SEC13 RIFSC_RISC_SECCFGRx_SEC13_Msk /*!< Security configuration for peripheral 13 */ +#define RIFSC_RISC_SECCFGRx_SEC14_Pos (14UL) +#define RIFSC_RISC_SECCFGRx_SEC14_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_SECCFGRx_SEC14 RIFSC_RISC_SECCFGRx_SEC14_Msk /*!< Security configuration for peripheral 14 */ +#define RIFSC_RISC_SECCFGRx_SEC15_Pos (15UL) +#define RIFSC_RISC_SECCFGRx_SEC15_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_SECCFGRx_SEC15 RIFSC_RISC_SECCFGRx_SEC15_Msk /*!< Security configuration for peripheral 15 */ +#define RIFSC_RISC_SECCFGRx_SEC16_Pos (16UL) +#define RIFSC_RISC_SECCFGRx_SEC16_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_SECCFGRx_SEC16 RIFSC_RISC_SECCFGRx_SEC16_Msk /*!< Security configuration for peripheral 16 */ +#define RIFSC_RISC_SECCFGRx_SEC17_Pos (17UL) +#define RIFSC_RISC_SECCFGRx_SEC17_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_SECCFGRx_SEC17 RIFSC_RISC_SECCFGRx_SEC17_Msk /*!< Security configuration for peripheral 17 */ +#define RIFSC_RISC_SECCFGRx_SEC18_Pos (18UL) +#define RIFSC_RISC_SECCFGRx_SEC18_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_SECCFGRx_SEC18 RIFSC_RISC_SECCFGRx_SEC18_Msk /*!< Security configuration for peripheral 18 */ +#define RIFSC_RISC_SECCFGRx_SEC19_Pos (19UL) +#define RIFSC_RISC_SECCFGRx_SEC19_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_SECCFGRx_SEC19 RIFSC_RISC_SECCFGRx_SEC19_Msk /*!< Security configuration for peripheral 19 */ +#define RIFSC_RISC_SECCFGRx_SEC20_Pos (20UL) +#define RIFSC_RISC_SECCFGRx_SEC20_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_SECCFGRx_SEC20 RIFSC_RISC_SECCFGRx_SEC20_Msk /*!< Security configuration for peripheral 20 */ +#define RIFSC_RISC_SECCFGRx_SEC21_Pos (21UL) +#define RIFSC_RISC_SECCFGRx_SEC21_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_SECCFGRx_SEC21 RIFSC_RISC_SECCFGRx_SEC21_Msk /*!< Security configuration for peripheral 21 */ +#define RIFSC_RISC_SECCFGRx_SEC22_Pos (22UL) +#define RIFSC_RISC_SECCFGRx_SEC22_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_SECCFGRx_SEC22 RIFSC_RISC_SECCFGRx_SEC22_Msk /*!< Security configuration for peripheral 22 */ +#define RIFSC_RISC_SECCFGRx_SEC23_Pos (23UL) +#define RIFSC_RISC_SECCFGRx_SEC23_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_SECCFGRx_SEC23 RIFSC_RISC_SECCFGRx_SEC23_Msk /*!< Security configuration for peripheral 23 */ +#define RIFSC_RISC_SECCFGRx_SEC24_Pos (24UL) +#define RIFSC_RISC_SECCFGRx_SEC24_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_SECCFGRx_SEC24 RIFSC_RISC_SECCFGRx_SEC24_Msk /*!< Security configuration for peripheral 24 */ +#define RIFSC_RISC_SECCFGRx_SEC25_Pos (25UL) +#define RIFSC_RISC_SECCFGRx_SEC25_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_SECCFGRx_SEC25 RIFSC_RISC_SECCFGRx_SEC25_Msk /*!< Security configuration for peripheral 25 */ +#define RIFSC_RISC_SECCFGRx_SEC26_Pos (26UL) +#define RIFSC_RISC_SECCFGRx_SEC26_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_SECCFGRx_SEC26 RIFSC_RISC_SECCFGRx_SEC26_Msk /*!< Security configuration for peripheral 26 */ +#define RIFSC_RISC_SECCFGRx_SEC27_Pos (27UL) +#define RIFSC_RISC_SECCFGRx_SEC27_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_SECCFGRx_SEC27 RIFSC_RISC_SECCFGRx_SEC27_Msk /*!< Security configuration for peripheral 27 */ +#define RIFSC_RISC_SECCFGRx_SEC28_Pos (28UL) +#define RIFSC_RISC_SECCFGRx_SEC28_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_SECCFGRx_SEC28 RIFSC_RISC_SECCFGRx_SEC28_Msk /*!< Security configuration for peripheral 28 */ +#define RIFSC_RISC_SECCFGRx_SEC29_Pos (29UL) +#define RIFSC_RISC_SECCFGRx_SEC29_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_SECCFGRx_SEC29 RIFSC_RISC_SECCFGRx_SEC29_Msk /*!< Security configuration for peripheral 29 */ +#define RIFSC_RISC_SECCFGRx_SEC30_Pos (30UL) +#define RIFSC_RISC_SECCFGRx_SEC30_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_SECCFGRx_SEC30 RIFSC_RISC_SECCFGRx_SEC30_Msk /*!< Security configuration for peripheral 30 */ +#define RIFSC_RISC_SECCFGRx_SEC31_Pos (31UL) +#define RIFSC_RISC_SECCFGRx_SEC31_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_SECCFGRx_SEC31 RIFSC_RISC_SECCFGRx_SEC31_Msk /*!< Security configuration for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_PRIVCFGRx register *************/ +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos (0UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV0 RIFSC_RISC_PRIVCFGRx_PRIV0_Msk /*!< privileged-only access permission for peripheral 0 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos (1UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV1 RIFSC_RISC_PRIVCFGRx_PRIV1_Msk /*!< privileged-only access permission for peripheral 1 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos (2UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV2 RIFSC_RISC_PRIVCFGRx_PRIV2_Msk /*!< privileged-only access permission for peripheral 2 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos (3UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV3 RIFSC_RISC_PRIVCFGRx_PRIV3_Msk /*!< privileged-only access permission for peripheral 3 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos (4UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV4 RIFSC_RISC_PRIVCFGRx_PRIV4_Msk /*!< privileged-only access permission for peripheral 4 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos (5UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV5 RIFSC_RISC_PRIVCFGRx_PRIV5_Msk /*!< privileged-only access permission for peripheral 5 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos (6UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV6 RIFSC_RISC_PRIVCFGRx_PRIV6_Msk /*!< privileged-only access permission for peripheral 6 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos (7UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV7 RIFSC_RISC_PRIVCFGRx_PRIV7_Msk /*!< privileged-only access permission for peripheral 7 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos (8UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV8 RIFSC_RISC_PRIVCFGRx_PRIV8_Msk /*!< privileged-only access permission for peripheral 8 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos (9UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV9 RIFSC_RISC_PRIVCFGRx_PRIV9_Msk /*!< privileged-only access permission for peripheral 9 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos (10UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV10 RIFSC_RISC_PRIVCFGRx_PRIV10_Msk /*!< privileged-only access permission for peripheral 10 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos (11UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV11 RIFSC_RISC_PRIVCFGRx_PRIV11_Msk /*!< privileged-only access permission for peripheral 11 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos (12UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV12 RIFSC_RISC_PRIVCFGRx_PRIV12_Msk /*!< privileged-only access permission for peripheral 12 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos (13UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV13 RIFSC_RISC_PRIVCFGRx_PRIV13_Msk /*!< privileged-only access permission for peripheral 13 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos (14UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV14 RIFSC_RISC_PRIVCFGRx_PRIV14_Msk /*!< privileged-only access permission for peripheral 14 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos (15UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV15 RIFSC_RISC_PRIVCFGRx_PRIV15_Msk /*!< privileged-only access permission for peripheral 15 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos (16UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV16 RIFSC_RISC_PRIVCFGRx_PRIV16_Msk /*!< privileged-only access permission for peripheral 16 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos (17UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV17 RIFSC_RISC_PRIVCFGRx_PRIV17_Msk /*!< privileged-only access permission for peripheral 17 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos (18UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV18 RIFSC_RISC_PRIVCFGRx_PRIV18_Msk /*!< privileged-only access permission for peripheral 18 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos (19UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV19 RIFSC_RISC_PRIVCFGRx_PRIV19_Msk /*!< privileged-only access permission for peripheral 19 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos (20UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV20 RIFSC_RISC_PRIVCFGRx_PRIV20_Msk /*!< privileged-only access permission for peripheral 20 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos (21UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV21 RIFSC_RISC_PRIVCFGRx_PRIV21_Msk /*!< privileged-only access permission for peripheral 21 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos (22UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV22 RIFSC_RISC_PRIVCFGRx_PRIV22_Msk /*!< privileged-only access permission for peripheral 22 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos (23UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV23 RIFSC_RISC_PRIVCFGRx_PRIV23_Msk /*!< privileged-only access permission for peripheral 23 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos (24UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV24 RIFSC_RISC_PRIVCFGRx_PRIV24_Msk /*!< privileged-only access permission for peripheral 24 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos (25UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV25 RIFSC_RISC_PRIVCFGRx_PRIV25_Msk /*!< privileged-only access permission for peripheral 25 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos (26UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV26 RIFSC_RISC_PRIVCFGRx_PRIV26_Msk /*!< privileged-only access permission for peripheral 26 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos (27UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV27 RIFSC_RISC_PRIVCFGRx_PRIV27_Msk /*!< privileged-only access permission for peripheral 27 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos (28UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV28 RIFSC_RISC_PRIVCFGRx_PRIV28_Msk /*!< privileged-only access permission for peripheral 28 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos (29UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV29 RIFSC_RISC_PRIVCFGRx_PRIV29_Msk /*!< privileged-only access permission for peripheral 29 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos (30UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV30 RIFSC_RISC_PRIVCFGRx_PRIV30_Msk /*!< privileged-only access permission for peripheral 30 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos (31UL) +#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_PRIVCFGRx_PRIV31 RIFSC_RISC_PRIVCFGRx_PRIV31_Msk /*!< privileged-only access permission for peripheral 31 */ + +/************* Bit definition for RIFSC_RISC_RCFGLOCKRx register *************/ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos (0UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos) /*!< 0x00000001 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK0 RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk /*!< Resource lock for peripheral 0 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos (1UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos) /*!< 0x00000002 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK1 RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk /*!< Resource lock for peripheral 1 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos (2UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos) /*!< 0x00000004 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK2 RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk /*!< Resource lock for peripheral 2 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos (3UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos) /*!< 0x00000008 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK3 RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk /*!< Resource lock for peripheral 3 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos (4UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos) /*!< 0x00000010 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK4 RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk /*!< Resource lock for peripheral 4 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos (5UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos) /*!< 0x00000020 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK5 RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk /*!< Resource lock for peripheral 5 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos (6UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos) /*!< 0x00000040 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK6 RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk /*!< Resource lock for peripheral 6 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos (7UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos) /*!< 0x00000080 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK7 RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk /*!< Resource lock for peripheral 7 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos (8UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos) /*!< 0x00000100 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK8 RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk /*!< Resource lock for peripheral 8 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos (9UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos) /*!< 0x00000200 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK9 RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk /*!< Resource lock for peripheral 9 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos (10UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos) /*!< 0x00000400 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK10 RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk /*!< Resource lock for peripheral 10 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos (11UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos) /*!< 0x00000800 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK11 RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk /*!< Resource lock for peripheral 11 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos (12UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos) /*!< 0x00001000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK12 RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk /*!< Resource lock for peripheral 12 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos (13UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos) /*!< 0x00002000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK13 RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk /*!< Resource lock for peripheral 13 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos (14UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos) /*!< 0x00004000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK14 RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk /*!< Resource lock for peripheral 14 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos (15UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos) /*!< 0x00008000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK15 RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk /*!< Resource lock for peripheral 15 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos (16UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos) /*!< 0x00010000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK16 RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk /*!< Resource lock for peripheral 16 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos (17UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos) /*!< 0x00020000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK17 RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk /*!< Resource lock for peripheral 17 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos (18UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos) /*!< 0x00040000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK18 RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk /*!< Resource lock for peripheral 18 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos (19UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos) /*!< 0x00080000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK19 RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk /*!< Resource lock for peripheral 19 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos (20UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos) /*!< 0x00100000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK20 RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk /*!< Resource lock for peripheral 20 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos (21UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos) /*!< 0x00200000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK21 RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk /*!< Resource lock for peripheral 21 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos (22UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos) /*!< 0x00400000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK22 RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk /*!< Resource lock for peripheral 22 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos (23UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos) /*!< 0x00800000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK23 RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk /*!< Resource lock for peripheral 23 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos (24UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos) /*!< 0x01000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK24 RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk /*!< Resource lock for peripheral 24 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos (25UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos) /*!< 0x02000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK25 RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk /*!< Resource lock for peripheral 25 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos (26UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos) /*!< 0x04000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK26 RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk /*!< Resource lock for peripheral 26 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos (27UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos) /*!< 0x08000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK27 RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk /*!< Resource lock for peripheral 27 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos (28UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos) /*!< 0x10000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK28 RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk /*!< Resource lock for peripheral 28 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos (29UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos) /*!< 0x20000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK29 RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk /*!< Resource lock for peripheral 29 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos (30UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos) /*!< 0x40000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK30 RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk /*!< Resource lock for peripheral 30 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos (31UL) +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos) /*!< 0x80000000 */ +#define RIFSC_RISC_RCFGLOCKRx_RLOCK31 RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk /*!< Resource lock for peripheral 31 */ + +/**************** Bit definition for RIFSC_RIMC_CR register *****************/ +#define RIFSC_RIMC_CR_GLOCK_Pos (0UL) +#define RIFSC_RIMC_CR_GLOCK_Msk (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RIFSC_RIMC_CR_GLOCK RIFSC_RIMC_CR_GLOCK_Msk /*!< Global lock */ +#define RIFSC_RIMC_CR_DAPCID_Pos (8UL) +#define RIFSC_RIMC_CR_DAPCID_Msk (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000700 */ +#define RIFSC_RIMC_CR_DAPCID RIFSC_RIMC_CR_DAPCID_Msk /*!< Debug access port compartment ID */ +#define RIFSC_RIMC_CR_DAPCID_0 (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_CR_DAPCID_1 (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_CR_DAPCID_2 (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000400 */ + +/*************** Bit definition for RIFSC_RIMC_ATTRx register ***************/ +#define RIFSC_RIMC_ATTRx_MCID_Pos (4UL) +#define RIFSC_RIMC_ATTRx_MCID_Msk (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000070 */ +#define RIFSC_RIMC_ATTRx_MCID RIFSC_RIMC_ATTRx_MCID_Msk /*!< Master CID */ +#define RIFSC_RIMC_ATTRx_MCID_0 (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000010 */ +#define RIFSC_RIMC_ATTRx_MCID_1 (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000020 */ +#define RIFSC_RIMC_ATTRx_MCID_2 (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000040 */ +#define RIFSC_RIMC_ATTRx_MSEC_Pos (8UL) +#define RIFSC_RIMC_ATTRx_MSEC_Msk (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos) /*!< 0x00000100 */ +#define RIFSC_RIMC_ATTRx_MSEC RIFSC_RIMC_ATTRx_MSEC_Msk /*!< Master secure */ +#define RIFSC_RIMC_ATTRx_MPRIV_Pos (9UL) +#define RIFSC_RIMC_ATTRx_MPRIV_Msk (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos) /*!< 0x00000200 */ +#define RIFSC_RIMC_ATTRx_MPRIV RIFSC_RIMC_ATTRx_MPRIV_Msk /*!< Master privileged */ + +/******************************************************************************/ +/* */ +/* Resource Isolation Slave unit for Address space protection (RISAF) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RISAF_CR register *******************/ +#define RISAF_CR_GLOCK_Pos (0UL) +#define RISAF_CR_GLOCK_Msk (0x1UL << RISAF_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define RISAF_CR_GLOCK RISAF_CR_GLOCK_Msk /*!< Global lock */ + +/****************** Bit definition for RISAF_IASR register ******************/ +#define RISAF_IASR_CAEF_Pos (0UL) +#define RISAF_IASR_CAEF_Msk (0x1UL << RISAF_IASR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IASR_CAEF RISAF_IASR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IASR_IAEF_Pos (1UL) +#define RISAF_IASR_IAEF_Msk (0x1UL << RISAF_IASR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IASR_IAEF RISAF_IASR_IAEF_Msk /*!< Illegal access error flag */ + +/****************** Bit definition for RISAF_IACR register ******************/ +#define RISAF_IACR_CAEF_Pos (0UL) +#define RISAF_IACR_CAEF_Msk (0x1UL << RISAF_IACR_CAEF_Pos) /*!< 0x00000001 */ +#define RISAF_IACR_CAEF RISAF_IACR_CAEF_Msk /*!< Configuration access error flag */ +#define RISAF_IACR_IAEF_Pos (1UL) +#define RISAF_IACR_IAEF_Msk (0x1UL << RISAF_IACR_IAEF_Pos) /*!< 0x00000002 */ +#define RISAF_IACR_IAEF RISAF_IACR_IAEF_Msk /*!< Illegal access error flag */ + +/***************** Bit definition for RISAF_IAESR register *****************/ +#define RISAF_IAESR_IACID_Pos (0UL) +#define RISAF_IAESR_IACID_Msk (0x7UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000007 */ +#define RISAF_IAESR_IACID RISAF_IAESR_IACID_Msk /*!< Illegal access compartment ID */ +#define RISAF_IAESR_IACID_0 (0x1UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000001 */ +#define RISAF_IAESR_IACID_1 (0x2UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000002 */ +#define RISAF_IAESR_IACID_2 (0x4UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000004 */ +#define RISAF_IAESR_IAPRIV_Pos (4UL) +#define RISAF_IAESR_IAPRIV_Msk (0x1UL << RISAF_IAESR_IAPRIV_Pos) /*!< 0x00000010 */ +#define RISAF_IAESR_IAPRIV RISAF_IAESR_IAPRIV_Msk /*!< Illegal access privileged */ +#define RISAF_IAESR_IASEC_Pos (5UL) +#define RISAF_IAESR_IASEC_Msk (0x1UL << RISAF_IAESR_IASEC_Pos) /*!< 0x00000020 */ +#define RISAF_IAESR_IASEC RISAF_IAESR_IASEC_Msk /*!< Illegal access security */ +#define RISAF_IAESR_IANRW_Pos (7UL) +#define RISAF_IAESR_IANRW_Msk (0x1UL << RISAF_IAESR_IANRW_Pos) /*!< 0x00000080 */ +#define RISAF_IAESR_IANRW RISAF_IAESR_IANRW_Msk /*!< Illegal access read/write */ + +/***************** Bit definition for RISAF_IADDR register *****************/ +#define RISAF_IADDR_IADD_Pos (0UL) +#define RISAF_IADDR_IADD_Msk (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_IADDR_IADD RISAF_IADDR_IADD_Msk /*!< Illegal address */ +#define RISAF_IADDR_IADD_0 (0x1UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000001 */ +#define RISAF_IADDR_IADD_1 (0x2UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000002 */ +#define RISAF_IADDR_IADD_2 (0x4UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000004 */ +#define RISAF_IADDR_IADD_3 (0x8UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000008 */ +#define RISAF_IADDR_IADD_4 (0x10UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000010 */ +#define RISAF_IADDR_IADD_5 (0x20UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000020 */ +#define RISAF_IADDR_IADD_6 (0x40UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000040 */ +#define RISAF_IADDR_IADD_7 (0x80UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000080 */ +#define RISAF_IADDR_IADD_8 (0x100UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000100 */ +#define RISAF_IADDR_IADD_9 (0x200UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000200 */ +#define RISAF_IADDR_IADD_10 (0x400UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000400 */ +#define RISAF_IADDR_IADD_11 (0x800UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000800 */ +#define RISAF_IADDR_IADD_12 (0x1000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00001000 */ +#define RISAF_IADDR_IADD_13 (0x2000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00002000 */ +#define RISAF_IADDR_IADD_14 (0x4000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00004000 */ +#define RISAF_IADDR_IADD_15 (0x8000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00008000 */ +#define RISAF_IADDR_IADD_16 (0x10000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00010000 */ +#define RISAF_IADDR_IADD_17 (0x20000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00020000 */ +#define RISAF_IADDR_IADD_18 (0x40000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00040000 */ +#define RISAF_IADDR_IADD_19 (0x80000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00080000 */ +#define RISAF_IADDR_IADD_20 (0x100000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00100000 */ +#define RISAF_IADDR_IADD_21 (0x200000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00200000 */ +#define RISAF_IADDR_IADD_22 (0x400000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00400000 */ +#define RISAF_IADDR_IADD_23 (0x800000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00800000 */ +#define RISAF_IADDR_IADD_24 (0x1000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x01000000 */ +#define RISAF_IADDR_IADD_25 (0x2000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x02000000 */ +#define RISAF_IADDR_IADD_26 (0x4000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x04000000 */ +#define RISAF_IADDR_IADD_27 (0x8000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x08000000 */ +#define RISAF_IADDR_IADD_28 (0x10000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x10000000 */ +#define RISAF_IADDR_IADD_29 (0x20000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x20000000 */ +#define RISAF_IADDR_IADD_30 (0x40000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x40000000 */ +#define RISAF_IADDR_IADD_31 (0x80000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_CFGR register ****************/ +#define RISAF_REGx_CFGR_BREN_Pos (0UL) +#define RISAF_REGx_CFGR_BREN_Msk (0x1UL << RISAF_REGx_CFGR_BREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CFGR_BREN RISAF_REGx_CFGR_BREN_Msk /*!< Base region enable */ +#define RISAF_REGx_CFGR_SEC_Pos (8UL) +#define RISAF_REGx_CFGR_SEC_Msk (0x1UL << RISAF_REGx_CFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_CFGR_SEC RISAF_REGx_CFGR_SEC_Msk /*!< Secure region */ +#define RISAF_REGx_CFGR_PRIVC0_Pos (16UL) +#define RISAF_REGx_CFGR_PRIVC0_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CFGR_PRIVC0 RISAF_REGx_CFGR_PRIVC0_Msk /*!< Privileged access for compartment 0 */ +#define RISAF_REGx_CFGR_PRIVC1_Pos (17UL) +#define RISAF_REGx_CFGR_PRIVC1_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CFGR_PRIVC1 RISAF_REGx_CFGR_PRIVC1_Msk /*!< Privileged access for compartment 1 */ +#define RISAF_REGx_CFGR_PRIVC2_Pos (18UL) +#define RISAF_REGx_CFGR_PRIVC2_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CFGR_PRIVC2 RISAF_REGx_CFGR_PRIVC2_Msk /*!< Privileged access for compartment 2 */ +#define RISAF_REGx_CFGR_PRIVC3_Pos (19UL) +#define RISAF_REGx_CFGR_PRIVC3_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CFGR_PRIVC3 RISAF_REGx_CFGR_PRIVC3_Msk /*!< Privileged access for compartment 3 */ +#define RISAF_REGx_CFGR_PRIVC4_Pos (20UL) +#define RISAF_REGx_CFGR_PRIVC4_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CFGR_PRIVC4 RISAF_REGx_CFGR_PRIVC4_Msk /*!< Privileged access for compartment 4 */ +#define RISAF_REGx_CFGR_PRIVC5_Pos (21UL) +#define RISAF_REGx_CFGR_PRIVC5_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CFGR_PRIVC5 RISAF_REGx_CFGR_PRIVC5_Msk /*!< Privileged access for compartment 5 */ +#define RISAF_REGx_CFGR_PRIVC6_Pos (22UL) +#define RISAF_REGx_CFGR_PRIVC6_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CFGR_PRIVC6 RISAF_REGx_CFGR_PRIVC6_Msk /*!< Privileged access for compartment 6 */ +#define RISAF_REGx_CFGR_PRIVC7_Pos (23UL) +#define RISAF_REGx_CFGR_PRIVC7_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CFGR_PRIVC7 RISAF_REGx_CFGR_PRIVC7_Msk /*!< Privileged access for compartment 7 */ + +/************** Bit definition for RISAF_REGx_STARTR register ***************/ +#define RISAF_REGx_STARTR_BADDSTART_Pos (0UL) +#define RISAF_REGx_STARTR_BADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_STARTR_BADDSTART RISAF_REGx_STARTR_BADDSTART_Msk /*!< Base region address start */ +#define RISAF_REGx_STARTR_BADDSTART_0 (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_STARTR_BADDSTART_1 (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_STARTR_BADDSTART_2 (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_STARTR_BADDSTART_3 (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_STARTR_BADDSTART_4 (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_STARTR_BADDSTART_5 (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_STARTR_BADDSTART_6 (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_STARTR_BADDSTART_7 (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_STARTR_BADDSTART_8 (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_STARTR_BADDSTART_9 (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_STARTR_BADDSTART_10 (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_STARTR_BADDSTART_11 (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_STARTR_BADDSTART_12 (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_STARTR_BADDSTART_13 (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_STARTR_BADDSTART_14 (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_STARTR_BADDSTART_15 (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_STARTR_BADDSTART_16 (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_STARTR_BADDSTART_17 (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_STARTR_BADDSTART_18 (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_STARTR_BADDSTART_19 (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_STARTR_BADDSTART_20 (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_STARTR_BADDSTART_21 (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_STARTR_BADDSTART_22 (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_STARTR_BADDSTART_23 (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_STARTR_BADDSTART_24 (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_STARTR_BADDSTART_25 (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_STARTR_BADDSTART_26 (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_STARTR_BADDSTART_27 (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_STARTR_BADDSTART_28 (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_STARTR_BADDSTART_29 (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_STARTR_BADDSTART_30 (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_STARTR_BADDSTART_31 (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_ENDR register ****************/ +#define RISAF_REGx_ENDR_BADDEND_Pos (0UL) +#define RISAF_REGx_ENDR_BADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_ENDR_BADDEND RISAF_REGx_ENDR_BADDEND_Msk /*!< Base region address end */ +#define RISAF_REGx_ENDR_BADDEND_0 (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_ENDR_BADDEND_1 (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_ENDR_BADDEND_2 (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_ENDR_BADDEND_3 (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_ENDR_BADDEND_4 (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_ENDR_BADDEND_5 (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_ENDR_BADDEND_6 (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_ENDR_BADDEND_7 (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_ENDR_BADDEND_8 (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_ENDR_BADDEND_9 (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_ENDR_BADDEND_10 (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_ENDR_BADDEND_11 (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_ENDR_BADDEND_12 (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_ENDR_BADDEND_13 (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_ENDR_BADDEND_14 (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_ENDR_BADDEND_15 (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_ENDR_BADDEND_16 (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_ENDR_BADDEND_17 (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_ENDR_BADDEND_18 (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_ENDR_BADDEND_19 (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_ENDR_BADDEND_20 (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_ENDR_BADDEND_21 (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_ENDR_BADDEND_22 (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_ENDR_BADDEND_23 (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_ENDR_BADDEND_24 (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_ENDR_BADDEND_25 (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_ENDR_BADDEND_26 (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_ENDR_BADDEND_27 (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_ENDR_BADDEND_28 (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_ENDR_BADDEND_29 (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_ENDR_BADDEND_30 (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_ENDR_BADDEND_31 (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_CIDCFGR register **************/ +#define RISAF_REGx_CIDCFGR_RDENC0_Pos (0UL) +#define RISAF_REGx_CIDCFGR_RDENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_CIDCFGR_RDENC0 RISAF_REGx_CIDCFGR_RDENC0_Msk /*!< Read enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_RDENC1_Pos (1UL) +#define RISAF_REGx_CIDCFGR_RDENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_CIDCFGR_RDENC1 RISAF_REGx_CIDCFGR_RDENC1_Msk /*!< Read enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_RDENC2_Pos (2UL) +#define RISAF_REGx_CIDCFGR_RDENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_CIDCFGR_RDENC2 RISAF_REGx_CIDCFGR_RDENC2_Msk /*!< Read enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_RDENC3_Pos (3UL) +#define RISAF_REGx_CIDCFGR_RDENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_CIDCFGR_RDENC3 RISAF_REGx_CIDCFGR_RDENC3_Msk /*!< Read enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_RDENC4_Pos (4UL) +#define RISAF_REGx_CIDCFGR_RDENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_CIDCFGR_RDENC4 RISAF_REGx_CIDCFGR_RDENC4_Msk /*!< Read enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_RDENC5_Pos (5UL) +#define RISAF_REGx_CIDCFGR_RDENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_CIDCFGR_RDENC5 RISAF_REGx_CIDCFGR_RDENC5_Msk /*!< Read enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_RDENC6_Pos (6UL) +#define RISAF_REGx_CIDCFGR_RDENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_CIDCFGR_RDENC6 RISAF_REGx_CIDCFGR_RDENC6_Msk /*!< Read enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_RDENC7_Pos (7UL) +#define RISAF_REGx_CIDCFGR_RDENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_CIDCFGR_RDENC7 RISAF_REGx_CIDCFGR_RDENC7_Msk /*!< Read enable for compartment 7 */ +#define RISAF_REGx_CIDCFGR_WRENC0_Pos (16UL) +#define RISAF_REGx_CIDCFGR_WRENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_CIDCFGR_WRENC0 RISAF_REGx_CIDCFGR_WRENC0_Msk /*!< Write enable for compartment 0 */ +#define RISAF_REGx_CIDCFGR_WRENC1_Pos (17UL) +#define RISAF_REGx_CIDCFGR_WRENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_CIDCFGR_WRENC1 RISAF_REGx_CIDCFGR_WRENC1_Msk /*!< Write enable for compartment 1 */ +#define RISAF_REGx_CIDCFGR_WRENC2_Pos (18UL) +#define RISAF_REGx_CIDCFGR_WRENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_CIDCFGR_WRENC2 RISAF_REGx_CIDCFGR_WRENC2_Msk /*!< Write enable for compartment 2 */ +#define RISAF_REGx_CIDCFGR_WRENC3_Pos (19UL) +#define RISAF_REGx_CIDCFGR_WRENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_CIDCFGR_WRENC3 RISAF_REGx_CIDCFGR_WRENC3_Msk /*!< Write enable for compartment 3 */ +#define RISAF_REGx_CIDCFGR_WRENC4_Pos (20UL) +#define RISAF_REGx_CIDCFGR_WRENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_CIDCFGR_WRENC4 RISAF_REGx_CIDCFGR_WRENC4_Msk /*!< Write enable for compartment 4 */ +#define RISAF_REGx_CIDCFGR_WRENC5_Pos (21UL) +#define RISAF_REGx_CIDCFGR_WRENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_CIDCFGR_WRENC5 RISAF_REGx_CIDCFGR_WRENC5_Msk /*!< Write enable for compartment 5 */ +#define RISAF_REGx_CIDCFGR_WRENC6_Pos (22UL) +#define RISAF_REGx_CIDCFGR_WRENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_CIDCFGR_WRENC6 RISAF_REGx_CIDCFGR_WRENC6_Msk /*!< Write enable for compartment 6 */ +#define RISAF_REGx_CIDCFGR_WRENC7_Pos (23UL) +#define RISAF_REGx_CIDCFGR_WRENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_CIDCFGR_WRENC7 RISAF_REGx_CIDCFGR_WRENC7_Msk /*!< Write enable for compartment 7 */ + +/*************** Bit definition for RISAF_REGx_zCFGR register ***************/ +#define RISAF_REGx_zCFGR_SREN_Pos (0UL) +#define RISAF_REGx_zCFGR_SREN_Msk (0x1UL << RISAF_REGx_zCFGR_SREN_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zCFGR_SREN RISAF_REGx_zCFGR_SREN_Msk /*!< Subregion enable */ +#define RISAF_REGx_zCFGR_RLOCK_Pos (1UL) +#define RISAF_REGx_zCFGR_RLOCK_Msk (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zCFGR_RLOCK RISAF_REGx_zCFGR_RLOCK_Msk /*!< Resource lock */ +#define RISAF_REGx_zCFGR_SRCID_Pos (4UL) +#define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zCFGR_SRCID RISAF_REGx_zCFGR_SRCID_Msk /*!< Subregion CID */ +#define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zCFGR_SEC_Pos (8UL) +#define RISAF_REGx_zCFGR_SEC_Msk (0x1UL << RISAF_REGx_zCFGR_SEC_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zCFGR_SEC RISAF_REGx_zCFGR_SEC_Msk /*!< Secure subregion */ +#define RISAF_REGx_zCFGR_PRIV_Pos (9UL) +#define RISAF_REGx_zCFGR_PRIV_Msk (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zCFGR_PRIV RISAF_REGx_zCFGR_PRIV_Msk /*!< Privileged subregion */ +#define RISAF_REGx_zCFGR_RDEN_Pos (12UL) +#define RISAF_REGx_zCFGR_RDEN_Msk (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zCFGR_RDEN RISAF_REGx_zCFGR_RDEN_Msk /*!< Read enable */ +#define RISAF_REGx_zCFGR_WREN_Pos (13UL) +#define RISAF_REGx_zCFGR_WREN_Msk (0x1UL << RISAF_REGx_zCFGR_WREN_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zCFGR_WREN RISAF_REGx_zCFGR_WREN_Msk /*!< Write enable */ + +/************** Bit definition for RISAF_REGx_zSTARTR register **************/ +#define RISAF_REGx_zSTARTR_SADDSTART_Pos (0UL) +#define RISAF_REGx_zSTARTR_SADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zSTARTR_SADDSTART RISAF_REGx_zSTARTR_SADDSTART_Msk /*!< Subregion address start */ +#define RISAF_REGx_zSTARTR_SADDSTART_0 (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zSTARTR_SADDSTART_1 (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zSTARTR_SADDSTART_2 (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zSTARTR_SADDSTART_3 (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zSTARTR_SADDSTART_4 (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zSTARTR_SADDSTART_5 (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zSTARTR_SADDSTART_6 (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zSTARTR_SADDSTART_7 (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zSTARTR_SADDSTART_8 (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zSTARTR_SADDSTART_9 (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zSTARTR_SADDSTART_10 (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zSTARTR_SADDSTART_11 (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zSTARTR_SADDSTART_12 (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_13 (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_14 (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_15 (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_16 (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_17 (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_18 (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_19 (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_20 (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_21 (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_22 (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_23 (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_24 (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_25 (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_26 (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_27 (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_28 (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_29 (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_30 (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zSTARTR_SADDSTART_31 (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RISAF_REGx_zENDR register ***************/ +#define RISAF_REGx_zENDR_SADDEND_Pos (0UL) +#define RISAF_REGx_zENDR_SADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0xFFFFFFFF */ +#define RISAF_REGx_zENDR_SADDEND RISAF_REGx_zENDR_SADDEND_Msk /*!< Subregion address end */ +#define RISAF_REGx_zENDR_SADDEND_0 (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000001 */ +#define RISAF_REGx_zENDR_SADDEND_1 (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000002 */ +#define RISAF_REGx_zENDR_SADDEND_2 (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zENDR_SADDEND_3 (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000008 */ +#define RISAF_REGx_zENDR_SADDEND_4 (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zENDR_SADDEND_5 (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zENDR_SADDEND_6 (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000040 */ +#define RISAF_REGx_zENDR_SADDEND_7 (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000080 */ +#define RISAF_REGx_zENDR_SADDEND_8 (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000100 */ +#define RISAF_REGx_zENDR_SADDEND_9 (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000200 */ +#define RISAF_REGx_zENDR_SADDEND_10 (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000400 */ +#define RISAF_REGx_zENDR_SADDEND_11 (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000800 */ +#define RISAF_REGx_zENDR_SADDEND_12 (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00001000 */ +#define RISAF_REGx_zENDR_SADDEND_13 (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00002000 */ +#define RISAF_REGx_zENDR_SADDEND_14 (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00004000 */ +#define RISAF_REGx_zENDR_SADDEND_15 (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00008000 */ +#define RISAF_REGx_zENDR_SADDEND_16 (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00010000 */ +#define RISAF_REGx_zENDR_SADDEND_17 (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00020000 */ +#define RISAF_REGx_zENDR_SADDEND_18 (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00040000 */ +#define RISAF_REGx_zENDR_SADDEND_19 (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00080000 */ +#define RISAF_REGx_zENDR_SADDEND_20 (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00100000 */ +#define RISAF_REGx_zENDR_SADDEND_21 (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00200000 */ +#define RISAF_REGx_zENDR_SADDEND_22 (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00400000 */ +#define RISAF_REGx_zENDR_SADDEND_23 (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00800000 */ +#define RISAF_REGx_zENDR_SADDEND_24 (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x01000000 */ +#define RISAF_REGx_zENDR_SADDEND_25 (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x02000000 */ +#define RISAF_REGx_zENDR_SADDEND_26 (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x04000000 */ +#define RISAF_REGx_zENDR_SADDEND_27 (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x08000000 */ +#define RISAF_REGx_zENDR_SADDEND_28 (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x10000000 */ +#define RISAF_REGx_zENDR_SADDEND_29 (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x20000000 */ +#define RISAF_REGx_zENDR_SADDEND_30 (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x40000000 */ +#define RISAF_REGx_zENDR_SADDEND_31 (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x80000000 */ + +/************** Bit definition for RISAF_REGx_zNESTR register ***************/ +#define RISAF_REGx_zNESTR_DCEN_Pos (2UL) +#define RISAF_REGx_zNESTR_DCEN_Msk (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos) /*!< 0x00000004 */ +#define RISAF_REGx_zNESTR_DCEN RISAF_REGx_zNESTR_DCEN_Msk /*!< Delegated configuration enable */ +#define RISAF_REGx_zNESTR_DCCID_Pos (4UL) +#define RISAF_REGx_zNESTR_DCCID_Msk (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000070 */ +#define RISAF_REGx_zNESTR_DCCID RISAF_REGx_zNESTR_DCCID_Msk /*!< Delegated configuration CID */ +#define RISAF_REGx_zNESTR_DCCID_0 (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000010 */ +#define RISAF_REGx_zNESTR_DCCID_1 (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000020 */ +#define RISAF_REGx_zNESTR_DCCID_2 (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000040 */ + +/******************************************************************************/ +/* */ +/* (IAC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IAC_IER0 register *******************/ +#define IAC_IERx_IAIE0_Pos (0UL) +#define IAC_IERx_IAIE0_Msk (0x1UL << IAC_IERx_IAIE0_Pos) /*!< 0x00000001 */ +#define IAC_IERx_IAIE0 IAC_IERx_IAIE0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_IERx_IAIE1_Pos (1UL) +#define IAC_IERx_IAIE1_Msk (0x1UL << IAC_IERx_IAIE1_Pos) /*!< 0x00000002 */ +#define IAC_IERx_IAIE1 IAC_IERx_IAIE1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_IERx_IAIE2_Pos (2UL) +#define IAC_IERx_IAIE2_Msk (0x1UL << IAC_IERx_IAIE2_Pos) /*!< 0x00000004 */ +#define IAC_IERx_IAIE2 IAC_IERx_IAIE2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_IERx_IAIE3_Pos (3UL) +#define IAC_IERx_IAIE3_Msk (0x1UL << IAC_IERx_IAIE3_Pos) /*!< 0x00000008 */ +#define IAC_IERx_IAIE3 IAC_IERx_IAIE3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_IERx_IAIE4_Pos (4UL) +#define IAC_IERx_IAIE4_Msk (0x1UL << IAC_IERx_IAIE4_Pos) /*!< 0x00000010 */ +#define IAC_IERx_IAIE4 IAC_IERx_IAIE4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_IERx_IAIE5_Pos (5UL) +#define IAC_IERx_IAIE5_Msk (0x1UL << IAC_IERx_IAIE5_Pos) /*!< 0x00000020 */ +#define IAC_IERx_IAIE5 IAC_IERx_IAIE5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_IERx_IAIE6_Pos (6UL) +#define IAC_IERx_IAIE6_Msk (0x1UL << IAC_IERx_IAIE6_Pos) /*!< 0x00000040 */ +#define IAC_IERx_IAIE6 IAC_IERx_IAIE6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_IERx_IAIE7_Pos (7UL) +#define IAC_IERx_IAIE7_Msk (0x1UL << IAC_IERx_IAIE7_Pos) /*!< 0x00000080 */ +#define IAC_IERx_IAIE7 IAC_IERx_IAIE7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_IERx_IAIE8_Pos (8UL) +#define IAC_IERx_IAIE8_Msk (0x1UL << IAC_IERx_IAIE8_Pos) /*!< 0x00000100 */ +#define IAC_IERx_IAIE8 IAC_IERx_IAIE8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_IERx_IAIE9_Pos (9UL) +#define IAC_IERx_IAIE9_Msk (0x1UL << IAC_IERx_IAIE9_Pos) /*!< 0x00000200 */ +#define IAC_IERx_IAIE9 IAC_IERx_IAIE9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_IERx_IAIE10_Pos (10UL) +#define IAC_IERx_IAIE10_Msk (0x1UL << IAC_IERx_IAIE10_Pos) /*!< 0x00000400 */ +#define IAC_IERx_IAIE10 IAC_IERx_IAIE10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_IERx_IAIE11_Pos (11UL) +#define IAC_IERx_IAIE11_Msk (0x1UL << IAC_IERx_IAIE11_Pos) /*!< 0x00000800 */ +#define IAC_IERx_IAIE11 IAC_IERx_IAIE11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_IERx_IAIE12_Pos (12UL) +#define IAC_IERx_IAIE12_Msk (0x1UL << IAC_IERx_IAIE12_Pos) /*!< 0x00001000 */ +#define IAC_IERx_IAIE12 IAC_IERx_IAIE12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_IERx_IAIE13_Pos (13UL) +#define IAC_IERx_IAIE13_Msk (0x1UL << IAC_IERx_IAIE13_Pos) /*!< 0x00002000 */ +#define IAC_IERx_IAIE13 IAC_IERx_IAIE13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_IERx_IAIE14_Pos (14UL) +#define IAC_IERx_IAIE14_Msk (0x1UL << IAC_IERx_IAIE14_Pos) /*!< 0x00004000 */ +#define IAC_IERx_IAIE14 IAC_IERx_IAIE14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_IERx_IAIE15_Pos (15UL) +#define IAC_IERx_IAIE15_Msk (0x1UL << IAC_IERx_IAIE15_Pos) /*!< 0x00008000 */ +#define IAC_IERx_IAIE15 IAC_IERx_IAIE15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_IERx_IAIE16_Pos (16UL) +#define IAC_IERx_IAIE16_Msk (0x1UL << IAC_IERx_IAIE16_Pos) /*!< 0x00010000 */ +#define IAC_IERx_IAIE16 IAC_IERx_IAIE16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_IERx_IAIE17_Pos (17UL) +#define IAC_IERx_IAIE17_Msk (0x1UL << IAC_IERx_IAIE17_Pos) /*!< 0x00020000 */ +#define IAC_IERx_IAIE17 IAC_IERx_IAIE17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_IERx_IAIE18_Pos (18UL) +#define IAC_IERx_IAIE18_Msk (0x1UL << IAC_IERx_IAIE18_Pos) /*!< 0x00040000 */ +#define IAC_IERx_IAIE18 IAC_IERx_IAIE18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_IERx_IAIE19_Pos (19UL) +#define IAC_IERx_IAIE19_Msk (0x1UL << IAC_IERx_IAIE19_Pos) /*!< 0x00080000 */ +#define IAC_IERx_IAIE19 IAC_IERx_IAIE19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_IERx_IAIE20_Pos (20UL) +#define IAC_IERx_IAIE20_Msk (0x1UL << IAC_IERx_IAIE20_Pos) /*!< 0x00100000 */ +#define IAC_IERx_IAIE20 IAC_IERx_IAIE20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_IERx_IAIE21_Pos (21UL) +#define IAC_IERx_IAIE21_Msk (0x1UL << IAC_IERx_IAIE21_Pos) /*!< 0x00200000 */ +#define IAC_IERx_IAIE21 IAC_IERx_IAIE21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_IERx_IAIE22_Pos (22UL) +#define IAC_IERx_IAIE22_Msk (0x1UL << IAC_IERx_IAIE22_Pos) /*!< 0x00400000 */ +#define IAC_IERx_IAIE22 IAC_IERx_IAIE22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_IERx_IAIE23_Pos (23UL) +#define IAC_IERx_IAIE23_Msk (0x1UL << IAC_IERx_IAIE23_Pos) /*!< 0x00800000 */ +#define IAC_IERx_IAIE23 IAC_IERx_IAIE23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_IERx_IAIE24_Pos (24UL) +#define IAC_IERx_IAIE24_Msk (0x1UL << IAC_IERx_IAIE24_Pos) /*!< 0x01000000 */ +#define IAC_IERx_IAIE24 IAC_IERx_IAIE24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_IERx_IAIE25_Pos (25UL) +#define IAC_IERx_IAIE25_Msk (0x1UL << IAC_IERx_IAIE25_Pos) /*!< 0x02000000 */ +#define IAC_IERx_IAIE25 IAC_IERx_IAIE25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_IERx_IAIE26_Pos (26UL) +#define IAC_IERx_IAIE26_Msk (0x1UL << IAC_IERx_IAIE26_Pos) /*!< 0x04000000 */ +#define IAC_IERx_IAIE26 IAC_IERx_IAIE26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_IERx_IAIE27_Pos (27UL) +#define IAC_IERx_IAIE27_Msk (0x1UL << IAC_IERx_IAIE27_Pos) /*!< 0x08000000 */ +#define IAC_IERx_IAIE27 IAC_IERx_IAIE27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_IERx_IAIE28_Pos (28UL) +#define IAC_IERx_IAIE28_Msk (0x1UL << IAC_IERx_IAIE28_Pos) /*!< 0x10000000 */ +#define IAC_IERx_IAIE28 IAC_IERx_IAIE28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_IERx_IAIE29_Pos (29UL) +#define IAC_IERx_IAIE29_Msk (0x1UL << IAC_IERx_IAIE29_Pos) /*!< 0x20000000 */ +#define IAC_IERx_IAIE29 IAC_IERx_IAIE29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_IERx_IAIE30_Pos (30UL) +#define IAC_IERx_IAIE30_Msk (0x1UL << IAC_IERx_IAIE30_Pos) /*!< 0x40000000 */ +#define IAC_IERx_IAIE30 IAC_IERx_IAIE30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_IERx_IAIE31_Pos (31UL) +#define IAC_IERx_IAIE31_Msk (0x1UL << IAC_IERx_IAIE31_Pos) /*!< 0x80000000 */ +#define IAC_IERx_IAIE31 IAC_IERx_IAIE31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ISRx register *******************/ +#define IAC_ISRx_IAF0_Pos (0UL) +#define IAC_ISRx_IAF0_Msk (0x1UL << IAC_ISRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ISRx_IAF0 IAC_ISRx_IAF0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */ +#define IAC_ISRx_IAF1_Pos (1UL) +#define IAC_ISRx_IAF1_Msk (0x1UL << IAC_ISRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ISRx_IAF1 IAC_ISRx_IAF1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */ +#define IAC_ISRx_IAF2_Pos (2UL) +#define IAC_ISRx_IAF2_Msk (0x1UL << IAC_ISRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ISRx_IAF2 IAC_ISRx_IAF2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */ +#define IAC_ISRx_IAF3_Pos (3UL) +#define IAC_ISRx_IAF3_Msk (0x1UL << IAC_ISRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ISRx_IAF3 IAC_ISRx_IAF3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */ +#define IAC_ISRx_IAF4_Pos (4UL) +#define IAC_ISRx_IAF4_Msk (0x1UL << IAC_ISRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ISRx_IAF4 IAC_ISRx_IAF4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */ +#define IAC_ISRx_IAF5_Pos (5UL) +#define IAC_ISRx_IAF5_Msk (0x1UL << IAC_ISRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ISRx_IAF5 IAC_ISRx_IAF5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */ +#define IAC_ISRx_IAF6_Pos (6UL) +#define IAC_ISRx_IAF6_Msk (0x1UL << IAC_ISRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ISRx_IAF6 IAC_ISRx_IAF6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */ +#define IAC_ISRx_IAF7_Pos (7UL) +#define IAC_ISRx_IAF7_Msk (0x1UL << IAC_ISRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ISRx_IAF7 IAC_ISRx_IAF7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */ +#define IAC_ISRx_IAF8_Pos (8UL) +#define IAC_ISRx_IAF8_Msk (0x1UL << IAC_ISRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ISRx_IAF8 IAC_ISRx_IAF8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */ +#define IAC_ISRx_IAF9_Pos (9UL) +#define IAC_ISRx_IAF9_Msk (0x1UL << IAC_ISRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ISRx_IAF9 IAC_ISRx_IAF9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */ +#define IAC_ISRx_IAF10_Pos (10UL) +#define IAC_ISRx_IAF10_Msk (0x1UL << IAC_ISRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ISRx_IAF10 IAC_ISRx_IAF10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */ +#define IAC_ISRx_IAF11_Pos (11UL) +#define IAC_ISRx_IAF11_Msk (0x1UL << IAC_ISRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ISRx_IAF11 IAC_ISRx_IAF11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */ +#define IAC_ISRx_IAF12_Pos (12UL) +#define IAC_ISRx_IAF12_Msk (0x1UL << IAC_ISRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ISRx_IAF12 IAC_ISRx_IAF12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */ +#define IAC_ISRx_IAF13_Pos (13UL) +#define IAC_ISRx_IAF13_Msk (0x1UL << IAC_ISRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ISRx_IAF13 IAC_ISRx_IAF13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */ +#define IAC_ISRx_IAF14_Pos (14UL) +#define IAC_ISRx_IAF14_Msk (0x1UL << IAC_ISRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ISRx_IAF14 IAC_ISRx_IAF14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */ +#define IAC_ISRx_IAF15_Pos (15UL) +#define IAC_ISRx_IAF15_Msk (0x1UL << IAC_ISRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ISRx_IAF15 IAC_ISRx_IAF15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */ +#define IAC_ISRx_IAF16_Pos (16UL) +#define IAC_ISRx_IAF16_Msk (0x1UL << IAC_ISRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ISRx_IAF16 IAC_ISRx_IAF16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */ +#define IAC_ISRx_IAF17_Pos (17UL) +#define IAC_ISRx_IAF17_Msk (0x1UL << IAC_ISRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ISRx_IAF17 IAC_ISRx_IAF17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */ +#define IAC_ISRx_IAF18_Pos (18UL) +#define IAC_ISRx_IAF18_Msk (0x1UL << IAC_ISRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ISRx_IAF18 IAC_ISRx_IAF18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */ +#define IAC_ISRx_IAF19_Pos (19UL) +#define IAC_ISRx_IAF19_Msk (0x1UL << IAC_ISRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ISRx_IAF19 IAC_ISRx_IAF19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */ +#define IAC_ISRx_IAF20_Pos (20UL) +#define IAC_ISRx_IAF20_Msk (0x1UL << IAC_ISRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ISRx_IAF20 IAC_ISRx_IAF20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */ +#define IAC_ISRx_IAF21_Pos (21UL) +#define IAC_ISRx_IAF21_Msk (0x1UL << IAC_ISRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ISRx_IAF21 IAC_ISRx_IAF21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */ +#define IAC_ISRx_IAF22_Pos (22UL) +#define IAC_ISRx_IAF22_Msk (0x1UL << IAC_ISRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ISRx_IAF22 IAC_ISRx_IAF22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */ +#define IAC_ISRx_IAF23_Pos (23UL) +#define IAC_ISRx_IAF23_Msk (0x1UL << IAC_ISRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ISRx_IAF23 IAC_ISRx_IAF23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */ +#define IAC_ISRx_IAF24_Pos (24UL) +#define IAC_ISRx_IAF24_Msk (0x1UL << IAC_ISRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ISRx_IAF24 IAC_ISRx_IAF24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */ +#define IAC_ISRx_IAF25_Pos (25UL) +#define IAC_ISRx_IAF25_Msk (0x1UL << IAC_ISRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ISRx_IAF25 IAC_ISRx_IAF25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */ +#define IAC_ISRx_IAF26_Pos (26UL) +#define IAC_ISRx_IAF26_Msk (0x1UL << IAC_ISRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ISRx_IAF26 IAC_ISRx_IAF26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */ +#define IAC_ISRx_IAF27_Pos (27UL) +#define IAC_ISRx_IAF27_Msk (0x1UL << IAC_ISRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ISRx_IAF27 IAC_ISRx_IAF27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */ +#define IAC_ISRx_IAF28_Pos (28UL) +#define IAC_ISRx_IAF28_Msk (0x1UL << IAC_ISRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ISRx_IAF28 IAC_ISRx_IAF28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */ +#define IAC_ISRx_IAF29_Pos (29UL) +#define IAC_ISRx_IAF29_Msk (0x1UL << IAC_ISRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ISRx_IAF29 IAC_ISRx_IAF29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */ +#define IAC_ISRx_IAF30_Pos (30UL) +#define IAC_ISRx_IAF30_Msk (0x1UL << IAC_ISRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ISRx_IAF30 IAC_ISRx_IAF30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */ +#define IAC_ISRx_IAF31_Pos (31UL) +#define IAC_ISRx_IAF31_Msk (0x1UL << IAC_ISRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ISRx_IAF31 IAC_ISRx_IAF31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */ + +/******************* Bit definition for IAC_ICRx register *******************/ +#define IAC_ICRx_IAF0_Pos (0UL) +#define IAC_ICRx_IAF0_Msk (0x1UL << IAC_ICRx_IAF0_Pos) /*!< 0x00000001 */ +#define IAC_ICRx_IAF0 IAC_ICRx_IAF0_Msk /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */ +#define IAC_ICRx_IAF1_Pos (1UL) +#define IAC_ICRx_IAF1_Msk (0x1UL << IAC_ICRx_IAF1_Pos) /*!< 0x00000002 */ +#define IAC_ICRx_IAF1 IAC_ICRx_IAF1_Msk /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */ +#define IAC_ICRx_IAF2_Pos (2UL) +#define IAC_ICRx_IAF2_Msk (0x1UL << IAC_ICRx_IAF2_Pos) /*!< 0x00000004 */ +#define IAC_ICRx_IAF2 IAC_ICRx_IAF2_Msk /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */ +#define IAC_ICRx_IAF3_Pos (3UL) +#define IAC_ICRx_IAF3_Msk (0x1UL << IAC_ICRx_IAF3_Pos) /*!< 0x00000008 */ +#define IAC_ICRx_IAF3 IAC_ICRx_IAF3_Msk /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */ +#define IAC_ICRx_IAF4_Pos (4UL) +#define IAC_ICRx_IAF4_Msk (0x1UL << IAC_ICRx_IAF4_Pos) /*!< 0x00000010 */ +#define IAC_ICRx_IAF4 IAC_ICRx_IAF4_Msk /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */ +#define IAC_ICRx_IAF5_Pos (5UL) +#define IAC_ICRx_IAF5_Msk (0x1UL << IAC_ICRx_IAF5_Pos) /*!< 0x00000020 */ +#define IAC_ICRx_IAF5 IAC_ICRx_IAF5_Msk /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */ +#define IAC_ICRx_IAF6_Pos (6UL) +#define IAC_ICRx_IAF6_Msk (0x1UL << IAC_ICRx_IAF6_Pos) /*!< 0x00000040 */ +#define IAC_ICRx_IAF6 IAC_ICRx_IAF6_Msk /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */ +#define IAC_ICRx_IAF7_Pos (7UL) +#define IAC_ICRx_IAF7_Msk (0x1UL << IAC_ICRx_IAF7_Pos) /*!< 0x00000080 */ +#define IAC_ICRx_IAF7 IAC_ICRx_IAF7_Msk /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */ +#define IAC_ICRx_IAF8_Pos (8UL) +#define IAC_ICRx_IAF8_Msk (0x1UL << IAC_ICRx_IAF8_Pos) /*!< 0x00000100 */ +#define IAC_ICRx_IAF8 IAC_ICRx_IAF8_Msk /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */ +#define IAC_ICRx_IAF9_Pos (9UL) +#define IAC_ICRx_IAF9_Msk (0x1UL << IAC_ICRx_IAF9_Pos) /*!< 0x00000200 */ +#define IAC_ICRx_IAF9 IAC_ICRx_IAF9_Msk /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */ +#define IAC_ICRx_IAF10_Pos (10UL) +#define IAC_ICRx_IAF10_Msk (0x1UL << IAC_ICRx_IAF10_Pos) /*!< 0x00000400 */ +#define IAC_ICRx_IAF10 IAC_ICRx_IAF10_Msk /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */ +#define IAC_ICRx_IAF11_Pos (11UL) +#define IAC_ICRx_IAF11_Msk (0x1UL << IAC_ICRx_IAF11_Pos) /*!< 0x00000800 */ +#define IAC_ICRx_IAF11 IAC_ICRx_IAF11_Msk /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */ +#define IAC_ICRx_IAF12_Pos (12UL) +#define IAC_ICRx_IAF12_Msk (0x1UL << IAC_ICRx_IAF12_Pos) /*!< 0x00001000 */ +#define IAC_ICRx_IAF12 IAC_ICRx_IAF12_Msk /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */ +#define IAC_ICRx_IAF13_Pos (13UL) +#define IAC_ICRx_IAF13_Msk (0x1UL << IAC_ICRx_IAF13_Pos) /*!< 0x00002000 */ +#define IAC_ICRx_IAF13 IAC_ICRx_IAF13_Msk /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */ +#define IAC_ICRx_IAF14_Pos (14UL) +#define IAC_ICRx_IAF14_Msk (0x1UL << IAC_ICRx_IAF14_Pos) /*!< 0x00004000 */ +#define IAC_ICRx_IAF14 IAC_ICRx_IAF14_Msk /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */ +#define IAC_ICRx_IAF15_Pos (15UL) +#define IAC_ICRx_IAF15_Msk (0x1UL << IAC_ICRx_IAF15_Pos) /*!< 0x00008000 */ +#define IAC_ICRx_IAF15 IAC_ICRx_IAF15_Msk /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */ +#define IAC_ICRx_IAF16_Pos (16UL) +#define IAC_ICRx_IAF16_Msk (0x1UL << IAC_ICRx_IAF16_Pos) /*!< 0x00010000 */ +#define IAC_ICRx_IAF16 IAC_ICRx_IAF16_Msk /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */ +#define IAC_ICRx_IAF17_Pos (17UL) +#define IAC_ICRx_IAF17_Msk (0x1UL << IAC_ICRx_IAF17_Pos) /*!< 0x00020000 */ +#define IAC_ICRx_IAF17 IAC_ICRx_IAF17_Msk /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */ +#define IAC_ICRx_IAF18_Pos (18UL) +#define IAC_ICRx_IAF18_Msk (0x1UL << IAC_ICRx_IAF18_Pos) /*!< 0x00040000 */ +#define IAC_ICRx_IAF18 IAC_ICRx_IAF18_Msk /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */ +#define IAC_ICRx_IAF19_Pos (19UL) +#define IAC_ICRx_IAF19_Msk (0x1UL << IAC_ICRx_IAF19_Pos) /*!< 0x00080000 */ +#define IAC_ICRx_IAF19 IAC_ICRx_IAF19_Msk /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */ +#define IAC_ICRx_IAF20_Pos (20UL) +#define IAC_ICRx_IAF20_Msk (0x1UL << IAC_ICRx_IAF20_Pos) /*!< 0x00100000 */ +#define IAC_ICRx_IAF20 IAC_ICRx_IAF20_Msk /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */ +#define IAC_ICRx_IAF21_Pos (21UL) +#define IAC_ICRx_IAF21_Msk (0x1UL << IAC_ICRx_IAF21_Pos) /*!< 0x00200000 */ +#define IAC_ICRx_IAF21 IAC_ICRx_IAF21_Msk /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */ +#define IAC_ICRx_IAF22_Pos (22UL) +#define IAC_ICRx_IAF22_Msk (0x1UL << IAC_ICRx_IAF22_Pos) /*!< 0x00400000 */ +#define IAC_ICRx_IAF22 IAC_ICRx_IAF22_Msk /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */ +#define IAC_ICRx_IAF23_Pos (23UL) +#define IAC_ICRx_IAF23_Msk (0x1UL << IAC_ICRx_IAF23_Pos) /*!< 0x00800000 */ +#define IAC_ICRx_IAF23 IAC_ICRx_IAF23_Msk /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */ +#define IAC_ICRx_IAF24_Pos (24UL) +#define IAC_ICRx_IAF24_Msk (0x1UL << IAC_ICRx_IAF24_Pos) /*!< 0x01000000 */ +#define IAC_ICRx_IAF24 IAC_ICRx_IAF24_Msk /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */ +#define IAC_ICRx_IAF25_Pos (25UL) +#define IAC_ICRx_IAF25_Msk (0x1UL << IAC_ICRx_IAF25_Pos) /*!< 0x02000000 */ +#define IAC_ICRx_IAF25 IAC_ICRx_IAF25_Msk /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */ +#define IAC_ICRx_IAF26_Pos (26UL) +#define IAC_ICRx_IAF26_Msk (0x1UL << IAC_ICRx_IAF26_Pos) /*!< 0x04000000 */ +#define IAC_ICRx_IAF26 IAC_ICRx_IAF26_Msk /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */ +#define IAC_ICRx_IAF27_Pos (27UL) +#define IAC_ICRx_IAF27_Msk (0x1UL << IAC_ICRx_IAF27_Pos) /*!< 0x08000000 */ +#define IAC_ICRx_IAF27 IAC_ICRx_IAF27_Msk /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */ +#define IAC_ICRx_IAF28_Pos (28UL) +#define IAC_ICRx_IAF28_Msk (0x1UL << IAC_ICRx_IAF28_Pos) /*!< 0x10000000 */ +#define IAC_ICRx_IAF28 IAC_ICRx_IAF28_Msk /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */ +#define IAC_ICRx_IAF29_Pos (29UL) +#define IAC_ICRx_IAF29_Msk (0x1UL << IAC_ICRx_IAF29_Pos) /*!< 0x20000000 */ +#define IAC_ICRx_IAF29 IAC_ICRx_IAF29_Msk /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */ +#define IAC_ICRx_IAF30_Pos (30UL) +#define IAC_ICRx_IAF30_Msk (0x1UL << IAC_ICRx_IAF30_Pos) /*!< 0x40000000 */ +#define IAC_ICRx_IAF30 IAC_ICRx_IAF30_Msk /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */ +#define IAC_ICRx_IAF31_Pos (31UL) +#define IAC_ICRx_IAF31_Msk (0x1UL << IAC_ICRx_IAF31_Pos) /*!< 0x80000000 */ +#define IAC_ICRx_IAF31 IAC_ICRx_IAF31_Msk /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */ + +/****************** Bit definition for IAC_IISRx register *******************/ +#define IAC_IISRx_ILACIN0_Pos (0UL) +#define IAC_IISRx_ILACIN0_Msk (0x1UL << IAC_IISRx_ILACIN0_Pos) /*!< 0x00000001 */ +#define IAC_IISRx_ILACIN0 IAC_IISRx_ILACIN0_Msk /*!< illegal access input 0 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN1_Pos (1UL) +#define IAC_IISRx_ILACIN1_Msk (0x1UL << IAC_IISRx_ILACIN1_Pos) /*!< 0x00000002 */ +#define IAC_IISRx_ILACIN1 IAC_IISRx_ILACIN1_Msk /*!< illegal access input 1 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN2_Pos (2UL) +#define IAC_IISRx_ILACIN2_Msk (0x1UL << IAC_IISRx_ILACIN2_Pos) /*!< 0x00000004 */ +#define IAC_IISRx_ILACIN2 IAC_IISRx_ILACIN2_Msk /*!< illegal access input 2 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN3_Pos (3UL) +#define IAC_IISRx_ILACIN3_Msk (0x1UL << IAC_IISRx_ILACIN3_Pos) /*!< 0x00000008 */ +#define IAC_IISRx_ILACIN3 IAC_IISRx_ILACIN3_Msk /*!< illegal access input 3 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN4_Pos (4UL) +#define IAC_IISRx_ILACIN4_Msk (0x1UL << IAC_IISRx_ILACIN4_Pos) /*!< 0x00000010 */ +#define IAC_IISRx_ILACIN4 IAC_IISRx_ILACIN4_Msk /*!< illegal access input 4 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN5_Pos (5UL) +#define IAC_IISRx_ILACIN5_Msk (0x1UL << IAC_IISRx_ILACIN5_Pos) /*!< 0x00000020 */ +#define IAC_IISRx_ILACIN5 IAC_IISRx_ILACIN5_Msk /*!< illegal access input 5 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN6_Pos (6UL) +#define IAC_IISRx_ILACIN6_Msk (0x1UL << IAC_IISRx_ILACIN6_Pos) /*!< 0x00000040 */ +#define IAC_IISRx_ILACIN6 IAC_IISRx_ILACIN6_Msk /*!< illegal access input 6 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN7_Pos (7UL) +#define IAC_IISRx_ILACIN7_Msk (0x1UL << IAC_IISRx_ILACIN7_Pos) /*!< 0x00000080 */ +#define IAC_IISRx_ILACIN7 IAC_IISRx_ILACIN7_Msk /*!< illegal access input 7 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN8_Pos (8UL) +#define IAC_IISRx_ILACIN8_Msk (0x1UL << IAC_IISRx_ILACIN8_Pos) /*!< 0x00000100 */ +#define IAC_IISRx_ILACIN8 IAC_IISRx_ILACIN8_Msk /*!< illegal access input 8 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN9_Pos (9UL) +#define IAC_IISRx_ILACIN9_Msk (0x1UL << IAC_IISRx_ILACIN9_Pos) /*!< 0x00000200 */ +#define IAC_IISRx_ILACIN9 IAC_IISRx_ILACIN9_Msk /*!< illegal access input 9 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN10_Pos (10UL) +#define IAC_IISRx_ILACIN10_Msk (0x1UL << IAC_IISRx_ILACIN10_Pos) /*!< 0x00000400 */ +#define IAC_IISRx_ILACIN10 IAC_IISRx_ILACIN10_Msk /*!< illegal access input 10 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN11_Pos (11UL) +#define IAC_IISRx_ILACIN11_Msk (0x1UL << IAC_IISRx_ILACIN11_Pos) /*!< 0x00000800 */ +#define IAC_IISRx_ILACIN11 IAC_IISRx_ILACIN11_Msk /*!< illegal access input 11 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN12_Pos (12UL) +#define IAC_IISRx_ILACIN12_Msk (0x1UL << IAC_IISRx_ILACIN12_Pos) /*!< 0x00001000 */ +#define IAC_IISRx_ILACIN12 IAC_IISRx_ILACIN12_Msk /*!< illegal access input 12 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN13_Pos (13UL) +#define IAC_IISRx_ILACIN13_Msk (0x1UL << IAC_IISRx_ILACIN13_Pos) /*!< 0x00002000 */ +#define IAC_IISRx_ILACIN13 IAC_IISRx_ILACIN13_Msk /*!< illegal access input 13 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN14_Pos (14UL) +#define IAC_IISRx_ILACIN14_Msk (0x1UL << IAC_IISRx_ILACIN14_Pos) /*!< 0x00004000 */ +#define IAC_IISRx_ILACIN14 IAC_IISRx_ILACIN14_Msk /*!< illegal access input 14 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN15_Pos (15UL) +#define IAC_IISRx_ILACIN15_Msk (0x1UL << IAC_IISRx_ILACIN15_Pos) /*!< 0x00008000 */ +#define IAC_IISRx_ILACIN15 IAC_IISRx_ILACIN15_Msk /*!< illegal access input 15 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN16_Pos (16UL) +#define IAC_IISRx_ILACIN16_Msk (0x1UL << IAC_IISRx_ILACIN16_Pos) /*!< 0x00010000 */ +#define IAC_IISRx_ILACIN16 IAC_IISRx_ILACIN16_Msk /*!< illegal access input 16 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN17_Pos (17UL) +#define IAC_IISRx_ILACIN17_Msk (0x1UL << IAC_IISRx_ILACIN17_Pos) /*!< 0x00020000 */ +#define IAC_IISRx_ILACIN17 IAC_IISRx_ILACIN17_Msk /*!< illegal access input 17 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN18_Pos (18UL) +#define IAC_IISRx_ILACIN18_Msk (0x1UL << IAC_IISRx_ILACIN18_Pos) /*!< 0x00040000 */ +#define IAC_IISRx_ILACIN18 IAC_IISRx_ILACIN18_Msk /*!< illegal access input 18 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN19_Pos (19UL) +#define IAC_IISRx_ILACIN19_Msk (0x1UL << IAC_IISRx_ILACIN19_Pos) /*!< 0x00080000 */ +#define IAC_IISRx_ILACIN19 IAC_IISRx_ILACIN19_Msk /*!< illegal access input 19 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN20_Pos (20UL) +#define IAC_IISRx_ILACIN20_Msk (0x1UL << IAC_IISRx_ILACIN20_Pos) /*!< 0x00100000 */ +#define IAC_IISRx_ILACIN20 IAC_IISRx_ILACIN20_Msk /*!< illegal access input 20 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN21_Pos (21UL) +#define IAC_IISRx_ILACIN21_Msk (0x1UL << IAC_IISRx_ILACIN21_Pos) /*!< 0x00200000 */ +#define IAC_IISRx_ILACIN21 IAC_IISRx_ILACIN21_Msk /*!< illegal access input 21 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN22_Pos (22UL) +#define IAC_IISRx_ILACIN22_Msk (0x1UL << IAC_IISRx_ILACIN22_Pos) /*!< 0x00400000 */ +#define IAC_IISRx_ILACIN22 IAC_IISRx_ILACIN22_Msk /*!< illegal access input 22 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN23_Pos (23UL) +#define IAC_IISRx_ILACIN23_Msk (0x1UL << IAC_IISRx_ILACIN23_Pos) /*!< 0x00800000 */ +#define IAC_IISRx_ILACIN23 IAC_IISRx_ILACIN23_Msk /*!< illegal access input 23 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN24_Pos (24UL) +#define IAC_IISRx_ILACIN24_Msk (0x1UL << IAC_IISRx_ILACIN24_Pos) /*!< 0x01000000 */ +#define IAC_IISRx_ILACIN24 IAC_IISRx_ILACIN24_Msk /*!< illegal access input 24 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN25_Pos (25UL) +#define IAC_IISRx_ILACIN25_Msk (0x1UL << IAC_IISRx_ILACIN25_Pos) /*!< 0x02000000 */ +#define IAC_IISRx_ILACIN25 IAC_IISRx_ILACIN25_Msk /*!< illegal access input 25 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN26_Pos (26UL) +#define IAC_IISRx_ILACIN26_Msk (0x1UL << IAC_IISRx_ILACIN26_Pos) /*!< 0x04000000 */ +#define IAC_IISRx_ILACIN26 IAC_IISRx_ILACIN26_Msk /*!< illegal access input 26 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN27_Pos (27UL) +#define IAC_IISRx_ILACIN27_Msk (0x1UL << IAC_IISRx_ILACIN27_Pos) /*!< 0x08000000 */ +#define IAC_IISRx_ILACIN27 IAC_IISRx_ILACIN27_Msk /*!< illegal access input 27 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN28_Pos (28UL) +#define IAC_IISRx_ILACIN28_Msk (0x1UL << IAC_IISRx_ILACIN28_Pos) /*!< 0x10000000 */ +#define IAC_IISRx_ILACIN28 IAC_IISRx_ILACIN28_Msk /*!< illegal access input 28 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN29_Pos (29UL) +#define IAC_IISRx_ILACIN29_Msk (0x1UL << IAC_IISRx_ILACIN29_Pos) /*!< 0x20000000 */ +#define IAC_IISRx_ILACIN29 IAC_IISRx_ILACIN29_Msk /*!< illegal access input 29 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN30_Pos (30UL) +#define IAC_IISRx_ILACIN30_Msk (0x1UL << IAC_IISRx_ILACIN30_Pos) /*!< 0x40000000 */ +#define IAC_IISRx_ILACIN30 IAC_IISRx_ILACIN30_Msk /*!< illegal access input 30 (i = 0 to 31) */ +#define IAC_IISRx_ILACIN31_Pos (31UL) +#define IAC_IISRx_ILACIN31_Msk (0x1UL << IAC_IISRx_ILACIN31_Pos) /*!< 0x80000000 */ +#define IAC_IISRx_ILACIN31 IAC_IISRx_ILACIN31_Msk /*!< illegal access input 31 (i = 0 to 31) */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0UL) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4UL) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8UL) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12UL) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16UL) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20UL) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22UL) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0UL) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4UL) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8UL) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12UL) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13UL) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16UL) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20UL) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0UL) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2UL) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3UL) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4UL) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5UL) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6UL) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7UL) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8UL) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10UL) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16UL) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0UL) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16UL) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0UL) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16UL) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0UL) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3UL) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4UL) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5UL) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6UL) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7UL) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8UL) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9UL) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10UL) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11UL) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12UL) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13UL) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14UL) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15UL) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16UL) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17UL) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18UL) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19UL) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20UL) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21UL) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23UL) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24UL) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Secure Advanced Encryption Standard (SAES) */ +/* */ +/******************************************************************************/ +/******************* Bits definition for SAES_CR register *********************/ +#define SAES_CR_EN_Pos (0UL) +#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ +#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ +#define SAES_CR_DATATYPE_Pos (1UL) +#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ +#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define SAES_CR_MODE_Pos (3UL) +#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ +#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ +#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ +#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ +#define SAES_CR_CHMOD_Pos (5UL) +#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ +#define SAES_CR_CHMOD_0 (0x1UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020*/ +#define SAES_CR_CHMOD_1 (0x2UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define SAES_CR_DMAINEN_Pos (11UL) +#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define SAES_CR_DMAOUTEN_Pos (12UL) +#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define SAES_CR_GCMPH_Pos (13UL) +#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x0006000 */ +#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM or CCM phase selection */ +#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00020000 */ +#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE_Pos (18UL) +#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define SAES_CR_KEYPROT_Pos (19UL) +#define SAES_CR_KEYPROT_Msk (0x1UL << SAES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define SAES_CR_KEYPROT SAES_CR_KEYPROT_Msk /*!< Key protection */ +#define SAES_CR_NPBLB_Pos (20UL) +#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in last block */ +#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define SAES_CR_KMOD_Pos (24UL) +#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ +#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define SAES_CR_KSHAREID_Pos (26UL) +#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define SAES_CR_KSHAREID_0 (0x1UL << SAES_CR_KSHAREID_Pos) /*!< 0x04000000 */ +#define SAES_CR_KSHAREID_1 (0x2UL << SAES_CR_KSHAREID_Pos) /*!< 0x08000000 */ +#define SAES_CR_KEYSEL_Pos (28UL) +#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ +#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define SAES_CR_IPRST_Pos (31UL) +#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ + +/******************* Bits definition for SAES_SR register *********************/ +#define SAES_SR_CCF_Pos (0UL) +#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define SAES_SR_RDERR_Pos (1UL) +#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ +#define SAES_SR_WRERR_Pos (2UL) +#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ +#define SAES_SR_BUSY_Pos (3UL) +#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ +#define SAES_SR_KEYVALID_Pos (7UL) +#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< Key valid Flag */ + +/******************* Bits definition for SAES_DINR register *******************/ +#define SAES_DINR_Pos (0UL) +#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ + +/******************* Bits definition for SAES_DOUTR register ******************/ +#define SAES_DOUTR_Pos (0UL) +#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ + +/******************* Bits definition for SAES_KEYR0 register ******************/ +#define SAES_KEYR0_Pos (0UL) +#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES cryptographic key, bits [31:0] */ + +/******************* Bits definition for SAES_KEYR1 register ******************/ +#define SAES_KEYR1_Pos (0UL) +#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES cryptographic key, bits [63:32] */ + +/******************* Bits definition for SAES_KEYR2 register ******************/ +#define SAES_KEYR2_Pos (0UL) +#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES cryptographic key, bits [95:64] */ + +/******************* Bits definition for SAES_KEYR3 register ******************/ +#define SAES_KEYR3_Pos (0UL) +#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR4 register ******************/ +#define SAES_KEYR4_Pos (0UL) +#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR5 register ******************/ +#define SAES_KEYR5_Pos (0UL) +#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR6 register ******************/ +#define SAES_KEYR6_Pos (0UL) +#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_KEYR7 register ******************/ +#define SAES_KEYR7_Pos (0UL) +#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES cryptographic key, bits [127:96] */ + +/******************* Bits definition for SAES_IVR0 register ******************/ +#define SAES_IVR0_Pos (0UL) +#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES initialization vector input, bits [31:0] */ + +/******************* Bits definition for SAES_IVR1 register ******************/ +#define SAES_IVR1_Pos (0UL) +#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES initialization vector input, bits [63:32] */ + +/******************* Bits definition for SAES_IVR2 register ******************/ +#define SAES_IVR2_Pos (0UL) +#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES initialization vector input, bits [95:64] */ + +/******************* Bits definition for SAES_IVR3 register ******************/ +#define SAES_IVR3_Pos (0UL) +#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES initialization vector input, bits [127:96] */ + +/******************* Bits definition for SAES_DPACFGR register ******************/ +#define SAES_DPACFGR_REDCFG_Pos (0UL) +#define SAES_DPACFGR_REDCFG_Msk (0x3UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000003 */ +#define SAES_DPACFGR_REDCFG SAES_DPACFGR_REDCFG_Msk /*!< Redundancy configuration*/ +#define SAES_DPACFGR_REDCFG_0 (0x1UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000001 */ +#define SAES_DPACFGR_REDCFG_1 (0x2UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000002 */ +#define SAES_DPACFGR_RESEED_Pos (2UL) +#define SAES_DPACFGR_RESEED_Msk (0x1UL << SAES_DPACFGR_RESEED_Pos) /*!< 0x00000004 */ +#define SAES_DPACFGR_RESEED SAES_DPACFGR_RESEED_Msk /*!< Automatic reseed enable */ +#define SAES_DPACFGR_TRIMCFG_Pos (3UL) +#define SAES_DPACFGR_TRIMCFG_Msk (0x3UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000018 */ +#define SAES_DPACFGR_TRIMCFG SAES_DPACFGR_TRIMCFG_Msk /*!< Clock trimming */ +#define SAES_DPACFGR_TRIMCFG_0 (0x1UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000008 */ +#define SAES_DPACFGR_TRIMCFG_1 (0x2UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000010 */ +#define SAES_DPACFGR_CONFIGLOCK_Pos (31UL) +#define SAES_DPACFGR_CONFIGLOCK_Msk (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos) /*!< 0x80000000 */ +#define SAES_DPACFGR_CONFIGLOCK SAES_DPACFGR_CONFIGLOCK_Msk /*!< DPA configuration lock */ + +/******************* Bits definition for SAES_IER register ******************/ +#define SAES_IER_CCFIE_Pos (0UL) +#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define SAES_IER_RWEIE_Pos (1UL) +#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define SAES_IER_KEIE_Pos (2UL) +#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define SAES_IER_RNGEIE_Pos (3UL) +#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< RNG error interrupt enable */ + +/******************* Bits definition for SAES_ISR register ******************/ +#define SAES_ISR_CCF_Pos (0UL) +#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ +#define SAES_ISR_RWEIF_Pos (1UL) +#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define SAES_ISR_KEIF_Pos (2UL) +#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define SAES_ISR_RNGEIF_Pos (3UL) +#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< RNG error interrupt flag */ + +/******************* Bits definition for SAES_ICR register ******************/ +#define SAES_ICR_CCF_Pos (0UL) +#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define SAES_ICR_RWEIF_Pos (1UL) +#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define SAES_ICR_KEIF_Pos (2UL) +#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define SAES_ICR_RNGEIF_Pos (3UL) +#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< RNG error interrupt flag clear */ + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0UL) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Exported_Functions + * @{ + */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + \brief Update SystemCoreClock variable from secure application and return its value + when security is implemented in the system (Non-secure callable function). + + Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. + */ +extern uint32_t SECURE_SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SYSTEM_STM32N6XX_H */ + +/** + * @} + */ + +/** + * @} + */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/LICENSE.txt =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/LICENSE.txt (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Device/ST/STM32N6xx/LICENSE.txt (revision 16) @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_armclang.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_armclang.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_armclang.h (revision 16) @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_armclang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_armclang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_armclang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_ARMCLANG_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_clang.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_clang.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_clang.h (revision 16) @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file cmsis_clang.h + * @brief CMSIS compiler LLVM/Clang header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_H +#define __CMSIS_CLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_clang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_clang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_clang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_CLANG_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_compiler.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_compiler.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_compiler.h (revision 16) @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Compiler Generic Header File + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler above 6.10.1 (armclang) + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + +/* + * TI Arm Clang Compiler (tiarmclang) + */ +#elif defined (__ti__) + #include "cmsis_tiarmclang.h" + + +/* + * LLVM/Clang Compiler + */ +#elif defined ( __clang__ ) + #include "cmsis_clang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler (armcl) + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_gcc.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_gcc.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_gcc.h (revision 16) @@ -0,0 +1,1006 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +#pragma GCC system_header /* treat file as system include file */ + +#include + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return (result); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ + return (int16_t)__builtin_bswap16(value); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__ARM_ARCH_ISA_THUMB >= 2) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if (__ARM_FEATURE_SAT >= 1) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return (result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) + /** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __enable_fault_irq(void) + { + __ASM volatile ("cpsie f" : : : "memory"); + } + + + /** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __disable_fault_irq(void) + { + __ASM volatile ("cpsid f" : : : "memory"); + } +#endif + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __sadd8 + #define __QADD8 __qadd8 + #define __SHADD8 __shadd8 + #define __UADD8 __uadd8 + #define __UQADD8 __uqadd8 + #define __UHADD8 __uhadd8 + #define __SSUB8 __ssub8 + #define __QSUB8 __qsub8 + #define __SHSUB8 __shsub8 + #define __USUB8 __usub8 + #define __UQSUB8 __uqsub8 + #define __UHSUB8 __uhsub8 + #define __SADD16 __sadd16 + #define __QADD16 __qadd16 + #define __SHADD16 __shadd16 + #define __UADD16 __uadd16 + #define __UQADD16 __uqadd16 + #define __UHADD16 __uhadd16 + #define __SSUB16 __ssub16 + #define __QSUB16 __qsub16 + #define __SHSUB16 __shsub16 + #define __USUB16 __usub16 + #define __UQSUB16 __uqsub16 + #define __UHSUB16 __uhsub16 + #define __SASX __sasx + #define __QASX __qasx + #define __SHASX __shasx + #define __UASX __uasx + #define __UQASX __uqasx + #define __UHASX __uhasx + #define __SSAX __ssax + #define __QSAX __qsax + #define __SHSAX __shsax + #define __USAX __usax + #define __UQSAX __uqsax + #define __UHSAX __uhsax + #define __USAD8 __usad8 + #define __USADA8 __usada8 + #define __SSAT16 __ssat16 + #define __USAT16 __usat16 + #define __UXTB16 __uxtb16 + #define __UXTAB16 __uxtab16 + #define __SXTB16 __sxtb16 + #define __SXTAB16 __sxtab16 + #define __SMUAD __smuad + #define __SMUADX __smuadx + #define __SMLAD __smlad + #define __SMLADX __smladx + #define __SMLALD __smlald + #define __SMLALDX __smlaldx + #define __SMUSD __smusd + #define __SMUSDX __smusdx + #define __SMLSD __smlsd + #define __SMLSDX __smlsdx + #define __SMLSLD __smlsld + #define __SMLSLDX __smlsldx + #define __SEL __sel + #define __QADD __qadd + #define __QSUB __qsub + + #define __PKHBT(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + #define __PKHTB(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) + { + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); + } +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_gcc_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_gcc_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_gcc_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_GCC_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_iccarm.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_iccarm.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_iccarm.h (revision 16) @@ -0,0 +1,571 @@ +/* + * Copyright (c) 2017-2024 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(Generic) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_H +#define __CMSIS_ICCARM_H + +#pragma system_include + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __NO_RETURN + #if defined(__cplusplus) && __cplusplus >= 201103L + #define __NO_RETURN [[noreturn]] + #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define __NO_RETURN _Noreturn + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif + +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +#if defined(__CLZ) + #undef __CLZ +#endif +#if defined(__REVSH) + #undef __REVSH +#endif +#if defined(__RBIT) + #undef __RBIT +#endif +#if defined(__SSAT) + #undef __SSAT +#endif +#if defined(__USAT) + #undef __USAT +#endif + +#include "iccarm_builtin.h" + +#define __disable_irq __iar_builtin_disable_interrupt +#define __enable_irq __iar_builtin_enable_interrupt +#define __arm_rsr __iar_builtin_rsr +#define __arm_wsr __iar_builtin_wsr + +#define __NOP __iar_builtin_no_operation +#define __WFI __iar_builtin_WFI +#define __WFE __iar_builtin_WFE +#define __ISB __iar_builtin_ISB +#define __SEV __iar_builtin_SEV +#define __DSB __iar_builtin_DSB +#define __DMB __iar_builtin_DMB +#define __REV __iar_builtin_REV +#define __REV16 __iar_builtin_REV16 +#define __ROR __iar_builtin_ROR +#define __RBIT __iar_builtin_RBIT +#define __CLZ __iar_builtin_CLZ + +__IAR_FT int16_t __REVSH(int16_t val) +{ + return (int16_t) __iar_builtin_REVSH(val); +} + + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if (__ARM_FEATURE_LDREX >= 1) + +/* + * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. + * As a workaround we use inline assembly and a memory barrier. + * (IAR issue EWARM-11901) + * Fixed in EWARM 9.50.i2 + */ + +__IAR_FT void __CLREX() { + __ASM volatile("CLREX" ::: "memory"); +} + + +#define __LDREXB __iar_builtin_LDREXB +#define __STREXB __iar_builtin_STREXB + +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + +#if (__ARM_FEATURE_LDREX >= 2) + +#define __LDREXH __iar_builtin_LDREXH +#define __STREXH __iar_builtin_STREXH + +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + +#if (__ARM_FEATURE_LDREX >= 4) + +#define __LDREXW __iar_builtin_LDREX +#define __STREXW __iar_builtin_STREX + +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __iar_builtin_SSAT + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value +*/ +#define __USAT __iar_builtin_USAT + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + +#if (__ARM_ARCH_ISA_THUMB >= 2) + +#define __RRX __iar_builtin_RRX + +__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); +} + +__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); +} + +__IAR_FT uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=&r" (res) : "r" (addr) : "memory"); + return res; +} + +__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); +} + +__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); +} + +__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); +} +#endif + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + + /* Note, these are suboptimal but I lack compiler features to express this */ + + #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + +#if (defined (__ARM_FP) && (__ARM_FP >= 1)) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) +#else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) +#endif + +#if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) +// This is not really fault_irq on Cortex-not-M. However +// there seems to be code that assumes this. + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } +#endif + +#if (__ARM_ARCH >= 8) + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH >= 8 */ + + #if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_iccarm_a.h" + #elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_iccarm_r.h" + #elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_iccarm_m.h" + #else + #error "Unknown Arm architecture profile" + #endif + + +#endif Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_version.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_version.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/cmsis_version.h (revision 16) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core Version Definitions + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS-Core(M) Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ + +/* CMSIS-Core(A) Version definitions */ +#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#endif Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm0.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm0.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm0.h (revision 16) @@ -0,0 +1,967 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M0 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/* NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm0plus.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm0plus.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm0plus.h (revision 16) @@ -0,0 +1,1103 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/* NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm1.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm1.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm1.h (revision 16) @@ -0,0 +1,992 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M1 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm23.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm23.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm23.h (revision 16) @@ -0,0 +1,2253 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M23 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM23 definitions */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED14[992U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_DWTENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/* NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/* NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm3.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm3.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm3.h (revision 16) @@ -0,0 +1,2045 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M3 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm33.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm33.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm33.h (revision 16) @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be written. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be written + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm35p.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm35p.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm35p.h (revision 16) @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M35P Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35 definitions */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm4.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm4.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm4.h (revision 16) @@ -0,0 +1,2237 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M4 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm52.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm52.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm52.h (revision 16) @@ -0,0 +1,4783 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. Copyright (c) 2024 Arm Technology (China) Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M52 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM52_H_GENERIC +#define __CORE_CM52_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M52 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM52 definitions */ + +#define __CORTEX_M (52U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM52_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM52_H_DEPENDANT +#define __CORE_CM52_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM52_REV + #define __CM52_REV 0x0002U + #warning "__CM52_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __UCACHE_PRESENT + #define __UCACHE_PRESENT 0U + #warning "__UCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M52 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED0[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED1[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED2[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED3[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED4[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_CTYPE1_Pos 0U +#define SCB_CLIDR_CTYPE1_Msk (7UL << SCB_CLIDR_CTYPE1_Pos) + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + + +/** \brief SCB U-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_UC_WAY_Pos 31U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_UC_WAY_Msk (1UL << SCB_DCISW_UC_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_UC_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_UC_SET_Msk (0x3FFUL << SCB_DCISW_UC_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB U-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_UC_WAY_Pos 31U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_UC_WAY_Msk (1UL << SCB_DCCSW_UC_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_UC_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_UC_SET_Msk (0x3FFUL << SCB_DCCSW_UC_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB U-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_UC_WAY_Pos 31U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_UC_WAY_Msk (1UL << SCB_DCCISW_UC_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_UC_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_UC_SET_Msk (0x3FFUL << SCB_DCCISW_UC_SET_Pos) /*!< SCB DCCISW: Set Mask */ + + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + uint32_t RESERVED1[3U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup DCAR_Type Direct Cache Access Registers + \brief Type definitions for the Direct Cache Access Registers (DCAR) + @{ + */ + +/** + \brief Structure type to access the Direct Cache Access Registers (DCAR). + */ +typedef struct +{ + __IM uint32_t DCADCRR; /*!< Offset: 0x000 (R/W) Direct Cache Access Data Cache Read Register */ + __IM uint32_t DCAICRR; /*!< Offset: 0x004 (R/W) Direct Cache Access Instruction Cache Read Register */ + uint32_t RESERVED1[2]; + __IOM uint32_t DCADCLR; /*!< Offset: 0x010 (R/W) Direct Cache Access Data Cache Location Registers */ + __IOM uint32_t DCAICLR; /*!< Offset: 0x014 (R/W) Direct Cache Access Instruction Cache Location Registers */ +} DCAR_Type; + +/*@}*/ /* end of group DCAR_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + __IM uint32_t TEBRDATA0; /*!< Offset: 0x024 (RO) Storage for corrected data that is associated with an error.*/ + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ + __IM uint32_t TEBRDATA1; /*!< Offset: 0x02c (RO) Storage for corrected data that is associated with an error.*/ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 27U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 26U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 27U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 26U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLDMPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register */ + +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register Definitions */ +#define STL_STLDMPUOR_HITREGION_Pos 9U /*!< STL STLDMPUOR: HITREGION Position */ +#define STL_STLDMPUOR_HITREGION_Msk (0xFFUL << STL_STLDMPUOR_HITREGION_Pos) /*!< STL STLDMPUOR: HITREGION Mask */ + +#define STL_STLDMPUOR_ATTR_Pos 0U /*!< STL STLDMPUOR: ATTR Position */ +#define STL_STLDMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLDMPUOR_ATTR_Pos*/) /*!< STL STLDMPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define DCAR_BASE (0xE001E200UL) /*!< Direct Cache Access Registers */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define DCAR ((DCAR_Type *) DCAR_BASE ) /*!< Direct Read Access to the embedded RAM associated with the L1 instruction and data cache */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M52 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM52_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM52_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM52_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM52_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM52_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM52_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM52_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM52_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM52_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM52_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM52_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM52_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM52_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM52_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM52_PMU_AXI_SAHB_WRITE_ACCESS 0xC302 /*!< M-AXI configuration: Any beat access to the M-AXI write interface.M-AHB configuration: Any write beat access to the SYS-AHB interface */ +#define ARMCM52_PMU_AXI_SAHB_READ_ACCESS 0xC303 /*!< M-AXI configuration: Any beat access to the M-AXI read interface.M-AHB configuration: Any read beat access to the SYS-AHB interface */ +#define ARMCM52_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM52_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM52_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ +#define ARMCM52_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ +#define ARMCM52_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ +#define ARMCM52_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ +#define ARMCM52_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ +#define ARMCM52_PMU_CAHB_WRITE_ACCESS 0xC420 /*!< M-AHB configuration: A Write beat transfer on Code-AHB */ +#define ARMCM52_PMU_CAHB_READ_ACCESS 0xC421 /*!< M-AHB configuration: A Read beat transfer on Code-AHB. */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "m-profile/armv81m_pac.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM52_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + + + + + Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm55.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm55.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm55.h (revision 16) @@ -0,0 +1,4908 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M55 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Coprocessor Power Control Register Definitions */ +#define ICB_CPPWR_SUS11_Pos 23U /*!< CPPWR: SUS11 Position */ +#define ICB_CPPWR_SUS11_Msk (1UL << ICB_CPPWR_SUS11_Pos) /*!< CPPWR: SUS11 Mask */ + +#define ICB_CPPWR_SU11_Pos 22U /*!< CPPWR: SU11 Position */ +#define ICB_CPPWR_SU11_Msk (1UL << ICB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */ + +#define ICB_CPPWR_SUS10_Pos 21U /*!< CPPWR: SUS10 Position */ +#define ICB_CPPWR_SUS10_Msk (1UL << ICB_CPPWR_SUS10_Pos) /*!< CPPWR: SUS10 Mask */ + +#define ICB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ +#define ICB_CPPWR_SU10_Msk (1UL << ICB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl Prefetcher Control Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 0 Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 1 Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + __OM uint32_t DSCEMCR; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_FPD_Pos DCB_DHCSR_S_FPD_Pos +#define CoreDebug_DHCSR_S_FPD_Msk DCB_DHCSR_S_FPD_Msk + +#define CoreDebug_DHCSR_S_SUIDE_Pos DCB_DHCSR_S_SUIDE_Pos +#define CoreDebug_DHCSR_S_SUIDE_Msk DCB_DHCSR_S_SUIDE_Msk + +#define CoreDebug_DHCSR_S_NSUIDE_Pos DCB_DHCSR_S_NSUIDE_Pos +#define CoreDebug_DHCSR_S_NSUIDE_Msk DCB_DHCSR_S_NSUIDE_Msk + +#define CoreDebug_DHCSR_S_SDE_Pos DCB_DHCSR_S_SDE_Pos +#define CoreDebug_DHCSR_S_SDE_Msk DCB_DHCSR_S_SDE_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_PMOV_Pos DCB_DHCSR_C_PMOV_Pos +#define CoreDebug_DHCSR_C_PMOV_Msk DCB_DHCSR_C_PMOV_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos DCB_DSCEMCR_CLR_MON_REQ_Pos +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk DCB_DSCEMCR_CLR_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos DCB_DSCEMCR_CLR_MON_PEND_Pos +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk DCB_DSCEMCR_CLR_MON_PEND_Msk + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos DCB_DSCEMCR_SET_MON_REQ_Pos +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk DCB_DSCEMCR_SET_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos DCB_DSCEMCR_SET_MON_PEND_Pos +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk DCB_DSCEMCR_SET_MON_PEND_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos DCB_DAUTHCTRL_UIDEN_Pos +#define CoreDebug_DAUTHCTRL_UIDEN_Msk DCB_DAUTHCTRL_UIDEN_Msk + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos DCB_DAUTHCTRL_UIDAPEN_Pos +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk DCB_DAUTHCTRL_UIDAPEN_Msk + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos DCB_DAUTHCTRL_FSDMA_Pos +#define CoreDebug_DAUTHCTRL_FSDMA_Msk DCB_DAUTHCTRL_FSDMA_Msk + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM55_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ +#define ARMCM55_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ +#define ARMCM55_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ +#define ARMCM55_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ +#define ARMCM55_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ +#define ARMCM55_PMU_PF_LF_LA_1 0xC41C /*!< A data prefetcher line-fill request is made while the lookahead distance is 1. */ +#define ARMCM55_PMU_PF_LF_LA_2 0xC41D /*!< A data prefetcher line-fill request is made while the lookahead distance is 2. */ +#define ARMCM55_PMU_PF_LF_LA_3 0xC41E /*!< A data prefetcher line-fill request is made while the lookahead distance is 3. */ +#define ARMCM55_PMU_PF_LF_LA_4 0xC41F /*!< A data prefetcher line-fill request is made while the lookahead distance is 4. */ +#define ARMCM55_PMU_PF_LF_LA_5 0xC420 /*!< A data prefetcher line-fill request is made while the lookahead distance is 5. */ +#define ARMCM55_PMU_PF_LF_LA_6 0xC421 /*!< A data prefetcher line-fill request is made while the lookahead distance is 6. */ +#define ARMCM55_PMU_PF_BUFFER_FULL 0xC422 /*!< A data prefetcher request is made while the buffer is full. */ +#define ARMCM55_PMU_PF_BUFFER_MISS 0xC423 /*!< A load requires a line-fill which misses in the data prefetcher buffer. */ +#define ARMCM55_PMU_PF_BUFFER_HIT 0xC424 /*!< A load access hits in the data prefetcher buffer. */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm7.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm7.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm7.h (revision 16) @@ -0,0 +1,2471 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M7 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/** \brief SCB Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/** \brief SCB Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/** \brief SCB AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/** \brief SCB L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/** \brief SCB AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/** \brief SCB Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm85.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm85.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_cm85.h (revision 16) @@ -0,0 +1,4949 @@ +/* + * Copyright (c) 2022-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M85 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Coprocessor Power Control Register Definitions */ +#define ICB_CPPWR_SUS11_Pos 23U /*!< CPPWR: SUS11 Position */ +#define ICB_CPPWR_SUS11_Msk (1UL << ICB_CPPWR_SUS11_Pos) /*!< CPPWR: SUS11 Mask */ + +#define ICB_CPPWR_SU11_Pos 22U /*!< CPPWR: SU11 Position */ +#define ICB_CPPWR_SU11_Msk (1UL << ICB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */ + +#define ICB_CPPWR_SUS10_Pos 21U /*!< CPPWR: SUS10 Position */ +#define ICB_CPPWR_SUS10_Msk (1UL << ICB_CPPWR_SUS10_Pos) /*!< CPPWR: SUS10 Mask */ + +#define ICB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ +#define ICB_CPPWR_SU10_Msk (1UL << ICB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl Prefetcher Control Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + __IM uint32_t STLD2MPUOR; /*!< Offset: 0x020 (R/ ) MPU Memory Attributes Register 2 */ + __IM uint32_t STLD3MPUOR; /*!< Offset: 0x024 (R/ ) MPU Memory Attributes Register 3 */ + __IOM uint32_t STLSTBSLOTSR; /*!< Offset: 0x028 (R/W) STB Control Register */ + __IOM uint32_t STLLFDENTRYSR; /*!< Offset: 0x02C (R/W) LFD Control Register */ +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 0 Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 1 Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 2 Definitions */ +#define STL_STLD2MPUOR_HITREGION_Pos 9U /*!< STL STLD2MPUOR: HITREGION Position */ +#define STL_STLD2MPUOR_HITREGION_Msk (0xFFUL << STL_STLD2MPUOR_HITREGION_Pos) /*!< STL STLD2MPUOR: HITREGION Mask */ + +#define STL_STLD2MPUOR_ATTR_Pos 0U /*!< STL STLD2MPUOR: ATTR Position */ +#define STL_STLD2MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD2MPUOR_ATTR_Pos*/) /*!< STL STLD2MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 3 Definitions */ +#define STL_STLD3MPUOR_HITREGION_Pos 9U /*!< STL STLD3MPUOR: HITREGION Position */ +#define STL_STLD3MPUOR_HITREGION_Msk (0xFFUL << STL_STLD3MPUOR_HITREGION_Pos) /*!< STL STLD3MPUOR: HITREGION Mask */ + +#define STL_STLD3MPUOR_ATTR_Pos 0U /*!< STL STLD3MPUOR: ATTR Position */ +#define STL_STLD3MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD3MPUOR_ATTR_Pos*/) /*!< STL STLD3MPUOR: ATTR Mask */ + +/** \brief STL STB Control Register Definitions */ +#define STL_STLSTBSLOTSR_VALID_Pos 4U /*!< STL STLSTBSLOTSR: VALID Position */ +#define STL_STLSTBSLOTSR_VALID_Msk (1UL << STL_STLSTBSLOTSR_VALID_Pos) /*!< STL STLSTBSLOTSR: VALID Mask */ + +#define STL_STLSTBSLOTSR_STBSLOTNUM_Pos 0U /*!< STL STLSTBSLOTSR: STBSLOTNUM Position */ +#define STL_STLSTBSLOTSR_STBSLOTNUM_Msk (0xFUL /*<< STL_STLSTBSLOTSR_STBSLOTNUM_Pos*/) /*!< STL STLSTBSLOTSR: STBSLOTNUM Mask */ + +/** \brief STL LFD Control Register Definitions */ +#define STL_STLLFDENTRYSR_VALID_Pos 4U /*!< STL STLLFDENTRYSR: VALID Position */ +#define STL_STLLFDENTRYSR_VALID_Msk (1UL << STL_STLLFDENTRYSR_VALID_Pos) /*!< STL STLLFDENTRYSR: VALID Mask */ + +#define STL_STLLFDENTRYSR_LFDENTRYNUM_Pos 0U /*!< STL STLLFDENTRYSR: LFDENTRYNUM Position */ +#define STL_STLLFDENTRYSR_LFDENTRYNUM_Msk (0xFUL /*<< STL_STLLFDENTRYSR_LFDENTRYNUM_Pos*/) /*!< STL STLLFDENTRYSR: LFDENTRYNUM Mask */ +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + __OM uint32_t DSCEMCR; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_FPD_Pos DCB_DHCSR_S_FPD_Pos +#define CoreDebug_DHCSR_S_FPD_Msk DCB_DHCSR_S_FPD_Msk + +#define CoreDebug_DHCSR_S_SUIDE_Pos DCB_DHCSR_S_SUIDE_Pos +#define CoreDebug_DHCSR_S_SUIDE_Msk DCB_DHCSR_S_SUIDE_Msk + +#define CoreDebug_DHCSR_S_NSUIDE_Pos DCB_DHCSR_S_NSUIDE_Pos +#define CoreDebug_DHCSR_S_NSUIDE_Msk DCB_DHCSR_S_NSUIDE_Msk + +#define CoreDebug_DHCSR_S_SDE_Pos DCB_DHCSR_S_SDE_Pos +#define CoreDebug_DHCSR_S_SDE_Msk DCB_DHCSR_S_SDE_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_PMOV_Pos DCB_DHCSR_C_PMOV_Pos +#define CoreDebug_DHCSR_C_PMOV_Msk DCB_DHCSR_C_PMOV_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos DCB_DSCEMCR_CLR_MON_REQ_Pos +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk DCB_DSCEMCR_CLR_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos DCB_DSCEMCR_CLR_MON_PEND_Pos +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk DCB_DSCEMCR_CLR_MON_PEND_Msk + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos DCB_DSCEMCR_SET_MON_REQ_Pos +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk DCB_DSCEMCR_SET_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos DCB_DSCEMCR_SET_MON_PEND_Pos +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk DCB_DSCEMCR_SET_MON_PEND_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos DCB_DAUTHCTRL_UIDEN_Pos +#define CoreDebug_DAUTHCTRL_UIDEN_Msk DCB_DAUTHCTRL_UIDEN_Msk + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos DCB_DAUTHCTRL_UIDAPEN_Pos +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk DCB_DAUTHCTRL_UIDAPEN_Msk + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos DCB_DAUTHCTRL_FSDMA_Pos +#define CoreDebug_DAUTHCTRL_FSDMA_Msk DCB_DAUTHCTRL_FSDMA_Msk + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM85_PMU_FUSED_INST_RETIRED 0xC500 /*!< Fused instructions architecturally executed */ +#define ARMCM85_PMU_BR_INDIRECT 0xC501 /*!< Indirect branch instruction architecturally executed */ +#define ARMCM85_PMU_BTAC_HIT 0xC502 /*!< BTAC branch predictor hit */ +#define ARMCM85_PMU_BTAC_HIT_RETURNS 0xC503 /*!< Return branch hits BTAC */ +#define ARMCM85_PMU_BTAC_HIT_CALLS 0xC504 /*!< Call branch hits BTAC */ +#define ARMCM85_PMU_BTAC_HIT_INDIRECT 0xC505 /*!< Indirect branch hits BTACT */ +#define ARMCM85_PMU_BTAC_NEW_ALLOC 0xC506 /*!< New allocation to BTAC */ +#define ARMCM85_PMU_BR_IND_MIS_PRED 0xC507 /*!< Indirect branch mis-predicted */ +#define ARMCM85_PMU_BR_RETURN_MIS_PRED 0xC508 /*!< Return branch mis-predicted */ +#define ARMCM85_PMU_BR_BTAC_OFFSET_OVERFLOW 0xC509 /*!< Branch does not allocate in BTAC due to offset overflow */ +#define ARMCM85_PMU_STB_FULL_STALL_AXI 0xC50A /*!< STore Buffer (STB) full with AXI requests causing CPU to stall */ +#define ARMCM85_PMU_STB_FULL_STALL_TCM 0xC50B /*!< STB full with TCM requests causing CPU to stall */ +#define ARMCM85_PMU_CPU_STALLED_AHBS 0xC50C /*!< CPU is stalled because TCM access through AHBS */ +#define ARMCM85_PMU_AHBS_STALLED_CPU 0xC50D /*!< AHBS is stalled due to TCM access by CPU */ +#define ARMCM85_PMU_BR_INTERSTATING_MIS_PRED 0xC50E /*!< Inter-stating branch is mis-predicted. */ +#define ARMCM85_PMU_DWT_STALL 0xC50F /*!< Data Watchpoint and Trace (DWT) stall */ +#define ARMCM85_PMU_DWT_FLUSH 0xC510 /*!< DWT flush */ +#define ARMCM85_PMU_ETM_STALL 0xC511 /*!< Embedded Trace Macrocell (ETM) stall */ +#define ARMCM85_PMU_ETM_FLUSH 0xC512 /*!< ETM flush */ +#define ARMCM85_PMU_ADDRESS_BANK_CONFLICT 0xC513 /*!< Bank conflict prevents memory instruction dual issue */ +#define ARMCM85_PMU_BLOCKED_DUAL_ISSUE 0xC514 /*!< Dual instruction issuing is prevented */ +#define ARMCM85_PMU_FP_CONTEXT_TRIGGER 0xC515 /*!< Floating Point Context is created */ +#define ARMCM85_PMU_TAIL_CHAIN 0xC516 /*!< New exception is handled without first unstacking */ +#define ARMCM85_PMU_LATE_ARRIVAL 0xC517 /*!< Late-arriving exception taken during exception entry */ +#define ARMCM85_PMU_INT_STALL_FAULT 0xC518 /*!< Delayed exception entry due to ongoing fault processing */ +#define ARMCM85_PMU_INT_STALL_DEV 0xC519 /*!< Delayed exception entry due to outstanding device access */ +#define ARMCM85_PMU_PAC_STALL 0xC51A /*!< Stall caused by authentication code computation */ +#define ARMCM85_PMU_PAC_RETIRED 0xC51B /*!< PAC instruction architecturally executed */ +#define ARMCM85_PMU_AUT_RETIRED 0xC51C /*!< AUT instruction architecturally executed */ +#define ARMCM85_PMU_BTI_RETIRED 0xC51D /*!< BTI instruction architecturally executed */ +#define ARMCM85_PMU_PF_NL_MODE 0xC51E /*!< Prefetch in next line mode */ +#define ARMCM85_PMU_PF_STREAM_MODE 0xC51F /*!< Prefetch in stream mode */ +#define ARMCM85_PMU_PF_BUFF_CACHE_HIT 0xC520 /*!< Prefetch request that hit in the cache */ +#define ARMCM85_PMU_PF_REQ_LFB_HIT 0xC521 /*!< Prefetch request that hit in line fill buffers */ +#define ARMCM85_PMU_PF_BUFF_FULL 0xC522 /*!< Number of times prefetch buffer is full */ +#define ARMCM85_PMU_PF_REQ_DCACHE_HIT 0xC523 /*!< Generated prefetch request address that hit in D-Cache */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "m-profile/armv81m_pac.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_sc000.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_sc000.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_sc000.h (revision 16) @@ -0,0 +1,1055 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS SC000 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ + +#define __CORTEX_SC (000U) /*!< Cortex Secure Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_sc300.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_sc300.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_sc300.h (revision 16) @@ -0,0 +1,2028 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS SC300 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ + +#define __CORTEX_SC (300U) /*!< Cortex Secure Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_starmc1.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_starmc1.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/core_starmc1.h (revision 16) @@ -0,0 +1,3673 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ + +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + uint32_t RESERVED0[3U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +} EMSS_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/** \brief Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/** \brief Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/** \brief L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_BPU Breakpoint Unit (BPU) + \brief Type definitions for the Breakpoint Unit (BPU) + @{ + */ + +/** + \brief Structure type to access the Breakpoint Unit Register (BPU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED1; + __IOM uint32_t COMP0; /*!< Offset: 0x008 (R/W) Comparator Register 0 */ + __IOM uint32_t COMP1; /*!< Offset: 0x00C (R/W) Comparator Register 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x010 (R/W) Comparator Register 2 */ + __IOM uint32_t COMP3; /*!< Offset: 0x014 (R/W) Comparator Register 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x018 (R/W) Comparator Register 0 */ + __IOM uint32_t COMP5; /*!< Offset: 0x01C (R/W) Comparator Register 0 */ + __IOM uint32_t COMP6; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t COMP7; /*!< Offset: 0x024 (R/W) Comparator Register 0 */ + uint32_t RESERVED2[997]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Register */ + uint32_t RESERVED3[3]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Architecture Register */ +} BPU_Type; + +/** \brief BPU Control Register Definitions */ +#define BPU_CTRL_REV_Pos 28U /*!< BPU CTRL: REV Position */ +#define BPU_CTRL_REV_Msk (0xFUL << BPU_CTRL_REV_Pos) /*!< BPU CTRL: REV Mask */ + +#define BPU_CTRL_NUM_CODE_H_Pos 12U /*!< BPU CTRL: NUM_CODE_H Position */ +#define BPU_CTRL_NUM_CODE_H_Msk (0x7UL << BPU_CTRL_NUM_CODE_H_Pos) /*!< BPU CTRL: NUM_CODE_H Mask */ + +#define BPU_CTRL_NUM_LIT_Pos 8U /*!< BPU CTRL: NUM_LIT Position */ +#define BPU_CTRL_NUM_LIT_Msk (0xFUL << BPU_CTRL_NUM_LIT_Pos) /*!< BPU CTRL: NUM_LIT Mask */ + +#define BPU_CTRL_NUM_CODE_L_Pos 4U /*!< BPU CTRL: NUM_CODE_L Position */ +#define BPU_CTRL_NUM_CODE_L_Msk (0xFUL << BPU_CTRL_NUM_CODE_L_Pos) /*!< BPU CTRL: NUM_CODE_L Mask */ + +#define BPU_CTRL_KEY_Pos 1U /*!< BPU CTRL: KEY Position */ +#define BPU_CTRL_KEY_Msk (0x1UL << BPU_CTRL_KEY_Pos) /*!< BPU CTRL: KEY Mask */ + +#define BPU_CTRL_ENABLE_Pos 0U /*!< BPU CTRL: ENABLE Position */ +#define BPU_CTRL_ENABLE_Msk (0x1UL << BPU_CTRL_ENABLE_Pos) /*!< BPU CTRL: ENABLE Mask */ + +/** \brief BPU Comparator Register Definitions */ +#define BPU_COMP_BPADDR_Pos 1U /*!< BPU COMP: BPADDR Position */ +#define BPU_COMP_BPADDR_Msk (0x7FFFFFFFUL << BPU_COMP_BPADDR_Pos) /*!< BPU COMP: BPADDR Mask */ + +#define BPU_COMP_BE_Pos 0U /*!< BPU COMP: BE Position */ +#define BPU_COMP_BE_Msk (0x1UL << BPU_COMP_BE_Pos) /*!< BPU COMP: BE Mask */ + +/*@}*/ /* end of group CMSIS_BPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit field value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define BPU_BASE (0xE0002000UL) /*!< BPU Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv7m_cachel1.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv7m_cachel1.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv7m_cachel1.h (revision 16) @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later + */ + +#ifndef ARM_ARMV7M_CACHEL1_H +#define ARM_ARMV7M_CACHEL1_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_ARMV7M_CACHEL1_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv7m_mpu.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv7m_mpu.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv7m_mpu.h (revision 16) @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv7-M MPU + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv81m_pac.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv81m_pac.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv81m_pac.h (revision 16) @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension + */ + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv8m_mpu.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv8m_mpu.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv8m_mpu.h (revision 16) @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE(void) +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv8m_pmu.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv8m_pmu.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/armv8m_pmu.h (revision 16) @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PMU API for Armv8.1-M PMU + */ + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_armclang_m.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_armclang_m.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_armclang_m.h (revision 16) @@ -0,0 +1,819 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_M_H +#define __CMSIS_ARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) +{ + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_M_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_clang_m.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_clang_m.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_clang_m.h (revision 16) @@ -0,0 +1,825 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_M_H +#define __CMSIS_CLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __stack +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __stack_limit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __stack_seal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) +{ + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_CLANG_M_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_gcc_m.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_gcc_m.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_gcc_m.h (revision 16) @@ -0,0 +1,716 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler GCC Header File + */ + +#ifndef __CMSIS_GCC_M_H +#define __CMSIS_GCC_M_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +#include + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct __copy_table { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct __zero_table { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) +{ + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CMSIS_GCC_M_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_iccarm_m.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_iccarm_m.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_iccarm_m.h (revision 16) @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2017-2024 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_M_H__ +#define __CMSIS_ICCARM_M_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #elif __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#define __get_APSR() (__arm_rsr("APSR")) +#define __get_BASEPRI() (__arm_rsr("BASEPRI")) +#define __get_CONTROL() (__arm_rsr("CONTROL")) +#define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + +#define __get_IPSR() (__arm_rsr("IPSR")) +#define __get_MSP() (__arm_rsr("MSP")) +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) +#else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) +#endif +#define __get_PRIMASK() (__arm_rsr("PRIMASK")) +#define __get_PSP() (__arm_rsr("PSP")) + +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) +#else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) +#endif + +#define __get_xPSR() (__arm_rsr("xPSR")) + +#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) +#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ +__arm_wsr("CONTROL", control); +__iar_builtin_ISB(); +} + +#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) +#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) +#else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) +#endif +#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) +#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) +#else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) +#endif + +#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ +__arm_wsr("CONTROL_NS", control); +__iar_builtin_ISB(); +} + +#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) +#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) +#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) +#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) +#define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) +#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) +#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) +#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) +#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) +#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) +#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) +#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) +#else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) +#endif + +#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) +#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + + +#endif /* __CMSIS_ICCARM_M_H__ */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_tiarmclang_m.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_tiarmclang_m.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/m-profile/cmsis_tiarmclang_m.h (revision 16) @@ -0,0 +1,1451 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler TIARMClang Header File + */ + +#ifndef __CMSIS_TIARMCLANG_M_H +#define __CMSIS_TIARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _c_int00 +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __STACK_END +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __STACK_SIZE +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) +{ + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_TIARMCLANG_M_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_armclang_r.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_armclang_r.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_armclang_r.h (revision 16) @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file cmsis_armclang_r.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 04. December 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_R_H +#define __CMSIS_ARMCLANG_R_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#endif /* __CMSIS_ARMCLANG_R_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_clang_r.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_clang_r.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_clang_r.h (revision 16) @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file cmsis_clang_r.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 04. December 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_CORER_H +#define __CMSIS_CLANG_CORER_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#endif /* __CMSIS_CLANG_COREA_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_gcc_r.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_gcc_r.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_gcc_r.h (revision 16) @@ -0,0 +1,163 @@ +/**************************************************************************//** + * @file cmsis_gcc_r.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 4. August 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_R_H +#define __CMSIS_GCC_R_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + + +/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +/*@} end of group CMSIS_Core_intrinsics */ + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_R_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_iccarm_r.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_iccarm_r.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/r-profile/cmsis_iccarm_r.h (revision 16) @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2017-2024 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(R) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_R_H +#define __CMSIS_ICCARM_R_H + +#pragma system_include /* treat file as system include file */ + +#ifndef __CMSIS_ICCARM_H + #error "This file must not be included directly" +#endif + +#define __get_CPSR() (__arm_rsr("CPSR")) +#define __get_mode() (__get_CPSR() & 0x1FU) + +#define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) +#define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + +#if (defined (__ARM_FP) && (__ARM_FP >= 1)) + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) +#else + #define __get_FPEXC() ( 0 ) + #define __set_FPEXC(VALUE) ((void)VALUE) +#endif + +#define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" #cp ":" #op1 ":c" #CRn ":c" #CRm ":" #op2)) + +#define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" #cp ":" #op1 ":c" #CRn ":c" #CRm ":" #op2, (RT))) + +#define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" #cp ", " #op1 ", %Q0, %R0, c" #CRm \ + : "=r"(Rt) \ + : \ + : "memory") + +#define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" #cp ", " #op1 ", %Q0, %R0, c" #CRm \ + : \ + : "r"(Rt) \ + : "memory") + + +__IAR_FT uint32_t __get_SP_usr(void) { + uint32_t cpsr; + uint32_t result; + __ASM volatile("MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" + : "+r"(cpsr), "=r"(result) + : + : "memory"); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) { + uint32_t cpsr; + __ASM volatile("MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" + : "+r"(cpsr) + : "r"(topOfProcStack) + : "memory"); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) { + __ASM volatile( + // Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + // Ensure that subsequent instructions occur in the context of VFP/NEON + // access permitted + " ISB \n" + + // Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + // Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + // Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + // Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + // Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" // Mask off all bits that do not + // have to be preserved. + // Non-preserved bits can/should be + // zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : + : + : "cc", "r1", "r2"); +} + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default = Pe940 +#pragma diag_default = Pe177 +#endif /* __CMSIS_ARMCLANG_R_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/tz_context.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/tz_context.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/Include/tz_context.h (revision 16) @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core(M) Context Management for Armv8-M TrustZone + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H Index: trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/LICENSE =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/LICENSE (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/CMSIS/LICENSE (revision 16) @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (revision 16) @@ -0,0 +1,4443 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + +#if defined(STM32N6) +/* alias CMSIS */ +#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos +#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk +#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN +#endif /* STM32N6 */ + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal.h (revision 16) @@ -0,0 +1,1040 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32N6xx_HAL_H +#define __STM32N6xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_conf.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Types HAL Exported Types + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** + * @brief STM32N6xx HAL Driver version number + */ +#define __STM32N6xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32N6xx_HAL_VERSION_SUB1 (0x04UL) /*!< [23:16] sub1 version */ +#define __STM32N6xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define __STM32N6xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32N6xx_HAL_VERSION ((__STM32N6xx_HAL_VERSION_MAIN << 24U) \ + |(__STM32N6xx_HAL_VERSION_SUB1 << 16U) \ + |(__STM32N6xx_HAL_VERSION_SUB2 << 8U ) \ + |(__STM32N6xx_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootId Boot Id + * @{ + */ +#define SYSCFG_BOOT_0 SYSCFG_BOOTCR_BOOT0_PD /*!< Boot 0 selection */ +#define SYSCFG_BOOT_1 SYSCFG_BOOTCR_BOOT1_PD /*!< Boot 1 selection */ +/** + * @} + */ + +/** @defgroup SYSCFG_SDMMCId SDMMC Id + * @{ + */ +#define SYSCFG_SDMMC1 SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE /*!< SDMMC 1 selection */ +#define SYSCFG_SDMMC2 SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE /*!< SDMMC 2 selection */ +#define SYSCFG_SDMMC_ALL (SYSCFG_SDMMC1 | SYSCFG_SDMMC2) /*!< SDMMC 1 & 2 selection */ +/** + * @} + */ + +/** @defgroup SYSCFG_USBId USB Id + * @{ + */ +#define SYSCFG_USB1 SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE /*!< USB 1 selection */ +#define SYSCFG_USB2 SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE /*!< USB 2 selection */ +#define SYSCFG_USB_ALL (SYSCFG_USB1 | SYSCFG_USB2) /*!< USB 1 & 2 selection */ +/** + * @} + */ + +/** @defgroup SYSCFG_XPUId XPU Id + * @{ + */ +#if defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE) +#define SYSCFG_NPU_NIC SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE /*!< NPU_NIC clock gating disable selection */ +#endif /* defined(SYSCFG_ICNCGCR_NPU_NOCSYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_CG_DISABLE) */ +#define SYSCFG_CPU_NIC SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE /*!< CPU_NIC clock gating disable selection */ +#define SYSCFG_CPU_NOC SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE /*!< CPU_NOC clock gating disable selection */ +#if defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE) +#define SYSCFG_CPU_ALL (SYSCFG_NPU_NIC | SYSCFG_CPU_NIC | SYSCFG_CPU_NOC) +#else +#define SYSCFG_CPU_ALL (SYSCFG_CPU_NIC | SYSCFG_CPU_NOC) +#endif /* defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE) */ +/** + * @} + */ + +/** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection + * @{ + */ +#define SYSCFG_IO_VDDIO2_CELL 0U /*!< I/O Compensation cell for VDDIO2 */ +#define SYSCFG_IO_VDDIO3_CELL 1U /*!< I/O Compensation cell for VDDIO3 */ +#define SYSCFG_IO_VDDIO4_CELL 2U /*!< I/O Compensation cell for VDDIO4 */ +#define SYSCFG_IO_VDDIO5_CELL 3U /*!< I/O Compensation cell for VDDIO5 */ +/** + * @} + */ + +/** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config + * @{ + */ +#define SYSCFG_IO_CELL_CODE 0UL /*!< Code from the cell */ +#define SYSCFG_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */ +/** + * @} + */ + +/** @defgroup SYSCFG_DELAY_Feedback_Clock Delay on feedback clock + * @{ + */ +#define SYSCFG_DELAY_FEEDBACK_NONE 0U /*!< No delay on the feedback clock */ +#define SYSCFG_DELAY_FEEDBACK_HALF_CYCLE SYSCFG_FMC_RETIMECR_SDFBCLK_180 /*!< Half a cycle delay on the feedback clock */ +/** + * @} + */ + + +/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts + * @{ + */ +#define SYSCFG_IT_FPU_IOC SYSCFG_CM55CR_FPU_IT_EN_0 /*!< Floating Point Unit Invalid operation Interrupt */ +#define SYSCFG_IT_FPU_DZC SYSCFG_CM55CR_FPU_IT_EN_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ +#define SYSCFG_IT_FPU_UFC SYSCFG_CM55CR_FPU_IT_EN_2 /*!< Floating Point Unit Underflow Interrupt */ +#define SYSCFG_IT_FPU_OFC SYSCFG_CM55CR_FPU_IT_EN_3 /*!< Floating Point Unit Overflow Interrupt */ +#define SYSCFG_IT_FPU_IDC SYSCFG_CM55CR_FPU_IT_EN_4 /*!< Floating Point Unit Input denormal Interrupt */ +#define SYSCFG_IT_FPU_IXC SYSCFG_CM55CR_FPU_IT_EN_5 /*!< Floating Point Unit Inexact Interrupt */ +#define SYSCFG_IT_FPU_ALL (SYSCFG_CM55CR_FPU_IT_EN_0 |\ + SYSCFG_CM55CR_FPU_IT_EN_1 |\ + SYSCFG_CM55CR_FPU_IT_EN_2 |\ + SYSCFG_CM55CR_FPU_IT_EN_3 |\ + SYSCFG_CM55CR_FPU_IT_EN_4 |\ + SYSCFG_CM55CR_FPU_IT_EN_5) + +/** + * @} + */ + + +/** @defgroup SYSCFG_Lock_items SYSCFG Lock items + * @brief SYSCFG items to set lock on + * @{ + */ +#define SYSCFG_MPU_NSEC SYSCFG_CM55CR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define SYSCFG_VTOR_NSEC SYSCFG_CM55CR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_DCAIC (SYSCFG_CM55CR_LOCKDCAIC) /*!< Disable access to the instruction cache direct cache access registers DCAICLR +and DCAICRR */ +#define SYSCFG_SAU (SYSCFG_CM55CR_LOCKSAU) /*!< SAU lock (privileged secure code only) */ +#define SYSCFG_MPU_SEC (SYSCFG_CM55CR_LOCKSMPU) /*!< Secure MPU lock (privileged secure code only) */ +#define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CM55CR_LOCKSVTAIRCR) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC | SYSCFG_VTOR_NSEC | SYSCFG_DCAIC | SYSCFG_SAU | SYSCFG_MPU_SEC | SYSCFG_VTOR_AIRCR_SEC) /*!< All */ +#else +#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC | SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup SYSCFG_DTCM_size SYSCFG DTCM size + * @brief DTCM size to be configured + * @{ + */ +#define SYSCFG_DTCM_128K (SYSCFG_CM55TCMCR_CFGDTCMSZ_3) /*!< DTCM memory size is 128K */ +#define SYSCFG_DTCM_256K (SYSCFG_CM55TCMCR_CFGDTCMSZ_0 | SYSCFG_CM55TCMCR_CFGDTCMSZ_3) /*!< DTCM memory size is 256K */ + +/** + * @} + */ + +/** @defgroup SYSCFG_ITCM_size SYSCFG ITCM size + * @brief ITCM size to be configured + * @{ + */ +#define SYSCFG_ITCM_64K (SYSCFG_CM55TCMCR_CFGITCMSZ_0 | SYSCFG_CM55TCMCR_CFGITCMSZ_1 | SYSCFG_CM55TCMCR_CFGITCMSZ_2) /*!< ITCM memory size is 64K */ +#define SYSCFG_ITCM_128K (SYSCFG_CM55TCMCR_CFGITCMSZ_3) /*!< ITCM memory size is 128K */ +#define SYSCFG_ITCM_256K (SYSCFG_CM55TCMCR_CFGITCMSZ_0 | SYSCFG_CM55TCMCR_CFGITCMSZ_3) /*!< ITCM memory size is 256K */ + +/** + * @} + */ + +/** @defgroup SYSCFG_WRITE_access WRITE access selection + * @brief WRITE assess to be configured + * @{ + */ +#define SYSCFG_LOCK_WR_TCM (SYSCFG_CM55TCMCR_LOCKTCM) /*!< ITCM memory size is 64K */ +#define SYSCFG_LOCK_WR_ITGU (SYSCFG_CM55TCMCR_LOCKITGU) /*!< Disable writes to registers associated with the ITCM interface security/gating. */ +#define SYSCFG_LOCK_WR_DTGU (SYSCFG_CM55TCMCR_LOCKDTGU) /*!< Disable writes to registers associated with the DTCM interface security/gating */ +#define SYSCFG_LOCK_WR_ALL (SYSCFG_CM55TCMCR_LOCKTCM | SYSCFG_CM55TCMCR_LOCKITGU | SYSCFG_CM55TCMCR_LOCKDTGU) /*!< All writes accesses */ +/** + * @} + */ +/** @defgroup SYSCFG_CACHE_biasing Cache biasing level adjust input selection + * @brief CACHE biasing level adjust input selection + * @{ + */ +#define SYSCFG_CACHE_BIAS_VNOM SYSCFG_CM55RWMCR_BC1_CACHE +#define SYSCFG_CACHE_BIAS_VNOM_10_PERCENT SYSCFG_CM55RWMCR_BC2_CACHE +/** + * @} + */ + +/** @defgroup SYSCFG_TCM_biasing biasing level selection + * @brief TCM biasing level adjust input selection + * @{ + */ +#define SYSCFG_TCM_BIAS_VNOM SYSCFG_CM55RWMCR_BC1_TCM +#define SYSCFG_TCM_BIAS_VNOM_10_PERCENT SYSCFG_CM55RWMCR_BC2_TCM +/** + * @} + */ + +/** @defgroup SBS_Timer_Break_Inputs Timer Break Inputs + * @{ + */ +#define SYSCFG_CBR_BREAK_LOCK_CORE SYSCFG_CBR_CM55L /*!< Cortex-CM55 lockup break lock */ +#define SYSCFG_CBR_BREAK_LOCK_PVD SYSCFG_CBR_PVDL_LOCK /*!< PVD lock */ +#define SYSCFG_CBR_BREAK_LOCK_BKPRAM SYSCFG_CBR_BKPRAML /*!< Backup SRAM ECC error break lock */ +#define SYSCFG_CBR_BREAK_LOCK_CM55_CACHE SYSCFG_CBR_CM55CACHEL /*!< CM55 cache double ECC error lock */ +#define SYSCFG_CBR_BREAK_LOCK_CM55_TCM SYSCFG_CBR_CM55TCML /*!< CM55 TCM double ECC error lock */ +#define SYSCFG_CBR_BREAK_LOCK_ALL (SYSCFG_CBR_CM55L |\ + SYSCFG_CBR_PVDL_LOCK |\ + SYSCFG_CBR_BKPRAML |\ + SYSCFG_CBR_CM55CACHEL |\ + SYSCFG_CBR_CM55TCML) + +/** + * @} + */ + +/** @defgroup FMC_SwapBankMapping_Config FMC SwapBankMapping Config + * @{ + */ +#define FMC_SWAPBANK_MODE0 (0x00000000U) /*!< FMC memory default mapping is used */ +#define FMC_SWAPBANK_MODE1 FMC_CFGR_BMAP_0 /*!< FMC SDRAM bank1 and NOR/SRAM/PSRAM bank are swapped */ + +/** + * @} + */ + +/** + * @} + */ + + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#if defined(DBGMCU_APB1LFZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM2_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM2_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM3_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM3_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM4_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM4_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM5_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM5_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM6_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM6_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM7_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM7_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM10_STOP) +#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM10_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM10_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM10_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM11_STOP) +#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM11_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM11_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM11_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM12_STOP) +#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM12_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM12_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM12_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM13_STOP) +#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM13_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM13_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM13_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM14_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM14_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C1_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C1_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C2_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C2_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_I2C3_STOP) +#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C3_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C3_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C3_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_I3C1_STOP) +#define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C1_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_I3C1_STOP) */ + +#if defined(DBGMCU_APB1LFZ1_DBG_I3C2_STOP) +#define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C2_STOP) +#endif /* defined(DBGMCU_APB1LFZ1_DBG_I3C2_STOP) */ + +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) +#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1HFZ1, DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) +#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1HFZ1, DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) +#endif /* defined(DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) */ + +#if defined(DBGMCU_APB2FZ1_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM1_STOP) +#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM1_STOP) */ + +#if defined(DBGMCU_APB2FZ1_DBG_TIM8_STOP) +#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM8_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM8_STOP) +#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM8_STOP) */ + +#if defined(DBGMCU_APB2FZ1_DBG_TIM18_STOP) +#define __HAL_DBGMCU_FREEZE_TIM18() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM18_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM18() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM18_STOP) +#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM18_STOP) */ + +#if defined(DBGMCU_APB2FZ1_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM15_STOP) +#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM15_STOP) */ + +#if defined(DBGMCU_APB2FZ1_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM16_STOP) +#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM16_STOP) */ + +#if defined(DBGMCU_APB2FZ1_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM17_STOP) +#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM17_STOP) */ + +#if defined(DBGMCU_APB2FZ1_DBG_TIM9_STOP) +#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM9_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM9_STOP) +#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM9_STOP) */ + +#if defined(DBGMCU_APB4FZ1_DBG_I2C4_STOP) +#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_I2C4_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_I2C4_STOP) +#endif /* defined(DBGMCU_APB4FZ1_DBG_I2C4_STOP) */ + +#if defined(DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) +#endif /* defined(DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) */ + +#if defined(DBGMCU_APB4FZ1_DBG_LPTIM3_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM3_STOP) +#endif /* DBGMCU_APB4FZ1_DBG_LPTIM3_STOP */ + +#if defined(DBGMCU_APB4FZ1_DBG_LPTIM4_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM4_STOP) +#endif /* DBGMCU_APB4FZ1_DBG_LPTIM4_STOP */ + +#if defined(DBGMCU_APB4FZ1_DBG_LPTIM5_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM5_STOP) +#endif /* DBGMCU_APB4FZ1_DBG_LPTIM5_STOP */ + +#if defined(DBGMCU_APB4FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_RTC_STOP) +#endif /* DBGMCU_APB4FZ1_DBG_RTC_STOP */ + +#if defined(DBGMCU_APB4FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_IWDG_STOP) +#endif /* DBGMCU_APB4FZ1_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB5FZ1_DBG_GFXTIM_STOP) +#define __HAL_DBGMCU_FREEZE_GFXTIM() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5FZ1_DBG_GFXTIM_STOP) +#define __HAL_DBGMCU_UNFREEZE_GFXTIM() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5FZ1_DBG_GFXTIM_STOP) +#endif /* DBGMCU_APB5FZ1_DBG_GFXTIM_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH0() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH0() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH1() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH1() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH2() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH2() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH3() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH3() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH4() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH4() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH5() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH5() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH6() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH6() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH7() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH7() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH8() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH8() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH9() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH9() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH10() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH10() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH11() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH11() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH12() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH12() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH13() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH13() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH14() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH14() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP */ + +#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_CH15() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH15() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP) +#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH0() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH0() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH1() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH1() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH2() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH2() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH3() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH3() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH4() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH4() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH5() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH5() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH6() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH6() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH7() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH7() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH8() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH8() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH9() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH9() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH10() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH10() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH11() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH11() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH12() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH12() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH13() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH13() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH14() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH14() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP */ + +#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP) +#define __HAL_DBGMCU_FREEZE_HPDMA1_CH15() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH15() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP) +#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP */ + +#if defined(DBGMCU_AHB5FZ1_NPU_DBG_FREEZE) +#define __HAL_DBGMCU_FREEZE_NPU() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_NPU_DBG_FREEZE) +#define __HAL_DBGMCU_UNFREEZE_NPU() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_NPU_DBG_FREEZE) +#endif /* DBGMCU_AHB5FZ1_NPU_DBG_FREEZE */ + + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief Floating Point Unit interrupt enable/disable macros + * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts + */ +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + SET_BIT(SYSCFG->CM55CR, (__INTERRUPT__));\ + }while(0) + +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + CLEAR_BIT(SYSCFG->CM55CR, (__INTERRUPT__));\ + }while(0) + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ +#define IS_SYSCFG_BOOT_ID(__BOOTID__) ((((__BOOTID__) & SYSCFG_BOOT_0) == SYSCFG_BOOT_0) || \ + (((__BOOTID__) & SYSCFG_BOOT_1) == SYSCFG_BOOT_1)) + +#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) (((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ + (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) && \ + (((__INTERRUPT__) & ~(SYSCFG_IT_FPU_ALL)) == 0U)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) (((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ + (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ + (((__ITEM__) & SYSCFG_DCAIC) == SYSCFG_DCAIC) || \ + (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ + (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ + (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC)) && \ + (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) +#else +#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) (((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ + (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC)) && \ + (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_SYSCFG_DTCM_SIZE(__SIZE__) ((((__SIZE__) & SYSCFG_CM55TCMCR_CFGDTCMSZ) == SYSCFG_DTCM_128K) || \ + (((__SIZE__) & SYSCFG_CM55TCMCR_CFGDTCMSZ) == SYSCFG_DTCM_256K)) + +#define IS_SYSCFG_ITCM_SIZE(__SIZE__) ((((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_64K) || \ + (((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_128K) || \ + (((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_256K)) + +#define IS_SYSCFG_LOCK_WRACCESS(__WRACCESS__) (((((__WRACCESS__) & SYSCFG_LOCK_WR_TCM) == SYSCFG_LOCK_WR_TCM) || \ + (((__WRACCESS__) & SYSCFG_LOCK_WR_ITGU) == SYSCFG_LOCK_WR_ITGU) || \ + (((__WRACCESS__) & SYSCFG_LOCK_WR_DTGU) == SYSCFG_LOCK_WR_DTGU)) && \ + (((__WRACCESS__) & ~(SYSCFG_LOCK_WR_ALL)) == 0U)) + +#define IS_TCM_MARGIN_INPUT(__MARGIN__) ((__MARGIN__) < 16U) + +#define IS_SYSCFG_CACHE_BIASING_LEVEL(__LEVEL__) ((((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_CACHE | SYSCFG_CM55RWMCR_BC2_CACHE)) == SYSCFG_CACHE_BIAS_VNOM) || \ + (((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_CACHE | SYSCFG_CM55RWMCR_BC2_CACHE)) == SYSCFG_CACHE_BIAS_VNOM_10_PERCENT)) + +#define IS_SYSCFG_TCM_BIASING_LEVEL(__LEVEL__) ((((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_TCM | SYSCFG_CM55RWMCR_BC2_TCM)) == SYSCFG_TCM_BIAS_VNOM) || \ + (((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_TCM | SYSCFG_CM55RWMCR_BC2_TCM)) == SYSCFG_TCM_BIAS_VNOM_10_PERCENT)) + +#define IS_VTOR_ADDRESS(__ADDRESS__) (((__ADDRESS__) & 0x7FU) == 0U) + +#define IS_SYSCFG_QOS_CPU(__QOS__) ((__QOS__) < 16U) + +#define IS_SYSCFG_SDMMC(__SDMMC__) (((((__SDMMC__) & SYSCFG_SDMMC1) == SYSCFG_SDMMC1) || \ + (((__SDMMC__) & SYSCFG_SDMMC2) == SYSCFG_SDMMC2)) && \ + (((__SDMMC__) & ~(SYSCFG_SDMMC_ALL)) == 0U)) + +#define IS_SYSCFG_USB(__USB__) (((((__USB__) & SYSCFG_USB1) == SYSCFG_USB1) || \ + (((__USB__) & SYSCFG_USB2) == SYSCFG_USB2)) && \ + (((__USB__) & ~(SYSCFG_USB_ALL)) == 0U)) + +#if defined(SYSCFG_ICNCGCR_NPU_NOC_CG_DISABLE) +#define IS_SYSCFG_CPU_CLK_GATING(__CPU__) (((((__CPU__) & SYSCFG_NPU_NOC) == SYSCFG_NPU_NOC) || \ + (((__CPU__) & SYSCFG_CPU_NIC) == SYSCFG_CPU_NIC) || \ + (((__CPU__) & SYSCFG_CPU_NOC) == SYSCFG_CPU_NOC)) && \ + (((__CPU__) & ~(SYSCFG_CPU_ALL)) == 0U)) +#else +#define IS_SYSCFG_CPU_CLK_GATING(__CPU__) (((((__CPU__) & SYSCFG_CPU_NIC) == SYSCFG_CPU_NIC) || \ + (((__CPU__) & SYSCFG_CPU_NOC) == SYSCFG_CPU_NOC)) && \ + (((__CPU__) & ~(SYSCFG_CPU_ALL)) == 0U)) +#endif /* defined(SYSCFG_ICNCGCR_NPU_NOC_CG_DISABLE) */ + +#define IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) +#define IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) + +#define IS_SYSCFG_COMPENSATION_CELL(__VALUE__) (((__VALUE__) == SYSCFG_IO_VDDIO2_CELL) || \ + ((__VALUE__) == SYSCFG_IO_VDDIO3_CELL) || \ + ((__VALUE__) == SYSCFG_IO_VDDIO4_CELL) || \ + ((__VALUE__) == SYSCFG_IO_VDDIO5_CELL)) + +#define IS_SYSCFG_IO_COMPENSATION_CODE(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_CODE) || \ + ((__CELL__) == SYSCFG_IO_REGISTER_CODE)) + +#define IS_SYSCFG_CBR_BREAK_INPUT(__VALUE__) \ + ((((__VALUE__) & SYSCFG_CBR_BREAK_LOCK_ALL) != 0U) && \ + (((__VALUE__) & ~SYSCFG_CBR_BREAK_LOCK_ALL) == 0U)) + +#define IS_SYSCFG_DMA_CID_SEC(__CID__) (((__CID__) < 8U)) + +#define IS_SYSCFG_DMA_CID_NON_SEC(__CID__) (((__CID__) < 8U)) + +#define IS_SYSCFG_DMA_DELAY_FEEDBACK_CLOCK(__DELAY__) (((__DELAY__) == SYSCFG_DELAY_FEEDBACK_NONE) || \ + ((__DELAY__) == SYSCFG_DELAY_FEEDBACK_HALF_CYCLE)) + +/** + * @} + */ + + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/** @defgroup FMC_Private_Macros FMC Private Macros + * @{ + */ +#define IS_FMC_SWAPBANK_MODE(__MODE__) (((__MODE__) == FMC_SWAPBANK_MODE0) || \ + ((__MODE__) == FMC_SWAPBANK_MODE1)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +#if defined(CPU_IN_SECURE_STATE) +uint32_t HAL_GetDEVID(void); +#endif /* CPU_IN_SECURE_STATE */ +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** @addtogroup HAL_Exported_Functions_Group4 + * @{ + */ + +/* SYSCFG Peripheral Control functions *****************************************/ +void HAL_SYSCFG_EnablePullDown(uint32_t BootId); +void HAL_SYSCFG_DisablePullDown(uint32_t BootId); + + +void HAL_SYSCFG_Lock(uint32_t Item); +HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); + +void HAL_SYSCFG_SetTCMSize(uint32_t DtcmSize, uint32_t ItcmSize); +HAL_StatusTypeDef HAL_SYSCFG_GetTCMSize(uint32_t *pDtcmSize, uint32_t *pItcmSize); + +void HAL_SYSCFG_LockWriteAccess(uint32_t Item); +HAL_StatusTypeDef HAL_SYSCFG_GetLockWriteAccess(uint32_t *pItem); + +void HAL_SYSCFG_EnableITCMWaiteState(void); +void HAL_SYSCFG_DisableITCMWaiteState(void); +void HAL_SYSCFG_EnableDTCMWaiteState(void); +void HAL_SYSCFG_DisableDTCMWaiteState(void); + +void HAL_SYSCFG_EnableTCMExternalMargin(void); +void HAL_SYSCFG_DisableTCMExternalMargin(void); + +void HAL_SYSCFG_SetTCMRWMarginInput(uint32_t TcmRwMarginInput); +HAL_StatusTypeDef HAL_SYSCFG_GetTCMRWMarginInput(uint32_t *pTcmRwMarginInput); + +void HAL_SYSCFG_SetTCMBiasingLevel(uint32_t Level); +HAL_StatusTypeDef HAL_SYSCFG_GetTCMBiasingLevel(uint32_t *pLevel); + +void HAL_SYSCFG_EnableCacheExternalMargin(void); +void HAL_SYSCFG_DisableCacheExternalMargin(void); + +void HAL_SYSCFG_SetCacheRWMarginInput(uint32_t CacheRWMarginInput); +HAL_StatusTypeDef HAL_SYSCFG_GetCacheRWMarginInput(uint32_t *pCacheRWMarginInput); + +void HAL_SYSCFG_SetCacheBiasingLevel(uint32_t Level); +HAL_StatusTypeDef HAL_SYSCFG_GetCacheBiasingLevel(uint32_t *pLevel); + + +void HAL_SYSCFG_SetSVTORAddress(uint32_t Address); +HAL_StatusTypeDef HAL_SYSCFG_GetSVTORAddress(uint32_t *pAddress); + +void HAL_SYSCFG_SetNSVTORAddress(uint32_t Address); +HAL_StatusTypeDef HAL_SYSCFG_GetNSVTORAddress(uint32_t *pAddress); + + +void HAL_SYSCFG_EnablePowerOnReset(void); +void HAL_SYSCFG_DisablePowerOnReset(void); + +void HAL_SYSCFG_EnableLockupWarmResetonRCC(void); +void HAL_SYSCFG_DisableLockupWarmResetonRCC(void); + +void HAL_SYSCFG_EnableLockupGenerateNMI(void); +void HAL_SYSCFG_DisableLockupGenerateNMI(void); + +HAL_StatusTypeDef HAL_SYSCFG_ReEnableWritePostingErrorCapture(void); + +#if defined(VENC) +void HAL_SYSCFG_EnableVENCRAMReserved(void); +void HAL_SYSCFG_DisableVENCRAMReserved(void); +#endif /* VENC */ + +void HAL_SYSCFG_EnableCRYPPotentialTamper(void); +void HAL_SYSCFG_DisableCRYPPotentialTamper(void); + + +void HAL_SYSCFG_SetWriteQosNP1(uint32_t QosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP1(uint32_t *pQosValue); +void HAL_SYSCFG_SetReadQosNP1(uint32_t QosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP1(uint32_t *pQosValue); + +void HAL_SYSCFG_SetWriteQosNP2(uint32_t QosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP2(uint32_t *pQosValue); +void HAL_SYSCFG_SetReadQosNP2(uint32_t QosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP2(uint32_t *pQosValue); + +void HAL_SYSCFG_SetWriteQosCPUSS(uint32_t QosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetwriteQosCPUSS(uint32_t *pQosValue); +void HAL_SYSCFG_SetReadQosCPUSS(uint32_t QosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetReadQosCPUSS(uint32_t *pQosValue); + + +void HAL_SYSCFG_EnableSDMMCEarlyWRRESP(uint32_t Sdmmc); +void HAL_SYSCFG_DisableSDMMCEarlyWRRSP(uint32_t Sdmmc); + +void HAL_SYSCFG_EnableUSBEarlyEarlyWRRESP(uint32_t Usb); +void HAL_SYSCFG_DisableUSBEarlyEarlyWRRESP(uint32_t Usb); + + +void HAL_SYSCFG_EnablexPUClockGating(uint32_t Xpu); +void HAL_SYSCFG_DisablexPUClockGating(uint32_t Xpu); + + + + +void HAL_SYSCFG_EnableVDDIO2CompensationCell(void); +void HAL_SYSCFG_DisableVDDIO2CompensationCell(void); + +void HAL_SYSCFG_EnableVDDIO3CompensationCell(void); +void HAL_SYSCFG_DisableVDDIO3CompensationCell(void); + +void HAL_SYSCFG_EnableVDDIO4CompensationCell(void); +void HAL_SYSCFG_DisableVDDIO4CompensationCell(void); + +void HAL_SYSCFG_EnableVDDIO5CompensationCell(void); +void HAL_SYSCFG_DisableVDDIO5CompensationCell(void); + + +HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDIOCompensationCell(uint32_t Selection, uint32_t Code, + uint32_t NmosValue, uint32_t PmosValue); + +HAL_StatusTypeDef HAL_SYSCFG_GetVDDIOCompensationCell(uint32_t Selection, const uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue); + + +uint32_t HAL_SYSCFG_GetCompVDDIO2CellReadyStatus(void); +uint32_t HAL_SYSCFG_GetCompVDDIO3CellReadyStatus(void); +uint32_t HAL_SYSCFG_GetCompVDDIO4CellReadyStatus(void); +uint32_t HAL_SYSCFG_GetCompVDDIO5CellReadyStatus(void); + +HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDCompensationCell(uint32_t Code, uint32_t NmosValue, uint32_t PmosValue); + +void HAL_SYSCFG_EnableVDDCompensationCell(void); +void HAL_SYSCFG_DisableVDDCompensationCell(void); + +HAL_StatusTypeDef HAL_SYSCFG_GetVDDCompensationCell(uint32_t Code, uint32_t *pNmosValue, + uint32_t *pPmosValue); +uint32_t HAL_SYSCFG_GetCompensationVDDCellReadyStatus(void); + +void HAL_SYSCFG_ConfigTimerBreakInput(uint32_t Input); +uint32_t HAL_SYSCFG_GetTimerBreakInputConfig(void); + +void HAL_SYSCFG_SetPerceivedCID(uint32_t Cid); +uint32_t HAL_SYSCFG_GetPerceivedCID(void); + +void HAL_SYSCFG_SetPerceivedPrivCID(uint32_t Cid); +uint32_t HAL_SYSCFG_GetPerceivedPrivCID(void); + +void HAL_SYSCFG_EnableReTimingRXpath(void); +void HAL_SYSCFG_DisableReTimingRXpath(void); + +void HAL_SYSCFG_EnableReTimingTXpath(void); +void HAL_SYSCFG_DisableReTimingTXpath(void); + +void HAL_SYSCFG_SetDelayOnFeedbackClock(uint32_t Delay); +uint32_t HAL_SYSCFG_GetDelayOnFeedbackClock(void); + +void HAL_SYSCFG_EnableInterleavingCpuRam(void); +void HAL_SYSCFG_DisableInterleavingCpuRam(void); + +uint32_t HAL_SYSCFG_GetBootPinConnection(uint32_t BootId); + +uint32_t HAL_SYSCFG_GetAddressWritePostingBuffer(void); + +/** @addtogroup HAL_Exported_Functions_Group5 + * @{ + */ + +/* FMC Configuration functions ************************************************/ +void HAL_FMC_SetBankSwapConfig(uint32_t BankMapConfig); +uint32_t HAL_FMC_GetBankSwapConfig(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32N6xx_HAL_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cortex.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cortex.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cortex.h (revision 16) @@ -0,0 +1,421 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_CORTEX_H +#define STM32N6xx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint8_t AttributesIndex; /*!< Specifies the memory attributes index. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t DisablePrivExec; /*!< Specifies if privileged software can execute instructions from this region. + This parameter can be a value of @ref CORTEX_MPU_Priv_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Number; /*!< Specifies the number of the memory attributes to configure. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + + uint8_t Attributes; /*!< Specifies the memory attributes vue. + This parameter can be a value of @ref CORTEX_MPU_Attributes */ + +} MPU_Attributes_InitTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 7U /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 6U /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 5U /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 4U /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 3U /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0U +#define SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE 1U +#define MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Priv_Instruction_Access CORTEX MPU Privileged Instruction Access + * @{ + */ +#define MPU_PRIV_INSTRUCTION_ACCESS_ENABLE 0U +#define MPU_PRIV_INSTRUCTION_ACCESS_DISABLE 1U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_NOT_SHAREABLE 0U +#define MPU_ACCESS_OUTER_SHAREABLE 2U +#define MPU_ACCESS_INNER_SHAREABLE 3U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_PRIV_RW 0U +#define MPU_REGION_ALL_RW 1U +#define MPU_REGION_PRIV_RO 2U +#define MPU_REGION_ALL_RO 3U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 0U +#define MPU_REGION_NUMBER1 1U +#define MPU_REGION_NUMBER2 2U +#define MPU_REGION_NUMBER3 3U +#define MPU_REGION_NUMBER4 4U +#define MPU_REGION_NUMBER5 5U +#define MPU_REGION_NUMBER6 6U +#define MPU_REGION_NUMBER7 7U +#define MPU_REGION_NUMBER8 8U +#define MPU_REGION_NUMBER9 9U +#define MPU_REGION_NUMBER10 10U +#define MPU_REGION_NUMBER11 11U +#define MPU_REGION_NUMBER12 12U +#define MPU_REGION_NUMBER13 13U +#define MPU_REGION_NUMBER14 14U +#define MPU_REGION_NUMBER15 15U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number + * @{ + */ +#define MPU_ATTRIBUTES_NUMBER0 0U +#define MPU_ATTRIBUTES_NUMBER1 1U +#define MPU_ATTRIBUTES_NUMBER2 2U +#define MPU_ATTRIBUTES_NUMBER3 3U +#define MPU_ATTRIBUTES_NUMBER4 4U +#define MPU_ATTRIBUTES_NUMBER5 5U +#define MPU_ATTRIBUTES_NUMBER6 6U +#define MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes + * @{ + */ + +/* Device memory attributes */ +#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ + +/* Normal Memory attributes */ +/* Note that these attributes need to be set for both inner AND outer attributes. + These defines should be used with the INNER_OUTER macro if they are the same for inner and outer. */ +/* - Non-cacheable memory attribute*/ +#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ + +/* - Cacheable memory attributes*/ +#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ +#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ + +#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ +#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ + +#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ +#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ +#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ +#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** @defgroup CORTEX_MPU_Normal_Memory_Attributes CORTEX MPU Normal Memory Attributes + * @{ + */ +/* __ATTR__ being a combination of MPU Normal memory attributes */ +#define OUTER(__ATTR__) ((__ATTR__) << 4U) +#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +__NO_RETURN void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, + uint32_t *pPreemptPriority, uint32_t *pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +void HAL_CORTEX_ClearEvent(void); +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit); +#ifdef MPU_NS +void HAL_MPU_Enable_NS(uint32_t MPU_Control); +void HAL_MPU_Disable_NS(void); +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *pMPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit); +#endif /* MPU_NS */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_INTERRUPT(__IT__) (((__IT__) > HardFault_IRQn) && ((__IT__) != DebugMonitor_IRQn)) + +#define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIO__) < (1UL << __NVIC_PRIO_BITS)) && \ + ((__PRIO__) < (1UL << (7U - (__PRIOGRP__))))) + +#define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIOGRP__) < (7U - __NVIC_PRIO_BITS)) ? \ + ((__PRIO__) < 1U): \ + ((__PRIO__) < (1UL << ((__PRIOGRP__) - (7U - __NVIC_PRIO_BITS))))) + +#define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ + ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \ + ((__STATE__) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_PRIV_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_PRIV_INSTRUCTION_ACCESS_ENABLE) || \ + ((__STATE__) == MPU_PRIV_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_OUTER_SHAREABLE) || \ + ((__STATE__) == MPU_ACCESS_INNER_SHAREABLE) || \ + ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_PRIV_RW) || \ + ((__TYPE__) == MPU_REGION_ALL_RW) || \ + ((__TYPE__) == MPU_REGION_PRIV_RO) || \ + ((__TYPE__) == MPU_REGION_ALL_RO)) + +#define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \ + ((__NUMBER__) == MPU_REGION_NUMBER1) || \ + ((__NUMBER__) == MPU_REGION_NUMBER2) || \ + ((__NUMBER__) == MPU_REGION_NUMBER3) || \ + ((__NUMBER__) == MPU_REGION_NUMBER4) || \ + ((__NUMBER__) == MPU_REGION_NUMBER5) || \ + ((__NUMBER__) == MPU_REGION_NUMBER6) || \ + ((__NUMBER__) == MPU_REGION_NUMBER7) || \ + ((__NUMBER__) == MPU_REGION_NUMBER8) || \ + ((__NUMBER__) == MPU_REGION_NUMBER9) || \ + ((__NUMBER__) == MPU_REGION_NUMBER10) || \ + ((__NUMBER__) == MPU_REGION_NUMBER11) || \ + ((__NUMBER__) == MPU_REGION_NUMBER12) || \ + ((__NUMBER__) == MPU_REGION_NUMBER13) || \ + ((__NUMBER__) == MPU_REGION_NUMBER14) || \ + ((__NUMBER__) == MPU_REGION_NUMBER15)) + +#define IS_MPU_ATTRIBUTES_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_ATTRIBUTES_NUMBER0) || \ + ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER1) || \ + ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER2) || \ + ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER3) || \ + ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER4) || \ + ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER5) || \ + ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER6) || \ + ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER7)) + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_CORTEX_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_def.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_def.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_def.h (revision 16) @@ -0,0 +1,214 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32N6xx_HAL_DEF +#define __STM32N6xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#include "stm32n6xx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((packed)) +#endif /* __packed */ +#elif defined (__GNUC__) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __ARMCC_VERSION */ + +/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */ +#define ALIGN_32BYTES(buf) buf __attribute__((aligned(32))) + +/* Legacy macros to get variable 4-bytes aligned */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif /* __ALIGN_END */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +/* ARM Compiler V6 + --------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined (__ICCARM__) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined (__GNUC__) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif /* __ARMCC_VERSION */ + +/** + * @brief __NOINLINE definition + */ +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__) +/* ARM Compiler V6 & GNU Compiler */ +#define __NOINLINE __attribute__((noinline)) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler */ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* __ARMCC_VERSION || __GNUC__ */ + +/* Non cacheable section and attribute + ------------------------------------ + Create a non-cacheable section for DMA buffers and other hardware shared data. + The user can then use the __NON_CACHEABLE_SECTION_BEGIN and NON_CACHEABLE_SECTION_END to configure a non cacheable region + containing the data that was defined using the __NON_CACHEABLE attribute. */ +#if defined(__ICCARM__) +#pragma section=".noncacheable" +#define __NON_CACHEABLE_SECTION_BEGIN ((uint32_t) __sfb(".noncacheable")) +#define __NON_CACHEABLE_SECTION_END ((uint32_t) __sfe(".noncacheable")) +#elif defined(__ARMCC_VERSION) +extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Base; +extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Limit; +#define __NON_CACHEABLE_SECTION_BEGIN ((uint32_t) &Image$$RW_NONCACHEABLEBUFFER$$Base) +#define __NON_CACHEABLE_SECTION_END ((uint32_t) &Image$$RW_NONCACHEABLEBUFFER$$Limit-1) +#elif defined(__GNUC__) +extern uint32_t __snoncacheable; +extern uint32_t __enoncacheable; +#define __NON_CACHEABLE_SECTION_BEGIN ((uint32_t) &__snoncacheable) +#define __NON_CACHEABLE_SECTION_END ((uint32_t) &__enoncacheable) +#endif /* defined(__ICCARM__) */ +#define __NON_CACHEABLE __attribute__((section(".noncacheable"))) + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32N6xx_HAL_DEF */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma.h (revision 16) @@ -0,0 +1,1173 @@ +/** + ********************************************************************************************************************** + * @file stm32n6xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32N6xx_HAL_DMA_H +#define STM32N6xx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Transfer Configuration Structure definition. + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the DMA channel request. + This parameter can be a value of @ref DMA_Request_Selection */ + + uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. + Block Hardware request feature can be used only with dedicated peripherals. + This parameter can be a value of @ref DMA_Block_Request */ + + uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. + This parameter can be a value of @ref DMA_Transfer_Direction */ + + uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Source_Increment_Mode */ + + uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Increment_Mode */ + + uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. + This parameter can be a value of @ref DMA_Source_Data_Width */ + + uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Data_Width */ + + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA + channel. + This parameter can be a value between 1 and 64 */ + + uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the + DMA channel. + This parameter can be a value between 1 and 64 */ + + uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. + This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Mode */ + +} DMA_InitTypeDef; + +/** + * @brief DMA Linked-List Configuration Structure Definition. + */ +typedef struct +{ + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Step_Mode */ + + uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. + This parameter can be a value of @ref DMAEx_LinkedList_Mode */ + +} DMA_InitLinkedListTypeDef; + +/** + * @brief DMA CID filtering (isolation) configuration structure. + */ +typedef struct +{ + uint32_t CidFiltering; /*!< Specified the CID filtering mode. + This parameter can be a value of @ref DMA_ISOLATION_MODE */ + uint32_t StaticCid; /*!< Specified the static CID. + This parameter can be a value of @ref DMA_Channel_CID_Filtering_Static */ +} DMA_IsolationConfigTypeDef; + +/** + * @brief HAL DMA State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ + HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ + +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Level Complete Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ + +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ + HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ + HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ + + DMA_InitTypeDef Init; /*!< DMA channel init parameters */ + + DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + uint32_t Mode; /*!< DMA transfer mode */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + __IO uint32_t ErrorCode; /*!< DMA error code */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ + + void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ + + struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ + +} DMA_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Codes DMA Error Codes + * @brief DMA Error Codes + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ +#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ +#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ +#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ +#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ +#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ +#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ +#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition + * @brief DMA Interrupt Enable Definition + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ +#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ +#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ +#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ +#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ +#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ +/** + * @} + */ + +/** @defgroup DMA_Flag_Definition DMA Flag Definition + * @brief DMA Flag Definition + * @{ + */ +#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ +#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ +#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ +#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ +#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ +#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ +#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ +#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ +/** + * @} + */ + +/** @defgroup DMA_Request_Selection DMA Request Selection + * @brief DMA Request Selection + * @{ + */ +/* HPDMA1 requests */ +#define HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_RX */ +#define HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_TX */ +#define HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */ +#define HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */ +#define HPDMA1_REQUEST_XSPI3 4U /*!< HPDMA1 HW request is XSPI3 */ +#define HPDMA1_REQUEST_FMC2_TXRX 5U /*!< HPDMA1 HW request is FMC2_TXRX */ +#define HPDMA1_REQUEST_FMC2_BCH 6U /*!< HPDMA1 HW request is FMC2_BCH */ +#define HPDMA1_REQUEST_ADC1 7U /*!< HPDMA1 HW request is ADC1 */ +#define HPDMA1_REQUEST_ADC2 8U /*!< HPDMA1 HW request is ADC2 */ +#define HPDMA1_REQUEST_CRYP_IN 9U /*!< HPDMA1 HW request is CRYP_IN */ +#define HPDMA1_REQUEST_CRYP_OUT 10U /*!< HPDMA1 HW request is CRYP_OUT */ +#define HPDMA1_REQUEST_SAES_OUT 11U /*!< HPDMA1 HW request is SAES_OUT */ +#define HPDMA1_REQUEST_SAES_IN 12U /*!< HPDMA1 HW request is SAES_IN */ +#define HPDMA1_REQUEST_HASH_IN 13U /*!< HPDMA1 HW request is HASH_IN */ + +#define HPDMA1_REQUEST_TIM1_CH1 14U /*!< HPDMA1 HW request is TIM1_CH1 */ +#define HPDMA1_REQUEST_TIM1_CH2 15U /*!< HPDMA1 HW request is TIM1_CH2 */ +#define HPDMA1_REQUEST_TIM1_CH3 16U /*!< HPDMA1 HW request is TIM1_CH3 */ +#define HPDMA1_REQUEST_TIM1_CH4 17U /*!< HPDMA1 HW request is TIM1_CH4 */ +#define HPDMA1_REQUEST_TIM1_UP 18U /*!< HPDMA1 HW request is TIM1_UP */ +#define HPDMA1_REQUEST_TIM1_TRIG 19U /*!< HPDMA1 HW request is TIM1_TRIG */ +#define HPDMA1_REQUEST_TIM1_COM 20U /*!< HPDMA1 HW request is TIM1_COM */ + +#define HPDMA1_REQUEST_TIM2_CH1 21U /*!< HPDMA1 HW request is TIM2_CH1 */ +#define HPDMA1_REQUEST_TIM2_CH2 22U /*!< HPDMA1 HW request is TIM2_CH2 */ +#define HPDMA1_REQUEST_TIM2_CH3 23U /*!< HPDMA1 HW request is TIM2_CH3 */ +#define HPDMA1_REQUEST_TIM2_CH4 24U /*!< HPDMA1 HW request is TIM2_CH4 */ +#define HPDMA1_REQUEST_TIM2_UP 25U /*!< HPDMA1 HW request is TIM2_UP */ +#define HPDMA1_REQUEST_TIM2_TRIG 26U /*!< HPDMA1 HW request is TIM2_TRIG */ + +#define HPDMA1_REQUEST_TIM3_CH1 27U /*!< HPDMA1 HW request is TIM3_CH1 */ +#define HPDMA1_REQUEST_TIM3_CH2 28U /*!< HPDMA1 HW request is TIM3_CH2 */ +#define HPDMA1_REQUEST_TIM3_CH3 29U /*!< HPDMA1 HW request is TIM3_CH3 */ +#define HPDMA1_REQUEST_TIM3_CH4 30U /*!< HPDMA1 HW request is TIM3_CH4 */ +#define HPDMA1_REQUEST_TIM3_UP 31U /*!< HPDMA1 HW request is TIM3_UP */ +#define HPDMA1_REQUEST_TIM3_TRIG 32U /*!< HPDMA1 HW request is TIM3_TRIG */ + +#define HPDMA1_REQUEST_TIM4_CH1 33U /*!< HPDMA1 HW request is TIM4_CH1 */ +#define HPDMA1_REQUEST_TIM4_CH2 34U /*!< HPDMA1 HW request is TIM4_CH2 */ +#define HPDMA1_REQUEST_TIM4_CH3 35U /*!< HPDMA1 HW request is TIM4_CH3 */ +#define HPDMA1_REQUEST_TIM4_CH4 36U /*!< HPDMA1 HW request is TIM4_CH4 */ +#define HPDMA1_REQUEST_TIM4_UP 37U /*!< HPDMA1 HW request is TIM4_UP */ +#define HPDMA1_REQUEST_TIM4_TRIG 38U /*!< HPDMA1 HW request is TIM4_TRIG */ + +#define HPDMA1_REQUEST_TIM5_CH1 39U /*!< HPDMA1 HW request is TIM5_CH1 */ +#define HPDMA1_REQUEST_TIM5_CH2 40U /*!< HPDMA1 HW request is TIM5_CH2 */ +#define HPDMA1_REQUEST_TIM5_CH3 41U /*!< HPDMA1 HW request is TIM5_CH3 */ +#define HPDMA1_REQUEST_TIM5_CH4 42U /*!< HPDMA1 HW request is TIM5_CH4 */ +#define HPDMA1_REQUEST_TIM5_UP 43U /*!< HPDMA1 HW request is TIM5_UP */ +#define HPDMA1_REQUEST_TIM5_TRIG 44U /*!< HPDMA1 HW request is TIM5_TRIG */ + +#define HPDMA1_REQUEST_TIM6_UP 45U /*!< HPDMA1 HW request is TIM6_UP */ +#define HPDMA1_REQUEST_TIM7_UP 46U /*!< HPDMA1 HW request is TIM7_UP */ + +#define HPDMA1_REQUEST_TIM8_CH1 47U /*!< HPDMA1 HW request is TIM8_CH1 */ +#define HPDMA1_REQUEST_TIM8_CH2 48U /*!< HPDMA1 HW request is TIM8_CH2 */ +#define HPDMA1_REQUEST_TIM8_CH3 49U /*!< HPDMA1 HW request is TIM8_CH3 */ +#define HPDMA1_REQUEST_TIM8_CH4 50U /*!< HPDMA1 HW request is TIM8_CH4 */ +#define HPDMA1_REQUEST_TIM8_UP 51U /*!< HPDMA1 HW request is TIM8_UP */ +#define HPDMA1_REQUEST_TIM8_TRIG 52U /*!< HPDMA1 HW request is TIM8_TRIG */ +#define HPDMA1_REQUEST_TIM8_COM 53U /*!< HPDMA1 HW request is TIM8_COM */ + +/* reserved 54U */ +/* reserved 55U */ + +#define HPDMA1_REQUEST_TIM15_CH1 56U /*!< HPDMA1 HW request is TIM15_CH1 */ +#define HPDMA1_REQUEST_TIM15_CH2 57U /*!< HPDMA1 HW request is TIM15_CH2 */ +#define HPDMA1_REQUEST_TIM15_UP 58U /*!< HPDMA1 HW request is TIM15_UP */ +#define HPDMA1_REQUEST_TIM15_TRIG 59U /*!< HPDMA1 HW request is TIM15_TRIG */ +#define HPDMA1_REQUEST_TIM15_COM 60U /*!< HPDMA1 HW request is TIM15_COM */ + +#define HPDMA1_REQUEST_TIM16_CH1 61U /*!< HPDMA1 HW request is TIM16_CH1 */ +#define HPDMA1_REQUEST_TIM16_UP 62U /*!< HPDMA1 HW request is TIM16_UP */ +#define HPDMA1_REQUEST_TIM16_COM 63U /*!< HPDMA1 HW request is TIM16_COM */ + +#define HPDMA1_REQUEST_TIM17_CH1 64U /*!< HPDMA1 HW request is TIM17_CH1 */ +#define HPDMA1_REQUEST_TIM17_UP 65U /*!< HPDMA1 HW request is TIM17_UP */ +#define HPDMA1_REQUEST_TIM17_COM 66U /*!< HPDMA1 HW request is TIM17_COM */ + +#define HPDMA1_REQUEST_TIM18_CH1 67U /*!< HPDMA1 HW request is TIM18_CH1 */ +#define HPDMA1_REQUEST_TIM18_UP 68U /*!< HPDMA1 HW request is TIM18_UP */ +#define HPDMA1_REQUEST_TIM18_COM 69U /*!< HPDMA1 HW request is TIM18_COM */ + +#define HPDMA1_REQUEST_LPTIM1_IC1 70U /*!< HPDMA1 HW request is LPTIM1_IC1 */ +#define HPDMA1_REQUEST_LPTIM1_IC2 71U /*!< HPDMA1 HW request is LPTIM1_IC2 */ +#define HPDMA1_REQUEST_LPTIM1_UE 72U /*!< HPDMA1 HW request is LPTIM1_UE */ +#define HPDMA1_REQUEST_LPTIM2_IC1 73U /*!< HPDMA1 HW request is LPTIM2_IC1 */ +#define HPDMA1_REQUEST_LPTIM2_IC2 74U /*!< HPDMA1 HW request is LPTIM2_IC2 */ +#define HPDMA1_REQUEST_LPTIM2_UE 75U /*!< HPDMA1 HW request is LPTIM2_UE */ +#define HPDMA1_REQUEST_LPTIM3_IC1 76U /*!< HPDMA1 HW request is LPTIM3_IC1 */ +#define HPDMA1_REQUEST_LPTIM3_IC2 77U /*!< HPDMA1 HW request is LPTIM3_IC2 */ +#define HPDMA1_REQUEST_LPTIM3_UE 78U /*!< HPDMA1 HW request is LPTIM3_UE */ + +#define HPDMA1_REQUEST_SPI1_RX 79U /*!< HPDMA1 HW request is SPI1_RX */ +#define HPDMA1_REQUEST_SPI1_TX 80U /*!< HPDMA1 HW request is SPI1_TX */ +#define HPDMA1_REQUEST_SPI2_RX 81U /*!< HPDMA1 HW request is SPI2_RX */ +#define HPDMA1_REQUEST_SPI2_TX 82U /*!< HPDMA1 HW request is SPI2_TX */ +#define HPDMA1_REQUEST_SPI3_RX 83U /*!< HPDMA1 HW request is SPI3_RX */ +#define HPDMA1_REQUEST_SPI3_TX 84U /*!< HPDMA1 HW request is SPI3_TX */ +#define HPDMA1_REQUEST_SPI4_RX 85U /*!< HPDMA1 HW request is SPI4_RX */ +#define HPDMA1_REQUEST_SPI4_TX 86U /*!< HPDMA1 HW request is SPI4_TX */ +#define HPDMA1_REQUEST_SPI5_RX 87U /*!< HPDMA1 HW request is SPI5_RX */ +#define HPDMA1_REQUEST_SPI5_TX 88U /*!< HPDMA1 HW request is SPI5_TX */ +#define HPDMA1_REQUEST_SPI6_RX 89U /*!< HPDMA1 HW request is SPI6_RX */ +#define HPDMA1_REQUEST_SPI6_TX 90U /*!< HPDMA1 HW request is SPI6_TX */ + +#define HPDMA1_REQUEST_SAI1_A 91U /*!< HPDMA1 HW request is SAI1_A */ +#define HPDMA1_REQUEST_SAI1_B 92U /*!< HPDMA1 HW request is SAI1_B */ +#define HPDMA1_REQUEST_SAI2_A 93U /*!< HPDMA1 HW request is SAI2_A */ +#define HPDMA1_REQUEST_SAI2_B 94U /*!< HPDMA1 HW request is SAI2_B */ + +#define HPDMA1_REQUEST_I2C1_RX 95U /*!< HPDMA1 HW request is I2C1_RX */ +#define HPDMA1_REQUEST_I2C1_TX 96U /*!< HPDMA1 HW request is I2C1_TX */ +#define HPDMA1_REQUEST_I2C2_RX 97U /*!< HPDMA1 HW request is I2C2_RX */ +#define HPDMA1_REQUEST_I2C2_TX 98U /*!< HPDMA1 HW request is I2C2_TX */ +#define HPDMA1_REQUEST_I2C3_RX 99U /*!< HPDMA1 HW request is I2C3_RX */ +#define HPDMA1_REQUEST_I2C3_TX 100U /*!< HPDMA1 HW request is I2C3_TX */ + +#define HPDMA1_REQUEST_I2C4_RX 101U /*!< HPDMA1 HW request is I2C4_RX */ +#define HPDMA1_REQUEST_I2C4_TX 102U /*!< HPDMA1 HW request is I2C4_TX */ + +#define HPDMA1_REQUEST_I3C1_RX 103U /*!< HPDMA1 HW request is I3C1_RX */ +#define HPDMA1_REQUEST_I3C1_TX 104U /*!< HPDMA1 HW request is I3C1_TX */ +#define HPDMA1_REQUEST_I3C2_RX 105U /*!< HPDMA1 HW request is I3C2_RX */ +#define HPDMA1_REQUEST_I3C2_TX 106U /*!< HPDMA1 HW request is I3C2_TX */ + +#define HPDMA1_REQUEST_USART1_RX 107U /*!< HPDMA1 HW request is USART1_RX */ +#define HPDMA1_REQUEST_USART1_TX 108U /*!< HPDMA1 HW request is USART1_TX */ +#define HPDMA1_REQUEST_USART2_RX 109U /*!< HPDMA1 HW request is USART2_RX */ +#define HPDMA1_REQUEST_USART2_TX 110U /*!< HPDMA1 HW request is USART2_TX */ +#define HPDMA1_REQUEST_USART3_RX 111U /*!< HPDMA1 HW request is USART3_RX */ +#define HPDMA1_REQUEST_USART3_TX 112U /*!< HPDMA1 HW request is USART3_TX */ +#define HPDMA1_REQUEST_UART4_RX 113U /*!< HPDMA1 HW request is UART4_RX */ +#define HPDMA1_REQUEST_UART4_TX 114U /*!< HPDMA1 HW request is UART4_TX */ +#define HPDMA1_REQUEST_UART5_RX 115U /*!< HPDMA1 HW request is UART5_RX */ +#define HPDMA1_REQUEST_UART5_TX 116U /*!< HPDMA1 HW request is UART5_TX */ +#define HPDMA1_REQUEST_USART6_RX 117U /*!< HPDMA1 HW request is USART6_RX */ +#define HPDMA1_REQUEST_USART6_TX 118U /*!< HPDMA1 HW request is USART6_TX */ +#define HPDMA1_REQUEST_UART7_RX 119U /*!< HPDMA1 HW request is UART7_RX */ +#define HPDMA1_REQUEST_UART7_TX 120U /*!< HPDMA1 HW request is UART7_TX */ +#define HPDMA1_REQUEST_UART8_RX 121U /*!< HPDMA1 HW request is UART8_RX */ +#define HPDMA1_REQUEST_UART8_TX 122U /*!< HPDMA1 HW request is UART8_TX */ +#define HPDMA1_REQUEST_UART9_RX 123U /*!< HPDMA1 HW request is UART9_RX */ +#define HPDMA1_REQUEST_UART9_TX 124U /*!< HPDMA1 HW request is UART9_TX */ +#define HPDMA1_REQUEST_USART10_RX 125U /*!< HPDMA1 HW request is USART10_RX */ +#define HPDMA1_REQUEST_USART10_TX 126U /*!< HPDMA1 HW request is USART10_TX */ + +#define HPDMA1_REQUEST_LPUART1_RX 127U /*!< HPDMA1 HW request is LPUART1_RX */ +#define HPDMA1_REQUEST_LPUART1_TX 128U /*!< HPDMA1 HW request is LPUART1_TX */ + +#define HPDMA1_REQUEST_SPDIFRX_CS 129U /*!< HPDMA1 HW request is SPDIFRX_CS */ +#define HPDMA1_REQUEST_SPDIFRX_DT 130U /*!< HPDMA1 HW request is SPDIFRX_DT */ + +#define HPDMA1_REQUEST_ADF1_FLT0 131U /*!< HPDMA1 HW request is ADF1_FLT0 */ + +#define HPDMA1_REQUEST_MDF1_FLT0 132U /*!< HPDMA1 HW request is MDF1_FLT0 */ +#define HPDMA1_REQUEST_MDF1_FLT1 133U /*!< HPDMA1 HW request is MDF1_FLT1 */ +#define HPDMA1_REQUEST_MDF1_FLT2 134U /*!< HPDMA1 HW request is MDF1_FLT2 */ +#define HPDMA1_REQUEST_MDF1_FLT3 135U /*!< HPDMA1 HW request is MDF1_FLT3 */ +#define HPDMA1_REQUEST_MDF1_FLT4 136U /*!< HPDMA1 HW request is MDF1_FLT4 */ +#define HPDMA1_REQUEST_MDF1_FLT5 137U /*!< HPDMA1 HW request is MDF1_FLT5 */ + +#define HPDMA1_REQUEST_UCPD1_TX 138U /*!< HPDMA1 HW request is UCPD1_TX */ +#define HPDMA1_REQUEST_UCPD1_RX 139U /*!< HPDMA1 HW request is UCPD1_RX */ + +#define HPDMA1_REQUEST_DCMI_PSSI 140U /*!< HPDMA1 HW request is DCMI_PSSI */ + +#define HPDMA1_REQUEST_I3C1_TC 141U /*!< HPDMA1 HW request is I3C1_TC */ +#define HPDMA1_REQUEST_I3C1_RS 142U /*!< HPDMA1 HW request is I3C1_RS */ + +#define HPDMA1_REQUEST_I3C2_TC 143U /*!< HPDMA1 HW request is I3C2_TC */ +#define HPDMA1_REQUEST_I3C2_RS 144U /*!< HPDMA1 HW request is I3C2_RS */ + +/* GPDMA1 requests */ +#define GPDMA1_REQUEST_JPEG_RX 0U /*!< GPDMA1 HW request is JPEG_DMA_RX */ +#define GPDMA1_REQUEST_JPEG_TX 1U /*!< GPDMA1 HW request is JPEG_DMA_TX */ +#define GPDMA1_REQUEST_XSPI1 2U /*!< GPDMA1 HW request is XSPI1 */ +#define GPDMA1_REQUEST_XSPI2 3U /*!< GPDMA1 HW request is XSPI2 */ +#define GPDMA1_REQUEST_XSPI3 4U /*!< GPDMA1 HW request is XSPI3 */ +#define GPDMA1_REQUEST_FMC2_TXRX 5U /*!< GPDMA1 HW request is FMC2_TXRX */ +#define GPDMA1_REQUEST_FMC2_BCH 6U /*!< GPDMA1 HW request is FMC2_BCH */ +#define GPDMA1_REQUEST_ADC1 7U /*!< GPDMA1 HW request is ADC1 */ +#define GPDMA1_REQUEST_ADC2 8U /*!< GPDMA1 HW request is ADC2 */ +#define GPDMA1_REQUEST_CRYP_IN 9U /*!< GPDMA1 HW request is CRYP_IN */ +#define GPDMA1_REQUEST_CRYP_OUT 10U /*!< GPDMA1 HW request is CRYP_OUT */ +#define GPDMA1_REQUEST_SAES_OUT 11U /*!< GPDMA1 HW request is SAES_OUT */ +#define GPDMA1_REQUEST_SAES_IN 12U /*!< GPDMA1 HW request is SAES_IN */ +#define GPDMA1_REQUEST_HASH_IN 13U /*!< GPDMA1 HW request is HASH_IN */ + +#define GPDMA1_REQUEST_TIM1_CH1 14U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define GPDMA1_REQUEST_TIM1_CH2 15U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define GPDMA1_REQUEST_TIM1_CH3 16U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define GPDMA1_REQUEST_TIM1_CH4 17U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define GPDMA1_REQUEST_TIM1_UP 18U /*!< GPDMA1 HW request is TIM1_UP */ +#define GPDMA1_REQUEST_TIM1_TRIG 19U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define GPDMA1_REQUEST_TIM1_COM 20U /*!< GPDMA1 HW request is TIM1_COM */ + +#define GPDMA1_REQUEST_TIM2_CH1 21U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define GPDMA1_REQUEST_TIM2_CH2 22U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define GPDMA1_REQUEST_TIM2_CH3 23U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define GPDMA1_REQUEST_TIM2_CH4 24U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define GPDMA1_REQUEST_TIM2_UP 25U /*!< GPDMA1 HW request is TIM2_UP */ +#define GPDMA1_REQUEST_TIM2_TRIG 26U /*!< GPDMA1 HW request is TIM2_TRIG */ + +#define GPDMA1_REQUEST_TIM3_CH1 27U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define GPDMA1_REQUEST_TIM3_CH2 28U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define GPDMA1_REQUEST_TIM3_CH3 29U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define GPDMA1_REQUEST_TIM3_CH4 30U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define GPDMA1_REQUEST_TIM3_UP 31U /*!< GPDMA1 HW request is TIM3_UP */ +#define GPDMA1_REQUEST_TIM3_TRIG 32U /*!< GPDMA1 HW request is TIM3_TRIG */ + +#define GPDMA1_REQUEST_TIM4_CH1 33U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define GPDMA1_REQUEST_TIM4_CH2 34U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define GPDMA1_REQUEST_TIM4_CH3 35U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define GPDMA1_REQUEST_TIM4_CH4 36U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define GPDMA1_REQUEST_TIM4_UP 37U /*!< GPDMA1 HW request is TIM4_UP */ +#define GPDMA1_REQUEST_TIM4_TRIG 38U /*!< GPDMA1 HW request is TIM4_TRIG */ + +#define GPDMA1_REQUEST_TIM5_CH1 39U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define GPDMA1_REQUEST_TIM5_CH2 40U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define GPDMA1_REQUEST_TIM5_CH3 41U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define GPDMA1_REQUEST_TIM5_CH4 42U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define GPDMA1_REQUEST_TIM5_UP 43U /*!< GPDMA1 HW request is TIM5_UP */ +#define GPDMA1_REQUEST_TIM5_TRIG 44U /*!< GPDMA1 HW request is TIM5_TRIG */ + +#define GPDMA1_REQUEST_TIM6_UP 45U /*!< GPDMA1 HW request is TIM6_UP */ +#define GPDMA1_REQUEST_TIM7_UP 46U /*!< GPDMA1 HW request is TIM6_UP */ + +#define GPDMA1_REQUEST_TIM8_CH1 47U /*!< GPDMA1 HW request is TIM8_CH1 */ +#define GPDMA1_REQUEST_TIM8_CH2 48U /*!< GPDMA1 HW request is TIM8_CH2 */ +#define GPDMA1_REQUEST_TIM8_CH3 49U /*!< GPDMA1 HW request is TIM8_CH3 */ +#define GPDMA1_REQUEST_TIM8_CH4 50U /*!< GPDMA1 HW request is TIM8_CH4 */ +#define GPDMA1_REQUEST_TIM8_UP 51U /*!< GPDMA1 HW request is TIM8_UP */ +#define GPDMA1_REQUEST_TIM8_TRIG 52U /*!< GPDMA1 HW request is TIM8_TRIG */ +#define GPDMA1_REQUEST_TIM8_COM 53U /*!< GPDMA1 HW request is TIM8_COM */ + +/* reserved 54U */ +/* reserved 55U */ + +#define GPDMA1_REQUEST_TIM15_CH1 56U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define GPDMA1_REQUEST_TIM15_CH2 57U /*!< GPDMA1 HW request is TIM15_CH2 */ +#define GPDMA1_REQUEST_TIM15_UP 58U /*!< GPDMA1 HW request is TIM15_UP */ +#define GPDMA1_REQUEST_TIM15_TRIG 59U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define GPDMA1_REQUEST_TIM15_COM 60U /*!< GPDMA1 HW request is TIM15_COM */ + +#define GPDMA1_REQUEST_TIM16_CH1 61U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define GPDMA1_REQUEST_TIM16_UP 62U /*!< GPDMA1 HW request is TIM16_UP */ +#define GPDMA1_REQUEST_TIM16_COM 63U /*!< GPDMA1 HW request is TIM16_COM */ + +#define GPDMA1_REQUEST_TIM17_CH1 64U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define GPDMA1_REQUEST_TIM17_UP 65U /*!< GPDMA1 HW request is TIM17_UP */ +#define GPDMA1_REQUEST_TIM17_COM 66U /*!< GPDMA1 HW request is TIM17_COM */ + +#define GPDMA1_REQUEST_TIM18_CH1 67U /*!< GPDMA1 HW request is TIM18_CH1 */ +#define GPDMA1_REQUEST_TIM18_UP 68U /*!< GPDMA1 HW request is TIM18_UP */ +#define GPDMA1_REQUEST_TIM18_COM 69U /*!< GPDMA1 HW request is TIM18_COM */ + +#define GPDMA1_REQUEST_LPTIM1_IC1 70U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define GPDMA1_REQUEST_LPTIM1_IC2 71U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define GPDMA1_REQUEST_LPTIM1_UE 72U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define GPDMA1_REQUEST_LPTIM2_IC1 73U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define GPDMA1_REQUEST_LPTIM2_IC2 74U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define GPDMA1_REQUEST_LPTIM2_UE 75U /*!< GPDMA1 HW request is LPTIM2_UE */ +#define GPDMA1_REQUEST_LPTIM3_IC1 76U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define GPDMA1_REQUEST_LPTIM3_IC2 77U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define GPDMA1_REQUEST_LPTIM3_UE 78U /*!< GPDMA1 HW request is LPTIM3_UE */ + +#define GPDMA1_REQUEST_SPI1_RX 79U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 80U /*!< GPDMA1 HW request is SPI1_TX */ +#define GPDMA1_REQUEST_SPI2_RX 81U /*!< GPDMA1 HW request is SPI2_RX */ +#define GPDMA1_REQUEST_SPI2_TX 82U /*!< GPDMA1 HW request is SPI2_TX */ +#define GPDMA1_REQUEST_SPI3_RX 83U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 84U /*!< GPDMA1 HW request is SPI3_TX */ +#define GPDMA1_REQUEST_SPI4_RX 85U /*!< GPDMA1 HW request is SPI4_RX */ +#define GPDMA1_REQUEST_SPI4_TX 86U /*!< GPDMA1 HW request is SPI4_TX */ +#define GPDMA1_REQUEST_SPI5_RX 87U /*!< GPDMA1 HW request is SPI5_RX */ +#define GPDMA1_REQUEST_SPI5_TX 88U /*!< GPDMA1 HW request is SPI5_TX */ +#define GPDMA1_REQUEST_SPI6_RX 89U /*!< GPDMA1 HW request is SPI6_RX */ +#define GPDMA1_REQUEST_SPI6_TX 90U /*!< GPDMA1 HW request is SPI6_TX */ + +#define GPDMA1_REQUEST_SAI1_A 91U /*!< GPDMA1 HW request is SAI1_A */ +#define GPDMA1_REQUEST_SAI1_B 92U /*!< GPDMA1 HW request is SAI1_B */ +#define GPDMA1_REQUEST_SAI2_A 93U /*!< GPDMA1 HW request is SAI2_A */ +#define GPDMA1_REQUEST_SAI2_B 94U /*!< GPDMA1 HW request is SAI2_B */ + +#define GPDMA1_REQUEST_I2C1_RX 95U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 96U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C2_RX 97U /*!< GPDMA1 HW request is I2C2_RX */ +#define GPDMA1_REQUEST_I2C2_TX 98U /*!< GPDMA1 HW request is I2C2_TX */ +#define GPDMA1_REQUEST_I2C3_RX 99U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 100U /*!< GPDMA1 HW request is I2C3_TX */ + +#define GPDMA1_REQUEST_I2C4_RX 101U /*!< GPDMA1 HW request is I2C4_RX */ +#define GPDMA1_REQUEST_I2C4_TX 102U /*!< GPDMA1 HW request is I2C4_TX */ + +#define GPDMA1_REQUEST_I3C1_RX 103U /*!< GPDMA1 HW request is I3C1_RX */ +#define GPDMA1_REQUEST_I3C1_TX 104U /*!< GPDMA1 HW request is I3C1_TX */ +#define GPDMA1_REQUEST_I3C2_RX 105U /*!< GPDMA1 HW request is I3C2_RX */ +#define GPDMA1_REQUEST_I3C2_TX 106U /*!< GPDMA1 HW request is I3C2_TX */ + +#define GPDMA1_REQUEST_USART1_RX 107U /*!< GPDMA1 HW request is USART1_RX */ +#define GPDMA1_REQUEST_USART1_TX 108U /*!< GPDMA1 HW request is USART1_TX */ +#define GPDMA1_REQUEST_USART2_RX 109U /*!< GPDMA1 HW request is USART2_RX */ +#define GPDMA1_REQUEST_USART2_TX 110U /*!< GPDMA1 HW request is USART2_TX */ +#define GPDMA1_REQUEST_USART3_RX 111U /*!< GPDMA1 HW request is USART3_RX */ +#define GPDMA1_REQUEST_USART3_TX 112U /*!< GPDMA1 HW request is USART3_TX */ +#define GPDMA1_REQUEST_UART4_RX 113U /*!< GPDMA1 HW request is UART4_RX */ +#define GPDMA1_REQUEST_UART4_TX 114U /*!< GPDMA1 HW request is UART4_TX */ +#define GPDMA1_REQUEST_UART5_RX 115U /*!< GPDMA1 HW request is UART5_RX */ +#define GPDMA1_REQUEST_UART5_TX 116U /*!< GPDMA1 HW request is UART5_TX */ +#define GPDMA1_REQUEST_USART6_RX 117U /*!< GPDMA1 HW request is USART6_RX */ +#define GPDMA1_REQUEST_USART6_TX 118U /*!< GPDMA1 HW request is USART6_TX */ +#define GPDMA1_REQUEST_UART7_RX 119U /*!< GPDMA1 HW request is UART7_RX */ +#define GPDMA1_REQUEST_UART7_TX 120U /*!< GPDMA1 HW request is UART7_TX */ +#define GPDMA1_REQUEST_UART8_RX 121U /*!< GPDMA1 HW request is UART8_RX */ +#define GPDMA1_REQUEST_UART8_TX 122U /*!< GPDMA1 HW request is UART8_TX */ +#define GPDMA1_REQUEST_UART9_RX 123U /*!< GPDMA1 HW request is UART9_RX */ +#define GPDMA1_REQUEST_UART9_TX 124U /*!< GPDMA1 HW request is UART9_TX */ +#define GPDMA1_REQUEST_USART10_RX 125U /*!< GPDMA1 HW request is USART10_RX */ +#define GPDMA1_REQUEST_USART10_TX 126U /*!< GPDMA1 HW request is USART10_TX */ + +#define GPDMA1_REQUEST_LPUART1_RX 127U /*!< GPDMA1 HW request is LPUART1_RX */ +#define GPDMA1_REQUEST_LPUART1_TX 128U /*!< GPDMA1 HW request is LPUART1_TX */ + +#define GPDMA1_REQUEST_SPDIFRX_CS 129U /*!< GPDMA1 HW request is SPDIFRX_CS */ +#define GPDMA1_REQUEST_SPDIFRX_DT 130U /*!< GPDMA1 HW request is SPDIFRX_DT */ + +#define GPDMA1_REQUEST_ADF1_FLT0 131U /*!< GPDMA1 HW request is ADF1_FLT0 */ + +#define GPDMA1_REQUEST_MDF1_FLT0 132U /*!< GPDMA1 HW request is MDF1_FLT0 */ +#define GPDMA1_REQUEST_MDF1_FLT1 133U /*!< GPDMA1 HW request is MDF1_FLT1 */ +#define GPDMA1_REQUEST_MDF1_FLT2 134U /*!< GPDMA1 HW request is MDF1_FLT2 */ +#define GPDMA1_REQUEST_MDF1_FLT3 135U /*!< GPDMA1 HW request is MDF1_FLT3 */ +#define GPDMA1_REQUEST_MDF1_FLT4 136U /*!< GPDMA1 HW request is MDF1_FLT4 */ +#define GPDMA1_REQUEST_MDF1_FLT5 137U /*!< GPDMA1 HW request is MDF1_FLT5 */ + +#define GPDMA1_REQUEST_UCPD1_TX 138U /*!< GPDMA1 HW request is UCPD1_TX */ +#define GPDMA1_REQUEST_UCPD1_RX 139U /*!< GPDMA1 HW request is UCPD1_RX */ + +#define GPDMA1_REQUEST_DCMI_PSSI 140U /*!< GPDMA1 HW request is DCMI_PSSI */ + +#define GPDMA1_REQUEST_I3C1_TC 141U /*!< GPDMA1 HW request is I3C1_TC */ +#define GPDMA1_REQUEST_I3C1_RS 142U /*!< GPDMA1 HW request is I3C1_RS */ + +#define GPDMA1_REQUEST_I3C2_TC 143U /*!< GPDMA1 HW request is I3C2_TC */ +#define GPDMA1_REQUEST_I3C2_RS 144U /*!< GPDMA1 HW request is I3C2_RS */ + +/* Software request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ + + +/** + * @} + */ + +/** @defgroup DMA_Block_Request DMA Block Request + * @brief DMA Block Request + * @{ + */ +#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ +#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Direction DMA Transfer Direction + * @brief DMA transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode + * @brief DMA Source Increment Mode + * @{ + */ +#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ +#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode + * @brief DMA Destination Increment Mode + * @{ + */ +#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ +#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Source_Data_Width DMA Source Data Width + * @brief DMA Source Data Width + * @{ + */ +#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ +#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ +#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ +#define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Data_Width DMA destination Data Width + * @brief DMA destination Data Width + * @{ + */ +#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ +#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ +#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ +#define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord */ + +/** + * @} + */ + +/** @defgroup DMA_Priority_Level DMA Priority Level + * @brief DMA Priority Level + * @{ + */ +#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ +#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ +#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ +#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port + * @brief DMA Transfer Allocated Port + * @{ + */ +#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ +#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ +#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ +#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode + * @brief DMA Transfer Event Mode + * @{ + */ +#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the + HT event is generated at the half of each block */ +#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block + and the HT event is generated at the half of the repeated + block */ +#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list + item and the HT event is generated at the half of each + linked-list item */ +#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last + linked-list item and the HT event is generated at the half + of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Mode DMA Transfer Mode + * @brief DMA Transfer Mode + * @{ + */ +#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ +#define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_ISOLATION_MODE DMA Channel isolation mode (CID filtering) + * @brief DMA Channel isolation enabling (CID filtering) + * @{ + */ +#define DMA_ISOLATION_OFF 0U /*!< DMA Channel isolation (CID filtering) is disabled */ +#define DMA_ISOLATION_ON 1U /*!< DMA Channel isolation (CID filtering) is enabled */ + +/** + * @} + */ + +/** @defgroup DMA_Channel_CID_Filtering_Static Static DMA Channel Filtering CID (isolation) + * @brief DMA Channel Filtering Static CID (isolation) + * @{ + */ +#define DMA_CHANNEL_STATIC_CID_0 (0U<State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) + +/** + * @brief Get the DMA channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update linked-list Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @arg DMA_FLAG_IDLEF : Idle flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CSR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update Linked-List Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt source to check. + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. + * @param __HANDLE__ : DMA handle. + * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ + MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) + +/** + * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. + * @param __HANDLE__ : DMA handle. + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) \ + (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) +/** + * @} + */ + + +/* Include DMA HAL Extension module */ +#include "stm32n6xx_hal_dma_ex.h" + + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions + * @brief I/O Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions + * @brief State and Error Functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions + * @brief DMA Attributes Functions + * @{ + */ + +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, + uint32_t ChannelAttributes); +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes); + +#if defined (CPU_IN_SECURE_STATE) +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); +#endif /* CPU_IN_SECURE_STATE */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pLockState); + + +#if defined (CPU_IN_SECURE_STATE) +HAL_StatusTypeDef HAL_DMA_SetIsolationAttributes(DMA_HandleTypeDef *const hdma, + DMA_IsolationConfigTypeDef const *const pConfig); +#endif /* CPU_IN_SECURE_STATE */ +HAL_StatusTypeDef HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const *const hdma, + DMA_IsolationConfigTypeDef *const pConfig); +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA Private Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ +#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ +#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ +#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ +#define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ +#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ +#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ +#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ +#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ +#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ +#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ +#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ +/** + * @} + */ + + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA Private Macros + * @{ + */ +#define GET_DMA_INSTANCE(__HANDLE__) \ + ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) + +#define GET_DMA_CHANNEL(__HANDLE__) \ + ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) + +#define IS_DMA_MODE(MODE) \ + (((MODE) == DMA_NORMAL) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_DIRECTION(DIRECTION) \ + (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_LEVEL_COMPLETE(LEVEL) \ + (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ + ((LEVEL) == HAL_DMA_HALF_TRANSFER)) + +#define IS_DMA_SOURCE_INC(INC) \ + (((INC) == DMA_SINC_FIXED) || \ + ((INC) == DMA_SINC_INCREMENTED)) + +#define IS_DMA_DESTINATION_INC(INC) \ + (((INC) == DMA_DINC_FIXED) || \ + ((INC) == DMA_DINC_INCREMENTED)) + +#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_WORD) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_DOUBLEWORD)) + +#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_WORD) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_DOUBLEWORD)) + +#define IS_DMA_BURST_LENGTH(LENGTH) \ + (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ + ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) + +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ + ((PRIORITY) == DMA_HIGH_PRIORITY)) + +#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ + (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) + +#define IS_DMA_REQUEST(REQUEST) \ + (((REQUEST) == DMA_REQUEST_SW) || \ + ((REQUEST) <= HPDMA1_REQUEST_I3C2_RS)) + +#define IS_DMA_BLOCK_HW_REQUEST(MODE) \ + (((MODE) == DMA_BREQ_SINGLE_BURST) || \ + ((MODE) == DMA_BREQ_BLOCK)) + +#define IS_DMA_TCEM_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_BLOCK_SIZE(SIZE) \ + (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) + +#if defined (CPU_IN_SECURE_STATE) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ + (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ + (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) +#else +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ + ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) +#endif /* CPU_IN_SECURE_STATE */ + +#if defined (CPU_IN_SECURE_STATE) +#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->SMISR & (GLOBAL_FLAG))) +#endif /* CPU_IN_SECURE_STATE */ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->MISR & (GLOBAL_FLAG))) + +#define IS_DMA_ISOLATION_MODE(MODE) \ + (((MODE) == DMA_ISOLATION_OFF) || \ + ((MODE) == DMA_ISOLATION_ON)) + +#define IS_DMA_ISOLATION_STATIC_CID(ID) \ + (((ID) == DMA_CHANNEL_STATIC_CID_0) || \ + ((ID) == DMA_CHANNEL_STATIC_CID_1) || \ + ((ID) == DMA_CHANNEL_STATIC_CID_2) || \ + ((ID) == DMA_CHANNEL_STATIC_CID_3) || \ + ((ID) == DMA_CHANNEL_STATIC_CID_4) || \ + ((ID) == DMA_CHANNEL_STATIC_CID_5) || \ + ((ID) == DMA_CHANNEL_STATIC_CID_6)) + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_DMA_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma_ex.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma_ex.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma_ex.h (revision 16) @@ -0,0 +1,876 @@ +/** + ********************************************************************************************************************** + * @file stm32n6xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32N6xx_HAL_DMA_EX_H +#define STM32N6xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief DMAEx Data Handling Configuration Structure Definition. + */ +typedef struct +{ + uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. + This parameter can be a value of @ref DMAEx_Data_Exchange */ + + uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode + This parameter can be a value of @ref DMAEx_Data_Alignment */ + +} DMA_DataHandlingConfTypeDef; + +/** + * @brief DMAEx Trigger Configuration Structure Definition. + */ +typedef struct +{ + uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. + This parameter can be a value of @ref DMAEx_Trigger_Mode */ + + uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. + This parameter can be a value of @ref DMAEx_Trigger_Polarity */ + + uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. + This parameter can be a value of @ref DMAEx_Trigger_Selection */ + +} DMA_TriggerConfTypeDef; + +/** + * @brief DMAEx Repeated Block Configuration Structure Definition. + */ +typedef struct +{ + uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). + This parameter can be a value between 1 and 2048 */ + + int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : + This parameter can be a value between -8191 and 8191. + * If source address offset > 0 => Increment the source address by offset from where + the last single/burst transfer ends. + * If source address offset < 0 => Decrement the source address by offset from where + the last single/burst transfer ends. + * If source address offset == 0 => The next single/burst source address starts from + where the last transfer ends */ + + int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : + This parameter can be a value between -8191 and 8191. + * If destination address offset > 0 => Increment the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset < 0 => Decrement the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset == 0 => The next single/burst destination address + starts from where the last transfer ends. */ + + int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block source address offset > 0 => Increment the block source address by offset + from where the last block ends. + * If block source address offset < 0 => Decrement the next block source address by + offset from where the last block ends. + * If block source address offset == 0 => the next block source address starts from + where the last block ends */ + + int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block destination address offset > 0 => Increment the block destination address + by offset from where the last block ends. + * If block destination address offset < 0 => Decrement the next block destination + address by offset from where the last block ends. + * If block destination address offset == 0 => the next block destination address + starts from where the last block ends */ + +} DMA_RepeatBlockConfTypeDef; + +/** + * @brief DMAEx Queue State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ + HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ + HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ + +} HAL_DMA_QStateTypeDef; + +/** + * @brief DMAEx Linked-List Node Configuration Structure Definition. + */ +typedef struct +{ + uint32_t NodeType; /*!< Specifies the DMA channel node type. + This parameter can be a value of @ref DMAEx_Node_Type */ + + DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ + + DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ + + DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ + + DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ + + uint32_t SrcAddress; /*!< Specifies the source memory address */ + uint32_t DstAddress; /*!< Specifies the destination memory address */ + uint32_t DataSize; /*!< Specifies the source data size in bytes */ + +#if defined (CPU_IN_SECURE_STATE) + uint32_t SrcSecure; /*!< Specifies the source security attribute */ + uint32_t DestSecure; /*!< Specifies the destination security attribute */ +#endif /* CPU_IN_SECURE_STATE */ + +} DMA_NodeConfTypeDef; + +/** + * @brief DMAEx Linked-List Node Structure Definition. + */ +typedef struct +{ + uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ + uint32_t NodeInfo; /*!< Node information */ + +} DMA_NodeTypeDef; + +/** + * @brief DMAEx Linked-List Queue Structure Definition. + */ +typedef struct __DMA_QListTypeDef +{ + DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ + + DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ + + uint32_t NodeNumber; /*!< Specifies the queue node number */ + + __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ + + __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ + + __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ + +} DMA_QListTypeDef; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @brief DMAEx Exported Constants + * @{ + */ + +/** @defgroup Queue_Error_Codes Queue Error Codes + * @brief Queue Error Codes + * @{ + */ +#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ +#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ +#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ +#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization + and queue circular types are incompatible */ +#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ +#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ +/** + * @} + */ + +/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode + * @brief DMAEx LinkedList Mode + * @{ + */ +#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ +#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment + * @brief DMAEx Data Alignment + * @{ + */ +#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width + => Right aligned padded with 0 up to destination data + width */ +#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width + => Right aligned left Truncated down to destination + data width */ +#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width + => Right Aligned padded with sign extended up to + destination data width */ +#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width + => Left Aligned Right Truncated down to the + destination data width */ +#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width + => Packed at the destination data width */ +#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange + * @brief DMAEx Data Exchange + * @{ + */ +#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ +#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ +#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ +#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ +#define DMA_EXCHANGE_DEST_WORD DMA_CTR1_DWX /*!< Destination Word exchange when destination data width is > Word */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity + * @brief DMAEx Trigger Polarity + * @{ + */ +#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ +#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ +#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode + * @brief DMAEx Trigger Mode + * @{ + */ +#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection + * @brief DMAEx Trigger Selection + * @{ + */ +/* HPDMA1 triggers */ +#define HPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_FEND */ +#define HPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_LEND */ +#define HPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */ +#define HPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */ + +#define HPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_FEND */ +#define HPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_LEND */ +#define HPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */ +#define HPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */ + +#define HPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_FEND */ +#define HPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_LEND */ +#define HPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */ +#define HPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */ + +#define HPDMA1_TRIGGER_DMA2D_CTC 12U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC */ +#define HPDMA1_TRIGGER_DMA2D_TC 13U /*!< HPDMA1 HW Trigger signal is DMA2D_TC */ +#define HPDMA1_TRIGGER_DMA2D_TW 14U /*!< HPDMA1 HW Trigger signal is DMA2D_TW */ + +#define HPDMA1_TRIGGER_JPEG_EOC 15U /*!< HPDMA1 HW Trigger signal is JPEG_EOC */ +#define HPDMA1_TRIGGER_JPEG_IFNF 16U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF */ +#define HPDMA1_TRIGGER_JPEG_IFT 17U /*!< HPDMA1 HW Trigger signal is JPEG_IFT */ +#define HPDMA1_TRIGGER_JPEG_OFNE 18U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE */ +#define HPDMA1_TRIGGER_JPEG_OFT 19U /*!< HPDMA1 HW Trigger signal is JPEG_OFT */ + +#define HPDMA1_LCD_LI 20U /*!< HPDMA1 HW Trigger signal is LCD_LI */ + +#define HPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_0 */ +#define HPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_1 */ +#define HPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_2 */ +#define HPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_3 */ + +#define HPDMA1_TRIGGER_GFXTIM_3 25U /*!< HPDMA1 HW Trigger signal is GFXTIM_3 */ +#define HPDMA1_TRIGGER_GFXTIM_2 26U /*!< HPDMA1 HW Trigger signal is GFXTIM_2 */ +#define HPDMA1_TRIGGER_GFXTIM_1 27U /*!< HPDMA1 HW Trigger signal is GFXTIM_1 */ +#define HPDMA1_TRIGGER_GFXTIM_0 28U /*!< HPDMA1 HW Trigger signal is GFXTIM_0 */ + +/* reserved 29U */ + +#define HPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define HPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define HPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define HPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define HPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define HPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#define HPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< HPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define HPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< HPDMA1 HW Trigger signal is LPTIM5_OUT */ + +/* reserved 38U */ + +#define HPDMA1_TRIGGER_RTC_WKUP 39U /*!< HPDMA1 HW Trigger signal is RTC_WKUP */ + +#define HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< HPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */ +#define HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< HPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */ + +#define HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< HPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */ + +/* reserved 43U */ + +#define HPDMA1_TRIGGER_TIM1_TRGO 44U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO */ +#define HPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO2 */ +#define HPDMA1_TRIGGER_TIM2_TRGO 46U /*!< HPDMA1 HW Trigger signal is TIM2_TRGO */ +#define HPDMA1_TRIGGER_TIM3_TRGO 47U /*!< HPDMA1 HW Trigger signal is TIM3_TRGO */ +#define HPDMA1_TRIGGER_TIM4_TRGO 48U /*!< HPDMA1 HW Trigger signal is TIM4_TRGO */ +#define HPDMA1_TRIGGER_TIM5_TRGO 49U /*!< HPDMA1 HW Trigger signal is TIM5_TRGO */ +#define HPDMA1_TRIGGER_TIM6_TRGO 50U /*!< HPDMA1 HW Trigger signal is TIM6_TRGO */ +#define HPDMA1_TRIGGER_TIM7_TRGO 51U /*!< HPDMA1 HW Trigger signal is TIM7_TRGO */ +#define HPDMA1_TRIGGER_TIM8_TRGO 52U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO */ +#define HPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO2 */ + +/* reserved 54U */ +/* reserved 55U */ +/* reserved 56U */ + +#define HPDMA1_TRIGGER_TIM12_TRGO 57U /*!< HPDMA1 HW Trigger signal is TIM12_TRGO */ +#define HPDMA1_TRIGGER_TIM15_TRGO 58U /*!< HPDMA1 HW Trigger signal is TIM15_TRGO */ + +/* reserved 59U */ + +#define HPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ + +#define HPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ + +/* reserved 92U */ + +#define HPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< HPDMA1 HW Trigger signal is EXTIT0_SYNC */ +#define HPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< HPDMA1 HW Trigger signal is EXTIT1_SYNC */ +#define HPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< HPDMA1 HW Trigger signal is EXTIT2_SYNC */ +#define HPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< HPDMA1 HW Trigger signal is EXTIT3_SYNC */ +#define HPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< HPDMA1 HW Trigger signal is EXTIT4_SYNC */ +#define HPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< HPDMA1 HW Trigger signal is EXTIT5_SYNC */ +#define HPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< HPDMA1 HW Trigger signal is EXTIT6_SYNC */ +#define HPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< HPDMA1 HW Trigger signal is EXTIT7_SYNC */ +#define HPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< HPDMA1 HW Trigger signal is EXTIT8_SYNC */ +#define HPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< HPDMA1 HW Trigger signal is EXTIT9_SYNC */ +#define HPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< HPDMA1 HW Trigger signal is EXTIT10_SYNC */ +#define HPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< HPDMA1 HW Trigger signal is EXTIT11_SYNC */ +#define HPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< HPDMA1 HW Trigger signal is EXTIT12_SYNC */ +#define HPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< HPDMA1 HW Trigger signal is EXTIT13_SYNC */ +#define HPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< HPDMA1 HW Trigger signal is EXTIT14_SYNC */ +#define HPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< HPDMA1 HW Trigger signal is EXTIT15_SYNC */ + + +/* GPDMA1 triggers */ +#define GPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_FEND */ +#define GPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_LEND */ +#define GPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */ +#define GPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */ + +#define GPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_FEND */ +#define GPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_LEND */ +#define GPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */ +#define GPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */ + +#define GPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_FEND */ +#define GPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_LEND */ +#define GPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */ +#define GPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */ + +#define GPDMA1_TRIGGER_DMA2D_CTC 12U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define GPDMA1_TRIGGER_DMA2D_TC 13U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define GPDMA1_TRIGGER_DMA2D_TW 14U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ + +#define GPDMA1_TRIGGER_JPEG_EOC 15U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define GPDMA1_TRIGGER_JPEG_IFNF 16U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define GPDMA1_TRIGGER_JPEG_IFT 17U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define GPDMA1_TRIGGER_JPEG_OFNE 18U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define GPDMA1_TRIGGER_JPEG_OFT 19U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ + +#define GPDMA1_LCD_LI 20U /*!< GPDMA1 HW Trigger signal is LCD_LI */ + +#define GPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_0 */ +#define GPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_1 */ +#define GPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_2 */ +#define GPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_3 */ + +#define GPDMA1_TRIGGER_GFXTIM_3 25U /*!< GPDMA1 HW Trigger signal is GFXTIM_3 */ +#define GPDMA1_TRIGGER_GFXTIM_2 26U /*!< GPDMA1 HW Trigger signal is GFXTIM_2 */ +#define GPDMA1_TRIGGER_GFXTIM_1 27U /*!< GPDMA1 HW Trigger signal is GFXTIM_1 */ +#define GPDMA1_TRIGGER_GFXTIM_0 28U /*!< GPDMA1 HW Trigger signal is GFXTIM_0 */ + +/* reserved 29U */ + +#define GPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define GPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define GPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define GPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#define GPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define GPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */ + +/* reserved 38U */ + +#define GPDMA1_TRIGGER_RTC_WKUP 39U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */ + +#define GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< GPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */ +#define GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< GPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */ + +#define GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< GPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */ + +/* reserved 43U */ + +#define GPDMA1_TRIGGER_TIM1_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */ +#define GPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */ +#define GPDMA1_TRIGGER_TIM2_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define GPDMA1_TRIGGER_TIM3_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#define GPDMA1_TRIGGER_TIM4_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#define GPDMA1_TRIGGER_TIM5_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#define GPDMA1_TRIGGER_TIM6_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */ +#define GPDMA1_TRIGGER_TIM7_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */ +#define GPDMA1_TRIGGER_TIM8_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO */ +#define GPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO2 */ + +/* reserved 54U */ +/* reserved 55U */ +/* reserved 56U */ + +#define GPDMA1_TRIGGER_TIM12_TRGO 57U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ +#define GPDMA1_TRIGGER_TIM15_TRGO 58U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ + +/* reserved 59U */ + +#define GPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ + +#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ + +/* reserved 92U */ + +#define GPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */ +#define GPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< GPDMA1 HW Trigger signal is EXTIT1_SYNC */ +#define GPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< GPDMA1 HW Trigger signal is EXTIT2_SYNC */ +#define GPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< GPDMA1 HW Trigger signal is EXTIT3_SYNC */ +#define GPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< GPDMA1 HW Trigger signal is EXTIT4_SYNC */ +#define GPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< GPDMA1 HW Trigger signal is EXTIT5_SYNC */ +#define GPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< GPDMA1 HW Trigger signal is EXTIT6_SYNC */ +#define GPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< GPDMA1 HW Trigger signal is EXTIT7_SYNC */ +#define GPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< GPDMA1 HW Trigger signal is EXTIT8_SYNC */ +#define GPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< GPDMA1 HW Trigger signal is EXTIT9_SYNC */ +#define GPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< GPDMA1 HW Trigger signal is EXTIT10_SYNC */ +#define GPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< GPDMA1 HW Trigger signal is EXTIT11_SYNC */ +#define GPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< GPDMA1 HW Trigger signal is EXTIT12_SYNC */ +#define GPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< GPDMA1 HW Trigger signal is EXTIT13_SYNC */ +#define GPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< GPDMA1 HW Trigger signal is EXTIT14_SYNC */ +#define GPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< GPDMA1 HW Trigger signal is EXTIT15_SYNC */ +/** + * @} + */ + +/** @defgroup DMAEx_Node_Type DMAEx Node Type + * @brief DMAEx Node Type + * @{ + */ +#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ +#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ +#define DMA_HPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the HPDMA linear addressing node type */ +#define DMA_HPDMA_2D_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the HPDMA 2 dimension addressing node type */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port + * @brief DMAEx Linked-List Allocated Port + * @{ + */ +#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ +#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode + * @brief DMAEx Link Step Mode + * @{ + */ +#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ +#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions + * @brief Linked-List Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions + * @brief Linked-List IO Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions + * @brief Linked-List Management Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); + +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode); +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions + * @brief Data Handling, Repeated Block and Trigger Configuration Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger); +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions + * @brief Suspend and Resume Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function + * @brief FIFO Status Function + * @{ + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Types DMAEx Private Types + * @brief DMAEx Private Types + * @{ + */ + +/** + * @brief DMA Node in Queue Information Structure Definition. + */ +typedef struct +{ + uint32_t cllr_offset; /* CLLR register offset */ + + uint32_t previousnode_addr; /* Previous node address */ + + uint32_t currentnode_pos; /* Current node position */ + + uint32_t currentnode_addr; /* Current node address */ + + uint32_t nextnode_addr; /* Next node address */ + +} DMA_NodeInQInfoTypeDef; +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Constants DMAEx Private Constants + * @brief DMAEx Private Constants + * @{ + */ +#define DMA_LINKEDLIST (0x0080UL) /* DMA channel linked-list mode */ + +#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001UL) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002UL) /* DMA channel 2D addressing mode */ +#define DMA_CHANNEL_TYPE_GPDMA (0x0020UL) /* GPDMA channel node */ +#define DMA_CHANNEL_TYPE_HPDMA (0x0040UL) /* HPDMA channel node */ + +#define NODE_TYPE_MASK (0x00FFUL) /* DMA channel node type */ +#define NODE_CLLR_IDX (0x0700UL) /* DMA channel node CLLR index mask */ +#define NODE_CLLR_IDX_POS (0x0008UL) /* DMA channel node CLLR index position */ + +#define NODE_MAXIMUM_SIZE (0x0008UL) /* Amount of registers of the node */ + +#define NODE_STATIC_FORMAT (0x0000UL) /* DMA channel node static format */ +#define NODE_DYNAMIC_FORMAT (0x0001UL) /* DMA channel node dynamic format */ + +#define UPDATE_CLLR_POSITION (0x0000UL) /* DMA channel update CLLR position */ +#define UPDATE_CLLR_VALUE (0x0001UL) /* DMA channel update CLLR value */ + +#define LASTNODE_ISNOT_CIRCULAR (0x0000UL) /* Last node is not first circular node */ +#define LASTNODE_IS_CIRCULAR (0x0001UL) /* Last node is first circular node */ + +#define QUEUE_TYPE_STATIC (0x0000UL) /* DMA channel static queue */ +#define QUEUE_TYPE_DYNAMIC (0x0001UL) /* DMA channel dynamic queue */ + +#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */ +#define NODE_CTR3_DEFAULT_OFFSET (0x0005UL) /* CTR3 2D addressing default offset */ +#define NODE_CBR2_DEFAULT_OFFSET (0x0006UL) /* CBR2 2D addressing default offset */ +#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */ + +#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ +#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx Private Macros + * @{ + */ +#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ + (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ + ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ + ((ALIGNMENT) == DMA_DATA_PACK)) + +#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ + (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD | \ + DMA_EXCHANGE_DEST_WORD))) == 0U) + +#define IS_DMA_REPEAT_COUNT(COUNT) \ + (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) + +#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ + (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ + ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) + +#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ + (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ + ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) + +#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ + (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) + +#define IS_DMA_LINK_STEP_MODE(MODE) \ + (((MODE) == DMA_LSM_FULL_EXECUTION) || \ + ((MODE) == DMA_LSM_1LINK_EXECUTION)) + +#define IS_DMA_TRIGGER_MODE(MODE) \ + (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) + +#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_LINKEDLIST_MODE(MODE) \ + (((MODE) == DMA_LINKEDLIST_NORMAL) || \ + ((MODE) == DMA_LINKEDLIST_CIRCULAR)) + +#define IS_DMA_TRIGGER_POLARITY(POLARITY) \ + (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ + ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ + ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) + +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ + ((TRIGGER) <= HPDMA1_TRIGGER_EXTIT15_SYNC) + +#define IS_DMA_NODE_TYPE(TYPE) \ + (((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ + ((TYPE) == DMA_GPDMA_2D_NODE) || \ + ((TYPE) == DMA_HPDMA_LINEAR_NODE) || \ + ((TYPE) == DMA_HPDMA_2D_NODE)) +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32N6xx_HAL_DMA_EX_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_exti.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_exti.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_exti.h (revision 16) @@ -0,0 +1,413 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_exti.h + * @author GPM Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_EXTI_H +#define STM32N6xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* RisingCallback)(void); /*!< Exti rising callback */ + void (* FallingCallback)(void); /*!< Exti falling callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00U) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01U) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02U) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03U) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04U) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05U) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06U) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07U) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08U) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09U) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0AU) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0BU) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0CU) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0DU) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0EU) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0FU) +#define EXTI_LINE_16 (EXTI_RESERVED | EXTI_REG1 | 0x10U) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11U) +#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x12U) +#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x13U) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14U) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15U) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x16U) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17U) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18U) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19U) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1AU) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1BU) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1CU) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1DU) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1EU) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1FU) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00U) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01U) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02U) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x03U) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x04U) +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x05U) +#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x06U) +#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x07U) +#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x08U) +#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x09U) +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0AU) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0BU) +#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0CU) +#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0DU) +#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0EU) +#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0FU) +#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x10U) +#define EXTI_LINE_49 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x11U) +#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x12U) +#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x13U) +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x14U) +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x15U) +#define EXTI_LINE_54 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x16U) +#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x17U) +#define EXTI_LINE_56 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x18U) +#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x19U) +#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1AU) +#define EXTI_LINE_59 (EXTI_RESERVED | EXTI_REG2 | 0x1BU) +#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1CU) +#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1DU) +#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1EU) +#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1FU) +#define EXTI_LINE_64 (EXTI_DIRECT | EXTI_REG3 | EXTI_EVENT | 0x00U) +#define EXTI_LINE_65 (EXTI_DIRECT | EXTI_REG3 | EXTI_EVENT | 0x01U) +#define EXTI_LINE_66 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x02U) +#define EXTI_LINE_67 (EXTI_RESERVED | EXTI_REG3 | 0x03U) +#define EXTI_LINE_68 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x04U) +#define EXTI_LINE_69 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x05U) +#define EXTI_LINE_70 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x06U) +#define EXTI_LINE_71 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x07U) +#define EXTI_LINE_72 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x08U) +#define EXTI_LINE_73 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x09U) +#define EXTI_LINE_74 (EXTI_CONFIG | EXTI_REG3 | EXTI_EVENT | 0x0AU) +#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_REG3 | 0x0BU) +#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_REG3 | 0x0CU) +#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_REG3 | EXTI_EVENT | 0x0DU) + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOD 0x00000003U +#define EXTI_GPIOE 0x00000004U +#define EXTI_GPIOF 0x00000005U +#define EXTI_GPIOG 0x00000006U +#define EXTI_GPIOH 0x00000007U +#define EXTI_GPION 0x00000008U +#define EXTI_GPIOO 0x00000009U +#define EXTI_GPIOP 0x0000000AU +#define EXTI_GPIOQ 0x0000000BU +/** + * @} + */ + +/** @defgroup EXTI_Line_attributes EXTI line attributes + * @brief EXTI line secure or non-secure and privileged or non-privileged attributes + * @note secure and non-secure attributes are only available from secure state + * @{ + */ +#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U) /*!< Secure line attribute */ +#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure line attribute */ +#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U) /*!< Privileged line attribute */ +#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privileged line attribute */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28UL +#define EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) + +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24UL +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16UL +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) +#define EXTI_REG3 (0x02UL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) +#define EXTI_PIN_MASK 0x0000001FU + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 78U + + +/** + * @brief EXTI Mask for secure & privilege attributes + */ +#define EXTI_LINE_ATTR_SEC_MASK 0x100U +#define EXTI_LINE_ATTR_PRIV_MASK 0x200U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + ((((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))) || \ + (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x0002000DUL))) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) + +#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \ + ((__LINE__) == EXTI_TRIGGER_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPION) || \ + ((__PORT__) == EXTI_GPIOO) || \ + ((__PORT__) == EXTI_GPIOP) || \ + ((__PORT__) == EXTI_GPIOQ)) + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) + +#if defined CPU_IN_SECURE_STATE +#define IS_EXTI_LINE_ATTRIBUTES(__ATTR__) (((((__ATTR__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \ + (((__ATTR__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \ + (((__ATTR__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTR__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTR__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U)) +#else +#define IS_EXTI_LINE_ATTRIBUTES(__ATTR__) (((((__ATTR__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTR__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTR__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U)) +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @{ + */ + + +/* EXTI line attributes management functions **********************************/ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes); +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes); +#if defined CPU_IN_SECURE_STATE +void HAL_EXTI_LockAttributes(void); +uint32_t HAL_EXTI_GetLockAttributes(void); +#endif /* CPU_IN_SECURE_STATE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_EXTI_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio.h (revision 16) @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_gpio.h + * @author GPM Application Team + * @brief Header for gpio.c module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_GPIO_H +#define STM32N6xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO delay parameters structure definition + */ +typedef struct +{ + uint32_t Delay; /*!< Specifies the delay to apply on signal of a pin. + This parameter can be a value of @ref GPIO_delay */ + + uint32_t Path; /*!< Specifies the path of the delay. + This parameter can be a value of @ref GPIO_path */ +} GPIO_DelayTypeDef; + +/** + * @brief GPIO retime parameters structure definition + */ +typedef struct +{ + uint32_t Retime; /*!< Enable or disable the retime functionality on a pin + This parameter can be any value of @ref GPIO_retime */ + + uint32_t Edge; /*!< Specifies the clock edge for retime functionality. + This parameter can be a value of @ref GPIO_clock */ +} GPIO_RetimeTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +/** + * @} + */ + +/** @defgroup GPIO_retime GPIO retime control + * @brief GPIO data retime enable/disable + * @{ + */ +#define GPIO_RETIME_OFF 0x00000000u /*!< Retime disable at pad level */ +#define GPIO_RETIME_ON GPIO_ADVCFGRL_RET0 /*!< Retime enable at pad level */ +/** + * @} + */ + +/** @defgroup GPIO_clock GPIO clock control + * @brief GPIO clock edge configuration for retime functionality + * @{ + */ +#define GPIO_CLOCK_RISING 0x00000000u /*!< Retime on rising edge */ +#define GPIO_CLOCK_FALLING GPIO_ADVCFGRL_INVCLK0 /*!< Retime on falling edge */ +#define GPIO_CLOCK_RISING_FALLING GPIO_ADVCFGRL_DE0 /*!< Retime on both edge */ +/** + * @} + */ + +/** @defgroup GPIO_path GPIO path control + * @brief GPIO path configuration for delay functionality + * @{ + */ +#define GPIO_PATH_OUT 0x00000000u /*!< Delay applied to output signal */ +#define GPIO_PATH_IN GPIO_ADVCFGRL_DLYPATH0 /*!< Delay applied to input signal */ +/** + * @} + */ + +/** @defgroup GPIO_delay GPIO delay + * @brief GPIO delay in picosecond to apply on the input/output path depending the value of control GPIO_path + * @{ + */ +#define GPIO_DELAY_PS_0 (GPIO_DELAYRL_DLY0_Pos) +#define GPIO_DELAY_PS_300 (GPIO_DELAYRL_DLY0_0) +#define GPIO_DELAY_PS_500 (GPIO_DELAYRL_DLY0_1) +#define GPIO_DELAY_PS_750 (GPIO_DELAYRL_DLY0_1 | GPIO_DELAYRL_DLY0_0) +#define GPIO_DELAY_PS_1000 (GPIO_DELAYRL_DLY0_2) +#define GPIO_DELAY_PS_1250 (GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_0) +#define GPIO_DELAY_PS_1500 (GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_1) +#define GPIO_DELAY_PS_1750 (GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_1 | GPIO_DELAYRL_DLY0_0) +#define GPIO_DELAY_PS_2000 (GPIO_DELAYRL_DLY0_3) +#define GPIO_DELAY_PS_2250 (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_0) +#define GPIO_DELAY_PS_2500 (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_1) +#define GPIO_DELAY_PS_2750 (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_1 | GPIO_DELAYRL_DLY0_0) +#define GPIO_DELAY_PS_3000 (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_2) +#define GPIO_DELAY_PS_3250 (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_0) +/** + * @} + */ + +/** @defgroup GPIO_attributes GPIO attributes + * @brief GPIO pin secure/non-secure or/and privileged/non-privileged + * @{ + */ +#define GPIO_PIN_SEC (GPIO_PIN_ATTR_SEC_MASK | 0x00000001U) /*!< Secure pin attribute */ +#define GPIO_PIN_NSEC (GPIO_PIN_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure pin attribute */ +#define GPIO_PIN_PRIV (GPIO_PIN_ATTR_PRIV_MASK | 0x00000002U) /*!< Privileged pin attribute */ +#define GPIO_PIN_NPRIV (GPIO_PIN_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privileged pin attribute */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line is rising edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line rising pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is falling edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line falling pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ + __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ + do { \ + __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ + } while(0) + + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) + +/** + * @brief Clear the EXTI line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +#define GPIO_PIN_ATTR_SEC_MASK 0x100U +#define GPIO_PIN_ATTR_PRIV_MASK 0x200U +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) + +#define IS_GPIO_DELAY(__DELAY__) (((__DELAY__) == GPIO_DELAY_PS_0) ||\ + ((__DELAY__) == GPIO_DELAY_PS_300) ||\ + ((__DELAY__) == GPIO_DELAY_PS_500) ||\ + ((__DELAY__) == GPIO_DELAY_PS_750) ||\ + ((__DELAY__) == GPIO_DELAY_PS_1000) ||\ + ((__DELAY__) == GPIO_DELAY_PS_1250) ||\ + ((__DELAY__) == GPIO_DELAY_PS_1500) ||\ + ((__DELAY__) == GPIO_DELAY_PS_1750) ||\ + ((__DELAY__) == GPIO_DELAY_PS_2000) ||\ + ((__DELAY__) == GPIO_DELAY_PS_2250) ||\ + ((__DELAY__) == GPIO_DELAY_PS_2500) ||\ + ((__DELAY__) == GPIO_DELAY_PS_2750) ||\ + ((__DELAY__) == GPIO_DELAY_PS_3000) ||\ + ((__DELAY__) == GPIO_DELAY_PS_3250)) + +#define IS_GPIO_RETIME(__RETIME__) (((__RETIME__) == GPIO_RETIME_ON) ||\ + ((__RETIME__) == GPIO_RETIME_OFF)) + +#define IS_GPIO_CLOCK(__CLOCK__) (((__CLOCK__) == GPIO_CLOCK_RISING) ||\ + ((__CLOCK__) == GPIO_CLOCK_FALLING) || \ + ((__CLOCK__) == GPIO_CLOCK_RISING_FALLING)) + +#define IS_GPIO_PATH(__PATH__) (((__PATH__) == GPIO_PATH_OUT) ||\ + ((__PATH__) == GPIO_PATH_IN)) + +#if defined CPU_IN_SECURE_STATE +#define IS_GPIO_PIN_ATTRIBUTES(__ATTR__) (((((__ATTR__) & GPIO_PIN_SEC) == GPIO_PIN_SEC) || \ + (((__ATTR__) & GPIO_PIN_NSEC) == GPIO_PIN_NSEC) || \ + (((__ATTR__) & GPIO_PIN_PRIV) == GPIO_PIN_PRIV) || \ + (((__ATTR__) & GPIO_PIN_NPRIV) == GPIO_PIN_NPRIV)) && \ + (((__ATTR__) & ~(GPIO_PIN_SEC|GPIO_PIN_NSEC|GPIO_PIN_PRIV|GPIO_PIN_NPRIV)) == 0U)) +#else +#define IS_GPIO_PIN_ATTRIBUTES(__ATTR__) (((((__ATTR__) & GPIO_PIN_PRIV) == GPIO_PIN_PRIV) || \ + (((__ATTR__) & GPIO_PIN_NPRIV) == GPIO_PIN_NPRIV)) && \ + (((__ATTR__) & ~(GPIO_PIN_PRIV | GPIO_PIN_NPRIV)) == 0U)) +#endif /* CPU_IN_SECURE_STATE */ +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32n6xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_SetRetime(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_RetimeTypeDef *pRet_Init); +HAL_StatusTypeDef HAL_GPIO_GetRetime(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_RetimeTypeDef *pRet_Init); +void HAL_GPIO_SetDelay(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_DelayTypeDef *pDly_Init); +HAL_StatusTypeDef HAL_GPIO_GetDelay(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_DelayTypeDef *pDly_Init); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +#if defined CPU_IN_SECURE_STATE + +/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @{ + */ + +/* IO attributes management functions *****************************************/ +void HAL_GPIO_LockPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint32_t HAL_GPIO_GetLockPinAttributes(const GPIO_TypeDef *GPIOx); +#endif /* CPU_IN_SECURE_STATE */ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_GPIO_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio_ex.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio_ex.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio_ex.h (revision 16) @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_gpio_ex.h + * @author GPM Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_GPIO_EX_H +#define STM32N6xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_RTC ((uint8_t)0x00) /*!< RTC Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_SYS ((uint8_t)0x00) /*!< BOOT1 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM5 ((uint8_t)0x01) /*!< LPTIM5 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF2_I3C2 ((uint8_t)0x02) /*!< I3C2 Alternate Function mapping */ +#define GPIO_AF2_SAI1 ((uint8_t)0x02) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM8 ((uint8_t)0x02) /*!< TIM8 Alternate Function mapping */ +#define GPIO_AF2_TIM12 ((uint8_t)0x02) /*!< TIM12 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_ADF1 ((uint8_t)0x03) /*!< ADF1 Alternate Function mapping */ +#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /*!< LPTIM3 Alternate Function mapping */ +#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /*!< LPTIM4 Alternate Function mapping */ +#define GPIO_AF3_LPUART1 ((uint8_t)0x03) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ +#define GPIO_AF3_USART3 ((uint8_t)0x03) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /*!< I2C4 Alternate Function mapping */ +#define GPIO_AF4_I3C1 ((uint8_t)0x04) /*!< I3C1 Alternate Function mapping */ +#define GPIO_AF4_MDF1 ((uint8_t)0x04) /*!< MDF1 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< UASRT1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_I3C1 ((uint8_t)0x05) /*!< I3C1 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /*!< SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /*!< SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /*!< SPI6 Alternate Function mapping */ +#define GPIO_AF5_SYS ((uint8_t)0x05) /*!< AUDIOCLK Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_FDCAN1 ((uint8_t)0x06) /*!< FDCAN1 Alternate Function mapping */ +#define GPIO_AF6_FDCAN2 ((uint8_t)0x06) /*!< FDCAN2 Alternate Function mapping */ +#define GPIO_AF6_FDCAN3 ((uint8_t)0x06) /*!< FDCAN3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /*!< SPI4 Alternate Function mapping */ +#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF6_USART10 ((uint8_t)0x06) /*!< USART10 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_I3C1 ((uint8_t)0x07) /*!< I3C1 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF7_SPI6 ((uint8_t)0x07) /*!< SPI6 Alternate Function mapping */ +#define GPIO_AF7_TIM15 ((uint8_t)0x07) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF7_UART9 ((uint8_t)0x07) /*!< UART9 Alternate Function mapping */ +#define GPIO_AF7_UCPD1 ((uint8_t)0x07) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF7_USART6 ((uint8_t)0x07) /*!< USART6 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_GFXTIM ((uint8_t)0x08) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /*!< SPDIFRX Alternate Function mapping */ +#define GPIO_AF8_SPI6 ((uint8_t)0x08) /*!< SPI6 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /*!< UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /*!< UART8 Alternate Function mapping */ +#define GPIO_AF8_USART2 ((uint8_t)0x08) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_XSPIM_P1 ((uint8_t)0x09) /*!< XSPIM Manager Port 1 Alternate Function mapping */ +#define GPIO_AF9_XSPIM_P2 ((uint8_t)0x09) /*!< XSPIM Manager Port 2 Alternate Function mapping */ +#define GPIO_AF9_PSSI ((uint8_t)0x09) /*!< PSSI Alternate Function mapping */ +#define GPIO_AF9_SPI5 ((uint8_t)0x09) /*!< SPI5 Alternate Function mapping */ +#define GPIO_AF9_TIM11 ((uint8_t)0x09) /*!< TIM11 Alternate Function mapping */ +#define GPIO_AF9_DCMIPP ((uint8_t)0x09) /*!< DCMIPP Alternate Function mapping */ +#define GPIO_AF9_DCMI ((uint8_t)0x09) /*!< DCMI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_LCD ((uint8_t)0x0A) /*!< LCD Alternate Function mapping */ +#define GPIO_AF10_MDIOS ((uint8_t)0x0A) /*!< MDIOS Alternate Function mapping */ +#define GPIO_AF10_PSSI ((uint8_t)0x0A) /*!< PSSI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /*!< SAI2 Alternate Function mapping */ +#define GPIO_AF10_SDMMC1 ((uint8_t)0x0A) /*!< SDMMC1 Alternate Function mapping */ +#define GPIO_AF10_SPI1 ((uint8_t)0x0A) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF10_TIM10 ((uint8_t)0x0A) /*!< TIM10 Alternate Function mapping */ +#define GPIO_AF10_TIM13 ((uint8_t)0x0A) /*!< TIM13 Alternate Function mapping */ +#define GPIO_AF10_UART7 ((uint8_t)0x0A) /*!< UART7 Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /*!< FMC Alternate Function mapping */ +#define GPIO_AF10_DCMIPP ((uint8_t)0x0A) /*!< DCMIPP Alternate Function mapping */ +#define GPIO_AF10_DCMI ((uint8_t)0x0A) /*!< DCMI Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH1 ((uint8_t)0x0B) /*!< ETH1 Alternate Function mapping */ +#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /*!< MDIOS Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_UART5 ((uint8_t)0x0B) /*!< UART5 Alternate Function mapping */ +#define GPIO_AF11_TIM14 ((uint8_t)0x0B) /*!< TIM14 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_ETH1 ((uint8_t)0x0C) /*!< ETH1 Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /*!< FMC Alternate Function mapping */ +#define GPIO_AF12_GFXTIM ((uint8_t)0x0C) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF12_LCD ((uint8_t)0x0C) /*!< LCD Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /*!< SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_FMC ((uint8_t)0x0E) /*!< FMC Alternate Function mapping */ +#define GPIO_AF14_LCD ((uint8_t)0x0E) /*!< LCD Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF15_HDP ((uint8_t)0x0F) /*!< HDP Alternate Function mapping */ + +/** + * @brief check if AF is valid + */ +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index + * @{ + */ +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :\ + ((__GPIOx__) == (GPIOG))? 6uL :\ + ((__GPIOx__) == (GPIOH))? 7uL :\ + ((__GPIOx__) == (GPION))? 8uL :\ + ((__GPIOx__) == (GPIOO))? 9uL :\ + ((__GPIOx__) == (GPIOP))? 10uL :\ + ((__GPIOx__) == (GPIOQ))? 11uL : 16uL) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_GPIO_EX_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pwr.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pwr.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pwr.h (revision 16) @@ -0,0 +1,683 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_PWR_H +#define STM32N6xx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +} PWR_PVDTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_LP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +/* define for interface compatibility purpose */ +#define PWR_MAINREGULATOR_ON (0U) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (1U) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE (2U) /*!< Wait For Event instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (3U) /*!< Wait For Event instruction to enter Sleep mode with no event clear */ +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI (1U) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE (2U) /*!< Wait For Event instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (3U) /*!< Wait For Event instruction to enter Stop mode with no event clear */ +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK (0x00FF0F0FU) +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pins PWR Wake-Up Pins + * @{ + */ +/* High level and No pull (default configuration) */ +#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 1 (with high level polarity) */ +#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 2 (with high level polarity) */ +#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 3 (with high level polarity) */ +#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 4 (with high level polarity) */ + +/* High level and No pull */ +#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 1 (with high level polarity) */ +#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 2 (with high level polarity) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 3 (with high level polarity) */ +#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 4 (with high level polarity) */ + +/* Low level and No pull */ +#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) /*!< Wakeup pin 1 (with low level polarity) */ +#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) /*!< Wakeup pin 2 (with low level polarity) */ +#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) /*!< Wakeup pin 3 (with low level polarity) */ +#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) /*!< Wakeup pin 4 (with low level polarity) */ +/** + * @} + */ + +/** @defgroup PWR_Flag_WUP PWR Flag WakeUp + * @{ + */ +#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 +#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 +#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 +#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 +#define PWR_FLAG_WKUP (PWR_FLAG_WKUP1 | PWR_WKUPCR_WKUPC2 | \ + PWR_FLAG_WKUP3 | PWR_WKUPCR_WKUPC4) +/** + * @} + */ + +/** @defgroup PWR_PIN_Polarity PWR Pin Polarity configuration + * @{ + */ +#define PWR_PIN_POLARITY_HIGH (0x0U) +#define PWR_PIN_POLARITY_LOW (0x1U) +/** + * @} + */ + +/** @defgroup PWR_PIN_Pull PWR Pin Pull configuration + * @{ + */ +#define PWR_PIN_NO_PULL (0x0U) +#define PWR_PIN_PULL_UP (0x1U) +#define PWR_PIN_PULL_DOWN (0x2U) +/** + * @} + */ + +/** @defgroup PWR_Wakeup_Pins_Flags PWR Wakeup Pins Flags. + * @{ + */ +#define PWR_WAKEUP_FLAG1 PWR_WKUPSR_WKUPF1 /*!< Wakeup flag on PA0 */ +#define PWR_WAKEUP_FLAG2 PWR_WKUPSR_WKUPF2 /*!< Wakeup flag on PA2 */ +#define PWR_WAKEUP_FLAG3 PWR_WKUPSR_WKUPF3 /*!< Wakeup flag on PC13 */ +#define PWR_WAKEUP_FLAG4 PWR_WKUPSR_WKUPF4 /*!< Wakeup flag on PD2 */ + +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPSR_WKUPF1 | PWR_WKUPSR_WKUPF2 |\ + PWR_WKUPSR_WKUPF3 | PWR_WKUPSR_WKUPF4) +/** + * @} + */ + +/** @defgroup PWR_Items PWR Items + * @{ + */ + +/* Use the PWR_SECCFGR bits definition offset for both Secure and Privilege because + it is the same offset value for the same item */ +#define PWR_ITEM_0 PWR_SECCFGR_SEC0 /*!< System supply configuration secure/privilege protection */ +#define PWR_ITEM_1 PWR_SECCFGR_SEC1 /*!< Programmable voltage detector secure/privilege protection */ +#define PWR_ITEM_2 PWR_SECCFGR_SEC2 /*!< VDDCORE monitor secure/privilege protection */ +#define PWR_ITEM_3 PWR_SECCFGR_SEC3 /*!< TCM and FLEXMEM low power control secure/privilege protection */ +#define PWR_ITEM_4 PWR_SECCFGR_SEC4 /*!< Voltage scaling selection secure/privilege protection */ +#define PWR_ITEM_5 PWR_SECCFGR_SEC5 /*!< Backup domain secure/privilege protection */ +#define PWR_ITEM_6 PWR_SECCFGR_SEC6 /*!< CPU power control secure/privilege protection */ +#define PWR_ITEM_7 PWR_SECCFGR_SEC7 /*!< Peripheral voltage monitor secure/privilege protection */ +#define PWR_ITEM_WKUP1 PWR_SECCFGR_WKUPSEC1 /*!< WKUP1 pin secure/privilege protection */ +#define PWR_ITEM_WKUP2 PWR_SECCFGR_WKUPSEC2 /*!< WKUP2 pin secure/privilege protection */ +#define PWR_ITEM_WKUP3 PWR_SECCFGR_WKUPSEC3 /*!< WKUP3 pin secure/privilege protection */ +#define PWR_ITEM_WKUP4 PWR_SECCFGR_WKUPSEC4 /*!< WKUP4 pin secure/privilege protection */ + +#define PWR_ITEM_ALL (PWR_ITEM_0 | PWR_ITEM_1 | PWR_ITEM_2 | PWR_ITEM_3 | PWR_ITEM_4 | PWR_ITEM_5 | \ + PWR_ITEM_6 | PWR_ITEM_7 | PWR_ITEM_WKUP1 | PWR_ITEM_WKUP2 | PWR_ITEM_WKUP3 | \ + PWR_ITEM_WKUP4) +/** + * @} + */ + +/** @defgroup PWR_Attributes PWR Attributes + * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes + * @{ + */ +/* Defines attribute */ +#define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ +#define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ + +#define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ +#define PWR_NSEC_NPRIV PWR_ITEM_ATTR_NSEC_PRIV_MASK /*!< NSecure and NPrivileged attribute */ +#define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ +#define PWR_SEC_NPRIV PWR_ITEM_ATTR_SEC_PRIV_MASK /*!< Secure and NPrivileged attribute */ +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Status Flags + * Elements values convention: 0000 00XX XXXX XXXY YYYYb + * - Y YYYY : Flag position in the XXX register (5 bits) + * - XX XXXX XXX : Status register (9 bits) + * - 000000001: CR2 register + * - 000000010: VOSCR register + * - 000000100: CR3 register + * - 000001000: BDCR1 register + * - 000010000: CPUCR register + * - 000100000: SVMCR1 register + * - 001000000: SVMCR2 register + * - 010000000: SVMCR3 register + * - 100000000: WKUPSR register + * @{ + */ +/* CR2 */ +#define PWR_FLAG_PVDO (0x0028U) /*!< Programmable voltage detect output */ + +/* VOSCR */ +#define PWR_FLAG_ACTVOSRDY (0x0051U) /*!< Voltage levels ready bit */ +#define PWR_FLAG_ACTVOS (0x0050U) /*!< Programmable voltage detect output */ +#define PWR_FLAG_VOSRDY (0x0041U) /*!< VOS Ready bit for VCORE voltage scaling output selection */ + +/* CR3 */ +#define PWR_FLAG_VCOREH (0x0089U) /*!< VDDCORE level monitoring versus high threshold */ +#define PWR_FLAG_VCOREL (0x0088U) /*!< VDDCORE level monitoring versus low threshold */ + +/* BDCR1 */ +#define PWR_FLAG_TEMPH (0x0113U) /*!< Temperature level monitoring versus high threshold */ +#define PWR_FLAG_TEMPL (0x0112U) /*!< Temperature level monitoring versus low threshold */ +#define PWR_FLAG_VBATH (0x0111U) /*!< VBAT level monitoring versus high threshold */ +#define PWR_FLAG_VBATL (0x0110U) /*!< VBAT level monitoring versus low threshold */ + +/* CPUCR */ +#define PWR_FLAG_SBF (0x0209U) /*!< System Standby flag */ +#define PWR_FLAG_STOPF (0x0208U) /*!< System Stop flag */ + +/* SVMCR1 */ +#define PWR_FLAG_VDDIO4RDY (0x0410U) /*!< VDDIO4 ready */ + + +/* SVMCR2 */ +#define PWR_FLAG_VDDIO5RDY (0x0810U) /*!< VDDIO5 ready */ + +/* SVMCR3 */ +#define PWR_FLAG_ARDY (0x1014U) /*!< VDDA18ADC ready */ +#define PWR_FLAG_USB33RDY (0x1012U) /*!< VDD33USB ready */ +#define PWR_FLAG_VDDIO3RDY (0x1011U) /*!< VDDIO3 ready */ +#define PWR_FLAG_VDDIO2RDY (0x1010U) /*!< VDDIO2 ready */ + +/* WKUPSR */ +#define PWR_FLAG_WKUPF4 (0x2004U) /*!< Wakeup event on wakeup pin 4 */ +#define PWR_FLAG_WKUPF3 (0x2003U) /*!< Wakeup event on wakeup pin 3 */ +#define PWR_FLAG_WKUPF2 (0x2002U) /*!< Wakeup event on wakeup pin 2 */ +#define PWR_FLAG_WKUPF1 (0x2001U) /*!< Wakeup event on wakeup pin 1 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_PVDO: This flag is valid only if PVD + * is enabled by the HAL_PWR_EnablePVD()function. + * The PVD is stopped by STANDBY mode. + * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the regulator voltage + * scaling output selection is ready. + * @arg PWR_FLAG_ACTVOS: This flag indicates that the regulator voltage + * scaling output selection is ready. + * @arg PWR_FLAG_VOSRDY When an internal regulator is used, this bit indicates + * that all the features allowed by the selected VOS can be used. + * @arg PWR_FLAG_VCOREH: This flag indicates if the VDDCORE level is above + * the high monitoring threshold. + * @arg PWR_FLAG_VCOREL This flag indicates if the VDDCORE level is above + * the low monitoring threshold. + * @arg PWR_FLAG_TEMPH: This flag indicates if the temperature level is above + * the high monitoring threshold. + * @arg PWR_FLAG_TEMPL This flag indicates if the temperature level is above + * the low monitoring threshold. + * @arg PWR_FLAG_VBATH: This flag indicates if the VBAT level is above + * the high monitoring threshold. + * @arg PWR_FLAG_VBATL: This flag indicates if the VBAT level is above + * the low monitoring threshold. + * @arg PWR_FLAG_SBF: Standby mode flag. + * @arg PWR_FLAG_STOPF: STOP mode flag. + * @arg PWR_FLAG_VDDIO5RDY: This flag indicates if the VDDIO5 is ready. + * @arg PWR_FLAG_VDDIO4RDY: This flag indicates if the VDDIO4 is ready. + * @arg PWR_FLAG_VDDIO3RDY: This flag indicates if the VDDIO3 is ready. + * @arg PWR_FLAG_VDDIO2RDY: This flag indicates if the VDDIO2 is ready. + * @arg PWR_FLAG_ARDY: This flag indicates if the VDDA18ADC is ready. + * @arg PWR_FLAG_USB33RDY: This flag indicates if the VDD33USB is ready. + * @arg PWR_FLAG_WUF1: This flag indicates a wakeup event was + * received from WKUP1 pin. + * @arg PWR_FLAG_WUF2: This flag indicates a wakeup event was + * received from WKUP2 pin. + * @arg PWR_FLAG_WUF3: This flag indicates a wakeup event was + * received from WKUP3 pin. + * @arg PWR_FLAG_WUF4: This flag indicates a wakeup event was + * received from WKUP4 pin. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CR2 & PWR_CR2_PVDO) == PWR_CR2_PVDO) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->VOSCR & PWR_VOSCR_ACTVOSRDY) == PWR_VOSCR_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_ACTVOS) ? ((PWR->VOSCR & PWR_VOSCR_ACTVOS) == PWR_VOSCR_ACTVOS) : \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->VOSCR & PWR_VOSCR_VOSRDY) == PWR_VOSCR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_VCOREH) ? ((PWR->CR3 & PWR_CR3_VCOREH) == PWR_CR3_VCOREH) : \ + ((__FLAG__) == PWR_FLAG_VCOREL) ? ((PWR->CR3 & PWR_CR3_VCOREL) == PWR_CR3_VCOREL) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->BDCR1 & PWR_BDCR1_TEMPH) == PWR_BDCR1_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->BDCR1 & PWR_BDCR1_TEMPL) == PWR_BDCR1_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->BDCR1 & PWR_BDCR1_VBATH) == PWR_BDCR1_VBATH) : \ + ((__FLAG__) == PWR_FLAG_VBATL) ? ((PWR->BDCR1 & PWR_BDCR1_VBATL) == PWR_BDCR1_VBATL) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_VDDIO4RDY) ? ((PWR->SVMCR1 & PWR_SVMCR1_VDDIO4RDY) == PWR_SVMCR1_VDDIO4RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDIO5RDY) ? ((PWR->SVMCR2 & PWR_SVMCR2_VDDIO5RDY) == PWR_SVMCR2_VDDIO5RDY) : \ + ((__FLAG__) == PWR_FLAG_ARDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_ARDY) == PWR_SVMCR3_ARDY) : \ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_USB33RDY) == PWR_SVMCR3_USB33RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDIO3RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_VDDIO3RDY) == PWR_SVMCR3_VDDIO3RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_VDDIO2RDY) == PWR_SVMCR3_VDDIO2RDY) : \ + ((__FLAG__) == PWR_FLAG_WKUPF4) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF4) == PWR_WKUPSR_WKUPF4) : \ + ((__FLAG__) == PWR_FLAG_WKUPF3) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF3) == PWR_WKUPSR_WKUPF3) : \ + ((__FLAG__) == PWR_FLAG_WKUPF2) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF2) == PWR_WKUPSR_WKUPF2) : \ + ((__FLAG__) == PWR_FLAG_WKUPF1) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF1) == PWR_WKUPSR_WKUPF1) : \ + ((PWR->WKUPSR & PWR_WKUPSR_WKUPF4) == PWR_WKUPSR_WKUPF4)) + +/** @brief Clear PWR flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_STOPF : Stop flag. + * Indicates that the device was resumed from Stop mode. + * @arg PWR_FLAG_SBF : Standby flag. + * Indicates that the device was resumed from Standby mode. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \ + (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF))) + +/** @brief Check PWR wake up flags are set or not. + * @param __FLAG__: specifies the wake up flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WKUP1 : This parameter gets Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter gets Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter gets Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter gets Wake up line 4 flag. + * @arg PWR_FLAG_WKUP : This parameter gets Wake up lines 1 to 4 flags. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0U : 1U) + +/** @brief Clear CPU PWR wake up flags. + * @param __FLAG__ : Specifies the wake up flag to be cleared. + * This parameter can be one of the following values : + * @arg PWR_FLAG_WKUP1 : This parameter clears Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clears Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clears Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clears Wake up line 4 flag. + * @arg PWR_FLAG_WKUP : This parameter clears Wake up lines 1 to 4 flags. + * @retval None. + */ +#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) + +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0); + +/** + * @brief Check whether or not the PVD EXTI interrupt Rising flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR3 & PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt Falling flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR3 & PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Rising flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVD) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD EXTI_IMR3_IM66 /*!< External interrupt line 66 connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ + +/* Check PVD mode parameter */ +#define IS_PWR_PVD_MODE(__MODE__) (((__MODE__) == PWR_PVD_MODE_IT_RISING) ||\ + ((__MODE__) == PWR_PVD_MODE_IT_FALLING) ||\ + ((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((__MODE__) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((__MODE__) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ + ((__MODE__) == PWR_PVD_MODE_NORMAL)) + +/* Check Sleep mode entry parameter */ +#define IS_PWR_SLEEP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_SLEEPENTRY_WFI) ||\ + ((__ENTRY__) == PWR_SLEEPENTRY_WFE) ||\ + ((__ENTRY__) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +/* Check Stop mode mode entry parameter */ +#define IS_PWR_STOP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_STOPENTRY_WFI) ||\ + ((__ENTRY__) == PWR_STOPENTRY_WFE) ||\ + ((__ENTRY__) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) + +/* Check wake up pin parameter */ +#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) ||\ + ((__PIN__) == PWR_WAKEUP_PIN2) ||\ + ((__PIN__) == PWR_WAKEUP_PIN3) ||\ + ((__PIN__) == PWR_WAKEUP_PIN4) ||\ + ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) ||\ + ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((__PIN__) == PWR_WAKEUP_PIN1_LOW) ||\ + ((__PIN__) == PWR_WAKEUP_PIN2_LOW) ||\ + ((__PIN__) == PWR_WAKEUP_PIN3_LOW) ||\ + ((__PIN__) == PWR_WAKEUP_PIN4_LOW)) + +/* Check wake up pin polarity parameter */ +#define IS_PWR_WAKEUP_PIN_POLARITY(__POLARITY__) (((__POLARITY__) == PWR_PIN_POLARITY_HIGH) ||\ + ((__POLARITY__) == PWR_PIN_POLARITY_LOW)) + +/* Check wake up pin pull configuration parameter */ +#define IS_PWR_WAKEUP_PIN_PULL(__PULL__) (((__PULL__) == PWR_PIN_NO_PULL) ||\ + ((__PULL__) == PWR_PIN_PULL_UP) ||\ + ((__PULL__) == PWR_PIN_PULL_DOWN)) + +/* Check wake up flag parameter */ +#define IS_PWR_WAKEUP_FLAG(__FLAG__) (((__FLAG__) == PWR_WAKEUP_FLAG1) ||\ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ||\ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ||\ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ||\ + ((__FLAG__) == PWR_WAKEUP_FLAG_ALL)) + + +/* PWR Secure/Privilege items check macro */ +#define IS_PWR_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & (~PWR_ITEM_ALL)) == 0U) && ((__ITEM__) != 0U)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* PWR attribute check macro (Secure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) ((((~(((ATTRIBUTES)& \ + 0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && \ + (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) +#else +/* PWR attribute check macro (NSecure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32n6xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @{ + */ +/* Peripheral Control Functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *pConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); +uint32_t HAL_PWR_GetWakeupFlag(uint32_t WakeUpFlag); +HAL_StatusTypeDef HAL_PWR_ClearWakeupFlag(uint32_t WakeUpFlag); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/* Interrupt handler functions ************************************************/ +void HAL_PWR_PVD_Rising_Callback(void); +void HAL_PWR_PVD_Falling_Callback(void); +void HAL_PWR_WAKEUP_PIN_IRQHandler(void); +void HAL_PWR_WKUP1_Callback(void); +void HAL_PWR_WKUP2_Callback(void); +void HAL_PWR_WKUP3_Callback(void); +void HAL_PWR_WKUP4_Callback(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group3 + * @{ + */ +/* Privileges and security configuration functions ****************************/ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32N6xx_HAL_PWR_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pwr_ex.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pwr_ex.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pwr_ex.h (revision 16) @@ -0,0 +1,1141 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_PWR_EX_H +#define STM32N6xx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ +/** + * @brief PWREx Wakeup pin configuration structure definition + */ +typedef struct +{ + uint32_t WakeUpPin; /*!< Specifies the Wake-Up pin to be enabled. + This parameter can be a value of @ref PWR_WakeUp_Pins */ + + uint32_t PinPolarity; /*!< Specifies the Wake-Up pin polarity. + This parameter can be a value of @ref PWR_PIN_Polarity */ + + uint32_t PinPull; /*!< Specifies the Wake-Up pin pull. + This parameter can be a value of @ref PWR_PIN_Pull */ +} PWREx_WakeupPinTypeDef; + +/** + * @brief PWR PVM configuration structure definition + */ +typedef struct +{ + uint32_t PVMType; /*!< Specifies which voltage is monitored. + This parameter can be a value of + @ref PWREx_PVM_Type. */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of + @ref PWREx_PVM_Mode. */ +} PWR_PVMTypeDef; + + +/** + * @brief PWR VddCORE monitoring configuration structure definition + */ +typedef struct +{ + uint32_t LowVoltageThreshold; /*!< Specifies the VDDCORE voltage detector low-level. + This parameter can be a value of + @ref PWREx_VDDCORE_Levels. */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of + @ref PWREx_VddCOREVM_Mode. */ +} PWR_VddCOREVMTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +/** @defgroup PWREx_Supply_configuration PWREx Supply configuration + * @{ + */ +#define PWR_SMPS_SUPPLY PWR_CR1_SDEN /*!< VCORE power domains are supplied from SMPS step-down converter according to VOS */ +#define PWR_EXTERNAL_SOURCE_SUPPLY (0U) /*!< SMPS step-down converter disabled. VCORE supplied from external source */ + +#define PWR_SUPPLY_CONFIG_MASK PWR_CR1_SDEN +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE0 PWR_VOSCR_VOS /*!< Voltage scaling range 0 (highest frequency) */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 (0U) /*!< Voltage scaling range 1 (lowest power) */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_STOP_VOLTAGE_SCALE3 PWR_CPUCR_SVOS /*!< System Stop mode voltage scaling range 3 (highest frequency) */ +#define PWR_REGULATOR_STOP_VOLTAGE_SCALE5 (0U) /*!< System Stop mode voltage scaling range 5 (lowest power) */ +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds + * @{ + */ +#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0U) +#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_BDCR1_VBATL +#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_BDCR1_VBATH +/** + * @} + */ + +/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds + * @{ + */ +#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0U) +#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_BDCR1_TEMPL +#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_BDCR1_TEMPH +/** + * @} + */ + +/** @defgroup PWREx_VDDCORE_Levels PWREx VDDCORE voltage detector low-level + * @{ + */ +#define PWR_VDDCORE_THRESHOLD_VOS0 PWR_CR3_VCORELLS +#define PWR_VDDCORE_THRESHOLD_VOS1 (0U) +/** + * @} + */ + +/** @defgroup PWREx_VDDCORE_Thresholds PWREx VDDCORE voltage detector low-level Thresholds + * @{ + */ +#define PWR_VDDCORE_BETWEEN_HIGH_LOW_THRESHOLD (0U) +#define PWR_VDDCORE_BELOW_LOW_THRESHOLD PWR_CR3_VCOREL +#define PWR_VDDCORE_ABOVE_HIGH_THRESHOLD PWR_CR3_VCOREH +/** + * @} + */ + +/** @defgroup PWREx_VddCOREVM_Mode PWR Extended VddCORE Monitoring Interrupt and Event Mode + * @{ + */ +#define PWR_VDDCOREVM_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ +#define PWR_VDDCOREVM_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_VDDCOREVM_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_VDDCOREVM_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_VDDCOREVM_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_VDDCOREVM_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_VDDCOREVM_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWREx_VDDIO PWREx Vdd IO selection + * @{ + */ +#define PWR_VDDIO (0U) +#define PWR_VDDIO2 (1U) +#define PWR_VDDIO3 (2U) +#define PWR_VDDIO4 (3U) +#define PWR_VDDIO5 (4U) +/** + * @} + */ + +/** @defgroup PWREx_VDDIO_Range PWREx Vdd IO Range + * @{ + */ +#define PWR_VDDIO_RANGE_3V3 (0U) +#define PWR_VDDIO_RANGE_1V8 (1U) +/** + * @} + */ + +/** @defgroup PWREx_PVM_Mode PWR Extended PVM Interrupt and Event Mode + * @{ + */ +#define PWR_PVM_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ +#define PWR_PVM_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ + +/** + * @brief Enable the USBVM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Disable the USBVM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Enable the USBVM Event Line. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Disable the USBVM Event Line. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Enable the USBVM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Disable the USBVM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Enable the USBVM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Disable the USBVM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Enable the USBVM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the USBVM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_USBVM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_USBVM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on USBVM EXTI Line. + * @retval None + */ +#define __HAL_PWR_USBVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Check whether the specified USBVM EXTI flag is set or not. + * @retval EXTI USBVM Line Status. + */ +#define __HAL_PWR_USBVM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Clear the USBVM interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_USBVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Clear the USBVM interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_USBVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDUSB) + +/** + * @brief Enable the IO2VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Disable the IO2VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Enable the IO2VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Disable the IO2VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Enable the IO2VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Disable the IO2VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Enable the IO2VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Disable the IO2VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Enable the IO2VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the IO2VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on IO2VM EXTI Line. + * @retval None + */ +#define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Check whether the specified IO2VM EXTI flag is set or not. + * @retval EXTI IO2VM Line Status. + */ +#define __HAL_PWR_IO2VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Clear the IO2VM interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_IO2VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Clear the IO2VM interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_IO2VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO2) + +/** + * @brief Enable the IO3VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Disable the IO3VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Enable the IO3VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Disable the IO3VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Enable the IO3VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Disable the IO3VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Enable the IO3VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Disable the IO3VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Enable the IO3VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_IO3VM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the IO3VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_IO3VM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on IO3VM EXTI Line. + * @retval None + */ +#define __HAL_PWR_IO3VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Check whether the specified IO3VM EXTI flag is set or not. + * @retval EXTI IO3VM Line Status. + */ +#define __HAL_PWR_IO3VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Clear the IO3VM interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_IO3VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Clear the IO3VM interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_IO3VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO3) + +/** + * @brief Enable the IO4VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Disable the IO4VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Enable the IO4VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Disable the IO4VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Enable the IO4VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Disable the IO4VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Enable the IO4VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Disable the IO4VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Enable the IO4VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_IO4VM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the IO4VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_IO4VM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on IO4VM EXTI Line. + * @retval None + */ +#define __HAL_PWR_IO4VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Check whether the specified IO4VM EXTI flag is set or not. + * @retval EXTI IO4VM Line Status. + */ +#define __HAL_PWR_IO4VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Clear the IO4VM interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_IO4VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Clear the IO4VM interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_IO4VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO4) + +/** + * @brief Enable the IO5VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Disable the IO5VM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Enable the IO5VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Disable the IO5VM Event Line. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Enable the IO5VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Disable the IO5VM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Enable the IO5VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Disable the IO5VM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Enable the IO5VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_IO5VM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the IO5VM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_IO5VM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on IO5VM EXTI Line. + * @retval None + */ +#define __HAL_PWR_IO5VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Check whether the specified IO5VM EXTI flag is set or not. + * @retval EXTI IO5VM Line Status. + */ +#define __HAL_PWR_IO5VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Clear the IO5VM interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_IO5VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Clear the IO5VM interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_IO5VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO5) + +/** + * @brief Enable the ADCVM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Disable the ADCVM Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Enable the ADCVM Event Line. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Disable the ADCVM Event Line. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Enable the ADCVM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Disable the ADCVM Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Enable the ADCVM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Disable the ADCVM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Enable the ADCVM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_ADCVM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the ADCVM Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_ADCVM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on ADCVM EXTI Line. + * @retval None + */ +#define __HAL_PWR_ADCVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Check whether the specified ADCVM EXTI flag is set or not. + * @retval EXTI ADCVM Line Status. + */ +#define __HAL_PWR_ADCVM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Clear the ADCVM interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_ADCVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Clear the ADCVM interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_ADCVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDA) + +/** + * @brief Enable the VddCORE monitoring Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Disable the VddCORE monitoring Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Enable the VddCORE monitoring Event Line. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Disable the VddCORE monitoring Event Line. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Enable the VddCORE monitoring Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Disable the VddCORE monitoring Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Enable the VddCORE monitoring Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Disable the VddCORE monitoring Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Enable the VddCORE monitoring Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_VCOREVM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the VddCORE monitoring Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_VCOREVM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on VddCORE monitoring EXTI Line. + * @retval None + */ +#define __HAL_PWR_VCOREVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Check whether the specified VddCORE monitoring EXTI flag is set or not. + * @retval EXTI VddCORE monitoring Line Status. + */ +#define __HAL_PWR_VCOREVM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Clear the VddCORE monitoring interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_VCOREVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_VCOREVM) + +/** + * @brief Clear the VddCORE monitoring interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_VCOREVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_VCOREVM) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @{ + */ +/* Power supply control functions */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig(void); + +/* Power voltage scaling functions */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange(void); +void HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetStopModeVoltageRange(void); + + +/** @addtogroup PWREx_Exported_Functions_Group2 Wakeup Pins configuration functions + * @{ + */ +/* Wakeup Pins control functions */ +void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams); +/** + * @} + */ + + +/** @addtogroup PWREx_Exported_Functions_Group3 Memories Retention Functions + * @{ + */ +void HAL_PWREx_EnableBkupRAMRetention(void); +void HAL_PWREx_DisableBkupRAMRetention(void); +void HAL_PWREx_EnableTCMRetention(void); +void HAL_PWREx_DisableTCMRetention(void); +void HAL_PWREx_EnableTCMFLXRetention(void); +void HAL_PWREx_DisableTCMFLXRetention(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 Low Power Control Functions + * @{ + */ +void HAL_PWREx_SetPulseLow(uint32_t Pulselowtime); +uint32_t HAL_PWREx_GetPulseLow(void); +void HAL_PWREx_EnableSMPSPWM(void); +void HAL_PWREx_DisableSMPSPWM(void); +void HAL_PWREx_EnablePullDownOutput(void); +void HAL_PWREx_DisablePullDownOutput(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group5 Power Monitoring functions + * @{ + */ +/* Power VBAT/Temperature monitoring functions */ +void HAL_PWREx_EnableMonitoring(void); +void HAL_PWREx_DisableMonitoring(void); +uint32_t HAL_PWREx_GetTemperatureLevel(void); +uint32_t HAL_PWREx_GetVBATLevel(void); +void HAL_PWREx_EnableVDDCOREMonitoring(void); +void HAL_PWREx_DisableVDDCOREMonitoring(void); +void HAL_PWREx_ConfigVDDCOREVM(const PWR_VddCOREVMTypeDef *pConfigVddCOREVM); +uint32_t HAL_PWREx_GetVDDCORELevel(void); +void HAL_PWREx_ConfigVddIORange(uint32_t VddIOPort, uint32_t VoltageRange); +uint32_t HAL_PWREx_GetVddIORange(uint32_t VddIOPort); +void HAL_PWREx_EnableVddIO4RangeSTBY(void); +void HAL_PWREx_DisableVddIO4RangeSTBY(void); +void HAL_PWREx_EnableVddIO5RangeSTBY(void); +void HAL_PWREx_DisableVddIO5RangeSTBY(void); +void HAL_PWREx_EnableVddUSB(void); +void HAL_PWREx_DisableVddUSB(void); +void HAL_PWREx_EnableVddIO2(void); +void HAL_PWREx_DisableVddIO2(void); +void HAL_PWREx_EnableVddIO3(void); +void HAL_PWREx_DisableVddIO3(void); +void HAL_PWREx_EnableVddIO4(void); +void HAL_PWREx_DisableVddIO4(void); +void HAL_PWREx_EnableVddIO5(void); +void HAL_PWREx_DisableVddIO5(void); +void HAL_PWREx_EnableVddA(void); +void HAL_PWREx_DisableVddA(void); +void HAL_PWREx_EnableVddUSBVMEN(void); +void HAL_PWREx_DisableVddUSBVMEN(void); +void HAL_PWREx_EnableVddIO2VMEN(void); +void HAL_PWREx_DisableVddIO2VMEN(void); +void HAL_PWREx_EnableVddIO3VMEN(void); +void HAL_PWREx_DisableVddIO3VMEN(void); +void HAL_PWREx_EnableVddIO4VMEN(void); +void HAL_PWREx_DisableVddIO4VMEN(void); +void HAL_PWREx_EnableVddIO5VMEN(void); +void HAL_PWREx_DisableVddIO5VMEN(void); +void HAL_PWREx_EnableVddAVMEN(void); +void HAL_PWREx_DisableVddAVMEN(void); +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *pConfigPVM); +void HAL_PWREx_PVD_PVM_IRQHandler(void); +void HAL_PWREx_VDDCORE_Rising_Callback(void); +void HAL_PWREx_VDDCORE_Falling_Callback(void); +void HAL_PWREx_USBVM_Rising_Callback(void); +void HAL_PWREx_USBVM_Falling_Callback(void); +void HAL_PWREx_IO2VM_Rising_Callback(void); +void HAL_PWREx_IO2VM_Falling_Callback(void); +void HAL_PWREx_IO3VM_Rising_Callback(void); +void HAL_PWREx_IO3VM_Falling_Callback(void); +void HAL_PWREx_IO4VM_Rising_Callback(void); +void HAL_PWREx_IO4VM_Falling_Callback(void); +void HAL_PWREx_IO5VM_Rising_Callback(void); +void HAL_PWREx_IO5VM_Falling_Callback(void); +void HAL_PWREx_ADCVM_Rising_Callback(void); +void HAL_PWREx_ADCVM_Falling_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + + +/** @defgroup PWREx_VDDCOREVM_EXTI PWR VddCORE monitoring extended interrupts and event lines defines + * @{ + */ +#define PWR_EXTI_LINE_VCOREVM EXTI_IMR3_IM68 /*!< VddCORE monitoring EXTI Line */ +/** + * @} + */ + +/** @defgroup PWREx_PVM_EXTI PWR PVM extended interrupts and event lines defines + * @{ + */ +#define PWR_EXTI_LINE_PVM_VDDIO2 EXTI_IMR3_IM69 /*!< PVM VDDIO2 EXTI Line */ +#define PWR_EXTI_LINE_PVM_VDDIO3 EXTI_IMR3_IM70 /*!< PVM VDDIO3 EXTI Line */ +#define PWR_EXTI_LINE_PVM_VDDIO4 EXTI_IMR3_IM71 /*!< PVM VDDIO4 EXTI Line */ +#define PWR_EXTI_LINE_PVM_VDDIO5 EXTI_IMR3_IM72 /*!< PVM VDDIO5 EXTI Line */ +#define PWR_EXTI_LINE_PVM_VDDUSB EXTI_IMR3_IM73 /*!< PVM VDD USB EXTI Line */ +#define PWR_EXTI_LINE_PVM_VDDA EXTI_IMR3_IM74 /*!< PVM VDD ADC EXTI Line */ +/** + * @} + */ + +/** @defgroup PWREx_PVM_Type PWR Extended Voltage Monitoring Type + * @{ + */ +#define PWR_VDDUSB_VM (0U) /*!< Independent USB voltage monitor */ +#define PWR_VDDIO2_VM (1U) /*!< Independent VDDIO2 voltage monitor */ +#define PWR_VDDIO3_VM (2U) /*!< Independent VDDIO3 voltage monitor */ +#define PWR_VDDIO4_VM (3U) /*!< Independent VDDIO4 voltage monitor */ +#define PWR_VDDIO5_VM (4U) /*!< Independent VDDIO5 voltage monitor */ +#define PWR_VDDA_VM (5U) /*!< Independent VDDA voltage monitor */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +/* Check PWR regulator configuration parameter */ +#define IS_PWR_SUPPLY(__SOURCE__) (((__SOURCE__) == PWR_SMPS_SUPPLY) ||\ + ((__SOURCE__) == PWR_EXTERNAL_SOURCE_SUPPLY)) + +/* Check low power regulator parameter */ +#define IS_PWR_REGULATOR(__REGULATOR__) ((__REGULATOR__) == PWR_MAINREGULATOR_ON) + +/* Check voltage scale level parameter */ +#define IS_PWR_REGULATOR_VOLTAGE(__VOLTAGE__) (((__VOLTAGE__) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ + ((__VOLTAGE__) == PWR_REGULATOR_VOLTAGE_SCALE1)) + +/* Check PWR regulator configuration in STOP mode parameter */ +#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(__VOLTAGE__) (((__VOLTAGE__) == PWR_REGULATOR_STOP_VOLTAGE_SCALE3) ||\ + ((__VOLTAGE__) == PWR_REGULATOR_STOP_VOLTAGE_SCALE5)) + +/* Check PWR pulse low time configuration parameter */ +#define IS_PWR_PULSE_LOW_TIME(__LOWTIME__) ((__LOWTIME__) <= 31U) + +/* Check VDDCORE voltage detector low-level parameter */ +#define IS_PWR_VDDCOREVM_LEVEL(__LEVEL__) (((__LEVEL__) == PWR_VDDCORE_THRESHOLD_VOS0) || \ + ((__LEVEL__) == PWR_VDDCORE_THRESHOLD_VOS1)) + +/* Check VddCORE VM mode check parameter */ +#define IS_PWR_VDDCOREVM_MODE(__MODE__) \ + (((__MODE__) == PWR_VDDCOREVM_MODE_NORMAL) ||\ + ((__MODE__) == PWR_VDDCOREVM_MODE_IT_RISING) ||\ + ((__MODE__) == PWR_VDDCOREVM_MODE_IT_FALLING) ||\ + ((__MODE__) == PWR_VDDCOREVM_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == PWR_VDDCOREVM_MODE_EVENT_RISING) ||\ + ((__MODE__) == PWR_VDDCOREVM_MODE_EVENT_FALLING) ||\ + ((__MODE__) == PWR_VDDCOREVM_MODE_EVENT_RISING_FALLING)) + +/* Check PVM type parameter */ +#define IS_PWR_PVM_TYPE(__TYPE__) \ + (((__TYPE__) == PWR_VDDUSB_VM) ||\ + ((__TYPE__) == PWR_VDDIO2_VM) ||\ + ((__TYPE__) == PWR_VDDIO3_VM) ||\ + ((__TYPE__) == PWR_VDDIO4_VM) ||\ + ((__TYPE__) == PWR_VDDIO5_VM) ||\ + ((__TYPE__) == PWR_VDDA_VM)) + +/* Check PVM mode check parameter */ +#define IS_PWR_PVM_MODE(__MODE__) \ + (((__MODE__) == PWR_PVM_MODE_NORMAL) ||\ + ((__MODE__) == PWR_PVM_MODE_IT_RISING) ||\ + ((__MODE__) == PWR_PVM_MODE_IT_FALLING) ||\ + ((__MODE__) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == PWR_PVM_MODE_EVENT_RISING) ||\ + ((__MODE__) == PWR_PVM_MODE_EVENT_FALLING) ||\ + ((__MODE__) == PWR_PVM_MODE_EVENT_RISING_FALLING)) + +/* Check the VddIO parameter */ +#define IS_PWR_VDDIO(__VDDIO__) (((__VDDIO__) == PWR_VDDIO) || \ + ((__VDDIO__) == PWR_VDDIO2) || \ + ((__VDDIO__) == PWR_VDDIO3) || \ + ((__VDDIO__) == PWR_VDDIO4) || \ + ((__VDDIO__) == PWR_VDDIO5)) + +/* Check the VddIO Range parameter */ +#define IS_PWR_VDDIO_RANGE(__RANGE__) (((__RANGE__) == PWR_VDDIO_RANGE_3V3) || \ + ((__RANGE__) == PWR_VDDIO_RANGE_1V8)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32N6xx_HAL_PWR_EX_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc.h (revision 16) @@ -0,0 +1,4664 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_RCC_H +#define STM32N6xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" +#include "stm32n6xx_ll_bus.h" +#include "stm32n6xx_ll_rcc.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + * (allow to configure the PLL in integer and fractional modes) + * Only PLLState field is applicable when its value is different from RCC_PLL_ON + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< Division factor M for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLLFractional; /*!< Fractional part of he VCO mulliplication factor. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFFFF */ + + uint32_t PLLN; /*!< Multiplication factor N for PLL VCO output clock. + In integer mode, this parameter must be a number between Min_Data = 10 and Max_Data = 2500. + In fractional mode, this parameter must be a number between Min_Data = 20 and Max_Data = 500.*/ + + uint32_t PLLP1; /*!< Division factor P1 for system clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 7 */ + + uint32_t PLLP2; /*!< Division factor P2 for system clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 7 */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) and PLLs configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSIDiv; /*!< The division factor of the HSI. + This parameter can be a value of @ref RCC_HSI_Div */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value. + This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t MSIState; /*!< The new state of the MSI. + This parameter can be a value of @ref RCC_MSI_Config */ + + uint32_t MSIFrequency; /*!< The MSI frequency selection. + This parameter can be a value of @ref RCC_MSI_Frequency */ + + uint32_t MSICalibrationValue; /*!< The calibration trimming value. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 */ + + RCC_PLLInitTypeDef PLL1; /*!< PLL1 structure parameters */ + + RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */ + + RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */ + + RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC extended interconnection structure definition + */ +typedef struct +{ + uint32_t ClockSelection; /*!< Specifies ICx clock source. + This parameter can be a value of @ref RCC_IC_Clock_Source */ + + uint32_t ClockDivider; /*!< Specifies ICx clock divider. + This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ +} RCC_ICInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_Clock_Type */ + + uint32_t CPUCLKSource; /*!< The clock source used as CPU clock (CPUCLK). + This parameter can be a value of @ref RCC_CPU_Clock_Source */ + + uint32_t SYSCLKSource; /*!< The clock source used as system bus clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Bus_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock divider for HCLK. + This clock is derived from the system clock divided by the system clock divider. + This parameter can be a value of @ref RCC_HCLK_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock divider for PCLK1. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock divider for PCLK2. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB2_Clock_Source */ + + uint32_t APB4CLKDivider; /*!< The APB4 clock divider for PCLK4. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB4_Clock_Source */ + + uint32_t APB5CLKDivider; /*!< The APB5 clock divider for PCLK5. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB5_Clock_Source */ + + RCC_ICInitTypeDef IC1Selection; /*!< IC1 parameters. + This parameter shall be used when IC1 is selected as CPU clock source (sysa_ck) */ + + RCC_ICInitTypeDef IC2Selection; /*!< IC2 parameters. + This parameter shall be used when IC2 is selected as system bus clock source (sysb_ck) */ + + RCC_ICInitTypeDef IC6Selection; /*!< IC6 parameters. + This parameter shall be used when IC6 is selected as system bus clock source (sysc_ck) */ + + RCC_ICInitTypeDef IC11Selection; /*!< IC11 parameters. + This parameter shall be used when IC11 is selected as system bus clock source (sysd_ck) */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x01U /*!< HSE selected */ +#define RCC_OSCILLATORTYPE_HSI 0x02U /*!< HSI selected */ +#define RCC_OSCILLATORTYPE_LSE 0x04U /*!< LSE selected */ +#define RCC_OSCILLATORTYPE_LSI 0x08U /*!< LSI selected */ +#define RCC_OSCILLATORTYPE_MSI 0x10U /*!< MSI selected */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_HSECFGR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass analog clock activation */ +#define RCC_HSE_BYPASS_DIGITAL (RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass digital clock activation */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_CR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_LSECFGR_LSEBYP | RCC_CR_LSEON) /*!< LSE bypass analog clock activation */ +#define RCC_LSE_BYPASS_DIGITAL (RCC_LSECFGR_LSEEXT | RCC_LSECFGR_LSEBYP | RCC_CR_LSEON) /*!< LSE bypass digital clock activation */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Div HSI Clock Divider + * @{ + */ +#define RCC_HSI_DIV1 LL_RCC_HSI_DIV_1 /*!< HSI clock is not divided */ +#define RCC_HSI_DIV2 LL_RCC_HSI_DIV_2 /*!< HSI clock is divided by 2 */ +#define RCC_HSI_DIV4 LL_RCC_HSI_DIV_4 /*!< HSI clock is divided by 4 */ +#define RCC_HSI_DIV8 LL_RCC_HSI_DIV_8 /*!< HSI clock is divided by 8 */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Calibration_Default HSI Calibration default + * @{ + */ +#define RCC_HSICALIBRATION_DEFAULT 0U /*!< Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_MSI_Config MSI Config + * @{ + */ +#define RCC_MSI_OFF 0U /*!< MSI clock deactivation */ +#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_MSI_Frequency MSI Frequency + * @{ + */ +#define RCC_MSI_FREQ_4MHZ LL_RCC_MSI_FREQ_4MHZ /*!< MSI 4MHz selection */ +#define RCC_MSI_FREQ_16MHZ LL_RCC_MSI_FREQ_16MHZ /*!< MSI 16MHz selection */ +/** + * @} + */ + +/** @defgroup RCC_MSI_Calibration_Default MSI Calibration default + * @{ + */ +#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 1U /*!< PLL deactivation */ +#define RCC_PLL_ON 2U /*!< PLL activation */ +#define RCC_PLL_BYPASS 3U /*!< PLL activation in bypass mode with FREF set as source */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI /*!< MSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE /*!< HSE clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_PIN LL_RCC_PLLSOURCE_I2S_CKIN /*!< External clock I2S_CKIN selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_Clock_Type Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_CPUCLK 0x01U /*!< CPU clock to configure */ +#define RCC_CLOCKTYPE_SYSCLK 0x02U /*!< System bus clock to configure for AXI */ +#define RCC_CLOCKTYPE_HCLK 0x04U /*!< HCLK to configure for AHB */ +#define RCC_CLOCKTYPE_PCLK1 0x08U /*!< PCLK1 to configure for APB1 */ +#define RCC_CLOCKTYPE_PCLK2 0x10U /*!< PCLK2 to configure for APB2 */ +#define RCC_CLOCKTYPE_PCLK4 0x20U /*!< PCLK4 to configure for APB4 */ +#define RCC_CLOCKTYPE_PCLK5 0x40U /*!< PCLK5 to configure for APB5 */ +/** + * @} + */ + +/** @defgroup RCC_CPU_Clock_Source CPU Clock Source + * @{ + */ +#define RCC_CPUCLKSOURCE_HSI LL_RCC_CPU_CLKSOURCE_HSI /*!< HSI selection as CPU clock */ +#define RCC_CPUCLKSOURCE_MSI LL_RCC_CPU_CLKSOURCE_MSI /*!< MSI selection as CPU clock */ +#define RCC_CPUCLKSOURCE_HSE LL_RCC_CPU_CLKSOURCE_HSE /*!< HSE selection as CPU clock */ +#define RCC_CPUCLKSOURCE_IC1 LL_RCC_CPU_CLKSOURCE_IC1 /*!< IC1 selection as CPU clock */ +/** + * @} + */ + +/** @defgroup RCC_CPU_Clock_Source_Status CPU Clock Source Status + * @{ + */ +#define RCC_CPUCLKSOURCE_STATUS_HSI LL_RCC_CPU_CLKSOURCE_STATUS_HSI /*!< HSI used as CPU clock */ +#define RCC_CPUCLKSOURCE_STATUS_MSI LL_RCC_CPU_CLKSOURCE_STATUS_MSI /*!< MSI used as CPU clock */ +#define RCC_CPUCLKSOURCE_STATUS_HSE LL_RCC_CPU_CLKSOURCE_STATUS_HSE /*!< HSE used as CPU clock */ +#define RCC_CPUCLKSOURCE_STATUS_IC1 LL_RCC_CPU_CLKSOURCE_STATUS_IC1 /*!< IC1 used as CPU clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Bus_Clock_Source System Bus Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI /*!< HSI selection as system bus clocks */ +#define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI /*!< MSI selection as system bus clocks */ +#define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE /*!< HSE selection as system bus clocks */ +#define RCC_SYSCLKSOURCE_IC2_IC6_IC11 LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11 /*!< IC2/IC6/IC11 selection as system bus clocks */ +/** + * @} + */ + +/** @defgroup RCC_System_Bus_Clock_Source_Status System Bus Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI /*!< HSI used as system bus clocks */ +#define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI /*!< MSI used as system bus clocks */ +#define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE /*!< HSE used as system bus clocks */ +#define RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11 LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11 /*!< IC2/IC6/IC11 used as system bus clocks */ +/** + * @} + */ + +/** @defgroup RCC_HCLK_Clock_Source HCLK Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 LL_RCC_AHB_DIV_1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 LL_RCC_AHB_DIV_2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 LL_RCC_AHB_DIV_4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 LL_RCC_AHB_DIV_8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 LL_RCC_AHB_DIV_16 /*!< HCLK divided by 16 */ +#define RCC_HCLK_DIV32 LL_RCC_AHB_DIV_32 /*!< HCLK divided by 32 */ +#define RCC_HCLK_DIV64 LL_RCC_AHB_DIV_64 /*!< HCLK divided by 64 */ +#define RCC_HCLK_DIV128 LL_RCC_AHB_DIV_128 /*!< HCLK divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source APB1 Clock Source + * @{ + */ +#define RCC_APB1_DIV1 LL_RCC_APB1_DIV_1 /*!< APB1 not divided */ +#define RCC_APB1_DIV2 LL_RCC_APB1_DIV_2 /*!< APB1 divided by 2 */ +#define RCC_APB1_DIV4 LL_RCC_APB1_DIV_4 /*!< APB1 divided by 4 */ +#define RCC_APB1_DIV8 LL_RCC_APB1_DIV_8 /*!< APB1 divided by 8 */ +#define RCC_APB1_DIV16 LL_RCC_APB1_DIV_16 /*!< APB1 divided by 16 */ +#define RCC_APB1_DIV32 LL_RCC_APB1_DIV_32 /*!< APB1 divided by 32 */ +#define RCC_APB1_DIV64 LL_RCC_APB1_DIV_64 /*!< APB1 divided by 64 */ +#define RCC_APB1_DIV128 LL_RCC_APB1_DIV_128 /*!< APB1 divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Source APB2 Clock Source + * @{ + */ +#define RCC_APB2_DIV1 LL_RCC_APB2_DIV_1 /*!< APB2 not divided */ +#define RCC_APB2_DIV2 LL_RCC_APB2_DIV_2 /*!< APB2 divided by 2 */ +#define RCC_APB2_DIV4 LL_RCC_APB2_DIV_4 /*!< APB2 divided by 4 */ +#define RCC_APB2_DIV8 LL_RCC_APB2_DIV_8 /*!< APB2 divided by 8 */ +#define RCC_APB2_DIV16 LL_RCC_APB2_DIV_16 /*!< APB2 divided by 16 */ +#define RCC_APB2_DIV32 LL_RCC_APB2_DIV_32 /*!< APB2 divided by 32 */ +#define RCC_APB2_DIV64 LL_RCC_APB2_DIV_64 /*!< APB2 divided by 64 */ +#define RCC_APB2_DIV128 LL_RCC_APB2_DIV_128 /*!< APB2 divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Source APB4 Clock Source + * @{ + */ +#define RCC_APB4_DIV1 LL_RCC_APB4_DIV_1 /*!< APB4 not divided */ +#define RCC_APB4_DIV2 LL_RCC_APB4_DIV_2 /*!< APB4 divided by 2 */ +#define RCC_APB4_DIV4 LL_RCC_APB4_DIV_4 /*!< APB4 divided by 4 */ +#define RCC_APB4_DIV8 LL_RCC_APB4_DIV_8 /*!< APB4 divided by 8 */ +#define RCC_APB4_DIV16 LL_RCC_APB4_DIV_16 /*!< APB4 divided by 16 */ +#define RCC_APB4_DIV32 LL_RCC_APB4_DIV_32 /*!< APB4 divided by 32 */ +#define RCC_APB4_DIV64 LL_RCC_APB4_DIV_64 /*!< APB4 divided by 64 */ +#define RCC_APB4_DIV128 LL_RCC_APB4_DIV_128 /*!< APB4 divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Source APB5 Clock Source + * @{ + */ +#define RCC_APB5_DIV1 LL_RCC_APB5_DIV_1 /*!< APB5 not divided */ +#define RCC_APB5_DIV2 LL_RCC_APB5_DIV_2 /*!< APB5 divided by 2 */ +#define RCC_APB5_DIV4 LL_RCC_APB5_DIV_4 /*!< APB5 divided by 4 */ +#define RCC_APB5_DIV8 LL_RCC_APB5_DIV_8 /*!< APB5 divided by 8 */ +#define RCC_APB5_DIV16 LL_RCC_APB5_DIV_16 /*!< APB5 divided by 16 */ +#define RCC_APB5_DIV32 LL_RCC_APB5_DIV_32 /*!< APB5 divided by 32 */ +#define RCC_APB5_DIV64 LL_RCC_APB5_DIV_64 /*!< APB5 divided by 64 */ +#define RCC_APB5_DIV128 LL_RCC_APB5_DIV_128 /*!< APB5 divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_IC_Clock_Source IC Clock Source + * @{ + */ +#define RCC_ICCLKSOURCE_PLL1 LL_RCC_ICCLKSOURCE_PLL1 /*!< ICx clock source selection is PLL1 output */ +#define RCC_ICCLKSOURCE_PLL2 LL_RCC_ICCLKSOURCE_PLL2 /*!< ICx clock source selection is PLL2 output */ +#define RCC_ICCLKSOURCE_PLL3 LL_RCC_ICCLKSOURCE_PLL3 /*!< ICx clock source selection is PLL3 output */ +#define RCC_ICCLKSOURCE_PLL4 LL_RCC_ICCLKSOURCE_PLL4 /*!< ICx clock source selection is PLL4 output */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_DISABLE 0UL /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_CCIPR7_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_CCIPR7_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1 ((0x00UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((0x01UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 4 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((0x02UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 9 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((0x03UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 16 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((0x04UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 25 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV36 ((0x05UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 36 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV49 ((0x06UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 49 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV64 ((0x07UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 64 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV81 ((0x08UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 81 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV100 ((0x09UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 100 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV121 ((0x0AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 121 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV144 ((0x0BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 144 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV169 ((0x0CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 169 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV196 ((0x0DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 196 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV225 ((0x0EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 225 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV256 ((0x0FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 256 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV289 ((0x10UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 289 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV324 ((0x11UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 324 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV361 ((0x12UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 361 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV400 ((0x13UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 400 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV441 ((0x14UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 441 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV484 ((0x15UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 484 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV529 ((0x16UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 529 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV576 ((0x17UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 576 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV625 ((0x18UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 625 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV676 ((0x19UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 676 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV729 ((0x1AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 729 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV784 ((0x1BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 784 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV841 ((0x1CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 841 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV900 ((0x1DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 900 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV961 ((0x1EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 961 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1024 ((0x1FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1024 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1089 ((0x20UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1089 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1156 ((0x21UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1156 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1225 ((0x22UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1225 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1296 ((0x23UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1296 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1369 ((0x24UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1369 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1444 ((0x25UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1444 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1521 ((0x26UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1521 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1600 ((0x27UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1600 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1681 ((0x28UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1681 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1764 ((0x29UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1764 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1849 ((0x2AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1849 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1936 ((0x2BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1936 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2025 ((0x2CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2025 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2116 ((0x2DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2116 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2209 ((0x2EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2209 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2304 ((0x2FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2304 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2401 ((0x30UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2401 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2500 ((0x31UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2500 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2601 ((0x32UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2601 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2704 ((0x33UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2704 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2809 ((0x34UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2809 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2916 ((0x35UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2916 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3025 ((0x36UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3025 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3136 ((0x37UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3136 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3249 ((0x38UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3249 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3364 ((0x39UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3364 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3481 ((0x3AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3481 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3600 ((0x3BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3600 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3721 ((0x3CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3721 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3844 ((0x3DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3844 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3969 ((0x3EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3969 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV4096 ((0x3FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 4096 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Index MCOx Index + * @{ + */ +#define RCC_MCO1 0U /*!< Microcontroller Clock Output 1 */ +#define RCC_MCO2 1U /*!< Microcontroller Clock Output 2 */ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI clock selected as MCO1 source (reset) */ +#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< HSI clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_IC5 LL_RCC_MCO1SOURCE_IC5 /*!< IC5 clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_IC10 LL_RCC_MCO1SOURCE_IC10 /*!< IC10 clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_SYSA LL_RCC_MCO1SOURCE_SYSA /*!< SYSA CPU clock selected as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_HSI LL_RCC_MCO2SOURCE_HSI /*!< HSI clock selected as MCO2 source (reset) */ +#define RCC_MCO2SOURCE_LSE LL_RCC_MCO2SOURCE_LSE /*!< LSE clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_MSI LL_RCC_MCO2SOURCE_MSI /*!< MSI clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_LSI LL_RCC_MCO2SOURCE_LSI /*!< LSI clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_HSE LL_RCC_MCO2SOURCE_HSE /*!< HSE clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_IC15 LL_RCC_MCO2SOURCE_IC15 /*!< IC15 clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_IC20 LL_RCC_MCO2SOURCE_IC20 /*!< IC20 clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_SYSB LL_RCC_MCO2SOURCE_SYSB /*!< SYSB bus clock selected as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO divided by 1 */ +#define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ +#define RCC_MCODIV_3 LL_RCC_MCO1_DIV_3 /*!< MCO divided by 3 */ +#define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ +#define RCC_MCODIV_5 LL_RCC_MCO1_DIV_5 /*!< MCO divided by 5 */ +#define RCC_MCODIV_6 LL_RCC_MCO1_DIV_6 /*!< MCO divided by 6 */ +#define RCC_MCODIV_7 LL_RCC_MCO1_DIV_7 /*!< MCO divided by 7 */ +#define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ +#define RCC_MCODIV_9 LL_RCC_MCO1_DIV_9 /*!< MCO divided by 9 */ +#define RCC_MCODIV_10 LL_RCC_MCO1_DIV_10 /*!< MCO divided by 10 */ +#define RCC_MCODIV_11 LL_RCC_MCO1_DIV_11 /*!< MCO divided by 11 */ +#define RCC_MCODIV_12 LL_RCC_MCO1_DIV_12 /*!< MCO divided by 12 */ +#define RCC_MCODIV_13 LL_RCC_MCO1_DIV_13 /*!< MCO divided by 13 */ +#define RCC_MCODIV_14 LL_RCC_MCO1_DIV_14 /*!< MCO divided by 14 */ +#define RCC_MCODIV_15 LL_RCC_MCO1_DIV_15 /*!< MCO divided by 15 */ +#define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16 /*!< MCO divided by 16 (reset) */ +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupt + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt */ +#define RCC_IT_LSERDY RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt */ +#define RCC_IT_MSIRDY RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt */ +#define RCC_IT_HSIRDY RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt */ +#define RCC_IT_HSERDY RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt */ +#define RCC_IT_PLL1RDY RCC_CIER_PLL1RDYIE /*!< PLL1 Ready Interrupt */ +#define RCC_IT_PLL2RDY RCC_CIER_PLL2RDYIE /*!< PLL2 Ready Interrupt */ +#define RCC_IT_PLL3RDY RCC_CIER_PLL3RDYIE /*!< PLL3 Ready Interrupt */ +#define RCC_IT_PLL4RDY RCC_CIER_PLL4RDYIE /*!< PLL4 Ready Interrupt */ +#define RCC_IT_LSECSS RCC_CIER_LSECSSIE /*!< LSE Clock Security System Interrupt */ +#define RCC_IT_HSECSS RCC_CIER_HSECSSIE /*!< HSE Clock Security System Interrupt */ +#define RCC_IT_WKUP RCC_CIER_WKUPIE /*!< CPU Wakeup Interrupt */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flag + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: SR register + * - 010: LSECFGR register + * - 011: HSECFGR register + * - 100: RSR register + * @{ + */ +/* Flags in the SR register */ +#define RCC_FLAG_LSIRDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_LSIRDY_Pos) /*!< LSI ready flag */ +#define RCC_FLAG_LSERDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_LSERDY_Pos) /*!< LSE ready flag */ +#define RCC_FLAG_HSIRDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_HSIRDY_Pos) /*!< HSI ready flag */ +#define RCC_FLAG_MSIRDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_MSIRDY_Pos) /*!< MSI ready flag */ +#define RCC_FLAG_HSERDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_HSERDY_Pos) /*!< HSE ready flag */ +#define RCC_FLAG_PLL1RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL1RDY_Pos) /*!< PLL1 ready flag */ +#define RCC_FLAG_PLL2RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL2RDY_Pos) /*!< PLL2 ready flag */ +#define RCC_FLAG_PLL3RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL3RDY_Pos) /*!< PLL3 ready flag */ +#define RCC_FLAG_PLL4RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL4RDY_Pos) /*!< PLL4 ready flag */ + +/* Flags in the LSECFGR register */ +#define RCC_FLAG_LSECSSD ((RCC_LSECFGR_REG_INDEX << 5U) | RCC_LSECFGR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ + +/* Flags in the HSECFGR register */ +#define RCC_FLAG_HSECSSD ((RCC_HSECFGR_REG_INDEX << 5U) | RCC_HSECFGR_HSECSSD_Pos) /*!< HSE Clock Security System failure detection flag */ + +/* Flags in the RSR register */ +#define RCC_FLAG_LCKRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LCKRSTF_Pos) /*!< CPU Lockup reset flag */ +#define RCC_FLAG_BORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_PINRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PORRSTF_Pos) /*!< Power-on reset flag */ +#define RCC_FLAG_SFTRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ + +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Config + * @{ + */ +#define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH /*!< LSE high drive capability */ +/** + * @} + */ + +/** @defgroup RCC_Stop_WakeUpClock Stop WakeUp Clock + * @{ + */ +#define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_SYSWAKEUP_CLKSOURCE_HSI /*!< HSI selected as wake up system clock from system Stop (default after reset) */ +#define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_SYSWAKEUP_CLKSOURCE_MSI /*!< MSI selected as wake up system clock from system Stop */ +/** + * @} + */ + + +/** @defgroup RCC_items RCC items + * @brief RCC items to configure attributes on + * @{ + */ +#define RCC_ITEM_LSI (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_LSISEC) +#define RCC_ITEM_LSE (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_LSESEC) +#define RCC_ITEM_MSI (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_MSISEC) +#define RCC_ITEM_HSI (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_HSISEC) +#define RCC_ITEM_HSE (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_HSESEC) +#define RCC_ITEM_PLL1 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL1SEC) +#define RCC_ITEM_PLL2 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL2SEC) +#define RCC_ITEM_PLL3 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL3SEC) +#define RCC_ITEM_PLL4 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL4SEC) +#define RCC_ITEM_IC1 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC1SEC) +#define RCC_ITEM_IC2 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC2SEC) +#define RCC_ITEM_IC3 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC3SEC) +#define RCC_ITEM_IC4 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC4SEC) +#define RCC_ITEM_IC5 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC5SEC) +#define RCC_ITEM_IC6 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC6SEC) +#define RCC_ITEM_IC7 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC7SEC) +#define RCC_ITEM_IC8 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC8SEC) +#define RCC_ITEM_IC9 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC9SEC) +#define RCC_ITEM_IC10 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC10SEC) +#define RCC_ITEM_IC11 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC11SEC) +#define RCC_ITEM_IC12 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC12SEC) +#define RCC_ITEM_IC13 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC13SEC) +#define RCC_ITEM_IC14 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC14SEC) +#define RCC_ITEM_IC15 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC15SEC) +#define RCC_ITEM_IC16 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC16SEC) +#define RCC_ITEM_IC17 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC17SEC) +#define RCC_ITEM_IC18 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC18SEC) +#define RCC_ITEM_IC19 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC19SEC) +#define RCC_ITEM_IC20 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC20SEC) +#define RCC_ITEM_MOD (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_MODSEC) +#define RCC_ITEM_SYS (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_SYSSEC) +#define RCC_ITEM_BUS (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_BUSSEC) +#define RCC_ITEM_PER (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_PERSEC) +#define RCC_ITEM_INT (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_INTSEC) +#define RCC_ITEM_RST (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_RSTSEC) +#define RCC_ITEM_ACLKN (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_ACLKNSEC) +#define RCC_ITEM_ACLKNC (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_ACLKNCSEC) +#define RCC_ITEM_AHBM (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHBMSEC) +#define RCC_ITEM_AHB1 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB1SEC) +#define RCC_ITEM_AHB2 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB2SEC) +#define RCC_ITEM_AHB3 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB3SEC) +#define RCC_ITEM_AHB4 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB4SEC) +#define RCC_ITEM_AHB5 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB5SEC) +#define RCC_ITEM_APB1 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB1SEC) +#define RCC_ITEM_APB2 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB2SEC) +#define RCC_ITEM_APB3 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB3SEC) +#define RCC_ITEM_APB4 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB4SEC) +#define RCC_ITEM_APB5 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB5SEC) +#define RCC_ITEM_NOC (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_NOCSEC) +#define RCC_ITEM_AXISRAM3 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM3PUB) +#define RCC_ITEM_AXISRAM4 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM4PUB) +#define RCC_ITEM_AXISRAM5 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM5PUB) +#define RCC_ITEM_AXISRAM6 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM6PUB) +#define RCC_ITEM_AHBSRAM1 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AHBSRAM1PUB) +#define RCC_ITEM_AHBSRAM2 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AHBSRAM2PUB) +#define RCC_ITEM_BKPSRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_BKPSRAMPUB) +#define RCC_ITEM_AXISRAM1 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM1PUB) +#define RCC_ITEM_AXISRAM2 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM2PUB) +#define RCC_ITEM_FLEXRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_FLEXRAMPUB) +#if defined(CACHEAXI) +#define RCC_ITEM_CACHEAXIRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_CACHEAXIRAMPUB) +#else +#define RCC_ITEM_CACHEAXIRAM (RCC_ITEM_GROUP_MEM) +#endif /* defined(CACHEAXI) */ +#define RCC_ITEM_VENCRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_VENCRAMPUB) + +#define RCC_ITEM_ALL (RCC_ITEM_LSI | RCC_ITEM_LSE | RCC_ITEM_MSI | RCC_ITEM_HSI | RCC_ITEM_HSE | \ + RCC_ITEM_PLL1 | RCC_ITEM_PLL2 | RCC_ITEM_PLL3 | RCC_ITEM_PLL4 | RCC_ITEM_IC1 | \ + RCC_ITEM_IC2 | RCC_ITEM_IC3 | RCC_ITEM_IC4 | RCC_ITEM_IC5 | RCC_ITEM_IC6 | \ + RCC_ITEM_IC7 | RCC_ITEM_IC8 | RCC_ITEM_IC9 | RCC_ITEM_IC10 | RCC_ITEM_IC11 | \ + RCC_ITEM_IC12 | RCC_ITEM_IC13 | RCC_ITEM_IC14 | RCC_ITEM_IC15 | RCC_ITEM_IC16 | \ + RCC_ITEM_IC17 | RCC_ITEM_IC18 | RCC_ITEM_IC19 | RCC_ITEM_IC20 | RCC_ITEM_MOD | \ + RCC_ITEM_SYS | RCC_ITEM_BUS | RCC_ITEM_PER | RCC_ITEM_INT | RCC_ITEM_RST | \ + RCC_ITEM_ACLKN | RCC_ITEM_ACLKNC | RCC_ITEM_AHBM | RCC_ITEM_AHB1 | RCC_ITEM_AHB2 | \ + RCC_ITEM_AHB3 | RCC_ITEM_AHB4 | RCC_ITEM_AHB5 | RCC_ITEM_APB1 | RCC_ITEM_APB2 | \ + RCC_ITEM_APB3 | RCC_ITEM_APB4 | RCC_ITEM_APB5 | RCC_ITEM_NOC | RCC_ITEM_AXISRAM3 | \ + RCC_ITEM_AXISRAM4 | RCC_ITEM_AXISRAM5 | RCC_ITEM_AXISRAM6 | RCC_ITEM_AHBSRAM1 | \ + RCC_ITEM_AHBSRAM2 | RCC_ITEM_BKPSRAM | RCC_ITEM_AXISRAM1 | RCC_ITEM_AXISRAM2 | \ + RCC_ITEM_FLEXRAM | RCC_ITEM_CACHEAXIRAM | RCC_ITEM_VENCRAM) + +#define RCC_ITEM_ALL_CLK (RCC_ITEM_LSI | RCC_ITEM_LSE | RCC_ITEM_MSI | RCC_ITEM_HSI | RCC_ITEM_HSE) +#define RCC_ITEM_ALL_PLL (RCC_ITEM_PLL1 | RCC_ITEM_PLL2 | RCC_ITEM_PLL3 | RCC_ITEM_PLL4) +#define RCC_ITEM_ALL_ICx (RCC_ITEM_IC1 | RCC_ITEM_IC2 | RCC_ITEM_IC3 | RCC_ITEM_IC4 | RCC_ITEM_IC5 | \ + RCC_ITEM_IC6 | RCC_ITEM_IC7 | RCC_ITEM_IC8 | RCC_ITEM_IC9 | RCC_ITEM_IC10 | \ + RCC_ITEM_IC11 | RCC_ITEM_IC12 | RCC_ITEM_IC13 | RCC_ITEM_IC14 | RCC_ITEM_IC15 | \ + RCC_ITEM_IC16 | RCC_ITEM_IC17 | RCC_ITEM_IC18 | RCC_ITEM_IC19 | RCC_ITEM_IC20) +#define RCC_ITEM_ALL_SYSCFG (RCC_ITEM_MOD | RCC_ITEM_SYS | RCC_ITEM_BUS | RCC_ITEM_PER | RCC_ITEM_INT | \ + RCC_ITEM_RST) +#define RCC_ITEM_ALL_BUS (RCC_ITEM_ACLKN | RCC_ITEM_ACLKNC | RCC_ITEM_AHBM | RCC_ITEM_AHB1 | RCC_ITEM_AHB2 | \ + RCC_ITEM_AHB3 | RCC_ITEM_AHB4 | RCC_ITEM_AHB5 | RCC_ITEM_APB1 | RCC_ITEM_APB2 | \ + RCC_ITEM_APB3 | RCC_ITEM_APB4 | RCC_ITEM_APB5 | RCC_ITEM_NOC) +#define RCC_ITEM_ALL_MEM (RCC_ITEM_AXISRAM3 | RCC_ITEM_AXISRAM4 | RCC_ITEM_AXISRAM5 | RCC_ITEM_AXISRAM6 | \ + RCC_ITEM_AHBSRAM1 | RCC_ITEM_AHBSRAM2 | RCC_ITEM_BKPSRAM | RCC_ITEM_AXISRAM1 | \ + RCC_ITEM_AXISRAM2 | RCC_ITEM_FLEXRAM | RCC_ITEM_CACHEAXIRAM | RCC_ITEM_VENCRAM) +/** + * @} + */ + +/** @defgroup RCC_attributes RCC attributes + * @brief RCC privilege/non-privilege, secure/non-secure, public/non-public and lock attributes + * @note Configuration registers of a SECURED item are only accessible from secure state. + * @note Configuration registers of a PRIVILEGED item are only writable from privileged state. + * @note Configuration registers of a PUBLIC and SECURED item are visible from NS (and S) software. + * @note Setting an item to LOCKED, definitively locks the SEC and PRIV attribute setting for this item. + * @{ + */ +#define RCC_ATTR_PRIV (RCC_ATTR_PRIV_MASK | 0x01U) /*!< attribute is privileged */ +#define RCC_ATTR_NPRIV RCC_ATTR_PRIV_MASK /*!< attribute is unprivileged */ + +#define RCC_ATTR_SEC (RCC_ATTR_SEC_MASK | 0x04U) /*!< attribute is secure */ +#define RCC_ATTR_NSEC RCC_ATTR_SEC_MASK /*!< attribute is non-secure */ + +#define RCC_ATTR_PUB (RCC_ATTR_PUB_MASK | 0x10U) /*!< attribute is public */ +#define RCC_ATTR_NPUB RCC_ATTR_PUB_MASK /*!< attribute is not public */ + +#define RCC_ATTR_LOCK (RCC_ATTR_LOCK_MASK | 0x40U) /*!< attribute is locked */ +#define RCC_ATTR_NLOCK RCC_ATTR_LOCK_MASK /*!< attribute is not locked */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_Embedded_Mem_Clock_Enable_Disable Embedded Memory Clock Enable Disable + * @brief Enable or disable the Embedded Memory clock. + * @note After reset, some embedded memory clocks are disabled + * and the application software has to enable these memory clocks before using them. + * @{ + */ + +#define __HAL_RCC_AXISRAM1_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM1) +#define __HAL_RCC_AXISRAM1_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM1) + +#define __HAL_RCC_AXISRAM2_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM2) +#define __HAL_RCC_AXISRAM2_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM2) + +#define __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM3) +#define __HAL_RCC_AXISRAM3_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM3) + +#define __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM4) +#define __HAL_RCC_AXISRAM4_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM4) + +#define __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM5) +#define __HAL_RCC_AXISRAM5_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM5) + +#define __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM6) +#define __HAL_RCC_AXISRAM6_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM6) + +#define __HAL_RCC_AHBSRAM1_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AHBSRAM1) +#define __HAL_RCC_AHBSRAM1_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AHBSRAM1) + +#define __HAL_RCC_AHBSRAM2_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AHBSRAM2) +#define __HAL_RCC_AHBSRAM2_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AHBSRAM2) + +#define __HAL_RCC_BKPSRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_BKPSRAM) +#define __HAL_RCC_BKPSRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_BKPSRAM) + +#define __HAL_RCC_FLEXRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_FLEXRAM) +#define __HAL_RCC_FLEXRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_FLEXRAM) + +#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_CACHEAXIRAM) +#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_CACHEAXIRAM) + +#define __HAL_RCC_VENCRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_VENCRAM) +#define __HAL_RCC_VENCRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_VENCRAM) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_ADC12_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ADC12) +#define __HAL_RCC_ADC12_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ADC12) + +#define __HAL_RCC_GPDMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPDMA1) +#define __HAL_RCC_GPDMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_GPDMA1) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_ADF1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADF1) +#define __HAL_RCC_ADF1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADF1) + +#define __HAL_RCC_MDF1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_MDF1) +#define __HAL_RCC_MDF1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_MDF1) + +#define __HAL_RCC_RAMCFG_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_RAMCFG) +#define __HAL_RCC_RAMCFG_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_RAMCFG) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @note IAC, RIFSC and RISAF peripheral clocks are always security-protected and thus hidden + * to the non-secure application. + * @{ + */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_CRYP) +#define __HAL_RCC_CRYP_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_CRYP) +#endif /* CRYP */ + +#define __HAL_RCC_HASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HASH) +#define __HAL_RCC_HASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HASH) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_IAC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IAC) +#define __HAL_RCC_IAC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IAC) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_RIFSC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RIFSC) +#define __HAL_RCC_RIFSC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RIFSC) +#endif /* CPU_IN_SECURE_STATE */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_RISAF_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RISAF) +#define __HAL_RCC_RISAF_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RISAF) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_SAES) +#define __HAL_RCC_SAES_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_SAES) +#endif /* SAES */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @note PWR peripheral clock is always security-protected and thus hidden to the non-secure + * application. + * @{ + */ + +#define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_CRC) +#define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_CRC) + +#define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOA) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOB) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOC) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD) +#define __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOD) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOE) +#define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOE) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOF) +#define __HAL_RCC_GPIOF_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOF) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG) +#define __HAL_RCC_GPIOG_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOG) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH) +#define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPION_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPION) +#define __HAL_RCC_GPION_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPION) + +#define __HAL_RCC_GPIOO_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOO) +#define __HAL_RCC_GPIOO_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOO) + +#define __HAL_RCC_GPIOP_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOP) +#define __HAL_RCC_GPIOP_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOP) + +#define __HAL_RCC_GPIOQ_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOQ) +#define __HAL_RCC_GPIOQ_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOQ) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_PWR_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR) +#define __HAL_RCC_PWR_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_PWR) +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Peripheral_Clock_Enable_Disable AHB5 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB5 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA2D_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_DMA2D) +#define __HAL_RCC_DMA2D_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_DMA2D) + +#if defined(ETH1) +#define __HAL_RCC_ETH1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1) +#define __HAL_RCC_ETH1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1) + +#define __HAL_RCC_ETH1MAC_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1MAC) +#define __HAL_RCC_ETH1MAC_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1MAC) + +#define __HAL_RCC_ETH1TX_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1TX) +#define __HAL_RCC_ETH1TX_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1TX) + +#define __HAL_RCC_ETH1RX_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1RX) +#define __HAL_RCC_ETH1RX_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1RX) +#endif /* ETH1 */ + +#define __HAL_RCC_FMC_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_FMC) +#define __HAL_RCC_FMC_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_FMC) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_GFXMMU) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_GPU2D) +#define __HAL_RCC_GPU2D_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_GPU2D) +#endif /* GPU2D */ + +#define __HAL_RCC_HPDMA1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_HPDMA1) +#define __HAL_RCC_HPDMA1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_HPDMA1) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_JPEG) +#define __HAL_RCC_JPEG_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_JPEG) +#endif /* JPEG */ + +#define __HAL_RCC_XSPI1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI1) +#define __HAL_RCC_XSPI1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI1) + +#define __HAL_RCC_XSPI2_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI2) +#define __HAL_RCC_XSPI2_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI2) + +#define __HAL_RCC_XSPI3_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI3) +#define __HAL_RCC_XSPI3_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI3) + +#define __HAL_RCC_XSPIM_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPIM) +#define __HAL_RCC_XSPIM_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPIM) + +#define __HAL_RCC_MCE1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE1) +#define __HAL_RCC_MCE1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE1) + +#define __HAL_RCC_MCE2_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE2) +#define __HAL_RCC_MCE2_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE2) + +#define __HAL_RCC_MCE3_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE3) +#define __HAL_RCC_MCE3_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE3) + +#define __HAL_RCC_MCE4_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE4) +#define __HAL_RCC_MCE4_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE4) + +#define __HAL_RCC_CACHEAXI_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_CACHEAXI) +#define __HAL_RCC_CACHEAXI_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_CACHEAXI) + +#define __HAL_RCC_NPU_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_NPU) +#define __HAL_RCC_NPU_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_NPU) + +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_PSSI) + +#define __HAL_RCC_SDMMC1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_SDMMC1) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_SDMMC1) + +#define __HAL_RCC_SDMMC2_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_SDMMC2) + +#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG1) +#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTG1) + +#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1) +#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1) + +#define __HAL_RCC_USB2_OTG_HS_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG2) +#define __HAL_RCC_USB2_OTG_HS_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTG2) + +#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY2) +#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTGPHY2) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_FDCAN_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_FDCAN) +#define __HAL_RCC_FDCAN_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_FDCAN) + +#define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) + +#define __HAL_RCC_I2C2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2) + +#define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) + +#define __HAL_RCC_I3C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I3C1) +#define __HAL_RCC_I3C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I3C1) + +#define __HAL_RCC_I3C2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I3C2) +#define __HAL_RCC_I3C2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I3C2) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_MDIOS_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_MDIOS) +#define __HAL_RCC_MDIOS_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_MDIOS) + +#define __HAL_RCC_SPDIFRX1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPDIFRX1) +#define __HAL_RCC_SPDIFRX1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPDIFRX1) + +#define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) + +#define __HAL_RCC_SPI3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI3) +#define __HAL_RCC_SPI3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI3) + +#define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) + +#define __HAL_RCC_TIM3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3) +#define __HAL_RCC_TIM3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM3) + +#define __HAL_RCC_TIM4_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM4) +#define __HAL_RCC_TIM4_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM4) + +#define __HAL_RCC_TIM5_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5) +#define __HAL_RCC_TIM5_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM5) + +#define __HAL_RCC_TIM6_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6) +#define __HAL_RCC_TIM6_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM6) + +#define __HAL_RCC_TIM7_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7) +#define __HAL_RCC_TIM7_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM7) + +#define __HAL_RCC_TIM10_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM10) +#define __HAL_RCC_TIM10_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM10) + +#define __HAL_RCC_TIM11_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM11) +#define __HAL_RCC_TIM11_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM11) + +#define __HAL_RCC_TIM12_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM12) +#define __HAL_RCC_TIM12_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM12) + +#define __HAL_RCC_TIM13_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM13) +#define __HAL_RCC_TIM13_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM13) + +#define __HAL_RCC_TIM14_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM14) +#define __HAL_RCC_TIM14_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM14) + +#define __HAL_RCC_USART2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_USART2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2) + +#define __HAL_RCC_USART3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3) +#define __HAL_RCC_USART3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART3) + +#define __HAL_RCC_UART4_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART4) +#define __HAL_RCC_UART4_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART4) + +#define __HAL_RCC_UART5_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART5) +#define __HAL_RCC_UART5_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART5) + +#define __HAL_RCC_UART7_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART7) +#define __HAL_RCC_UART7_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART7) + +#define __HAL_RCC_UART8_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART8) +#define __HAL_RCC_UART8_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART8) + +#define __HAL_RCC_UCPD1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1) +#define __HAL_RCC_UCPD1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1) + +#define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1) +#define __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1) + +#define __HAL_RCC_SAI2_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI2) +#define __HAL_RCC_SAI2_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI2) + +#define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) + +#define __HAL_RCC_SPI4_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4) +#define __HAL_RCC_SPI4_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI4) + +#define __HAL_RCC_SPI5_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5) +#define __HAL_RCC_SPI5_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI5) + +#define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) + +#define __HAL_RCC_TIM8_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM8) +#define __HAL_RCC_TIM8_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM8) + +#define __HAL_RCC_TIM9_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM9) +#define __HAL_RCC_TIM9_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM9) + +#define __HAL_RCC_TIM15_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM15) +#define __HAL_RCC_TIM15_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM15) + +#define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) + +#define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) +#define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_TIM18_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM18) +#define __HAL_RCC_TIM18_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM18) + +#define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) + +#define __HAL_RCC_USART6_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART6) +#define __HAL_RCC_USART6_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART6) + +#define __HAL_RCC_UART9_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_UART9) +#define __HAL_RCC_UART9_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_UART9) + +#define __HAL_RCC_USART10_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART10) +#define __HAL_RCC_USART10_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART10) + +/** + * @} + */ + +/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable + * @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DBGMCU_CLK_ENABLE() LL_BUS_EnableClock(LL_APB3); +#define __HAL_RCC_DBGMCU_CLK_DISABLE() LL_BUS_DisableClock(LL_APB3); + +/** + * @} + */ + +/** @defgroup RCC_APB4_Peripheral_Clock_Enable_Disable APB4 Peripheral Clock Enable Disable + * @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @note BSEC peripheral clock is always security-protected and thus hidden to the non-secure + * application. + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_BSEC_CLK_ENABLE() LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC) +#define __HAL_RCC_BSEC_CLK_DISABLE() LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_BSEC) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_DTS_CLK_ENABLE() LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_DTS) +#define __HAL_RCC_DTS_CLK_DISABLE() LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_DTS) + +#define __HAL_RCC_HDP_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_HDP) +#define __HAL_RCC_HDP_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_HDP) + +#define __HAL_RCC_I2C4_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_I2C4) +#define __HAL_RCC_I2C4_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_I2C4) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM2) + +#define __HAL_RCC_LPTIM3_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM3) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM3) + +#define __HAL_RCC_LPTIM4_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM4) + +#define __HAL_RCC_LPTIM5_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM5) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPUART1) +#define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPUART1) + +#define __HAL_RCC_RTC_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_RTC) +#define __HAL_RCC_RTC_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_RTC) + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_RTCAPB) + +#define __HAL_RCC_SPI6_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SPI6) +#define __HAL_RCC_SPI6_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_SPI6) + +#define __HAL_RCC_SYSCFG_CLK_ENABLE() LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_SYSCFG) + +#define __HAL_RCC_VREFBUF_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_VREFBUF) +#define __HAL_RCC_VREFBUF_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_VREFBUF) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Peripheral_Clock_Enable_Disable APB5 Peripheral Clock Enable Disable + * @brief Enable or disable the APB5 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_CSI_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_CSI) +#define __HAL_RCC_CSI_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_CSI) + +#define __HAL_RCC_DCMIPP_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_DCMIPP) +#define __HAL_RCC_DCMIPP_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_DCMIPP) + +#define __HAL_RCC_GFXTIM_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_GFXTIM) + +#define __HAL_RCC_LTDC_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_LTDC) + +#define __HAL_RCC_VENC_CLK_ENABLE() do { \ + LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_VENC); \ + LL_BUS_EnableClock(LL_APB5); \ + } while(0) +#define __HAL_RCC_VENC_CLK_DISABLE() do { \ + LL_BUS_DisableClock(LL_APB5); \ + LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_VENC); \ + } while(0) + +/** + * @} + */ + +/** @defgroup RCC_MISC_Configuration_Clock_Enable_Disable Misc Configuration Clock Enable Disable + * @brief Enable or disable the misc configuration clock. + * @note After reset, the misc configuration clock is disabled and + * the application software has to enable this clock before using it. + * @note DBG clock is always security-protected and thus hidden to the non-secure application. + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_DBG_CLK_ENABLE() LL_MISC_EnableClock(LL_DBG) +#define __HAL_RCC_DBG_CLK_DISABLE() LL_MISC_DisableClock(LL_DBG) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_XSPIPHYCOMP_CLK_ENABLE() LL_MISC_EnableClock(LL_XSPIPHYCOMP) +#define __HAL_RCC_XSPIPHYCOMP_CLK_DISABLE() LL_MISC_DisableClock(LL_XSPIPHYCOMP) + +#define __HAL_RCC_PER_CLK_ENABLE() LL_MISC_EnableClock(LL_PER) +#define __HAL_RCC_PER_CLK_DISABLE() LL_MISC_DisableClock(LL_PER) + +/** + * @} + */ + +/** @defgroup RCC_Embedded_Mem_Clock_Status Embedded Memory Clock Enabled Status + * @brief Check whether the embedded memory clock is enabled or not. + * @note After reset, some embedded memory clocks are disabled + * and the application software has to enable these memory clocks before using them. + * @{ + */ + +#define __HAL_RCC_AXISRAM1_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM1) +#define __HAL_RCC_AXISRAM2_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM2) +#define __HAL_RCC_AXISRAM3_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM3) +#define __HAL_RCC_AXISRAM4_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM4) +#define __HAL_RCC_AXISRAM5_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM5) +#define __HAL_RCC_AXISRAM6_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM6) +#define __HAL_RCC_AHBSRAM1_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AHBSRAM1) +#define __HAL_RCC_AHBSRAM2_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AHBSRAM2) +#define __HAL_RCC_BKPSRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_BKPSRAM) +#define __HAL_RCC_FLEXRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_FLEXRAM) +#define __HAL_RCC_CACHEAXIRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_CACHEAXIRAM) +#define __HAL_RCC_VENCRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_VENCRAM) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Status AHB1 Peripheral Clock Enabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ADC12) + +#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_GPDMA1) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Enable_Status AHB2 Peripheral Clock Enabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_ADF1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADF1) + +#define __HAL_RCC_MDF1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_MDF1) + +#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_RAMCFG) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Enable_Status AHB3 Peripheral Clock Enabled Status + * @brief Check whether the AHB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_CRYP) +#endif /* CRYP */ + +#define __HAL_RCC_HASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HASH) + +#define __HAL_RCC_IAC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IAC) + +#define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) + +#define __HAL_RCC_RIFSC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RIFSC) + +#define __HAL_RCC_RISAF_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RISAF) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_SAES) +#endif /* SAES */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Enable_Status AHB4 Peripheral Clock Enabled Status + * @brief Check whether the AHB4 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_CRC) + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOA) + +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOB) + +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOC) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOD) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOE) + +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOF) + +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOG) + +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPION_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPION) + +#define __HAL_RCC_GPIOO_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOO) + +#define __HAL_RCC_GPIOP_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOP) + +#define __HAL_RCC_GPIOQ_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOQ) + +#define __HAL_RCC_PWR_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_PWR) + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Enable_Status AHB5 Peripheral Clock Enabled Status + * @brief Check whether the AHB5 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_DMA2D) + +#if defined(ETH1) +#define __HAL_RCC_ETH1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1) + +#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1MAC) + +#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1TX) + +#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1RX) +#endif /* ETH1 */ + +#define __HAL_RCC_FMC_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_FMC) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_GFXMMU) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_GPU2D) +#endif /* GPU2D */ + +#define __HAL_RCC_HPDMA1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_HPDMA1) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_JPEG) +#endif /* JPEG */ + +#define __HAL_RCC_XSPI1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI1) + +#define __HAL_RCC_XSPI2_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI2) + +#define __HAL_RCC_XSPI3_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI3) + +#define __HAL_RCC_XSPIM_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPIM) + +#define __HAL_RCC_MCE1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE1) + +#define __HAL_RCC_MCE2_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE2) + +#define __HAL_RCC_MCE3_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE3) + +#define __HAL_RCC_MCE4_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE4) + +#define __HAL_RCC_CACHEAXI_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_CACHEAXI) + +#define __HAL_RCC_NPU_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_NPU) + +#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_PSSI) + +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_SDMMC1) + +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_SDMMC2) + +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTG1) + +#define __HAL_RCC_USB1_OTG_HS_PHY_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTGPHY1) + +#define __HAL_RCC_USB2_OTG_HS_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTG2) + +#define __HAL_RCC_USB2_OTG_HS_PHY_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTGPHY2) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Status APB1 Peripheral Clock Enabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_FDCAN) + +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) + +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2) + +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) + +#define __HAL_RCC_I3C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I3C1) + +#define __HAL_RCC_I3C2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I3C2) + +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_MDIOS) + +#define __HAL_RCC_SPDIFRX1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPDIFRX1) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) + +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI3) + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) + +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM3) + +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM4) + +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM5) + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM6) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM7) + +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM10) + +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM11) + +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM12) + +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM13) + +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM14) + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART2) + +#define __HAL_RCC_USART3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART3) + +#define __HAL_RCC_UART4_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART4) + +#define __HAL_RCC_UART5_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART5) + +#define __HAL_RCC_UART7_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART7) + +#define __HAL_RCC_UART8_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART8) + +#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_UCPD1) + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Status APB2 Peripheral Clock Enabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1) + +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI2) + +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) + +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI4) + +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI5) + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) + +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM8) + +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM9) + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM15) + +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) + +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_TIM18_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM18) + +#define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) + +#define __HAL_RCC_USART6_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART6) + +#define __HAL_RCC_UART9_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_UART9) + +#define __HAL_RCC_USART10_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART10) + +/** + * @} + */ + + +/** @defgroup RCC_APB3_Clock_Enable_Status APB3 Peripheral Clock Enabled Status + * @brief Check whether the APB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() LL_BUS_IsEnabledClock(LL_APB3); + +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Enable_Status APB4 Peripheral Clock Enabled Status + * @brief Check whether the APB4 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_BSEC_IS_CLK_ENABLED() LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_BSEC) + +#define __HAL_RCC_DTS_IS_CLK_ENABLED() LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_DTS) + +#define __HAL_RCC_HDP_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_HDP) + +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_I2C4) + +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM2) + +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM3) + +#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM4) + +#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM5) + +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPUART1) + +#define __HAL_RCC_RTC_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_RTC) + +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_RTCAPB) + +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_SPI6) + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_SYSCFG) + +#define __HAL_RCC_VREFBUF_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_VREFBUF) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Enable_Status APB5 Peripheral Clock Enabled Status + * @brief Check whether the APB5 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_CSI_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_CSI) + +#define __HAL_RCC_DCMIPP_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_DCMIPP) + +#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_GFXTIM) + +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_LTDC) + +#define __HAL_RCC_VENC_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_VENC) + +/** + * @} + */ + +/** @defgroup RCC_MISC_Configuration_Clock_Enable_Status Misc Configuration Clock Enabled Status + * @brief Check whether the misc configuration clock is enabled or not. + * @note After reset, the misc configuration clock is disabled and + * the application software has to enable this clock before using it. + * @{ + */ + +#define __HAL_RCC_DBG_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_DBG) + +#define __HAL_RCC_MCO1_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_MCO1) + +#define __HAL_RCC_MCO2_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_MCO2) + +#define __HAL_RCC_XSPIPHYCOMP_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_XSPIPHYCOMP) + +#define __HAL_RCC_PER_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_PER) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTSR, 0x00000030UL); +#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTSR, 0UL) + +#define __HAL_RCC_GPDMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1) +#define __HAL_RCC_GPDMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1) + +#define __HAL_RCC_ADC12_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12) +#define __HAL_RCC_ADC12_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTSR, 0x00031000UL); +#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTSR, 0UL) + +#define __HAL_RCC_ADF1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADF1) +#define __HAL_RCC_ADF1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADF1) + +#define __HAL_RCC_MDF1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_MDF1) +#define __HAL_RCC_MDF1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_MDF1) + +#define __HAL_RCC_RAMCFG_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RAMCFG) +#define __HAL_RCC_RAMCFG_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RAMCFG) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @note IAC peripheral reset is always security-protected and thus hidden to the non-secure + * application. + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTSR, 0x00000517UL); +#else +#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTSR, 0x00000117UL); +#endif /* CPU_IN_SECURE_STATE */ +#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTSR, 0UL) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_IAC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IAC) +#define __HAL_RCC_IAC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IAC) +#endif /* CPU_IN_SECURE_STATE */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_CRYP) +#define __HAL_RCC_CRYP_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_CRYP) +#endif /* CRYP */ + +#define __HAL_RCC_HASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HASH) +#define __HAL_RCC_HASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HASH) + +#define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) + +#define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) + +#if defined(SAES) +#define __HAL_RCC_SAES_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_SAES) +#define __HAL_RCC_SAES_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_SAES) +#endif /* SAES */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset + * @brief Force or release AHB4 peripheral reset. + * @note PWR peripheral reset is always security-protected and thus hidden to the non-secure + * application. + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTSR, 0x000DE0FFUL); +#else +#define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTSR, 0x0005E0FFUL); +#endif /* CPU_IN_SECURE_STATE */ +#define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTSR, 0UL) + +#define __HAL_RCC_CRC_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_CRC) +#define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_CRC) + +#define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA) + +#define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB) + +#define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC) + +#define __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD) +#define __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD) + +#define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE) +#define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE) + +#define __HAL_RCC_GPIOF_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF) +#define __HAL_RCC_GPIOF_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF) + +#define __HAL_RCC_GPIOG_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG) +#define __HAL_RCC_GPIOG_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG) + +#define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH) +#define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPION_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPION) +#define __HAL_RCC_GPION_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPION) + +#define __HAL_RCC_GPIOO_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOO) +#define __HAL_RCC_GPIOO_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOO) + +#define __HAL_RCC_GPIOP_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOP) +#define __HAL_RCC_GPIOP_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOP) + +#define __HAL_RCC_GPIOQ_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOQ) +#define __HAL_RCC_GPIOQ_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOQ) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_PWR_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_PWR) +#define __HAL_RCC_PWR_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_PWR) +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Force_Release_Reset AHB5 Peripheral Force Release Reset + * @brief Force or release AHB5 peripheral reset. + * @{ + */ + +/* Caution: The two following macros should only be called from code running in internal RAM + * since it resets the external peripheral memory interfaces. + */ +#define __HAL_RCC_AHB5_FORCE_RESET() WRITE_REG(RCC->AHB5RSTSR, 0xFF9A31FBUL) +#define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTSR, 0UL) + +#define __HAL_RCC_DMA2D_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_DMA2D) +#define __HAL_RCC_DMA2D_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_DMA2D) + +#if defined(ETH1) +#define __HAL_RCC_ETH1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_ETH1); +#define __HAL_RCC_ETH1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_ETH1); +#endif /* ETH1 */ + +#define __HAL_RCC_FMC_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_FMC) +#define __HAL_RCC_FMC_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_FMC) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_GFXMMU) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_GPU2D) +#define __HAL_RCC_GPU2D_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_GPU2D) +#endif /* GPU2D */ + +#define __HAL_RCC_HPDMA1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_HPDMA1) +#define __HAL_RCC_HPDMA1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_HPDMA1) + +#define __HAL_RCC_XSPI1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI1) +#define __HAL_RCC_XSPI1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI1) + +#define __HAL_RCC_XSPI2_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI2) +#define __HAL_RCC_XSPI2_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI2) + +#define __HAL_RCC_XSPI3_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI3); +#define __HAL_RCC_XSPI3_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI3); + +#define __HAL_RCC_XSPIM_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPIM) +#define __HAL_RCC_XSPIM_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPIM) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_JPEG) +#define __HAL_RCC_JPEG_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_JPEG) +#endif /* JPEG */ + +#define __HAL_RCC_CACHEAXI_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_CACHEAXI); +#define __HAL_RCC_CACHEAXI_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_CACHEAXI); + +#define __HAL_RCC_NPU_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_NPU); +#define __HAL_RCC_NPU_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_NPU); + +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_PSSI) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_PSSI) + +#define __HAL_RCC_SDMMC1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_SDMMC1) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_SDMMC1) + +#define __HAL_RCC_SDMMC2_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_SDMMC2) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_SDMMC2) + +#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG1) +#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG1) + +#define __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTGPHY1); +#define __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTGPHY1); + +#define __HAL_RCC_USB1_OTG_HS_CTL_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG1PHYCTL); +#define __HAL_RCC_USB1_OTG_HS_CTL_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG1PHYCTL); + +#define __HAL_RCC_USB2_OTG_HS_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG2) +#define __HAL_RCC_USB2_OTG_HS_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG2) + +#define __HAL_RCC_USB2_OTG_HS_PHY_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTGPHY2); +#define __HAL_RCC_USB2_OTG_HS_PHY_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTGPHY2); + +#define __HAL_RCC_USB2_OTG_HS_CTL_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG2PHYCTL); +#define __HAL_RCC_USB2_OTG_HS_CTL_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG2PHYCTL); + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB1_FORCE_RESET() do { \ + WRITE_REG(RCC->APB1RSTSR1, 0xC3FFF3FFUL); \ + WRITE_REG(RCC->APB1RSTSR2, 0x00040120UL); \ + } while(0) +#define __HAL_RCC_APB1_RELEASE_RESET() do { \ + WRITE_REG(RCC->APB1RSTSR1, 0UL); \ + WRITE_REG(RCC->APB1RSTSR2, 0UL); \ + } while(0) + +#define __HAL_RCC_FDCAN_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_FDCAN) +#define __HAL_RCC_FDCAN_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_FDCAN) + +#define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) + +#define __HAL_RCC_I2C2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2) + +#define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) + +#define __HAL_RCC_I3C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C1) +#define __HAL_RCC_I3C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C1) + +#define __HAL_RCC_I3C2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C2) +#define __HAL_RCC_I3C2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C2) + +#define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_MDIOS_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_MDIOS) +#define __HAL_RCC_MDIOS_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_MDIOS) + +#define __HAL_RCC_SPDIFRX1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPDIFRX1) +#define __HAL_RCC_SPDIFRX1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPDIFRX1) + +#define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) + +#define __HAL_RCC_SPI3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3) +#define __HAL_RCC_SPI3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3) + +#define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) + +#define __HAL_RCC_TIM3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3) +#define __HAL_RCC_TIM3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3) + +#define __HAL_RCC_TIM4_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4) +#define __HAL_RCC_TIM4_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4) + +#define __HAL_RCC_TIM5_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5) +#define __HAL_RCC_TIM5_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5) + +#define __HAL_RCC_TIM6_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6) +#define __HAL_RCC_TIM6_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6) + +#define __HAL_RCC_TIM7_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7) +#define __HAL_RCC_TIM7_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7) + +#define __HAL_RCC_TIM10_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM10) +#define __HAL_RCC_TIM10_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM10) + +#define __HAL_RCC_TIM11_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM11) +#define __HAL_RCC_TIM11_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM11) + +#define __HAL_RCC_TIM12_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12) +#define __HAL_RCC_TIM12_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12) + +#define __HAL_RCC_TIM13_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13) +#define __HAL_RCC_TIM13_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13) + +#define __HAL_RCC_TIM14_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14) +#define __HAL_RCC_TIM14_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14) + +#define __HAL_RCC_UCPD1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1) +#define __HAL_RCC_UCPD1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1) + +#define __HAL_RCC_USART2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_USART2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2) + +#define __HAL_RCC_USART3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3) +#define __HAL_RCC_USART3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3) + +#define __HAL_RCC_UART4_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4) +#define __HAL_RCC_UART4_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4) + +#define __HAL_RCC_UART5_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5) +#define __HAL_RCC_UART5_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5) + +#define __HAL_RCC_UART7_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7) +#define __HAL_RCC_UART7_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7) + +#define __HAL_RCC_UART8_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8) +#define __HAL_RCC_UART8_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTSR, 0x007FB0F3UL) +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTSR, 0UL) + +#define __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1) +#define __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1) + +#define __HAL_RCC_SAI2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI2) +#define __HAL_RCC_SAI2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI2) + +#define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) + +#define __HAL_RCC_SPI4_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4) +#define __HAL_RCC_SPI4_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4) + +#define __HAL_RCC_SPI5_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5) +#define __HAL_RCC_SPI5_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5) + +#define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) + +#define __HAL_RCC_TIM8_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8) +#define __HAL_RCC_TIM8_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8) + +#define __HAL_RCC_TIM9_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9) +#define __HAL_RCC_TIM9_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9) + +#define __HAL_RCC_TIM15_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15) +#define __HAL_RCC_TIM15_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15) + +#define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) + +#define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) +#define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_TIM18_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM18) +#define __HAL_RCC_TIM18_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM18) + +#define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) + +#define __HAL_RCC_USART6_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6) +#define __HAL_RCC_USART6_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6) + +#define __HAL_RCC_UART9_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9) +#define __HAL_RCC_UART9_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9) + +#define __HAL_RCC_USART10_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10) +#define __HAL_RCC_USART10_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Force_Release_Reset APB4 Peripheral Force Release Reset + * @brief Force or release APB4 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB4_FORCE_RESET() do { \ + WRITE_REG(RCC->APB4RSTSR1, 0x00019EACUL); \ + WRITE_REG(RCC->APB4RSTSR2, 0x00000005UL); \ + } while(0) +#define __HAL_RCC_APB4_RELEASE_RESET() do { \ + WRITE_REG(RCC->APB4RSTSR1, 0UL); \ + WRITE_REG(RCC->APB4RSTSR2, 0UL); \ + } while(0) + +#define __HAL_RCC_DTS_FORCE_RESET() LL_APB4_GRP2_ForceReset(LL_APB4_GRP2_PERIPH_DTS) +#define __HAL_RCC_DTS_RELEASE_RESET() LL_APB4_GRP2_ReleaseReset(LL_APB4_GRP2_PERIPH_DTS) + +#define __HAL_RCC_HDP_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_HDP) +#define __HAL_RCC_HDP_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_HDP) + +#define __HAL_RCC_I2C4_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_I2C4) +#define __HAL_RCC_I2C4_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_I2C4) + +#define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2) + +#define __HAL_RCC_LPTIM3_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3) +#define __HAL_RCC_LPTIM3_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3) + +#define __HAL_RCC_LPTIM4_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4) +#define __HAL_RCC_LPTIM4_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4) + +#define __HAL_RCC_LPTIM5_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5) +#define __HAL_RCC_LPTIM5_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5) + +#define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPUART1) +#define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPUART1) + +#define __HAL_RCC_RTC_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_RTC) +#define __HAL_RCC_RTC_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_RTC) + +#define __HAL_RCC_SPI6_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6) +#define __HAL_RCC_SPI6_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6) + +#define __HAL_RCC_SYSCFG_FORCE_RESET() LL_APB4_GRP2_ForceReset(LL_APB4_GRP2_PERIPH_SYSCFG) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() LL_APB4_GRP2_ReleaseReset(LL_APB4_GRP2_PERIPH_SYSCFG) + +#define __HAL_RCC_VREFBUF_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_VREFBUF) +#define __HAL_RCC_VREFBUF_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_VREFBUF) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Force_Release_Reset APB5 Peripheral Force Release Reset + * @brief Force or release APB5 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB5_FORCE_RESET() WRITE_REG(RCC->APB5RSTSR, 0x00000076UL) +#define __HAL_RCC_APB5_RELEASE_RESET() WRITE_REG(RCC->APB5RSTSR, 0UL) + +#define __HAL_RCC_CSI_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_CSI) +#define __HAL_RCC_CSI_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_CSI) + +#define __HAL_RCC_DCMIPP_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_DCMIPP) +#define __HAL_RCC_DCMIPP_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_DCMIPP) + +#define __HAL_RCC_GFXTIM_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_GFXTIM) +#define __HAL_RCC_GFXTIM_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_GFXTIM) + +#define __HAL_RCC_LTDC_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_LTDC) + +#define __HAL_RCC_VENC_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_VENC) +#define __HAL_RCC_VENC_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_VENC) + +/** + * @} + */ + +/** @defgroup RCC_MISC_Configuration_Force_Release_Reset Misc Configuration Force Release Reset + * @brief Force or release misc configuration reset. + * @note DBG reset is always security-protected and thus hidden to the non-secure application. + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_DBG_FORCE_RESET() LL_MISC_ForceReset(LL_DBG) +#define __HAL_RCC_DBG_RELEASE_RESET() LL_MISC_ReleaseReset(LL_DBG) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_XSPIPHY1_FORCE_RESET() LL_MISC_ForceReset(LL_XSPIPHY1) +#define __HAL_RCC_XSPIPHY1_RELEASE_RESET() LL_MISC_ReleaseReset(LL_XSPIPHY1) + +#define __HAL_RCC_XSPIPHY2_FORCE_RESET() LL_MISC_ForceReset(LL_XSPIPHY2) +#define __HAL_RCC_XSPIPHY2_RELEASE_RESET() LL_MISC_ReleaseReset(LL_XSPIPHY2) + +#define __HAL_RCC_SDMMC1DLL_FORCE_RESET() LL_MISC_ForceReset(LL_SDMMC1DLL) +#define __HAL_RCC_SDMMC1DLL_RELEASE_RESET() LL_MISC_ReleaseReset(LL_SDMMC1DLL) + +#define __HAL_RCC_SDMMC2DLL_FORCE_RESET() LL_MISC_ForceReset(LL_SDMMC2DLL) +#define __HAL_RCC_SDMMC2DLL_RELEASE_RESET() LL_MISC_ReleaseReset(LL_SDMMC2DLL) + +/** + * @} + */ + + +/** @defgroup RCC_Embedded_Mem_Clock_Sleep_Enable_Disable Embedded memory Clock Sleep Enable Disable + * @brief Enable or disable the embedded memory clock during Low Power (Sleep) mode. + * @note Embedded memory clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all embedded memory clocks are disabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM1) +#define __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM1) + +#define __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM2) +#define __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM2) + +#define __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM3) +#define __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM3) + +#define __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM4) +#define __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM4) + +#define __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM5) +#define __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM5) + +#define __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM6) +#define __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM6) + +#define __HAL_RCC_AHBSRAM1_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AHBSRAM1) +#define __HAL_RCC_AHBSRAM1_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AHBSRAM1) + +#define __HAL_RCC_AHBSRAM2_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AHBSRAM2) +#define __HAL_RCC_AHBSRAM2_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AHBSRAM2) + +#define __HAL_RCC_BKPSRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_BKPSRAM) +#define __HAL_RCC_BKPSRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_BKPSRAM) + +#define __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_FLEXRAM) +#define __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_FLEXRAM) + +#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_CACHEAXIRAM) +#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_CACHEAXIRAM) + +#define __HAL_RCC_VENCRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_VENCRAM) +#define __HAL_RCC_VENCRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_VENCRAM) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks are disabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12) +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12) + +#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1) +#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks are disabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1) +#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1) + +#define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1) +#define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1) + +#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG) +#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks except IAC are disabled during SLEEP mode. + * @note IAC, RIFSC and RIFAF peripheral clocks are always security-protected and thus hidden + * to the non-secure application. + * @{ + */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP) +#endif /* CRYP */ + +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_HASH) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_IAC_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_IAC) +#define __HAL_RCC_IAC_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_IAC) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_PKA) +#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_PKA) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_RIFSC_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC) +#define __HAL_RCC_RIFSC_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC) +#endif /* CPU_IN_SECURE_STATE */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_RISAF_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF) +#define __HAL_RCC_RISAF_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RNG) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RNG) + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_SAES) +#endif /* SAES */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks except PWR are disabled during SLEEP mode. + * @note PWR is always security-protected and thus hidden for non-secure application + * @{ + */ + +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_CRC) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_CRC) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA) +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE) + +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF) + +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG) + +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPION_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPION) +#define __HAL_RCC_GPION_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPION) + +#define __HAL_RCC_GPIOO_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO) +#define __HAL_RCC_GPIOO_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO) + +#define __HAL_RCC_GPIOP_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP) +#define __HAL_RCC_GPIOP_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP) + +#define __HAL_RCC_GPIOQ_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ) +#define __HAL_RCC_GPIOQ_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ) + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_PWR) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_PWR) +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable AHB5 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks are disabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D) + +#if defined(ETH1) +#define __HAL_RCC_ETH1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1) +#define __HAL_RCC_ETH1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1) + +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC) + +#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX) + +#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX) +#endif /* ETH1 */ + +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_FMC) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_FMC) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D) +#endif /* GPU2D */ + +#define __HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1) +#define __HAL_RCC_HPDMA1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG) +#endif /* JPEG */ + +#define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1) +#define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1) + +#define __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2) +#define __HAL_RCC_XSPI2_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2) + +#define __HAL_RCC_XSPI3_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3) +#define __HAL_RCC_XSPI3_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3) + +#define __HAL_RCC_XSPIM_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM) +#define __HAL_RCC_XSPIM_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM) + +#define __HAL_RCC_MCE1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1) +#define __HAL_RCC_MCE1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1) + +#define __HAL_RCC_MCE2_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2) +#define __HAL_RCC_MCE2_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2) + +#define __HAL_RCC_MCE3_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3) +#define __HAL_RCC_MCE3_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3) + +#define __HAL_RCC_MCE4_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4) +#define __HAL_RCC_MCE4_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4) + +#define __HAL_RCC_CACHEAXI_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI) +#define __HAL_RCC_CACHEAXI_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI) + +#define __HAL_RCC_NPU_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_NPU) +#define __HAL_RCC_NPU_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_NPU) + +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI) + +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1) + +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2) + +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1) +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1) + +#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1) +#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1) + +#define __HAL_RCC_USB2_OTG_HS_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2) +#define __HAL_RCC_USB2_OTG_HS_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2) + +#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2) +#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks are disabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN) + +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1) + +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2) + +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C3) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C3) + +#define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1) +#define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1) + +#define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C2) +#define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C2) + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS) +#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS) + +#define __HAL_RCC_SPDIFRX1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1) +#define __HAL_RCC_SPDIFRX1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1) + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2) + +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3) + +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2) +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2) + +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3) + +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4) + +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5) + +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6) + +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7) + +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM10) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM10) + +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM11) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM11) + +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12) + +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM13) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM13) + +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM14) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM14) + +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART2) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART2) + +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART3) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART3) + +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART4) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART4) + +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART5) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART5) + +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART7) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART7) + +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART8) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART8) + +#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1) +#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1) + +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks are disabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SAI1) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SAI1) + +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SAI2) + +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1) + +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI4) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI4) + +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI5) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI5) + +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1) +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1) + +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8) + +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM9) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM9) + +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15) + +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16) + +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_TIM18_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM18) +#define __HAL_RCC_TIM18_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM18) + +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART1) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART1) + +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART6) + +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_UART9) + +#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART10) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Sleep_Enable_Disable APB4 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks except BSEC are disabled during SLEEP mode. + * @note BSEC peripheral clock is always security-protected and thus hidden to the non-secure + * application. + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_BSEC) +#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_BSEC) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_DTS) + +#define __HAL_RCC_HDP_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_HDP) +#define __HAL_RCC_HDP_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_HDP) + +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_I2C4) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_I2C4) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2) + +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3) + +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4) + +#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1) + +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_RTC) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_RTC) + +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB) + +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_SPI6) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_SPI6) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG) + +#define __HAL_RCC_VREFBUF_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF) +#define __HAL_RCC_VREFBUF_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Sleep_Enable_Disable APB5 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB5 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note By default, all peripheral clocks are disabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_CSI_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_CSI) +#define __HAL_RCC_CSI_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_CSI) + +#define __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP) +#define __HAL_RCC_DCMIPP_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP) + +#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM) + +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_LTDC) + +#define __HAL_RCC_VENC_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_VENC) +#define __HAL_RCC_VENC_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_VENC) + +/** + * @} + */ + +/** @defgroup RCC_MISC_Configuration_Clock_Sleep_Enable_Disable Misc Configuration Clock Sleep Enable Disable + * @brief Enable or disable the misc configuration clock during Low Power (Sleep) mode. + * @note After reset, the misc configuration clock is disabled and + * the application software has to enable this clock before using it. + * @note After wakeup from SLEEP mode, the misc configuration clock is enabled again. + * @note DBG clock is always security-protected and thus hidden the non-secure application. + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) +#define __HAL_RCC_DBG_CLK_SLEEP_ENABLE() LL_MISC_EnableClockLowPower(LL_DBG) +#define __HAL_RCC_DBG_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_DBG) +#endif /* CPU_IN_SECURE_STATE */ + +#define __HAL_RCC_XSPIPHYCOMP_CLK_SLEEP_ENABLE() LL_MISC_EnableClockLowPower(LL_XSPIPHYCOMP) +#define __HAL_RCC_XSPIPHYCOMP_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_XSPIPHYCOMP) + +#define __HAL_RCC_PER_CLK_SLEEP_ENABLE() LL_MISC_EnableClockLowPower(LL_PER) +#define __HAL_RCC_PER_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_PER) + +/** + * @} + */ + +/** @defgroup RCC_Embedded_Mem_Clock_Sleep_Enable_Status Embedded Memory Clock Sleep Enabled Status + * @brief Check whether the embedded memory clock sleep is enabled or not. + * @note After reset, some embedded memory clocks are disabled + * and the application software has to enable these memory clocks before using them. + * @{ + */ + +#define __HAL_RCC_AXISRAM1_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM1) +#define __HAL_RCC_AXISRAM2_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM2) +#define __HAL_RCC_AXISRAM3_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM3) +#define __HAL_RCC_AXISRAM4_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM4) +#define __HAL_RCC_AXISRAM5_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM5) +#define __HAL_RCC_AXISRAM6_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM6) +#define __HAL_RCC_AHBSRAM1_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AHBSRAM1) +#define __HAL_RCC_AHBSRAM2_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AHBSRAM2) +#define __HAL_RCC_BKPSRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_BKPSRAM) +#define __HAL_RCC_FLEXRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_FLEXRAM) +#define __HAL_RCC_CACHEAXIRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_CACHEAXIRAM) +#define __HAL_RCC_VENCRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_VENCRAM) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Status AHB1 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB1 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12) + +#define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Status AHB2 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB2 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_ADF1_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1) + +#define __HAL_RCC_MDF1_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1) + +#define __HAL_RCC_RAMCFG_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Status AHB3 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB3 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP) +#endif /* CRYP */ + +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_HASH) + +#define __HAL_RCC_IAC_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_IAC) + +#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_PKA) + +#define __HAL_RCC_RIFSC_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC) + +#define __HAL_RCC_RISAF_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF) + +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RNG) + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_SAES) +#endif /* SAES */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Status AHB4 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB4 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_CRC) + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA) + +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB) + +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC) + +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD) + +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE) + +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF) + +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG) + +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH) + +#define __HAL_RCC_GPION_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPION) + +#define __HAL_RCC_GPIOO_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO) + +#define __HAL_RCC_GPIOP_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP) + +#define __HAL_RCC_GPIOQ_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ) + +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_PWR) + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Sleep_Enable_Status AHB5 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB5 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D) + +#if defined(ETH1) +#define __HAL_RCC_ETH1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1) + +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC) + +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX) + +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX) +#endif /* ETH1 */ + +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_FMC) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D) +#endif /* GPU2D */ + +#define __HAL_RCC_HPDMA1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG) +#endif /* JPEG */ + +#define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1) + +#define __HAL_RCC_XSPI2_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2) + +#define __HAL_RCC_XSPI3_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3) + +#define __HAL_RCC_XSPIM_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM) + +#define __HAL_RCC_MCE1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1) + +#define __HAL_RCC_MCE2_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2) + +#define __HAL_RCC_MCE3_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3) + +#define __HAL_RCC_MCE4_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4) + +#define __HAL_RCC_CACHEAXI_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI) + +#define __HAL_RCC_NPU_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_NPU) + +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI) + +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1) + +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2) + +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1) + +#define __HAL_RCC_USB1_OTG_HS_PHY_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1) + +#define __HAL_RCC_USB2_OTG_HS_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2) + +#define __HAL_RCC_USB2_OTG_HS_PHY_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Status APB1 Peripheral Clock Sleep Enabled Status + * @brief Check whether the APB1 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN) + +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C1) + +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C2) + +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C3) + +#define __HAL_RCC_I3C1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I3C1) + +#define __HAL_RCC_I3C2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I3C2) + +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1) + +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS) + +#define __HAL_RCC_SPDIFRX1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1) + +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPI2) + +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPI3) + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM2) + +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM3) + +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM4) + +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM5) + +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM6) + +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM7) + +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM10) + +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM11) + +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM12) + +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM13) + +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM14) + +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_USART2) + +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_USART3) + +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART4) + +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART5) + +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART7) + +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART8) + +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1) + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_WWDG) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Status APB2 Peripheral Clock Sleep Enabled Status + * @brief Check whether the APB2 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SAI1) + +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SAI2) + +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI1) + +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI4) + +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI5) + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM1) + +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM8) + +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM9) + +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM15) + +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM16) + +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM17) + +#define __HAL_RCC_TIM18_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM18) + +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART1) + +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART6) + +#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_UART9) + +#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART10) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Sleep_Enable_Status APB4 Peripheral Clock Sleep Enabled Status + * @brief Check whether the APB4 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_BSEC_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_BSEC) + +#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_DTS) + +#define __HAL_RCC_HDP_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_HDP) + +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_I2C4) + +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2) + +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3) + +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4) + +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5) + +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1) + +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_RTC) + +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB) + +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_SPI6) + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG) + +#define __HAL_RCC_VREFBUF_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Sleep_Enable_Status APB5 Peripheral Clock Sleep Enabled Status + * @brief Check whether the APB5 peripheral clock sleep is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_CSI_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_CSI) + +#define __HAL_RCC_DCMIPP_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP) + +#define __HAL_RCC_GFXTIM_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM) + +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_LTDC) + +#define __HAL_RCC_VENC_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_VENC) + + +/** + * @} + */ + +/** @defgroup RCC_MISC_Configuration_Clock_Sleep_Enable_Status Misc Configuration Clock Sleep Enabled Status + * @brief Check whether the misc configuration clock sleep is enabled or not. + * @note After reset, the misc configuration clock is disabled and + * the application software has to enable this clock before using it. + * @{ + */ + +#define __HAL_RCC_DBG_IS_CLK_SLEEP_ENABLED() LL_MISC_IsEnabledClockLowPower(LL_DBG) + +#define __HAL_RCC_XSPIPHYCOMP_IS_CLK_SLEEP_ENABLED() LL_MISC_IsEnabledClockLowPower(LL_XSPIPHYCOMP) + +#define __HAL_RCC_PER_IS_CLK_SLEEP_ENABLED() LL_MISC_IsEnabledClockLowPower(LL_PER) + +/** + * @} + */ + +/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY flag to be set indicating that the HSI clock is stable + * and that HSI clock can be used to clock the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param __STATE__ specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator + * @arg @ref RCC_HSI_ON turn ON the HSI oscillator + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION, (uint32_t)(__STATE__)) + +/** @brief Macro to configure the Internal High Speed oscillator (HSI) clock divider. + * @param __HSIDIV__ specifies the HSI division factor. + * This parameter can be one of the following values: + * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) + * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 + * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 + * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 + */ +#define __HAL_RCC_HSI_DIVIDER_CONFIG(__HSIDIV__) LL_RCC_HSI_SetDivider((uint32_t)(__HSIDIV__)) + +/** @brief Macro to get the HSI divider. + * @retval The HSI divider. The returned value can be one of the following values: + * of the following: + * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) + * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 + * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 + * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 + */ +#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)LL_RCC_HSI_GetDivider()) + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after start-up + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() + +#define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable() + +/** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 127. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + LL_RCC_HSI_SetCalibTrimming((uint32_t)(__HSICALIBRATIONVALUE__)); + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for some peripherals. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI start-up time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() + +#define __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode() + +/** + * @brief Macros to enable or disable the Internal oscillator (MSI). + * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * start-up from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note MSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the MSI. + * @note After enabling the MSI, the application software should wait on + * MSIRDY flag to be set indicating that MSI clock is stable and can + * be used as system clock source. + * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator + * clock cycles. + */ +#define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() + +#define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() + +/** @brief Macro to configure the Internal oscillator (MSI) frequency. + * @param __FREQ__ specifies the MSI frequency. + * This parameter can be one of the following values: + * @arg RCC_MSI_FREQ_4MHZ 4MHz selection (default after reset) + * @arg RCC_MSI_FREQ_16MHZ 16MHz selection + */ +#define __HAL_RCC_MSI_FREQUENCY_CONFIG(__FREQ__) LL_RCC_MSI_SetFrequency((uint32_t)(__FREQ__)) + +/** @brief Macro to adjust the Internal oscillator (MSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal MSI RC. + * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_MSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ + LL_RCC_MSI_SetCalibTrimming((uint32_t)(__MSICALIBRATIONVALUE__)) + +/** + * @brief Macros to enable or disable the force of the Low-power Internal oscillator (MSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the MSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the MSI start-up time. + * @note The enable of this function has not effect on the MSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_MSISTOP_ENABLE() LL_RCC_MSI_EnableInStopMode() + +#define __HAL_RCC_MSISTOP_DISABLE() LL_RCC_MSI_DisableInStopMode() + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() LL_RCC_LSI_Enable() + +#define __HAL_RCC_LSI_DISABLE() LL_RCC_LSI_Disable() + +/** + * @brief Macros to configure the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), + * the application software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock and peripheral kernel + * clock source. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock (analog). + * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed with external digital clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + WRITE_REG(RCC->CSR, RCC_CSR_HSEONS); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + WRITE_REG(RCC->CCR, RCC_CCR_HSEONC); \ + CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP); \ + CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT); \ + WRITE_REG(RCC->CSR, RCC_CSR_HSEONS); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \ + WRITE_REG(RCC->CSR, RCC_CSR_HSEONS); \ + } \ + else \ + { \ + WRITE_REG(RCC->CCR, RCC_CCR_HSEONC); \ + CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \ + } \ + } while(0) + +/** + * @brief Macros to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). + A duty cycle close to 50% is recommended. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock (analog). + * @arg @ref RCC_LSE_BYPASS_DIGITAL LSE oscillator bypassed with external digital clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + WRITE_REG(RCC->CSR, RCC_CSR_LSEONS); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + WRITE_REG(RCC->CCR, RCC_CCR_LSEONC); \ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ + WRITE_REG(RCC->CSR, RCC_CSR_LSEONS); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ + WRITE_REG(RCC->CSR, RCC_CSR_LSEONS); \ + } \ + else \ + { \ + WRITE_REG(RCC->CCR, RCC_CCR_LSEONC); \ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ + } \ + } while(0) + +/** @brief Macros to enable or disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC() + +#define __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC() + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() and + * __HAL_RCC_BACKUPRESET_RELEASE() macros, or by a Power On Reset (POR). + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected + * as RTC clock, where x:[1,4096] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + do { \ + if (((__RTC_CLKSOURCE__) & (RCC_CCIPR7_RTCSEL)) == RCC_CCIPR7_RTCSEL) { \ + __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ + } \ + LL_RCC_SetRTCClockSource((__RTC_CLKSOURCE__) & RCC_CCIPR7_RTCSEL); \ + } while(0) + +/** @brief Macro to configure the RTC clock prescaler for HSE for RTCCLK. + * @param __RTC_CLKSOURCE__ specifies the RTC clock prescaler for HSE. + * This parameter can be one of the following values: + * RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected + * as RTC clock, where x:[1,4096] + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) \ + LL_RCC_SetRTC_HSEPrescaler(((__RTC_CLKSOURCE__) & (~RCC_CCIPR7_RTCSEL))) + +/** @brief Macros to get the RTC clock (RTCCLK). + * @retval The returned value can be one of the following values: + * RCC_RTCCLKSOURCE_DISABLE No clock selected as RTC clock. + * RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected + * as RTC clock, where x:[1,4096] + */ +#define __HAL_RCC_GET_RTC_SOURCE() \ + ((READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL) == RCC_CCIPR7_RTCSEL) ? \ + (READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE) | RCC_CCIPR7_RTCSEL) : READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL)) + +/** @brief Macros to force or release the Vswitch backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset() + +#define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset() + +/** @brief Macros to enable or disable the PLL1. + * @note After enabling the PLL1, the application software should wait on + * PLL1RDY flag to be set indicating that PLL1 clock is stable and can + * be used as CPU and/or system bus and/or kernel clock source thru ICx. + * @note The PLL1 can not be disabled if it is used as system clock source + * @note The PLL1 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL1_ENABLE() LL_RCC_PLL1_Enable() + +#define __HAL_RCC_PLL1_DISABLE() LL_RCC_PLL1_Disable() + +/** + * @brief Macros to enable or disable the PLL1 post divider 1, post divider 2 + * and PLL1 clock output when not in bypass mode. + */ +#define __HAL_RCC_PLL1CLKOUT_ENABLE() LL_RCC_PLL1P_Enable() +#define __HAL_RCC_PLL1CLKOUT_DISABLE() LL_RCC_PLL1P_Disable() + +/** + * @brief Macro to configure the PLL1 in integer mode with clock source, multiplication + * and division factors. + * @note This macro must be used only when the PLL1 is disabled or the PLL1 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry + * @note This clock source cannot be changed on any PLL if another PLL is already enabled. + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock. + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 50 MHz. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. + * This parameter must be a number between 16 and 2500. + * + * @param __PLLP1__ specifies the post division factor 1 for system clock. + * This parameter must be a number between 1 and 7. + * + * @param __PLLP2__ specifies the post division factor 2 for system clock. + * This parameter must be a number between 1 and 7. + * + * @retval None + */ + +#define __HAL_RCC_PLL1_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ + do { \ + MODIFY_REG(RCC->PLL1CFGR1, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1BYP | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \ + ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL1CFGR1_PLL1DIVM_Pos) | (((__PLLN__) << RCC_PLL1CFGR1_PLL1DIVN_Pos)))); \ + MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC, 0U); \ + MODIFY_REG(RCC->PLL1CFGR3, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \ + ((((__PLLP1__) << RCC_PLL1CFGR3_PLL1PDIV1_Pos) & RCC_PLL1CFGR3_PLL1PDIV1) | \ + ((((__PLLP2__) << RCC_PLL1CFGR3_PLL1PDIV2_Pos) & RCC_PLL1CFGR3_PLL1PDIV2)))); \ + } while(0) + +/** @brief Macro to configure the PLL1 clock source. + * @note This macro must be used only when the PLL1 is disabled or the PLL1 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry + */ +#define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL1_SetSource((uin32_t)__PLLSOURCE__) + +/** @brief Macro to get the clock source used as PLL1 clock source. + * @retval The oscillator used as PLL clock source. + * The returned value can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL1_OSCSOURCE() LL_RCC_PLL1_GetSource() + +/** + * @brief Macro to configure the PLL1 clock Fractional Part Of The Multiplication Factor + * @note This configuration cannot be requested when the PLL1 has been enabled. + * + * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL1 VCO. + * It should be a value between 0 and 2^24. + * @retval None + */ +#define __HAL_RCC_PLL1_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL1_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) + +/** + * @brief Macro to enable the PLL1 clock Fractional mode + * @note This configuration cannot be requested when the PLL1 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_ENABLE() LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum() + +/** + * @brief Macro to disable the PLL1 clock Fractional mode + * @note This configuration cannot be requested when the PLL1 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_DISABLE() LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum() + +/** @brief Macros to enable or disable PLL2. + * @note After enabling PLL2, the application software should wait on + * PLL2RDY flag to be set indicating that PLL2 clock is stable and can + * be used as CPU and/or system bus and/or kernel clock source thru ICx. + * @note PLL2 is disabled by hardware when entering Stop and Standby modes. + */ +#define __HAL_RCC_PLL2_ENABLE() LL_RCC_PLL2_Enable() +#define __HAL_RCC_PLL2_DISABLE() LL_RCC_PLL2_Disable() + +/** + * @brief Macros to enable or disable the PLL2 post divider 1, post divider 2 + * and PLL2 clock output when not in bypass mode. + */ +#define __HAL_RCC_PLL2CLKOUT_ENABLE() LL_RCC_PLL2P_Enable() +#define __HAL_RCC_PLL2CLKOUT_DISABLE() LL_RCC_PLL2P_Disable() + +/** + * @brief Macro to configure the PLL2 in integer mode with clock source, multiplication + * and division factors. + * @note This macro must be used only when the PLL2 is disabled or the PLL2 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry + * @note This clock source cannot be changed on any PLL if another PLL is already enabled. + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 50 MHz. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 16 and 2500. + * @param __PLLP1__ specifies the post division factor 1 for system clock. + * This parameter must be a number between 1 and 7. + * @param __PLLP2__ specifies the post division factor 2 for system clock. + * This parameter must be a number between 1 and 7. + * + * @retval None + */ + +#define __HAL_RCC_PLL2_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ + do { \ + MODIFY_REG(RCC->PLL2CFGR1, (RCC_PLL2CFGR1_PLL2SEL | RCC_PLL2CFGR1_PLL2BYP | RCC_PLL2CFGR1_PLL2DIVM | RCC_PLL2CFGR1_PLL2DIVN), \ + ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL2CFGR1_PLL2DIVM_Pos) | (((__PLLN__) << RCC_PLL2CFGR1_PLL2DIVN_Pos)))); \ + MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC, 0U); \ + MODIFY_REG(RCC->PLL2CFGR3, (RCC_PLL2CFGR3_PLL2PDIV1 | RCC_PLL2CFGR3_PLL2PDIV2), \ + ((((__PLLP1__) << RCC_PLL2CFGR3_PLL2PDIV1_Pos) & RCC_PLL2CFGR3_PLL2PDIV1) | \ + ((((__PLLP2__) << RCC_PLL2CFGR3_PLL2PDIV2_Pos) & RCC_PLL2CFGR3_PLL2PDIV2)))); \ + } while(0) + + +/** @brief Macro to configure the PLL2 clock source. + * @note This macro must be used only when the PLL2 is disabled or the PLL2 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry + */ +#define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL2_SetSource((uin32_t)__PLLSOURCE__) + +/** @brief Macro to get the clock source used as PLL2 clock source. + * @retval The oscillator used as PLL clock source. + * The returned value can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL2_OSCSOURCE() LL_RCC_PLL2_GetSource() + +/** + * @brief Macro to configure the PLL2 clock Fractional Part Of The Multiplication Factor + * @note This configuration cannot be requested when the PLL2 has been enabled. + * + * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL2 VCO. + * It should be a value between 0 and 2^24. + * @retval None + */ +#define __HAL_RCC_PLL2_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL2_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) + +/** + * @brief Macro to enable the PLL2 clock Fractional mode + * @note This configuration cannot be requested when the PLL2 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL2_FRACN_ENABLE() LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum() + +/** + * @brief Macro to disable the PLL2 clock Fractional mode + * @note This configuration cannot be requested when the PLL2 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL2_FRACN_DISABLE() LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum() + +/** @brief Macros to enable or disable PLL3. + * @note After enabling PLL3, the application software should wait on + * PLL3RDY flag to be set indicating that PLL3 clock is stable and can + * be used as CPU and/or system bus and/or kernel clock source thru ICx. + * @note PLL3 is disabled by hardware when entering Stop and Standby modes. + */ +#define __HAL_RCC_PLL3_ENABLE() LL_RCC_PLL3_Enable() +#define __HAL_RCC_PLL3_DISABLE() LL_RCC_PLL3_Disable() + +/** + * @brief Macros to enable or disable the PLL3 post divider 1, post divider 2 + * and PLL3 clock output when not in bypass mode. + */ +#define __HAL_RCC_PLL3CLKOUT_ENABLE() LL_RCC_PLL3P_Enable() +#define __HAL_RCC_PLL3CLKOUT_DISABLE() LL_RCC_PLL3P_Disable() + +/** + * @brief Macro to configure the PLL3 in integer mode with clock source, multiplication + * and division factors. + * @note This macro must be used only when the PLL3 is disabled or the PLL3 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry + * @note This clock source cannot be changed on any PLL if another PLL is already enabled. + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 50 MHz. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 16 and 2500. + * @param __PLLP1__ specifies the post division factor 1 for system clock. + * This parameter must be a number between 1 and 7. + * @param __PLLP2__ specifies the post division factor 2 for system clock. + * This parameter must be a number between 1 and 7. + * + * @retval None + */ + +#define __HAL_RCC_PLL3_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ + do { \ + MODIFY_REG(RCC->PLL3CFGR1, (RCC_PLL3CFGR1_PLL3SEL | RCC_PLL3CFGR1_PLL3BYP | RCC_PLL3CFGR1_PLL3DIVM | RCC_PLL3CFGR1_PLL3DIVN), \ + ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL3CFGR1_PLL3DIVM_Pos) | (((__PLLN__) << RCC_PLL3CFGR1_PLL3DIVN_Pos)))); \ + MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC, 0U); \ + MODIFY_REG(RCC->PLL3CFGR3, (RCC_PLL3CFGR3_PLL3PDIV1 | RCC_PLL3CFGR3_PLL3PDIV2), \ + ((((__PLLP1__) << RCC_PLL3CFGR3_PLL3PDIV1_Pos) & RCC_PLL3CFGR3_PLL3PDIV1) | \ + ((((__PLLP2__) << RCC_PLL3CFGR3_PLL3PDIV2_Pos) & RCC_PLL3CFGR3_PLL3PDIV2)))); \ + } while(0) + + +/** @brief Macro to configure the PLL3 clock source. + * @note This macro must be used only when the PLL3 is disabled or the PLL3 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry + */ +#define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL3_SetSource((uin32_t)__PLLSOURCE__) + +/** @brief Macro to get the clock source used as PLL3 clock source. + * @retval The oscillator used as PLL clock source. + * The returned value can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL3_OSCSOURCE() LL_RCC_PLL3_GetSource() + +/** + * @brief Macro to configure the PLL3 clock Fractional Part Of The Multiplication Factor + * @note This configuration cannot be requested when the PLL3 has been enabled. + * + * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO. + * It should be a value between 0 and 2^24. + * @retval None + */ +#define __HAL_RCC_PLL3_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL3_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) + +/** + * @brief Macro to enable the PLL3 clock Fractional mode + * @note This configuration cannot be requested when the PLL3 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL3_FRACN_ENABLE() LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum() + +/** + * @brief Macro to disable the PLL3 clock Fractional mode + * @note This configuration cannot be requested when the PLL3 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL3_FRACN_DISABLE() LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum() + +/** @brief Macros to enable or disable PLL4. + * @note After enabling PLL4, the application software should wait on + * PLL4RDY flag to be set indicating that PLL4 clock is stable and can + * be used as CPU and/or system bus and/or kernel clock source thru ICx. + * @note PLL4 is disabled by hardware when entering Stop and Standby modes. + */ +#define __HAL_RCC_PLL4_ENABLE() LL_RCC_PLL4_Enable() +#define __HAL_RCC_PLL4_DISABLE() LL_RCC_PLL4_Disable() + +/** + * @brief Macros to enable or disable the PLL4 post divider 1, post divider 2 + * and PLL4 clock output when not in bypass mode. + */ +#define __HAL_RCC_PLL4CLKOUT_ENABLE() LL_RCC_PLL4P_Enable() +#define __HAL_RCC_PLL4CLKOUT_DISABLE() LL_RCC_PLL4P_Disable() + +/** + * @brief Macro to configure the PLL4 in integer mode with clock source, multiplication + * and division factors. + * @note This macro must be used only when the PLL4 is disabled or the PLL4 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry + * @note This clock source cannot be changed on any PLL if another PLL is already enabled. + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 50 MHz. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 16 and 2500. + * @param __PLLP1__ specifies the post division factor 1 for system clock. + * This parameter must be a number between 1 and 7. + * @param __PLLP2__ specifies the post division factor 2 for system clock. + * This parameter must be a number between 1 and 7. + * + * @retval None + */ + +#define __HAL_RCC_PLL4_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ + do { \ + MODIFY_REG(RCC->PLL4CFGR1, (RCC_PLL4CFGR1_PLL4SEL | RCC_PLL4CFGR1_PLL4BYP | RCC_PLL4CFGR1_PLL4DIVM | RCC_PLL4CFGR1_PLL4DIVN), \ + ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL4CFGR1_PLL4DIVM_Pos) | (((__PLLN__) << RCC_PLL4CFGR1_PLL4DIVN_Pos)))); \ + MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC, 0U); \ + MODIFY_REG(RCC->PLL4CFGR3, (RCC_PLL4CFGR3_PLL4PDIV1 | RCC_PLL4CFGR3_PLL4PDIV2), \ + ((((__PLLP1__) << RCC_PLL4CFGR3_PLL4PDIV1_Pos) & RCC_PLL4CFGR3_PLL4PDIV1) | \ + ((((__PLLP2__) << RCC_PLL4CFGR3_PLL4PDIV2_Pos) & RCC_PLL4CFGR3_PLL4PDIV2)))); \ + } while(0) + + +/** @brief Macro to configure the PLL4 clock source. + * @note This macro must be used only when the PLL4 is disabled or the PLL4 output is bypassed + * and driven by the PLL reference clock. This macro switches off the bypass mode. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry + */ +#define __HAL_RCC_PLL4_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL4_SetSource((uin32_t)__PLLSOURCE__) + +/** @brief Macro to get the clock source used as PLL4 clock source. + * @retval The oscillator used as PLL clock source. + * The returned value can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL4_OSCSOURCE() LL_RCC_PLL4_GetSource() + +/** + * @brief Macro to configure the PLL4 clock Fractional Part Of The Multiplication Factor + * @note This configuration cannot be requested when the PLL4 has been enabled. + * + * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL4 VCO. + * It should be a value between 0 and 2^24. + * @retval None + */ +#define __HAL_RCC_PLL4_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL4_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) + +/** + * @brief Macro to enable the PLL4 clock Fractional mode + * @note This configuration cannot be requested when the PLL4 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL4_FRACN_ENABLE() LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum() + + +/** + * @brief Macro to disable the PLL4 clock Fractional mode + * @note This configuration cannot be requested when the PLL4 has been enabled. + * @retval None + */ +#define __HAL_RCC_PLL4_FRACN_DISABLE() LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum() + +/** + * @brief Macro to configure the CPU clock source. + * @param __CPUCLKSOURCE__ specifies the CPU clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_CPUCLKSOURCE_HSI HSI oscillator is used as CPU clock source. + * @arg @ref RCC_CPUCLKSOURCE_MSI MSI oscillator is used as CPU clock source. + * @arg @ref RCC_CPUCLKSOURCE_HSE HSE oscillator is used as CPU clock source. + * @arg @ref RCC_CPUCLKSOURCE_IC1 IC1 output is used as CPU clock source. + * @retval None + */ +#define __HAL_RCC_CPUCLK_CONFIG(__CPUCLKSOURCE__) LL_RCC_SetCpuClkSource((uint32_t)(__CPUCLKSOURCE__)) + +/** @brief Macro to get the clock source used as CPU clock. + * @retval The clock source used as CPU clock. + * The returned value can be one of the following values: + * @arg @ref RCC_CPUCLKSOURCE_STATUS_HSI HSI used as CPU clock. + * @arg @ref RCC_CPUCLKSOURCE_STATUS_MSI MSI used as CPU clock. + * @arg @ref RCC_CPUCLKSOURCE_STATUS_HSE HSE used as CPU clock. + * @arg @ref RCC_CPUCLKSOURCE_STATUS_IC1 IC1 used as CPU clock. + */ +#define __HAL_RCC_GET_CPUCLK_SOURCE() LL_RCC_GetCpuClkSource() + + +/** + * @brief Macro to configure the system bus clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system bus clock source. + * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system bus clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system bus clock source. + * @arg @ref RCC_SYSCLKSOURCE_IC2_IC6_IC11 IC2, IC6 and IC11 outputs are used as system bus clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource((uint32_t)(__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system bus clock. + * @retval The clock source used as system clock. + * The returned value can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system bus clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system bus clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system bus clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11 IC2, IC6 and IC11 outputs used as system bus clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource() + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note This parameter cannot be updated while LSE is ON. + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability((uint32_t)(__LSEDRIVE__)) + +/** + * @brief Macro to configure the wake up from stop clock. + * @param __STOPWUCLK__ specifies the clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source + * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetSysWakeUpClkSource((uint32_t)(__STOPWUCLK__)) + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** + * @brief Macros to enable or disable the MCO1 clock output + * @retval None + */ +#define __HAL_RCC_MCO1_ENABLE() LL_RCC_EnableMCO(LL_RCC_MCO1) + +#define __HAL_RCC_MCO1_DISABLE() LL_RCC_DisableMCO(LL_RCC_MCO1) + +/** + * @brief Macros to enable or disable the MCO2 clock output + * @retval None + */ +#define __HAL_RCC_MCO2_ENABLE() LL_RCC_EnableMCO(LL_RCC_MCO2) + +#define __HAL_RCC_MCO2_DISABLE() LL_RCC_DisableMCO(LL_RCC_MCO2) + + +/** @brief Macro to configure the MCO1 clock. + * @note MCO1 clock output shall be enabled with __HAL_RCC_MCO1_ENABLE() + * @note The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch). + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_IC5 IC5 clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_IC10 IC10 clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_SYSA SYSA CPU clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_16 : divider applied to MCO1 clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO(__MCOCLKSOURCE__, __MCODIV__) + +/** @brief Macro to configure the MCO2 clock. + * @note MCO2 clock output shall be enabled with __HAL_RCC_MCO2_ENABLE() + * @note The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch). + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_MSI MSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_IC15 IC15 clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_IC20 IC20 clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_SYSB SYSB bus clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_16 : divider applied to MCO2 clock + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO(__MCOCLKSOURCE__, __MCODIV__) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt + * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt + * @arg @ref RCC_IT_HSECSS HSE clock security system interrupt + * @arg @ref RCC_IT_WKUP CPU wakeup interrupt + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt + * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt + * @arg @ref RCC_IT_HSECSS HSE clock security system interrupt + * @arg @ref RCC_IT_WKUP CPU wakeup interrupt + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt + * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt + * @arg @ref RCC_IT_HSECSS HSE clock security interrupt + * @arg @ref RCC_IT_WKUP CPU wakeup interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt + * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt + * @arg @ref RCC_IT_HSECSS HSE clock security interrupt + * @arg @ref RCC_IT_WKUP CPU wakeup interrupt + * @retval The pending state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_LCKRST, RCC_FLAG_BORRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags() + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_LCKRST CPU lockup reset flag + * @arg @ref RCC_FLAG_BORRST BOR reset flag + * @arg @ref RCC_FLAG_PINRST Pin reset flag + * @arg @ref RCC_FLAG_PORRST Power-on reset flag + * @arg @ref RCC_FLAG_SFTRST Software reset flag + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset flag + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset flag + * @arg @ref RCC_FLAG_LPWRRST Low Power reset flag + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection flag + * @arg @ref RCC_FLAG_HSECSSD Clock security system failure on HSE oscillator detection flag + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready flag + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready flag + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready flag + * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready flag + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready flag + * @arg @ref RCC_FLAG_PLL1RDY PLL1 ready flag + * @arg @ref RCC_FLAG_PLL2RDY PLL2 ready flag + * @arg @ref RCC_FLAG_PLL3RDY PLL3 ready flag + * @arg @ref RCC_FLAG_PLL4RDY PLL4 ready flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == RCC_RSR_REG_INDEX) ? RCC->RSR : \ + ((((__FLAG__) >> 5U) == RCC_LSECFGR_REG_INDEX) ? RCC->LSECFGR : \ + ((((__FLAG__) >> 5U) == RCC_HSECFGR_REG_INDEX) ? RCC->HSECFGR : RCC->SR)))) \ + & (1UL << ((__FLAG__) & RCC_FLAG_POS_MASK))) != 0U) ? 1U : 0U) + +/** + * @} + */ + +/** @defgroup RCC_Attributes_Management Attribute Management + * @brief macros to manage the RCC Attributes. + * @{ + */ + +/** @brief Check whether an item attribute is secured + * @param __ATTRIBUTES__ specifies the item attributes + * This parameter is a combination of @ref RCC_attributes + * @retval 1 if the item attribute is secured, 0 otherwise. + */ +#define HAL_RCC_ATTRIBUTES_IS_SEC(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_SEC) == RCC_ATTR_SEC) ? 1U : 0U) + +/** @brief Check whether an item attribute is privileged + * @param __ATTRIBUTES__ specifies the item attributes + * This parameter is a combination of @ref RCC_attributes + * @retval 1 if the item attribute is privileged, 0 otherwise. + */ +#define HAL_RCC_ATTRIBUTES_IS_PRIV(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) ? 1U : 0U) + +/** @brief Check whether an item attribute is public + * @param __ATTRIBUTES__ specifies the item attributes + * This parameter is a combination of @ref RCC_attributes + * @retval 1 if the item attribute is public, 0 otherwise. + */ +#define HAL_RCC_ATTRIBUTES_IS_PUB(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_PUB) == RCC_ATTR_PUB) ? 1U : 0U) + +/** @brief Check whether an item attribute is locked + * @param __ATTRIBUTES__ specifies the item attributes + * This parameter is a combination of @ref RCC_attributes + * @retval 1 if the item attribute is locked, 0 otherwise. + */ +#define HAL_RCC_ATTRIBUTES_IS_LOCK(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_LOCK) == RCC_ATTR_LOCK) ? 1U : 0U) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32n6xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *pRCC_ClkInitStruct); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +uint32_t HAL_RCC_GetCpuClockFreq(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetNPUClockFreq(void); +uint32_t HAL_RCC_GetNPURAMSClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +uint32_t HAL_RCC_GetPCLK4Freq(void); +uint32_t HAL_RCC_GetPCLK5Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User callback in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group3 + * @{ + */ +/* Attributes management functions ********************************************/ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define RCC_PLL_TIMEOUT_VALUE 1U /* 1 ms */ + +/* Defines used for Flags */ +#define RCC_SR_REG_INDEX 1U +#define RCC_LSECFGR_REG_INDEX 2U +#define RCC_HSECFGR_REG_INDEX 3U +#define RCC_RSR_REG_INDEX 4U +#define RCC_FLAG_POS_MASK 0x0000001FU + +/* Defines RCC privilege/secure/public/lock attribute masks */ +#define RCC_ATTR_PRIV_MASK (0x00000002U) /* RCC privilege mask */ +#define RCC_ATTR_SEC_MASK (0x00000008U) /* RCC secure mask */ +#define RCC_ATTR_PUB_MASK (0x00000020U) /* RCC public mask */ +#define RCC_ATTR_LOCK_MASK (0x00000080U) /* RCC lock mask */ + +/* Defines RCC item groups masks */ +/* Item ID are masked with item group to get an unique ID + 31 24 16 8 0 + -------------------------------------------------------- + | Item Group | Item | + --------------------------------------------------------*/ +#define RCC_ITEM_GROUP_POS 24UL +#define RCC_ITEM_GROUP_MASK 0xFF000000UL +#define RCC_ITEM_MASK 0x00FFFFFFUL +#define RCC_ITEM_GROUP_OSC 0x01000000UL +#define RCC_ITEM_GROUP_PLL 0x02000000UL +#define RCC_ITEM_GROUP_IC 0x04000000UL +#define RCC_ITEM_GROUP_SYSCFG 0x08000000UL +#define RCC_ITEM_GROUP_BUS 0x10000000UL +#define RCC_ITEM_GROUP_MEM 0x20000000UL + +#define RCC_ITEM_GROUP_OSC_MASK 0x0000001FUL +#define RCC_ITEM_GROUP_PLL_MASK 0x0000000FUL +#define RCC_ITEM_GROUP_IC_MASK 0x000FFFFFUL +#define RCC_ITEM_GROUP_SYSCFG_MASK 0x0000003FUL +#define RCC_ITEM_GROUP_BUS_MASK 0x00003FFFUL +#define RCC_ITEM_GROUP_MEM_MASK 0x00000FFFUL + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define IS_RCC_HSI_DIV(__HSI__) (((__HSI__) == RCC_HSI_DIV1) || ((__HSI__) == RCC_HSI_DIV2) || \ + ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_DIV8)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) + +#define IS_RCC_MSI_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == RCC_MSI_FREQ_4MHZ) ||\ + ((__FREQUENCY__) == RCC_MSI_FREQ_16MHZ)) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || \ + ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON) || \ + ((__PLL__) == RCC_PLL_BYPASS)) + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE) || \ + ((__SOURCE__) == RCC_PLLSOURCE_PIN)) + +#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) + +#define IS_RCC_PLLN_VALUE(__VALUE__) ((10U <= (__VALUE__)) && ((__VALUE__) <= 2500U)) + +#define IS_RCC_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 7U)) + +#define IS_RCC_PLLFRACN_VALUE(__VALUE__) ((__VALUE__) <= (RCC_PLL1CFGR2_PLL1DIVNFRAC >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)) + +#define IS_RCC_CLOCKTYPE(__CLK__) ((__CLK__) <= 0x7FU) + +#define IS_RCC_CPUCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_CPUCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_CPUCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_CPUCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_CPUCLKSOURCE_IC1)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_HCLK_DIV1) || ((__HCLK__) == RCC_HCLK_DIV2) || \ + ((__HCLK__) == RCC_HCLK_DIV4) || ((__HCLK__) == RCC_HCLK_DIV8) || \ + ((__HCLK__) == RCC_HCLK_DIV16) || ((__HCLK__) == RCC_HCLK_DIV32) || \ + ((__HCLK__) == RCC_HCLK_DIV64) || ((__HCLK__) == RCC_HCLK_DIV128)) + +#define IS_RCC_PCLK1(__PCLK1__) (((__PCLK1__) == RCC_APB1_DIV1) || ((__PCLK1__) == RCC_APB1_DIV2) || \ + ((__PCLK1__) == RCC_APB1_DIV4) || ((__PCLK1__) == RCC_APB1_DIV8) || \ + ((__PCLK1__) == RCC_APB1_DIV16) || ((__PCLK1__) == RCC_APB1_DIV32) || \ + ((__PCLK1__) == RCC_APB1_DIV64) || ((__PCLK1__) == RCC_APB1_DIV128)) + +#define IS_RCC_PCLK2(__PCLK2__) (((__PCLK2__) == RCC_APB2_DIV1) || ((__PCLK2__) == RCC_APB2_DIV2) || \ + ((__PCLK2__) == RCC_APB2_DIV4) || ((__PCLK2__) == RCC_APB2_DIV8) || \ + ((__PCLK2__) == RCC_APB2_DIV16) || ((__PCLK2__) == RCC_APB2_DIV32) || \ + ((__PCLK2__) == RCC_APB2_DIV64) || ((__PCLK2__) == RCC_APB2_DIV128)) + +#define IS_RCC_PCLK4(__PCLK4__) (((__PCLK4__) == RCC_APB4_DIV1) || ((__PCLK4__) == RCC_APB4_DIV2) || \ + ((__PCLK4__) == RCC_APB4_DIV4) || ((__PCLK4__) == RCC_APB4_DIV8) || \ + ((__PCLK4__) == RCC_APB4_DIV16) || ((__PCLK4__) == RCC_APB4_DIV32) || \ + ((__PCLK4__) == RCC_APB4_DIV64) || ((__PCLK4__) == RCC_APB4_DIV128)) + +#define IS_RCC_PCLK5(__PCLK5__) (((__PCLK5__) == RCC_APB5_DIV1) || ((__PCLK5__) == RCC_APB5_DIV2) || \ + ((__PCLK5__) == RCC_APB5_DIV4) || ((__PCLK5__) == RCC_APB5_DIV8) || \ + ((__PCLK5__) == RCC_APB5_DIV16) || ((__PCLK5__) == RCC_APB5_DIV32) || \ + ((__PCLK5__) == RCC_APB5_DIV64) || ((__PCLK5__) == RCC_APB5_DIV128)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV36) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV49) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV64) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV81) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV100) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV121) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV144) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV169) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV196) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV225) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV256) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV289) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV324) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV361) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV400) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV441) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV484) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV529) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV576) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV625) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV676) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV729) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV784) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV841) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV900) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV961) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1024)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1089)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1156)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1225)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1296)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1369)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1444)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1521)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1600)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1681)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1764)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1849)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1936)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2025)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2116)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2209)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2304)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2401)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2500)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2601)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2704)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2809)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2916)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3025)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3136)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3249)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3364)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3481)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3600)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3721)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3844)|| \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3969)|| ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4096)) + +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_IC5) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_IC10) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSA)) + +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_LSI) || ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_MSI) || ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || ((__SOURCE__) == RCC_MCO2SOURCE_IC15) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_IC20) || ((__SOURCE__) == RCC_MCO2SOURCE_SYSB)) + +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_3) || ((__DIV__) == RCC_MCODIV_4) || \ + ((__DIV__) == RCC_MCODIV_5) || ((__DIV__) == RCC_MCODIV_6) || \ + ((__DIV__) == RCC_MCODIV_7) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_9) || ((__DIV__) == RCC_MCODIV_10) || \ + ((__DIV__) == RCC_MCODIV_11) || ((__DIV__) == RCC_MCODIV_12) || \ + ((__DIV__) == RCC_MCODIV_13) || ((__DIV__) == RCC_MCODIV_14) || \ + ((__DIV__) == RCC_MCODIV_15) || ((__DIV__) == RCC_MCODIV_16)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_RCC_MSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) + +#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ + ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) + +#define IS_RCC_ICCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ICCLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_ICCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_ICCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_ICCLKSOURCE_PLL4)) + +#define IS_RCC_ICCLKDIVIDER(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 256U)) + +#define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((((ITEM) & RCC_ITEM_ALL) != 0U) && (((ITEM) & ~RCC_ITEM_ALL) == 0U)) + +#define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_ITEM_LSI) || \ + ((ITEM) == RCC_ITEM_LSE) || \ + ((ITEM) == RCC_ITEM_MSI) || \ + ((ITEM) == RCC_ITEM_HSI) || \ + ((ITEM) == RCC_ITEM_HSE) || \ + ((ITEM) == RCC_ITEM_PLL1) || \ + ((ITEM) == RCC_ITEM_PLL2) || \ + ((ITEM) == RCC_ITEM_PLL3) || \ + ((ITEM) == RCC_ITEM_PLL4) || \ + ((ITEM) == RCC_ITEM_IC1) || \ + ((ITEM) == RCC_ITEM_IC2) || \ + ((ITEM) == RCC_ITEM_IC3) || \ + ((ITEM) == RCC_ITEM_IC4) || \ + ((ITEM) == RCC_ITEM_IC5) || \ + ((ITEM) == RCC_ITEM_IC6) || \ + ((ITEM) == RCC_ITEM_IC7) || \ + ((ITEM) == RCC_ITEM_IC8) || \ + ((ITEM) == RCC_ITEM_IC9) || \ + ((ITEM) == RCC_ITEM_IC10) || \ + ((ITEM) == RCC_ITEM_IC11) || \ + ((ITEM) == RCC_ITEM_IC12) || \ + ((ITEM) == RCC_ITEM_IC13) || \ + ((ITEM) == RCC_ITEM_IC14) || \ + ((ITEM) == RCC_ITEM_IC15) || \ + ((ITEM) == RCC_ITEM_IC16) || \ + ((ITEM) == RCC_ITEM_IC17) || \ + ((ITEM) == RCC_ITEM_IC18) || \ + ((ITEM) == RCC_ITEM_IC19) || \ + ((ITEM) == RCC_ITEM_IC20) || \ + ((ITEM) == RCC_ITEM_MOD) || \ + ((ITEM) == RCC_ITEM_SYS) || \ + ((ITEM) == RCC_ITEM_BUS) || \ + ((ITEM) == RCC_ITEM_PER) || \ + ((ITEM) == RCC_ITEM_INT) || \ + ((ITEM) == RCC_ITEM_RST) || \ + ((ITEM) == RCC_ITEM_ACLKN) || \ + ((ITEM) == RCC_ITEM_ACLKNC) || \ + ((ITEM) == RCC_ITEM_AHBM) || \ + ((ITEM) == RCC_ITEM_AHB1) || \ + ((ITEM) == RCC_ITEM_AHB2) || \ + ((ITEM) == RCC_ITEM_AHB3) || \ + ((ITEM) == RCC_ITEM_AHB4) || \ + ((ITEM) == RCC_ITEM_AHB5) || \ + ((ITEM) == RCC_ITEM_APB1) || \ + ((ITEM) == RCC_ITEM_APB2) || \ + ((ITEM) == RCC_ITEM_APB3) || \ + ((ITEM) == RCC_ITEM_APB4) || \ + ((ITEM) == RCC_ITEM_APB5) || \ + ((ITEM) == RCC_ITEM_NOC) || \ + ((ITEM) == RCC_ITEM_AXISRAM3) || \ + ((ITEM) == RCC_ITEM_AXISRAM4) || \ + ((ITEM) == RCC_ITEM_AXISRAM5) || \ + ((ITEM) == RCC_ITEM_AXISRAM6) || \ + ((ITEM) == RCC_ITEM_AHBSRAM1) || \ + ((ITEM) == RCC_ITEM_AHBSRAM2) || \ + ((ITEM) == RCC_ITEM_BKPSRAM) || \ + ((ITEM) == RCC_ITEM_AXISRAM1) || \ + ((ITEM) == RCC_ITEM_AXISRAM2) || \ + ((ITEM) == RCC_ITEM_FLEXRAM) || \ + ((ITEM) == RCC_ITEM_CACHEAXIRAM) || \ + ((ITEM) == RCC_ITEM_VENCRAM)) + + +#if defined (CPU_IN_SECURE_STATE) +#define IS_RCC_ATTRIBUTES(ATTRIBUTE) (((((ATTRIBUTE) & RCC_ATTR_SEC) == RCC_ATTR_SEC) || \ + (((ATTRIBUTE) & RCC_ATTR_NSEC) == RCC_ATTR_NSEC) || \ + (((ATTRIBUTE) & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) || \ + (((ATTRIBUTE) & RCC_ATTR_NPRIV) == RCC_ATTR_NPRIV) || \ + (((ATTRIBUTE) & RCC_ATTR_PUB) == RCC_ATTR_PUB) || \ + (((ATTRIBUTE) & RCC_ATTR_NPUB) == RCC_ATTR_NPUB) || \ + (((ATTRIBUTE) & RCC_ATTR_LOCK) == RCC_ATTR_LOCK)) && \ + (((ATTRIBUTE) & ~(RCC_ATTR_SEC|RCC_ATTR_NSEC|RCC_ATTR_PRIV|RCC_ATTR_NPRIV|\ + RCC_ATTR_PUB|RCC_ATTR_NPUB|RCC_ATTR_LOCK)) == 0U)) +#else +#define IS_RCC_ATTRIBUTES(ATTRIBUTE) (((((ATTRIBUTE) & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) || \ + (((ATTRIBUTE) & RCC_ATTR_NPRIV) == RCC_ATTR_NPRIV)) && \ + (((ATTRIBUTE) & ~(RCC_ATTR_PRIV|RCC_ATTR_NPRIV)) == 0U)) + +#endif /* CPU_IN_SECURE_STATE */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_RCC_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc_ex.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc_ex.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc_ex.h (revision 16) @@ -0,0 +1,3156 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_RCC_EX_H +#define STM32N6xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_ADC (0x0000000000000001UL) +#define RCC_PERIPHCLK_ADF1 (0x0000000000000002UL) +#define RCC_PERIPHCLK_CKPER (0x0000000000000004UL) +#define RCC_PERIPHCLK_CSI (0x0000000000000008UL) +#define RCC_PERIPHCLK_DCMIPP (0x0000000000000010UL) +#define RCC_PERIPHCLK_ETH1 (0x0000000000000020UL) +#define RCC_PERIPHCLK_ETH1PHY (0x0000000000000040UL) +#define RCC_PERIPHCLK_ETH1RX (0x0000000000000080UL) +#define RCC_PERIPHCLK_ETH1TX (0x0000000000000100UL) +#define RCC_PERIPHCLK_ETH1PTP (0x0000000000000200UL) +#define RCC_PERIPHCLK_FDCAN (0x0000000000000400UL) +#define RCC_PERIPHCLK_FMC (0x0000000000000800UL) +#define RCC_PERIPHCLK_I2C1 (0x0000000000001000UL) +#define RCC_PERIPHCLK_I2C2 (0x0000000000002000UL) +#define RCC_PERIPHCLK_I2C3 (0x0000000000004000UL) +#define RCC_PERIPHCLK_I2C4 (0x0000000000008000UL) +#define RCC_PERIPHCLK_I3C1 (0x0000000000010000UL) +#define RCC_PERIPHCLK_I3C2 (0x0000000000020000UL) +#define RCC_PERIPHCLK_LPTIM1 (0x0000000000040000UL) +#define RCC_PERIPHCLK_LPTIM2 (0x0000000000080000UL) +#define RCC_PERIPHCLK_LPTIM3 (0x0000000000100000UL) +#define RCC_PERIPHCLK_LPTIM4 (0x0000000000200000UL) +#define RCC_PERIPHCLK_LPTIM5 (0x0000000000400000UL) +#define RCC_PERIPHCLK_LPUART1 (0x0000000000800000UL) +#define RCC_PERIPHCLK_LTDC (0x0000000001000000UL) +#define RCC_PERIPHCLK_MDF1 (0x0000000002000000UL) +#define RCC_PERIPHCLK_PSSI (0x0000000004000000UL) +#define RCC_PERIPHCLK_RTC (0x0000000008000000UL) +#define RCC_PERIPHCLK_SAI1 (0x0000000010000000UL) +#define RCC_PERIPHCLK_SAI2 (0x0000000020000000UL) +#define RCC_PERIPHCLK_SDMMC1 (0x0000000040000000UL) +#define RCC_PERIPHCLK_SDMMC2 (0x0000000080000000UL) +#define RCC_PERIPHCLK_SPDIFRX1 (0x0000000100000000UL) +#define RCC_PERIPHCLK_SPI1 (0x0000000200000000UL) +#define RCC_PERIPHCLK_SPI2 (0x0000000400000000UL) +#define RCC_PERIPHCLK_SPI3 (0x0000000800000000UL) +#define RCC_PERIPHCLK_SPI4 (0x0000001000000000UL) +#define RCC_PERIPHCLK_SPI5 (0x0000002000000000UL) +#define RCC_PERIPHCLK_SPI6 (0x0000004000000000UL) +#define RCC_PERIPHCLK_TIM (0x0000008000000000UL) +#define RCC_PERIPHCLK_USART1 (0x0000010000000000UL) +#define RCC_PERIPHCLK_USART2 (0x0000020000000000UL) +#define RCC_PERIPHCLK_USART3 (0x0000040000000000UL) +#define RCC_PERIPHCLK_UART4 (0x0000080000000000UL) +#define RCC_PERIPHCLK_UART5 (0x0000100000000000UL) +#define RCC_PERIPHCLK_USART6 (0x0000200000000000UL) +#define RCC_PERIPHCLK_UART7 (0x0000400000000000UL) +#define RCC_PERIPHCLK_UART8 (0x0000800000000000UL) +#define RCC_PERIPHCLK_UART9 (0x0001000000000000UL) +#define RCC_PERIPHCLK_USART10 (0x0002000000000000UL) +#define RCC_PERIPHCLK_USBPHY1 (0x0004000000000000UL) +#define RCC_PERIPHCLK_USBOTGHS1 (0x0008000000000000UL) +#define RCC_PERIPHCLK_USBPHY2 (0x0010000000000000UL) +#define RCC_PERIPHCLK_USBOTGHS2 (0x0020000000000000UL) +#define RCC_PERIPHCLK_XSPI1 (0x0040000000000000UL) +#define RCC_PERIPHCLK_XSPI2 (0x0080000000000000UL) +#define RCC_PERIPHCLK_XSPI3 (0x0100000000000000UL) +/** + * @} + */ + + +/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source + * @{ + */ +#define RCC_ADCCLKSOURCE_HCLK LL_RCC_ADC_CLKSOURCE_HCLK +#define RCC_ADCCLKSOURCE_CLKP LL_RCC_ADC_CLKSOURCE_CLKP +#define RCC_ADCCLKSOURCE_IC7 LL_RCC_ADC_CLKSOURCE_IC7 +#define RCC_ADCCLKSOURCE_IC8 LL_RCC_ADC_CLKSOURCE_IC8 +#define RCC_ADCCLKSOURCE_MSI LL_RCC_ADC_CLKSOURCE_MSI +#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI +#define RCC_ADCCLKSOURCE_PIN LL_RCC_ADC_CLKSOURCE_I2S_CKIN +#define RCC_ADCCLKSOURCE_TIMG LL_RCC_ADC_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source + * @{ + */ +#define RCC_ADF1CLKSOURCE_HCLK LL_RCC_ADF1_CLKSOURCE_HCLK +#define RCC_ADF1CLKSOURCE_CLKP LL_RCC_ADF1_CLKSOURCE_CLKP +#define RCC_ADF1CLKSOURCE_IC7 LL_RCC_ADF1_CLKSOURCE_IC7 +#define RCC_ADF1CLKSOURCE_IC8 LL_RCC_ADF1_CLKSOURCE_IC8 +#define RCC_ADF1CLKSOURCE_MSI LL_RCC_ADF1_CLKSOURCE_MSI +#define RCC_ADF1CLKSOURCE_HSI LL_RCC_ADF1_CLKSOURCE_HSI +#define RCC_ADF1CLKSOURCE_PIN LL_RCC_ADF1_CLKSOURCE_I2S_CKIN +#define RCC_ADF1CLKSOURCE_TIMG LL_RCC_ADF1_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_CLKP_Clock_Source CLKP Clock Source + * @{ + */ +#define RCC_CLKPCLKSOURCE_HSI LL_RCC_CLKP_CLKSOURCE_HSI +#define RCC_CLKPCLKSOURCE_MSI LL_RCC_CLKP_CLKSOURCE_MSI +#define RCC_CLKPCLKSOURCE_HSE LL_RCC_CLKP_CLKSOURCE_HSE +#define RCC_CLKPCLKSOURCE_IC5 LL_RCC_CLKP_CLKSOURCE_IC5 +#define RCC_CLKPCLKSOURCE_IC10 LL_RCC_CLKP_CLKSOURCE_IC10 +#define RCC_CLKPCLKSOURCE_IC15 LL_RCC_CLKP_CLKSOURCE_IC15 +#define RCC_CLKPCLKSOURCE_IC19 LL_RCC_CLKP_CLKSOURCE_IC19 +#define RCC_CLKPCLKSOURCE_IC20 LL_RCC_CLKP_CLKSOURCE_IC20 +/** + * @} + */ + +/** @defgroup RCCEx_DCMIPP_Clock_Source DCMIPP Clock Source + * @{ + */ +#define RCC_DCMIPPCLKSOURCE_PCLK5 LL_RCC_DCMIPP_CLKSOURCE_PCLK5 +#define RCC_DCMIPPCLKSOURCE_CLKP LL_RCC_DCMIPP_CLKSOURCE_CLKP +#define RCC_DCMIPPCLKSOURCE_IC17 LL_RCC_DCMIPP_CLKSOURCE_IC17 +#define RCC_DCMIPPCLKSOURCE_HSI LL_RCC_DCMIPP_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_ETH1_Clock_Source ETH1 Clock Source + * @{ + */ +#define RCC_ETH1CLKSOURCE_HCLK LL_RCC_ETH1_CLKSOURCE_HCLK +#define RCC_ETH1CLKSOURCE_CLKP LL_RCC_ETH1_CLKSOURCE_CLKP +#define RCC_ETH1CLKSOURCE_IC12 LL_RCC_ETH1_CLKSOURCE_IC12 +#define RCC_ETH1CLKSOURCE_HSE LL_RCC_ETH1_CLKSOURCE_HSE +/** + * @} + */ + +/** @defgroup RCCEx_ETH1_PHY_Interface ETH1 PHY Interface + * @{ + */ +#define RCC_ETH1PHYIF_MII LL_RCC_ETH1PHY_IF_MII +#define RCC_ETH1PHYIF_RGMII LL_RCC_ETH1PHY_IF_RGMII +#define RCC_ETH1PHYIF_RMII LL_RCC_ETH1PHY_IF_RMII +/** + * @} + */ + +/** @defgroup RCCEx_ETH1_RX_Clock_Source ETH1 RX Clock Source + * @{ + */ +#define RCC_ETH1RXCLKSOURCE_EXT LL_RCC_ETH1REFRX_CLKSOURCE_EXT +#define RCC_ETH1RXCLKSOURCE_INT LL_RCC_ETH1REFRX_CLKSOURCE_INT +/** + * @} + */ + +/** @defgroup RCCEx_ETH1_TX_Clock_Source ETH1 TX Clock Source + * @{ + */ +#define RCC_ETH1TXCLKSOURCE_EXT LL_RCC_ETH1REFTX_CLKSOURCE_EXT +#define RCC_ETH1TXCLKSOURCE_INT LL_RCC_ETH1REFTX_CLKSOURCE_INT +/** + * @} + */ + +/** @defgroup RCCEx_ETH1_PTP_Clock_Source ETH1 PTP Clock Source + * @{ + */ +#define RCC_ETH1PTPCLKSOURCE_HCLK LL_RCC_ETH1PTP_CLKSOURCE_HCLK +#define RCC_ETH1PTPCLKSOURCE_CLKP LL_RCC_ETH1PTP_CLKSOURCE_CLKP +#define RCC_ETH1PTPCLKSOURCE_IC13 LL_RCC_ETH1PTP_CLKSOURCE_IC13 +#define RCC_ETH1PTPCLKSOURCE_HSE LL_RCC_ETH1PTP_CLKSOURCE_HSE +/** + * @} + */ + +/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source + * @{ + */ +#define RCC_FDCANCLKSOURCE_PCLK1 LL_RCC_FDCAN_CLKSOURCE_PCLK1 +#define RCC_FDCANCLKSOURCE_CLKP LL_RCC_FDCAN_CLKSOURCE_CLKP +#define RCC_FDCANCLKSOURCE_IC19 LL_RCC_FDCAN_CLKSOURCE_IC19 +#define RCC_FDCANCLKSOURCE_HSE LL_RCC_FDCAN_CLKSOURCE_HSE +/** + * @} + */ + +/** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source + * @{ + */ +#define RCC_FMCCLKSOURCE_HCLK LL_RCC_FMC_CLKSOURCE_HCLK +#define RCC_FMCCLKSOURCE_CLKP LL_RCC_FMC_CLKSOURCE_CLKP +#define RCC_FMCCLKSOURCE_IC3 LL_RCC_FMC_CLKSOURCE_IC3 +#define RCC_FMCCLKSOURCE_IC4 LL_RCC_FMC_CLKSOURCE_IC4 +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1 +#define RCC_I2C1CLKSOURCE_CLKP LL_RCC_I2C1_CLKSOURCE_CLKP +#define RCC_I2C1CLKSOURCE_IC10 LL_RCC_I2C1_CLKSOURCE_IC10 +#define RCC_I2C1CLKSOURCE_IC15 LL_RCC_I2C1_CLKSOURCE_IC15 +#define RCC_I2C1CLKSOURCE_MSI LL_RCC_I2C1_CLKSOURCE_MSI +#define RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 LL_RCC_I2C2_CLKSOURCE_PCLK1 +#define RCC_I2C2CLKSOURCE_CLKP LL_RCC_I2C2_CLKSOURCE_CLKP +#define RCC_I2C2CLKSOURCE_IC10 LL_RCC_I2C2_CLKSOURCE_IC10 +#define RCC_I2C2CLKSOURCE_IC15 LL_RCC_I2C2_CLKSOURCE_IC15 +#define RCC_I2C2CLKSOURCE_MSI LL_RCC_I2C2_CLKSOURCE_MSI +#define RCC_I2C2CLKSOURCE_HSI LL_RCC_I2C2_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1 +#define RCC_I2C3CLKSOURCE_CLKP LL_RCC_I2C3_CLKSOURCE_CLKP +#define RCC_I2C3CLKSOURCE_IC10 LL_RCC_I2C3_CLKSOURCE_IC10 +#define RCC_I2C3CLKSOURCE_IC15 LL_RCC_I2C3_CLKSOURCE_IC15 +#define RCC_I2C3CLKSOURCE_MSI LL_RCC_I2C3_CLKSOURCE_MSI +#define RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source + * @{ + */ +#define RCC_I2C4CLKSOURCE_PCLK1 LL_RCC_I2C4_CLKSOURCE_PCLK1 +#define RCC_I2C4CLKSOURCE_CLKP LL_RCC_I2C4_CLKSOURCE_CLKP +#define RCC_I2C4CLKSOURCE_IC10 LL_RCC_I2C4_CLKSOURCE_IC10 +#define RCC_I2C4CLKSOURCE_IC15 LL_RCC_I2C4_CLKSOURCE_IC15 +#define RCC_I2C4CLKSOURCE_MSI LL_RCC_I2C4_CLKSOURCE_MSI +#define RCC_I2C4CLKSOURCE_HSI LL_RCC_I2C4_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_I3C1_Clock_Source I3C1 Clock Source + * @{ + */ +#define RCC_I3C1CLKSOURCE_PCLK1 LL_RCC_I3C1_CLKSOURCE_PCLK1 +#define RCC_I3C1CLKSOURCE_CLKP LL_RCC_I3C1_CLKSOURCE_CLKP +#define RCC_I3C1CLKSOURCE_IC10 LL_RCC_I3C1_CLKSOURCE_IC10 +#define RCC_I3C1CLKSOURCE_IC15 LL_RCC_I3C1_CLKSOURCE_IC15 +#define RCC_I3C1CLKSOURCE_MSI LL_RCC_I3C1_CLKSOURCE_MSI +#define RCC_I3C1CLKSOURCE_HSI LL_RCC_I3C1_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_I3C2_Clock_Source I3C2 Clock Source + * @{ + */ +#define RCC_I3C2CLKSOURCE_PCLK1 LL_RCC_I3C2_CLKSOURCE_PCLK1 +#define RCC_I3C2CLKSOURCE_CLKP LL_RCC_I3C2_CLKSOURCE_CLKP +#define RCC_I3C2CLKSOURCE_IC10 LL_RCC_I3C2_CLKSOURCE_IC10 +#define RCC_I3C2CLKSOURCE_IC15 LL_RCC_I3C2_CLKSOURCE_IC15 +#define RCC_I3C2CLKSOURCE_MSI LL_RCC_I3C2_CLKSOURCE_MSI +#define RCC_I3C2CLKSOURCE_HSI LL_RCC_I3C2_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_CLKP LL_RCC_LPTIM1_CLKSOURCE_CLKP +#define RCC_LPTIM1CLKSOURCE_IC15 LL_RCC_LPTIM1_CLKSOURCE_IC15 +#define RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE +#define RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI +#define RCC_LPTIM1CLKSOURCE_TIMG LL_RCC_LPTIM1_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source + * @{ + */ +#define RCC_LPTIM2CLKSOURCE_PCLK4 LL_RCC_LPTIM2_CLKSOURCE_PCLK4 +#define RCC_LPTIM2CLKSOURCE_CLKP LL_RCC_LPTIM2_CLKSOURCE_CLKP +#define RCC_LPTIM2CLKSOURCE_IC15 LL_RCC_LPTIM2_CLKSOURCE_IC15 +#define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE +#define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI +#define RCC_LPTIM2CLKSOURCE_TIMG LL_RCC_LPTIM2_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source + * @{ + */ +#define RCC_LPTIM3CLKSOURCE_PCLK4 LL_RCC_LPTIM3_CLKSOURCE_PCLK4 +#define RCC_LPTIM3CLKSOURCE_CLKP LL_RCC_LPTIM3_CLKSOURCE_CLKP +#define RCC_LPTIM3CLKSOURCE_IC15 LL_RCC_LPTIM3_CLKSOURCE_IC15 +#define RCC_LPTIM3CLKSOURCE_LSE LL_RCC_LPTIM3_CLKSOURCE_LSE +#define RCC_LPTIM3CLKSOURCE_LSI LL_RCC_LPTIM3_CLKSOURCE_LSI +#define RCC_LPTIM3CLKSOURCE_TIMG LL_RCC_LPTIM3_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM4_Clock_Source LPTIM4 Clock Source + * @{ + */ +#define RCC_LPTIM4CLKSOURCE_PCLK4 LL_RCC_LPTIM4_CLKSOURCE_PCLK4 +#define RCC_LPTIM4CLKSOURCE_CLKP LL_RCC_LPTIM4_CLKSOURCE_CLKP +#define RCC_LPTIM4CLKSOURCE_IC15 LL_RCC_LPTIM4_CLKSOURCE_IC15 +#define RCC_LPTIM4CLKSOURCE_LSE LL_RCC_LPTIM4_CLKSOURCE_LSE +#define RCC_LPTIM4CLKSOURCE_LSI LL_RCC_LPTIM4_CLKSOURCE_LSI +#define RCC_LPTIM4CLKSOURCE_TIMG LL_RCC_LPTIM4_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM5_Clock_Source LPTIM5 Clock Source + * @{ + */ +#define RCC_LPTIM5CLKSOURCE_PCLK4 LL_RCC_LPTIM5_CLKSOURCE_PCLK4 +#define RCC_LPTIM5CLKSOURCE_CLKP LL_RCC_LPTIM5_CLKSOURCE_CLKP +#define RCC_LPTIM5CLKSOURCE_IC15 LL_RCC_LPTIM5_CLKSOURCE_IC15 +#define RCC_LPTIM5CLKSOURCE_LSE LL_RCC_LPTIM5_CLKSOURCE_LSE +#define RCC_LPTIM5CLKSOURCE_LSI LL_RCC_LPTIM5_CLKSOURCE_LSI +#define RCC_LPTIM5CLKSOURCE_TIMG LL_RCC_LPTIM5_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK4 LL_RCC_LPUART1_CLKSOURCE_PCLK4 +#define RCC_LPUART1CLKSOURCE_CLKP LL_RCC_LPUART1_CLKSOURCE_CLKP +#define RCC_LPUART1CLKSOURCE_IC9 LL_RCC_LPUART1_CLKSOURCE_IC9 +#define RCC_LPUART1CLKSOURCE_IC14 LL_RCC_LPUART1_CLKSOURCE_IC14 +#define RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE +#define RCC_LPUART1CLKSOURCE_MSI LL_RCC_LPUART1_CLKSOURCE_MSI +#define RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source + * @{ + */ +#define RCC_LTDCCLKSOURCE_PCLK5 LL_RCC_LTDC_CLKSOURCE_PCLK5 +#define RCC_LTDCCLKSOURCE_CLKP LL_RCC_LTDC_CLKSOURCE_CLKP +#define RCC_LTDCCLKSOURCE_IC16 LL_RCC_LTDC_CLKSOURCE_IC16 +#define RCC_LTDCCLKSOURCE_HSI LL_RCC_LTDC_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_MDF1_Clock_Source MDF1 Clock Source + * @{ + */ +#define RCC_MDF1CLKSOURCE_HCLK LL_RCC_MDF1_CLKSOURCE_HCLK +#define RCC_MDF1CLKSOURCE_CLKP LL_RCC_MDF1_CLKSOURCE_CLKP +#define RCC_MDF1CLKSOURCE_IC7 LL_RCC_MDF1_CLKSOURCE_IC7 +#define RCC_MDF1CLKSOURCE_IC8 LL_RCC_MDF1_CLKSOURCE_IC8 +#define RCC_MDF1CLKSOURCE_MSI LL_RCC_MDF1_CLKSOURCE_MSI +#define RCC_MDF1CLKSOURCE_HSI LL_RCC_MDF1_CLKSOURCE_HSI +#define RCC_MDF1CLKSOURCE_PIN LL_RCC_MDF1_CLKSOURCE_I2S_CKIN +#define RCC_MDF1CLKSOURCE_TIMG LL_RCC_MDF1_CLKSOURCE_TIMG +/** + * @} + */ + +/** @defgroup RCCEx_PSSI_Clock_Source PSSI Clock Source + * @{ + */ +#define RCC_PSSICLKSOURCE_HCLK LL_RCC_PSSI_CLKSOURCE_HCLK +#define RCC_PSSICLKSOURCE_CLKP LL_RCC_PSSI_CLKSOURCE_CLKP +#define RCC_PSSICLKSOURCE_IC20 LL_RCC_PSSI_CLKSOURCE_IC20 +#define RCC_PSSICLKSOURCE_HSI LL_RCC_PSSI_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PCLK2 LL_RCC_SAI1_CLKSOURCE_PCLK2 +#define RCC_SAI1CLKSOURCE_CLKP LL_RCC_SAI1_CLKSOURCE_CLKP +#define RCC_SAI1CLKSOURCE_IC7 LL_RCC_SAI1_CLKSOURCE_IC7 +#define RCC_SAI1CLKSOURCE_IC8 LL_RCC_SAI1_CLKSOURCE_IC8 +#define RCC_SAI1CLKSOURCE_MSI LL_RCC_SAI1_CLKSOURCE_MSI +#define RCC_SAI1CLKSOURCE_HSI LL_RCC_SAI1_CLKSOURCE_HSI +#define RCC_SAI1CLKSOURCE_PIN LL_RCC_SAI1_CLKSOURCE_I2S_CKIN +#define RCC_SAI1CLKSOURCE_SPDIFRX1 LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PCLK2 LL_RCC_SAI2_CLKSOURCE_PCLK2 +#define RCC_SAI2CLKSOURCE_CLKP LL_RCC_SAI2_CLKSOURCE_CLKP +#define RCC_SAI2CLKSOURCE_IC7 LL_RCC_SAI2_CLKSOURCE_IC7 +#define RCC_SAI2CLKSOURCE_IC8 LL_RCC_SAI2_CLKSOURCE_IC8 +#define RCC_SAI2CLKSOURCE_MSI LL_RCC_SAI2_CLKSOURCE_MSI +#define RCC_SAI2CLKSOURCE_HSI LL_RCC_SAI2_CLKSOURCE_HSI +#define RCC_SAI2CLKSOURCE_PIN LL_RCC_SAI2_CLKSOURCE_I2S_CKIN +#define RCC_SAI2CLKSOURCE_SPDIFRX1 LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 +/** + * @} + */ + +/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source + * @{ + */ +#define RCC_SDMMC1CLKSOURCE_HCLK LL_RCC_SDMMC1_CLKSOURCE_HCLK +#define RCC_SDMMC1CLKSOURCE_CLKP LL_RCC_SDMMC1_CLKSOURCE_CLKP +#define RCC_SDMMC1CLKSOURCE_IC4 LL_RCC_SDMMC1_CLKSOURCE_IC4 +#define RCC_SDMMC1CLKSOURCE_IC5 LL_RCC_SDMMC1_CLKSOURCE_IC5 +/** + * @} + */ + +/** @defgroup RCCEx_SDMMC2_Clock_Source SDMMC2 Clock Source + * @{ + */ +#define RCC_SDMMC2CLKSOURCE_HCLK LL_RCC_SDMMC2_CLKSOURCE_HCLK +#define RCC_SDMMC2CLKSOURCE_CLKP LL_RCC_SDMMC2_CLKSOURCE_CLKP +#define RCC_SDMMC2CLKSOURCE_IC4 LL_RCC_SDMMC2_CLKSOURCE_IC4 +#define RCC_SDMMC2CLKSOURCE_IC5 LL_RCC_SDMMC2_CLKSOURCE_IC5 +/** + * @} + */ + +/** @defgroup RCCEx_SPDIFRX1_Clock_Source SPDIFRX1 Clock Source + * @{ + */ +#define RCC_SPDIFRX1CLKSOURCE_PCLK1 LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1 +#define RCC_SPDIFRX1CLKSOURCE_CLKP LL_RCC_SPDIFRX1_CLKSOURCE_CLKP +#define RCC_SPDIFRX1CLKSOURCE_IC7 LL_RCC_SPDIFRX1_CLKSOURCE_IC7 +#define RCC_SPDIFRX1CLKSOURCE_IC8 LL_RCC_SPDIFRX1_CLKSOURCE_IC8 +#define RCC_SPDIFRX1CLKSOURCE_MSI LL_RCC_SPDIFRX1_CLKSOURCE_MSI +#define RCC_SPDIFRX1CLKSOURCE_HSI LL_RCC_SPDIFRX1_CLKSOURCE_HSI +#define RCC_SPDIFRX1CLKSOURCE_PIN LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN +/** + * @} + */ + +/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source + * @{ + */ +#define RCC_SPI1CLKSOURCE_PCLK2 LL_RCC_SPI1_CLKSOURCE_PCLK2 +#define RCC_SPI1CLKSOURCE_CLKP LL_RCC_SPI1_CLKSOURCE_CLKP +#define RCC_SPI1CLKSOURCE_IC8 LL_RCC_SPI1_CLKSOURCE_IC8 +#define RCC_SPI1CLKSOURCE_IC9 LL_RCC_SPI1_CLKSOURCE_IC9 +#define RCC_SPI1CLKSOURCE_MSI LL_RCC_SPI1_CLKSOURCE_MSI +#define RCC_SPI1CLKSOURCE_HSI LL_RCC_SPI1_CLKSOURCE_HSI +#define RCC_SPI1CLKSOURCE_PIN LL_RCC_SPI1_CLKSOURCE_I2S_CKIN +/** + * @} + */ + +/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source + * @{ + */ +#define RCC_SPI2CLKSOURCE_PCLK1 LL_RCC_SPI2_CLKSOURCE_PCLK1 +#define RCC_SPI2CLKSOURCE_CLKP LL_RCC_SPI2_CLKSOURCE_CLKP +#define RCC_SPI2CLKSOURCE_IC8 LL_RCC_SPI2_CLKSOURCE_IC8 +#define RCC_SPI2CLKSOURCE_IC9 LL_RCC_SPI2_CLKSOURCE_IC9 +#define RCC_SPI2CLKSOURCE_MSI LL_RCC_SPI2_CLKSOURCE_MSI +#define RCC_SPI2CLKSOURCE_HSI LL_RCC_SPI2_CLKSOURCE_HSI +#define RCC_SPI2CLKSOURCE_PIN LL_RCC_SPI2_CLKSOURCE_I2S_CKIN +/** + * @} + */ + +/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source + * @{ + */ +#define RCC_SPI3CLKSOURCE_PCLK1 LL_RCC_SPI3_CLKSOURCE_PCLK1 +#define RCC_SPI3CLKSOURCE_CLKP LL_RCC_SPI3_CLKSOURCE_CLKP +#define RCC_SPI3CLKSOURCE_IC8 LL_RCC_SPI3_CLKSOURCE_IC8 +#define RCC_SPI3CLKSOURCE_IC9 LL_RCC_SPI3_CLKSOURCE_IC9 +#define RCC_SPI3CLKSOURCE_MSI LL_RCC_SPI3_CLKSOURCE_MSI +#define RCC_SPI3CLKSOURCE_HSI LL_RCC_SPI3_CLKSOURCE_HSI +#define RCC_SPI3CLKSOURCE_PIN LL_RCC_SPI3_CLKSOURCE_I2S_CKIN +/** + * @} + */ + +/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source + * @{ + */ +#define RCC_SPI4CLKSOURCE_PCLK2 LL_RCC_SPI4_CLKSOURCE_PCLK2 +#define RCC_SPI4CLKSOURCE_CLKP LL_RCC_SPI4_CLKSOURCE_CLKP +#define RCC_SPI4CLKSOURCE_IC9 LL_RCC_SPI4_CLKSOURCE_IC9 +#define RCC_SPI4CLKSOURCE_IC14 LL_RCC_SPI4_CLKSOURCE_IC14 +#define RCC_SPI4CLKSOURCE_MSI LL_RCC_SPI4_CLKSOURCE_MSI +#define RCC_SPI4CLKSOURCE_HSI LL_RCC_SPI4_CLKSOURCE_HSI +#define RCC_SPI4CLKSOURCE_HSE LL_RCC_SPI4_CLKSOURCE_HSE +/** + * @} + */ + +/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source + * @{ + */ +#define RCC_SPI5CLKSOURCE_PCLK2 LL_RCC_SPI5_CLKSOURCE_PCLK2 +#define RCC_SPI5CLKSOURCE_CLKP LL_RCC_SPI5_CLKSOURCE_CLKP +#define RCC_SPI5CLKSOURCE_IC9 LL_RCC_SPI5_CLKSOURCE_IC9 +#define RCC_SPI5CLKSOURCE_IC14 LL_RCC_SPI5_CLKSOURCE_IC14 +#define RCC_SPI5CLKSOURCE_MSI LL_RCC_SPI5_CLKSOURCE_MSI +#define RCC_SPI5CLKSOURCE_HSI LL_RCC_SPI5_CLKSOURCE_HSI +#define RCC_SPI5CLKSOURCE_HSE LL_RCC_SPI5_CLKSOURCE_HSE +/** + * @} + */ + +/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source + * @{ + */ +#define RCC_SPI6CLKSOURCE_PCLK4 LL_RCC_SPI6_CLKSOURCE_PCLK4 +#define RCC_SPI6CLKSOURCE_CLKP LL_RCC_SPI6_CLKSOURCE_CLKP +#define RCC_SPI6CLKSOURCE_IC8 LL_RCC_SPI6_CLKSOURCE_IC8 +#define RCC_SPI6CLKSOURCE_IC9 LL_RCC_SPI6_CLKSOURCE_IC9 +#define RCC_SPI6CLKSOURCE_MSI LL_RCC_SPI6_CLKSOURCE_MSI +#define RCC_SPI6CLKSOURCE_HSI LL_RCC_SPI6_CLKSOURCE_HSI +#define RCC_SPI6CLKSOURCE_PIN LL_RCC_SPI6_CLKSOURCE_I2S_CKIN +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2 +#define RCC_USART1CLKSOURCE_CLKP LL_RCC_USART1_CLKSOURCE_CLKP +#define RCC_USART1CLKSOURCE_IC9 LL_RCC_USART1_CLKSOURCE_IC9 +#define RCC_USART1CLKSOURCE_IC14 LL_RCC_USART1_CLKSOURCE_IC14 +#define RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE +#define RCC_USART1CLKSOURCE_MSI LL_RCC_USART1_CLKSOURCE_MSI +#define RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 LL_RCC_USART2_CLKSOURCE_PCLK1 +#define RCC_USART2CLKSOURCE_CLKP LL_RCC_USART2_CLKSOURCE_CLKP +#define RCC_USART2CLKSOURCE_IC9 LL_RCC_USART2_CLKSOURCE_IC9 +#define RCC_USART2CLKSOURCE_IC14 LL_RCC_USART2_CLKSOURCE_IC14 +#define RCC_USART2CLKSOURCE_LSE LL_RCC_USART2_CLKSOURCE_LSE +#define RCC_USART2CLKSOURCE_MSI LL_RCC_USART2_CLKSOURCE_MSI +#define RCC_USART2CLKSOURCE_HSI LL_RCC_USART2_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 LL_RCC_USART3_CLKSOURCE_PCLK1 +#define RCC_USART3CLKSOURCE_CLKP LL_RCC_USART3_CLKSOURCE_CLKP +#define RCC_USART3CLKSOURCE_IC9 LL_RCC_USART3_CLKSOURCE_IC9 +#define RCC_USART3CLKSOURCE_IC14 LL_RCC_USART3_CLKSOURCE_IC14 +#define RCC_USART3CLKSOURCE_LSE LL_RCC_USART3_CLKSOURCE_LSE +#define RCC_USART3CLKSOURCE_MSI LL_RCC_USART3_CLKSOURCE_MSI +#define RCC_USART3CLKSOURCE_HSI LL_RCC_USART3_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 LL_RCC_UART4_CLKSOURCE_PCLK1 +#define RCC_UART4CLKSOURCE_CLKP LL_RCC_UART4_CLKSOURCE_CLKP +#define RCC_UART4CLKSOURCE_IC9 LL_RCC_UART4_CLKSOURCE_IC9 +#define RCC_UART4CLKSOURCE_IC14 LL_RCC_UART4_CLKSOURCE_IC14 +#define RCC_UART4CLKSOURCE_LSE LL_RCC_UART4_CLKSOURCE_LSE +#define RCC_UART4CLKSOURCE_MSI LL_RCC_UART4_CLKSOURCE_MSI +#define RCC_UART4CLKSOURCE_HSI LL_RCC_UART4_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 LL_RCC_UART5_CLKSOURCE_PCLK1 +#define RCC_UART5CLKSOURCE_CLKP LL_RCC_UART5_CLKSOURCE_CLKP +#define RCC_UART5CLKSOURCE_IC9 LL_RCC_UART5_CLKSOURCE_IC9 +#define RCC_UART5CLKSOURCE_IC14 LL_RCC_UART5_CLKSOURCE_IC14 +#define RCC_UART5CLKSOURCE_LSE LL_RCC_UART5_CLKSOURCE_LSE +#define RCC_UART5CLKSOURCE_MSI LL_RCC_UART5_CLKSOURCE_MSI +#define RCC_UART5CLKSOURCE_HSI LL_RCC_UART5_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source + * @{ + */ +#define RCC_USART6CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK2 +#define RCC_USART6CLKSOURCE_CLKP LL_RCC_USART6_CLKSOURCE_CLKP +#define RCC_USART6CLKSOURCE_IC9 LL_RCC_USART6_CLKSOURCE_IC9 +#define RCC_USART6CLKSOURCE_IC14 LL_RCC_USART6_CLKSOURCE_IC14 +#define RCC_USART6CLKSOURCE_LSE LL_RCC_USART6_CLKSOURCE_LSE +#define RCC_USART6CLKSOURCE_MSI LL_RCC_USART6_CLKSOURCE_MSI +#define RCC_USART6CLKSOURCE_HSI LL_RCC_USART6_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_UART7_Clock_Source UART7 Clock Source + * @{ + */ +#define RCC_UART7CLKSOURCE_PCLK1 LL_RCC_UART7_CLKSOURCE_PCLK1 +#define RCC_UART7CLKSOURCE_CLKP LL_RCC_UART7_CLKSOURCE_CLKP +#define RCC_UART7CLKSOURCE_IC9 LL_RCC_UART7_CLKSOURCE_IC9 +#define RCC_UART7CLKSOURCE_IC14 LL_RCC_UART7_CLKSOURCE_IC14 +#define RCC_UART7CLKSOURCE_LSE LL_RCC_UART7_CLKSOURCE_LSE +#define RCC_UART7CLKSOURCE_MSI LL_RCC_UART7_CLKSOURCE_MSI +#define RCC_UART7CLKSOURCE_HSI LL_RCC_UART7_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_UART8_Clock_Source UART8 Clock Source + * @{ + */ +#define RCC_UART8CLKSOURCE_PCLK1 LL_RCC_UART8_CLKSOURCE_PCLK1 +#define RCC_UART8CLKSOURCE_CLKP LL_RCC_UART8_CLKSOURCE_CLKP +#define RCC_UART8CLKSOURCE_IC9 LL_RCC_UART8_CLKSOURCE_IC9 +#define RCC_UART8CLKSOURCE_IC14 LL_RCC_UART8_CLKSOURCE_IC14 +#define RCC_UART8CLKSOURCE_LSE LL_RCC_UART8_CLKSOURCE_LSE +#define RCC_UART8CLKSOURCE_MSI LL_RCC_UART8_CLKSOURCE_MSI +#define RCC_UART8CLKSOURCE_HSI LL_RCC_UART8_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_UART9_Clock_Source UART9 Clock Source + * @{ + */ +#define RCC_UART9CLKSOURCE_PCLK2 LL_RCC_UART9_CLKSOURCE_PCLK2 +#define RCC_UART9CLKSOURCE_CLKP LL_RCC_UART9_CLKSOURCE_CLKP +#define RCC_UART9CLKSOURCE_IC9 LL_RCC_UART9_CLKSOURCE_IC9 +#define RCC_UART9CLKSOURCE_IC14 LL_RCC_UART9_CLKSOURCE_IC14 +#define RCC_UART9CLKSOURCE_LSE LL_RCC_UART9_CLKSOURCE_LSE +#define RCC_UART9CLKSOURCE_MSI LL_RCC_UART9_CLKSOURCE_MSI +#define RCC_UART9CLKSOURCE_HSI LL_RCC_UART9_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_USART10_Clock_Source USART10 Clock Source + * @{ + */ +#define RCC_USART10CLKSOURCE_PCLK2 LL_RCC_USART10_CLKSOURCE_PCLK2 +#define RCC_USART10CLKSOURCE_CLKP LL_RCC_USART10_CLKSOURCE_CLKP +#define RCC_USART10CLKSOURCE_IC9 LL_RCC_USART10_CLKSOURCE_IC9 +#define RCC_USART10CLKSOURCE_IC14 LL_RCC_USART10_CLKSOURCE_IC14 +#define RCC_USART10CLKSOURCE_LSE LL_RCC_USART10_CLKSOURCE_LSE +#define RCC_USART10CLKSOURCE_MSI LL_RCC_USART10_CLKSOURCE_MSI +#define RCC_USART10CLKSOURCE_HSI LL_RCC_USART10_CLKSOURCE_HSI +/** + * @} + */ + +/** @defgroup RCCEx_USBPHY1_Clock_Source USBPHY1 Clock Source + * @{ + */ +#define RCC_USBPHY1CLKSOURCE_HSE_DIV2 LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 +#define RCC_USBPHY1CLKSOURCE_CLKP LL_RCC_OTGPHY1_CLKSOURCE_CLKP +#define RCC_USBPHY1CLKSOURCE_IC15 LL_RCC_OTGPHY1_CLKSOURCE_IC15 +#define RCC_USBPHY1CLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC +#define RCC_USBPHY1CLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) +/** + * @} + */ + +/** @defgroup RCCEx_USBPHY2_Clock_Source USBPHY2 Clock Source + * @{ + */ +#define RCC_USBPHY2CLKSOURCE_HSE_DIV2 LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 +#define RCC_USBPHY2CLKSOURCE_CLKP LL_RCC_OTGPHY2_CLKSOURCE_CLKP +#define RCC_USBPHY2CLKSOURCE_IC15 LL_RCC_OTGPHY2_CLKSOURCE_IC15 +#define RCC_USBPHY2CLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC +#define RCC_USBPHY2CLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) +/** + * @} + */ + +/** @defgroup RCCEx_USB_OTGHS1_Clock_Source USB OTGHS1 Clock Source + * @{ + */ +#define RCC_USBOTGHS1CLKSOURCE_OTGPHY1 LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 +#define RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC +#define RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) +/** + * @} + */ + +/** @defgroup RCCEx_USB_OTGHS2_Clock_Source USB OTGHS2 Clock Source + * @{ + */ +#define RCC_USBOTGHS2CLKSOURCE_OTGPHY2 LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 +#define RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC +#define RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2 (LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL) +/** + * @} + */ + +/** @defgroup RCCEx_XSPI1_Clock_Source XSPI1 Clock Source + * @{ + */ +#define RCC_XSPI1CLKSOURCE_HCLK LL_RCC_XSPI1_CLKSOURCE_HCLK +#define RCC_XSPI1CLKSOURCE_CLKP LL_RCC_XSPI1_CLKSOURCE_CLKP +#define RCC_XSPI1CLKSOURCE_IC3 LL_RCC_XSPI1_CLKSOURCE_IC3 +#define RCC_XSPI1CLKSOURCE_IC4 LL_RCC_XSPI1_CLKSOURCE_IC4 +/** + * @} + */ + +/** @defgroup RCCEx_XSPI2_Clock_Source XSPI2 Clock Source + * @{ + */ +#define RCC_XSPI2CLKSOURCE_HCLK LL_RCC_XSPI2_CLKSOURCE_HCLK +#define RCC_XSPI2CLKSOURCE_CLKP LL_RCC_XSPI2_CLKSOURCE_CLKP +#define RCC_XSPI2CLKSOURCE_IC3 LL_RCC_XSPI2_CLKSOURCE_IC3 +#define RCC_XSPI2CLKSOURCE_IC4 LL_RCC_XSPI2_CLKSOURCE_IC4 +/** + * @} + */ + +/** @defgroup RCCEx_XSPI3_Clock_Source XSPI3 Clock Source + * @{ + */ +#define RCC_XSPI3CLKSOURCE_HCLK LL_RCC_XSPI3_CLKSOURCE_HCLK +#define RCC_XSPI3CLKSOURCE_CLKP LL_RCC_XSPI3_CLKSOURCE_CLKP +#define RCC_XSPI3CLKSOURCE_IC3 LL_RCC_XSPI3_CLKSOURCE_IC3 +#define RCC_XSPI3CLKSOURCE_IC4 LL_RCC_XSPI3_CLKSOURCE_IC4 +/** + * @} + */ + + +/** @defgroup RCCEx_TIM_Prescaler_Selection TIM Prescaler Selection + * @{ + */ +#define RCC_TIMPRES_DIV1 LL_RCC_TIM_PRESCALER_1 /*!< Timers clocks prescaler divide by 1 */ +#define RCC_TIMPRES_DIV2 LL_RCC_TIM_PRESCALER_2 /*!< Timers clocks prescaler divide by 2 */ +#define RCC_TIMPRES_DIV4 LL_RCC_TIM_PRESCALER_4 /*!< Timers clocks prescaler divide by 4 */ +#define RCC_TIMPRES_DIV8 LL_RCC_TIM_PRESCALER_8 /*!< Timers clocks prescaler divide by 8 */ +/** + * @} + */ + +/** @defgroup RCCEx_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define RCC_PERIPH_FREQUENCY_NO LL_RCC_PERIPH_FREQUENCY_NO /*!< No clock enabled for the peripheral */ +#define RCC_PERIPH_FREQUENCY_NA LL_RCC_PERIPH_FREQUENCY_NA /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ + +/** @defgroup RCCEx_IC_Selection_Max Maximum IC Selection + * @{ + */ +#define RCC_IC_MAX_NUMBER 20U +/** + * @} + */ + +/** @defgroup RCCEx_IC_Selection IC Selection + * @{ + */ +#define RCC_IC1 0U /*!< IC1 source is PLL1 output by default */ +#define RCC_IC2 1U /*!< IC2 source is PLL1 output by default */ +#define RCC_IC3 2U /*!< IC3 source is PLL1 output by default */ +#define RCC_IC4 3U /*!< IC4 source is PLL1 output by default */ +#define RCC_IC5 4U /*!< IC5 source is PLL1 output by default */ +#define RCC_IC6 5U /*!< IC6 source is PLL1 output by default */ +#define RCC_IC7 6U /*!< IC7 source is PLL2 output by default */ +#define RCC_IC8 7U /*!< IC8 source is PLL2 output by default */ +#define RCC_IC9 8U /*!< IC9 source is PLL2 output by default */ +#define RCC_IC10 9U /*!< IC10 source is PLL2 output by default */ +#define RCC_IC11 10U /*!< IC11 source is PLL1 output by default */ +#define RCC_IC12 11U /*!< IC12 source is PLL3 output by default */ +#define RCC_IC13 12U /*!< IC13 source is PLL3 output by default */ +#define RCC_IC14 13U /*!< IC14 source is PLL3 output by default */ +#define RCC_IC15 14U /*!< IC15 source is PLL3 output by default */ +#define RCC_IC16 15U /*!< IC16 source is PLL4 output by default */ +#define RCC_IC17 16U /*!< IC17 source is PLL4 output by default */ +#define RCC_IC18 17U /*!< IC18 source is PLL4 output by default */ +#define RCC_IC19 18U /*!< IC19 source is PLL4 output by default */ +#define RCC_IC20 19U /*!< IC20 source is PLL4 output by default */ +/** + * @} + */ + +/** @defgroup RCCEx_EXTI_LINE_LSECSS LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS EXTI_IMR3_IM65 /*!< LSE CSS failure interrupt connected to direct EXTI line 65 (Tamper) */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Selection PLL selection + * @{ + */ +#define RCC_PLL1 0U +#define RCC_PLL2 1U +#define RCC_PLL3 2U +#define RCC_PLL4 3U +/** + * @} + */ + +/** @defgroup RCC_PLL_SSCGSpread_Mode PLL SSCG spread mode selection + * @{ + */ +#define RCC_PLL_SSCG_CENTER 0U /*!< PLL SSCG center spread modulation */ +#define RCC_PLL_SSCG_DOWN 1U /*!< PLL SSCG down spread modulation */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_ICInitTypeDef ICSelection[RCC_IC_MAX_NUMBER]; /*!< ICx structure parameters. + This parameter shall be used when ICx is selected as kernel clock source + for some peripherals */ + + uint32_t FmcClockSelection; /*!< Specifies FMC clock source. + This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ + + uint32_t Xspi1ClockSelection; /*!< Specifies XSPI1 clock source. + This parameter can be a value of @ref RCCEx_XSPI1_Clock_Source */ + + uint32_t Xspi2ClockSelection; /*!< Specifies XSPI2 clock source. + This parameter can be a value of @ref RCCEx_XSPI2_Clock_Source */ + + uint32_t Xspi3ClockSelection; /*!< Specifies XSPI3 clock source. + This parameter can be a value of @ref RCCEx_XSPI3_Clock_Source */ + + uint32_t CkperClockSelection; /*!< Specifies CKPER clock source. + This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ + + uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. + This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ + + uint32_t AdcDivider; /*!< Specifies ADC clock divider. + This parameter can be a value between 1 to 256 */ + + uint32_t Adf1ClockSelection; /*!< Specifies ADF1 Clock clock source. + This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ + + uint32_t DcmippClockSelection; /*!< Specifies DCMIPP clock source. + This parameter can be a value of @ref RCCEx_DCMIPP_Clock_Source */ + + uint32_t Eth1ClockSelection; /*!< Specifies ETH1 clock source. + This parameter can be a value of @ref RCCEx_ETH1_Clock_Source */ + + uint32_t Eth1PhyInterfaceSelection; /*!< Specifies ETH1 PHY interface. + This parameter can be a value of @ref RCCEx_ETH1_PHY_Interface */ + + uint32_t Eth1RxClockSelection; /*!< Specifies ETH1 RX clock source. + This parameter can be a value of @ref RCCEx_ETH1_RX_Clock_Source */ + + uint32_t Eth1TxClockSelection; /*!< Specifies ETH1 TX clock source. + This parameter can be a value of @ref RCCEx_ETH1_TX_Clock_Source */ + + uint32_t Eth1PtpClockSelection; /*!< Specifies ETH1 PTP clock source. + This parameter can be a value of @ref RCCEx_ETH1_PTP_Clock_Source */ + + uint32_t Eth1PtpDivider; /*!< Specifies ETH1 PTP clock divider. + This parameter can be a value between 1 to 16 */ + + uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source. + This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. + This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ + + uint32_t I3c1ClockSelection; /*!< Specifies I3C1 clock source. + This parameter can be a value of @ref RCCEx_I3C1_Clock_Source */ + + uint32_t I3c2ClockSelection; /*!< Specifies I3C2 clock source. + This parameter can be a value of @ref RCCEx_I3C2_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. + This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ + + uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. + This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ + + uint32_t Lptim4ClockSelection; /*!< Specifies LPTIM4 clock source. + This parameter can be a value of @ref RCCEx_LPTIM4_Clock_Source */ + + uint32_t Lptim5ClockSelection; /*!< Specifies LPTIM5 clock source. + This parameter can be a value of @ref RCCEx_LPTIM5_Clock_Source */ + + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ + + uint32_t LtdcClockSelection; /*!< Specifies LPUART1 clock source. + This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ + + uint32_t Mdf1ClockSelection; /*!< Specifies MDF1 Clock clock source. + This parameter can be a value of @ref RCCEx_MDF1_Clock_Source */ + + uint32_t PssiClockSelection; /*!< Specifies PSSI clock source. + This parameter can be a value of @ref RCCEx_PSSI_Clock_Source */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source. + This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ + + uint32_t Sdmmc2ClockSelection; /*!< Specifies SDMMC2 clock source. + This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ + + uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source. + This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ + + uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source. + This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ + + uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source. + This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ + + uint32_t Spi4ClockSelection; /*!< Specifies SPI4 clock source. + This parameter can be a value of @ref RCCEx_SPI4_Clock_Source */ + + uint32_t Spi5ClockSelection; /*!< Specifies SPI5 clock source. + This parameter can be a value of @ref RCCEx_SPI5_Clock_Source */ + + uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source. + This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ + + uint32_t Spdifrx1ClockSelection; /*!< Specifies SPDIFRX1 Clock clock source. + This parameter can be a value of @ref RCCEx_SPDIFRX1_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. + This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ + + uint32_t Uart7ClockSelection; /*!< Specifies UART7 clock source. + This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ + + uint32_t Uart8ClockSelection; /*!< Specifies UART8 clock source. + This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ + + uint32_t Uart9ClockSelection; /*!< Specifies UART9 clock source. + This parameter can be a value of @ref RCCEx_UART9_Clock_Source */ + + uint32_t Usart10ClockSelection; /*!< Specifies USART10 clock source. + This parameter can be a value of @ref RCCEx_USART10_Clock_Source */ + + uint32_t UsbPhy1ClockSelection; /*!< Specifies USBPHY1 clock source. + This parameter can be a value of @ref RCCEx_USBPHY1_Clock_Source */ + + uint32_t UsbOtgHs1ClockSelection; /*!< Specifies USB OTG HS1 clock source. + This parameter can be a value of @ref RCCEx_USB_OTGHS1_Clock_Source */ + + uint32_t UsbPhy2ClockSelection; /*!< Specifies USBPHY2 clock source. + This parameter can be a value of @ref RCCEx_USBPHY2_Clock_Source */ + + uint32_t UsbOtgHs2ClockSelection; /*!< Specifies USB OTG HS2 clock source. + This parameter can be a value of @ref RCCEx_USB_OTGHS2_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; + +/** + * @brief RCC Extended PLL configuration structure definition + * (allow to configure the PLL in SSCG mode) + */ +typedef struct +{ + uint32_t PLLModDiv; /*!< Modulation division frequency. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xF */ + uint32_t PLLModSpreadDepth; /*!< Modulation spread spectrum depth. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1F */ + uint32_t PLLModSpreadMode; /*!< Modulation spread spectrum mode. + This parameter must be a value of @ref RCC_PLL_SSCGSpread_Mode */ +} RCC_PLLSSCGInitTypeDef; +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** + * @brief Macro to configure the PLL1 SSCG Spread Depth + * @note This configuration cannot be requested when the PLL1 has been enabled. + * + * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. + * It should be a value between 0 and 0x1F. + * @retval None + */ +#define __HAL_RCC_PLL1_MODSPR_CONFIG(__PLLMODSPR__) \ + MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL1CFGR3_PLL1MODSPR_Pos) + +/** + * @brief Macro to configure the PLL1 SSCG Spread Mode + * @note This configuration cannot be requested when the PLL1 has been enabled. + * + * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. + * It should be a value of @ref RCC_PLL_SSCGSpread_Mode + * @retval None + */ +#define __HAL_RCC_PLL1_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ + MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) + + +/** + * @brief Macro to configure the PLL2 SSCG Spread Depth + * @note This configuration cannot be requested when the PLL2 has been enabled. + * + * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. + * It should be a value between 0 and 0x1F. + * @retval None + */ +#define __HAL_RCC_PLL2_MODSPR_CONFIG(__PLLMODSPR__) \ + MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL2CFGR3_PLL2MODSPR_Pos) + +/** + * @brief Macro to configure the PLL2 SSCG Spread Mode + * @note This configuration cannot be requested when the PLL2 has been enabled. + * + * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. + * It should be a value of @ref RCC_PLL_SSCGSpread_Mode + * @retval None + */ +#define __HAL_RCC_PLL2_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ + MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) + + +/** + * @brief Macro to configure the PLL3 SSCG Spread Depth + * @note This configuration cannot be requested when the PLL3 has been enabled. + * + * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. + * It should be a value between 0 and 0x1F. + * @retval None + */ +#define __HAL_RCC_PLL3_MODSPR_CONFIG(__PLLMODSPR__) \ + MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL3CFGR3_PLL3MODSPR_Pos) + +/** + * @brief Macro to configure the PLL3 SSCG Spread Mode + * @note This configuration cannot be requested when the PLL3 has been enabled. + * + * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. + * It should be a value of @ref RCC_PLL_SSCGSpread_Mode + * @retval None + */ +#define __HAL_RCC_PLL3_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ + MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) + + +/** + * @brief Macro to configure the PLL4 SSCG Spread Depth + * @note This configuration cannot be requested when the PLL4 has been enabled. + * + * @param __PLLMODSPR__ specifies the SSCG modulation spread depth. + * It should be a value between 0 and 0x1F. + * @retval None + */ +#define __HAL_RCC_PLL4_MODSPR_CONFIG(__PLLMODSPR__) \ + MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL4CFGR3_PLL4MODSPR_Pos) + +/** + * @brief Macro to configure the PLL4 SSCG Spread Mode + * @note This configuration cannot be requested when the PLL4 has been enabled. + * + * @param __PLLMODSPRDW__ specifies the SSCG modulation spread mode. + * It should be a value of @ref RCC_PLL_SSCGSpread_Mode + * @retval None + */ +#define __HAL_RCC_PLL4_MODSPRDW_CONFIG(__PLLMODSPRDW__) \ + MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) + +/** + * @brief Macro to configure an IC Source and Divider + * + * @param __ICSEL__ specifies the IC Selection. It must be a value of @ref RCCEx_IC_Selection + * @param __ICCLKSRC__ specifies the IC clock source. It must be a value of @ref RCC_IC_Clock_Source + * @param __ICCLKDIV__ specifies the IC clock divider. It must be a a number between Min_Data = 1 and Max_Data = 256 + * @retval None + */ +#define __HAL_RCC_IC_CONFIG(__ICSEL__, __ICCLKSRC__, __ICCLKDIV__) \ + MODIFY_REG(*((&(RCC->IC1CFGR)) + (__ICSEL__)), \ + RCC_IC1CFGR_IC1SEL | RCC_IC1CFGR_IC1INT, \ + ((__ICCLKSRC__) | ((uint32_t)((__ICCLKDIV__)-1) << RCC_IC1CFGR_IC1INT_Pos))) + +/** @brief Macro to configure the ADC clock + * @param __ADC_CLKSOURCE__ specifies the ADC clock source. + * This parameter can be one of the following values: + * @arg RCC_ADCCLKSOURCE_HCLK HCLK Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP CLKP selected as ADC clock + * @arg RCC_ADCCLKSOURCE_IC7 IC7 selected as ADC clock + * @arg RCC_ADCCLKSOURCE_IC8 IC8 selected as ADC clock + * @arg RCC_ADCCLKSOURCE_MSI MSI selected as ADC clock + * @arg RCC_ADCCLKSOURCE_HSI HSI selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PIN External I2S_CKIN selected as ADC clock + * @arg RCC_ADCCLKSOURCE_TIMG TIMG selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ + LL_RCC_SetADCClockSource((__ADC_CLKSOURCE__)) + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADCCLKSOURCE_HCLK HCLK Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP CLKP selected as ADC clock + * @arg RCC_ADCCLKSOURCE_IC7 IC7 selected as ADC clock + * @arg RCC_ADCCLKSOURCE_IC8 IC8 selected as ADC clock + * @arg RCC_ADCCLKSOURCE_MSI MSI selected as ADC clock + * @arg RCC_ADCCLKSOURCE_HSI HSI selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PIN External I2S_CKIN selected as ADC clock + * @arg RCC_ADCCLKSOURCE_TIMG TIMG selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE) + +/** @brief Macro to configure the ADC clock divider. + * @param __ADC_DIVIDER__ specifies clock divider for ADC. + * This parameter can be a value between 1 and 256. + */ +#define __HAL_RCC_ADC_DIVIDER_CONFIG(__ADC_DIVIDER__) LL_RCC_SetADCPrescaler((__ADC_DIVIDER__) - 1U) + +/** @brief Macro to get the ADC clock divider. + * @retval The divider can be a value between 1 and 256. + */ +#define __HAL_RCC_GET_ADC_DIVIDER() (LL_RCC_GetADCPrescaler() + 1U) + +/** @brief Macro to configure the ADF1 clock + * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. + * This parameter can be one of the following values: + * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_CLKP CLKP selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_IC7 IC7 selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_IC8 IC8 selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_MSI MSI selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_TIMG TIMG selected as ADF1 clock + */ +#define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ + LL_RCC_SetADFClockSource((__ADF1_CLKSOURCE__)) + +/** @brief Macro to get the ADF1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_CLKP CLKP selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_IC7 IC7 selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_IC8 IC8 selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_MSI MSI selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_TIMG TIMG selected as ADF1 clock + */ +#define __HAL_RCC_GET_ADF1_SOURCE() LL_RCC_GetADFClockSource(LL_RCC_ADF1_CLKSOURCE) + +/** @brief Macro to configure the CLKP clock for peripheral + * @param __CLKP_CLKSOURCE__ specifies the clock for peripheral + * This parameter can be one of the following values: + * @arg RCC_CLKPCLKSOURCE_HSI HSI selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_MSI MSI selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_HSE HSE selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC5 IC5 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC10 IC10 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC15 IC15 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC19 IC19 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC20 IC20 selected as CLKP clock + */ +#define __HAL_RCC_CLKP_CONFIG(__CLKP_CLKSOURCE__) \ + LL_RCC_SetCLKPClockSource((__CLKP_CLKSOURCE__)) + +/** @brief Macro to get the Oscillator clock for peripheral source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLKPCLKSOURCE_HSI HSI selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_MSI MSI selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_HSE HSE selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC5 IC5 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC10 IC10 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC15 IC15 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC19 IC19 selected as CLKP clock + * @arg RCC_CLKPCLKSOURCE_IC20 IC20 selected as CLKP clock + */ +#define __HAL_RCC_GET_CLKP_SOURCE() LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE) + +/** @brief Macro to configure the DCMIPP clock source. + * + * @param __DCMIPP_CLKSOURCE__ specifies the DCMIPP clock source. + * @arg RCC_DCMIPPCLKSOURCE_PCLK5 PCLK5 selected as DCMIPP clock + * @arg RCC_DCMIPPCLKSOURCE_CLKP CLKP selected as DCMIPP clock + * @arg RCC_DCMIPPCLKSOURCE_IC17 IC17 selected as DCMIPP clock + * @arg RCC_DCMIPPCLKSOURCE_HSI HSI selected as DCMIPP clock + */ +#define __HAL_RCC_DCMIPP_CONFIG(__DCMIPP_CLKSOURCE__) \ + LL_RCC_SetDCMIPPClockSource((__DCMIPP_CLKSOURCE__)) + +/** @brief Macro to get the DCMIPP clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DCMIPPCLKSOURCE_PCLK5 PCLK5 selected as DCMIPP clock + * @arg RCC_DCMIPPCLKSOURCE_CLKP CLKP selected as DCMIPP clock + * @arg RCC_DCMIPPCLKSOURCE_IC17 IC17 elected as DCMIPP clock + * @arg RCC_DCMIPPCLKSOURCE_HSI HSI selected as DCMIPP clock + */ +#define __HAL_RCC_GET_DCMIPP_SOURCE() LL_RCC_GetDCMIPPClockSource(LL_RCC_DCMIPP_CLKSOURCE) + +/** @brief Macro to configure the ETH1 kernel clock source. + * @param __ETH1_CLKSOURCE__ specifies clock source for ETH1 + * This parameter can be one of the following values: + * @arg RCC_ETH1CLKSOURCE_HCLK HCLK selected as ETH1 clock + * @arg RCC_ETH1CLKSOURCE_CLKP CLKP selected as ETH1 clock + * @arg RCC_ETH1CLKSOURCE_IC12 IC12 selected as ETH1 clock + * @arg RCC_ETH1CLKSOURCE_HSE HSE selected as ETH1 clock + */ +#define __HAL_RCC_ETH1_CONFIG(__ETH1_CLKSOURCE__) \ + LL_RCC_SetETHClockSource(__ETH1_CLKSOURCE__) + +/** @brief Macro to get the ETH1 kernel clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETH1CLKSOURCE_HCLK HCLK selected as ETH1 clock + * @arg RCC_ETH1CLKSOURCE_CLKP CLKP selected as ETH1 clock + * @arg RCC_ETH1CLKSOURCE_IC12 IC12 selected as ETH1 clock + * @arg RCC_ETH1CLKSOURCE_HSE HSE selected as ETH1 clock + */ +#define __HAL_RCC_GET_ETH1_SOURCE() LL_RCC_GetETHClockSource(LL_RCC_ETH1_CLKSOURCE) + +/** @brief Macro to configure the ETH1 PHY interface. + * @note This configuration must be done while ETH1 is under reset, + * and before enabling the ETH1 clocks + * @param __ETH1PHY_IF__ specifies interface for ETH1 PHY + * This parameter can be one of the following values: + * @arg RCC_ETH1PHYIF_MII MII selected as ETH1 PHY interface + * @arg RCC_ETH1PHYIF_RGMII RGMII selected as ETH1 PHY interface + * @arg RCC_ETH1PHYIF_RMII RMII selected as ETH1 PHY interface + */ +#define __HAL_RCC_ETH1PHY_CONFIG(__ETH1PHY_IF__) \ + LL_RCC_SetETHPHYInterface(__ETH1PHY_IF__) + +/** @brief Macro to get the ETH PHY clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETH1PHYIF_MII MII selected as ETH1 PHY interface + * @arg RCC_ETH1PHYIF_RGMII RGMII selected as ETH1 PHY interface + * @arg RCC_ETH1PHYIF_RMII RMII selected as ETH1 PHY interface + */ +#define __HAL_RCC_GET_ETH1PHY_INTERFACE() LL_RCC_GetETHPHYInterface(LL_RCC_ETH1PHY_IF) + +/** @brief Macro to configure the ETH1 reference Rx clock source. + * @param __ETH1RX_CLKSOURCE__ specifies clock source for ETH1 reference Rx + * This parameter can be one of the following values: + * @arg RCC_ETH1RXCLKSOURCE_EXT External clock selected as ETH1 reference Rx clock + * @arg RCC_ETH1RXCLKSOURCE_INT Internal kernel selected as ETH1 reference Rx clock + */ +#define __HAL_RCC_ETH1RX_CONFIG(__ETH1RX_CLKSOURCE__) \ + LL_RCC_SetETHREFRXClockSource(__ETH1RX_CLKSOURCE__) + +/** @brief Macro to get the ETH1 reference Rx clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETH1RXCLKSOURCE_EXT External clock selected as ETH1 reference Rx clock + * @arg RCC_ETH1RXCLKSOURCE_INT Internal kernel selected as ETH1 reference Rx clock + */ +#define __HAL_RCC_GET_ETH1RX_SOURCE() LL_RCC_GetETHREFRXClockSource(LL_RCC_ETH1REFRX_CLKSOURCE) + +/** @brief Macro to configure the ETH1 reference Tx RGMII 125MHz clock source. + * @param __ETH1TX_CLKSOURCE__ specifies clock source for ETH1 reference Tx + * This parameter can be one of the following values: + * @arg RCC_ETH1TXCLKSOURCE_EXT External clock selected as ETH1 reference Tx clock + * @arg RCC_ETH1TXCLKSOURCE_INT Internal kernel selected as ETH1 reference Tx clock + */ +#define __HAL_RCC_ETH1TX_CONFIG(__ETH1TX_CLKSOURCE__) \ + LL_RCC_SetETHREFTXClockSource(__ETH1TX_CLKSOURCE__) + +/** @brief Macro to get the ETH1 reference Tx RGMII 125MHz clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETH1TXCLKSOURCE_EXT External clock selected as ETH1 reference Tx clock + * @arg RCC_ETH1TXCLKSOURCE_INT Internal kernel selected as ETH1 reference Tx clock + */ +#define __HAL_RCC_GET_ETH1TX_SOURCE() LL_RCC_GetETHREFTXClockSource(LL_RCC_ETH1REFTX_CLKSOURCE) + +/** @brief Macro to configure the ETH1 PTP clock source. + * @param __ETH1PTP_CLKSOURCE__ specifies clock source for ETH1 PTP + * This parameter can be one of the following values: + * @arg RCC_ETH1PTPCLKSOURCE_HCLK HCLK selected as ETH1 PTP clock + * @arg RCC_ETH1PTPCLKSOURCE_CLKP CLKP selected as ETH1 PTP clock + * @arg RCC_ETH1PTPCLKSOURCE_IC13 IC13 selected as ETH1 PTP clock + * @arg RCC_ETH1PTPCLKSOURCE_HSE HSE selected as ETH1 PTP clock + */ +#define __HAL_RCC_ETH1PTP_CONFIG(__ETH1PTP_CLKSOURCE__) \ + LL_RCC_SetETHPTPClockSource(__ETH1PTP_CLKSOURCE__) + +/** @brief Macro to get the ETH1 PTP clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETH1PTPCLKSOURCE_HCLK HCLK selected as ETH1 PTP clock + * @arg RCC_ETH1PTPCLKSOURCE_CLKP CLKP selected as ETH1 PTP clock + * @arg RCC_ETH1PTPCLKSOURCE_IC13 IC13 selected as ETH1 PTP clock + * @arg RCC_ETH1PTPCLKSOURCE_HSE HSE selected as ETH1 PTP clock + */ +#define __HAL_RCC_GET_ETH1PTP_SOURCE() LL_RCC_GetETHPTPClockSource(LL_RCC_ETH1PTP_CLKSOURCE) + +/** @brief Macro to configure the ETH1 PTP divider. + * @param __ETH1PTP_DIVIDER__ specifies clock divider for ETH1 PTP + * This parameter can be a value between 1 and 16. + */ +#define __HAL_RCC_ETH1PTP_DIVIDER_CONFIG(__ETH1PTP_DIVIDER__) \ + LL_RCC_SetETH1PTPDivider(((__ETH1PTP_DIVIDER__) - 1U) << RCC_CCIPR2_ETH1PTPDIV_Pos) + +/** @brief Macro to get the ETH1 PTP divider. + * @retval The divider can be a value between 1 and 16. + */ +#define __HAL_RCC_GET_ETH1PTP_DIVIDER() \ + ((LL_RCC_GetETH1PTPDivider() >> RCC_CCIPR2_ETH1PTPDIV_Pos) + 1U) + +/** @brief Macro to configure the FDCAN kernel clock source. + * @param __FDCAN_CLKSOURCE__ specifies clock source for FDCAN kernel + * This parameter can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_PCLK1 PCLK1 selected as FDCAN kernel clock (default) + * @arg RCC_FDCANCLKSOURCE_CLKP CLKP selected as FDCAN kernel clock + * @arg RCC_FDCANCLKSOURCE_IC19 IC19 selected as FDCAN kernel clock + * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock + */ +#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ + LL_RCC_SetFDCANClockSource((__FDCAN_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN kernel clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_PCLK1 PCLK1 selected as FDCAN kernel clock (default) + * @arg RCC_FDCANCLKSOURCE_CLKP CLKP selected as FDCAN kernel clock + * @arg RCC_FDCANCLKSOURCE_IC19 IC19 selected as FDCAN kernel clock + * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock + */ +#define __HAL_RCC_GET_FDCAN_SOURCE() LL_RCC_GetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE) + +/** @brief Macro to configure the FMC clock source. + * + * @param __FMC_CLKSOURCE__ specifies the FMC clock source. + * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_CLKP CLKP Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_IC3 IC3 Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_IC4 IC4 selected as FMC clock + */ +#define __HAL_RCC_FMC_CONFIG(__FMC_CLKSOURCE__) \ + LL_RCC_SetFMCClockSource((__FMC_CLKSOURCE__)) + +/** @brief Macro to get the FMC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_CLKP CLKP Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_IC3 IC3 Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_IC4 IC4 selected as FMC clock + */ +#define __HAL_RCC_GET_FMC_SOURCE() LL_RCC_GetFMCClockSource(LL_RCC_FMC_CLKSOURCE) + +/** @brief Macro to configure the I2C1 clock source. + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CLKP CKLP selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_IC10 IC10 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_IC15 IC15 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_MSI MSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + LL_RCC_SetI2CClockSource((__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CLKP CKLP selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_IC10 IC10 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_IC15 IC15 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_MSI MSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE) + +/** @brief Macro to configure the I2C2 clock source. + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CLKP CKLP selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_IC10 IC10 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_IC15 IC15 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_MSI MSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + LL_RCC_SetI2CClockSource((__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CLKP CKLP selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_IC10 IC10 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_IC15 IC15 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_MSI MSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE) + +/** @brief Macro to configure the I2C3 clock source. + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CLKP CKLP selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_IC10 IC10 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_IC15 IC15 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_MSI MSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + LL_RCC_SetI2CClockSource((__I2C3_CLKSOURCE__)) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CLKP CKLP selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_IC10 IC10 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_IC15 IC15 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_MSI MSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) + +/** @brief Macro to configure the I2C4 clock source. + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CLKP CKLP selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_IC10 IC10 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_IC15 IC15 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_MSI MSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + LL_RCC_SetI2CClockSource((__I2C4_CLKSOURCE__)) + +/** @brief Macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CLKP CKLP selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_IC10 IC10 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_IC15 IC15 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_MSI MSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C4_CLKSOURCE) + +/** @brief Macro to configure the I3C1 clock source. + * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_CLKP CKLP selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_IC10 IC10 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_IC15 IC15 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_MSI MSI selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock + */ +#define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ + LL_RCC_SetI3CClockSource((__I3C1_CLKSOURCE__)) + +/** @brief Macro to get the I3C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_CLKP CKLP selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_IC10 IC10 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_IC15 IC15 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_MSI MSI selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock + */ +#define __HAL_RCC_GET_I3C1_SOURCE() LL_RCC_GetI3CClockSource(LL_RCC_I3C1_CLKSOURCE) + +/** @brief Macro to configure the I3C2 clock source. + * @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I3C2CLKSOURCE_PCLK1 PCLK1 selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_CLKP CKLP selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_IC10 IC10 selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_IC15 IC15 selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_MSI MSI selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock + */ +#define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \ + LL_RCC_SetI3CClockSource((__I3C2_CLKSOURCE__)) + +/** @brief Macro to get the I3C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I3C2CLKSOURCE_PCLK1 PCLK1 selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_CLKP CKLP selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_IC10 IC10 selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_IC15 IC15 selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_MSI MSI selected as I3C2 clock + * @arg RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock + */ +#define __HAL_RCC_GET_I3C2_SOURCE() LL_RCC_GetI3CClockSource(LL_RCC_I3C2_CLKSOURCE) + +/** @brief Macro to configure the LPTIM1 clock source. + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_IC15 IC15 clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE LSE clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI LSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_TIMG TIMG clock selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + LL_RCC_SetLPTIMClockSource((__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_IC15 IC15 clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE LSE clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI LSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_TIMG TIMG clock selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE) + +/** @brief Macro to configure the LPTIM2 clock source. + * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP CLKP clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_IC15 IC15 clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE LSE clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI LSI clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_TIMG TIMG clock selected as LPTIM2 clock + */ +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ + LL_RCC_SetLPTIMClockSource((__LPTIM2_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP CLKP clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_IC15 IC15 clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE LSE clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI LSI clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_TIMG TIMG clock selected as LPTIM2 clock + */ +#define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE) + +/** @brief Macro to configure the LPTIM3 clock source. + * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM3CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP CLKP clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_IC15 IC15 clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE LSE clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI LSI clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_TIMG TIMG clock selected as LPTIM3 clock + */ +#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ + LL_RCC_SetLPTIMClockSource((__LPTIM3_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM3CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP CLKP clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_IC15 IC15 clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE LSE clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI LSI clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_TIMG TIMG clock selected as LPTIM3 clock + */ +#define __HAL_RCC_GET_LPTIM3_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE) + +/** @brief Macro to configure the LPTIM4 clock source. + * @param __LPTIM4_CLKSOURCE__ specifies the LPTIM4 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM4CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP CLKP clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_IC15 IC15 clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE LSE clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI LSI clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_TIMG TIMG clock selected as LPTIM4 clock + */ +#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4_CLKSOURCE__) \ + LL_RCC_SetLPTIMClockSource((__LPTIM4_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM4CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP CLKP clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_IC15 IC15 clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE LSE clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI LSI clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_TIMG TIMG clock selected as LPTIM4 clock + */ +#define __HAL_RCC_GET_LPTIM4_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM4_CLKSOURCE) + +/** @brief Macro to configure the LPTIM5 clock source. + * @param __LPTIM5_CLKSOURCE__ specifies the LPTIM5 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM5CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP CLKP clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_IC15 IC15 clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE LSE clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI LSI clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_TIMG TIMG clock selected as LPTIM5 clock + */ +#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5_CLKSOURCE__) \ + LL_RCC_SetLPTIMClockSource((__LPTIM5_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM5CLKSOURCE_PCLK4 PCLK4 clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP CLKP clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_IC15 IC15 clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE LSE clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI LSI clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_TIMG TIMG clock selected as LPTIM5 clock + */ +#define __HAL_RCC_GET_LPTIM5_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM5_CLKSOURCE) + +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_PCLK4 PCLK4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CLKP CLKP selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_IC9 IC9 selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_IC14 IC14 selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_MSI MSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + LL_RCC_SetLPUARTClockSource((__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_PCLK4 PCLK4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CLKP CLKP selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_IC9 IC9 selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_IC14 IC14 selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_MSI MSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) + +/** @brief Macro to configure the LTDC clock (LTDCCLK). + * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. + * This parameter can be one of the following values: + * @arg RCC_LTDCCLKSOURCE_PCLK5 PCLK5 Clock selected as LTDC clock + * @arg RCC_LTDCCLKSOURCE_CLKP CLKP selected as LTDC clock + * @arg RCC_LTDCCLKSOURCE_IC16 IC14 selected as LTDC clock + * @arg RCC_LTDCCLKSOURCE_HSI HSI selected as LTDC clock + */ +#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ + LL_RCC_SetLTDCClockSource((__LTDC_CLKSOURCE__)) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LTDCCLKSOURCE_PCLK5 PCLK5 Clock selected as LTDC clock + * @arg RCC_LTDCCLKSOURCE_CLKP CLKP selected as LTDC clock + * @arg RCC_LTDCCLKSOURCE_IC16 IC14 selected as LTDC clock + * @arg RCC_LTDCCLKSOURCE_HSI HSI selected as LTDC clock + */ +#define __HAL_RCC_GET_LTDC_SOURCE() LL_RCC_GetLTDCClockSource(LL_RCC_LTDC_CLKSOURCE) + +/** @brief Macro to configure the MDF1 clock + * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. + * This parameter can be one of the following values: + * @arg RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_CLKP CLKP selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_IC7 IC7 selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_IC8 IC8 selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_MSI MSI selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_HSI HSI selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PIN External I2S_CKIN selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_TIMG TIMG selected as MDF1 clock + */ +#define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \ + LL_RCC_SetMDFClockSource((__MDF1_CLKSOURCE__)) + +/** @brief Macro to get the MDF1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_CLKP CLKP selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_IC7 IC7 selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_IC8 IC8 selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_MSI MSI selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_HSI HSI selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PIN External I2S_CKIN selected as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_TIMG TIMG selected as MDF1 clock + */ +#define __HAL_RCC_GET_MDF1_SOURCE() LL_RCC_GetMDFClockSource(LL_RCC_MDF1_CLKSOURCE) + +/** + * @brief Macro to configure the PSSI clock source. + * @param __PSSI_CLKSOURCE__ defines the PSSI clock source. + * This parameter can be one of the following values: + * @arg RCC_PSSICLKSOURCE_HCLK HCLK selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock CLKP selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_IC20 IC20 selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_HSI HSI selected as PSSI clock + * @retval None + */ +#define __HAL_RCC_PSSI_CONFIG(__PSSI_CLKSOURCE__) \ + LL_RCC_SetPSSIClockSource((__PSSI_CLKSOURCE__)) + +/** @brief Macro to get the PSSI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_PSSICLKSOURCE_HCLK HCLK selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock CLKP selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_IC20 IC20 selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_HSI HSI selected as PSSI clock + */ +#define __HAL_RCC_GET_PSSI_SOURCE() LL_RCC_GetPSSIClockSource(LL_RCC_PSSI_CLKSOURCE) + +/** + * @brief Macro to configure the SAI1 clock source. + * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_IC7 IC7 selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_IC8 IC8 selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_MSI MSI selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_HSI HSI selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI1 clock + * @retval None + */ +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) \ + LL_RCC_SetSAIClockSource((__SAI1_CLKSOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_IC7 IC7 selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_IC8 IC8 selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_MSI MSI selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_HSI HSI selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI1 clock + */ +#define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE) + +/** + * @brief Macro to configure the SAI2 clock source. + * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_IC7 IC7 selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_IC8 IC8 selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_MSI MSI selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_HSI HSI selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI2 clock + * @retval None + */ +#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) \ + LL_RCC_SetSAIClockSource((__SAI2_CLKSOURCE__)) + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PCLK2 PCLK2 Clock selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock CLKP selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_IC7 IC7 selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_IC8 IC8 selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_MSI MSI selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_HSI HSI selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI2 clock + */ +#define __HAL_RCC_GET_SAI2_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI2_CLKSOURCE) + +/** @brief Macro to configure the SDMMC1 kernel clock source. + * @param __SDMMC1_CLKSOURCE__ specifies clock source for SDMMC1 + * This parameter can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_HCLK HCLK Clock selected as SDMMC1 kernel clock + * @arg RCC_SDMMC1CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC1 kernel clock + * @arg RCC_SDMMC1CLKSOURCE_IC4 IC4 selected as SDMMC1 kernel clock + * @arg RCC_SDMMC1CLKSOURCE_IC5 IC5 selected as SDMMC1 kernel clock + */ +#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ + LL_RCC_SetSDMMCClockSource((__SDMMC1_CLKSOURCE__)) + +/** @brief Macro to get the SDMMC1 kernel clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_HCLK HCLK Clock selected as SDMMC1 kernel clock + * @arg RCC_SDMMC1CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC1 kernel clock + * @arg RCC_SDMMC1CLKSOURCE_IC4 IC4 selected as SDMMC1 kernel clock + * @arg RCC_SDMMC1CLKSOURCE_IC5 IC5 selected as SDMMC1 kernel clock + */ +#define __HAL_RCC_GET_SDMMC1_SOURCE() LL_RCC_GetSDMMCClockSource(LL_RCC_SDMMC1_CLKSOURCE) + +/** @brief Macro to configure the SDMMC2 kernel clock source. + * @param __SDMMC2_CLKSOURCE__ specifies clock source for SDMMC2 + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_HCLK HCLK Clock selected as SDMMC2 kernel clock + * @arg RCC_SDMMC2CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC2 kernel clock + * @arg RCC_SDMMC2CLKSOURCE_IC4 IC4 selected as SDMMC2 kernel clock + * @arg RCC_SDMMC2CLKSOURCE_IC5 IC5 selected as SDMMC2 kernel clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + LL_RCC_SetSDMMCClockSource((__SDMMC2_CLKSOURCE__)) + +/** @brief Macro to get the SDMMC2 kernel clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_HCLK HCLK Clock selected as SDMMC2 kernel clock + * @arg RCC_SDMMC2CLKSOURCE_CLKP Peripheral clock CLKP selected as SDMMC2 kernel clock + * @arg RCC_SDMMC2CLKSOURCE_IC4 IC4 selected as SDMMC2 kernel clock + * @arg RCC_SDMMC2CLKSOURCE_IC5 IC5 selected as SDMMC2 kernel clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() LL_RCC_GetSDMMCClockSource(LL_RCC_SDMMC2_CLKSOURCE) + +/** + * @brief Macro to Configure the SPDIFRX1 clock source. + * @param __SPDIFRX_CLKSOURCE__ defines the SPDIFRX1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPDIFRX1CLKSOURCE_PCLK1 PCLK1 Clock selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_CLKP Peripheral clock CLKP selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_IC7 IC7 selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_IC8 IC8 selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_MSI MSI selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_HSI HSI selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_PIN External I2S_CKIN selected as SPDIFRX1 clock + * @retval None + */ +#define __HAL_RCC_SPDIFRX1_CONFIG(__SPDIFRX_CLKSOURCE__ ) \ + LL_RCC_SetSPDIFRXClockSource((__SPDIFRX_CLKSOURCE__)) + +/** + * @brief Macro to get the SPDIFRX1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPDIFRX1CLKSOURCE_PCLK1 PCLK1 Clock selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_CLKP Peripheral clock CLKP selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_IC7 IC7 selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_IC8 IC8 selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_MSI MSI selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_HSI HSI selected as SPDIFRX1 clock + * @arg RCC_SPDIFRX1CLKSOURCE_PIN External I2S_CKIN selected as SPDIFRX1 clock + * @retval None + */ +#define __HAL_RCC_GET_SPDIFRX1_SOURCE() LL_RCC_GetSPDIFRXClockSource(LL_RCC_SPDIFRX1_CLKSOURCE) + +/** + * @brief Macro to configure the SPI1 clock source. + * @param __SPI1_CLKSOURCE__ defines the SPI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PCLK2 PCLK2 selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_IC8 IC8 selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_IC9 IC9 selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_MSI MSI selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_HSI HSI selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock + * @retval None + */ +#define __HAL_RCC_SPI1_CONFIG(__SPI1_CLKSOURCE__ ) \ + LL_RCC_SetSPIClockSource((__SPI1_CLKSOURCE__)) + +/** @brief Macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PCLK2 PCLK2 selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_IC8 IC8 selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_IC9 IC9 selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_MSI MSI selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_HSI HSI selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock + */ +#define __HAL_RCC_GET_SPI1_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI1_CLKSOURCE) + +/** + * @brief Macro to configure the SPI2 clock source. + * @param __SPI2_CLKSOURCE__ defines the SPI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PCLK1 PCLK1 selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_IC8 IC8 selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_IC9 IC9 selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_MSI MSI selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_HSI HSI selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_PIN External I2S_CKIN selected as SPI2 clock + * @retval None + */ +#define __HAL_RCC_SPI2_CONFIG(__SPI2_CLKSOURCE__ ) \ + LL_RCC_SetSPIClockSource((__SPI2_CLKSOURCE__)) + +/** @brief Macro to get the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PCLK1 PCLK1 selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_IC8 IC8 selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_IC9 IC9 selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_MSI MSI selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_HSI HSI selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_PIN External I2S_CKIN selected as SPI2 clock + */ +#define __HAL_RCC_GET_SPI2_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI2_CLKSOURCE) + +/** + * @brief Macro to configure the SPI3 clock source. + * @param __SPI3_CLKSOURCE__ defines the SPI3 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PCLK1 PCLK1 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_IC8 IC8 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_IC9 IC9 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_MSI MSI selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_HSI HSI selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_PIN External I2S_CKIN selected as SPI3 clock + * @retval None + */ +#define __HAL_RCC_SPI3_CONFIG(__SPI3_CLKSOURCE__ ) \ + LL_RCC_SetSPIClockSource((__SPI3_CLKSOURCE__)) + +/** @brief Macro to get the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PCLK1 PCLK1 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_IC8 IC8 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_IC9 IC9 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_MSI MSI selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_HSI HSI selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_PIN External I2S_CKIN selected as SPI3 clock + */ +#define __HAL_RCC_GET_SPI3_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI3_CLKSOURCE) + +/** + * @brief Macro to configure the SPI4 clock source. + * @param __SPI4_CLKSOURCE__ defines the SPI4 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_IC8 IC8 selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_IC9 IC9 selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_MSI MSI selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_HSI HSI selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_PIN External I2S_CKIN selected as SPI4 clock + * @retval None + */ +#define __HAL_RCC_SPI4_CONFIG(__SPI4_CLKSOURCE__ ) \ + LL_RCC_SetSPIClockSource((__SPI4_CLKSOURCE__)) + +/** @brief Macro to get the SPI4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_IC8 IC8 selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_IC9 IC9 selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_MSI MSI selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_HSI HSI selected as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_PIN External I2S_CKIN selected as SPI4 clock + */ +#define __HAL_RCC_GET_SPI4_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI4_CLKSOURCE) + +/** + * @brief Macro to configure the SPI5 clock source. + * @param __SPI5_CLKSOURCE__ defines the SPI5 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_PCLK2 PCLK2 selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_IC8 IC8 selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_IC9 IC9 selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_MSI MSI selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_HSI HSI selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_PIN External I2S_CKIN selected as SPI5 clock + * @retval None + */ +#define __HAL_RCC_SPI5_CONFIG(__SPI5_CLKSOURCE__ ) \ + LL_RCC_SetSPIClockSource((__SPI5_CLKSOURCE__)) + +/** @brief Macro to get the SPI5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_PCLK2 PCLK2 selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_IC8 IC8 selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_IC9 IC9 selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_MSI MSI selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_HSI HSI selected as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_PIN External I2S_CKIN selected as SPI5 clock + */ +#define __HAL_RCC_GET_SPI5_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI5_CLKSOURCE) + +/** + * @brief Macro to configure the SPI6 clock source. + * @param __SPI6_CLKSOURCE__ defines the SPI6 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_PCLK4 PCLK4 selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_IC8 IC8 selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_IC9 IC9 selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_MSI MSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PIN External I2S_CKIN selected as SPI6 clock + * @retval None + */ +#define __HAL_RCC_SPI6_CONFIG(__SPI6_CLKSOURCE__ ) \ + LL_RCC_SetSPIClockSource((__SPI6_CLKSOURCE__)) + +/** @brief Macro to get the SPI6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_PCLK4 PCLK4 selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_CLKP Peripheral clock CKLP selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_IC8 IC8 selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_IC9 IC9 selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_MSI MSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PIN External I2S_CKIN selected as SPI6 clock + */ +#define __HAL_RCC_GET_SPI6_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI6_CLKSOURCE) + +/** @brief Macro to configure the USART1 clock source. + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CLKP Peripheral clock CKLP selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_IC9 IC9 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_IC14 IC14 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_MSI MSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CLKP Peripheral clock CKLP selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_IC9 IC9 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_IC14 IC14 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_MSI MSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE) + +/** @brief Macro to configure the USART2 clock source. + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CLKP Peripheral clock CKLP selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_IC9 IC9 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_IC14 IC14 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_MSI MSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__USART2_CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CLKP Peripheral clock CKLP selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_IC9 IC9 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_IC14 IC14 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_MSI MSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE) + +/** @brief Macro to configure the USART3 clock source. + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CLKP Peripheral clock CKLP selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_IC9 IC9 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_IC14 IC14 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_MSI MSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__USART3_CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CLKP Peripheral clock CKLP selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_IC9 IC9 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_IC14 IC14 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_MSI MSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART3_CLKSOURCE) + +/** @brief Macro to configure the UART4 clock source. + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CLKP Peripheral clock CKLP selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_IC9 IC9 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_IC14 IC14 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_MSI MSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__UART4_CLKSOURCE__)) + +/** @brief Macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CLKP Peripheral clock CKLP selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_IC9 IC9 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_IC14 IC14 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_MSI MSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART4_CLKSOURCE) + +/** @brief Macro to configure the UART5 clock source. + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CLKP Peripheral clock CKLP selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_IC9 IC9 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_IC14 IC14 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_MSI MSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__UART5_CLKSOURCE__)) + +/** @brief Macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CLKP Peripheral clock CKLP selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_IC9 IC9 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_IC14 IC14 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_MSI MSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART5_CLKSOURCE) + +/** @brief Macro to configure the USART6 clock source. + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK2 PCLK2 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CLKP Peripheral clock CKLP selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_IC9 IC9 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_IC14 IC14 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_MSI MSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__USART6_CLKSOURCE__)) + +/** @brief Macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK2 PCLK2 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CLKP Peripheral clock CKLP selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_IC9 IC9 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_IC14 IC14 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_MSI MSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART6_CLKSOURCE) + +/** @brief Macro to configure the UART7 clock source. + * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CLKP Peripheral clock CKLP selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_IC9 IC9 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_IC14 IC14 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_MSI MSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock + */ +#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__UART7_CLKSOURCE__)) + +/** @brief Macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CLKP Peripheral clock CKLP selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_IC9 IC9 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_IC14 IC14 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_MSI MSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART7_CLKSOURCE) + +/** @brief Macro to configure the UART8 clock source. + * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CLKP Peripheral clock CKLP selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_IC9 IC9 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_IC14 IC14 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_MSI MSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock + */ +#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__UART8_CLKSOURCE__)) + +/** @brief Macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CLKP Peripheral clock CKLP selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_IC9 IC9 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_IC14 IC14 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_MSI MSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART8_CLKSOURCE) + +/** @brief Macro to configure the UART9 clock source. + * @param __UART9_CLKSOURCE__ specifies the UART9 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART9CLKSOURCE_PCLK2 PCLK2 selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CLKP Peripheral clock CKLP selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_IC9 IC9 selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_IC14 IC14 selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_MSI MSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock + */ +#define __HAL_RCC_UART9_CONFIG(__UART9_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__UART9_CLKSOURCE__)) + +/** @brief Macro to get the UART9 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART9CLKSOURCE_PCLK2 PCLK2 selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CLKP Peripheral clock CKLP selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_IC9 IC9 selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_IC14 IC14 selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_MSI MSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock + */ +#define __HAL_RCC_GET_UART9_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART9_CLKSOURCE) + +/** @brief Macro to configure the USART10 clock source. + * @param __USART10_CLKSOURCE__ specifies the USART10 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART10CLKSOURCE_PCLK2 PCLK2 selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CLKP Peripheral clock CKLP selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_IC9 IC9 selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_IC14 IC14 selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_MSI MSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock + */ +#define __HAL_RCC_USART10_CONFIG(__USART10_CLKSOURCE__) \ + LL_RCC_SetUSARTClockSource((__USART10_CLKSOURCE__)) + +/** @brief Macro to get the USART10 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART10CLKSOURCE_PCLK2 PCLK2 selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CLKP Peripheral clock CKLP selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_IC9 IC9 selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_IC14 IC14 selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_MSI MSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock + */ +#define __HAL_RCC_GET_USART10_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART10_CLKSOURCE) + +/** @brief Macro to configure the XSPI1 clock source. + * + * @param __XSPI1_CLKSOURCE__ specifies the XSPI1 clock source. + * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_IC3 IC3 selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_IC4 IC4 selected as XSPI1 clock + */ +#define __HAL_RCC_XSPI1_CONFIG(__XSPI1_CLKSOURCE__) \ + LL_RCC_SetXSPIClockSource((__XSPI1_CLKSOURCE__)) + +/** @brief Macro to get the XSPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_IC3 IC3 selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_IC4 IC4 selected as XSPI1 clock + */ +#define __HAL_RCC_GET_XSPI1_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI1_CLKSOURCE) + +/** @brief Macro to configure the XSPI2 clock source. + * + * @param __XSPI2_CLKSOURCE__ specifies the XSPI2 clock source. + * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_IC3 IC3 selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_IC4 IC4 selected as XSPI2 clock + */ +#define __HAL_RCC_XSPI2_CONFIG(__XSPI2_CLKSOURCE__) \ + LL_RCC_SetXSPIClockSource((__XSPI2_CLKSOURCE__)) + +/** @brief Macro to get the XSPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_IC3 IC3 selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_IC4 IC4 selected as XSPI2 clock + */ +#define __HAL_RCC_GET_XSPI2_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI2_CLKSOURCE) + +/** @brief Macro to configure the XSPI3 clock source. + * + * @param __XSPI3_CLKSOURCE__ specifies the XSPI3 clock source. + * @arg RCC_XSPI3CLKSOURCE_HCLK HCLK selected as XSPI3 clock + * @arg RCC_XSPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI3 clock + * @arg RCC_XSPI3CLKSOURCE_IC3 IC3 selected as XSPI3 clock + * @arg RCC_XSPI3CLKSOURCE_IC4 IC4 selected as XSPI3 clock + */ +#define __HAL_RCC_XSPI3_CONFIG(__XSPI3_CLKSOURCE__) \ + LL_RCC_SetXSPIClockSource((__XSPI3_CLKSOURCE__)) + +/** @brief Macro to get the XSPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_XSPI3CLKSOURCE_HCLK HCLK selected as XSPI3 clock + * @arg RCC_XSPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI3 clock + * @arg RCC_XSPI3CLKSOURCE_IC3 IC3 selected as XSPI3 clock + * @arg RCC_XSPI3CLKSOURCE_IC4 IC4 selected as XSPI3 clock + */ +#define __HAL_RCC_GET_XSPI3_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI3_CLKSOURCE) + +/** @brief Macro to configure the Timers clocks prescaler + * @param __PRESC__ specifies the Timers clocks prescaler selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DIV1 The Timers kernels clocks prescaler is 1 + * @arg RCC_TIMPRES_DIV2 The Timers kernels clocks prescaler is 2 + * @arg RCC_TIMPRES_DIV4 The Timers kernels clocks prescaler is 4 + * @arg RCC_TIMPRES_DIV8 The Timers kernels clocks prescaler is 8 + * @note The clock ratio tim_ker_ck/tim_pclk must be an integer between 1 and 16 + */ +#define __HAL_RCC_TIMCLKPRESCALER_CONFIG(__PRESC__) LL_RCC_SetTIMPrescaler((__PRESC__)) + +/** @brief Macro to get the Timers clocks prescaler. + * @retval Timers clocks prescaler can be one of the following values: + * @arg RCC_TIMPRES_DIV1 The Timers kernels clocks prescaler is 1 + * @arg RCC_TIMPRES_DIV2 The Timers kernels clocks prescaler is 2 + * @arg RCC_TIMPRES_DIV4 The Timers kernels clocks prescaler is 4 + * @arg RCC_TIMPRES_DIV8 The Timers kernels clocks prescaler is 8 + */ +#define __HAL_RCC_GET_TIMCLKPRESCALER() LL_RCC_GetTIMPrescaler() + +/** @brief Macro to configure the USBPHY1 clock. + * @param __USBPHY1_CLKSOURCE__ specifies the USBPHY1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USBPHY1CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_CLKP Peripheral clock CKLP selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_IC15 IC15 selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY1 clock + */ +#define __HAL_RCC_USBPHY1_CONFIG(__USBPHY1_CLKSOURCE__) \ + do \ + { \ + LL_RCC_SetOTGPHYClockSource((__USBPHY1_CLKSOURCE__) & 0x7FFFFFFFUL); \ + if(((__USBPHY1_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ + else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ + } while (0) + + +/** @brief Macro to get the USBPHY1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBPHY1CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_CLKP Peripheral clock CKLP selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_IC15 IC15 selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY1 clock + * @arg RCC_USBPHY1CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY1 clock + */ +#define __HAL_RCC_GET_USBPHY1_SOURCE() \ + (LL_RCC_GetOTGPHYClockSource(LL_RCC_OTGPHY1_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) + +/** @brief Macro to configure the USBPHY2 clock. + * @param __USBPHY2_CLKSOURCE__ specifies the USBPHY2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USBPHY2CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_CLKP Peripheral clock CKLP selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_IC15 IC15 selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY2 clock + */ +#define __HAL_RCC_USBPHY2_CONFIG(__USBPHY2_CLKSOURCE__) \ + do \ + { \ + LL_RCC_SetOTGPHYClockSource((__USBPHY2_CLKSOURCE__) & 0x7FFFFFFFUL); \ + if(((__USBPHY2_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ + else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ + } while (0) + +/** @brief Macro to get the USBPHY2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBPHY2CLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_CLKP Peripheral clock CKLP selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_IC15 IC15 selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBPHY2 clock + * @arg RCC_USBPHY2CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY2 clock + */ +#define __HAL_RCC_GET_USBPHY2_SOURCE() \ + (LL_RCC_GetOTGPHYClockSource(LL_RCC_OTGPHY2_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) + +/** @brief Macro to configure the USB OTGHS1 clock. + * @param __USBOTGHS1_CLKSOURCE__ specifies the USB OTGHS1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USBOTGHS1CLKSOURCE_OTGPHY1 OTGPHY1 selected as USBOTGHS1 clock + * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBOTGHS1 clock + * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBOTGHS1 clock + */ +#define __HAL_RCC_USBOTGHS1_CONFIG(__USBOTGHS1_CLKSOURCE__) \ + do \ + { \ + LL_RCC_SetOTGPHYCKREFClockSource((__USBOTGHS1_CLKSOURCE__) & 0x7FFFFFFFUL); \ + if(((__USBOTGHS1_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ + else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ + } while (0) + +/** @brief Macro to get the USB OTGHS1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBOTGHS1CLKSOURCE_OTGPHY1 OTGPHY1 selected as USBOTGHS1 clock + * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBOTGHS1 clock + * @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBOTGHS1 clock + */ +#define __HAL_RCC_GET_USBOTGHS1_SOURCE() \ + (LL_RCC_GetOTGPHYCKREFClockSource(LL_RCC_OTGPHY1CKREF_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) + +/** @brief Macro to configure the USB OTGHS2 clock. + * @param __USBOTGHS2_CLKSOURCE__ specifies the USB OTGHS2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USBOTGHS2CLKSOURCE_OTGPHY2 OTGPHY2 selected as USBOTGHS2 clock + * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBOTGHS2 clock + * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBOTGHS2 clock + */ +#define __HAL_RCC_USBOTGHS2_CONFIG(__USBOTGHS2_CLKSOURCE__) \ + do \ + { \ + LL_RCC_SetOTGPHYCKREFClockSource((__USBOTGHS2_CLKSOURCE__) & 0x7FFFFFFFUL); \ + if(((__USBOTGHS2_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \ + else {LL_RCC_HSE_SelectHSEAsDiv2Clock();} \ + } while (0) + +/** @brief Macro to get the USB OTGHS2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBOTGHS2CLKSOURCE_OTGPHY2 OTGPHY2 selected as USBOTGHS2 clock + * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT HSE from oscillator selected as USBOTGHS2 clock + * @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBOTGHS2 clock + */ +#define __HAL_RCC_GET_USBOTGHS2_SOURCE() \ + (LL_RCC_GetOTGPHYCKREFClockSource(LL_RCC_OTGPHY2CKREF_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U)) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, RCC_EXTI_LINE_LSECSS) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +uint32_t HAL_RCCEx_GetPLL1CLKFreq(void); +uint32_t HAL_RCCEx_GetPLL2CLKFreq(void); +uint32_t HAL_RCCEx_GetPLL3CLKFreq(void); +uint32_t HAL_RCCEx_GetPLL4CLKFreq(void); +uint32_t HAL_RCCEx_GetTIMGFreq(void); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_DisableLSECSS_IT(void); +void HAL_RCCEx_ReArmLSECSS(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +HAL_StatusTypeDef HAL_RCCEx_PLLSSCGConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit, + const RCC_PLLSSCGInitTypeDef *pPLLSSCGInit); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +/** @defgroup RCCEx_IS_RCC_Definitions Private macros to check input parameters + * @{ + */ +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_XSPI3) == RCC_PERIPHCLK_XSPI3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CSI) == RCC_PERIPHCLK_CSI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DCMIPP) == RCC_PERIPHCLK_DCMIPP) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ETH1) == RCC_PERIPHCLK_ETH1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ETH1RX) == RCC_PERIPHCLK_ETH1RX) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ETH1TX) == RCC_PERIPHCLK_ETH1TX) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ETH1PTP) == RCC_PERIPHCLK_ETH1PTP) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPDIFRX1) == RCC_PERIPHCLK_SPDIFRX1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USBPHY1) == RCC_PERIPHCLK_USBPHY1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USBPHY2) == RCC_PERIPHCLK_USBPHY2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USBOTGHS1) == RCC_PERIPHCLK_USBOTGHS1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USBOTGHS2) == RCC_PERIPHCLK_USBOTGHS2)) + +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_IC7) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_TIMG)) + +#define IS_RCC_ADCDIVIDER(__VALUE__) \ + ((1U <= (__VALUE__)) && ((__VALUE__) <= 256U)) + +#define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_IC7) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_TIMG)) + +#define IS_RCC_CKPERCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_CLKPCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_CLKPCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_CLKPCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC19) || \ + ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC5) || \ + ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC10) || \ + ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC20)) + +#define IS_RCC_DCMIPPCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DCMIPPCLKSOURCE_PCLK5) || \ + ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_IC17) || \ + ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_HSI)) + +#define IS_RCC_ETH1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETH1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ETH1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_ETH1CLKSOURCE_IC12) || \ + ((__SOURCE__) == RCC_ETH1CLKSOURCE_HSE)) + +#define IS_RCC_ETH1PHYIF(__SOURCE__) \ + (((__SOURCE__) == RCC_ETH1PHYIF_MII) || \ + ((__SOURCE__) == RCC_ETH1PHYIF_RGMII) || \ + ((__SOURCE__) == RCC_ETH1PHYIF_RMII)) + +#define IS_RCC_ETH1RXCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETH1RXCLKSOURCE_EXT) || \ + ((__SOURCE__) == RCC_ETH1RXCLKSOURCE_INT)) + +#define IS_RCC_ETH1TXCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETH1TXCLKSOURCE_EXT) || \ + ((__SOURCE__) == RCC_ETH1TXCLKSOURCE_INT)) + +#define IS_RCC_ETH1PTPCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_IC13) || \ + ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_HSE)) + +#define IS_RCC_ETH1PTPDIVIDER(__VALUE__) \ + ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) + +#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_IC19) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)) + +#define IS_RCC_FMCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FMCCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_IC3) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_IC4)) + +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_IC10) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) + +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_IC10) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) + +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_IC10) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) + +#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_IC10) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) + +#define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_IC10) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) + +#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_IC10) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) + +#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_TIMG)) + +#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_TIMG)) + +#define IS_RCC_LPTIM3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_TIMG)) + +#define IS_RCC_LPTIM4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_TIMG)) + +#define IS_RCC_LPTIM5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_TIMG)) + +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) + +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LTDCCLKSOURCE_PCLK5) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_IC16) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_HSI)) + +#define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_IC7) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_TIMG)) + +#define IS_RCC_PSSICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_PSSICLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_PSSICLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_PSSICLKSOURCE_IC20) || \ + ((__SOURCE__) == RCC_PSSICLKSOURCE_HSI)) + +#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_IC7) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_SPDIFRX1)) + +#define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_IC7) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIFRX1)) + +#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_IC4) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_IC5)) + +#define IS_RCC_SDMMC2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC2CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_IC4) || \ + ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_IC5)) + +#define IS_RCC_SPDIFRX1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_IC7) || \ + ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_PIN)) + +#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) + +#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) + +#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) + +#define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) + +#define IS_RCC_SPI5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI5CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) + +#define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_IC8) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) + +#define IS_RCC_TIMPRES(__VALUE__) \ + (((__VALUE__) == RCC_TIMPRES_DIV1) || \ + ((__VALUE__) == RCC_TIMPRES_DIV2) || \ + ((__VALUE__) == RCC_TIMPRES_DIV4) || \ + ((__VALUE__) == RCC_TIMPRES_DIV8)) + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) + +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) + +#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) + +#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) + +#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI)) + +#define IS_RCC_UART7CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI)) + +#define IS_RCC_UART8CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI)) + +#define IS_RCC_UART9CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART9CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_HSI)) + +#define IS_RCC_USART10CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART10CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_IC9) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_IC14) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_HSI)) + +#define IS_RCC_USBPHY1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBPHY1CLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_USBPHY1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_USBPHY1CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_USBPHY1CLKSOURCE_HSE_DIRECT) || \ + ((__SOURCE__) == RCC_USBPHY1CLKSOURCE_HSE_DIRECT_DIV2)) + +#define IS_RCC_USBPHY2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBPHY2CLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_USBPHY2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_USBPHY2CLKSOURCE_IC15) || \ + ((__SOURCE__) == RCC_USBPHY2CLKSOURCE_HSE_DIRECT) || \ + ((__SOURCE__) == RCC_USBPHY2CLKSOURCE_HSE_DIRECT_DIV2)) + +#define IS_RCC_USBOTGHS1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_OTGPHY1) || \ + ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT) || \ + ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2)) + +#define IS_RCC_USBOTGHS2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_OTGPHY2) || \ + ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT) || \ + ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2)) + +#define IS_RCC_XSPI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_XSPI1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_XSPI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_XSPI1CLKSOURCE_IC3) || \ + ((__SOURCE__) == RCC_XSPI1CLKSOURCE_IC4)) + +#define IS_RCC_XSPI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_XSPI2CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_XSPI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_XSPI2CLKSOURCE_IC3) || \ + ((__SOURCE__) == RCC_XSPI2CLKSOURCE_IC4)) + +#define IS_RCC_XSPI3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_XSPI3CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_XSPI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_XSPI3CLKSOURCE_IC3) || \ + ((__SOURCE__) == RCC_XSPI3CLKSOURCE_IC4)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_RCC_EX_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_xspi.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_xspi.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_xspi.h (revision 16) @@ -0,0 +1,1321 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_xspi.h + * @author MCD Application Team + * @brief Header file of XSPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_XSPI_H +#define STM32N6xx_HAL_XSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal_def.h" + +#if defined(XSPI) || defined(XSPI1) || defined(XSPI2) || defined(XSPI3) + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup XSPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Types XSPI Exported Types + * @{ + */ + +/** + * @brief XSPI Init structure definition + */ +typedef struct +{ + uint32_t FifoThresholdByte; /*!< This is the threshold used by the Peripheral to generate the interrupt + indicating that data are available in reception or free place + is available in transmission. + For XSPI, this parameter can be a value between 1 and 64 */ + uint32_t MemoryMode; /*!< It Specifies the memory mode. + This parameter can be a value of @ref XSPI_MemoryMode */ + uint32_t MemoryType; /*!< It indicates the external device type connected to the XSPI. + This parameter can be a value of @ref XSPI_MemoryType */ + uint32_t MemorySize; /*!< It defines the size of the external device connected to the XSPI, + it corresponds to the number of address bits required to access + the external device. + This parameter can be a value of @ref XSPI_MemorySize*/ + uint32_t ChipSelectHighTimeCycle; /*!< It defines the minimum number of clocks which the chip select + must remain high between commands. + This parameter can be a value between 1 and 64U */ + uint32_t FreeRunningClock; /*!< It enables or not the free running clock. + This parameter can be a value of @ref XSPI_FreeRunningClock */ + uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. + This parameter can be a value of @ref XSPI_ClockMode */ + uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. + This parameter can be a value of @ref XSPI_WrapSize */ + uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating + the external clock based on the AHB clock. + This parameter can be a value between 0 and 255U */ + uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order + to take in account external signal delays. + This parameter can be a value of @ref XSPI_SampleShifting */ + uint32_t DelayHoldQuarterCycle; /*!< This parameter is deprecated and is not used on STM32N6xx devices */ + uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select. + This parameter can be a value of @ref XSPI_ChipSelectBoundary */ + uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is + released every MaxTran+1 bytes when the other XSPI request the access + to the bus. + This parameter can be a value between 0 and 255U */ + uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every + Refresh+1 clock cycles. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t MemorySelect; /*!< It indicates if the output of nCS. + This parameter can be a value of @ref XSPI_MemorySelect */ + uint32_t MemoryExtended; /*!< If available, It indicates if NCS1 and NCS2 are software or hardware controlled when one + XSPI drives two same size external memories located in contiguous places + in the memory map. + This parameter can be a value of @ref XSPI_MemoryExtended */ +} XSPI_InitTypeDef; + +/** + * @brief HAL XSPI Handle Structure definition + */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +typedef struct __XSPI_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +{ + XSPI_TypeDef *Instance; /*!< XSPI registers base address */ + XSPI_InitTypeDef Init; /*!< XSPI initialization parameters */ + uint8_t *pBuffPtr; /*!< Address of the XSPI buffer for transfer */ + __IO uint32_t XferSize; /*!< Number of data to transfer */ + __IO uint32_t XferCount; /*!< Counter of data transferred */ +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< Handle of the DMA channel used for transmit */ + DMA_HandleTypeDef *hdmarx; /*!< Handle of the DMA channel used for receive */ +#endif /* HAL_DMA_MODULE_ENABLED */ + __IO uint32_t State; /*!< Internal state of the XSPI HAL driver */ + __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ + uint32_t Timeout; /*!< Timeout used for the XSPI external device access */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi); + + void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +} XSPI_HandleTypeDef; + +/** + * @brief HAL XSPI Regular Command Structure definition + */ +typedef struct +{ + uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or + to the registers for the write operation (these registers are only + used for memory-mapped mode). + This parameter can be a value of @ref XSPI_OperationType */ + uint32_t IOSelect; /*!< It indicates the IOs used to exchange data with external memory. + This parameter can be a value of @ref XSPI_IOSelect */ + uint32_t Instruction; /*!< It contains the instruction to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFFU */ + uint32_t InstructionMode; /*!< It indicates the mode of the instruction. + This parameter can be a value of @ref XSPI_InstructionMode */ + uint32_t InstructionWidth; /*!< It indicates the width of the instruction. + This parameter can be a value of @ref XSPI_InstructionWidth */ + uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase. + This parameter can be a value of @ref XSPI_InstructionDTRMode */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFFU */ + uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises number of lines + for address (except no address). + This parameter can be a value of @ref XSPI_AddressMode */ + uint32_t AddressWidth; /*!< It indicates the width of the address. + This parameter can be a value of @ref XSPI_AddressWidth */ + uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase. + This parameter can be a value of @ref XSPI_AddressDTRMode */ + uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFFU */ + uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. + This parameter can be a value of @ref XSPI_AlternateBytesMode */ + uint32_t AlternateBytesWidth; /*!< It indicates the width of the alternate bytes. + This parameter can be a value of @ref XSPI_AlternateBytesWidth */ + uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes phase. + This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */ + uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines + for data exchange (except no data). + This parameter can be a value of @ref XSPI_DataMode */ + uint32_t DataLength; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFFU */ + uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase. + This parameter can be a value of @ref XSPI_DataDTRMode */ + uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. + This parameter can be a value between 0 and 31U */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref XSPI_DQSMode */ +} XSPI_RegularCmdTypeDef; + +/** + * @brief HAL XSPI Hyperbus Configuration Structure definition + */ +typedef struct +{ + uint32_t RWRecoveryTimeCycle; /*!< It indicates the number of cycles for the device read write recovery time. + This parameter can be a value between 0 and 255U */ + uint32_t AccessTimeCycle; /*!< It indicates the number of cycles for the device access time. + This parameter can be a value between 0 and 255U */ + uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. + This parameter can be a value of @ref XSPI_WriteZeroLatency */ + uint32_t LatencyMode; /*!< It configures the latency mode. + This parameter can be a value of @ref XSPI_LatencyMode */ +} XSPI_HyperbusCfgTypeDef; + +/** + * @brief HAL XSPI Hyperbus Command Structure definition + */ +typedef struct +{ + uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. + This parameter can be a value of @ref XSPI_AddressSpace */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFFU */ + uint32_t AddressWidth; /*!< It indicates the width of the address. + This parameter can be a value of @ref XSPI_AddressWidth */ + uint32_t DataLength; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF + In case of autopolling mode, this parameter can be + any value between 1 and 4 */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref XSPI_DQSMode */ + uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines + for data exchange (except no data). + This parameter can be a value of @ref XSPI_DataMode */ +} XSPI_HyperbusCmdTypeDef; + +/** + * @brief HAL XSPI Auto Polling mode configuration structure definition + */ +typedef struct +{ + uint32_t MatchValue; /*!< Specifies the value to be compared with the masked status register to get + a match. + This parameter can be any value between 0 and 0xFFFFFFFFU */ + uint32_t MatchMask; /*!< Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFFU */ + uint32_t MatchMode; /*!< Specifies the method used for determining a match. + This parameter can be a value of @ref XSPI_MatchMode */ + uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref XSPI_AutomaticStop */ + uint32_t IntervalTime; /*!< Specifies the number of clock cycles between two read during automatic + polling phases. + This parameter can be any value between 0 and 0xFFFFU */ +} XSPI_AutoPollingTypeDef; + +/** + * @brief HAL XSPI Memory Mapped mode configuration structure definition + */ +typedef struct +{ + uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref XSPI_TimeOutActivation */ + uint32_t TimeoutPeriodClock; /*!< Specifies the number of clock to wait when the FIFO is full before to + release the chip select. + This parameter can be any value between 0 and 0xFFFFU */ + uint32_t NoPrefetchData; /*!< Specifies if the automatic prefetch in the external memory is enabled or not. + This parameter can be a value of @ref XSPI_NoPrefetchData */ + uint32_t NoPrefetchAXI; /*!< Specifies if the automatic prefetch in the external memory when the corresponding AXI + transaction is signaled as not-prefetchable, is enabled or not. + This parameter can be a value of @ref XSPI_NoPrefetchAXI */ +} XSPI_MemoryMappedTypeDef; + +/** + * @brief HAL XSPI IO Manager Configuration structure definition + */ +typedef struct +{ + uint32_t nCSOverride; /*!< It indicates Chip select selector override setting for XSPI. + This parameter can be a value @ref XSPIM_MemorySelect_Override */ + uint32_t IOPort; /*!< It indicates which port of the XSPI IO Manager is used for the instance. + This parameter can be a value of @ref XSPI_IO_Manger_IOPort */ + uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) + expected if some signals are multiplexed in the XSPI IO Manager with the + other XSPI. + This parameter can be a value between 1 and 256 */ +} XSPIM_CfgTypeDef; + +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL XSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_XSPI_ERROR_CB_ID = 0x00U, /*!< XSPI Error Callback ID */ + HAL_XSPI_ABORT_CB_ID = 0x01U, /*!< XSPI Abort Callback ID */ + HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< XSPI FIFO Threshold Callback ID */ + HAL_XSPI_CMD_CPLT_CB_ID = 0x03U, /*!< XSPI Command Complete Callback ID */ + HAL_XSPI_RX_CPLT_CB_ID = 0x04U, /*!< XSPI Rx Complete Callback ID */ + HAL_XSPI_TX_CPLT_CB_ID = 0x05U, /*!< XSPI Tx Complete Callback ID */ + HAL_XSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< XSPI Rx Half Complete Callback ID */ + HAL_XSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< XSPI Tx Half Complete Callback ID */ + HAL_XSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< XSPI Status Match Callback ID */ + HAL_XSPI_TIMEOUT_CB_ID = 0x09U, /*!< XSPI Timeout Callback ID */ + HAL_XSPI_MSP_INIT_CB_ID = 0x0AU, /*!< XSPI MspInit Callback ID */ + HAL_XSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< XSPI MspDeInit Callback ID */ +} HAL_XSPI_CallbackIDTypeDef; + +/** + * @brief HAL XSPI Callback pointer definition + */ +typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); + +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +/** + * @brief HAL XSPI High-speed interface calibration structure definition + */ +typedef struct +{ + uint32_t DelayValueType; /*!< It indicates which calibration is concerned by the configuration. + This parameter can be a value of @ref XSPI_DelayType */ + uint32_t FineCalibrationUnit; /*!< It indicates the fine calibration value of the delay. + This parameter can be a value between 0 and 0x7FU */ + uint32_t CoarseCalibrationUnit; /*!< It indicates the coarse calibration value of the delay. + This parameter can be a value between 0 and 0x1FU */ + uint32_t MaxCalibration; /*!< It indicates that the calibration is outside the range of DLL master. + It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY. + This parameter can be a value of @ref XSPI_MaxCal */ +} XSPI_HSCalTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Constants XSPI Exported Constants + * @{ + */ + +/** @defgroup XSPI_State XSPI State + * @{ + */ +#define HAL_XSPI_STATE_RESET (0x00000000U) /*!< Initial state */ +#define HAL_XSPI_STATE_READY (0x00000002U) /*!< Driver ready to be used */ +#define HAL_XSPI_STATE_HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ +#define HAL_XSPI_STATE_CMD_CFG (0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ +#define HAL_XSPI_STATE_READ_CMD_CFG (0x00000014U) /*!< Read command configuration done, not the write command configuration */ +#define HAL_XSPI_STATE_WRITE_CMD_CFG (0x00000024U) /*!< Write command configuration done, not the read command configuration */ +#define HAL_XSPI_STATE_BUSY_CMD (0x00000008U) /*!< Command without data on-going */ +#define HAL_XSPI_STATE_BUSY_TX (0x00000018U) /*!< Indirect Tx on-going */ +#define HAL_XSPI_STATE_BUSY_RX (0x00000028U) /*!< Indirect Rx on-going */ +#define HAL_XSPI_STATE_BUSY_AUTO_POLLING (0x00000048U) /*!< Auto-polling on-going */ +#define HAL_XSPI_STATE_BUSY_MEM_MAPPED (0x00000088U) /*!< Memory-mapped on-going */ +#define HAL_XSPI_STATE_ABORT (0x00000100U) /*!< Abort on-going */ +#define HAL_XSPI_STATE_ERROR (0x00000200U) /*!< Blocking error, driver should be re-initialized */ +/** + * @} + */ + +/** @defgroup XSPI_ErrorCode XSPI Error Code + * @{ + */ +#define HAL_XSPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_XSPI_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#define HAL_XSPI_ERROR_TRANSFER (0x00000002U) /*!< Transfer error */ +#define HAL_XSPI_ERROR_DMA (0x00000004U) /*!< DMA transfer error */ +#define HAL_XSPI_ERROR_INVALID_PARAM (0x00000008U) /*!< Invalid parameters error */ +#define HAL_XSPI_ERROR_INVALID_SEQUENCE (0x00000010U) /*!< Sequence is incorrect */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +#define HAL_XSPI_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid callback error */ +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +/** + * @} + */ + +/** @defgroup XSPI_MemoryMode XSPI Memory Mode + * @{ + */ +#define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */ +#define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */ + +/** + * @} + */ + +/** @defgroup XSPI_MemoryType XSPI Memory Type + * @{ + */ +#define HAL_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */ +#define HAL_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */ +#define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */ +#define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/ +#define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ +#define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */ + +/** + * @} + */ + +/** @defgroup XSPI_MemorySize XSPI Memory Size + * @{ + */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ +/** + * @} + */ + +/** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock + * @{ + */ +#define HAL_XSPI_FREERUNCLK_DISABLE (0x00000000U) /*!< CLK is not free running */ +#define HAL_XSPI_FREERUNCLK_ENABLE ((uint32_t)XSPI_DCR1_FRCK) /*!< CLK is always provided (running) */ +/** + * @} + */ + +/** @defgroup XSPI_ClockMode XSPI Clock Mode + * @{ + */ +#define HAL_XSPI_CLOCK_MODE_0 (0x00000000U) /*!< CLK must stay low while nCS is high */ +#define HAL_XSPI_CLOCK_MODE_3 ((uint32_t)XSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ +/** + * @} + */ + +/** @defgroup XSPI_WrapSize XSPI Wrap-Size + * @{ + */ +#define HAL_XSPI_WRAP_NOT_SUPPORTED (0x00000000U) /*!< wrapped reads are not supported by the memory */ +#define HAL_XSPI_WRAP_16_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ +#define HAL_XSPI_WRAP_32_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ +#define HAL_XSPI_WRAP_64_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ +#define HAL_XSPI_WRAP_128_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ +/** + * @} + */ + +/** @defgroup XSPI_SampleShifting XSPI Sample Shifting + * @{ + */ +#define HAL_XSPI_SAMPLE_SHIFT_NONE (0x00000000U) /*!< No shift */ +#define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE ((uint32_t)XSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ +/** + * @} + */ + +/** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle + * @note These constants are deprecated and are not expected to be used anymore. + * @{ + */ +#define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */ +#define HAL_XSPI_DHQC_ENABLE ((uint32_t)XSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ +/** + * @} + */ + +/** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary + * @{ + */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Bytes = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Bytes = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Bytes = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Bytes = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Bytes = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Bytes = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Bytes = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Bytes = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Bytes = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KBytes = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KBytes = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KBytes = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MBytes = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MBytes = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MBytes = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ +/** + * @} + */ + +/** @defgroup XSPI_MemorySelect XSPI Memory Select + * @{ + */ +#define HAL_XSPI_CSSEL_NCS1 (0x00000000U) /*!< The output of nCS is nCS1 */ +#define HAL_XSPI_CSSEL_NCS2 ((uint32_t)XSPI_CR_CSSEL) /*!< The output of nCS is nCS2 */ +/** + * @} + */ + +/** @defgroup XSPI_MemoryExtended XSPI Memory Extended + * @{ + */ +#define HAL_XSPI_CSSEL_SW (0x00000000U) /*!< NCS1 and NCS2 are software controlled. */ +#define HAL_XSPI_CSSEL_HW ((uint32_t)XSPI_DCR1_EXTENDMEM) /*!< NCS1 and NCS2 are hardware controlled. */ +/** + * @} + */ + +/** @defgroup XSPI_OperationType XSPI Operation Type + * @{ + */ +#define HAL_XSPI_OPTYPE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ +#define HAL_XSPI_OPTYPE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */ +#define HAL_XSPI_OPTYPE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */ +#define HAL_XSPI_OPTYPE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ + +/** + * @} + */ + +/** @defgroup XSPI_IOSelect XSPI IO Select + * @{ + */ +#define HAL_XSPI_SELECT_IO_3_0 (0x00000000U) /*!< Data exchanged over IO[3:0] */ +#define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)XSPI_CR_MSEL_0) /*!< Data exchanged over IO[7:4] */ +#define HAL_XSPI_SELECT_IO_11_8 ((uint32_t)XSPI_CR_MSEL_1) /*!< Data exchanged over IO[11:8] */ +#define HAL_XSPI_SELECT_IO_15_12 ((uint32_t)XSPI_CR_MSEL ) /*!< Data exchanged over IO[15:12] */ +#define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ +#define HAL_XSPI_SELECT_IO_15_8 ((uint32_t)XSPI_CR_MSEL_1) /*!< Data exchanged over IO[15:8] */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionMode XSPI Instruction Mode + * @{ + */ +#define HAL_XSPI_INSTRUCTION_NONE (0x00000000U) /*!< No instruction */ +#define HAL_XSPI_INSTRUCTION_1_LINE ((uint32_t)XSPI_CCR_IMODE_0) /*!< Instruction on a single line */ +#define HAL_XSPI_INSTRUCTION_2_LINES ((uint32_t)XSPI_CCR_IMODE_1) /*!< Instruction on two lines */ +#define HAL_XSPI_INSTRUCTION_4_LINES ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ +#define HAL_XSPI_INSTRUCTION_8_LINES ((uint32_t)XSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionWidth XSPI Instruction Width + * @{ + */ +#define HAL_XSPI_INSTRUCTION_8_BITS (0x00000000U) /*!< 8-bit instruction */ +#define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ +#define HAL_XSPI_INSTRUCTION_24_BITS ((uint32_t)XSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ +#define HAL_XSPI_INSTRUCTION_32_BITS ((uint32_t)XSPI_CCR_ISIZE) /*!< 32-bit instruction */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode + * @{ + */ +#define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for instruction phase */ +#define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ +/** + * @} + */ + +/** @defgroup XSPI_AddressMode XSPI Address Mode + * @{ + */ +#define HAL_XSPI_ADDRESS_NONE (0x00000000U) /*!< No address */ +#define HAL_XSPI_ADDRESS_1_LINE ((uint32_t)XSPI_CCR_ADMODE_0) /*!< Address on a single line */ +#define HAL_XSPI_ADDRESS_2_LINES ((uint32_t)XSPI_CCR_ADMODE_1) /*!< Address on two lines */ +#define HAL_XSPI_ADDRESS_4_LINES ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1)) /*!< Address on four lines */ +#define HAL_XSPI_ADDRESS_8_LINES ((uint32_t)XSPI_CCR_ADMODE_2) /*!< Address on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_AddressWidth XSPI Address width + * @{ + */ +#define HAL_XSPI_ADDRESS_8_BITS (0x00000000U) /*!< 8-bit address */ +#define HAL_XSPI_ADDRESS_16_BITS ((uint32_t)XSPI_CCR_ADSIZE_0) /*!< 16-bit address */ +#define HAL_XSPI_ADDRESS_24_BITS ((uint32_t)XSPI_CCR_ADSIZE_1) /*!< 24-bit address */ +#define HAL_XSPI_ADDRESS_32_BITS ((uint32_t)XSPI_CCR_ADSIZE) /*!< 32-bit address */ +/** + * @} + */ + +/** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode + * @{ + */ +#define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for address phase */ +#define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode + * @{ + */ +#define HAL_XSPI_ALT_BYTES_NONE (0x00000000U) /*!< No alternate bytes */ +#define HAL_XSPI_ALT_BYTES_1_LINE ((uint32_t)XSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ +#define HAL_XSPI_ALT_BYTES_2_LINES ((uint32_t)XSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ +#define HAL_XSPI_ALT_BYTES_4_LINES ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ +#define HAL_XSPI_ALT_BYTES_8_LINES ((uint32_t)XSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width + * @{ + */ +#define HAL_XSPI_ALT_BYTES_8_BITS (0x00000000U) /*!< 8-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_16_BITS ((uint32_t)XSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_24_BITS ((uint32_t)XSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_32_BITS ((uint32_t)XSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode + * @{ + */ +#define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ +#define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ +/** + * @} + */ + +/** @defgroup XSPI_DataMode XSPI Data Mode + * @{ + */ +#define HAL_XSPI_DATA_NONE (0x00000000U) /*!< No data */ +#define HAL_XSPI_DATA_1_LINE ((uint32_t)XSPI_CCR_DMODE_0) /*!< Data on a single line */ +#define HAL_XSPI_DATA_2_LINES ((uint32_t)XSPI_CCR_DMODE_1) /*!< Data on two lines */ +#define HAL_XSPI_DATA_4_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1)) /*!< Data on four lines */ +#define HAL_XSPI_DATA_8_LINES ((uint32_t)XSPI_CCR_DMODE_2) /*!< Data on eight lines */ +#define HAL_XSPI_DATA_16_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2)) /*!< Data on sixteen lines valid for HSPI only */ +/** + * @} + */ + +/** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode + * @{ + */ +#define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for data phase */ +#define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ +/** + * @} + */ + +/** @defgroup XSPI_DQSMode XSPI DQS Mode + * @{ + */ +#define HAL_XSPI_DQS_DISABLE (0x00000000U) /*!< DQS disabled */ +#define HAL_XSPI_DQS_ENABLE ((uint32_t)XSPI_CCR_DQSE) /*!< DQS enabled */ +/** + * @} + */ + +/** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation + * @{ + */ +#define HAL_XSPI_LATENCY_ON_WRITE (0x00000000U) /*!< Latency on write accesses */ +#define HAL_XSPI_NO_LATENCY_ON_WRITE ((uint32_t)XSPI_HLCR_WZL) /*!< No latency on write accesses */ +/** + * @} + */ + +/** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode + * @{ + */ +#define HAL_XSPI_VARIABLE_LATENCY (0x00000000U) /*!< Variable initial latency */ +#define HAL_XSPI_FIXED_LATENCY ((uint32_t)XSPI_HLCR_LM) /*!< Fixed latency */ +/** + * @} + */ + +/** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space + * @{ + */ +#define HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */ +#define HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ +/** + * @} + */ + +/** @defgroup XSPI_MatchMode XSPI Match Mode + * @{ + */ +#define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between unmasked bits */ +#define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between unmasked bits */ +/** + * @} + */ + +/** @defgroup XSPI_AutomaticStop XSPI Automatic Stop + * @{ + */ +#define HAL_XSPI_AUTOMATIC_STOP_DISABLE (0x00000000U) /*!< AutoPolling stops only with abort or XSPI disabling */ +#define HAL_XSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)XSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ +/** + * @} + */ + +/** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation + * @{ + */ +#define HAL_XSPI_TIMEOUT_COUNTER_DISABLE (0x00000000U) /*!< Timeout counter disabled, nCS remains active */ +#define HAL_XSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)XSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ +/** + * @} + */ + +/** @defgroup XSPI_NoPrefetchAXI XSPI No Prefetch AXI + * @{ + */ +#define HAL_XSPI_AXI_PREFETCH_ENABLE (0x00000000U) /*!< Prefetch is enabled for AXI signaled transactions */ +#define HAL_XSPI_AXI_PREFETCH_DISABLE ((uint32_t)XSPI_CR_NOPREF_AXI) /*!< Prefetch is disable for AXI signaled transactions */ +/** + * @} + */ + +/** @defgroup XSPI_NoPrefetchData XSPI No Prefetch Data + * @{ + */ +#define HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE (0x00000000U) /*!< Automatic prefetch enabled */ +#define HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE ((uint32_t)XSPI_CR_NOPREF) /*!< Automatic prefetch disabled */ +/** + * @} + */ + +/** @defgroup XSPI_Flags XSPI Flags + * @{ + */ +#define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ +#define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ +#define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ +#define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ +#define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ +#define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ +/** + * @} + */ + +/** @defgroup XSPI_Interrupts XSPI Interrupts + * @{ + */ +#define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */ +#define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */ +#define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ +#define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ +#define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ +/** + * @} + */ + +/** @defgroup XSPI_Timeout_definition XSPI Timeout definition + * @{ + */ +#define HAL_XSPI_TIMEOUT_DEFAULT_VALUE (5000U) /* 5 s */ +/** + * @} + */ + +/** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port + * @{ + */ +#define HAL_XSPIM_IOPORT_1 (0x00000000U) /*!< Port 1 */ +#define HAL_XSPIM_IOPORT_2 (0x00000001U) /*!< Port 2 */ +/** + * @} + */ + + +/** @defgroup XSPI_DelayType XSPI Calibration Delay Type + * @{ + */ +#define HAL_XSPI_CAL_FULL_CYCLE_DELAY (0x00000000U) /*!< Delay value equivalent to full memory-clock cycle */ +#define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY (0x00000001U) /*!< Delay value for the feedback clock when reading without DQS */ +#define HAL_XSPI_CAL_DATA_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operations */ +#define HAL_XSPI_CAL_DQS_INPUT_DELAY (0x00000003U) /*!< Delay value for DQS input when sampling data for read operations */ +/** + * @} + */ + +/** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value + * @{ + */ +#define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */ +#define HAL_XSPI_MAXCAL_REACHED ((uint32_t)XSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */ +/** + * @} + */ + +/** @defgroup XSPIM_MemorySelect_Override XSPIM Memory Select Override + * @{ + */ +#define HAL_XSPI_CSSEL_OVR_DISABLED (0x00000000U) +#define HAL_XSPI_CSSEL_OVR_NCS1 (0x00000010U) /*!< The chip select signal from XSPI is sent to NCS1 */ +#define HAL_XSPI_CSSEL_OVR_NCS2 (0x00000070U) /*!< The chip select signal from XSPI is sent to NCS2 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Macros XSPI Exported Macros + * @{ + */ +/** @brief Reset XSPI handle state. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_XSPI_STATE_RESET) +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** @brief Enable the XSPI peripheral. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#define HAL_XSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) + +/** @brief Disable the XSPI peripheral. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#define HAL_XSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) + +/** @brief Enable the specified XSPI interrupt. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to enable. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval None + */ +#define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Disable the specified XSPI interrupt. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to disable. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval None + */ +#define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Check whether the specified XSPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to check. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ + == (__INTERRUPT__)) + +/** + * @brief Check whether the selected XSPI flag is set or not. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __FLAG__ specifies the XSPI flag to check. + * This parameter can be one of the following values: + * @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @retval None + */ +#define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ + != 0U) ? SET : RESET) + +/** @brief Clears the specified XSPI's flag status. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __FLAG__ specifies the XSPI clear register flag that needs to be set + * This parameter can be one of the following values: + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @retval None + */ +#define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup XSPI_Exported_Functions XSPI Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup XSPI_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* XSPI IRQ handler function */ +void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); + +/* XSPI command configuration functions */ +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd); +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCfgTypeDef *pCfg, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCmdTypeDef *pCmd, + uint32_t Timeout); + +/* XSPI indirect mode functions */ +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *pData); + +/* XSPI status flag polling mode functions */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg); + +/* XSPI memory-mapped mode functions */ +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, const XSPI_MemoryMappedTypeDef *pCfg); +uint32_t HAL_XSPI_IsMemoryMapped(XSPI_HandleTypeDef *hxspi); + +/* Callback functions in non-blocking modes ***********************************/ +void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI indirect mode Callback functions */ +void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI status flag polling mode functions */ +void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI memory-mapped mode functions */ +void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi); + +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/* XSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, + pXSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** + * @} + */ + +/* Peripheral Control and State functions ************************************/ +/** @addtogroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold); +uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type); +HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size); +HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler); +HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout); +uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi); +uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); + +/** + * @} + */ + +/* XSPI IO Manager configuration function ************************************/ +/** @addtogroup XSPI_Exported_Functions_Group4 IO Manager configuration function + * @{ + */ +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, const XSPIM_CfgTypeDef *pCfg, uint32_t Timeout); + +/** + * @} + */ + +/* XSPI high-speed interface and calibration functions ***********************/ +/** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *pCfg); +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, const XSPI_HSCalTypeDef *pCfg); + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** + @cond 0 + */ +#define IS_XSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ + ((THRESHOLD) <= ((XSPI_CR_FTHRES >> XSPI_CR_FTHRES_Pos)+1U))) +#define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ + ((MODE) == HAL_XSPI_DUAL_MEM)) + +#define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS)) + +#define IS_XSPI_MEMORY_SIZE(SIZE) (((SIZE) == HAL_XSPI_SIZE_16B) || \ + ((SIZE) == HAL_XSPI_SIZE_32B) || \ + ((SIZE) == HAL_XSPI_SIZE_64B) || \ + ((SIZE) == HAL_XSPI_SIZE_128B) || \ + ((SIZE) == HAL_XSPI_SIZE_256B) || \ + ((SIZE) == HAL_XSPI_SIZE_512B) || \ + ((SIZE) == HAL_XSPI_SIZE_1KB) || \ + ((SIZE) == HAL_XSPI_SIZE_2KB) || \ + ((SIZE) == HAL_XSPI_SIZE_4KB) || \ + ((SIZE) == HAL_XSPI_SIZE_8KB) || \ + ((SIZE) == HAL_XSPI_SIZE_16KB) || \ + ((SIZE) == HAL_XSPI_SIZE_32KB) || \ + ((SIZE) == HAL_XSPI_SIZE_64KB) || \ + ((SIZE) == HAL_XSPI_SIZE_128KB) || \ + ((SIZE) == HAL_XSPI_SIZE_256KB) || \ + ((SIZE) == HAL_XSPI_SIZE_512KB) || \ + ((SIZE) == HAL_XSPI_SIZE_1MB) || \ + ((SIZE) == HAL_XSPI_SIZE_2MB) || \ + ((SIZE) == HAL_XSPI_SIZE_4MB) || \ + ((SIZE) == HAL_XSPI_SIZE_8MB) || \ + ((SIZE) == HAL_XSPI_SIZE_16MB) || \ + ((SIZE) == HAL_XSPI_SIZE_32MB) || \ + ((SIZE) == HAL_XSPI_SIZE_64MB) || \ + ((SIZE) == HAL_XSPI_SIZE_128MB) || \ + ((SIZE) == HAL_XSPI_SIZE_256MB) || \ + ((SIZE) == HAL_XSPI_SIZE_512MB) || \ + ((SIZE) == HAL_XSPI_SIZE_1GB) || \ + ((SIZE) == HAL_XSPI_SIZE_2GB) || \ + ((SIZE) == HAL_XSPI_SIZE_4GB) || \ + ((SIZE) == HAL_XSPI_SIZE_8GB) || \ + ((SIZE) == HAL_XSPI_SIZE_16GB) || \ + ((SIZE) == HAL_XSPI_SIZE_32GB)) + +#define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) + +#define IS_XSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \ + ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE)) + +#define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ + ((MODE) == HAL_XSPI_CLOCK_MODE_3)) + +#define IS_XSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \ + ((SIZE) == HAL_XSPI_WRAP_16_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_32_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_64_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_128_BYTES)) + +#define IS_XSPI_CLK_PRESCALER(PRESCALER) ((PRESCALER) <= 255U) + +#define IS_XSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE) || \ + ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)) + +#define IS_XSPI_DHQC(CYCLE) (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \ + ((CYCLE) == HAL_XSPI_DHQC_ENABLE)) + +#define IS_XSPI_CS_BOUND(SIZE) (((SIZE) == HAL_XSPI_BONDARYOF_NONE) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16GB)) + + +#define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) + +#define IS_XSPI_CSSEL(CSSEL) (((CSSEL) == HAL_XSPI_CSSEL_NCS1) || \ + ((CSSEL) == HAL_XSPI_CSSEL_NCS2)) + +#define IS_XSPI_EXTENDMEM(EXTENDMEM) (((EXTENDMEM) == HAL_XSPI_CSSEL_SW) || \ + ((EXTENDMEM) == HAL_XSPI_CSSEL_HW)) + +#define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG)) + +#define IS_XSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_11_8) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_15_8)) + +#define IS_XSPI_INSTRUCTION(OPCODE) ((OPCODE) <= 0xFFFFFFFFU) + +#define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES)) + +#define IS_XSPI_INSTRUCTION_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS)) + +#define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + +#define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ + ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \ + ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \ + ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \ + ((MODE) == HAL_XSPI_ADDRESS_8_LINES)) + +#define IS_XSPI_ADDRESS_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS)) + +#define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE)) + +#define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES)) + +#define IS_XSPI_ALT_BYTES_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS)) + +#define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE)) + +#define IS_XSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ + (((MODE) == HAL_XSPI_DATA_NONE) || \ + ((MODE) == HAL_XSPI_DATA_8_LINES) || \ + ((MODE) == HAL_XSPI_DATA_16_LINES)): \ + (((MODE) == HAL_XSPI_DATA_NONE) || \ + ((MODE) == HAL_XSPI_DATA_1_LINE) || \ + ((MODE) == HAL_XSPI_DATA_2_LINES) || \ + ((MODE) == HAL_XSPI_DATA_4_LINES) || \ + ((MODE) == HAL_XSPI_DATA_8_LINES) || \ + ((MODE) == HAL_XSPI_DATA_16_LINES))) +#define IS_XSPI_DATA_LENGTH(NUMBER) ((NUMBER) >= 1U) + +#define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_DATA_DTR_ENABLE)) + +#define IS_XSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) + +#define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ + ((MODE) == HAL_XSPI_DQS_ENABLE)) + +#define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) + +#define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) + +#define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ + ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE)) + +#define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ + ((MODE) == HAL_XSPI_FIXED_LATENCY)) + +#define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \ + ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE)) + +#define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ + ((MODE) == HAL_XSPI_MATCH_MODE_OR)) + +#define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ + ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE)) + +#define IS_XSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) + +#define IS_XSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) + +#define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE)) +#define IS_XSPI_NO_PREFETCH_DATA(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE) || \ + ((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE)) + +#define IS_XSPI_NO_PREFETCH_AXI(MODE) (((MODE) == HAL_XSPI_AXI_PREFETCH_ENABLE) || \ + ((MODE) == HAL_XSPI_AXI_PREFETCH_DISABLE)) + +#define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) + +#define IS_XSPI_PROG_DATA(SET_DATA, REQ_DATA) ((SET_DATA) == (REQ_DATA)) + +#define IS_XSPI_PROG_ADDR(SET_ADDR, REQ_ADDR) ((SET_ADDR) == (REQ_ADDR)) + +#define IS_XSPIM_IO_PORT(PORT) (((PORT) == HAL_XSPIM_IOPORT_1) || \ + ((PORT) == HAL_XSPIM_IOPORT_2)) + +#define IS_XSPIM_NCS_OVR(PORT) (((PORT) == HAL_XSPI_CSSEL_OVR_DISABLED) || \ + ((PORT) == HAL_XSPI_CSSEL_OVR_NCS1) || \ + ((PORT) == HAL_XSPI_CSSEL_OVR_NCS2)) + +#define IS_XSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) + +#define IS_XSPI_DELAY_TYPE(TYPE) (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY)) + +#define IS_XSPI_FINECAL_VALUE(VALUE) ((VALUE) <= 0x7FU) + +#define IS_XSPI_COARSECAL_VALUE(VALUE) ((VALUE) <= 0x1FU) + +/** + @endcond + */ + +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XSPI || XSPI1 || XSPI2 || XSPI3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_XSPI_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_bus.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_bus.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_bus.h (revision 16) @@ -0,0 +1,3962 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_BUS_H +#define STM32N6xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AXI AXI + * @{ + */ +#define LL_ACLKN RCC_BUSENR_ACLKNEN +#define LL_ACLKNC RCC_BUSENR_ACLKNCEN +#define LL_AHBM RCC_BUSENR_AHBMEN +#define LL_AHB1 RCC_BUSENR_AHB1EN +#define LL_AHB2 RCC_BUSENR_AHB2EN +#define LL_AHB3 RCC_BUSENR_AHB3EN +#define LL_AHB4 RCC_BUSENR_AHB4EN +#define LL_AHB5 RCC_BUSENR_AHB5EN +#define LL_APB1 RCC_BUSENR_APB1EN +#define LL_APB2 RCC_BUSENR_APB2EN +#define LL_APB3 RCC_BUSENR_APB3EN +#define LL_APB4 RCC_BUSENR_APB4EN +#define LL_APB5 RCC_BUSENR_APB5EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_MEM MEM + * @{ + */ +#define LL_MEM_AXISRAM1 RCC_MEMENR_AXISRAM1EN +#define LL_MEM_AXISRAM2 RCC_MEMENR_AXISRAM2EN +#define LL_MEM_AXISRAM3 RCC_MEMENR_AXISRAM3EN +#define LL_MEM_AXISRAM4 RCC_MEMENR_AXISRAM4EN +#define LL_MEM_AXISRAM5 RCC_MEMENR_AXISRAM5EN +#define LL_MEM_AXISRAM6 RCC_MEMENR_AXISRAM6EN +#define LL_MEM_AHBSRAM1 RCC_MEMENR_AHBSRAM1EN +#define LL_MEM_AHBSRAM2 RCC_MEMENR_AHBSRAM2EN +#define LL_MEM_BKPSRAM RCC_MEMENR_BKPSRAMEN +#define LL_MEM_FLEXRAM RCC_MEMENR_FLEXRAMEN +#define LL_MEM_CACHEAXIRAM RCC_MEMENR_CACHEAXIRAMEN +#define LL_MEM_VENCRAM RCC_MEMENR_VENCRAMEN +#define LL_MEM_BOOTROM RCC_MEMENR_BOOTROMEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN +#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#define LL_AHB1_GRP1_PERIPH_ALL (LL_AHB1_GRP1_PERIPH_ADC12 | LL_AHB1_GRP1_PERIPH_GPDMA1) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ADF1 RCC_AHB2ENR_ADF1EN +#define LL_AHB2_GRP1_PERIPH_MDF1 RCC_AHB2ENR_MDF1EN +#define LL_AHB2_GRP1_PERIPH_RAMCFG RCC_AHB2ENR_RAMCFGEN +#define LL_AHB2_GRP1_PERIPH_ALL (LL_AHB2_GRP1_PERIPH_ADF1 | LL_AHB2_GRP1_PERIPH_MDF1 | \ + LL_AHB2_GRP1_PERIPH_RAMCFG) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#if defined(CRYP) +#define LL_AHB3_GRP1_PERIPH_CRYP RCC_AHB3ENR_CRYPEN +#else +#define LL_AHB3_GRP1_PERIPH_CRYP +#endif /* CRYP */ +#define LL_AHB3_GRP1_PERIPH_HASH RCC_AHB3ENR_HASHEN +#define LL_AHB3_GRP1_PERIPH_IAC RCC_AHB3ENR_IACEN +#if defined(PKA) +#define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN +#else +#define LL_AHB3_GRP1_PERIPH_PKA +#endif /* PKA */ +#define LL_AHB3_GRP1_PERIPH_RIFSC RCC_AHB3ENR_RIFSCEN +#define LL_AHB3_GRP1_PERIPH_RISAF RCC_AHB3ENR_RISAFEN +#define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN +#if defined(SAES) +#define LL_AHB3_GRP1_PERIPH_SAES RCC_AHB3ENR_SAESEN +#else +#define LL_AHB3_GRP1_PERIPH_SAES +#endif /* SAES */ +#define LL_AHB3_GRP1_PERIPH_ALL (LL_AHB3_GRP1_PERIPH_CRYP | LL_AHB3_GRP1_PERIPH_HASH | \ + LL_AHB3_GRP1_PERIPH_IAC | LL_AHB3_GRP1_PERIPH_PKA | \ + LL_AHB3_GRP1_PERIPH_RIFSC | LL_AHB3_GRP1_PERIPH_RISAF | \ + LL_AHB3_GRP1_PERIPH_RNG | LL_AHB3_GRP1_PERIPH_SAES) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN +#define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN +#define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN +#define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN +#define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN +#define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN +#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN +#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN +#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN +#define LL_AHB4_GRP1_PERIPH_GPION RCC_AHB4ENR_GPIONEN +#define LL_AHB4_GRP1_PERIPH_GPIOO RCC_AHB4ENR_GPIOOEN +#define LL_AHB4_GRP1_PERIPH_GPIOP RCC_AHB4ENR_GPIOPEN +#define LL_AHB4_GRP1_PERIPH_GPIOQ RCC_AHB4ENR_GPIOQEN +#define LL_AHB4_GRP1_PERIPH_PWR RCC_AHB4ENR_PWREN +#define LL_AHB4_GRP1_PERIPH_ALL (LL_AHB4_GRP1_PERIPH_CRC | LL_AHB4_GRP1_PERIPH_GPIOA | \ + LL_AHB4_GRP1_PERIPH_GPIOB | LL_AHB4_GRP1_PERIPH_GPIOC | \ + LL_AHB4_GRP1_PERIPH_GPIOD | LL_AHB4_GRP1_PERIPH_GPIOE | \ + LL_AHB4_GRP1_PERIPH_GPIOF | LL_AHB4_GRP1_PERIPH_GPIOG | \ + LL_AHB4_GRP1_PERIPH_GPIOH | LL_AHB4_GRP1_PERIPH_GPION | \ + LL_AHB4_GRP1_PERIPH_GPIOO | LL_AHB4_GRP1_PERIPH_GPIOP | \ + LL_AHB4_GRP1_PERIPH_GPIOQ | LL_AHB4_GRP1_PERIPH_PWR) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH + * @{ + */ +#define LL_AHB5_GRP1_PERIPH_DMA2D RCC_AHB5ENR_DMA2DEN +#define LL_AHB5_GRP1_PERIPH_ETH1 RCC_AHB5ENR_ETH1EN +#define LL_AHB5_GRP1_PERIPH_ETH1MAC RCC_AHB5ENR_ETH1MACEN +#define LL_AHB5_GRP1_PERIPH_ETH1TX RCC_AHB5ENR_ETH1TXEN +#define LL_AHB5_GRP1_PERIPH_ETH1RX RCC_AHB5ENR_ETH1RXEN +#define LL_AHB5_GRP1_PERIPH_FMC RCC_AHB5ENR_FMCEN +#define LL_AHB5_GRP1_PERIPH_GFXMMU RCC_AHB5ENR_GFXMMUEN +#define LL_AHB5_GRP1_PERIPH_GPU2D RCC_AHB5ENR_GPU2DEN +#define LL_AHB5_GRP1_PERIPH_HPDMA1 RCC_AHB5ENR_HPDMA1EN +#define LL_AHB5_GRP1_PERIPH_XSPI1 RCC_AHB5ENR_XSPI1EN +#define LL_AHB5_GRP1_PERIPH_XSPI2 RCC_AHB5ENR_XSPI2EN +#define LL_AHB5_GRP1_PERIPH_XSPI3 RCC_AHB5ENR_XSPI3EN +#define LL_AHB5_GRP1_PERIPH_XSPIM RCC_AHB5ENR_XSPIMEN +#define LL_AHB5_GRP1_PERIPH_JPEG RCC_AHB5ENR_JPEGEN +#define LL_AHB5_GRP1_PERIPH_MCE1 RCC_AHB5ENR_MCE1EN +#define LL_AHB5_GRP1_PERIPH_MCE2 RCC_AHB5ENR_MCE2EN +#define LL_AHB5_GRP1_PERIPH_MCE3 RCC_AHB5ENR_MCE3EN +#define LL_AHB5_GRP1_PERIPH_MCE4 RCC_AHB5ENR_MCE4EN +#define LL_AHB5_GRP1_PERIPH_CACHEAXI RCC_AHB5ENR_CACHEAXIEN +#define LL_AHB5_GRP1_PERIPH_NPU RCC_AHB5ENR_NPUEN +#define LL_AHB5_GRP1_PERIPH_OTG1 RCC_AHB5ENR_OTG1EN +#define LL_AHB5_GRP1_PERIPH_OTG2 RCC_AHB5ENR_OTG2EN +#define LL_AHB5_GRP1_PERIPH_OTGPHY1 RCC_AHB5ENR_OTGPHY1EN +#define LL_AHB5_GRP1_PERIPH_OTGPHY2 RCC_AHB5ENR_OTGPHY2EN +#define LL_AHB5_GRP1_PERIPH_OTG1PHYCTL RCC_AHB5RSTR_OTG1PHYCTLRST +#define LL_AHB5_GRP1_PERIPH_OTG2PHYCTL RCC_AHB5RSTR_OTG2PHYCTLRST +#define LL_AHB5_GRP1_PERIPH_PSSI RCC_AHB5ENR_PSSIEN +#define LL_AHB5_GRP1_PERIPH_SDMMC1 RCC_AHB5ENR_SDMMC1EN +#define LL_AHB5_GRP1_PERIPH_SDMMC2 RCC_AHB5ENR_SDMMC2EN +#define LL_AHB5_GRP1_PERIPH_ALL (LL_AHB5_GRP1_PERIPH_DMA2D | LL_AHB5_GRP1_PERIPH_ETH1 | \ + LL_AHB5_GRP1_PERIPH_ETH1MAC | LL_AHB5_GRP1_PERIPH_ETH1TX | \ + LL_AHB5_GRP1_PERIPH_ETH1RX | LL_AHB5_GRP1_PERIPH_FMC | \ + LL_AHB5_GRP1_PERIPH_GFXMMU | LL_AHB5_GRP1_PERIPH_GPU2D | \ + LL_AHB5_GRP1_PERIPH_HPDMA1 | LL_AHB5_GRP1_PERIPH_XSPI1 | \ + LL_AHB5_GRP1_PERIPH_XSPI2 | LL_AHB5_GRP1_PERIPH_XSPI3 | \ + LL_AHB5_GRP1_PERIPH_XSPIM | LL_AHB5_GRP1_PERIPH_JPEG | \ + LL_AHB5_GRP1_PERIPH_MCE1 | LL_AHB5_GRP1_PERIPH_MCE2 | \ + LL_AHB5_GRP1_PERIPH_MCE3 | LL_AHB5_GRP1_PERIPH_MCE4 | \ + LL_AHB5_GRP1_PERIPH_CACHEAXI | LL_AHB5_GRP1_PERIPH_NPU | \ + LL_AHB5_GRP1_PERIPH_OTG1 | LL_AHB5_GRP1_PERIPH_OTG2 | \ + LL_AHB5_GRP1_PERIPH_OTGPHY1 | LL_AHB5_GRP1_PERIPH_OTGPHY2 | \ + LL_AHB5_GRP1_PERIPH_PSSI | LL_AHB5_GRP1_PERIPH_SDMMC1 | \ + LL_AHB5_GRP1_PERIPH_SDMMC2) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN +#define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1ENR1_I3C1EN +#define LL_APB1_GRP1_PERIPH_I3C2 RCC_APB1ENR1_I3C2EN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN +#define LL_APB1_GRP1_PERIPH_SPDIFRX1 RCC_APB1ENR1_SPDIFRX1EN +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM10 RCC_APB1ENR1_TIM10EN +#define LL_APB1_GRP1_PERIPH_TIM11 RCC_APB1ENR1_TIM11EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR1_TIM12EN +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR1_TIM13EN +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR1_TIM14EN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR1_UART7EN +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR1_UART8EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#define LL_APB1_GRP1_PERIPH_ALL (LL_APB1_GRP1_PERIPH_I2C1 | LL_APB1_GRP1_PERIPH_I2C2 | \ + LL_APB1_GRP1_PERIPH_I2C3 | LL_APB1_GRP1_PERIPH_I3C1 | \ + LL_APB1_GRP1_PERIPH_I3C2 | LL_APB1_GRP1_PERIPH_LPTIM1 | \ + LL_APB1_GRP1_PERIPH_SPDIFRX1 | LL_APB1_GRP1_PERIPH_SPI2 | \ + LL_APB1_GRP1_PERIPH_SPI3 | LL_APB1_GRP1_PERIPH_TIM2 | \ + LL_APB1_GRP1_PERIPH_TIM3 | LL_APB1_GRP1_PERIPH_TIM4 | \ + LL_APB1_GRP1_PERIPH_TIM5 | LL_APB1_GRP1_PERIPH_TIM6 | \ + LL_APB1_GRP1_PERIPH_TIM7 | LL_APB1_GRP1_PERIPH_TIM10 | \ + LL_APB1_GRP1_PERIPH_TIM11 | LL_APB1_GRP1_PERIPH_TIM12 | \ + LL_APB1_GRP1_PERIPH_TIM13 | LL_APB1_GRP1_PERIPH_TIM14 | \ + LL_APB1_GRP1_PERIPH_USART2 | LL_APB1_GRP1_PERIPH_USART3 | \ + LL_APB1_GRP1_PERIPH_UART4 | LL_APB1_GRP1_PERIPH_UART5 | \ + LL_APB1_GRP1_PERIPH_UART7 | LL_APB1_GRP1_PERIPH_UART8 | \ + LL_APB1_GRP1_PERIPH_WWDG) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1ENR2_FDCANEN +#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1ENR2_MDIOSEN +#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN +#define LL_APB1_GRP2_PERIPH_ALL (LL_APB1_GRP2_PERIPH_FDCAN | LL_APB1_GRP2_PERIPH_MDIOS | \ + LL_APB1_GRP2_PERIPH_UCPD1) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB2_GRP1_PERIPH_TIM18 RCC_APB2ENR_TIM18EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN +#define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN +#define LL_APB2_GRP1_PERIPH_ALL (LL_APB2_GRP1_PERIPH_SAI1 | LL_APB2_GRP1_PERIPH_SAI2 | \ + LL_APB2_GRP1_PERIPH_SPI1 | LL_APB2_GRP1_PERIPH_SPI4 | \ + LL_APB2_GRP1_PERIPH_SPI5 | LL_APB2_GRP1_PERIPH_TIM1 | \ + LL_APB2_GRP1_PERIPH_TIM8 | LL_APB2_GRP1_PERIPH_TIM9 | \ + LL_APB2_GRP1_PERIPH_TIM15 | LL_APB2_GRP1_PERIPH_TIM16 | \ + LL_APB2_GRP1_PERIPH_TIM17 | LL_APB2_GRP1_PERIPH_TIM18 | \ + LL_APB2_GRP1_PERIPH_USART1 | LL_APB2_GRP1_PERIPH_USART6 | \ + LL_APB2_GRP1_PERIPH_UART9 | LL_APB2_GRP1_PERIPH_USART10) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH + * @{ + */ +#define LL_APB4_GRP1_PERIPH_HDP RCC_APB4ENR1_HDPEN +#define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR1_I2C4EN +#define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR1_LPTIM2EN +#define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR1_LPTIM3EN +#define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR1_LPTIM4EN +#define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR1_LPTIM5EN +#define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR1_LPUART1EN +#define LL_APB4_GRP1_PERIPH_RTC RCC_APB4ENR1_RTCEN +#define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR1_RTCAPBEN +#define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR1_SPI6EN +#define LL_APB4_GRP1_PERIPH_VREFBUF RCC_APB4ENR1_VREFBUFEN +#define LL_APB4_GRP1_PERIPH_ALL (LL_APB4_GRP1_PERIPH_HDP | LL_APB4_GRP1_PERIPH_I2C4 | \ + LL_APB4_GRP1_PERIPH_LPTIM2 | LL_APB4_GRP1_PERIPH_LPTIM3 | \ + LL_APB4_GRP1_PERIPH_LPTIM4 | LL_APB4_GRP1_PERIPH_LPTIM5 | \ + LL_APB4_GRP1_PERIPH_LPUART1 | LL_APB4_GRP1_PERIPH_RTC | \ + LL_APB4_GRP1_PERIPH_RTCAPB | LL_APB4_GRP1_PERIPH_SPI6 | \ + LL_APB4_GRP1_PERIPH_VREFBUF) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB4_GRP2_PERIPH APB4 GRP2 PERIPH + * @{ + */ +#define LL_APB4_GRP2_PERIPH_BSEC RCC_APB4ENR2_BSECEN +#define LL_APB4_GRP2_PERIPH_DTS RCC_APB4ENR2_DTSEN +#define LL_APB4_GRP2_PERIPH_SYSCFG RCC_APB4ENR2_SYSCFGEN +#define LL_APB4_GRP2_PERIPH_ALL (LL_APB4_GRP2_PERIPH_BSEC | LL_APB4_GRP2_PERIPH_DTS | \ + LL_APB4_GRP2_PERIPH_SYSCFG) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB5_GRP1_PERIPH APB5 GRP1 PERIPH + * @{ + */ +#define LL_APB5_GRP1_PERIPH_CSI RCC_APB5ENR_CSIEN +#define LL_APB5_GRP1_PERIPH_DCMIPP RCC_APB5ENR_DCMIPPEN +#define LL_APB5_GRP1_PERIPH_GFXTIM RCC_APB5ENR_GFXTIMEN +#define LL_APB5_GRP1_PERIPH_LTDC RCC_APB5ENR_LTDCEN +#if defined(VENC) +#define LL_APB5_GRP1_PERIPH_VENC RCC_APB5ENR_VENCEN +#else +#define LL_APB5_GRP1_PERIPH_VENC +#endif /* VENC */ +#define LL_APB5_GRP1_PERIPH_ALL (LL_APB5_GRP1_PERIPH_CSI | LL_APB5_GRP1_PERIPH_DCMIPP | \ + LL_APB5_GRP1_PERIPH_GFXTIM | LL_APB5_GRP1_PERIPH_LTDC | \ + LL_APB5_GRP1_PERIPH_VENC) +/** + * @} + */ + +/** @defgroup BUS_LL_EC_MISC MISC + * @{ + */ +#define LL_DBG RCC_MISCENR_DBGEN +#define LL_MCO1 RCC_MISCENR_MCO1EN +#define LL_MCO2 RCC_MISCENR_MCO2EN +#define LL_XSPIPHYCOMP RCC_MISCENR_XSPIPHYCOMPEN +#define LL_XSPIPHY1 RCC_MISCRSTR_XSPIPHY1RST +#define LL_XSPIPHY2 RCC_MISCRSTR_XSPIPHY2RST +#define LL_PER RCC_MISCENR_PEREN +#define LL_SDMMC1DLL RCC_MISCRSTR_SDMMC1DLLRST +#define LL_SDMMC2DLL RCC_MISCRSTR_SDMMC2DLLRST +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_BUS BUS + * @{ + */ + +/** + * @brief Enable AXI bus clock. + * @rmtoll BUSENSR ACLKNENS LL_BUS_EnableClock\n + * BUSENSR ACLKNCENS LL_BUS_EnableClock\n + * BUSENSR AHBMENS LL_BUS_EnableClock\n + * BUSENSR AHB1ENS LL_BUS_EnableClock\n + * BUSENSR AHB2ENS LL_BUS_EnableClock\n + * BUSENSR AHB3ENS LL_BUS_EnableClock\n + * BUSENSR AHB4ENS LL_BUS_EnableClock\n + * BUSENSR AHB5ENS LL_BUS_EnableClock\n + * BUSENSR APB1ENS LL_BUS_EnableClock\n + * BUSENSR APB2ENS LL_BUS_EnableClock\n + * BUSENSR APB3ENS LL_BUS_EnableClock\n + * BUSENSR APB4ENS LL_BUS_EnableClock\n + * BUSENSR APB5ENS LL_BUS_EnableClock + * @param Bus This parameter can be a combination of the following values: + * @arg @ref LL_ACLKN + * @arg @ref LL_ACLKNC + * @arg @ref LL_AHBM + * @arg @ref LL_AHB1 + * @arg @ref LL_AHB2 + * @arg @ref LL_AHB3 + * @arg @ref LL_AHB4 + * @arg @ref LL_AHB5 + * @arg @ref LL_APB1 + * @arg @ref LL_APB2 + * @arg @ref LL_APB3 + * @arg @ref LL_APB4 + * @arg @ref LL_APB5 + * @retval None + */ +__STATIC_INLINE void LL_BUS_EnableClock(uint32_t Bus) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->BUSENSR, Bus); + /* Delay after an RCC bus clock enabling */ + tmpreg = READ_REG(RCC->BUSENR); + (void)tmpreg; +} + +/** + * @brief Check if AXI bus clock is enabled or not + * @rmtoll BUSENR ACLKNEN LL_BUS_IsEnabledClock\n + * BUSENR ACLKNCEN LL_BUS_IsEnabledClock\n + * BUSENR AHBMEN LL_BUS_IsEnabledClock\n + * BUSENR AHB1EN LL_BUS_IsEnabledClock\n + * BUSENR AHB2EN LL_BUS_IsEnabledClock\n + * BUSENR AHB3EN LL_BUS_IsEnabledClock\n + * BUSENR AHB4EN LL_BUS_IsEnabledClock\n + * BUSENR AHB5EN LL_BUS_IsEnabledClock\n + * BUSENR APB1EN LL_BUS_IsEnabledClock\n + * BUSENR APB2EN LL_BUS_IsEnabledClock\n + * BUSENR APB3EN LL_BUS_IsEnabledClock\n + * BUSENR APB4EN LL_BUS_IsEnabledClock\n + * BUSENR APB5EN LL_BUS_IsEnabledClock + * @param Bus This parameter can be a combination of the following values: + * @arg @ref LL_ACLKN + * @arg @ref LL_ACLKNC + * @arg @ref LL_AHBM + * @arg @ref LL_AHB1 + * @arg @ref LL_AHB2 + * @arg @ref LL_AHB3 + * @arg @ref LL_AHB4 + * @arg @ref LL_AHB5 + * @arg @ref LL_APB1 + * @arg @ref LL_APB2 + * @arg @ref LL_APB3 + * @arg @ref LL_APB4 + * @arg @ref LL_APB5 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_BUS_IsEnabledClock(uint32_t Bus) +{ + return ((READ_BIT(RCC->BUSENR, Bus) == Bus) ? 1UL : 0UL); +} + +/** + * @brief Disable AXI bus clock. + * @rmtoll BUSENCR ACLKNENC LL_BUS_DisableClock\n + * BUSENCR ACLKNCENC LL_BUS_DisableClock\n + * BUSENCR AHBMENC LL_BUS_DisableClock\n + * BUSENCR AHB1ENC LL_BUS_DisableClock\n + * BUSENCR AHB2ENC LL_BUS_DisableClock\n + * BUSENCR AHB3ENC LL_BUS_DisableClock\n + * BUSENCR AHB4ENC LL_BUS_DisableClock\n + * BUSENCR AHB5ENC LL_BUS_DisableClock\n + * BUSENCR APB1ENC LL_BUS_DisableClock\n + * BUSENCR APB2ENC LL_BUS_DisableClock\n + * BUSENCR APB3ENC LL_BUS_DisableClock\n + * BUSENCR APB4ENC LL_BUS_DisableClock\n + * BUSENCR APB5ENC LL_BUS_DisableClock + * @param Bus This parameter can be a combination of the following values: + * @arg @ref LL_ACLKN + * @arg @ref LL_ACLKNC + * @arg @ref LL_AHBM + * @arg @ref LL_AHB1 + * @arg @ref LL_AHB2 + * @arg @ref LL_AHB3 + * @arg @ref LL_AHB4 + * @arg @ref LL_AHB5 + * @arg @ref LL_APB1 + * @arg @ref LL_APB2 + * @arg @ref LL_APB3 + * @arg @ref LL_APB4 + * @arg @ref LL_APB5 + * @retval None + */ +__STATIC_INLINE void LL_BUS_DisableClock(uint32_t Bus) +{ + WRITE_REG(RCC->BUSENCR, Bus); +} + +/** + * @brief Enable AXI bus clock during Low Power mode. + * @rmtoll BUSLPENSR ACLKNLPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR ACLKNCLPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR AHBMLPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR AHB1LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR AHB2LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR AHB3LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR AHB4LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR AHB5LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR APB1LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR APB2LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR APB3LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR APB4LPENS LL_BUS_EnableClockLowPower\n + * BUSLPENSR APB5LPENS LL_BUS_EnableClockLowPower + * @param Bus This parameter can be a combination of the following values: + * @arg @ref LL_ACLKN + * @arg @ref LL_ACLKNC + * @arg @ref LL_AHBM + * @arg @ref LL_AHB1 + * @arg @ref LL_AHB2 + * @arg @ref LL_AHB3 + * @arg @ref LL_AHB4 + * @arg @ref LL_AHB5 + * @arg @ref LL_APB1 + * @arg @ref LL_APB2 + * @arg @ref LL_APB3 + * @arg @ref LL_APB4 + * @arg @ref LL_APB5 + * @retval None + */ +__STATIC_INLINE void LL_BUS_EnableClockLowPower(uint32_t Bus) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->BUSLPENSR, Bus); + /* Delay after an RCC bus clock enabling */ + tmpreg = READ_REG(RCC->BUSLPENR); + (void)tmpreg; +} + +/** + * @brief Check if AXI bus clock during Low Power mode is enabled or not + * @rmtoll BUSLPENR ACLKNLPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR ACLKNCLPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR AHBMLPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR AHB1LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR AHB2LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR AHB3LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR AHB4LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR AHB5LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR APB1LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR APB2LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR APB3LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR APB4LPEN LL_BUS_IsEnabledClockLowPower\n + * BUSLPENR APB5LPEN LL_BUS_IsEnabledClockLowPower + * @param Bus This parameter can be a combination of the following values: + * @arg @ref LL_ACLKN + * @arg @ref LL_ACLKNC + * @arg @ref LL_AHBM + * @arg @ref LL_AHB1 + * @arg @ref LL_AHB2 + * @arg @ref LL_AHB3 + * @arg @ref LL_AHB4 + * @arg @ref LL_AHB5 + * @arg @ref LL_APB1 + * @arg @ref LL_APB2 + * @arg @ref LL_APB3 + * @arg @ref LL_APB4 + * @arg @ref LL_APB5 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_BUS_IsEnabledClockLowPower(uint32_t Bus) +{ + return ((READ_BIT(RCC->BUSLPENR, Bus) == Bus) ? 1UL : 0UL); +} + +/** + * @brief Disable AXI bus clock during Low Power mode. + * @rmtoll BUSLPENCR ACLKNLPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR ACLKNCLPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR AHBMLPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR AHB1LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR AHB2LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR AHB3LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR AHB4LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR AHB5LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR APB1LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR APB2LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR APB3LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR APB4LPENC LL_BUS_DisableClockLowPower\n + * BUSLPENCR APB5LPENC LL_BUS_DisableClockLowPower + * @param Bus This parameter can be a combination of the following values: + * @arg @ref LL_ACLKN + * @arg @ref LL_ACLKNC + * @arg @ref LL_AHBM + * @arg @ref LL_AHB1 + * @arg @ref LL_AHB2 + * @arg @ref LL_AHB3 + * @arg @ref LL_AHB4 + * @arg @ref LL_AHB5 + * @arg @ref LL_APB1 + * @arg @ref LL_APB2 + * @arg @ref LL_APB3 + * @arg @ref LL_APB4 + * @arg @ref LL_APB5 + * @retval None + */ +__STATIC_INLINE void LL_BUS_DisableClockLowPower(uint32_t Bus) +{ + WRITE_REG(RCC->BUSLPENCR, Bus); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_MEM MEM + * @{ + */ + +/** + * @brief Enable memories clock. + * @rmtoll MEMENSR AXISRAM1ENS LL_MEM_EnableClock\n + * MEMENSR AXISRAM2ENS LL_MEM_EnableClock\n + * MEMENSR AXISRAM3ENS LL_MEM_EnableClock\n + * MEMENSR AXISRAM4ENS LL_MEM_EnableClock\n + * MEMENSR AXISRAM5ENS LL_MEM_EnableClock\n + * MEMENSR AXISRAM6ENS LL_MEM_EnableClock\n + * MEMENSR AHBSRAM1ENS LL_MEM_EnableClock\n + * MEMENSR AHBSRAM2ENS LL_MEM_EnableClock\n + * MEMENSR BKPSRAMENS LL_MEM_EnableClock\n + * MEMENSR FLEXRAMENS LL_MEM_EnableClock\n + * MEMENSR CACHEAXIRAMENS LL_MEM_EnableClock\n + * MEMENSR VENCRAMENS LL_MEM_EnableClock + * @param Memories This parameter can be a combination of the following values: + * @arg @ref LL_MEM_AXISRAM1 + * @arg @ref LL_MEM_AXISRAM2 + * @arg @ref LL_MEM_AXISRAM3 + * @arg @ref LL_MEM_AXISRAM4 + * @arg @ref LL_MEM_AXISRAM5 + * @arg @ref LL_MEM_AXISRAM6 + * @arg @ref LL_MEM_AHBSRAM1 + * @arg @ref LL_MEM_AHBSRAM2 + * @arg @ref LL_MEM_BKPSRAM + * @arg @ref LL_MEM_FLEXRAM + * @arg @ref LL_MEM_CACHEAXIRAM + * @arg @ref LL_MEM_VENCRAM + * @retval None + */ +__STATIC_INLINE void LL_MEM_EnableClock(uint32_t Memories) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->MEMENSR, Memories); + /* Delay after an RCC memories clock enabling */ + tmpreg = READ_REG(RCC->MEMENR); + (void)tmpreg; +} + +/** + * @brief Check if memory clock is enabled or not + * @rmtoll MEMENR AXISRAM1EN LL_MEM_IsEnabledClock\n + * MEMENR AXISRAM2EN LL_MEM_IsEnabledClock\n + * MEMENR AXISRAM3EN LL_MEM_IsEnabledClock\n + * MEMENR AXISRAM4EN LL_MEM_IsEnabledClock\n + * MEMENR AXISRAM5EN LL_MEM_IsEnabledClock\n + * MEMENR AXISRAM6EN LL_MEM_IsEnabledClock\n + * MEMENR AHBSRAM1EN LL_MEM_IsEnabledClock\n + * MEMENR AHBSRAM2EN LL_MEM_IsEnabledClock\n + * MEMENR BKPSRAMEN LL_MEM_IsEnabledClock\n + * MEMENR FLEXRAMEN LL_MEM_IsEnabledClock\n + * MEMENR CACHEAXIRAMEN LL_MEM_IsEnabledClock\n + * MEMENR VENCRAMEN LL_MEM_IsEnabledClock + * @param Memories This parameter can be a combination of the following values: + * @arg @ref LL_MEM_AXISRAM1 + * @arg @ref LL_MEM_AXISRAM2 + * @arg @ref LL_MEM_AXISRAM3 + * @arg @ref LL_MEM_AXISRAM4 + * @arg @ref LL_MEM_AXISRAM5 + * @arg @ref LL_MEM_AXISRAM6 + * @arg @ref LL_MEM_AHBSRAM1 + * @arg @ref LL_MEM_AHBSRAM2 + * @arg @ref LL_MEM_BKPSRAM + * @arg @ref LL_MEM_FLEXRAM + * @arg @ref LL_MEM_CACHEAXIRAM + * @arg @ref LL_MEM_VENCRAM + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_MEM_IsEnabledClock(uint32_t Memories) +{ + return ((READ_BIT(RCC->MEMENR, Memories) == Memories) ? 1UL : 0UL); +} + +/** + * @brief Disable memories clock. + * @rmtoll MEMENCR AXISRAM1ENC LL_MEM_DisableClock\n + * MEMENCR AXISRAM2ENC LL_MEM_DisableClock\n + * MEMENCR AXISRAM3ENC LL_MEM_DisableClock\n + * MEMENCR AXISRAM4ENC LL_MEM_DisableClock\n + * MEMENCR AXISRAM5ENC LL_MEM_DisableClock\n + * MEMENCR AXISRAM6ENC LL_MEM_DisableClock\n + * MEMENCR AHBSRAM1ENC LL_MEM_DisableClock\n + * MEMENCR AHBSRAM2ENC LL_MEM_DisableClock\n + * MEMENCR BKPSRAMENC LL_MEM_DisableClock\n + * MEMENCR FLEXRAMENC LL_MEM_DisableClock\n + * MEMENCR CACHEAXIRAMENC LL_MEM_DisableClock\n + * MEMENCR VENCRAMENC LL_MEM_DisableClock + * @param Memories This parameter can be a combination of the following values: + * @arg @ref LL_MEM_AXISRAM1 + * @arg @ref LL_MEM_AXISRAM2 + * @arg @ref LL_MEM_AXISRAM3 + * @arg @ref LL_MEM_AXISRAM4 + * @arg @ref LL_MEM_AXISRAM5 + * @arg @ref LL_MEM_AXISRAM6 + * @arg @ref LL_MEM_AHBSRAM1 + * @arg @ref LL_MEM_AHBSRAM2 + * @arg @ref LL_MEM_BKPSRAM + * @arg @ref LL_MEM_FLEXRAM + * @arg @ref LL_MEM_CACHEAXIRAM + * @arg @ref LL_MEM_VENCRAM + * @retval None + */ +__STATIC_INLINE void LL_MEM_DisableClock(uint32_t Memories) +{ + WRITE_REG(RCC->MEMENCR, Memories); +} + +/** + * @brief Enable memories clock during Low Power mode. + * @rmtoll MEMLPENSR AXISRAM1LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR AXISRAM2LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR AXISRAM3LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR AXISRAM4LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR AXISRAM5LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR AXISRAM6LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR AHBSRAM1LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR AHBSRAM2LPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR BKPSRAMLPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR FLEXRAMLPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR CACHEAXIRAMLPENS LL_MEM_EnableClockLowPower\n + * MEMLPENSR VENCRAMLPENS LL_MEM_EnableClockLowPower + * @param Memories This parameter can be a combination of the following values: + * @arg @ref LL_MEM_AXISRAM1 + * @arg @ref LL_MEM_AXISRAM2 + * @arg @ref LL_MEM_AXISRAM3 + * @arg @ref LL_MEM_AXISRAM4 + * @arg @ref LL_MEM_AXISRAM5 + * @arg @ref LL_MEM_AXISRAM6 + * @arg @ref LL_MEM_AHBSRAM1 + * @arg @ref LL_MEM_AHBSRAM2 + * @arg @ref LL_MEM_BKPSRAM + * @arg @ref LL_MEM_FLEXRAM + * @arg @ref LL_MEM_CACHEAXIRAM + * @arg @ref LL_MEM_VENCRAM + * @retval None + */ +__STATIC_INLINE void LL_MEM_EnableClockLowPower(uint32_t Memories) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->MEMLPENSR, Memories); + /* Delay after an RCC memories clock enabling */ + tmpreg = READ_REG(RCC->MEMLPENR); + (void)tmpreg; +} + +/** + * @brief Check if memories clock during Low Power mode is enabled or not . + * @rmtoll MEMLPENR AXISRAM1LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR AXISRAM2LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR AXISRAM3LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR AXISRAM4LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR AXISRAM5LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR AXISRAM6LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR AHBSRAM1LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR AHBSRAM2LPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR BKPSRAMLPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR FLEXRAMLPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR CACHEAXIRAMLPEN LL_MEM_IsEnabledClockLowPower\n + * MEMLPENR VENCRAMLPEN LL_MEM_IsEnabledClockLowPower + * @param Memories This parameter can be a combination of the following values: + * @arg @ref LL_MEM_AXISRAM1 + * @arg @ref LL_MEM_AXISRAM2 + * @arg @ref LL_MEM_AXISRAM3 + * @arg @ref LL_MEM_AXISRAM4 + * @arg @ref LL_MEM_AXISRAM5 + * @arg @ref LL_MEM_AXISRAM6 + * @arg @ref LL_MEM_AHBSRAM1 + * @arg @ref LL_MEM_AHBSRAM2 + * @arg @ref LL_MEM_BKPSRAM + * @arg @ref LL_MEM_FLEXRAM + * @arg @ref LL_MEM_CACHEAXIRAM + * @arg @ref LL_MEM_VENCRAM + * @retval None + */ +__STATIC_INLINE uint32_t LL_MEM_IsEnabledClockLowPower(uint32_t Memories) +{ + return ((READ_BIT(RCC->MEMLPENR, Memories) == Memories) ? 1UL : 0UL); +} + +/** + * @brief Disable memories clock during Low Power mode. + * @rmtoll MEMLPENCR AXISRAM1LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR AXISRAM2LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR AXISRAM3LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR AXISRAM4LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR AXISRAM5LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR AXISRAM6LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR AHBSRAM1LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR AHBSRAM2LPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR BKPSRAMLPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR FLEXRAMLPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR CACHEAXIRAMLPENC LL_MEM_DisableClockLowPower\n + * MEMLPENCR VENCRAMLPENC LL_MEM_DisableClockLowPower + * @param Memories This parameter can be a combination of the following values: + * @arg @ref LL_MEM_AXISRAM1 + * @arg @ref LL_MEM_AXISRAM2 + * @arg @ref LL_MEM_AXISRAM3 + * @arg @ref LL_MEM_AXISRAM4 + * @arg @ref LL_MEM_AXISRAM5 + * @arg @ref LL_MEM_AXISRAM6 + * @arg @ref LL_MEM_AHBSRAM1 + * @arg @ref LL_MEM_AHBSRAM2 + * @arg @ref LL_MEM_BKPSRAM + * @arg @ref LL_MEM_FLEXRAM + * @arg @ref LL_MEM_CACHEAXIRAM + * @arg @ref LL_MEM_VENCRAM + * @retval None + */ +__STATIC_INLINE void LL_MEM_DisableClockLowPower(uint32_t Memories) +{ + WRITE_REG(RCC->MEMLPENCR, Memories); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENSR GPDMA1ENS LL_AHB1_GRP1_EnableClock\n + * AHB1ENSR ADC12ENS LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB1ENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB1ENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENCR GPDMA1ENC LL_AHB1_GRP1_DisableClock\n + * AHB1ENCR ADC12ENC LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB1ENCR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTSR GPDMA1RSTS LL_AHB1_GRP1_ForceReset\n + * AHB1RSTSR ADC12RSTS LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB1RSTSR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTCR GPDMA1RSTC LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTCR ADC12RSTC LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB1RSTCR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power mode. + * @rmtoll AHB1LPENSR GPDMA1LPENS LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENSR ADC12LPENS LL_AHB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB1LPENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB1LPENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock during Low Power mode is enabled or not . + * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_IsEnabledClockLowPower\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power mode. + * @rmtoll AHB1LPENCR GPDMA1LPENC LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENCR ADC12LPENC LL_AHB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB1LPENCR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENSR RAMCFGENS LL_AHB2_GRP1_EnableClock\n + * AHB2ENSR MDF1ENS LL_AHB2_GRP1_EnableClock\n + * AHB2ENSR ADF1ENS LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB2ENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB2ENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR RAMCFGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR MDF1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR ADF1EN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENCR RAMCFGENC LL_AHB2_GRP1_DisableClock\n + * AHB2ENCR MDF1ENC LL_AHB2_GRP1_DisableClock\n + * AHB2ENCR ADF1ENC LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB2ENCR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTSR RAMCFGRSTS LL_AHB2_GRP1_ForceReset\n + * AHB2RSTSR MDF1RSTS LL_AHB2_GRP1_ForceReset\n + * AHB2RSTSR ADF1RSTS LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB2RSTSR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTCR RAMCFGRSTC LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTCR MDF1RSTC LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTCR ADF1RSTC LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB2RSTCR, Periphs); +} + +/** + * @brief Enable AHB2 peripherals clock during Low Power mode. + * @rmtoll AHB2LPENSR RAMCFGLPENC LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENSR MDF1LPENC LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENSR ADF1LPENC LL_AHB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB2LPENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB2LPENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock during Low Power mode is enabled or not . + * @rmtoll AHB2LPENR RAMCFGLPEN LL_AHB2_GRP1_IsEnabledClockLowPower\n + * AHB2LPENR MDF1LPEN LL_AHB2_GRP1_IsEnabledClockLowPower\n + * AHB2LPENR ADF1LPEN LL_AHB2_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripherals clock during Low Power mode. + * @rmtoll AHB2LPENCR RAMCFGLPENC LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENCR MDF1LPENC LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENCR ADF1LPENC LL_AHB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1 + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB2LPENCR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENSR RNGENS LL_AHB3_GRP1_EnableClock\n + * AHB3ENSR HASHENS LL_AHB3_GRP1_EnableClock\n + * AHB3ENSR CRYPENS LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENSR SAESENS LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENSR PKAENS LL_AHB3_GRP1_EnableClock\n + * AHB3ENSR RIFSCENS LL_AHB3_GRP1_EnableClock\n + * AHB3ENSR RISAFENS LL_AHB3_GRP1_EnableClock\n + * AHB3ENSR IACENS LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC + * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB3ENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB3ENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR HASHEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR CRYPEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR SAESEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR RIFSCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR RISAFEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR IACEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC + * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENCR RNGENC LL_AHB3_GRP1_DisableClock\n + * AHB3ENCR HASHENC LL_AHB3_GRP1_DisableClock\n + * AHB3ENCR CRYPENC LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENCR SAESENC LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENCR PKAENC LL_AHB3_GRP1_DisableClock\n + * AHB3ENCR RIFSCENC LL_AHB3_GRP1_DisableClock\n + * AHB3ENCR RISAFENC LL_AHB3_GRP1_DisableClock\n + * AHB3ENCR IACENC LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC + * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB3ENCR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTSR RNGRSTS LL_AHB3_GRP1_ForceReset\n + * AHB3RSTSR HASHRSTS LL_AHB3_GRP1_ForceReset\n + * AHB3RSTSR CRYPRSTS LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTSR SAESRSTS LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTSR PKARSTS LL_AHB3_GRP1_ForceReset\n + * AHB3RSTSR IACRSTS LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB3RSTSR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTCR RNGRSTC LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTCR HASHRSTC LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTCR CRYPRSTC LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTCR SAESRSTC LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTCR PKARSTC LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTCR IACRSTC LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB3RSTCR, Periphs); +} + +/** + * @brief Enable AHB3 peripherals clock during Low Power mode. + * @rmtoll AHB3LPENSR RNGLPENS LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENSR HASHLPENS LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENSR CRYPLPENS LL_AHB3_GRP1_EnableClockLowPower\n (*) + * AHB3LPENSR SAESLPENS LL_AHB3_GRP1_EnableClockLowPower\n (*) + * AHB3LPENSR PKALPENS LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENSR RIFSCLPENS LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENSR RISAFLPENS LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENSR IACLPENS LL_AHB3_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC + * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB3LPENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB3LPENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock during Low Power mode is enabled or not . + * @rmtoll AHB3LPENR RNGLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n + * AHB3LPENR HASHLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n + * AHB3LPENR CRYPLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n (*) + * AHB3LPENR SAESLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n (*) + * AHB3LPENR PKALPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n + * AHB3LPENR RIFSCLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n + * AHB3LPENR RISAFLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n + * AHB3LPENR IACLPEN LL_AHB3_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC + * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB3 peripherals clock during Low Power mode. + * @rmtoll AHB3LPENCR RNGLPENC LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENCR HASHLPENC LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENCR CRYPLPENC LL_AHB3_GRP1_DisableClockLowPower\n (*) + * AHB3LPENCR SAESLPENC LL_AHB3_GRP1_DisableClockLowPower\n (*) + * AHB3LPENCR PKALPENC LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENCR RIFSCLPENC LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENCR RISAFLPENC LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENCR IACLPENC LL_AHB3_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC + * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF + * @arg @ref LL_AHB3_GRP1_PERIPH_IAC + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB3LPENCR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable AHB4 peripherals clock. + * @rmtoll AHB4ENSR GPIOAENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOBENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOCENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIODENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOEENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOFENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOGENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOHENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIONENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOOENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOPENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR GPIOQENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR PWRENS LL_AHB4_GRP1_EnableClock\n + * AHB4ENSR CRCENS LL_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB4ENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB4ENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIONEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOOEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOPEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOQEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR PWREN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 peripherals clock. + * @rmtoll AHB4ENCR GPIOAENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOBENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOCENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIODENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOEENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOFENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOGENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOHENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIONENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOOENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOPENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR GPIOQENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR PWRENC LL_AHB4_GRP1_DisableClock\n + * AHB4ENCR CRCENC LL_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB4ENCR, Periphs); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll AHB4RSTSR GPIOARSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOBRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOCRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIODRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOERSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOFRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOGRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOHRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIONRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOORSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOPRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR GPIOQRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR CRCRSTS LL_AHB4_GRP1_ForceReset\n + * AHB4RSTSR BKPRAMRSTS LL_AHB4_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB4RSTSR, Periphs); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll AHB4RSTCR GPIOARSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOBRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOCRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIODRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOERSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOFRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOGRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOHRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIONRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOORSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOPRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR GPIOQRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR CRCRSTC LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTCR BKPRAMRSTC LL_AHB4_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB4RSTCR, Periphs); +} + +/** + * @brief Enable AHB4 peripherals clock during Low Power mode. + * @rmtoll AHB4LPENSR GPIOALPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOBLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOCLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIODLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOELPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOFLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOGLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOHLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIONLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOOLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOPLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR GPIOQLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR CRCLPENS LL_AHB4_GRP1_EnableClockLowPower\n + * AHB4LPENSR BKPRAMLPENS LL_AHB4_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB4LPENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB4LPENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock during Low Power mode is enabled or not . + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIONLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOOLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOPLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR GPIOQLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR PWRLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 peripherals clock during Low Power mode. + * @rmtoll AHB4LPENCR GPIOALPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOBLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOCLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIODLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOELPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOFLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOGLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOHLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIONLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOOLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOPLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR GPIOQLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR PWRLPENC LL_AHB4_GRP1_DisableClockLowPower\n + * AHB4LPENCR CRCLPENC LL_AHB4_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB4LPENCR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB5 AHB5 + * @{ + */ + +/** + * @brief Enable AHB5 peripherals clock. + * @rmtoll AHB5ENSR HPDMA1ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR DMA2DENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR JPEGENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR FMCENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR XSPI1ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR PSSIENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR SDMMC2ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR SDMMC1ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR XSPI2ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR XSPIMENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR MCE1ENS LL_AHB5_GRP1_EnableClock\n (*) + * AHB5ENSR MCE2ENS LL_AHB5_GRP1_EnableClock\n (*) + * AHB5ENSR MCE3ENS LL_AHB5_GRP1_EnableClock\n (*) + * AHB5ENSR XSPI3ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR MCE4ENS LL_AHB5_GRP1_EnableClock\n (*) + * AHB5ENSR GFXMMUENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR GPU2DENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR ETH1MACENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR ETH1TXENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR ETH1RXENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR ETH1ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR OTG1ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR OTGPHY1ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR OTGPHY2ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR OTG2ENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR CACHEAXIENS LL_AHB5_GRP1_EnableClock\n + * AHB5ENSR NPUENS LL_AHB5_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB5ENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB5ENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB5 peripheral clock is enabled or not + * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR DMA2DEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR JPEGEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR FMCEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR XSPI1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR PSSIEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR SDMMC2EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR SDMMC1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR XSPI2EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR XSPIMEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR MCE1EN LL_AHB5_GRP1_IsEnabledClock\n (*) + * AHB5ENR MCE2EN LL_AHB5_GRP1_IsEnabledClock\n (*) + * AHB5ENR MCE3EN LL_AHB5_GRP1_IsEnabledClock\n (*) + * AHB5ENR XSPI3EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR MCE4EN LL_AHB5_GRP1_IsEnabledClock\n (*) + * AHB5ENR GFXMMUEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR GPU2DEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR ETH1MACEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR ETH1TXEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR ETH1RXEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR ETH1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR OTG1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR OTGPHY1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR OTGPHY2EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR OTG2EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR CACHEAXIEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR NPUEN LL_AHB5_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB5 peripherals clock. + * @rmtoll AHB5ENCR HPDMA1ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR DMA2DENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR JPEGENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR FMCENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR XSPI1ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR PSSIENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR SDMMC2ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR SDMMC1ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR XSPI2ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR XSPIMENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR MCE1ENC LL_AHB5_GRP1_DisableClock\n (*) + * AHB5ENCR MCE2ENC LL_AHB5_GRP1_DisableClock\n (*) + * AHB5ENCR MCE3ENC LL_AHB5_GRP1_DisableClock\n (*) + * AHB5ENCR XSPI3ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR MCE4ENC LL_AHB5_GRP1_DisableClock\n (*) + * AHB5ENCR GFXMMUENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR GPU2DENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR ETH1MACENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR ETH1TXENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR ETH1RXENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR ETH1ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR OTG1ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR OTGPHY1ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR OTGPHY2ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR OTG2ENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR CACHEAXIENC LL_AHB5_GRP1_DisableClock\n + * AHB5ENCR NPUENC LL_AHB5_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB5ENCR, Periphs); +} + +/** + * @brief Force AHB5 peripherals reset. + * @rmtoll AHB5RSTSR HPDMA1RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR DMA2DRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR JPEGRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR FMCRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR XSPI1RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR PSSIRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR SDMMC2RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR SDMMC1RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR XSPI2RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR XSPIMRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR XSPI3RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR GFXMMURSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR GPU2DRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR OTG1PHYCTLRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR OTG2PHYCTLRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR ETH1RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR OTG1RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR OTGPHY1RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR OTGPHY2RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR OTG2RSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR CACHEAXIRSTS LL_AHB5_GRP1_ForceReset\n + * AHB5RSTSR NPURSTS LL_AHB5_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1PHYCTL + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2PHYCTL + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB5RSTSR, Periphs); +} + +/** + * @brief Release AHB5 peripherals reset. + * @rmtoll AHB5RSTCR HPDMA1RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR DMA2DRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR JPEGRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR FMCRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR XSPI1RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR PSSIRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR SDMMC2RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR SDMMC1RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR XSPI2RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR XSPIMRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR XSPI3RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR GFXMMURSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR GPU2DRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR OTG1PHYCTLRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR OTG2PHYCTLRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR ETH1RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR OTG1RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR OTGPHY1RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR OTGPHY2RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR OTG2RSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR CACHEAXIRSTC LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTCR NPURSTS LL_AHB5_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1PHYCTL + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2PHYCTL + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB5RSTCR, Periphs); +} + +/** + * @brief Enable AHB5 peripherals clock during Low Power mode. + * @rmtoll AHB5LPENSR HPDMA1LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR DMA2DLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR JPEGLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR FMCLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR XSPI1LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR PSSILPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR SDMMC2LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR SDMMC1LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR XSPI2LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR XSPIMLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR MCE1LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*) + * AHB5LPENSR MCE2LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*) + * AHB5LPENSR MCE3LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*) + * AHB5LPENSR XSPI3LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR MCE4LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*) + * AHB5LPENSR GFXMMULPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR GPU2DLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR ETH1MACLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR ETH1TXLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR ETH1RXLPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR ETH1LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR OTG1LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR OTGPHY1LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR OTGPHY2LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR OTG2LPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR CACHEAXILPENS LL_AHB5_GRP1_EnableClockLowPower\n + * AHB5LPENSR NPULPENS LL_AHB5_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->AHB5LPENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->AHB5LPENR); + (void)tmpreg; +} + +/** + * @brief Check if AHB5 peripheral clock during Low Power mode is enabled or not . + * @rmtoll AHB5LPENR HPDMA1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR DMA2DLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR JPEGLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR FMCLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR XSPI1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR PSSILPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR SDMMC2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR SDMMC1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR XSPI2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR XSPIMLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR MCE1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*) + * AHB5LPENR MCE2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*) + * AHB5LPENR MCE3LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*) + * AHB5LPENR XSPI3LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR MCE4LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*) + * AHB5LPENR GFXMMULPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR GPU2DLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR ETH1MACLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR ETH1TXLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR ETH1RXLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR ETH1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR OTG1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR OTGPHY1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR OTGPHY2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR OTG2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR CACHEAXILPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n + * AHB5LPENR NPULPEN LL_AHB5_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB5LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB5 peripherals clock during Low Power mode. + * @rmtoll AHB5LPENCR HPDMA1LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR DMA2DLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR JPEGLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR FMCLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR XSPI1LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR PSSILPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR SDMMC2LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR SDMMC1LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR XSPI2LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR XSPIMLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR MCE1LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*) + * AHB5LPENCR MCE2LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*) + * AHB5LPENCR MCE3LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*) + * AHB5LPENCR XSPI3LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR MCE4LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*) + * AHB5LPENCR GFXMMULPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR GPU2DLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR ETH1MACLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR ETH1TXLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR ETH1RXLPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR ETH1LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR OTG1LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR OTGPHY1LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR OTGPHY2LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR OTG2LPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR CACHEAXILPENC LL_AHB5_GRP1_DisableClockLowPower\n + * AHB5LPENCR NPULPENC LL_AHB5_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1 + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1 + * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2 + * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI + * @arg @ref LL_AHB5_GRP1_PERIPH_NPU + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->AHB5LPENCR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENSR1 TIM2ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM3ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM4ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM5ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM6ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM7ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM12ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM13ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM14ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 LPTIM1ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 WWDGENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM10ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 TIM11ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 SPI2ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 SPI3ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 SPDIFRX1ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 USART2ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 USART3ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 UART4ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 UART5ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 I2C1ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 I2C2ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 I2C3ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 I3C1ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 I3C2ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 UART7ENS LL_APB1_GRP1_EnableClock\n + * APB1ENSR1 UART8ENS LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB1ENSR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB1ENR1); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM10EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM11EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPDIFRX1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I3C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I3C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART8EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENCR1 TIM2ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM3ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM4ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM5ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM6ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM7ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM12ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM13ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM14ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 LPTIM1ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM10ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 TIM11ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 SPI2ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 SPI3ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 SPDIFRX1ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 USART2ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 USART3ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 UART4ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 UART5ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 I2C1ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 I2C2ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 I2C3ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 I3C1ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 I3C2ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 UART7ENC LL_APB1_GRP1_DisableClock\n + * APB1ENCR1 UART8ENC LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1ENCR1, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTSR1 TIM2RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM3RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM4RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM5RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM6RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM7RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM12RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM13RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM14RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 LPTIM1RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM10RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 TIM11RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 SPI2RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 SPI3RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 SPDIFRX1RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 USART2RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 USART3RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 UART4RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 UART5RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 I2C1RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 I2C2RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 I2C3RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 I3C1RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 I3C2RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 UART7RSTS LL_APB1_GRP1_ForceReset\n + * APB1RSTSR1 UART8RSTS LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1RSTSR1, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTCR1 TIM2RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM3RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM4RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM5RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM6RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM7RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM12RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM13RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM14RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 LPTIM1RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM10RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 TIM11RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 SPI2RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 SPI3RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 SPDIFRX1RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 USART2RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 USART3RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 UART4RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 UART5RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 I2C1RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 I2C2RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 I2C3RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 I3C1RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 I3C2RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 UART7RSTC LL_APB1_GRP1_ReleaseReset\n + * APB1RSTCR1 UART8RSTC LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1RSTCR1, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power mode. + * @rmtoll APB1LPENSR1 TIM2LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM3LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM4LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM5LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM6LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM7LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM12LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM13LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM14LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 LPTIM1LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 WWDGLPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM10LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 TIM11LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 SPI2LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 SPI3LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 SPDIFRX1LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 USART2LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 USART3LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 UART4LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 UART5LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 I2C1LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 I2C2LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 I2C3LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 I3C1LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 I3C2LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 UART7LPENS LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENSR1 UART8LPENS LL_APB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB1LPENSR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB1LPENR1); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock during Low Power mode is enabled or not . + * @rmtoll APB1LPENR1 TIM2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM4LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM5LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM6LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM7LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM12LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM13LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM14LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 LPTIM1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 WWDGLPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM10LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 TIM11LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 SPI2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 SPI3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 SPDIFRX1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 USART2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 USART3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 UART4LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 UART5LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 I2C1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 I2C2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 I2C3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 I3C1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 I3C2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 UART7LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n + * APB1LPENR1 UART8LPEN LL_APB1_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1LPENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock during Low Power mode. + * @rmtoll APB1LPENCR1 TIM2LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM3LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM4LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM5LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM6LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM7LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM12LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM13LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM14LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 LPTIM1LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 WWDGLPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM10LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 TIM11LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 SPI2LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 SPI3LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 SPDIFRX1LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 USART2LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 USART3LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 UART4LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 UART5LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 I2C1LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 I2C2LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 I2C3LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 I3C1LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 I3C2LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 UART7LPENC LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENCR1 UART8LPENC LL_APB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1LPENCR1, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENSR2 MDIOSENS LL_APB1_GRP2_EnableClock\n + * APB1ENSR2 FDCANENS LL_APB1_GRP2_EnableClock\n + * APB1ENSR2 UCPD1ENS LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB1ENSR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB1ENR2); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR2 MDIOSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 FDCANEN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENCR2 MDIOSENC LL_APB1_GRP2_DisableClock\n + * APB1ENCR2 FDCANENC LL_APB1_GRP2_DisableClock\n + * APB1ENCR2 UCPD1ENC LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1ENCR2, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTSR2 MDIOSRSTS LL_APB1_GRP2_ForceReset\n + * APB1RSTSR2 FDCANRSTS LL_APB1_GRP2_ForceReset\n + * APB1RSTSR2 UCPD1RSTS LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1RSTSR2, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTCR2 MDIOSRSTC LL_APB1_GRP2_ReleaseReset\n + * APB1RSTCR2 FDCANRSTC LL_APB1_GRP2_ReleaseReset\n + * APB1RSTCR2 UCPD1RSTC LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1RSTCR2, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power mode. + * @rmtoll APB1LPENSR2 MDIOSLPENS LL_APB1_GRP2_EnableClockLowPower\n + * APB1LPENSR2 FDCANLPENS LL_APB1_GRP2_EnableClockLowPower\n + * APB1LPENSR2 UCPD1LPENS LL_APB1_GRP2_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB1LPENSR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB1LPENR2); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock during Low Power mode is enabled or not . + * @rmtoll APB1LPENR2 MDIOSLPEN LL_APB1_GRP2_IsEnabledClockLowPower\n + * APB1LPENR2 FDCANLPEN LL_APB1_GRP2_IsEnabledClockLowPower\n + * APB1LPENR2 UCPD1LPEN LL_APB1_GRP2_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1LPENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock during Low Power mode. + * @rmtoll APB1LPENCR2 MDIOSLPENC LL_APB1_GRP2_DisableClockLowPower\n + * APB1LPENCR2 FDCANLPENC LL_APB1_GRP2_DisableClockLowPower\n + * APB1LPENCR2 UCPD1LPENC LL_APB1_GRP2_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->APB1LPENCR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENSR TIM1ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR TIM8ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR USART1ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR USART6ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR UART9ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR USART10ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR SPI1ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR SPI4ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR TIM18ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR TIM15ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR TIM16ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR TIM17ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR TIM9ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR SPI5ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR SAI1ENS LL_APB2_GRP1_EnableClock\n + * APB2ENSR SAI2ENS LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB2ENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB2ENR); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM18EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENCR TIM1ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR TIM8ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR USART1ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR USART6ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR UART9ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR USART10ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR SPI1ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR SPI4ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR TIM18ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR TIM15ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR TIM16ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR TIM17ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR TIM9ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR SPI5ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR SAI1ENC LL_APB2_GRP1_DisableClock\n + * APB2ENCR SAI2ENC LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->APB2ENCR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTSR TIM1RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR TIM8RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR USART1RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR USART6RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR UART9RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR USART10RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR SPI1RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR SPI4RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR TIM18RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR TIM15RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR TIM16RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR TIM17RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR TIM9RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR SPI5RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR SAI1RSTS LL_APB2_GRP1_ForceReset\n + * APB2RSTSR SAI2RSTS LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB2RSTSR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTCR TIM1RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR TIM8RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR USART1RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR USART6RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR UART9RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR USART10RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR SPI1RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR SPI4RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR TIM18RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR TIM15RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR TIM16RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR TIM17RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR TIM9RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR SPI5RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR SAI1RSTC LL_APB2_GRP1_ReleaseReset\n + * APB2RSTCR SAI2RSTC LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB2RSTCR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power mode. + * @rmtoll APB2LPENSR TIM1LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR TIM8LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR USART1LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR USART6LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR UART9LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR USART10LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR SPI1LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR SPI4LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR TIM18LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR TIM15LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR TIM16LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR TIM17LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR TIM9LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR SPI5LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR SAI1LPENS LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENSR SAI2LPENS LL_APB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB2LPENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB2LPENR); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock during Low Power mode is enabled or not . + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR UART9LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR USART10LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR TIM18LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock during Low Power mode. + * @rmtoll APB2LPENCR TIM1LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR TIM8LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR USART1LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR USART6LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR UART9LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR USART10LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR SPI1LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR SPI4LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR TIM18LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR TIM15LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR TIM16LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR TIM17LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR TIM9LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR SPI5LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR SAI1LPENC LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENCR SAI2LPENC LL_APB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM18 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->APB2LPENCR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable APB4 peripherals clock. + * @rmtoll APB4ENSR1 HDPENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 LPUART1ENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 SPI6ENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 I2C4ENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 LPTIM2ENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 LPTIM3ENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 LPTIM4ENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 LPTIM5ENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 VREFBUFENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 RTCENS LL_APB4_GRP1_EnableClock\n + * APB4ENSR1 RTCAPBENS LL_APB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTC + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB4ENSR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB4ENR1); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR1 HDPEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 LPUART1EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 SPI6EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 I2C4EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 VREFBUFEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 RTCEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR1 RTCAPBEN LL_APB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTC + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4ENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB4 peripherals clock. + * @rmtoll APB4ENCR1 HDPENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 LPUART1ENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 SPI6ENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 I2C4ENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 LPTIM2ENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 LPTIM3ENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 LPTIM4ENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 LPTIM5ENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 VREFBUFENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 RTCENC LL_APB4_GRP1_DisableClock\n + * APB4ENCR1 RTCAPBENC LL_APB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTC + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4ENCR1, Periphs); +} + +/** + * @brief Force APB4 peripherals reset. + * @rmtoll APB4RSTSR1 HDPRSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 LPUART1RSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 SPI6RSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 I2C4RSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 LPTIM2RSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 LPTIM3RSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 LPTIM4RSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 LPTIM5RSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 VREFBUFRSTS LL_APB4_GRP1_ForceReset\n + * APB4RSTSR1 RTCAPBRSTS LL_APB4_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4RSTSR1, Periphs); +} + +/** + * @brief Release APB4 peripherals reset. + * @rmtoll APB4RSTCR1 HDPRSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 LPUART1RSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 SPI6RSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 I2C4RSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 LPTIM2RSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 LPTIM3RSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 LPTIM4RSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 LPTIM5RSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 VREFBUFRSTC LL_APB4_GRP1_ReleaseReset\n + * APB4RSTCR1 RTCAPBRSTC LL_APB4_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4RSTCR1, Periphs); +} + +/** + * @brief Enable APB4 peripherals clock during Low Power mode. + * @rmtoll APB4LPENSR1 HDPLPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 LPUART1LPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 SPI6LPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 I2C4LPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 LPTIM2LPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 LPTIM3LPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 LPTIM4LPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 LPTIM5LPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 VREFBUFLPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 RTCLPENS LL_APB4_GRP1_EnableClockLowPower\n + * APB4LPENSR1 RTCAPBLPENS LL_APB4_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTC + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB4LPENSR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB4LPENR1); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock during Low Power mode is enabled or not . + * @rmtoll APB4LPENR1 HDPLPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 LPUART1LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 SPI6LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 I2C4LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 LPTIM2LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 LPTIM3LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 LPTIM4LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 LPTIM5LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 VREFBUFLPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 RTCLPEN LL_APB4_GRP1_IsEnabledClockLowPower\n + * APB4LPENR1 RTCAPBLPEN LL_APB4_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTC + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4LPENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB4 peripherals clock during Low Power mode. + * @rmtoll APB4LPENCR1 HDPLPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 LPUART1LPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 SPI6LPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 I2C4LPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 LPTIM2LPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 LPTIM3LPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 LPTIM4LPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 LPTIM5LPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 VREFBUFLPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 RTCLPENC LL_APB4_GRP1_DisableClockLowPower\n + * APB4LPENCR1 RTCAPBLPENC LL_APB4_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_HDP + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_RTC + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4LPENCR1, Periphs); +} + +/** + * @brief Enable APB4 peripherals clock. + * @rmtoll APB4ENSR2 SYSCFGENS LL_APB4_GRP2_EnableClock\n + * APB4ENSR2 BSECENS LL_APB4_GRP2_EnableClock\n + * APB4ENSR2 DTSENS LL_APB4_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_BSEC + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB4ENSR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB4ENR2); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR2 SYSCFGEN LL_APB4_GRP2_IsEnabledClock\n + * APB4ENR2 BSECEN LL_APB4_GRP2_IsEnabledClock\n + * APB4ENR2 DTSEN LL_APB4_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_BSEC + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4ENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB4 peripherals clock. + * @rmtoll APB4ENCR2 SYSCFGENC LL_APB4_GRP2_DisableClock\n + * APB4ENCR2 BSECENC LL_APB4_GRP2_DisableClock\n + * APB4ENCR2 DTSENC LL_APB4_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_BSEC + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP2_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4ENCR2, Periphs); +} + +/** + * @brief Force APB4 peripherals reset. + * @rmtoll APB4RSTR2 SYSCFGRSTS LL_APB4_GRP2_ForceReset\n + * APB4RSTR2 DTSRSTS LL_APB4_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP2_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4RSTSR2, Periphs); +} + +/** + * @brief Release APB4 peripherals reset. + * @rmtoll APB4RSTCR2 SYSCFGRSTC LL_APB4_GRP2_ReleaseReset\n + * APB4RSTCR2 DTSRSTC LL_APB4_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP2_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4RSTCR2, Periphs); +} + +/** + * @brief Enable APB4 peripherals clock during Low Power mode. + * @rmtoll APB4LPENSR2 SYSCFGLPENS LL_APB4_GRP2_EnableClockLowPower\n + * APB4LPENSR2 BSECLPENS LL_APB4_GRP2_EnableClockLowPower\n + * APB4LPENSR2 DTSLPENS LL_APB4_GRP2_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_BSEC + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP2_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB4LPENSR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB4LPENR2); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock during Low Power mode is enabled or not . + * @rmtoll APB4LPENR2 SYSCFGLPEN LL_APB4_GRP2_IsEnabledClockLowPower\n + * APB4LPENR2 BSECLPEN LL_APB4_GRP2_IsEnabledClockLowPower\n + * APB4LPENR2 DTSLPEN LL_APB4_GRP2_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_BSEC + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4LPENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB4 peripherals clock during Low Power mode. + * @rmtoll APB4LPENCR2 SYSCFGLPENC LL_APB4_GRP2_DisableClockLowPower\n + * APB4LPENCR2 BSECLPENC LL_APB4_GRP2_DisableClockLowPower\n + * APB4LPENCR2 DTSLPENC LL_APB4_GRP2_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP2_PERIPH_BSEC + * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP2_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP2_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->APB4LPENCR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB5 APB5 + * @{ + */ + +/** + * @brief Enable APB5 peripherals clock. + * @rmtoll APB5ENSR LTDCENS LL_APB5_GRP1_EnableClock\n + * APB5ENSR DCMIPPENS LL_APB5_GRP1_EnableClock\n + * APB5ENSR GFXTIMENS LL_APB5_GRP1_EnableClock\n + * APB5ENSR VENCENS LL_APB5_GRP1_EnableClock\n (*) + * APB5ENSR CSIENS LL_APB5_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB5ENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB5ENR); + (void)tmpreg; +} + +/** + * @brief Check if APB5 peripheral clock is enabled or not + * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_IsEnabledClock\n + * APB5ENR DCMIPPEN LL_APB5_GRP1_IsEnabledClock\n + * APB5ENR GFXTIMEN LL_APB5_GRP1_IsEnabledClock\n + * APB5ENR VENCEN LL_APB5_GRP1_IsEnabledClock\n (*) + * APB5ENR CSIEN LL_APB5_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB5ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB5 peripherals clock. + * @rmtoll APB5ENCR LTDCENC LL_APB5_GRP1_DisableClock\n + * APB5ENCR DCMIPPENC LL_APB5_GRP1_DisableClock\n + * APB5ENCR GFXTIMENC LL_APB5_GRP1_DisableClock\n + * APB5ENCR VENCENC LL_APB5_GRP1_DisableClock\n (*) + * APB5ENCR CSIENC LL_APB5_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs) +{ + WRITE_REG(RCC->APB5ENCR, Periphs); +} + +/** + * @brief Force APB5 peripherals reset. + * @rmtoll APB5RSTSR LTDCRSTS LL_APB5_GRP1_ForceReset\n + * APB5RSTSR DCMIPPRSTS LL_APB5_GRP1_ForceReset\n + * APB5RSTSR GFXTIMRSTS LL_APB5_GRP1_ForceReset\n + * APB5RSTSR VENCRSTS LL_APB5_GRP1_ForceReset\n (*) + * APB5RSTSR CSIRSTS LL_APB5_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB5RSTSR, Periphs); +} + +/** + * @brief Release APB5 peripherals reset. + * @rmtoll APB5RSTCR LTDCRSTC LL_APB5_GRP1_ReleaseReset\n + * APB5RSTCR DCMIPPRSTC LL_APB5_GRP1_ReleaseReset\n + * APB5RSTCR GFXTIMRSTC LL_APB5_GRP1_ReleaseReset\n + * APB5RSTCR VENCRSTC LL_APB5_GRP1_ReleaseReset\n (*) + * APB5RSTCR CSIRSTC LL_APB5_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs) +{ + WRITE_REG(RCC->APB5RSTCR, Periphs); +} + +/** + * @brief Enable APB5 peripherals clock during Low Power mode. + * @rmtoll APB5LPENSR LTDCLPENS LL_APB5_GRP1_EnableClockLowPower\n + * APB5LPENSR DCMIPPLPENS LL_APB5_GRP1_EnableClockLowPower\n + * APB5LPENSR GFXTIMLPENS LL_APB5_GRP1_EnableClockLowPower\n + * APB5LPENSR VENCLPENS LL_APB5_GRP1_EnableClockLowPower\n (*) + * APB5LPENSR CSILPENS LL_APB5_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->APB5LPENSR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_REG(RCC->APB5LPENR); + (void)tmpreg; +} + +/** + * @brief Check if APB5 peripheral clock during Low Power mode is enabled or not . + * @rmtoll APB5LPENR LTDCLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n + * APB5LPENR DCMIPPLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n + * APB5LPENR GFXTIMLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n + * APB5LPENR VENCLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n (*) + * APB5LPENR CSILPEN LL_APB5_GRP1_IsEnabledClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB5LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB5 peripherals clock during Low Power mode. + * @rmtoll APB5LPENCR LTDCLPENC LL_APB5_GRP1_DisableClockLowPower\n + * APB5LPENCR DCMIPPLPENC LL_APB5_GRP1_DisableClockLowPower\n + * APB5LPENCR GFXTIMLPENC LL_APB5_GRP1_DisableClockLowPower\n + * APB5LPENCR VENCLPENC LL_APB5_GRP1_DisableClockLowPower\n (*) + * APB5LPENCR CSILPENC LL_APB5_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_CSI + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC + * @arg @ref LL_APB5_GRP1_PERIPH_VENC + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + WRITE_REG(RCC->APB5LPENCR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_MISC MISC + * @{ + */ + +/** + * @brief Enable miscellaneous clock. + * @rmtoll MISCENSR DBGENS LL_MISC_EnableClock\n + * MISCENSR MCO1ENS LL_MISC_EnableClock\n + * MISCENSR MCO2ENS LL_MISC_EnableClock\n + * MISCENSR XSPIPHYCOMPENS LL_MISC_EnableClock\n + * MISCENSR PERENS LL_MISC_EnableClock + * @param Misc This parameter can be a combination of the following values: + * @arg @ref LL_DBG + * @arg @ref LL_MCO1 + * @arg @ref LL_MCO2 + * @arg @ref LL_XSPIPHYCOMP + * @arg @ref LL_PER + * @retval None + */ +__STATIC_INLINE void LL_MISC_EnableClock(uint32_t Misc) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->MISCENSR, Misc); + /* Delay after an RCC miscellaneous clock enabling */ + tmpreg = READ_REG(RCC->MISCENR); + (void)tmpreg; +} + +/** + * @brief Check if miscellaneous clock is enabled or not + * @rmtoll MISCENR DBGEN LL_MISC_IsEnabledClock\n + * MISCENR MCO1EN LL_MISC_IsEnabledClock\n + * MISCENR MCO2EN LL_MISC_IsEnabledClock\n + * MISCENR XSPIPHYCOMPEN LL_MISC_IsEnabledClock\n + * MISCENR PEREN LL_MISC_IsEnabledClock + * @param Misc This parameter can be a combination of the following values: + * @arg @ref LL_DBG + * @arg @ref LL_MCO1 + * @arg @ref LL_MCO2 + * @arg @ref LL_XSPIPHYCOMP + * @arg @ref LL_PER + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_MISC_IsEnabledClock(uint32_t Misc) +{ + return ((READ_BIT(RCC->MISCENR, Misc) == Misc) ? 1UL : 0UL); +} + +/** + * @brief Disable miscellaneous clock. + * @rmtoll MISCENCR DBGENC LL_MISC_DisableClock\n + * MISCENCR MCO1ENC LL_MISC_DisableClock\n + * MISCENCR MCO2ENC LL_MISC_DisableClock\n + * MISCENCR XSPIPHYCOMPENC LL_MISC_DisableClock\n + * MISCENCR PERENC LL_MISC_DisableClock + * @param Misc This parameter can be a combination of the following values: + * @arg @ref LL_DBG + * @arg @ref LL_MCO1 + * @arg @ref LL_MCO2 + * @arg @ref LL_XSPIPHYCOMP + * @arg @ref LL_PER + * @retval None + */ +__STATIC_INLINE void LL_MISC_DisableClock(uint32_t Misc) +{ + WRITE_REG(RCC->MISCENCR, Misc); +} + +/** + * @brief Force miscellaneous reset. + * @rmtoll MISCRSTSR DBGRSTS LL_MISC_ForceReset\n + * MISCRSTSR XSPIPHY1RSTS LL_MISC_ForceReset\n + * MISCRSTSR XSPIPHY2RSTS LL_MISC_ForceReset\n + * MISCRSTSR SDMMC1DLLRSTS LL_MISC_ForceReset\n + * MISCRSTSR SDMMC2DLLRSTS LL_MISC_ForceReset + * @param Misc This parameter can be a combination of the following values: + * @arg @ref LL_DBG + * @arg @ref LL_XSPIPHY1 + * @arg @ref LL_XSPIPHY2 + * @arg @ref LL_SDMMC1DLL + * @arg @ref LL_SDMMC2DLL + * @retval None + */ +__STATIC_INLINE void LL_MISC_ForceReset(uint32_t Misc) +{ + WRITE_REG(RCC->MISCRSTSR, Misc); +} + +/** + * @brief Release miscellaneous reset. + * @rmtoll MISCRSTCR DBGRSTC LL_MISC_ReleaseReset\n + * MISCRSTCR XSPIPHY1RSTC LL_MISC_ReleaseReset\n + * MISCRSTCR XSPIPHY2RSTC LL_MISC_ReleaseReset\n + * MISCRSTCR SDMMC1DLLRSTC LL_MISC_ReleaseReset\n + * MISCRSTCR SDMMC2DLLRSTC LL_MISC_ReleaseReset + * @param Misc This parameter can be a combination of the following values: + * @arg @ref LL_DBG + * @arg @ref LL_XSPIPHY1 + * @arg @ref LL_XSPIPHY2 + * @arg @ref LL_SDMMC1DLL + * @arg @ref LL_SDMMC2DLL + * @retval None + */ +__STATIC_INLINE void LL_MISC_ReleaseReset(uint32_t Misc) +{ + WRITE_REG(RCC->MISCRSTCR, Misc); +} + +/** + * @brief Enable bus clock during Low Power mode. + * @rmtoll MISCLPENSR DBGLPENS LL_MISC_EnableClockLowPower\n + * MISCLPENSR XSPIPHYCOMPLPENS LL_MISC_EnableClockLowPower\n + * MISCLPENSR PERLPENS LL_MISC_EnableClockLowPower + * @param Misc This parameter can be a combination of the following values: + * @arg @ref LL_DBG + * @arg @ref LL_XSPIPHYCOMP + * @arg @ref LL_PER + * @retval None + */ +__STATIC_INLINE void LL_MISC_EnableClockLowPower(uint32_t Misc) +{ + __IO uint32_t tmpreg; + WRITE_REG(RCC->MISCLPENSR, Misc); + /* Delay after an RCC miscellaneous clock enabling */ + tmpreg = READ_REG(RCC->MISCLPENR); + (void)tmpreg; +} + +/** + * @brief Disable bus clock during Low Power mode. + * @rmtoll MISCLPENCR DBGLPENC LL_MISC_DisableClockLowPower\n + * MISCLPENCR XSPIPHYCOMPLPENC LL_MISC_DisableClockLowPower\n + * MISCLPENCR PERLPENC LL_MISC_DisableClockLowPower + * @param Misc This parameter can be a combination of the following values: + * @arg @ref LL_DBG + * @arg @ref LL_XSPIPHYCOMP + * @arg @ref LL_PER + * @retval None + */ +__STATIC_INLINE void LL_MISC_DisableClockLowPower(uint32_t Misc) +{ + WRITE_REG(RCC->MISCLPENCR, Misc); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_LL_BUS_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_cortex.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_cortex.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_cortex.h (revision 16) @@ -0,0 +1,1482 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + (+) API to enable and disable the MPU secure and non-secure + (+) API to configure the region of MPU secure and non-secure + (+) API to configure the attributes region of MPU secure and non-secure + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_CORTEX_H +#define STM32N6xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes + * @{ + */ +/* Register MPU_RBAR (Cortex-M55) : bits [4:0] */ +#define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK CORTEX LL SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0U /*!< AHB clock divided by 8 selected as SysTick + clock source */ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick + clock source */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT CORTEX LL Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +#define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes + * @{ + */ +#define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ + +#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ +#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ +#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ + +#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ +#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ + +#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ +#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ +#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ +#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable + * @{ + */ +#define LL_MPU_REGION_ENABLE 1U +#define LL_MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable + * @{ + */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes + * @{ + */ +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0U +#define LL_MPU_REGION_NUMBER1 1U +#define LL_MPU_REGION_NUMBER2 2U +#define LL_MPU_REGION_NUMBER3 3U +#define LL_MPU_REGION_NUMBER4 4U +#define LL_MPU_REGION_NUMBER5 5U +#define LL_MPU_REGION_NUMBER6 6U +#define LL_MPU_REGION_NUMBER7 7U +#define LL_MPU_REGION_NUMBER8 8U +#define LL_MPU_REGION_NUMBER9 9U +#define LL_MPU_REGION_NUMBER10 10U +#define LL_MPU_REGION_NUMBER11 11U +#define LL_MPU_REGION_NUMBER12 12U +#define LL_MPU_REGION_NUMBER13 13U +#define LL_MPU_REGION_NUMBER14 14U +#define LL_MPU_REGION_NUMBER15 15U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index + * @{ + */ +#define LL_MPU_ATTRIBUTES_NUMBER0 0U +#define LL_MPU_ATTRIBUTES_NUMBER1 1U +#define LL_MPU_ATTRIBUTES_NUMBER2 2U +#define LL_MPU_ATTRIBUTES_NUMBER3 3U +#define LL_MPU_ATTRIBUTES_NUMBER4 4U +#define LL_MPU_ATTRIBUTES_NUMBER5 5U +#define LL_MPU_ATTRIBUTES_NUMBER6 6U +#define LL_MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK CORTEX LL SYSTICK + * @brief CORTEX SYSTICK LL module driver + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source); +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture version + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xF for Cortex-M55 ("ARMv8-M with Main Extension") + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xD22 for Cortex-M55 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Force any outstanding transfers to complete before enabling MPU */ + + /* Enable the MPU */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** + * @brief Enable non-secure MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Force any outstanding transfers to complete before enabling MPU */ + /* Enable the MPU */ + MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} +#endif /* MPU_NS */ + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable MPU_NS */ + WRITE_REG(MPU->CTRL, 0U); + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** + * @brief Disable the non-secure MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable_NS(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable MPU_NS */ + WRITE_REG(MPU_NS->CTRL, 0U); + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} +#endif /* MPU_NS */ + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +#ifdef MPU_NS +/** + * @brief Check if non-secure MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void) +{ + return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} +#endif /* MPU_NS */ + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if MPU region is enabled or not + * @rmtoll MPU_RNR EN LL_MPU_IsEnabledRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Return MPU region status */ + return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} + +#ifdef MPU_NS +/** + * @brief Enable a non-secure MPU region + * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if non-secure MPU region is enabled or not + * @rmtoll MPU_RNR EN LL_MPU_IsEnabledRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Return non-secure MPU region status */ + return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} +#endif /* MPU_NS */ + +/** + * @brief Disable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RLAR EN LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#ifdef MPU_NS +/** + * @brief Disable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n + * MPU_RLAR EN LL_MPU_DisableRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* MPU_NS */ + +/** + * @brief Configure and enable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR BASE LL_MPU_ConfigRegion\n + * MPU_RLAR LIMIT LL_MPU_ConfigRegion\n + * MPU_RBAR XN LL_MPU_ConfigRegion\n + * MPU_RBAR AP LL_MPU_ConfigRegion\n + * MPU_RBAR SH LL_MPU_ConfigRegion\n + * MPU_RLAR EN LL_MPU_ConfigRegion\n + * MPU_RLAR AttrX LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, + uint32_t LimitAddress) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Set region base address and region access attributes */ + WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); +} + +#ifdef MPU_NS +/** + * @brief Configure and enable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n + * MPU_RBAR BASE LL_MPU_ConfigRegion_NS\n + * MPU_RLAR LIMIT LL_MPU_ConfigRegion_NS\n + * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n + * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n + * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n + * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n + * MPU_RLAR AttrX LL_MPU_ConfigRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, + uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set region base address and region access attributes */ + WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); +} +#endif /* MPU_NS */ + +/** + * @brief Configure a MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n + * MPU_RBAR BASE LL_MPU_ConfigRegionAddress\n + * MPU_RLAR LIMIT LL_MPU_ConfigRegionAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Modify region base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Modify region limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +#ifdef MPU_NS +/** + * @brief Configure a non-secure MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n + * MPU_RBAR BASE LL_MPU_ConfigRegionAddress_NS\n + * MPU_RLAR LIMIT LL_MPU_ConfigRegionAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} +#endif /* MPU_NS */ + +/** + * @brief Configure a MPU attributes index + * @rmtoll MPU_MAIR0 AttrX LL_MPU_ConfigAttributes\n + * MPU_MAIR1 AttrX LL_MPU_ConfigAttributes + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0 accordingly */ + MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1 accordingly */ + MODIFY_REG(MPU->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} + +#ifdef MPU_NS +/** + * @brief Configure a non-secure MPU attributes index + * @rmtoll MPU_MAIR0 AttrX LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 AttrX LL_MPU_ConfigAttributes_NS + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} +#endif /* MPU_NS */ + +/** + * @brief Configure a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n + * MPU_RLAR LIMIT LL_MPU_SetRegionLimitAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param LimitAddress Value of region limit address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n + * MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval MPU region limit address + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n + * MPU_RBAR BASE LL_MPU_SetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param BaseAddress Value of region base address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n + * MPU_RBAR BASE LL_MPU_GetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval MPU region base address + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n + * MPU_RBAR XN LL_MPU_SetRegionAccess\n + * MPU_RBAR AP LL_MPU_SetRegionAccess\n + * MPU_RBAR SH LL_MPU_SetRegionAccess + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n + * MPU_RBAR XN LL_MPU_GetRegionAccess\n + * MPU_RBAR AP LL_MPU_GetRegionAccess\n + * MPU_RBAR SH LL_MPU_GetRegionAccess + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval MPU region access attributes + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} + +#ifdef MPU_NS +/** + * @brief Configure a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n + * MPU_RLAR LIMIT LL_MPU_SetRegionLimitAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param LimitAddress Value of region limit address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n + * MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval Non-secure MPU region limit address + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n + * MPU_RBAR BASE LL_MPU_SetRegionBaseAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param BaseAddress Value of region base address + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n + * MPU_RBAR BASE LL_MPU_GetRegionBaseAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval Non-secure MPU region base address + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a non-secure MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_SetRegionAccess_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note Cortex-M55 supports 16 secure and 16 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address Attributes */ + MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a non-secure MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_GetRegionAccess_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval Non-secure MPU region access attributes + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} +#endif /* MPU_NS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_LL_CORTEX_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_dma.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_dma.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_dma.h (revision 16) @@ -0,0 +1,8115 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### LL DMA driver acronyms ##### + ============================================================================== + [..] Acronyms table : + ========================================= + || Acronym || || + ========================================= + || SRC || Source || + || DEST || Destination || + || ADDR || Address || + || ADDRS || Addresses || + || INC || Increment / Incremented || + || DEC || Decrement / Decremented || + || BLK || Block || + || RPT || Repeat / Repeated || + || TRIG || Trigger || + ========================================= + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_DMA_H +#define STM32N6xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ + +#if (defined (GPDMA1) || defined (HPDMA1)) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +#define DMA_CHANNEL0_OFFSET (0x00000050UL) +#define DMA_CHANNEL1_OFFSET (0x000000D0UL) +#define DMA_CHANNEL2_OFFSET (0x00000150UL) +#define DMA_CHANNEL3_OFFSET (0x000001D0UL) +#define DMA_CHANNEL4_OFFSET (0x00000250UL) +#define DMA_CHANNEL5_OFFSET (0x000002D0UL) +#define DMA_CHANNEL6_OFFSET (0x00000350UL) +#define DMA_CHANNEL7_OFFSET (0x000003D0UL) +#define DMA_CHANNEL8_OFFSET (0x00000450UL) +#define DMA_CHANNEL9_OFFSET (0x000004D0UL) +#define DMA_CHANNEL10_OFFSET (0x00000550UL) +#define DMA_CHANNEL11_OFFSET (0x000005D0UL) +#define DMA_CHANNEL12_OFFSET (0x00000650UL) +#define DMA_CHANNEL13_OFFSET (0x000006D0UL) +#define DMA_CHANNEL14_OFFSET (0x00000750UL) +#define DMA_CHANNEL15_OFFSET (0x000007D0UL) + +/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ +static const uint32_t LL_DMA_CH_OFFSET_TAB[] = +{ + DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET, + DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET, + DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET, + DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET, +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ + +/** + * @brief LL DMA init structure definition. + */ +typedef struct +{ + uint32_t SrcAddress; /*!< This field specify the data transfer source address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddress(). */ + + uint32_t DestAddress; /*!< This field specify the data transfer destination address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddress(). */ + + uint32_t Direction; /*!< This field specify the data transfer direction. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkHWRequest(). */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataAlignment(). */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcBurstLength(). */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestBurstLength(). */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcDataWidth(). */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestDataWidth(). */ + + uint32_t SrcIncMode; /*!< This field specify the source burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcIncMode(). */ + + uint32_t DestIncMode; /*!< This field specify the destination burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestIncMode(). */ + + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkDataLength(). */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptCount(). */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerMode(). */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerPolarity(). */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetHWTrigger(). */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ + + uint32_t DestWordExchange; /*!< This field specify the destination word exchange. + Programming this field is mandatory for all available HPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestWordExchange(). */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestHWordExchange(). */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestByteExchange(). */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcByteExchange(). */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAllocatedPort(). */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAllocatedPort(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdate(). */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdate(). */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdateValue(). */ + + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdateValue(). */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */ + + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdate(). */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */ + + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */ + + uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first + bytes are always forced to 0). + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListBaseAddr(). */ + + uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0x0000FFFC. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListAddrOffset(). */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_LL_TRANSFER_MODE */ +} LL_DMA_InitTypeDef; + + +/** + * @brief LL DMA init linked list structure definition. + */ +typedef struct +{ + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ +} LL_DMA_InitLinkedListTypeDef; + + +/** + * @brief LL DMA node init structure definition. + */ +typedef struct +{ + /* CTR1 register fields ****************************************************** + If any CTR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR1 register fields and enable update + CTR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + */ +#if defined (CPU_IN_SECURE_STATE) + uint32_t DestSecure; /*!< This field specify the destination secure. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ +#endif /* CPU_IN_SECURE_STATE */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ + + uint32_t DestWordExchange; /*!< This field specify the destination word exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE. */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t DestIncMode; /*!< This field specify the destination increment mode. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */ + +#if defined (CPU_IN_SECURE_STATE) + uint32_t SrcSecure; /*!< This field specify the source secure. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ +#endif /* CPU_IN_SECURE_STATE */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t SrcIncMode; /*!< This field specify the source increment mode. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */ + + + /* CTR2 register fields ****************************************************** + If any CTR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR2 register fields and enable update + CTR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */ + + uint32_t Direction; /*!< This field specify the transfer direction. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */ + + uint32_t Mode; /*!< This field DMA Transfer Mode. + This parameter can be a value of @ref DMA_LL_TRANSFER_MODE. */ + + /* CBR1 register fields ****************************************************** + If any CBR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR1 register fields and enable update + CBR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + If the node to be created is not for 2D addressing channels, there is no + need to fill the following fields for CBR1 register : + - BlkReptDestAddrUpdate. + - BlkRptSrcAddrUpdate. + - DestAddrUpdate. + - SrcAddrUpdate. + - BlkRptCount. + */ + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0x0000FFFF. */ + + /* CSAR register fields ****************************************************** + If any CSAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CSAR register fields and enable update + CSAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t SrcAddress; /*!< This field specify the transfer source address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + + /* CDAR register fields ****************************************************** + If any CDAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CDAR register fields and enable update + CDAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t DestAddress; /*!< This field specify the transfer destination address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + /* CTR3 register fields ****************************************************** + If any CTR3 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR3 register fields and enable update + CTR3 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be overwritten by + CLLR register in memory. + When this register is enabled on UpdateRegisters and the selected channel + is linear addressing, LL APIs will discard this register update in memory. + */ + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + + /* CBR2 register fields ****************************************************** + If any CBR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR2 register fields and enable update + CBR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be discarded in + memory. When this register is enabled on UpdateRegisters and the selected + channel is linear addressing, LL APIs will discard this register update in + memory. + */ + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + /* CLLR register fields ****************************************************** + If any CLLR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CLLR register fields and enable update + CLLR register in UpdateRegisters fields if it is not enabled in the + previous node. + + If used channel is linear addressing, there is no need to enable/disable + CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded + by LL APIs. + */ + uint32_t UpdateRegisters; /*!< Specifies the linked list register update. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */ + + /* DMA Node type field ******************************************************* + This parameter defines node types as node size and node content varies + between channels. + Thanks to this fields, linked list queue could be created independently + from channel selection. So, one queue could be executed by all DMA channels. + */ + uint32_t NodeType; /*!< Specifies the node type to be created. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */ +} LL_DMA_InitNodeTypeDef; + +/** + * @brief LL DMA linked list node structure definition. + * @note For 2D addressing channels, the maximum node size is : + * (4 Bytes * 8 registers = 32 Bytes). + * For GPDMA & HPDMA linear addressing channels, the maximum node size is : + * (4 Bytes * 6 registers = 24 Bytes). + */ +typedef struct +{ + __IO uint32_t LinkRegisters[8U]; + +} LL_DMA_LinkNodeTypeDef; +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_DMA_CHANNEL_0 (0x00U) +#define LL_DMA_CHANNEL_1 (0x01U) +#define LL_DMA_CHANNEL_2 (0x02U) +#define LL_DMA_CHANNEL_3 (0x03U) +#define LL_DMA_CHANNEL_4 (0x04U) +#define LL_DMA_CHANNEL_5 (0x05U) +#define LL_DMA_CHANNEL_6 (0x06U) +#define LL_DMA_CHANNEL_7 (0x07U) +#define LL_DMA_CHANNEL_8 (0x08U) +#define LL_DMA_CHANNEL_9 (0x09U) +#define LL_DMA_CHANNEL_10 (0x0AU) +#define LL_DMA_CHANNEL_11 (0x0BU) +#define LL_DMA_CHANNEL_12 (0x0CU) +#define LL_DMA_CHANNEL_13 (0x0DU) +#define LL_DMA_CHANNEL_14 (0x0EU) +#define LL_DMA_CHANNEL_15 (0x0FU) +#if defined (USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL (0x10U) +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset + * @{ + */ +#define LL_DMA_CLLR_OFFSET0 (0x00U) +#define LL_DMA_CLLR_OFFSET1 (0x01U) +#define LL_DMA_CLLR_OFFSET2 (0x02U) +#define LL_DMA_CLLR_OFFSET3 (0x03U) +#define LL_DMA_CLLR_OFFSET4 (0x04U) +#define LL_DMA_CLLR_OFFSET5 (0x05U) +#define LL_DMA_CLLR_OFFSET6 (0x06U) +#define LL_DMA_CLLR_OFFSET7 (0x07U) +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup DMA_LL_EC_CID Static Isolation CID + * @{ + */ +#define LL_DMA_CHANNEL_STATIC_CID_0 (0U< Byte */ +#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange + * @{ + */ +#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */ +#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port + * @{ + */ +#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ +#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port + * @{ + */ +#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ +#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode + * @{ + */ +#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */ +#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width + * @{ + */ +#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */ +#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */ +#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */ +#define LL_DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination Data Width : DoubleWord */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment + * @{ + */ +#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width : + => Right Aligned padded with 0 up to destination + data width. + If src data width > dest data width : + => Right Aligned Left Truncated down to destination + data width. */ +#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width : + => Right Aligned padded with sign extended up to destination + data width. + If src data width > dest data width : + => Left Aligned Right Truncated down to the destination + data width */ +#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width : + => Packed at the destination data width + If src data width > dest data width : + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode + * @{ + */ +#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */ +#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width + * @{ + */ +#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */ +#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */ +#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */ +#define LL_DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source Data Width : DoubleWord */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request + * @{ + */ +#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a burst level */ +#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode + * @{ + */ +#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the + (respectively half) end of each block */ +#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the + (respectively half) end of the repeated block */ +#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the + (respectively half) end of each linked-list item */ +#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the + (respectively half) end of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity + * @{ + */ +#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. + Masked trigger event */ +#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising + edge of the selected trigger event input */ +#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling + edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode + * @{ + */ +#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least) + one hit trigger */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_DMA_NORMAL 0x00000000U /*!< Normal DMA transfer */ +#define LL_DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block + transfer by source update value */ +#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block + transfer by destination update value */ +#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block + transfer by destination update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode + * @{ + */ +#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst + transfer by source update value */ +#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode + * @{ + */ +#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each + burst transfer by destination update value */ +#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each + burst transfer by destination update value */ +/** + * @} + */ + +#if defined (CPU_IN_SECURE_STATE) +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */ +#define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */ +#define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */ +#define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */ +/** + * @} + */ +#endif /* CPU_IN_SECURE_STATE */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type + * @{ + */ +#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */ +#define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */ +#define LL_DMA_HPDMA_LINEAR_NODE 0x04U /*!< HPDMA node : linear addressing node */ +#define LL_DMA_HPDMA_2D_NODE 0x08U /*!< HPDMA node : 2 dimension addressing node */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update + * @{ + */ +#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory : + available for all DMA channels */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection + * @{ + */ +/* HPDMA1 requests */ +#define LL_HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_RX */ +#define LL_HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_TX */ +#define LL_HPDMA1_REQUEST_OCTOSPI1 2U /*!< HPDMA1 HW request is OCTOSPI1 */ +#define LL_HPDMA1_REQUEST_OCTOSPI2 3U /*!< HPDMA1 HW request is OCTOSPI2 */ +#define LL_HPDMA1_REQUEST_OCTOSPI3 4U /*!< HPDMA1 HW request is OCTOSPI3 */ +#define LL_HPDMA1_REQUEST_FMC2_TXRX 5U /*!< HPDMA1 HW request is FMC2_TXRX */ +#define LL_HPDMA1_REQUEST_FMC2_BCH 6U /*!< HPDMA1 HW request is FMC2_BCH */ +#define LL_HPDMA1_REQUEST_ADC1 7U /*!< HPDMA1 HW request is ADC1 */ +#define LL_HPDMA1_REQUEST_ADC2 8U /*!< HPDMA1 HW request is ADC2 */ +#define LL_HPDMA1_REQUEST_CRYP_IN 9U /*!< HPDMA1 HW request is CRYP_IN */ +#define LL_HPDMA1_REQUEST_CRYP_OUT 10U /*!< HPDMA1 HW request is CRYP_OUT */ +#define LL_HPDMA1_REQUEST_SAES_OUT 11U /*!< HPDMA1 HW request is SAES_OUT */ +#define LL_HPDMA1_REQUEST_SAES_IN 12U /*!< HPDMA1 HW request is SAES_IN */ +#define LL_HPDMA1_REQUEST_HASH_IN 13U /*!< HPDMA1 HW request is HASH_IN */ + +#define LL_HPDMA1_REQUEST_TIM1_CH1 14U /*!< HPDMA1 HW request is TIM1_CH1 */ +#define LL_HPDMA1_REQUEST_TIM1_CH2 15U /*!< HPDMA1 HW request is TIM1_CH2 */ +#define LL_HPDMA1_REQUEST_TIM1_CH3 16U /*!< HPDMA1 HW request is TIM1_CH3 */ +#define LL_HPDMA1_REQUEST_TIM1_CH4 17U /*!< HPDMA1 HW request is TIM1_CH4 */ +#define LL_HPDMA1_REQUEST_TIM1_UP 18U /*!< HPDMA1 HW request is TIM1_UP */ +#define LL_HPDMA1_REQUEST_TIM1_TRIG 19U /*!< HPDMA1 HW request is TIM1_TRIG */ +#define LL_HPDMA1_REQUEST_TIM1_COM 20U /*!< HPDMA1 HW request is TIM1_COM */ + +#define LL_HPDMA1_REQUEST_TIM2_CH1 21U /*!< HPDMA1 HW request is TIM2_CH1 */ +#define LL_HPDMA1_REQUEST_TIM2_CH2 22U /*!< HPDMA1 HW request is TIM2_CH2 */ +#define LL_HPDMA1_REQUEST_TIM2_CH3 23U /*!< HPDMA1 HW request is TIM2_CH3 */ +#define LL_HPDMA1_REQUEST_TIM2_CH4 24U /*!< HPDMA1 HW request is TIM2_CH4 */ +#define LL_HPDMA1_REQUEST_TIM2_UP 25U /*!< HPDMA1 HW request is TIM2_UP */ +#define LL_HPDMA1_REQUEST_TIM2_TRIG 26U /*!< HPDMA1 HW request is TIM2_TRIG */ + +#define LL_HPDMA1_REQUEST_TIM3_CH1 27U /*!< HPDMA1 HW request is TIM3_CH1 */ +#define LL_HPDMA1_REQUEST_TIM3_CH2 28U /*!< HPDMA1 HW request is TIM3_CH2 */ +#define LL_HPDMA1_REQUEST_TIM3_CH3 29U /*!< HPDMA1 HW request is TIM3_CH3 */ +#define LL_HPDMA1_REQUEST_TIM3_CH4 30U /*!< HPDMA1 HW request is TIM3_CH4 */ +#define LL_HPDMA1_REQUEST_TIM3_UP 31U /*!< HPDMA1 HW request is TIM3_UP */ +#define LL_HPDMA1_REQUEST_TIM3_TRIG 32U /*!< HPDMA1 HW request is TIM3_TRIG */ + +#define LL_HPDMA1_REQUEST_TIM4_CH1 33U /*!< HPDMA1 HW request is TIM4_CH1 */ +#define LL_HPDMA1_REQUEST_TIM4_CH2 34U /*!< HPDMA1 HW request is TIM4_CH2 */ +#define LL_HPDMA1_REQUEST_TIM4_CH3 35U /*!< HPDMA1 HW request is TIM4_CH3 */ +#define LL_HPDMA1_REQUEST_TIM4_CH4 36U /*!< HPDMA1 HW request is TIM4_CH4 */ +#define LL_HPDMA1_REQUEST_TIM4_UP 37U /*!< HPDMA1 HW request is TIM4_UP */ +#define LL_HPDMA1_REQUEST_TIM4_TRIG 38U /*!< HPDMA1 HW request is TIM4_TRIG */ + +#define LL_HPDMA1_REQUEST_TIM5_CH1 39U /*!< HPDMA1 HW request is TIM5_CH1 */ +#define LL_HPDMA1_REQUEST_TIM5_CH2 40U /*!< HPDMA1 HW request is TIM5_CH2 */ +#define LL_HPDMA1_REQUEST_TIM5_CH3 41U /*!< HPDMA1 HW request is TIM5_CH3 */ +#define LL_HPDMA1_REQUEST_TIM5_CH4 42U /*!< HPDMA1 HW request is TIM5_CH4 */ +#define LL_HPDMA1_REQUEST_TIM5_UP 43U /*!< HPDMA1 HW request is TIM5_UP */ +#define LL_HPDMA1_REQUEST_TIM5_TRIG 44U /*!< HPDMA1 HW request is TIM5_TRIG */ + +#define LL_HPDMA1_REQUEST_TIM6_UP 45U /*!< HPDMA1 HW request is TIM6_UP */ +#define LL_HPDMA1_REQUEST_TIM7_UP 46U /*!< HPDMA1 HW request is TIM7_UP */ + +#define LL_HPDMA1_REQUEST_TIM8_CH1 47U /*!< HPDMA1 HW request is TIM8_CH1 */ +#define LL_HPDMA1_REQUEST_TIM8_CH2 48U /*!< HPDMA1 HW request is TIM8_CH2 */ +#define LL_HPDMA1_REQUEST_TIM8_CH3 49U /*!< HPDMA1 HW request is TIM8_CH3 */ +#define LL_HPDMA1_REQUEST_TIM8_CH4 50U /*!< HPDMA1 HW request is TIM8_CH4 */ +#define LL_HPDMA1_REQUEST_TIM8_UP 51U /*!< HPDMA1 HW request is TIM8_UP */ +#define LL_HPDMA1_REQUEST_TIM8_TRIG 52U /*!< HPDMA1 HW request is TIM8_TRIG */ +#define LL_HPDMA1_REQUEST_TIM8_COM 53U /*!< HPDMA1 HW request is TIM8_COM */ + +/* reserved 54U */ +/* reserved 55U */ + +#define LL_HPDMA1_REQUEST_TIM15_CH1 56U /*!< HPDMA1 HW request is TIM15_CH1 */ +#define LL_HPDMA1_REQUEST_TIM15_CH2 57U /*!< HPDMA1 HW request is TIM15_CH2 */ +#define LL_HPDMA1_REQUEST_TIM15_UP 58U /*!< HPDMA1 HW request is TIM15_UP */ +#define LL_HPDMA1_REQUEST_TIM15_TRIG 59U /*!< HPDMA1 HW request is TIM15_TRIG */ +#define LL_HPDMA1_REQUEST_TIM15_COM 60U /*!< HPDMA1 HW request is TIM15_COM */ + +#define LL_HPDMA1_REQUEST_TIM16_CH1 61U /*!< HPDMA1 HW request is TIM16_CH1 */ +#define LL_HPDMA1_REQUEST_TIM16_UP 62U /*!< HPDMA1 HW request is TIM16_UP */ +#define LL_HPDMA1_REQUEST_TIM16_COM 63U /*!< HPDMA1 HW request is TIM16_COM */ + +#define LL_HPDMA1_REQUEST_TIM17_CH1 64U /*!< HPDMA1 HW request is TIM17_CH1 */ +#define LL_HPDMA1_REQUEST_TIM17_UP 65U /*!< HPDMA1 HW request is TIM17_UP */ +#define LL_HPDMA1_REQUEST_TIM17_COM 66U /*!< HPDMA1 HW request is TIM17_COM */ + +#define LL_HPDMA1_REQUEST_TIM18_CH1 67U /*!< HPDMA1 HW request is TIM18_CH1 */ +#define LL_HPDMA1_REQUEST_TIM18_UP 68U /*!< HPDMA1 HW request is TIM18_UP */ +#define LL_HPDMA1_REQUEST_TIM18_COM 69U /*!< HPDMA1 HW request is TIM18_COM */ + +#define LL_HPDMA1_REQUEST_LPTIM1_IC1 70U /*!< HPDMA1 HW request is LPTIM1_IC1 */ +#define LL_HPDMA1_REQUEST_LPTIM1_IC2 71U /*!< HPDMA1 HW request is LPTIM1_IC2 */ +#define LL_HPDMA1_REQUEST_LPTIM1_UE 72U /*!< HPDMA1 HW request is LPTIM1_UE */ +#define LL_HPDMA1_REQUEST_LPTIM2_IC1 73U /*!< HPDMA1 HW request is LPTIM2_IC1 */ +#define LL_HPDMA1_REQUEST_LPTIM2_IC2 74U /*!< HPDMA1 HW request is LPTIM2_IC2 */ +#define LL_HPDMA1_REQUEST_LPTIM2_UE 75U /*!< HPDMA1 HW request is LPTIM2_UE */ +#define LL_HPDMA1_REQUEST_LPTIM3_IC1 76U /*!< HPDMA1 HW request is LPTIM3_IC1 */ +#define LL_HPDMA1_REQUEST_LPTIM3_IC2 77U /*!< HPDMA1 HW request is LPTIM3_IC2 */ +#define LL_HPDMA1_REQUEST_LPTIM3_UE 78U /*!< HPDMA1 HW request is LPTIM3_UE */ + +#define LL_HPDMA1_REQUEST_SPI1_RX 79U /*!< HPDMA1 HW request is SPI1_RX */ +#define LL_HPDMA1_REQUEST_SPI1_TX 80U /*!< HPDMA1 HW request is SPI1_TX */ +#define LL_HPDMA1_REQUEST_SPI2_RX 81U /*!< HPDMA1 HW request is SPI2_RX */ +#define LL_HPDMA1_REQUEST_SPI2_TX 82U /*!< HPDMA1 HW request is SPI2_TX */ +#define LL_HPDMA1_REQUEST_SPI3_RX 83U /*!< HPDMA1 HW request is SPI3_RX */ +#define LL_HPDMA1_REQUEST_SPI3_TX 84U /*!< HPDMA1 HW request is SPI3_TX */ +#define LL_HPDMA1_REQUEST_SPI4_RX 85U /*!< HPDMA1 HW request is SPI4_RX */ +#define LL_HPDMA1_REQUEST_SPI4_TX 86U /*!< HPDMA1 HW request is SPI4_TX */ +#define LL_HPDMA1_REQUEST_SPI5_RX 87U /*!< HPDMA1 HW request is SPI5_RX */ +#define LL_HPDMA1_REQUEST_SPI5_TX 88U /*!< HPDMA1 HW request is SPI5_TX */ +#define LL_HPDMA1_REQUEST_SPI6_RX 89U /*!< HPDMA1 HW request is SPI6_RX */ +#define LL_HPDMA1_REQUEST_SPI6_TX 90U /*!< HPDMA1 HW request is SPI6_TX */ + +#define LL_HPDMA1_REQUEST_SAI1_A 91U /*!< HPDMA1 HW request is SAI1_A */ +#define LL_HPDMA1_REQUEST_SAI1_B 92U /*!< HPDMA1 HW request is SAI1_B */ +#define LL_HPDMA1_REQUEST_SAI2_A 93U /*!< HPDMA1 HW request is SAI2_A */ +#define LL_HPDMA1_REQUEST_SAI2_B 94U /*!< HPDMA1 HW request is SAI2_B */ + +#define LL_HPDMA1_REQUEST_I2C1_RX 95U /*!< HPDMA1 HW request is I2C1_RX */ +#define LL_HPDMA1_REQUEST_I2C1_TX 96U /*!< HPDMA1 HW request is I2C1_TX */ +#define LL_HPDMA1_REQUEST_I2C2_RX 97U /*!< HPDMA1 HW request is I2C2_RX */ +#define LL_HPDMA1_REQUEST_I2C2_TX 98U /*!< HPDMA1 HW request is I2C2_TX */ +#define LL_HPDMA1_REQUEST_I2C3_RX 99U /*!< HPDMA1 HW request is I2C3_RX */ +#define LL_HPDMA1_REQUEST_I2C3_TX 100U /*!< HPDMA1 HW request is I2C3_TX */ + +#define LL_HPDMA1_REQUEST_I2C4_RX 101U /*!< HPDMA1 HW request is I2C4_RX */ +#define LL_HPDMA1_REQUEST_I2C4_TX 102U /*!< HPDMA1 HW request is I2C4_TX */ + +#define LL_HPDMA1_REQUEST_I3C1_RX 103U /*!< HPDMA1 HW request is I3C1_RX */ +#define LL_HPDMA1_REQUEST_I3C1_TX 104U /*!< HPDMA1 HW request is I3C1_TX */ +#define LL_HPDMA1_REQUEST_I3C2_RX 105U /*!< HPDMA1 HW request is I3C2_RX */ +#define LL_HPDMA1_REQUEST_I3C2_TX 106U /*!< HPDMA1 HW request is I3C2_TX */ + +#define LL_HPDMA1_REQUEST_USART1_RX 107U /*!< HPDMA1 HW request is USART1_RX */ +#define LL_HPDMA1_REQUEST_USART1_TX 108U /*!< HPDMA1 HW request is USART1_TX */ +#define LL_HPDMA1_REQUEST_USART2_RX 109U /*!< HPDMA1 HW request is USART2_RX */ +#define LL_HPDMA1_REQUEST_USART2_TX 110U /*!< HPDMA1 HW request is USART2_TX */ +#define LL_HPDMA1_REQUEST_USART3_RX 111U /*!< HPDMA1 HW request is USART3_RX */ +#define LL_HPDMA1_REQUEST_USART3_TX 112U /*!< HPDMA1 HW request is USART3_TX */ +#define LL_HPDMA1_REQUEST_UART4_RX 113U /*!< HPDMA1 HW request is UART4_RX */ +#define LL_HPDMA1_REQUEST_UART4_TX 114U /*!< HPDMA1 HW request is UART4_TX */ +#define LL_HPDMA1_REQUEST_UART5_RX 115U /*!< HPDMA1 HW request is UART5_RX */ +#define LL_HPDMA1_REQUEST_UART5_TX 116U /*!< HPDMA1 HW request is UART5_TX */ +#define LL_HPDMA1_REQUEST_USART6_RX 117U /*!< HPDMA1 HW request is USART6_RX */ +#define LL_HPDMA1_REQUEST_USART6_TX 118U /*!< HPDMA1 HW request is USART6_TX */ +#define LL_HPDMA1_REQUEST_UART7_RX 119U /*!< HPDMA1 HW request is UART7_RX */ +#define LL_HPDMA1_REQUEST_UART7_TX 120U /*!< HPDMA1 HW request is UART7_TX */ +#define LL_HPDMA1_REQUEST_UART8_RX 121U /*!< HPDMA1 HW request is UART8_RX */ +#define LL_HPDMA1_REQUEST_UART8_TX 122U /*!< HPDMA1 HW request is UART8_TX */ +#define LL_HPDMA1_REQUEST_UART9_RX 123U /*!< HPDMA1 HW request is UART9_RX */ +#define LL_HPDMA1_REQUEST_UART9_TX 124U /*!< HPDMA1 HW request is UART9_TX */ +#define LL_HPDMA1_REQUEST_USART10_RX 125U /*!< HPDMA1 HW request is USART10_RX */ +#define LL_HPDMA1_REQUEST_USART10_TX 126U /*!< HPDMA1 HW request is USART10_TX */ + +#define LL_HPDMA1_REQUEST_LPUART1_RX 127U /*!< HPDMA1 HW request is LPUART1_RX */ +#define LL_HPDMA1_REQUEST_LPUART1_TX 128U /*!< HPDMA1 HW request is LPUART1_TX */ + +#define LL_HPDMA1_REQUEST_SPDIFRX_CS 129U /*!< HPDMA1 HW request is SPDIFRX_CS */ +#define LL_HPDMA1_REQUEST_SPDIFRX_DT 130U /*!< HPDMA1 HW request is SPDIFRX_DT */ + +#define LL_HPDMA1_REQUEST_ADF1_FLT0 131U /*!< HPDMA1 HW request is ADF1_FLT0 */ + +#define LL_HPDMA1_REQUEST_MDF1_FLT0 132U /*!< HPDMA1 HW request is MDF1_FLT0 */ +#define LL_HPDMA1_REQUEST_MDF1_FLT1 133U /*!< HPDMA1 HW request is MDF1_FLT1 */ +#define LL_HPDMA1_REQUEST_MDF1_FLT2 134U /*!< HPDMA1 HW request is MDF1_FLT2 */ +#define LL_HPDMA1_REQUEST_MDF1_FLT3 135U /*!< HPDMA1 HW request is MDF1_FLT3 */ +#define LL_HPDMA1_REQUEST_MDF1_FLT4 136U /*!< HPDMA1 HW request is MDF1_FLT4 */ +#define LL_HPDMA1_REQUEST_MDF1_FLT5 137U /*!< HPDMA1 HW request is MDF1_FLT5 */ + +#define LL_HPDMA1_REQUEST_UCPD1_TX 138U /*!< HPDMA1 HW request is UCPD1_TX */ +#define LL_HPDMA1_REQUEST_UCPD1_RX 139U /*!< HPDMA1 HW request is UCPD1_RX */ + +#define LL_HPDMA1_REQUEST_DCMI_PSSI 140U /*!< HPDMA1 HW request is DCMI_PSSI */ + +#define LL_HPDMA1_REQUEST_I3C1_TC 141U /*!< HPDMA1 HW request is I3C1_TC */ +#define LL_HPDMA1_REQUEST_I3C1_RS 142U /*!< HPDMA1 HW request is I3C1_RS */ + +#define LL_HPDMA1_REQUEST_I3C2_TC 143U /*!< HPDMA1 HW request is I3C2_TC */ +#define LL_HPDMA1_REQUEST_I3C2_RS 144U /*!< HPDMA1 HW request is I3C2_RS */ + + +/* GPDMA1 requests */ +#define LL_GPDMA1_REQUEST_JPEG_RX 0U /*!< GPDMA1 HW request is JPEG_DMA_RX */ +#define LL_GPDMA1_REQUEST_JPEG_TX 1U /*!< GPDMA1 HW request is JPEG_DMA_TX */ +#define LL_GPDMA1_REQUEST_OCTOSPI1 2U /*!< GPDMA1 HW request is OCTOSPI1 */ +#define LL_GPDMA1_REQUEST_OCTOSPI2 3U /*!< GPDMA1 HW request is OCTOSPI2 */ +#define LL_GPDMA1_REQUEST_OCTOSPI3 4U /*!< GPDMA1 HW request is OCTOSPI3 */ +#define LL_GPDMA1_REQUEST_FMC2_TXRX 5U /*!< GPDMA1 HW request is FMC2_TXRX */ +#define LL_GPDMA1_REQUEST_FMC2_BCH 6U /*!< GPDMA1 HW request is FMC2_BCH */ +#define LL_GPDMA1_REQUEST_ADC1 7U /*!< GPDMA1 HW request is ADC1 */ +#define LL_GPDMA1_REQUEST_ADC2 8U /*!< GPDMA1 HW request is ADC2 */ +#define LL_GPDMA1_REQUEST_CRYP_IN 9U /*!< GPDMA1 HW request is CRYP_IN */ +#define LL_GPDMA1_REQUEST_CRYP_OUT 10U /*!< GPDMA1 HW request is CRYP_OUT */ +#define LL_GPDMA1_REQUEST_SAES_OUT 11U /*!< GPDMA1 HW request is SAES_OUT */ +#define LL_GPDMA1_REQUEST_SAES_IN 12U /*!< GPDMA1 HW request is SAES_IN */ +#define LL_GPDMA1_REQUEST_HASH_IN 13U /*!< GPDMA1 HW request is HASH_IN */ + +#define LL_GPDMA1_REQUEST_TIM1_CH1 14U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH2 15U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM1_CH3 16U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define LL_GPDMA1_REQUEST_TIM1_CH4 17U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define LL_GPDMA1_REQUEST_TIM1_UP 18U /*!< GPDMA1 HW request is TIM1_UP */ +#define LL_GPDMA1_REQUEST_TIM1_TRIG 19U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define LL_GPDMA1_REQUEST_TIM1_COM 20U /*!< GPDMA1 HW request is TIM1_COM */ + +#define LL_GPDMA1_REQUEST_TIM2_CH1 21U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define LL_GPDMA1_REQUEST_TIM2_CH2 22U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define LL_GPDMA1_REQUEST_TIM2_CH3 23U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define LL_GPDMA1_REQUEST_TIM2_CH4 24U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define LL_GPDMA1_REQUEST_TIM2_UP 25U /*!< GPDMA1 HW request is TIM2_UP */ +#define LL_GPDMA1_REQUEST_TIM2_TRIG 26U /*!< GPDMA1 HW request is TIM2_TRIG */ + +#define LL_GPDMA1_REQUEST_TIM3_CH1 27U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define LL_GPDMA1_REQUEST_TIM3_CH2 28U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define LL_GPDMA1_REQUEST_TIM3_CH3 29U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define LL_GPDMA1_REQUEST_TIM3_CH4 30U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define LL_GPDMA1_REQUEST_TIM3_UP 31U /*!< GPDMA1 HW request is TIM3_UP */ +#define LL_GPDMA1_REQUEST_TIM3_TRIG 32U /*!< GPDMA1 HW request is TIM3_TRIG */ + +#define LL_GPDMA1_REQUEST_TIM4_CH1 33U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define LL_GPDMA1_REQUEST_TIM4_CH2 34U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define LL_GPDMA1_REQUEST_TIM4_CH3 35U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define LL_GPDMA1_REQUEST_TIM4_CH4 36U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define LL_GPDMA1_REQUEST_TIM4_UP 37U /*!< GPDMA1 HW request is TIM4_UP */ +#define LL_GPDMA1_REQUEST_TIM4_TRIG 38U /*!< GPDMA1 HW request is TIM4_TRIG */ + +#define LL_GPDMA1_REQUEST_TIM5_CH1 39U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define LL_GPDMA1_REQUEST_TIM5_CH2 40U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define LL_GPDMA1_REQUEST_TIM5_CH3 41U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define LL_GPDMA1_REQUEST_TIM5_CH4 42U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define LL_GPDMA1_REQUEST_TIM5_UP 43U /*!< GPDMA1 HW request is TIM5_UP */ +#define LL_GPDMA1_REQUEST_TIM5_TRIG 44U /*!< GPDMA1 HW request is TIM5_TRIG */ + +#define LL_GPDMA1_REQUEST_TIM6_UP 45U /*!< GPDMA1 HW request is TIM6_UP */ +#define LL_GPDMA1_REQUEST_TIM7_UP 46U /*!< GPDMA1 HW request is TIM6_UP */ + +#define LL_GPDMA1_REQUEST_TIM8_CH1 47U /*!< GPDMA1 HW request is TIM8_CH1 */ +#define LL_GPDMA1_REQUEST_TIM8_CH2 48U /*!< GPDMA1 HW request is TIM8_CH2 */ +#define LL_GPDMA1_REQUEST_TIM8_CH3 49U /*!< GPDMA1 HW request is TIM8_CH3 */ +#define LL_GPDMA1_REQUEST_TIM8_CH4 50U /*!< GPDMA1 HW request is TIM8_CH4 */ +#define LL_GPDMA1_REQUEST_TIM8_UP 51U /*!< GPDMA1 HW request is TIM8_UP */ +#define LL_GPDMA1_REQUEST_TIM8_TRIG 52U /*!< GPDMA1 HW request is TIM8_TRIG */ +#define LL_GPDMA1_REQUEST_TIM8_COM 53U /*!< GPDMA1 HW request is TIM8_COM */ + +/* reserved 54U */ +/* reserved 55U */ + +#define LL_GPDMA1_REQUEST_TIM15_CH1 56U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define LL_GPDMA1_REQUEST_TIM15_CH2 57U /*!< GPDMA1 HW request is TIM15_CH2 */ +#define LL_GPDMA1_REQUEST_TIM15_UP 58U /*!< GPDMA1 HW request is TIM15_UP */ +#define LL_GPDMA1_REQUEST_TIM15_TRIG 59U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define LL_GPDMA1_REQUEST_TIM15_COM 60U /*!< GPDMA1 HW request is TIM15_COM */ + +#define LL_GPDMA1_REQUEST_TIM16_CH1 61U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define LL_GPDMA1_REQUEST_TIM16_UP 62U /*!< GPDMA1 HW request is TIM16_UP */ +#define LL_GPDMA1_REQUEST_TIM16_COM 63U /*!< GPDMA1 HW request is TIM16_COM */ + +#define LL_GPDMA1_REQUEST_TIM17_CH1 64U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define LL_GPDMA1_REQUEST_TIM17_UP 65U /*!< GPDMA1 HW request is TIM17_UP */ +#define LL_GPDMA1_REQUEST_TIM17_COM 66U /*!< GPDMA1 HW request is TIM17_COM */ + +#define LL_GPDMA1_REQUEST_TIM18_CH1 67U /*!< GPDMA1 HW request is TIM18_CH1 */ +#define LL_GPDMA1_REQUEST_TIM18_UP 68U /*!< GPDMA1 HW request is TIM18_UP */ +#define LL_GPDMA1_REQUEST_TIM18_COM 69U /*!< GPDMA1 HW request is TIM18_COM */ + +#define LL_GPDMA1_REQUEST_LPTIM1_IC1 70U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC2 71U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM1_UE 72U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC1 73U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC2 74U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM2_UE 75U /*!< GPDMA1 HW request is LPTIM2_UE */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC1 76U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC2 77U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM3_UE 78U /*!< GPDMA1 HW request is LPTIM3_UE */ + +#define LL_GPDMA1_REQUEST_SPI1_RX 79U /*!< GPDMA1 HW request is SPI1_RX */ +#define LL_GPDMA1_REQUEST_SPI1_TX 80U /*!< GPDMA1 HW request is SPI1_TX */ +#define LL_GPDMA1_REQUEST_SPI2_RX 81U /*!< GPDMA1 HW request is SPI2_RX */ +#define LL_GPDMA1_REQUEST_SPI2_TX 82U /*!< GPDMA1 HW request is SPI2_TX */ +#define LL_GPDMA1_REQUEST_SPI3_RX 83U /*!< GPDMA1 HW request is SPI3_RX */ +#define LL_GPDMA1_REQUEST_SPI3_TX 84U /*!< GPDMA1 HW request is SPI3_TX */ +#define LL_GPDMA1_REQUEST_SPI4_RX 85U /*!< GPDMA1 HW request is SPI4_RX */ +#define LL_GPDMA1_REQUEST_SPI4_TX 86U /*!< GPDMA1 HW request is SPI4_TX */ +#define LL_GPDMA1_REQUEST_SPI5_RX 87U /*!< GPDMA1 HW request is SPI5_RX */ +#define LL_GPDMA1_REQUEST_SPI5_TX 88U /*!< GPDMA1 HW request is SPI5_TX */ +#define LL_GPDMA1_REQUEST_SPI6_RX 89U /*!< GPDMA1 HW request is SPI6_RX */ +#define LL_GPDMA1_REQUEST_SPI6_TX 90U /*!< GPDMA1 HW request is SPI6_TX */ + +#define LL_GPDMA1_REQUEST_SAI1_A 91U /*!< GPDMA1 HW request is SAI1_A */ +#define LL_GPDMA1_REQUEST_SAI1_B 92U /*!< GPDMA1 HW request is SAI1_B */ +#define LL_GPDMA1_REQUEST_SAI2_A 93U /*!< GPDMA1 HW request is SAI2_A */ +#define LL_GPDMA1_REQUEST_SAI2_B 94U /*!< GPDMA1 HW request is SAI2_B */ + +#define LL_GPDMA1_REQUEST_I2C1_RX 95U /*!< GPDMA1 HW request is I2C1_RX */ +#define LL_GPDMA1_REQUEST_I2C1_TX 96U /*!< GPDMA1 HW request is I2C1_TX */ +#define LL_GPDMA1_REQUEST_I2C2_RX 97U /*!< GPDMA1 HW request is I2C2_RX */ +#define LL_GPDMA1_REQUEST_I2C2_TX 98U /*!< GPDMA1 HW request is I2C2_TX */ +#define LL_GPDMA1_REQUEST_I2C3_RX 99U /*!< GPDMA1 HW request is I2C3_RX */ +#define LL_GPDMA1_REQUEST_I2C3_TX 100U /*!< GPDMA1 HW request is I2C3_TX */ + +#define LL_GPDMA1_REQUEST_I2C4_RX 101U /*!< GPDMA1 HW request is I2C4_RX */ +#define LL_GPDMA1_REQUEST_I2C4_TX 102U /*!< GPDMA1 HW request is I2C4_TX */ + +#define LL_GPDMA1_REQUEST_I3C1_RX 103U /*!< GPDMA1 HW request is I3C1_RX */ +#define LL_GPDMA1_REQUEST_I3C1_TX 104U /*!< GPDMA1 HW request is I3C1_TX */ +#define LL_GPDMA1_REQUEST_I3C2_RX 105U /*!< GPDMA1 HW request is I3C2_RX */ +#define LL_GPDMA1_REQUEST_I3C2_TX 106U /*!< GPDMA1 HW request is I3C2_TX */ + +#define LL_GPDMA1_REQUEST_USART1_RX 107U /*!< GPDMA1 HW request is USART1_RX */ +#define LL_GPDMA1_REQUEST_USART1_TX 108U /*!< GPDMA1 HW request is USART1_TX */ +#define LL_GPDMA1_REQUEST_USART2_RX 109U /*!< GPDMA1 HW request is USART2_RX */ +#define LL_GPDMA1_REQUEST_USART2_TX 110U /*!< GPDMA1 HW request is USART2_TX */ +#define LL_GPDMA1_REQUEST_USART3_RX 111U /*!< GPDMA1 HW request is USART3_RX */ +#define LL_GPDMA1_REQUEST_USART3_TX 112U /*!< GPDMA1 HW request is USART3_TX */ +#define LL_GPDMA1_REQUEST_UART4_RX 113U /*!< GPDMA1 HW request is UART4_RX */ +#define LL_GPDMA1_REQUEST_UART4_TX 114U /*!< GPDMA1 HW request is UART4_TX */ +#define LL_GPDMA1_REQUEST_UART5_RX 115U /*!< GPDMA1 HW request is UART5_RX */ +#define LL_GPDMA1_REQUEST_UART5_TX 116U /*!< GPDMA1 HW request is UART5_TX */ +#define LL_GPDMA1_REQUEST_USART6_RX 117U /*!< GPDMA1 HW request is USART6_RX */ +#define LL_GPDMA1_REQUEST_USART6_TX 118U /*!< GPDMA1 HW request is USART6_TX */ +#define LL_GPDMA1_REQUEST_UART7_RX 119U /*!< GPDMA1 HW request is UART7_RX */ +#define LL_GPDMA1_REQUEST_UART7_TX 120U /*!< GPDMA1 HW request is UART7_TX */ +#define LL_GPDMA1_REQUEST_UART8_RX 121U /*!< GPDMA1 HW request is UART8_RX */ +#define LL_GPDMA1_REQUEST_UART8_TX 122U /*!< GPDMA1 HW request is UART8_TX */ +#define LL_GPDMA1_REQUEST_UART9_RX 123U /*!< GPDMA1 HW request is UART9_RX */ +#define LL_GPDMA1_REQUEST_UART9_TX 124U /*!< GPDMA1 HW request is UART9_TX */ +#define LL_GPDMA1_REQUEST_USART10_RX 125U /*!< GPDMA1 HW request is USART10_RX */ +#define LL_GPDMA1_REQUEST_USART10_TX 126U /*!< GPDMA1 HW request is USART10_TX */ + +#define LL_GPDMA1_REQUEST_LPUART1_RX 127U /*!< GPDMA1 HW request is LPUART1_RX */ +#define LL_GPDMA1_REQUEST_LPUART1_TX 128U /*!< GPDMA1 HW request is LPUART1_TX */ + +#define LL_GPDMA1_REQUEST_SPDIFRX_CS 129U /*!< GPDMA1 HW request is SPDIFRX_CS */ +#define LL_GPDMA1_REQUEST_SPDIFRX_DT 130U /*!< GPDMA1 HW request is SPDIFRX_DT */ + +#define LL_GPDMA1_REQUEST_ADF1_FLT0 131U /*!< GPDMA1 HW request is ADF1_FLT0 */ + +#define LL_GPDMA1_REQUEST_MDF1_FLT0 132U /*!< GPDMA1 HW request is MDF1_FLT0 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT1 133U /*!< GPDMA1 HW request is MDF1_FLT1 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT2 134U /*!< GPDMA1 HW request is MDF1_FLT2 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT3 135U /*!< GPDMA1 HW request is MDF1_FLT3 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT4 136U /*!< GPDMA1 HW request is MDF1_FLT4 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT5 137U /*!< GPDMA1 HW request is MDF1_FLT5 */ + +#define LL_GPDMA1_REQUEST_UCPD1_TX 138U /*!< GPDMA1 HW request is UCPD1_TX */ +#define LL_GPDMA1_REQUEST_UCPD1_RX 139U /*!< GPDMA1 HW request is UCPD1_RX */ + +#define LL_GPDMA1_REQUEST_DCMI_PSSI 140U /*!< GPDMA1 HW request is DCMI_PSSI */ + +#define LL_GPDMA1_REQUEST_I3C1_TC 141U /*!< GPDMA1 HW request is I3C1_TC */ +#define LL_GPDMA1_REQUEST_I3C1_RS 142U /*!< GPDMA1 HW request is I3C1_RS */ + +#define LL_GPDMA1_REQUEST_I3C2_TC 143U /*!< GPDMA1 HW request is I3C2_TC */ +#define LL_GPDMA1_REQUEST_I3C2_RS 144U /*!< GPDMA1 HW request is I3C2_RS */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection + * @{ + */ +/* HPDMA1 triggers */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_FEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_LEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */ + +#define LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_FEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_LEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */ + +#define LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_FEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_LEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */ +#define LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */ + +#define LL_HPDMA1_TRIGGER_DMA2D_CTC 12U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC */ +#define LL_HPDMA1_TRIGGER_DMA2D_TC 13U /*!< HPDMA1 HW Trigger signal is DMA2D_TC */ +#define LL_HPDMA1_TRIGGER_DMA2D_TW 14U /*!< HPDMA1 HW Trigger signal is DMA2D_TW */ + +#define LL_HPDMA1_TRIGGER_JPEG_EOC 15U /*!< HPDMA1 HW Trigger signal is JPEG_EOC */ +#define LL_HPDMA1_TRIGGER_JPEG_IFNF 16U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF */ +#define LL_HPDMA1_TRIGGER_JPEG_IFT 17U /*!< HPDMA1 HW Trigger signal is JPEG_IFT */ +#define LL_HPDMA1_TRIGGER_JPEG_OFNE 18U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE */ +#define LL_HPDMA1_TRIGGER_JPEG_OFT 19U /*!< HPDMA1 HW Trigger signal is JPEG_OFT */ + +#define LL_HPDMA1_TRIGGER_LCD_LI 20U /*!< HPDMA1 HW Trigger signal is LCD_LI */ + +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_0 */ +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_1 */ +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_2 */ +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_3 */ + +#define LL_HPDMA1_TRIGGER_GFXTIM_3 25U /*!< HPDMA1 HW Trigger signal is GFXTIM_3 */ +#define LL_HPDMA1_TRIGGER_GFXTIM_2 26U /*!< HPDMA1 HW Trigger signal is GFXTIM_2 */ +#define LL_HPDMA1_TRIGGER_GFXTIM_1 27U /*!< HPDMA1 HW Trigger signal is GFXTIM_1 */ +#define LL_HPDMA1_TRIGGER_GFXTIM_0 28U /*!< HPDMA1 HW Trigger signal is GFXTIM_0 */ + +/* reserved 29U */ + +#define LL_HPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LL_HPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< HPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LL_HPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define LL_HPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< HPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define LL_HPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define LL_HPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< HPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#define LL_HPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< HPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define LL_HPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< HPDMA1 HW Trigger signal is LPTIM5_OUT */ + +/* reserved 38U */ + +#define LL_HPDMA1_TRIGGER_RTC_WKUP 39U /*!< HPDMA1 HW Trigger signal is RTC_WKUP */ + +#define LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< HPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */ +#define LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< HPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */ + +#define LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< HPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */ + +/* reserved 43U */ + +#define LL_HPDMA1_TRIGGER_TIM1_TRGO 44U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< HPDMA1 HW Trigger signal is TIM1_TRGO2 */ +#define LL_HPDMA1_TRIGGER_TIM2_TRGO 46U /*!< HPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM3_TRGO 47U /*!< HPDMA1 HW Trigger signal is TIM3_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM4_TRGO 48U /*!< HPDMA1 HW Trigger signal is TIM4_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM5_TRGO 49U /*!< HPDMA1 HW Trigger signal is TIM5_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM6_TRGO 50U /*!< HPDMA1 HW Trigger signal is TIM6_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM7_TRGO 51U /*!< HPDMA1 HW Trigger signal is TIM7_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM8_TRGO 52U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< HPDMA1 HW Trigger signal is TIM8_TRGO2 */ + +/* reserved 54U */ +/* reserved 55U */ +/* reserved 56U */ + +#define LL_HPDMA1_TRIGGER_TIM12_TRGO 57U /*!< HPDMA1 HW Trigger signal is TIM12_TRGO */ +#define LL_HPDMA1_TRIGGER_TIM15_TRGO 58U /*!< HPDMA1 HW Trigger signal is TIM15_TRGO */ + +/* reserved 59U */ + +#define LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ + +#define LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ + +/* reserved 92U */ + +#define LL_HPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< HPDMA1 HW Trigger signal is EXTIT0_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< HPDMA1 HW Trigger signal is EXTIT1_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< HPDMA1 HW Trigger signal is EXTIT2_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< HPDMA1 HW Trigger signal is EXTIT3_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< HPDMA1 HW Trigger signal is EXTIT4_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< HPDMA1 HW Trigger signal is EXTIT5_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< HPDMA1 HW Trigger signal is EXTIT6_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< HPDMA1 HW Trigger signal is EXTIT7_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< HPDMA1 HW Trigger signal is EXTIT8_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< HPDMA1 HW Trigger signal is EXTIT9_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< HPDMA1 HW Trigger signal is EXTIT10_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< HPDMA1 HW Trigger signal is EXTIT11_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< HPDMA1 HW Trigger signal is EXTIT12_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< HPDMA1 HW Trigger signal is EXTIT13_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< HPDMA1 HW Trigger signal is EXTIT14_SYNC */ +#define LL_HPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< HPDMA1 HW Trigger signal is EXTIT15_SYNC */ + + +/* GPDMA1 triggers */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND 0U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_FEND */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND 1U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_LEND */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC 2U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC 3U /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC */ + +#define LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND 4U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_FEND */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND 5U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_LEND */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC 6U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC 7U /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC */ + +#define LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND 8U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_FEND */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND 9U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_LEND */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC 10U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC */ +#define LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC 11U /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC */ + +#define LL_GPDMA1_TRIGGER_DMA2D_CTC 12U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define LL_GPDMA1_TRIGGER_DMA2D_TC 13U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define LL_GPDMA1_TRIGGER_DMA2D_TW 14U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ + +#define LL_GPDMA1_TRIGGER_JPEG_EOC 15U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define LL_GPDMA1_TRIGGER_JPEG_IFNF 16U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define LL_GPDMA1_TRIGGER_JPEG_IFT 17U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define LL_GPDMA1_TRIGGER_JPEG_OFNE 18U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define LL_GPDMA1_TRIGGER_JPEG_OFT 19U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ + +#define LL_GPDMA1_TRIGGER_LCD_LI 20U /*!< GPDMA1 HW Trigger signal is LCD_LI */ + +#define LL_GPDMA1_TRIGGER_GPU2D1_GP_0 21U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_0 */ +#define LL_GPDMA1_TRIGGER_GPU2D1_GP_1 22U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_1 */ +#define LL_GPDMA1_TRIGGER_GPU2D1_GP_2 23U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_2 */ +#define LL_GPDMA1_TRIGGER_GPU2D1_GP_3 24U /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_3 */ + +#define LL_GPDMA1_TRIGGER_GFXTIM_3 25U /*!< GPDMA1 HW Trigger signal is GFXTIM_3 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_2 26U /*!< GPDMA1 HW Trigger signal is GFXTIM_2 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_1 27U /*!< GPDMA1 HW Trigger signal is GFXTIM_1 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_0 28U /*!< GPDMA1 HW Trigger signal is GFXTIM_0 */ + +/* reserved 29U */ + +#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 30U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 31U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 32U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 33U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM3_CH1 34U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM3_CH2 35U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 36U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define LL_GPDMA1_TRIGGER_LPTIM5_OUT 37U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */ + +/* reserved 38U */ + +#define LL_GPDMA1_TRIGGER_RTC_WKUP 39U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */ + +#define LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 40U /*!< GPDMA1 HW Trigger signal is IT_R_WUP_ASYNC */ +#define LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 41U /*!< GPDMA1 HW Trigger signal is IT_T_WUP_ASYNC */ + +#define LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U /*!< GPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */ + +/* reserved 43U */ + +#define LL_GPDMA1_TRIGGER_TIM1_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM1_TRGO2 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */ +#define LL_GPDMA1_TRIGGER_TIM2_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM3_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM4_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM5_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM6_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM7_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM8_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM8_TRGO2 53U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO2 */ + +/* reserved 54U */ +/* reserved 55U */ +/* reserved 56U */ + +#define LL_GPDMA1_TRIGGER_TIM12_TRGO 57U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM15_TRGO 58U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ + +/* reserved 59U */ + +#define LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF 60U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF 61U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF 62U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF 63U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF 64U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF 65U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF 66U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF 67U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF 68U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF 69U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF 70U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF 71U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF 72U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF 73U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF 74U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF 75U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ + +#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 76U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 77U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 78U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 79U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 80U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 81U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 82U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 83U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 84U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 85U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 86U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 87U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 88U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 89U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 90U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 91U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ + +/* reserved 92U */ + +#define LL_GPDMA1_TRIGGER_EXTIT0_SYNC 93U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT1_SYNC 94U /*!< GPDMA1 HW Trigger signal is EXTIT1_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT2_SYNC 95U /*!< GPDMA1 HW Trigger signal is EXTIT2_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT3_SYNC 96U /*!< GPDMA1 HW Trigger signal is EXTIT3_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT4_SYNC 97U /*!< GPDMA1 HW Trigger signal is EXTIT4_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT5_SYNC 98U /*!< GPDMA1 HW Trigger signal is EXTIT5_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT6_SYNC 99U /*!< GPDMA1 HW Trigger signal is EXTIT6_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT7_SYNC 100U /*!< GPDMA1 HW Trigger signal is EXTIT7_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT8_SYNC 101U /*!< GPDMA1 HW Trigger signal is EXTIT8_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT9_SYNC 102U /*!< GPDMA1 HW Trigger signal is EXTIT9_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT10_SYNC 103U /*!< GPDMA1 HW Trigger signal is EXTIT10_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT11_SYNC 104U /*!< GPDMA1 HW Trigger signal is EXTIT11_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT12_SYNC 105U /*!< GPDMA1 HW Trigger signal is EXTIT12_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT13_SYNC 106U /*!< GPDMA1 HW Trigger signal is EXTIT13_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT14_SYNC 107U /*!< GPDMA1 HW Trigger signal is EXTIT14_SYNC */ +#define LL_GPDMA1_TRIGGER_EXTIT15_SYNC 108U /*!< GPDMA1 HW Trigger signal is EXTIT15_SYNC */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros + * @{ + */ +/** + * @brief Write a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval DMAx. + */ +#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? HPDMA1 : GPDMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval LL_DMA_CHANNEL_y. + */ +#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \ + LL_DMA_CHANNEL_15) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely. + * @param __DMA_INSTANCE__ DMAx. + * @param __CHANNEL__ LL_DMA_CHANNEL_y. + * @retval DMAx_Channely. + */ +#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? HPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? HPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? HPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? GPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? HPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? GPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? HPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? GPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? HPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? GPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? HPDMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? GPDMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? HPDMA1_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? GPDMA1_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \ + ? HPDMA1_Channel8 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \ + ? GPDMA1_Channel8 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \ + ? HPDMA1_Channel9 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \ + ? GPDMA1_Channel9 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ + ? HPDMA1_Channel10 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ + ? GPDMA1_Channel10 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\ + ? HPDMA1_Channel11 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\ + ? GPDMA1_Channel11 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\ + ? HPDMA1_Channel12 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\ + ? GPDMA1_Channel12 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\ + ? HPDMA1_Channel13 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\ + ? GPDMA1_Channel13 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\ + ? HPDMA1_Channel14 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\ + ? GPDMA1_Channel14 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_15)))\ + ? HPDMA1_Channel15 : GPDMA1_Channel15) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_SUSP | DMA_CCR_RESET)); +} + +/** + * @brief Check if channel is enabled or disabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN) + == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Reset channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR RESET LL_DMA_ResetChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET); +} + +/** + * @brief Suspend channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_SuspendChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Resume channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_ResumeChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Check if channel is suspended. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP) + == (DMA_CCR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Set linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes + * are always 0) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListBaseAddr) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA, + (LinkedListBaseAddr & DMA_CLBAR_LBA)); +} + +/** + * @brief Get linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0) + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA)); +} + +/** + * @brief Configure all parameters linked to channel control. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_ConfigControl\n + * CCR LAP LL_DMA_ConfigControl\n + * CCR LSM LL_DMA_ConfigControl + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or + * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); +} + +/** + * @brief Set priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority); +} + +/** + * @brief Get Channel priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO)); +} + +/** + * @brief Set linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_LAP, LinkAllocatedPort); +} + +/** + * @brief Get linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP)); +} + +/** + * @brief Set link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_SetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkStepMode This parameter can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode); +} + +/** + * @brief Get Link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_GetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM)); +} + +/** + * @brief Configure data transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n + * CTR1 DWX LL_DMA_ConfigTransfer\n + * CTR1 DHX LL_DMA_ConfigTransfer\n + * CTR1 DBX LL_DMA_ConfigTransfer\n + * CTR1 DINC LL_DMA_ConfigTransfer\n + * CTR1 SAP LL_DMA_ConfigTransfer\n + * CTR1 SBX LL_DMA_ConfigTransfer\n + * CTR1 PAM LL_DMA_ConfigTransfer\n + * CTR1 SINC LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DEST_WORD_PRESERVE or @ref LL_DMA_DEST_WORD_EXCHANGE + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE + * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or + * @ref LL_DMA_DEST_DATAWIDTH_WORD or @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or + * @ref LL_DMA_DATA_PACK_UNPACK + * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or + * @ref LL_DMA_SRC_DATAWIDTH_WORD or @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DAP | DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | \ + DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); +} + +/** + * @brief Configure source and destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n + * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcBurstLength Between 1 to 64 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength, + uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ + (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); +} + +#if defined(CPU_IN_SECURE_STATE) +/** + * @brief Set the static isolation attribute (CID) of the DMA channel. + * @note This API is used for HPDMA channels. + * @rmtoll CCIDCFGR SCID LL_DMA_SetStaticIsolation\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Cid This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_0 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_1 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_2 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_3 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_4 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_5 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_6 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetStaticIsolation(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Cid) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, + DMA_CCIDCFGR_SCID, Cid); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Get the static isolation attribute (CID) of the DMA channel. + * @note This API is used for HPDMA channels. + * @rmtoll CCIDCFGR SCID LL_DMA_GetStaticIsolation\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_0 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_1 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_2 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_3 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_4 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_5 + * @arg @ref LL_DMA_CHANNEL_STATIC_CID_6 + */ +__STATIC_INLINE uint32_t LL_DMA_GetStaticIsolation(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, + DMA_CCIDCFGR_SCID)); +} + +/** + * @brief Enable the isolation (CID filtering) of the DMA channel. + * @note This API is used for HPDMA channels. + * @rmtoll CCIDCFGR CFEN LL_DMA_EnableIsolation + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIsolation(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, DMA_CCIDCFGR_CFEN); +} + +/** + * @brief Disable the isolation (CID filtering) of the DMA channel. + * @note This API is used for HPDMA channels. + * @rmtoll CCIDCFGR CFEN LL_DMA_DisableIsolation + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIsolation(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, DMA_CCIDCFGR_CFEN); +} + +/** + * @brief Check isolation (CID filtering) of the DMA channel. + * @note This API is used for HPDMA channels. + * @rmtoll CCIDCFGR CFEN LL_DMA_IsEnabledIsolation + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIsolation(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, + DMA_CCIDCFGR_CFEN) == (DMA_CCIDCFGR_CFEN)) ? 1UL : 0UL); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Configure all secure parameters linked to DMA channel. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC + * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC + * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel)); + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); +} + +/** + * @brief Enable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Check security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC) + == (DMA_CTR1_DSEC)) ? 1UL : 0UL); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Enable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Check security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) + == (DMA_CTR1_SSEC)) ? 1UL : 0UL); +} + +/** + * @brief Set destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP, + DestAllocatedPort); +} + +/** + * @brief Get destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP)); +} + +/** + * @brief Set destination word exchange. + * @rmtoll CTR1 DWX LL_DMA_SetDestWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestWordExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_WORD_PRESERVE + * @arg @ref LL_DMA_DEST_WORD_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestWordExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX, + DestWordExchange); +} + +/** + * @brief Get destination word exchange. + * @rmtoll CTR1 DWX LL_DMA_GetDestWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_WORD_PRESERVE + * @arg @ref LL_DMA_DEST_WORD_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX)); +} + +/** + * @brief Set destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestHWordExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX, + DestHWordExchange); +} + +/** + * @brief Get destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX)); +} + +/** + * @brief Set destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX, + DestByteExchange); +} + +/** + * @brief Get destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX)); +} + +/** + * @brief Set source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX, + SrcByteExchange); +} + +/** + * @brief Get source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX)); +} + +/** + * @brief Set destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1, + ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1); +} + +/** + * @brief Get destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 1 to 64. + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); +} + +/** + * @brief Set destination increment mode. + * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestInc This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); +} + +/** + * @brief Get destination increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC)); +} + +/** + * @brief Set destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, + DestDataWidth); +} + +/** + * @brief Get destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); +} + +/** + * @brief Set source allocated port. + * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP, + SrcAllocatedPort); +} + +/** + * @brief Get source allocated port. + * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP)); +} + +/** + * @brief Set data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, + DataAlignment); +} + +/** + * @brief Get data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); +} + +/** + * @brief Set source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1, + ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1); +} + +/** + * @brief Get source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); +} + +/** + * @brief Set source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcInc This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc); +} + +/** + * @brief Get source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC)); +} + +/** + * @brief Set source data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, + SrcDataWidth); +} + +/** + * @brief Get Source Data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); +} + +/** + * @brief Configure channel transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n + * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 SWREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 PFREQ LL_DMA_ConfigChannelTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or + * @ref LL_DMA_TRIG_POLARITY_FALLING + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or + * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_NORMAL or @ref LL_DMA_PFCTRL + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ | + DMA_CTR2_PFREQ), Configuration); +} + +/** + * @brief Set transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TransferEventMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM, + TransferEventMode); +} + +/** + * @brief Get transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM)); +} + +/** + * @brief Set trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TriggerPolarity This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL, + TriggerPolarity); +} + +/** + * @brief Get trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL)); +} + +/** + * @brief Set trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TriggerMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM, + TriggerMode); +} + +/** + * @brief Get trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM)); +} + +/** + * @brief Set destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction); +} + +/** + * @brief Get destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ)); +} + +/** + * @brief Set block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkHWRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ, + BlkHWRequest); +} + +/** + * @brief Get block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ)); +} + +/** + * @brief Set hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX + * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX + * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI1 + * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI2 + * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI3 + * @arg @ref LL_HPDMA1_REQUEST_FMC2_TXRX + * @arg @ref LL_HPDMA1_REQUEST_FMC2_BCH + * @arg @ref LL_HPDMA1_REQUEST_ADC1 + * @arg @ref LL_HPDMA1_REQUEST_ADC2 + * @arg @ref LL_HPDMA1_REQUEST_CRYP_IN + * @arg @ref LL_HPDMA1_REQUEST_CRYP_OUT + * @arg @ref LL_HPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_HPDMA1_REQUEST_SAES_IN + * @arg @ref LL_HPDMA1_REQUEST_HASH_IN + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM2_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM4_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM8_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM16_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM17_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM18_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM18_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM18_COM + * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_HPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI5_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI5_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI6_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI6_TX + * @arg @ref LL_HPDMA1_REQUEST_SAI1_A + * @arg @ref LL_HPDMA1_REQUEST_SAI1_B + * @arg @ref LL_HPDMA1_REQUEST_SAI1_A + * @arg @ref LL_HPDMA1_REQUEST_SAI1_B + * @arg @ref LL_HPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_HPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_HPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_HPDMA1_REQUEST_I2C4_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C4_TX + * @arg @ref LL_HPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_HPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_HPDMA1_REQUEST_I3C2_RX + * @arg @ref LL_HPDMA1_REQUEST_I3C2_TX + * @arg @ref LL_HPDMA1_REQUEST_USART1_RX + * @arg @ref LL_HPDMA1_REQUEST_USART1_TX + * @arg @ref LL_HPDMA1_REQUEST_USART2_RX + * @arg @ref LL_HPDMA1_REQUEST_USART2_TX + * @arg @ref LL_HPDMA1_REQUEST_USART3_RX + * @arg @ref LL_HPDMA1_REQUEST_USART3_TX + * @arg @ref LL_HPDMA1_REQUEST_UART4_RX + * @arg @ref LL_HPDMA1_REQUEST_UART4_TX + * @arg @ref LL_HPDMA1_REQUEST_UART5_RX + * @arg @ref LL_HPDMA1_REQUEST_UART5_TX + * @arg @ref LL_HPDMA1_REQUEST_USART6_RX + * @arg @ref LL_HPDMA1_REQUEST_USART6_TX + * @arg @ref LL_HPDMA1_REQUEST_UART7_RX + * @arg @ref LL_HPDMA1_REQUEST_UART7_TX + * @arg @ref LL_HPDMA1_REQUEST_UART8_RX + * @arg @ref LL_HPDMA1_REQUEST_UART8_TX + * @arg @ref LL_HPDMA1_REQUEST_UART9_RX + * @arg @ref LL_HPDMA1_REQUEST_UART9_TX + * @arg @ref LL_HPDMA1_REQUEST_USART10_RX + * @arg @ref LL_HPDMA1_REQUEST_USART10_TX + * @arg @ref LL_HPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_HPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_CS + * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_DT + * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT0 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT1 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT2 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT3 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT4 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT5 + * @arg @ref LL_HPDMA1_REQUEST_UCPD1_TX + * @arg @ref LL_HPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_HPDMA1_REQUEST_DCMI_PSSI + * @arg @ref LL_HPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_HPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_HPDMA1_REQUEST_I3C2_TC + * @arg @ref LL_HPDMA1_REQUEST_I3C2_RS + * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX + * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI3 + * @arg @ref LL_GPDMA1_REQUEST_FMC2_TXRX + * @arg @ref LL_GPDMA1_REQUEST_FMC2_BCH + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC2 + * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN + * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM18_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM18_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM18_COM + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX + * @arg @ref LL_GPDMA1_REQUEST_UART7_RX + * @arg @ref LL_GPDMA1_REQUEST_UART7_TX + * @arg @ref LL_GPDMA1_REQUEST_UART8_RX + * @arg @ref LL_GPDMA1_REQUEST_UART8_TX + * @arg @ref LL_GPDMA1_REQUEST_UART9_RX + * @arg @ref LL_GPDMA1_REQUEST_UART9_TX + * @arg @ref LL_GPDMA1_REQUEST_USART10_RX + * @arg @ref LL_GPDMA1_REQUEST_USART10_TX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_DT + * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_CS + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request); +} + +/** + * @brief Get hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX + * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX + * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI1 + * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI2 + * @arg @ref LL_HPDMA1_REQUEST_OCTOSPI3 + * @arg @ref LL_HPDMA1_REQUEST_FMC2_TXRX + * @arg @ref LL_HPDMA1_REQUEST_FMC2_BCH + * @arg @ref LL_HPDMA1_REQUEST_ADC1 + * @arg @ref LL_HPDMA1_REQUEST_ADC2 + * @arg @ref LL_HPDMA1_REQUEST_CRYP_IN + * @arg @ref LL_HPDMA1_REQUEST_CRYP_OUT + * @arg @ref LL_HPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_HPDMA1_REQUEST_SAES_IN + * @arg @ref LL_HPDMA1_REQUEST_HASH_IN + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM2_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM4_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH3 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_CH4 + * @arg @ref LL_HPDMA1_REQUEST_TIM8_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM8_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM15_CH2 + * @arg @ref LL_HPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_HPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM16_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM17_COM + * @arg @ref LL_HPDMA1_REQUEST_TIM18_CH1 + * @arg @ref LL_HPDMA1_REQUEST_TIM18_UP + * @arg @ref LL_HPDMA1_REQUEST_TIM18_COM + * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_HPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI5_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI5_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI6_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI6_TX + * @arg @ref LL_HPDMA1_REQUEST_SAI1_A + * @arg @ref LL_HPDMA1_REQUEST_SAI1_B + * @arg @ref LL_HPDMA1_REQUEST_SAI1_A + * @arg @ref LL_HPDMA1_REQUEST_SAI1_B + * @arg @ref LL_HPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_HPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_HPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_HPDMA1_REQUEST_I2C4_RX + * @arg @ref LL_HPDMA1_REQUEST_I2C4_TX + * @arg @ref LL_HPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_HPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_HPDMA1_REQUEST_I3C2_RX + * @arg @ref LL_HPDMA1_REQUEST_I3C2_TX + * @arg @ref LL_HPDMA1_REQUEST_USART1_RX + * @arg @ref LL_HPDMA1_REQUEST_USART1_TX + * @arg @ref LL_HPDMA1_REQUEST_USART2_RX + * @arg @ref LL_HPDMA1_REQUEST_USART2_TX + * @arg @ref LL_HPDMA1_REQUEST_USART3_RX + * @arg @ref LL_HPDMA1_REQUEST_USART3_TX + * @arg @ref LL_HPDMA1_REQUEST_UART4_RX + * @arg @ref LL_HPDMA1_REQUEST_UART4_TX + * @arg @ref LL_HPDMA1_REQUEST_UART5_RX + * @arg @ref LL_HPDMA1_REQUEST_UART5_TX + * @arg @ref LL_HPDMA1_REQUEST_USART6_RX + * @arg @ref LL_HPDMA1_REQUEST_USART6_TX + * @arg @ref LL_HPDMA1_REQUEST_UART7_RX + * @arg @ref LL_HPDMA1_REQUEST_UART7_TX + * @arg @ref LL_HPDMA1_REQUEST_UART8_RX + * @arg @ref LL_HPDMA1_REQUEST_UART8_TX + * @arg @ref LL_HPDMA1_REQUEST_UART9_RX + * @arg @ref LL_HPDMA1_REQUEST_UART9_TX + * @arg @ref LL_HPDMA1_REQUEST_USART10_RX + * @arg @ref LL_HPDMA1_REQUEST_USART10_TX + * @arg @ref LL_HPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_HPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_CS + * @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_DT + * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT0 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT1 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT2 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT3 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT4 + * @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT5 + * @arg @ref LL_HPDMA1_REQUEST_UCPD1_TX + * @arg @ref LL_HPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_HPDMA1_REQUEST_DCMI_PSSI + * @arg @ref LL_HPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_HPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_HPDMA1_REQUEST_I3C2_TC + * @arg @ref LL_HPDMA1_REQUEST_I3C2_RS + * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX + * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI3 + * @arg @ref LL_GPDMA1_REQUEST_FMC2_TXRX + * @arg @ref LL_GPDMA1_REQUEST_FMC2_BCH + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC2 + * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN + * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM18_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM18_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM18_COM + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX + * @arg @ref LL_GPDMA1_REQUEST_UART7_RX + * @arg @ref LL_GPDMA1_REQUEST_UART7_TX + * @arg @ref LL_GPDMA1_REQUEST_UART8_RX + * @arg @ref LL_GPDMA1_REQUEST_UART8_TX + * @arg @ref LL_GPDMA1_REQUEST_UART9_RX + * @arg @ref LL_GPDMA1_REQUEST_UART9_TX + * @arg @ref LL_GPDMA1_REQUEST_USART10_RX + * @arg @ref LL_GPDMA1_REQUEST_USART10_TX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_DT + * @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_CS + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL)); +} + +/** + * @brief Set hardware trigger. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT + * @arg @ref LL_HPDMA1_TRIGGER_LCD_LI + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_0 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_1 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_2 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_2 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_1 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM5_OUT + * @arg @ref LL_HPDMA1_TRIGGER_RTC_WKUP + * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC + * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC + * @arg @ref LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO2 + * @arg @ref LL_HPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM3_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM4_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM5_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM6_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM7_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO2 + * @arg @ref LL_HPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT0_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT1_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT2_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT3_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT4_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT5_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT6_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT7_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT8_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT9_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT10_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT11_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT12_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT13_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT14_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT15_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT + * @arg @ref LL_GPDMA1_TRIGGER_LCD_LI + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_0 + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_1 + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_2 + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_3 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_3 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_2 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_1 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_0 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT1_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT2_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT3_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT4_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT5_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT6_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT7_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT8_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT9_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT10_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT11_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT12_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT13_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT14_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT15_SYNC + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL, + (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); +} + +/** + * @brief Get hardware triggers. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT + * @arg @ref LL_HPDMA1_TRIGGER_LCD_LI + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_0 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_1 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_2 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_2 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_1 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_HPDMA1_TRIGGER_LPTIM5_OUT + * @arg @ref LL_HPDMA1_TRIGGER_RTC_WKUP + * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC + * @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC + * @arg @ref LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO2 + * @arg @ref LL_HPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM3_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM4_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM5_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM6_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM7_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO2 + * @arg @ref LL_HPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT0_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT1_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT2_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT3_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT4_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT5_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT6_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT7_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT8_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT9_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT10_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT11_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT12_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT13_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT14_SYNC + * @arg @ref LL_HPDMA1_TRIGGER_EXTIT15_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT + * @arg @ref LL_GPDMA1_TRIGGER_LCD_LI + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_0 + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_1 + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_2 + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_3 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_3 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_2 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_1 + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_0 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT1_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT2_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT3_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT4_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT5_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT6_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT7_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT8_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT9_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT10_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT11_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT12_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT13_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT14_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT15_SYNC + */ +__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); +} + +/** + * @brief Set DMA transfer mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 PFREQ LL_DMA_SetTransferMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_NORMAL + * @arg @ref LL_DMA_PFCTRL + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_PFREQ, + Mode & DMA_CTR2_PFREQ); +} + +/** + * @brief Get DMA transfer mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetTransferMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_NORMAL + * @arg @ref LL_DMA_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_PFREQ)); +} + +/** + * @brief Configure addresses update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); +} + +/** + * @brief Configure DMA Block number of data and repeat Count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n + * CBR1 BRC LL_DMA_ConfigBlkCounters + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkDataLength Block transfer length + Value between 0 to 0x0000FFFF + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength, + uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos))); +} + +/** + * @brief Set block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC, + BlkRptDestAddrUpdate); +} + +/** + * @brief Get block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC)); +} + +/** + * @brief Set block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptSrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC, + BlkRptSrcAddrUpdate); +} + +/** + * @brief Get block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC)); +} + +/** + * @brief Set destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC, + DestAddrUpdate); +} + +/** + * @brief Get destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC)); +} + +/** + * @brief Set source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC, + SrcAddrUpdate); +} + +/** + * @brief Get source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC)); +} + +/** + * @brief Set block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC, + (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); +} + +/** + * @brief Get block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x000007FF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos); +} + +/** + * @brief Set block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkDataLength Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT, + BlkDataLength); +} + +/** + * @brief Get block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT)); +} + +/** + * @brief Configure the source and destination addresses. + * @note This API is used for all available DMA channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n + * CDAR DA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t + DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Set source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_SetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); +} + +/** + * @brief Get source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_GetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR)); +} + +/** + * @brief Set destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_SetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Get destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_GetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR)); +} + +/** + * @brief Configure source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n + * CTR3 SAO LL_DMA_ConfigAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrOffset Between 0 to 0x00001FFF + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset, + uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Set destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO, + ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Get destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); +} + +/** + * @brief Set source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, + SrcAddrOffset & DMA_CTR3_SAO); +} + +/** + * @brief Get source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); +} + +/** + * @brief Configure the block repeated source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n + * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO)); +} + +/** + * @brief Set block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO)); +} + +/** + * @brief Get block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); +} + +/** + * @brief Set block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO, + BlkRptSrcAddrOffset); +} + +/** + * @brief Get block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO)); +} + +/** + * @brief Configure registers update and node address offset during the link transfer. + * @note This API is used for all available DMA channels. + * For linear addressing channels, UT3 and UB2 fields are discarded. + * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param RegistersUpdate This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_UPDATE_CTR1 + * @arg @ref LL_DMA_UPDATE_CTR2 + * @arg @ref LL_DMA_UPDATE_CBR1 + * @arg @ref LL_DMA_UPDATE_CSAR + * @arg @ref LL_DMA_UPDATE_CDAR + * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CLLR + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ + DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); +} + +/** + * @brief Enable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Disable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Check if CTR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) + == (DMA_CLLR_UT1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Disable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Check if CTR2 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2) + == (DMA_CLLR_UT2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Disable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Check if CBR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) + == (DMA_CLLR_UB1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Disable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Check if CSAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) + == (DMA_CLLR_USA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Disable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Check if CDAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) + == (DMA_CLLR_UDA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); +} + +/** + * @brief Disable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); +} + +/** + * @brief Check if CTR3 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) + == (DMA_CLLR_UT3)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); +} + +/** + * @brief Disable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); +} + +/** + * @brief Check if CBR2 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2) + == (DMA_CLLR_UB2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Disable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Check if CLLR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) + == (DMA_CLLR_ULL)) ? 1UL : 0UL); +} + +/** + * @brief Set linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA, + (LinkedListAddrOffset & DMA_CLLR_LA)); +} + +/** + * @brief Get linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFC. + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); +} + +/** + * @brief Get FIFO level. + * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x000000FF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, + DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Enable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Check if DMA channel secure is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) + == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +/** + * @brief Enable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Check if DMA Channel privilege is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) + == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Enable the DMA channel lock attributes. + * @note This API is used for all available DMA channels. + * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Check if DMA channel attributes are locked. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) + == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management Flag Management + * @{ + */ + +/** + * @brief Clear trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF); +} + +/** + * @brief Clear suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF); +} + +/** + * @brief Clear user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF); +} + +/** + * @brief Clear link transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF); +} + +/** + * @brief Clear data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF); +} + +/** + * @brief Clear half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF); +} + +/** + * @brief Clear transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF); +} + +/** + * @brief Get trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF) + == (DMA_CSR_TOF)) ? 1UL : 0UL); +} + +/** + * @brief Get suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF) + == (DMA_CSR_SUSPF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF) + == (DMA_CSR_USEF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF) + == (DMA_CSR_ULEF)) ? 1UL : 0UL); +} + +/** + * @brief Get data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF) + == (DMA_CSR_DTEF)) ? 1UL : 0UL); +} + +/** + * @brief Get half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF) + == (DMA_CSR_HTF)) ? 1UL : 0UL); +} + +/** + * @brief Get transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF) + == (DMA_CSR_TCF)) ? 1UL : 0UL); +} + +/** + * @brief Get idle flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF) + == (DMA_CSR_IDLEF)) ? 1UL : 0UL); +} + +/** + * @brief Check if nsecure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) + == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Check if secure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) + == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} +#endif /* CPU_IN_SECURE_STATE */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_EnableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Enable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Enable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_EnableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Enable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Enable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Enable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_DisableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Disable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Disable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_DisableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Disable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Disable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Disable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Check if trigger overrun interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE) + == DMA_CCR_TOIE) ? 1UL : 0UL); +} + +/** + * @brief Check if suspension interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE) + == DMA_CCR_SUSPIE) ? 1UL : 0UL); +} + +/** + * @brief Check if user setting error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE) + == DMA_CCR_USEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if update link transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE) + == DMA_CCR_ULEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if data transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE) + == DMA_CCR_DTEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if half transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE) + == DMA_CCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE) + == DMA_CCR_TCIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); +void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct); + +uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, + LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, + LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); +void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPDMA1 || HPDMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32N6xx_LL_DMA_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_exti.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_exti.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_exti.h (revision 16) @@ -0,0 +1,2896 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_exti.h + * @author GPM Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_EXTI_H +#define STM32N6xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_64_95; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< ALL Extended line */ + +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ +#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ +#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ +#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ +#define LL_EXTI_LINE_49 EXTI_IMR2_IM49 /*!< Extended line 49 */ +#define LL_EXTI_LINE_50 EXTI_IMR2_IM50 /*!< Extended line 50 */ +#define LL_EXTI_LINE_51 EXTI_IMR2_IM51 /*!< Extended line 51 */ +#define LL_EXTI_LINE_52 EXTI_IMR2_IM52 /*!< Extended line 52 */ +#define LL_EXTI_LINE_53 EXTI_IMR2_IM53 /*!< Extended line 53 */ +#define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */ +#define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */ +#define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */ +#define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */ +#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ +#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ +#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ +#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ +#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_64 EXTI_IMR3_IM64 /*!< Extended line 64 */ +#define LL_EXTI_LINE_65 EXTI_IMR3_IM65 /*!< Extended line 65 */ +#define LL_EXTI_LINE_66 EXTI_IMR3_IM66 /*!< Extended line 66 */ +#define LL_EXTI_LINE_68 EXTI_IMR3_IM68 /*!< Extended line 68 */ +#define LL_EXTI_LINE_69 EXTI_IMR3_IM69 /*!< Extended line 69 */ +#define LL_EXTI_LINE_70 EXTI_IMR3_IM70 /*!< Extended line 70 */ +#define LL_EXTI_LINE_71 EXTI_IMR3_IM71 /*!< Extended line 71 */ +#define LL_EXTI_LINE_72 EXTI_IMR3_IM72 /*!< Extended line 72 */ +#define LL_EXTI_LINE_73 EXTI_IMR3_IM73 /*!< Extended line 73 */ +#define LL_EXTI_LINE_74 EXTI_IMR3_IM74 /*!< Extended line 74 */ +#define LL_EXTI_LINE_77 EXTI_IMR3_IM77 /*!< Extended line 77 */ +#define LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM /*!< All Extended line not reserved*/ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT + * @{ + */ +#define LL_EXTI_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_EXTI_EXTI_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ +#define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +#define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ +#define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +#define LL_EXTI_EXTI_PORTN EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT N */ +#define LL_EXTI_EXTI_PORTO (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT O */ +#define LL_EXTI_EXTI_PORTP (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT P */ +#define LL_EXTI_EXTI_PORTQ (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT Q */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE + * @{ + */ +#define LL_EXTI_EXTI_LINE0 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE1 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE2 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE3 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE4 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE5 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE6 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE7 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE8 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE9 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE10 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE11 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE12 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE13 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE14 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE15 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ +/** + * @} + */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR3 IMx LL_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR3 IMx LL_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR3 IMx LL_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_EnableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_DisableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR3, ExtiLine); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll RTSR3 RTx LL_EXTI_IsEnabledRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR3 FTx LL_EXTI_EnableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR3 FTx LL_EXTI_DisableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR3, ExtiLine); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll FTSR3 FTx LL_EXTI_IsEnabledFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 64 to 95 + * @note If the interrupt is enabled on this line in the EXTI_IMR3, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR3 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR3 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER3, ExtiLine); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_IsActiveFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR3 FPIFx LL_EXTI_IsActiveFallingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ReadFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR2, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR3 FPIFx LL_EXTI_ReadFallingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR3, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ClearFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR3 FPIFx LL_EXTI_ClearFallingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR3, ExtiLine); +} + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_IsActiveRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 64 to 95 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR3 RPIFx LL_EXTI_IsActiveRisingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ReadRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR2, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 64 to 95 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR3 RPIFx LL_EXTI_ReadRisingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR3, ExtiLine)); +} + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ClearRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_56 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 64 to 95 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR3 RPIFx LL_EXTI_ClearRisingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR3, ExtiLine); +} + +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_PORTA + * @arg @ref LL_EXTI_EXTI_PORTB + * @arg @ref LL_EXTI_EXTI_PORTC + * @arg @ref LL_EXTI_EXTI_PORTD + * @arg @ref LL_EXTI_EXTI_PORTE + * @arg @ref LL_EXTI_EXTI_PORTF + * @arg @ref LL_EXTI_EXTI_PORTG + * @arg @ref LL_EXTI_EXTI_PORTH + * @arg @ref LL_EXTI_EXTI_PORTN + * @arg @ref LL_EXTI_EXTI_PORTO + * @arg @ref LL_EXTI_EXTI_PORTP + * @arg @ref LL_EXTI_EXTI_PORTQ + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_LINE0 + * @arg @ref LL_EXTI_EXTI_LINE1 + * @arg @ref LL_EXTI_EXTI_LINE2 + * @arg @ref LL_EXTI_EXTI_LINE3 + * @arg @ref LL_EXTI_EXTI_LINE4 + * @arg @ref LL_EXTI_EXTI_LINE5 + * @arg @ref LL_EXTI_EXTI_LINE6 + * @arg @ref LL_EXTI_EXTI_LINE7 + * @arg @ref LL_EXTI_EXTI_LINE8 + * @arg @ref LL_EXTI_EXTI_LINE9 + * @arg @ref LL_EXTI_EXTI_LINE10 + * @arg @ref LL_EXTI_EXTI_LINE11 + * @arg @ref LL_EXTI_EXTI_LINE12 + * @arg @ref LL_EXTI_EXTI_LINE13 + * @arg @ref LL_EXTI_EXTI_LINE14 + * @arg @ref LL_EXTI_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), + Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_LINE0 + * @arg @ref LL_EXTI_EXTI_LINE1 + * @arg @ref LL_EXTI_EXTI_LINE2 + * @arg @ref LL_EXTI_EXTI_LINE3 + * @arg @ref LL_EXTI_EXTI_LINE4 + * @arg @ref LL_EXTI_EXTI_LINE5 + * @arg @ref LL_EXTI_EXTI_LINE6 + * @arg @ref LL_EXTI_EXTI_LINE7 + * @arg @ref LL_EXTI_EXTI_LINE8 + * @arg @ref LL_EXTI_EXTI_LINE9 + * @arg @ref LL_EXTI_EXTI_LINE10 + * @arg @ref LL_EXTI_EXTI_LINE11 + * @arg @ref LL_EXTI_EXTI_LINE12 + * @arg @ref LL_EXTI_EXTI_LINE13 + * @arg @ref LL_EXTI_EXTI_LINE14 + * @arg @ref LL_EXTI_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_EXTI_PORTA + * @arg @ref LL_EXTI_EXTI_PORTB + * @arg @ref LL_EXTI_EXTI_PORTC + * @arg @ref LL_EXTI_EXTI_PORTD + * @arg @ref LL_EXTI_EXTI_PORTE + * @arg @ref LL_EXTI_EXTI_PORTF + * @arg @ref LL_EXTI_EXTI_PORTG + * @arg @ref LL_EXTI_EXTI_PORTH + * @arg @ref LL_EXTI_EXTI_PORTN + * @arg @ref LL_EXTI_EXTI_PORTO + * @arg @ref LL_EXTI_EXTI_PORTP + * @arg @ref LL_EXTI_EXTI_PORTQ + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], + (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management + * @{ + */ + +#if defined CPU_IN_SECURE_STATE + +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_EnableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 32 to 63 + * @rmtoll SECCFGR2 SECx LL_EXTI_EnableSecure_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 64 to 95 + * @rmtoll SECCFGR3 SECx LL_EXTI_EnableSecure_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_DisableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 32 to 63 + * @rmtoll SECCFGR2 SECx LL_EXTI_DisableSecure_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 64 to 95 + * @rmtoll SECCFGR3 SECx LL_EXTI_DisableSecure_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR3, ExtiLine); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 32 to 63 + * @rmtoll SECCFGR2 SECx LL_EXTI_IsEnabledSecure_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 64 to 95 + * @rmtoll SECCFGR3 SECx LL_EXTI_IsEnabledSecure_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_EnablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 32 to 63 + * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_EnablePrivilege_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 64 to 95 + * @rmtoll PRIVCFGR3 PRIVx LL_EXTI_EnablePrivilege_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_DisablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 32 to 63 + * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_DisablePrivilege_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 64 to 95 + * @rmtoll PRIVCFGR3 PRIVx LL_EXTI_DisablePrivilege_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_IsEnabledPrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 32 to 63 + * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_IsEnabledPrivilege_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 64 to 95 + * @rmtoll PRIVCFGR3 PRIVx LL_EXTI_IsEnabledPrivilege_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined CPU_IN_SECURE_STATE +/** + * @brief Lock the secure and privilege configuration registers. + * @rmtoll LOCKR LOCK LL_EXTI_LockAttributes + * @retval None + */ +__STATIC_INLINE void LL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @rmtoll LOCKR LOCK LL_EXTI_GetLockAttributes + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +__STATIC_INLINE uint32_t LL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} +#endif /* CPU_IN_SECURE_STATE */ + + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_LL_EXTI_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_gpio.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_gpio.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_gpio.h (revision 16) @@ -0,0 +1,1537 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_gpio.h + * @author GPM Application Team + * @brief Header for ll_gpio.c module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_GPIO_H +#define STM32N6xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPION) || defined (GPIOO) || defined (GPIOP) || defined (GPIOQ) +/** @defgroup GPIO_LL GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ + LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ + LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ + LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ + LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ + LL_GPIO_PIN_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_DELAY Delay + * @{ + */ +#define LL_GPIO_DELAY_0 (0x0000000U) /*!< Select no delay */ +#define LL_GPIO_DELAY_300 (0x0000001U) /*!< Select 0.3 ns */ +#define LL_GPIO_DELAY_500 (0x0000002U) /*!< Select 0.5 ns */ +#define LL_GPIO_DELAY_750 (0x0000003U) /*!< Select 0.75 ns */ +#define LL_GPIO_DELAY_1000 (0x0000004U) /*!< Select 1 ns */ +#define LL_GPIO_DELAY_1250 (0x0000005U) /*!< Select 1.25 ns */ +#define LL_GPIO_DELAY_1500 (0x0000006U) /*!< Select 1.5 ns */ +#define LL_GPIO_DELAY_1750 (0x0000007U) /*!< Select 1.75 ns */ +#define LL_GPIO_DELAY_2000 (0x0000008U) /*!< Select 2 ns */ +#define LL_GPIO_DELAY_2250 (0x0000009U) /*!< Select 2.25 ns */ +#define LL_GPIO_DELAY_2500 (0x000000AU) /*!< Select 2.5 ns */ +#define LL_GPIO_DELAY_2750 (0x000000BU) /*!< Select 2.75 ns */ +#define LL_GPIO_DELAY_3000 (0x000000CU) /*!< Select 3 ns */ +#define LL_GPIO_DELAY_3250 (0x000000DU) /*!< Select 3.25 ns */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) + >> (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @brief Lock resource configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a security configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockResourcePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + MODIFY_REG(GPIOx->RCFGLOCKR, 0U, PinMask); +} + +/** + * @brief Return 1 if all resource pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsResourcePinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->RCFGLOCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the resource pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyResourcePinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((GPIOx->RCFGLOCKR == 0x00000000U) ? 0UL : 1UL); +} + + +/** + * @brief Configure gpio delay of a dedicated pin from 0 to 7 for a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Delay This parameter can be one of the following values: + * @arg @ref LL_GPIO_DELAY_0 + * @arg @ref LL_GPIO_DELAY_300 + * @arg @ref LL_GPIO_DELAY_500 + * @arg @ref LL_GPIO_DELAY_750 + * @arg @ref LL_GPIO_DELAY_1000 + * @arg @ref LL_GPIO_DELAY_1250 + * @arg @ref LL_GPIO_DELAY_1500 + * @arg @ref LL_GPIO_DELAY_1750 + * @arg @ref LL_GPIO_DELAY_2000 + * @arg @ref LL_GPIO_DELAY_2250 + * @arg @ref LL_GPIO_DELAY_2500 + * @arg @ref LL_GPIO_DELAY_2750 + * @arg @ref LL_GPIO_DELAY_3000 + * @arg @ref LL_GPIO_DELAY_3250 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetDelayPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Delay) +{ + MODIFY_REG(GPIOx->DELAYR[0], GPIO_DELAYRL_DLY0 << (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos), + (Delay << (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos))); +} + +/** + * @brief Return gpio delay of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_DELAY_0 + * @arg @ref LL_GPIO_DELAY_300 + * @arg @ref LL_GPIO_DELAY_500 + * @arg @ref LL_GPIO_DELAY_750 + * @arg @ref LL_GPIO_DELAY_1000 + * @arg @ref LL_GPIO_DELAY_1250 + * @arg @ref LL_GPIO_DELAY_1500 + * @arg @ref LL_GPIO_DELAY_1750 + * @arg @ref LL_GPIO_DELAY_2000 + * @arg @ref LL_GPIO_DELAY_2250 + * @arg @ref LL_GPIO_DELAY_2500 + * @arg @ref LL_GPIO_DELAY_2750 + * @arg @ref LL_GPIO_DELAY_3000 + * @arg @ref LL_GPIO_DELAY_3250 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetDelayPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DELAYR[0], (GPIO_DELAYRL_DLY0 << (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos)); +} + +/** + * @brief Configure gpio delay of a dedicated pin from 8 to 15 for a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Delay This parameter can be one of the following values: + * @arg @ref LL_GPIO_DELAY_0 + * @arg @ref LL_GPIO_DELAY_300 + * @arg @ref LL_GPIO_DELAY_500 + * @arg @ref LL_GPIO_DELAY_750 + * @arg @ref LL_GPIO_DELAY_1000 + * @arg @ref LL_GPIO_DELAY_1250 + * @arg @ref LL_GPIO_DELAY_1500 + * @arg @ref LL_GPIO_DELAY_1750 + * @arg @ref LL_GPIO_DELAY_2000 + * @arg @ref LL_GPIO_DELAY_2250 + * @arg @ref LL_GPIO_DELAY_2500 + * @arg @ref LL_GPIO_DELAY_2750 + * @arg @ref LL_GPIO_DELAY_3000 + * @arg @ref LL_GPIO_DELAY_3250 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetDelayPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Delay) +{ + MODIFY_REG(GPIOx->DELAYR[1], GPIO_DELAYRH_DLY8 << ((POSITION_VAL(Pin) & 0x07U) * GPIO_DELAYRH_DLY9_Pos), + (Delay << ((POSITION_VAL(Pin) & 0x07U) * GPIO_DELAYRH_DLY9_Pos))); +} + +/** + * @brief Return gpio delay of a dedicated pin from 8 to 15 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_DELAY_0 + * @arg @ref LL_GPIO_DELAY_300 + * @arg @ref LL_GPIO_DELAY_500 + * @arg @ref LL_GPIO_DELAY_750 + * @arg @ref LL_GPIO_DELAY_1000 + * @arg @ref LL_GPIO_DELAY_1250 + * @arg @ref LL_GPIO_DELAY_1500 + * @arg @ref LL_GPIO_DELAY_1750 + * @arg @ref LL_GPIO_DELAY_2000 + * @arg @ref LL_GPIO_DELAY_2250 + * @arg @ref LL_GPIO_DELAY_2500 + * @arg @ref LL_GPIO_DELAY_2750 + * @arg @ref LL_GPIO_DELAY_3000 + * @arg @ref LL_GPIO_DELAY_3250 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetDelayPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DELAYR[1], + (GPIO_DELAYRH_DLY8 << ((POSITION_VAL(Pin) & 0x07U) * GPIO_DELAYRH_DLY9_Pos))) + >> ((POSITION_VAL(Pin) & 0x07U) * GPIO_DELAYRH_DLY9_Pos)); +} + +/** + * @brief Configure gpio delay of a dedicated pin from 0 to 7 for a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param CfgMask: + * ADVCFG[0] : Delay on ouptput path + * ADVCFG[1] : input and ouptput data are double edge + * ADVCFG[2] : I/O clocks are inverted + * ADVCFG[3] : input and ouptput data are retimed + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPIOControlPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t CfgMask) +{ + MODIFY_REG(GPIOx->ADVCFGR[0], GPIO_ADVCFGRL_0 << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos), + (CfgMask << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos))); +} + +/** + * @brief Return gpio delay of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * ADVCFG[0] : Delay on ouptput path + * ADVCFG[1] : input and ouptput data are double edge + * ADVCFG[2] : I/O clocks are inverted + * ADVCFG[3] : input and ouptput data are retimed + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPIOControlPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->ADVCFGR[0], + (GPIO_ADVCFGRL_0 << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos)); +} + +/** + * @brief Configure gpio delay of a dedicated pin from 8 to 15 for a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param CfgMask: + * ADVCFG[0] : Delay on ouptput path + * ADVCFG[1] : input and ouptput data are double edge + * ADVCFG[2] : I/O clocks are inverted + * ADVCFG[3] : input and ouptput data are retimed + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPIOControlPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t CfgMask) +{ + MODIFY_REG(GPIOx->ADVCFGR[1], GPIO_ADVCFGRH_8 << ((POSITION_VAL(Pin) & 0x07U) * GPIO_ADVCFGRH_9_Pos), + (CfgMask << ((POSITION_VAL(Pin) & 0x07U) * GPIO_ADVCFGRH_9_Pos))); +} + +/** + * @brief Return gpio delay of a dedicated pin from 8 to 15 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * ADVCFG[0] : Delay on ouptput path + * ADVCFG[1] : input and ouptput data are double edge + * ADVCFG[2] : I/O clocks are inverted + * ADVCFG[3] : input and ouptput data are retimed + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPIOControlPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->ADVCFGR[1], + (GPIO_ADVCFGRH_8 << ((POSITION_VAL(Pin) & 0x07U) * GPIO_ADVCFGRH_9_Pos))) + >> ((POSITION_VAL(Pin) & 0x07U) * GPIO_ADVCFGRH_9_Pos)); +} + +/** + * @} + */ + + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + + +#if defined CPU_IN_SECURE_STATE + +/** + * @brief Enable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_EnablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->SECCFGR, PinMask); +} + + +/** + * @brief Disable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_DisablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->SECCFGR, PinMask); +} + +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Return if secure write only access for several pin of dedicated port is enabled or not. + * @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + + + +#if defined CPU_IN_SECURE_STATE + +/** + * @brief Enable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_EnablePinPrivilege + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnablePinPrivilege(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->PRIVCFGR, PinMask); +} + + +/** + * @brief Disable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_DisablePinPrivilege + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisablePinPrivilege(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->PRIVCFGR, PinMask); +} + +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Return if privilege write only access for several pin of dedicated port is enabled or not. + * @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinPrivilege(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->PRIVCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, const LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPION) || defined (GPIOO) || defined (GPIOP) || defined (GPIOQ) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_LL_GPIO_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_pwr.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_pwr.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_pwr.h (revision 16) @@ -0,0 +1,1868 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_PWR_H +#define STM32N6xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +/* Wake-Up Pins PWR register offsets */ +#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2UL) +#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK (0x1FU) +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration + * @{ + */ +#define LL_PWR_SMPS_SUPPLY PWR_CR1_SDEN /*!< Core domains are supplied from the SMPS */ +#define LL_PWR_EXTERNAL_SOURCE_SUPPLY (0U) /*!< The SMPS is Bypassed. The Core domains are supplied from an external source */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration + * @{ + */ +#define LL_PWR_VCOREMON_LEVEL_SCALE1 (0U) /*!< VDDCORE low-voltage threshold 1 selected (VOS 1) */ +#define LL_PWR_VCOREMON_LEVEL_SCALE0 PWR_CR3_VCORELLS /*!< VDDCORE low-voltage threshold 2 selected (VOS 0) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 PWR_VOSCR_VOS /*!< Voltage scaling range 0 (highest frequency) */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (0U) /*!< Voltage scaling range 1 (lowest power) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Power Down Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_POWERDOWN_MODE_DS_STOP (0U) /*!< Enter to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_POWERDOWN_MODE_DS_STANDBY PWR_CPUCR_PDDS /*!< Enter to Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_STOP_VOLTAGE_SCALE3 PWR_CPUCR_SVOS /*!< Voltage scaling range 3 (highest frequency) when system enters STOP mode */ +#define LL_PWR_REGU_STOP_VOLTAGE_SCALE5 (0U) /*!< Voltage scaling range 5 (lowest power) when system enters STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_VDDIO_VOLTAGE_RANGE VDD I/O voltage range selection + * @{ + */ +#define LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 (1U) /*!< 1v8 voltage range */ +#define LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 (0U) /*!< 3v3 voltage range */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */ +#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PC13 */ +#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PD2 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration + * @{ + */ +#define LL_PWR_WAKEUP_PIN_NOPULL (0UL) /*!< Configure Wake-Up pin in no pull */ +#define LL_PWR_WAKEUP_PIN_PULLUP (1UL) /*!< Configure Wake-Up pin in pull Up */ +#define LL_PWR_WAKEUP_PIN_PULLDOWN (2UL) /*!< Configure Wake-Up pin in pull Down */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_ITEMS_PRIVILEGE_ATTRIBUTE PWR Items Privilege Attribute + * @{ + */ +#define LL_PWR_PRIV0_NPRIV (0U) /*!< System supply configuration non privilege mode */ +#define LL_PWR_PRIV0_PRIV PWR_PRIVCFGR_PRIV0 /*!< System supply configuration privilege mode */ +#define LL_PWR_PRIV1_NPRIV (0U) /*!< Programmable voltage detector non privilege mode */ +#define LL_PWR_PRIV1_PRIV PWR_PRIVCFGR_PRIV1 /*!< Programmable voltage detect privilege mode */ +#define LL_PWR_PRIV2_NPRIV (0U) /*!< VDDCORE monitor non privilege mode */ +#define LL_PWR_PRIV2_PRIV PWR_PRIVCFGR_PRIV2 /*!< VDDCORE monitor privilege mode */ +#define LL_PWR_PRIV3_NPRIV (0U) /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control non privilege mode */ +#define LL_PWR_PRIV3_PRIV PWR_PRIVCFGR_PRIV3 /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control privilege mode */ +#define LL_PWR_PRIV4_NPRIV (0U) /*!< Voltage scaling selection nprivilege mode */ +#define LL_PWR_PRIV4_PRIV PWR_PRIVCFGR_PRIV4 /*!< Voltage scaling selection privilege mode */ +#define LL_PWR_PRIV5_NPRIV (0U) /*!< Backup domain non privilege mode */ +#define LL_PWR_PRIV5_PRIV PWR_PRIVCFGR_PRIV5 /*!< Backup domain privilege mode */ +#define LL_PWR_PRIV6_NPRIV (0U) /*!< CPU power control non privilege mode */ +#define LL_PWR_PRIV6_PRIV PWR_PRIVCFGR_PRIV6 /*!< CPU power control privilege mode */ +#define LL_PWR_PRIV7_NPRIV (0U) /*!< Peripheral voltage monitor non privilege mode */ +#define LL_PWR_PRIV7_PRIV PWR_PRIVCFGR_PRIV7 /*!< Peripheral voltage monitor privilege mode */ +#define LL_PWR_WAKEUP_PIN1_NPRIV (0U) /*!< Wake up pin 1 non privilege mode */ +#define LL_PWR_WAKEUP_PIN1_PRIV PWR_PRIVCFGR_WKUPPRIV1 /*!< Wake up pin 1 privilege mode */ +#define LL_PWR_WAKEUP_PIN2_NPRIV (0U) /*!< Wake up pin 2 non privilege mode */ +#define LL_PWR_WAKEUP_PIN2_PRIV PWR_PRIVCFGR_WKUPPRIV2 /*!< Wake up pin 2 privilege mode */ +#define LL_PWR_WAKEUP_PIN3_NPRIV (0U) /*!< Wake up pin 3 non privilege mode */ +#define LL_PWR_WAKEUP_PIN3_PRIV PWR_PRIVCFGR_WKUPPRIV3 /*!< Wake up pin 3 privilege mode */ +#define LL_PWR_WAKEUP_PIN4_NPRIV (0U) /*!< Wake up pin 4 non privilege mode */ +#define LL_PWR_WAKEUP_PIN4_PRIV PWR_PRIVCFGR_WKUPPRIV4 /*!< Wake up pin 4 privilege mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute + * @{ + */ +#define LL_PWR_SEC0_NSEC (0U) /*!< System supply configuration non secure mode */ +#define LL_PWR_SEC0_SEC PWR_SECCFGR_SEC0 /*!< System supply configuration secure mode */ +#define LL_PWR_SEC1_NSEC (0U) /*!< Programmable voltage detector non secure mode */ +#define LL_PWR_SEC1_SEC PWR_SECCFGR_SEC1 /*!< Programmable voltage detect secure mode */ +#define LL_PWR_SEC2_NSEC (0U) /*!< VDDCORE monitor non secure mode */ +#define LL_PWR_SEC2_SEC PWR_SECCFGR_SEC2 /*!< VDDCORE monitor secure mode */ +#define LL_PWR_SEC3_NSEC (0U) /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control non secure mode */ +#define LL_PWR_SEC3_SEC PWR_SECCFGR_SEC3 /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control secure mode */ +#define LL_PWR_SEC4_NSEC (0U) /*!< Voltage scaling selection nsecure mode */ +#define LL_PWR_SEC4_SEC PWR_SECCFGR_SEC4 /*!< Voltage scaling selection secure mode */ +#define LL_PWR_SEC5_NSEC (0U) /*!< Backup domain non secure mode */ +#define LL_PWR_SEC5_SEC PWR_SECCFGR_SEC5 /*!< Backup domain secure mode */ +#define LL_PWR_SEC6_NSEC (0U) /*!< CPU power control non secure mode */ +#define LL_PWR_SEC6_SEC PWR_SECCFGR_SEC6 /*!< CPU power control secure mode */ +#define LL_PWR_SEC7_NSEC (0U) /*!< Peripheral voltage monitor non secure mode */ +#define LL_PWR_SEC7_SEC PWR_SECCFGR_SEC7 /*!< Peripheral voltage monitor secure mode */ +#define LL_PWR_WAKEUP_PIN1_NSEC (0U) /*!< Wake up pin 1 non secure mode */ +#define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WKUPSEC1 /*!< Wake up pin 1 secure mode */ +#define LL_PWR_WAKEUP_PIN2_NSEC (0U) /*!< Wake up pin 2 non secure mode */ +#define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WKUPSEC2 /*!< Wake up pin 2 secure mode */ +#define LL_PWR_WAKEUP_PIN3_NSEC (0U) /*!< Wake up pin 3 non secure mode */ +#define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WKUPSEC3 /*!< Wake up pin 3 secure mode */ +#define LL_PWR_WAKEUP_PIN4_NSEC (0U) /*!< Wake up pin 4 non secure mode */ +#define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WKUPSEC4 /*!< Wake up pin 4 secure mode */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration PWR Configuration + * @{ + */ + +/** + * @brief Configure the PWR supply + * @rmtoll CR1 SDEN LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_SMPS_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR1, PWR_CR1_SDEN, SupplySource); +} + +/** + * @brief Get the PWR supply + * @rmtoll CR1 SDEN LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SMPS_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return READ_BIT(PWR->CR1, PWR_CR1_SDEN); +} + +/** + * @brief Enable the SMPS low-power mode. + * @rmtoll CR1 LPDS08V LL_PWR_EnableSMPSLPMode + * @note This bit is used to keep the SMPS in PWM mode (MR) + * in Stop SVOS 3. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSMPSLPMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_LPDS08V); +} + +/** + * @brief Disable the SMPS low-power mode. + * @rmtoll CR1 LPDS08V LL_PWR_DisableSMPSLPMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSMPSLPMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS08V); +} + +/** + * @brief Check if the SMPS low-power mode is enabled. + * @rmtoll CR1 LPDS08V LL_PWR_IsEnabledSMPSLPMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSLPMode(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_LPDS08V) == (PWR_CR1_LPDS08V)) ? 1UL : 0UL); +} + +/** + * @brief Enable the pull down on output voltage during power-down mode. + * @rmtoll CR2 MODE_PDN LL_PWR_EnablePullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePullDown(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_MODE_PDN); +} + +/** + * @brief Disable the pull down on output voltage during power-down mode. + * @rmtoll CR1 MODE_PDN LL_PWR_DisablePullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePullDown(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_MODE_PDN); +} + +/** + * @brief Check if the pull down on output voltage during power-down mode is enabled. + * @rmtoll CR1 MODE_PDN LL_PWR_IsEnabledPullDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPullDown(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_MODE_PDN) == (PWR_CR1_MODE_PDN)) ? 1UL : 0UL); +} + +/** + * @brief Set the pwr_on pulse low time + * @rmtoll CR1 POPL LL_PWR_SetPwrONPulseLowTime + * @param PulseTime Value between Min_Data = 0 and Max_Data = 31 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPwrONPulseLowTime(uint32_t PulseTime) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_POPL, (PulseTime << PWR_CR1_POPL_Pos)); +} + +/** + * @brief Get the pwr_on pulse low time + * @rmtoll CR1 POPL LL_PWR_GetPwrONPulseLowTime + * @retval Value between Min_Data = 0 and Max_Data = 31 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPwrONPulseLowTime(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_POPL) >> PWR_CR1_POPL_Pos); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR2 PVDEN LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVDEN); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR2 PVDEN LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDEN); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR2 PVDEN LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_PVDEN) == (PWR_CR2_PVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable VCORE monitoring + * @rmtoll CR3 VCOREMONEN LL_PWR_EnableVCOREMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVCOREMonitoring(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_VCOREMONEN); +} + +/** + * @brief Disable VCORE monitoring + * @rmtoll CR3 VCOREMONEN LL_PWR_DisableVCOREMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVCOREMonitoring(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_VCOREMONEN); +} + +/** + * @brief Check if the VCORE monitoring is enabled + * @rmtoll CR3 VCOREMONEN LL_PWR_IsEnabledVCOREMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVCOREMonitoring(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREMONEN) == (PWR_CR3_VCOREMONEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the VDDCORE voltage detector low-level selection + * @rmtoll CR3 VCORELLS LL_PWR_SetVCORELowLevelDetection + * @param Lowlevel This parameter can be one of the following values: + * @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE1 + * @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE0 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetVCORELowLevelDetection(uint32_t Lowlevel) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_VCORELLS, Lowlevel); +} + +/** + * @brief Get the VDDCORE voltage detector low-level selection + * @rmtoll CR3 VCORELLS LL_PWR_GetVCORELowLevelDetection + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE1 + * @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE0 + */ +__STATIC_INLINE uint32_t LL_PWR_GetVCORELowLevelDetection(void) +{ + return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VCORELLS)); +} + +/** + * @brief Enable I-TCM and D-TCM RAMs retention in Standby mode. + * @rmtoll CR4 TCMRBSEN LL_PWR_EnableTCMSBRetention + * @note When this bit is set, I-TCM and D-TCM RAMs are supplied + * from backup regulator in Standby mode. + * When this bit is reset, I-TCM and D-TCM RAMs can still + * be used in Run and Stop modes, but their content is lost + * in Standby mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableTCMSBRetention(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_TCMRBSEN); +} + +/** + * @brief Disable I-TCM and D-TCM RAMs retention in Standby mode. + * @rmtoll CR4 TCMRBSEN LL_PWR_DisableTCMSBRetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableTCMSBRetention(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_TCMRBSEN); +} + +/** + * @brief Check if the I-TCM and D-TCM RAMs retention in Standby mode is enabled + * @rmtoll CR4 TCMRBSEN LL_PWR_IsEnabledTCMSBRetention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledTCMSBRetention(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_TCMRBSEN) == (PWR_CR4_TCMRBSEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable I-TCM FLEXMEM retention in Standby mode. + * @rmtoll CR4 TCMFLXRBSEN LL_PWR_EnableTCMFLXSBRetention + * @note When this bit is set, the I-TCM FLEXMEM is supplied + * from backup regulator in Standby mode. + * When this bit is reset, the I-TCM FLEXMEM can still + * be used in Run and Stop modes, but its content is lost + * in Standby mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableTCMFLXSBRetention(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN); +} + +/** + * @brief Disable I-TCM FLEXMEM RAMs retention in Standby mode. + * @rmtoll CR4 TCMFLXRBSEN LL_PWR_DisableTCMFLXSBRetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableTCMFLXSBRetention(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN); +} + +/** + * @brief Check if the I-TCM FLEXMEM retention in Standby mode is enabled + * @rmtoll CR4 TCMFLXRBSEN LL_PWR_IsEnabledTCMFLXSBRetention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledTCMFLXSBRetention(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN) == (PWR_CR4_TCMFLXRBSEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll VOSCR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal Regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @rmtoll VOSCR ACTVOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOS) == (PWR_VOSCR_ACTVOS)) ? 1UL : 0UL); +} + +/** + * @brief Enable VBAT and Temperature monitoring + * @rmtoll BDCR1 MONEN LL_PWR_EnableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMonitoring(void) +{ + SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +/** + * @brief Disable VBAT and Temperature monitoring + * @rmtoll BDCR1 MONEN LL_PWR_DisableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +/** + * @brief Check if the VBAT and Temperature monitoring is enabled + * @rmtoll BDCR1 MONEN LL_PWR_IsEnabledMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) +{ + return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable BKPSRAM retention in Standby mode. + * @rmtoll BDCR2 BKPRBSEN LL_PWR_EnableBkpSRAMSBRetention + * @note When this bit is set, the backup ram is supplied from backup regulator in Standby and + * VBAT modes. + * When this bit is reset, the backup ram can still be used in Run and Stop modes, + * but its content is lost in Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkpSRAMSBRetention(void) +{ + SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); +} + +/** + * @brief Disable BKPSRAM retention in Standby mode. + * @rmtoll BDCR2 BKPRBSEN LL_PWR_DisableBkpSRAMSBRetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkpSRAMSBRetention(void) +{ + CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); +} + +/** + * @brief Check if the BKPSRAM retention in Standby mode is enabled + * @rmtoll BDCR2 BKPRBSEN LL_PWR_IsEnabledBkpSRAMSBRetention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkpSRAMSBRetention(void) +{ + return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN) == (PWR_BDCR2_BKPRBSEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll DBPCR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll DBPCR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll DBPCR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Set the internal Regulator output voltage in STOP mode + * @rmtoll CPUCR SVOS LL_PWR_SetStopModeRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3 + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling); +} + +/** + * @brief Get the internal Regulator output voltage in STOP mode + * @rmtoll CPUCR SVOS LL_PWR_GetStopModeRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3 + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5 + */ +__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) +{ + return READ_BIT(PWR->CPUCR, PWR_CPUCR_SVOS); +} + +/** + * @brief Set the Power Down mode when device enters deepsleep mode + * @rmtoll CPUCR PDDS LL_PWR_SetPowerDownModeDS + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerDownModeDS(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS, PDMode); +} + +/** + * @brief Get the Power Down mode when device enters deepsleep mode + * @rmtoll CPUCR PDDS LL_PWR_GetPowerDownModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerDownModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS)); +} + +/** + * @brief Enable Vdd IO2 voltage supply + * @rmtoll SVMCR3 VDDIO2SV LL_PWR_EnableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO2(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV); +} + +/** + * @brief Disable Vdd IO2 voltage supply + * @rmtoll SVMCR3 VDDIO2SV LL_PWR_DisableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV); +} + +/** + * @brief Check if the Vdd IO2 voltage supply is enabled + * @rmtoll SVMCR3 VDDIO2SV LL_PWR_IsEnabledVddIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV) == (PWR_SVMCR3_VDDIO2SV)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO3 voltage supply + * @rmtoll SVMCR3 VDDIO3SV LL_PWR_EnableVddIO3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO3(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV); +} + +/** + * @brief Disable Vdd IO3 voltage supply + * @rmtoll SVMCR3 VDDIO3SV LL_PWR_DisableVddIO3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO3(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV); +} + +/** + * @brief Check if the Vdd IO3 voltage supply is enabled + * @rmtoll SVMCR3 VDDIO3SV LL_PWR_IsEnabledVddIO3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO3(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV) == (PWR_SVMCR3_VDDIO3SV)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO4 voltage supply + * @rmtoll SVMCR1 VDDIO4SV LL_PWR_EnableVddIO4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO4(void) +{ + SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV); +} + +/** + * @brief Disable Vdd IO4 voltage supply + * @rmtoll SVMCR1 VDDIO4SV LL_PWR_DisableVddIO4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO4(void) +{ + CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV); +} + +/** + * @brief Check if the Vdd IO4 voltage supply is enabled + * @rmtoll SVMCR1 VDDIO4SV LL_PWR_IsEnabledVddIO4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4(void) +{ + return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV) == (PWR_SVMCR1_VDDIO4SV)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO5 voltage supply + * @rmtoll SVMCR2 VDDIO5SV LL_PWR_EnableVddIO5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO5(void) +{ + SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); +} + +/** + * @brief Disable Vdd IO5 voltage supply + * @rmtoll SVMCR2 VDDIO5SV LL_PWR_DisableVddIO5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO5(void) +{ + CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); +} + +/** + * @brief Check if the Vdd IO5 voltage supply is enabled + * @rmtoll SVMCR2 VDDIO5SV LL_PWR_IsEnabledVddIO5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5(void) +{ + return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV) == (PWR_SVMCR2_VDDIO5SV)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd USB voltage supply + * @rmtoll SVMCR3 USB33SV LL_PWR_EnableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSB(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV); +} + +/** + * @brief Disable Vdd USB voltage supply + * @rmtoll SVMCR3 USB33SV LL_PWR_DisableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV); +} + +/** + * @brief Check if the Vdd USB voltage supply is enabled + * @rmtoll SVMCR3 USB33SV LL_PWR_IsEnabledVddUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV) == (PWR_SVMCR3_USB33SV)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd ADC voltage supply + * @rmtoll SVMCR3 ASV LL_PWR_EnableVddADC + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddADC(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV); +} + +/** + * @brief Disable Vdd ADC voltage supply + * @rmtoll SVMCR3 ASV LL_PWR_DisableVddADC + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddADC(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV); +} + +/** + * @brief Check if the Vdd ADC voltage supply is enabled + * @rmtoll SVMCR3 ASV LL_PWR_IsEnabledVddADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddADC(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV) == (PWR_SVMCR3_ASV)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO2 voltage monitoring + * @rmtoll SVMCR3 VDDIO2VMEN LL_PWR_EnableVddIO2Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO2Monitoring(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN); +} + +/** + * @brief Disable Vdd IO2 voltage monitoring + * @rmtoll SVMCR3 VDDIO2VMEN LL_PWR_DisableVddIO2Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO2Monitoring(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN); +} + +/** + * @brief Check if the Vdd IO2 voltage monitoring is enabled + * @rmtoll SVMCR3 VDDIO2VMEN LL_PWR_IsEnabledVddIO2Monitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2Monitoring(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN) == (PWR_SVMCR3_VDDIO2VMEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO3 voltage monitoring + * @rmtoll SVMCR3 VDDIO3VMEN LL_PWR_EnableVddIO3Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO3Monitoring(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN); +} + +/** + * @brief Disable Vdd IO3 voltage monitoring + * @rmtoll SVMCR3 VDDIO3VMEN LL_PWR_DisableVddIO3Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO3Monitoring(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN); +} + +/** + * @brief Check if the Vdd IO3 voltage monitoring is enabled + * @rmtoll SVMCR3 VDDIO3VMEN LL_PWR_IsEnabledVddIO3Monitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO3Monitoring(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN) == (PWR_SVMCR3_VDDIO3VMEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO4 voltage monitoring + * @rmtoll SVMCR1 VDDIO4VMEN LL_PWR_EnableVddIO4Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO4Monitoring(void) +{ + SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN); +} + +/** + * @brief Disable Vdd IO4 voltage monitoring + * @rmtoll SVMCR1 VDDIO4VMEN LL_PWR_DisableVddIO4Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO4Monitoring(void) +{ + CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN); +} + +/** + * @brief Check if the Vdd IO4 voltage monitoring is enabled + * @rmtoll SVMCR1 VDDIO4VMEN LL_PWR_IsEnabledVddIO4Monitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4Monitoring(void) +{ + return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN) == (PWR_SVMCR1_VDDIO4VMEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO5 voltage monitoring + * @rmtoll SVMCR2 VDDIO5VMEN LL_PWR_EnableVddIO5Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO5Monitoring(void) +{ + SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); +} + +/** + * @brief Disable Vdd IO5 voltage monitoring + * @rmtoll SVMCR2 VDDIO5VMEN LL_PWR_DisableVddIO5Monitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO5Monitoring(void) +{ + CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); +} + +/** + * @brief Check if the Vdd IO5 voltage monitoring is enabled + * @rmtoll SVMCR2 VDDIO5VMEN LL_PWR_IsEnabledVddIO5Monitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5Monitoring(void) +{ + return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN) == (PWR_SVMCR2_VDDIO5VMEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd ADC voltage monitoring + * @rmtoll SVMCR3 AVMEN LL_PWR_EnableVddADCMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddADCMonitoring(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN); +} + +/** + * @brief Disable Vdd ADC voltage monitoring + * @rmtoll SVMCR3 AVMEN LL_PWR_DisableVddADCMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddADCMonitoring(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN); +} + +/** + * @brief Check if the Vdd ADC voltage monitoring is enabled + * @rmtoll SVMCR3 AVMEN LL_PWR_IsEnabledVddADCMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddADCMonitoring(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN) == (PWR_SVMCR3_AVMEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd USB voltage monitoring + * @rmtoll SVMCR3 USB33VMEN LL_PWR_EnableVddUSBMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSBMonitoring(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN); +} + +/** + * @brief Disable Vdd USB voltage monitoring + * @rmtoll SVMCR3 USB33VMEN LL_PWR_DisableVddUSBMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSBMonitoring(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN); +} + +/** + * @brief Check if the Vdd USB voltage monitoring is enabled + * @rmtoll SVMCR3 USB33VMEN LL_PWR_IsEnabledVddUSBMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSBMonitoring(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN) == (PWR_SVMCR3_USB33VMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the VDD I/O voltage range + * @rmtoll SVMCR3 VDDIOVRSEL LL_PWR_SetVddIOVoltageRange + * @param VoltageRange This parameter can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + * @note HSLV_VDD option bit must be set to allow 1v8 voltage range + * operation. + * Setting this configuration while VDD is in 3v3 range damages the device. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetVddIOVoltageRange(uint32_t VoltageRange) +{ + MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL, (VoltageRange << PWR_SVMCR3_VDDIOVRSEL_Pos)); +} + +/** + * @brief Get the VDD IO voltage range + * @rmtoll SVMCR3 VDDIOVRSEL LL_PWR_GetVddIOVoltageRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + */ +__STATIC_INLINE uint32_t LL_PWR_GetVddIOVoltageRange(void) +{ + return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL) >> PWR_SVMCR3_VDDIOVRSEL_Pos); +} + +/** + * @brief Set the VDD IO2 voltage range + * @rmtoll SVMCR3 VDDIO2VRSEL LL_PWR_SetVddIO2VoltageRange + * @param VoltageRange This parameter can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + * @note HSLV_VDD option bit must be set to allow 1v8 voltage range + * operation. + * Setting this configuration while VDD is in 3v3 range damages the device. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetVddIO2VoltageRange(uint32_t VoltageRange) +{ + MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO2VRSEL_Pos)); +} + +/** + * @brief Get the VDD IO2 voltage range + * @rmtoll SVMCR3 VDDIO2VRSEL LL_PWR_GetVddIO2VoltageRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + */ +__STATIC_INLINE uint32_t LL_PWR_GetVddIO2VoltageRange(void) +{ + return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL) >> PWR_SVMCR3_VDDIO2VRSEL_Pos); +} + +/** + * @brief Set the VDD IO3 voltage range + * @rmtoll SVMCR3 VDDIO3VRSEL LL_PWR_SetVddIO3VoltageRange + * @param VoltageRange This parameter can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + * @note HSLV_VDD option bit must be set to allow 1v8 voltage range + * operation. + * Setting this configuration while VDD is in 3v3 range damages the device. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetVddIO3VoltageRange(uint32_t VoltageRange) +{ + MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO3VRSEL_Pos)); +} + +/** + * @brief Get the VDD IO3 voltage range + * @rmtoll SVMCR3 VDDIO3VRSEL LL_PWR_GetVddIO3VoltageRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + */ +__STATIC_INLINE uint32_t LL_PWR_GetVddIO3VoltageRange(void) +{ + return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL) >> PWR_SVMCR3_VDDIO3VRSEL_Pos); +} + +/** + * @brief Set the VDD IO4 voltage range + * @rmtoll SVMCR1 VDDIO4VRSEL LL_PWR_SetVddIO4VoltageRange + * @param VoltageRange This parameter can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + * @note HSLV_VDD option bit must be set to allow 1v8 voltage range + * operation. + * Setting this configuration while VDD is in 3v3 range damages the device. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetVddIO4VoltageRange(uint32_t VoltageRange) +{ + MODIFY_REG(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL, (VoltageRange << PWR_SVMCR1_VDDIO4VRSEL_Pos)); +} + +/** + * @brief Get the VDD IO4 voltage range + * @rmtoll SVMCR1 VDDIO4VRSEL LL_PWR_GetVddIO4VoltageRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + */ +__STATIC_INLINE uint32_t LL_PWR_GetVddIO4VoltageRange(void) +{ + return (uint32_t)(READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL) >> PWR_SVMCR1_VDDIO4VRSEL_Pos); +} + +/** + * @brief Set the VDD IO5 voltage range + * @rmtoll SVMCR2 VDDIO5VRSEL LL_PWR_SetVddIO5VoltageRange + * @param VoltageRange This parameter can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + * @note HSLV_VDD option bit must be set to allow 1v8 voltage range + * operation. + * Setting this configuration while VDD is in 3v3 range damages the device. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetVddIO5VoltageRange(uint32_t VoltageRange) +{ + MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, (VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos)); +} + +/** + * @brief Get the VDD IO5 voltage range + * @rmtoll SVMCR2 VDDIO5VRSEL LL_PWR_GetVddIO5VoltageRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3 + * @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8 + */ +__STATIC_INLINE uint32_t LL_PWR_GetVddIO5VoltageRange(void) +{ + return (uint32_t)(READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos); +} + +/** + * @brief Enable Vdd IO4 voltage range retained in Standby mode + * @rmtoll SVMCR1 VDDIO4VRSTBY LL_PWR_EnableVddIO4VoltageRangeSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO4VoltageRangeSB(void) +{ + SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY); +} + +/** + * @brief Disable Vdd IO4 voltage range retained in Standby mode + * @rmtoll SVMCR1 VDDIO4VRSTBY LL_PWR_DisableVddIO4VoltageRangeSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO4VoltageRangeSB(void) +{ + CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY); +} + +/** + * @brief Check if the Vdd IO4 voltage range retained in Standby mode is enabled + * @rmtoll SVMCR1 VDDIO4VRSTBY LL_PWR_IsEnabledVddIO4VoltageRangeSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4VoltageRangeSB(void) +{ + return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY) == (PWR_SVMCR1_VDDIO4VRSTBY)) ? 1UL : 0UL); +} + +/** + * @brief Enable Vdd IO5 voltage range retained in Standby mode + * @rmtoll SVMCR2 VDDIO5VRSTBY LL_PWR_EnableVddIO5VoltageRangeSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO5VoltageRangeSB(void) +{ + SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); +} + +/** + * @brief Disable Vdd IO5 voltage range retained in Standby mode + * @rmtoll SVMCR2 VDDIO5VRSTBY LL_PWR_DisableVddIO5VoltageRangeSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO5VoltageRangeSB(void) +{ + CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); +} + +/** + * @brief Check if the Vdd IO5 voltage range retained in Standby mode is enabled + * @rmtoll SVMCR2 VDDIO5VRSTBY LL_PWR_IsEnabledVddIO5VoltageRangeSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5VoltageRangeSB(void) +{ + return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY) == (PWR_SVMCR2_VDDIO5VRSTBY)) ? 1UL : 0UL); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Check if the Wake-Up pin polarity is low for event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin Pull None + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Up + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Down + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Get the Wake-Up pin pull + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\ + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL + * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP + * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) +{ + uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL( + WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management + * @{ + */ + +/** + * @brief Indicate whether the voltage level is ready for current actual used VOS + * @rmtoll VOSCR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOSRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOSRDY(void) +{ + return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOSRDY) == (PWR_VOSCR_ACTVOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CR2 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_PVDO) == (PWR_CR2_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VCORE level is above or below low threshold + * @rmtoll CR3 VCOREL LL_PWR_IsActiveFlag_VCOREL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VCOREL(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREL) == (PWR_CR3_VCOREL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VCORE level is above or below high threshold + * @rmtoll CR3 VCOREH LL_PWR_IsActiveFlag_VCOREH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VCOREH(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREH) == (PWR_CR3_VCOREH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range + * or if its output voltage is still changing to the required voltage level + * @rmtoll VOSCR VOSRDY LL_PWR_IsActiveFlag_VOSRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSRDY(void) +{ + return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_VOSRDY) == (PWR_VOSCR_VOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below low threshold + * @rmtoll BDCR1 VBATL LL_PWR_IsActiveFlag_VBATL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) +{ + return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATL) == (PWR_BDCR1_VBATL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below high threshold + * @rmtoll BDCR1 VBATH LL_PWR_IsActiveFlag_VBATH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) +{ + return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATH) == (PWR_BDCR1_VBATH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below low threshold + * @rmtoll BDCR1 TEMPL LL_PWR_IsActiveFlag_TEMPL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) +{ + return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPL) == (PWR_BDCR1_TEMPL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below high threshold + * @rmtoll BDCR1 TEMPH LL_PWR_IsActiveFlag_TEMPH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) +{ + return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPH) == (PWR_BDCR1_TEMPH)) ? 1UL : 0UL); +} + +/** + * @brief Get System Stop Flag + * @rmtoll CPUCR STOPF LL_PWR_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Get System Standby Flag + * @rmtoll CPUCR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Get VDDIO2 ready Flag + * @rmtoll SVMCR3 VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2RDY(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2RDY) == (PWR_SVMCR3_VDDIO2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get VDDIO3 ready Flag + * @rmtoll SVMCR3 VDDIO3RDY LL_PWR_IsActiveFlag_VDDIO3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO3RDY(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3RDY) == (PWR_SVMCR3_VDDIO3RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get VDDIO4 ready Flag + * @rmtoll SVMCR1 VDDIO4RDY LL_PWR_IsActiveFlag_VDDIO4RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO4RDY(void) +{ + return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4RDY) == (PWR_SVMCR1_VDDIO4RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get VDDIO5 ready Flag + * @rmtoll SVMCR2 VDDIO5RDY LL_PWR_IsActiveFlag_VDDIO5RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO5RDY(void) +{ + return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5RDY) == (PWR_SVMCR2_VDDIO5RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get VDD ADC ready Flag + * @rmtoll SVMCR3 ARDY LL_PWR_IsActiveFlag_ARDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ARDY(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ARDY) == (PWR_SVMCR3_ARDY)) ? 1UL : 0UL); +} + +/** + * @brief Get VDD USB33 ready Flag + * @rmtoll SVMCR3 USB33RDY LL_PWR_IsActiveFlag_USB33RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB33RDY(void) +{ + return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33RDY) == (PWR_SVMCR3_USB33RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll WKUPSR WKUPF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF1) == (PWR_WKUPSR_WKUPF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll WKUPSR WKUPF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF2) == (PWR_WKUPSR_WKUPF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 3 + * @rmtoll WKUPSR WKUPF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF3) == (PWR_WKUPSR_WKUPF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll WKUPSR WKUPF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF4) == (PWR_WKUPSR_WKUPF4)) ? 1UL : 0UL); +} + +/** + * @brief Clear STOP and STANDBY and flags + * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_STOP_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_STOP_SB(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); +} + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); +} + +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); +} + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); +} + +/** + * @brief Clear all wake up flags. + * @rmtoll WUSCR WKUPC LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management + * @{ + */ + +/** + * @brief Configure privilege attribute mode. + * @note This API can be executed only by CPU in privilege mode. + * @rmtoll PRIVCFGR PRIV0 LL_PWR_ConfigPrivilege\n + * PRIVCFGR PRIV1 LL_PWR_ConfigPrivilege\n + * PRIVCFGR PRIV2 LL_PWR_ConfigPrivilege\n + * PRIVCFGR PRIV3 LL_PWR_ConfigPrivilege\n + * PRIVCFGR PRIV4 LL_PWR_ConfigPrivilege\n + * PRIVCFGR PRIV5 LL_PWR_ConfigPrivilege\n + * PRIVCFGR PRIV6 LL_PWR_ConfigPrivilege\n + * PRIVCFGR PRIV7 LL_PWR_ConfigPrivilege\n + * PRIVCFGR WKUPPRIV1 LL_PWR_ConfigPrivilege\n + * PRIVCFGR WKUPPRIV2 LL_PWR_ConfigPrivilege\n + * PRIVCFGR WKUPPRIV3 LL_PWR_ConfigPrivilege\n + * PRIVCFGR WKUPPRIV4 LL_PWR_ConfigPrivilege + * @param PrivilegeConfig This parameter can be the full combination + * of the following values: + * @arg @ref LL_PWR_PRIV0_PRIV or LL_PWR_PRIV0_NPRIV + * @arg @ref LL_PWR_PRIV1_PRIV or LL_PWR_PRIV1_NPRIV + * @arg @ref LL_PWR_PRIV2_PRIV or LL_PWR_PRIV2_NPRIV + * @arg @ref LL_PWR_PRIV3_PRIV or LL_PWR_PRIV3_NPRIV + * @arg @ref LL_PWR_PRIV4_PRIV or LL_PWR_PRIV4_NPRIV + * @arg @ref LL_PWR_PRIV5_PRIV or LL_PWR_PRIV5_NPRIV + * @arg @ref LL_PWR_PRIV6_PRIV or LL_PWR_PRIV6_NPRIV + * @arg @ref LL_PWR_PRIV7_PRIV or LL_PWR_PRIV7_NPRIV + * @arg @ref LL_PWR_WAKEUP_PIN1_NPRIV or LL_PWR_WAKEUP_PIN1_PRIV + * @arg @ref LL_PWR_WAKEUP_PIN2_NPRIV or LL_PWR_WAKEUP_PIN2_PRIV + * @arg @ref LL_PWR_WAKEUP_PIN3_NPRIV or LL_PWR_WAKEUP_PIN3_PRIV + * @arg @ref LL_PWR_WAKEUP_PIN4_NPRIV or LL_PWR_WAKEUP_PIN4_PRIV + * @retval None. + */ +__STATIC_INLINE void LL_PWR_ConfigPrivilege(uint32_t PrivilegeConfig) +{ + WRITE_REG(PWR->PRIVCFGR, PrivilegeConfig); +} + +/** + * @brief Get privilege attribute configuration. + * @rmtoll PRIVCFGR PRIV0 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR PRIV1 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR PRIV2 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR PRIV3 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR PRIV4 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR PRIV5 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR PRIV6 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR PRIV7 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR WKUPPRIV1 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR WKUPPRIV2 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR WKUPPRIV3 LL_PWR_GetConfigPrivilege\n + * PRIVCFGR WKUPPRIV4 LL_PWR_GetConfigPrivilege + * @retval Returned value is the combination of the following values: + * @arg @ref LL_PWR_PRIV0_PRIV or LL_PWR_PRIV0_NPRIV + * @arg @ref LL_PWR_PRIV1_PRIV or LL_PWR_PRIV1_NPRIV + * @arg @ref LL_PWR_PRIV2_PRIV or LL_PWR_PRIV2_NPRIV + * @arg @ref LL_PWR_PRIV3_PRIV or LL_PWR_PRIV3_NPRIV + * @arg @ref LL_PWR_PRIV4_PRIV or LL_PWR_PRIV4_NPRIV + * @arg @ref LL_PWR_PRIV5_PRIV or LL_PWR_PRIV5_NPRIV + * @arg @ref LL_PWR_PRIV6_PRIV or LL_PWR_PRIV6_NPRIV + * @arg @ref LL_PWR_PRIV7_PRIV or LL_PWR_PRIV7_NPRIV + * @arg @ref LL_PWR_WAKEUP_PIN1_NPRIV or LL_PWR_WAKEUP_PIN1_PRIV + * @arg @ref LL_PWR_WAKEUP_PIN2_NPRIV or LL_PWR_WAKEUP_PIN2_PRIV + * @arg @ref LL_PWR_WAKEUP_PIN3_NPRIV or LL_PWR_WAKEUP_PIN3_PRIV + * @arg @ref LL_PWR_WAKEUP_PIN4_NPRIV or LL_PWR_WAKEUP_PIN4_PRIV + */ +__STATIC_INLINE uint32_t LL_PWR_GetConfigPrivilege(void) +{ + return (READ_REG(PWR->PRIVCFGR)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure secure attribute mode. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR SEC0 LL_PWR_ConfigSecure\n + * SECCFGR SEC1 LL_PWR_ConfigSecure\n + * SECCFGR SEC2 LL_PWR_ConfigSecure\n + * SECCFGR SEC3 LL_PWR_ConfigSecure\n + * SECCFGR SEC4 LL_PWR_ConfigSecure\n + * SECCFGR SEC5 LL_PWR_ConfigSecure\n + * SECCFGR SEC6 LL_PWR_ConfigSecure\n + * SECCFGR SEC7 LL_PWR_ConfigSecure\n + * SECCFGR WKUPSEC1 LL_PWR_ConfigSecure\n + * SECCFGR WKUPSEC2 LL_PWR_ConfigSecure\n + * SECCFGR WKUPSEC3 LL_PWR_ConfigSecure\n + * SECCFGR WKUPSEC4 LL_PWR_ConfigSecure + * @param SecureConfig This parameter can be the full combination + * of the following values: + * @arg @ref LL_PWR_SEC0_SEC or LL_PWR_SEC0_NSEC + * @arg @ref LL_PWR_SEC1_SEC or LL_PWR_SEC1_NSEC + * @arg @ref LL_PWR_SEC2_SEC or LL_PWR_SEC2_NSEC + * @arg @ref LL_PWR_SEC3_SEC or LL_PWR_SEC3_NSEC + * @arg @ref LL_PWR_SEC4_SEC or LL_PWR_SEC4_NSEC + * @arg @ref LL_PWR_SEC5_SEC or LL_PWR_SEC5_NSEC + * @arg @ref LL_PWR_SEC6_SEC or LL_PWR_SEC6_NSEC + * @arg @ref LL_PWR_SEC7_SEC or LL_PWR_SEC7_NSEC + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + * @retval None. + */ +__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig) +{ + WRITE_REG(PWR->SECCFGR, SecureConfig); +} + +/** + * @brief Get secure attribute configuration. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR SEC0 LL_PWR_GetConfigSecure\n + * SECCFGR SEC1 LL_PWR_GetConfigSecure\n + * SECCFGR SEC2 LL_PWR_GetConfigSecure\n + * SECCFGR SEC3 LL_PWR_GetConfigSecure\n + * SECCFGR SEC4 LL_PWR_GetConfigSecure\n + * SECCFGR SEC5 LL_PWR_GetConfigSecure\n + * SECCFGR SEC6 LL_PWR_GetConfigSecure\n + * SECCFGR SEC7 LL_PWR_GetConfigSecure\n + * SECCFGR WKUPSEC1 LL_PWR_GetConfigSecure\n + * SECCFGR WKUPSEC2 LL_PWR_GetConfigSecure\n + * SECCFGR WKUPSEC3 LL_PWR_GetConfigSecure\n + * SECCFGR WKUPSEC4 LL_PWR_GetConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_PWR_SEC0_SEC or LL_PWR_SEC0_NSEC + * @arg @ref LL_PWR_SEC1_SEC or LL_PWR_SEC1_NSEC + * @arg @ref LL_PWR_SEC2_SEC or LL_PWR_SEC2_NSEC + * @arg @ref LL_PWR_SEC3_SEC or LL_PWR_SEC3_NSEC + * @arg @ref LL_PWR_SEC4_SEC or LL_PWR_SEC4_NSEC + * @arg @ref LL_PWR_SEC5_SEC or LL_PWR_SEC5_NSEC + * @arg @ref LL_PWR_SEC6_SEC or LL_PWR_SEC6_NSEC + * @arg @ref LL_PWR_SEC7_SEC or LL_PWR_SEC7_NSEC + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + */ +__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void) +{ + return (READ_REG(PWR->SECCFGR)); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32N6xx_LL_PWR_H */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_rcc.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_rcc.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_rcc.h (revision 16) @@ -0,0 +1,8785 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_RCC_H +#define STM32N6xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" +#include + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Constants for LL_CLKSOURCE_xxx() macros + 31 24 16 8 0 + -------------------------------------------------------- + | Mask | ClkSource | Bit | Register | + | | Config | Position | Offset | + --------------------------------------------------------*/ + +/* Clock source register offset Vs CCIPR1 register */ +#define CCIPR1_OFFSET 0x0UL +#define CCIPR2_OFFSET 0x4UL +#define CCIPR3_OFFSET 0x8UL +#define CCIPR4_OFFSET 0xCUL +#define CCIPR5_OFFSET 0x10UL +#define CCIPR6_OFFSET 0x14UL +#define CCIPR7_OFFSET 0x18UL +#define CCIPR8_OFFSET 0x1CUL +#define CCIPR9_OFFSET 0x20UL +#define CCIPR12_OFFSET 0x2CUL +#define CCIPR13_OFFSET 0x30UL +#define CCIPR14_OFFSET 0x34UL + +#define LL_RCC_REG_SHIFT 0U +#define LL_RCC_POS_SHIFT 8U +#define LL_RCC_CONFIG_SHIFT 16U +#define LL_RCC_MASK_SHIFT 24U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* UNUSED */ + +#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) + +#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) &\ + 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\ + 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) + +#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ + (( __POS__ ) << LL_RCC_POS_SHIFT) | \ + (( __REG__ ) << LL_RCC_REG_SHIFT) | \ + (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t CPUCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; + uint32_t PCLK4_Frequency; + uint32_t PCLK5_Frequency; +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000U /*!< Value of the MSI oscillator in Hz */ +#endif /* MSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider + * @{ + */ +#define LL_RCC_HSI_DIV_1 0U +#define LL_RCC_HSI_DIV_2 RCC_HSICFGR_HSIDIV_0 +#define LL_RCC_HSI_DIV_4 RCC_HSICFGR_HSIDIV_1 +#define LL_RCC_HSI_DIV_8 RCC_HSICFGR_HSIDIV +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIFREQ MSI oscillator frequency select + * @{ + */ +#define LL_RCC_MSI_FREQ_4MHZ 0U +#define LL_RCC_MSI_FREQ_16MHZ RCC_MSICFGR_MSIFREQSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0U +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_LSECFGR_LSEDRV_1 +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_LSECFGR_LSEDRV_0 +#define LL_RCC_LSEDRIVE_HIGH RCC_LSECFGR_LSEDRV +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSECSSBYP_DIV HSI divider to apply for replacement of HSE on CSS bypass + * @{ + */ +#define LL_RCC_HSECSSBYP_DIV_1 0U +#define LL_RCC_HSECSSBYP_DIV_2 RCC_HSECFGR_HSECSSBPRE_0 +#define LL_RCC_HSECSSBYP_DIV_3 RCC_HSECFGR_HSECSSBPRE_1 +#define LL_RCC_HSECSSBYP_DIV_4 (RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0) +#define LL_RCC_HSECSSBYP_DIV_5 RCC_HSECFGR_HSECSSBPRE_2 +#define LL_RCC_HSECSSBYP_DIV_6 (RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_0) +#define LL_RCC_HSECSSBYP_DIV_7 (RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_1) +#define LL_RCC_HSECSSBYP_DIV_8 (RCC_HSECFGR_HSECSSBPRE_2 |\ + RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0) +#define LL_RCC_HSECSSBYP_DIV_9 RCC_HSECFGR_HSECSSBPRE_3 +#define LL_RCC_HSECSSBYP_DIV_10 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_0) +#define LL_RCC_HSECSSBYP_DIV_11 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_1) +#define LL_RCC_HSECSSBYP_DIV_12 (RCC_HSECFGR_HSECSSBPRE_3 |\ + RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0) +#define LL_RCC_HSECSSBYP_DIV_13 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_2) +#define LL_RCC_HSECSSBYP_DIV_14 (RCC_HSECFGR_HSECSSBPRE_3 |\ + RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_0) +#define LL_RCC_HSECSSBYP_DIV_15 (RCC_HSECFGR_HSECSSBPRE_3 |\ + RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_1) +#define LL_RCC_HSECSSBYP_DIV_16 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_2 |\ + RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0) +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_CPU_CLKSOURCE CPU clock switch + * @{ + */ +#define LL_RCC_CPU_CLKSOURCE_HSI 0U /*!< Select HSI as CPU clock */ +#define LL_RCC_CPU_CLKSOURCE_MSI RCC_CFGR1_CPUSW_0 /*!< Select MSI as CPU clock */ +#define LL_RCC_CPU_CLKSOURCE_HSE RCC_CFGR1_CPUSW_1 /*!< Select HSE as CPU clock */ +#define LL_RCC_CPU_CLKSOURCE_IC1 (RCC_CFGR1_CPUSW_1 | RCC_CFGR1_CPUSW_0) /*!< Select IC1 as CPU clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CPU_CLKSOURCE_STATUS CPU clock switch status + * @{ + */ +#define LL_RCC_CPU_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as CPU clock */ +#define LL_RCC_CPU_CLKSOURCE_STATUS_MSI RCC_CFGR1_CPUSWS_0 /*!< MSI used as CPU clock */ +#define LL_RCC_CPU_CLKSOURCE_STATUS_HSE RCC_CFGR1_CPUSWS_1 /*!< HSE used as CPU clock */ +#define LL_RCC_CPU_CLKSOURCE_STATUS_IC1 (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0) /*!< IC1 used as CPU clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System bus clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI 0U /*!< Select HSI as system bus clocks */ +#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR1_SYSSW_0 /*!< Select MSI as system bus clocks */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SYSSW_1 /*!< Select HSE as system bus clocks */ +#define LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11 (RCC_CFGR1_SYSSW_1 | RCC_CFGR1_SYSSW_0) /*!< Select IC2/IC6/IC11 as system bus clocks */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System bus clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system bus clocks */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR1_SYSSWS_0 /*!< MSI used as system bus clocks */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SYSSWS_1 /*!< HSE used as system bus clocks */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11 (RCC_CFGR1_SYSSWS_1 | RCC_CFGR1_SYSSWS_0) /*!< IC2/IC6/IC11 used as system bus clocks */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source + * @{ + */ +#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 0U +#define LL_RCC_SYSWAKEUP_CLKSOURCE_MSI RCC_CFGR1_STOPWUCK +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler + * @{ + */ +#define LL_RCC_AHB_DIV_1 0U +#define LL_RCC_AHB_DIV_2 RCC_CFGR2_HPRE_0 +#define LL_RCC_AHB_DIV_4 RCC_CFGR2_HPRE_1 +#define LL_RCC_AHB_DIV_8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) +#define LL_RCC_AHB_DIV_16 RCC_CFGR2_HPRE_2 +#define LL_RCC_AHB_DIV_32 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) +#define LL_RCC_AHB_DIV_64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) +#define LL_RCC_AHB_DIV_128 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler + * @{ + */ +#define LL_RCC_APB1_DIV_1 0U +#define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_0 +#define LL_RCC_APB1_DIV_4 RCC_CFGR2_PPRE1_1 +#define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) +#define LL_RCC_APB1_DIV_16 RCC_CFGR2_PPRE1_2 +#define LL_RCC_APB1_DIV_32 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) +#define LL_RCC_APB1_DIV_64 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) +#define LL_RCC_APB1_DIV_128 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler + * @{ + */ +#define LL_RCC_APB2_DIV_1 0U +#define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_0 +#define LL_RCC_APB2_DIV_4 RCC_CFGR2_PPRE2_1 +#define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) +#define LL_RCC_APB2_DIV_16 RCC_CFGR2_PPRE2_2 +#define LL_RCC_APB2_DIV_32 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) +#define LL_RCC_APB2_DIV_64 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) +#define LL_RCC_APB2_DIV_128 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB4_DIV APB4 prescaler + * @{ + */ +#define LL_RCC_APB4_DIV_1 0U +#define LL_RCC_APB4_DIV_2 RCC_CFGR2_PPRE4_0 +#define LL_RCC_APB4_DIV_4 RCC_CFGR2_PPRE4_1 +#define LL_RCC_APB4_DIV_8 (RCC_CFGR2_PPRE4_1 | RCC_CFGR2_PPRE4_0) +#define LL_RCC_APB4_DIV_16 RCC_CFGR2_PPRE4_2 +#define LL_RCC_APB4_DIV_32 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_0) +#define LL_RCC_APB4_DIV_64 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_1) +#define LL_RCC_APB4_DIV_128 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_1 | RCC_CFGR2_PPRE4_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB5_DIV APB5 prescaler + * @{ + */ +#define LL_RCC_APB5_DIV_1 0U +#define LL_RCC_APB5_DIV_2 RCC_CFGR2_PPRE5_0 +#define LL_RCC_APB5_DIV_4 RCC_CFGR2_PPRE5_1 +#define LL_RCC_APB5_DIV_8 (RCC_CFGR2_PPRE5_1 | RCC_CFGR2_PPRE5_0) +#define LL_RCC_APB5_DIV_16 RCC_CFGR2_PPRE5_2 +#define LL_RCC_APB5_DIV_32 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_0) +#define LL_RCC_APB5_DIV_64 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_1) +#define LL_RCC_APB5_DIV_128 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_1 | RCC_CFGR2_PPRE5_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx MCO selection + * @{ + */ +#define LL_RCC_MCO1 RCC_MISCENR_MCO1EN +#define LL_RCC_MCO2 RCC_MISCENR_MCO2EN +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI ((RCC_CCIPR5_MCO1SEL<<16U) | 0U) +#define LL_RCC_MCO1SOURCE_LSE ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_MSI ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_1) +#define LL_RCC_MCO1SOURCE_LSI ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_1 | RCC_CCIPR5_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_HSE ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2) +#define LL_RCC_MCO1SOURCE_IC5 ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_IC10 ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_1) +#define LL_RCC_MCO1SOURCE_SYSA ((RCC_CCIPR5_MCO1SEL<<16U) |\ + RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_1 | RCC_CCIPR5_MCO1SEL_0) +#define LL_RCC_MCO2SOURCE_HSI ((RCC_CCIPR5_MCO2SEL<<16U) | 0U) +#define LL_RCC_MCO2SOURCE_LSE ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_MSI ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_1) +#define LL_RCC_MCO2SOURCE_LSI ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_1 | RCC_CCIPR5_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_HSE ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2) +#define LL_RCC_MCO2SOURCE_IC15 ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_IC20 ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_1) +#define LL_RCC_MCO2SOURCE_SYSB ((RCC_CCIPR5_MCO2SEL<<16U) |\ + RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_1 | RCC_CCIPR5_MCO2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (RCC_CCIPR5_MCO1PRE<<16U) +#define LL_RCC_MCO1_DIV_2 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_3 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_4 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_5 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_6 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_7 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_8 ((RCC_CCIPR5_MCO1PRE<<16U) |\ + RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_9 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_10 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_11 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_12 ((RCC_CCIPR5_MCO1PRE<<16U) |\ + RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_13 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_14 ((RCC_CCIPR5_MCO1PRE<<16U) |\ + RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_15 ((RCC_CCIPR5_MCO1PRE<<16U) |\ + RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_16 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE) +#define LL_RCC_MCO2_DIV_1 (RCC_CCIPR5_MCO2PRE<<16U) +#define LL_RCC_MCO2_DIV_2 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_3 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_4 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_5 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_6 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_7 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_8 ((RCC_CCIPR5_MCO2PRE<<16U) |\ + RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_9 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_10 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_11 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_12 ((RCC_CCIPR5_MCO2PRE<<16U) |\ + RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_13 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_14 ((RCC_CCIPR5_MCO2PRE<<16U) |\ + RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_15 ((RCC_CCIPR5_MCO2PRE<<16U) |\ + RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_16 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE) + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSE_DIV Prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_HSE_DIV_1 0U +#define LL_RCC_RTC_HSE_DIV_4 RCC_CCIPR7_RTCPRE_0 +#define LL_RCC_RTC_HSE_DIV_9 RCC_CCIPR7_RTCPRE_1 +#define LL_RCC_RTC_HSE_DIV_16 (RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_25 RCC_CCIPR7_RTCPRE_2 +#define LL_RCC_RTC_HSE_DIV_36 (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_49 (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_64 (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_81 RCC_CCIPR7_RTCPRE_3 +#define LL_RCC_RTC_HSE_DIV_100 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_121 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_144 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_169 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_196 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_225 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_256 (RCC_CCIPR7_RTCPRE_3 |\ + RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_289 RCC_CCIPR7_RTCPRE_4 +#define LL_RCC_RTC_HSE_DIV_324 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_361 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_400 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_441 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_484 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_529 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_576 (RCC_CCIPR7_RTCPRE_4 |\ + RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_625 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_676 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_729 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_784 (RCC_CCIPR7_RTCPRE_4 |\ + RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_841 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_900 (RCC_CCIPR7_RTCPRE_4 |\ + RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_961 (RCC_CCIPR7_RTCPRE_4 |\ + RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_1024 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 |\ + RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_1089 RCC_CCIPR7_RTCPRE_5 +#define LL_RCC_RTC_HSE_DIV_1156 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_1225 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_1296 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_1369 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_1444 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_1521 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_1600 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_1681 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_1764 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_1849 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_1936 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_2025 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_2116 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_2209 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_2304 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 |\ + RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_2401 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_2500 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_2601 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_2704 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_2809 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_2916 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_3025 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_3136 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 |\ + RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_3249 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_3364 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_3481 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_3600 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\ + RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_3721 (RCC_CCIPR7_RTCPRE_5 |\ + RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_3844 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\ + RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_3969 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\ + RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_4096 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\ + RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_HCLK 0U +#define LL_RCC_ADC_CLKSOURCE_CLKP RCC_CCIPR1_ADC12SEL_0 +#define LL_RCC_ADC_CLKSOURCE_IC7 RCC_CCIPR1_ADC12SEL_1 +#define LL_RCC_ADC_CLKSOURCE_IC8 (RCC_CCIPR1_ADC12SEL_1 | RCC_CCIPR1_ADC12SEL_0) +#define LL_RCC_ADC_CLKSOURCE_MSI RCC_CCIPR1_ADC12SEL_2 +#define LL_RCC_ADC_CLKSOURCE_HSI (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_0) +#define LL_RCC_ADC_CLKSOURCE_I2S_CKIN (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_1) +#define LL_RCC_ADC_CLKSOURCE_TIMG (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_1 | RCC_CCIPR1_ADC12SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADF_CLKSOURCE Peripheral ADF clock source selection + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE_HCLK 0U +#define LL_RCC_ADF1_CLKSOURCE_CLKP RCC_CCIPR1_ADF1SEL_0 +#define LL_RCC_ADF1_CLKSOURCE_IC7 RCC_CCIPR1_ADF1SEL_1 +#define LL_RCC_ADF1_CLKSOURCE_IC8 (RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0) +#define LL_RCC_ADF1_CLKSOURCE_MSI RCC_CCIPR1_ADF1SEL_2 +#define LL_RCC_ADF1_CLKSOURCE_HSI (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_0) +#define LL_RCC_ADF1_CLKSOURCE_I2S_CKIN (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_1) +#define LL_RCC_ADF1_CLKSOURCE_TIMG (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection + * @{ + */ +#define LL_RCC_CLKP_CLKSOURCE_HSI 0U +#define LL_RCC_CLKP_CLKSOURCE_MSI RCC_CCIPR7_PERSEL_0 +#define LL_RCC_CLKP_CLKSOURCE_HSE RCC_CCIPR7_PERSEL_1 +#define LL_RCC_CLKP_CLKSOURCE_IC19 (RCC_CCIPR7_PERSEL_1 | RCC_CCIPR7_PERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_IC5 RCC_CCIPR7_PERSEL_2 +#define LL_RCC_CLKP_CLKSOURCE_IC10 (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_IC15 (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_1) +#define LL_RCC_CLKP_CLKSOURCE_IC20 (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_1 | RCC_CCIPR7_PERSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DCMIPP_CLKSOURCE Peripheral DCMIPP clock source selection + * @{ + */ +#define LL_RCC_DCMIPP_CLKSOURCE_PCLK5 0U +#define LL_RCC_DCMIPP_CLKSOURCE_CLKP RCC_CCIPR1_DCMIPPSEL_0 +#define LL_RCC_DCMIPP_CLKSOURCE_IC17 RCC_CCIPR1_DCMIPPSEL_1 +#define LL_RCC_DCMIPP_CLKSOURCE_HSI (RCC_CCIPR1_DCMIPPSEL_1 | RCC_CCIPR1_DCMIPPSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETH_CLKSOURCE Peripheral ETH kernel clock source selection + * @{ + */ +#define LL_RCC_ETH1_CLKSOURCE_HCLK 0U +#define LL_RCC_ETH1_CLKSOURCE_CLKP RCC_CCIPR2_ETH1CLKSEL_0 +#define LL_RCC_ETH1_CLKSOURCE_IC12 RCC_CCIPR2_ETH1CLKSEL_1 +#define LL_RCC_ETH1_CLKSOURCE_HSE (RCC_CCIPR2_ETH1CLKSEL_1 | RCC_CCIPR2_ETH1CLKSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHPHY_IF Peripheral ETH PHY interface selection + * @{ + */ +#define LL_RCC_ETH1PHY_IF_MII 0U +#define LL_RCC_ETH1PHY_IF_RGMII RCC_CCIPR2_ETH1SEL_0 +#define LL_RCC_ETH1PHY_IF_RMII RCC_CCIPR2_ETH1SEL_2 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHREFRX_CLKSOURCE Peripheral ETH Reference RX clock source selection + * @{ + */ +#define LL_RCC_ETH1REFRX_CLKSOURCE_EXT 0U +#define LL_RCC_ETH1REFRX_CLKSOURCE_INT RCC_CCIPR2_ETH1REFCLKSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHREFTX_CLKSOURCE Peripheral ETH Reference TX clock source selection + * @{ + */ +#define LL_RCC_ETH1REFTX_CLKSOURCE_EXT 0U +#define LL_RCC_ETH1REFTX_CLKSOURCE_INT RCC_CCIPR2_ETH1GTXCLKSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHPTP_CLKSOURCE Peripheral ETH PTP kernel clock source selection + * @{ + */ +#define LL_RCC_ETH1PTP_CLKSOURCE_HCLK 0U +#define LL_RCC_ETH1PTP_CLKSOURCE_CLKP RCC_CCIPR2_ETH1PTPSEL_0 +#define LL_RCC_ETH1PTP_CLKSOURCE_IC13 RCC_CCIPR2_ETH1PTPSEL_1 +#define LL_RCC_ETH1PTP_CLKSOURCE_HSE (RCC_CCIPR2_ETH1PTPSEL_1 | RCC_CCIPR2_ETH1PTPSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETH1PTP_DIV ETH1 PTP kernel clock divider selection + * @{ + */ +#define LL_RCC_ETH1PTP_DIV_1 0U +#define LL_RCC_ETH1PTP_DIV_2 RCC_CCIPR2_ETH1PTPDIV_0 +#define LL_RCC_ETH1PTP_DIV_3 RCC_CCIPR2_ETH1PTPDIV_1 +#define LL_RCC_ETH1PTP_DIV_4 (RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0) +#define LL_RCC_ETH1PTP_DIV_5 RCC_CCIPR2_ETH1PTPDIV_2 +#define LL_RCC_ETH1PTP_DIV_6 (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_0) +#define LL_RCC_ETH1PTP_DIV_7 (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1) +#define LL_RCC_ETH1PTP_DIV_8 (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0) +#define LL_RCC_ETH1PTP_DIV_9 RCC_CCIPR2_ETH1PTPDIV_3 +#define LL_RCC_ETH1PTP_DIV_10 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_0) +#define LL_RCC_ETH1PTP_DIV_11 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_1) +#define LL_RCC_ETH1PTP_DIV_12 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0) +#define LL_RCC_ETH1PTP_DIV_13 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2) +#define LL_RCC_ETH1PTP_DIV_14 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_0) +#define LL_RCC_ETH1PTP_DIV_15 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1) +#define LL_RCC_ETH1PTP_DIV_16 (RCC_CCIPR2_ETH1PTPDIV_3 |\ + RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0U +#define LL_RCC_FDCAN_CLKSOURCE_CLKP RCC_CCIPR3_FDCANSEL_0 +#define LL_RCC_FDCAN_CLKSOURCE_IC19 RCC_CCIPR3_FDCANSEL_1 +#define LL_RCC_FDCAN_CLKSOURCE_HSE (RCC_CCIPR3_FDCANSEL_1 | RCC_CCIPR3_FDCANSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection + * @{ + */ +#define LL_RCC_FMC_CLKSOURCE_HCLK 0U +#define LL_RCC_FMC_CLKSOURCE_CLKP RCC_CCIPR3_FMCSEL_0 +#define LL_RCC_FMC_CLKSOURCE_IC3 RCC_CCIPR3_FMCSEL_1 +#define LL_RCC_FMC_CLKSOURCE_IC4 (RCC_CCIPR3_FMCSEL_1 | RCC_CCIPR3_FMCSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0U) +#define LL_RCC_I2C1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\ + RCC_CCIPR4_I2C1SEL_0) +#define LL_RCC_I2C1_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\ + RCC_CCIPR4_I2C1SEL_1) +#define LL_RCC_I2C1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\ + RCC_CCIPR4_I2C1SEL_1 | RCC_CCIPR4_I2C1SEL_0) +#define LL_RCC_I2C1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\ + RCC_CCIPR4_I2C1SEL_2) +#define LL_RCC_I2C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\ + RCC_CCIPR4_I2C1SEL_2| RCC_CCIPR4_I2C1SEL_0) + +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0U) +#define LL_RCC_I2C2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\ + RCC_CCIPR4_I2C2SEL_0) +#define LL_RCC_I2C2_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\ + RCC_CCIPR4_I2C2SEL_1) +#define LL_RCC_I2C2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\ + RCC_CCIPR4_I2C2SEL_1 | RCC_CCIPR4_I2C2SEL_0) +#define LL_RCC_I2C2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\ + RCC_CCIPR4_I2C2SEL_2) +#define LL_RCC_I2C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\ + RCC_CCIPR4_I2C2SEL_2 | RCC_CCIPR4_I2C2SEL_0) + +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0UL) +#define LL_RCC_I2C3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ + RCC_CCIPR4_I2C3SEL_0) +#define LL_RCC_I2C3_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ + RCC_CCIPR4_I2C3SEL_1) +#define LL_RCC_I2C3_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ + RCC_CCIPR4_I2C3SEL_1 | RCC_CCIPR4_I2C3SEL_0) +#define LL_RCC_I2C3_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ + RCC_CCIPR4_I2C3SEL_2) +#define LL_RCC_I2C3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ + RCC_CCIPR4_I2C3SEL_2| RCC_CCIPR4_I2C3SEL_0) + +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0UL) +#define LL_RCC_I2C4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\ + RCC_CCIPR4_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\ + RCC_CCIPR4_I2C4SEL_1) +#define LL_RCC_I2C4_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\ + RCC_CCIPR4_I2C4SEL_1 | RCC_CCIPR4_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\ + RCC_CCIPR4_I2C4SEL_2) +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\ + RCC_CCIPR4_I2C4SEL_2| RCC_CCIPR4_I2C4SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I3C_CLKSOURCE Peripheral I3C clock source selection + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0UL) +#define LL_RCC_I3C1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ + RCC_CCIPR4_I3C1SEL_0) +#define LL_RCC_I3C1_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ + RCC_CCIPR4_I3C1SEL_1) +#define LL_RCC_I3C1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ + RCC_CCIPR4_I3C1SEL_1 | RCC_CCIPR4_I3C1SEL_0) +#define LL_RCC_I3C1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ + RCC_CCIPR4_I3C1SEL_2) +#define LL_RCC_I3C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ + RCC_CCIPR4_I3C1SEL_2| RCC_CCIPR4_I3C1SEL_0) + +#define LL_RCC_I3C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0UL) +#define LL_RCC_I3C2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\ + RCC_CCIPR4_I3C2SEL_0) +#define LL_RCC_I3C2_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\ + RCC_CCIPR4_I3C2SEL_1) +#define LL_RCC_I3C2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\ + RCC_CCIPR4_I3C2SEL_1 | RCC_CCIPR4_I3C2SEL_0) +#define LL_RCC_I3C2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\ + RCC_CCIPR4_I3C2SEL_2) +#define LL_RCC_I3C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\ + RCC_CCIPR4_I3C2SEL_2 | RCC_CCIPR4_I3C2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0UL) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_1 |\ + RCC_CCIPR12_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_2 |\ + RCC_CCIPR12_LPTIM1SEL_0) + +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0UL) +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_1 |\ + RCC_CCIPR12_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_2) +#define LL_RCC_LPTIM2_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_2 |\ + RCC_CCIPR12_LPTIM2SEL_0) + +#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0UL) +#define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_0) +#define LL_RCC_LPTIM3_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_1) +#define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_1 |\ + RCC_CCIPR12_LPTIM3SEL_0) +#define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_2) +#define LL_RCC_LPTIM3_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_2 |\ + RCC_CCIPR12_LPTIM3SEL_0) + +#define LL_RCC_LPTIM4_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0UL) +#define LL_RCC_LPTIM4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_0) +#define LL_RCC_LPTIM4_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_1) +#define LL_RCC_LPTIM4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_1 |\ + RCC_CCIPR12_LPTIM4SEL_0) +#define LL_RCC_LPTIM4_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_2) +#define LL_RCC_LPTIM4_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_2 |\ + RCC_CCIPR12_LPTIM4SEL_0) + +#define LL_RCC_LPTIM5_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0UL) +#define LL_RCC_LPTIM5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_0) +#define LL_RCC_LPTIM5_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_1) +#define LL_RCC_LPTIM5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_1 |\ + RCC_CCIPR12_LPTIM5SEL_0) +#define LL_RCC_LPTIM5_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_2) +#define LL_RCC_LPTIM5_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_2 |\ + RCC_CCIPR12_LPTIM5SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 0U +#define LL_RCC_LPUART1_CLKSOURCE_CLKP RCC_CCIPR14_LPUART1SEL_0 +#define LL_RCC_LPUART1_CLKSOURCE_IC9 RCC_CCIPR14_LPUART1SEL_1 +#define LL_RCC_LPUART1_CLKSOURCE_IC14 (RCC_CCIPR14_LPUART1SEL_1 | RCC_CCIPR14_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR14_LPUART1SEL_2 +#define LL_RCC_LPUART1_CLKSOURCE_MSI (RCC_CCIPR14_LPUART1SEL_2 | RCC_CCIPR14_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_CCIPR14_LPUART1SEL_2 | RCC_CCIPR14_LPUART1SEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PCLK5 0U +#define LL_RCC_LTDC_CLKSOURCE_CLKP RCC_CCIPR4_LTDCSEL_0 +#define LL_RCC_LTDC_CLKSOURCE_IC16 RCC_CCIPR4_LTDCSEL_1 +#define LL_RCC_LTDC_CLKSOURCE_HSI (RCC_CCIPR4_LTDCSEL_1 | RCC_CCIPR4_LTDCSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MDF_CLKSOURCE Peripheral MDF clock source selection + * @{ + */ +#define LL_RCC_MDF1_CLKSOURCE_HCLK 0U +#define LL_RCC_MDF1_CLKSOURCE_CLKP RCC_CCIPR5_MDF1SEL_0 +#define LL_RCC_MDF1_CLKSOURCE_IC7 RCC_CCIPR5_MDF1SEL_1 +#define LL_RCC_MDF1_CLKSOURCE_IC8 (RCC_CCIPR5_MDF1SEL_1 | RCC_CCIPR5_MDF1SEL_0) +#define LL_RCC_MDF1_CLKSOURCE_MSI RCC_CCIPR5_MDF1SEL_2 +#define LL_RCC_MDF1_CLKSOURCE_HSI (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_0) +#define LL_RCC_MDF1_CLKSOURCE_I2S_CKIN (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_1) +#define LL_RCC_MDF1_CLKSOURCE_TIMG (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_1 | RCC_CCIPR5_MDF1SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OTGPHY_CLKSOURCE Peripheral OTGPHY clock source selection + * @{ + */ +#define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0UL) +#define LL_RCC_OTGPHY1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_0) +#define LL_RCC_OTGPHY1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1) +#define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1 |\ + RCC_CCIPR6_OTGPHY1SEL_0) + +#define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0UL) +#define LL_RCC_OTGPHY2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_0) +#define LL_RCC_OTGPHY2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1) +#define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1 |\ + RCC_CCIPR6_OTGPHY2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OTGPHYCKREF_CLKSOURCE Peripheral OTGPHYCKREF clock source selection + * @{ + */ +#define LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0UL) +#define LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, RCC_CCIPR6_OTGPHY1CKREFSEL) + +#define LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0UL) +#define LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, RCC_CCIPR6_OTGPHY2CKREFSEL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PSSI_CLKSOURCE Peripheral PSSI clock source selection + * @{ + */ +#define LL_RCC_PSSI_CLKSOURCE_HCLK 0U +#define LL_RCC_PSSI_CLKSOURCE_CLKP RCC_CCIPR7_PSSISEL_0 +#define LL_RCC_PSSI_CLKSOURCE_IC20 RCC_CCIPR7_PSSISEL_1 +#define LL_RCC_PSSI_CLKSOURCE_HSI (RCC_CCIPR7_PSSISEL_1 | RCC_CCIPR7_PSSISEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0U +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_CCIPR7_RTCSEL_0 +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_CCIPR7_RTCSEL_1 +#define LL_RCC_RTC_CLKSOURCE_HSE (RCC_CCIPR7_RTCSEL_1 | RCC_CCIPR7_RTCSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0UL) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_IC7 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1 |\ + RCC_CCIPR7_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2) +#define LL_RCC_SAI1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\ + RCC_CCIPR7_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\ + RCC_CCIPR7_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\ + RCC_CCIPR7_SAI1SEL_1 | RCC_CCIPR7_SAI1SEL_0) + +#define LL_RCC_SAI2_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0UL) +#define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_0) +#define LL_RCC_SAI2_CLKSOURCE_IC7 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1) +#define LL_RCC_SAI2_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1 |\ + RCC_CCIPR7_SAI2SEL_0) +#define LL_RCC_SAI2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2) +#define LL_RCC_SAI2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\ + RCC_CCIPR7_SAI2SEL_0) +#define LL_RCC_SAI2_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\ + RCC_CCIPR7_SAI2SEL_1) +#define LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\ + RCC_CCIPR7_SAI2SEL_1 | RCC_CCIPR7_SAI2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0UL) +#define LL_RCC_SDMMC1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_0) +#define LL_RCC_SDMMC1_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1) +#define LL_RCC_SDMMC1_CLKSOURCE_IC5 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1 |\ + RCC_CCIPR8_SDMMC1SEL_0) + +#define LL_RCC_SDMMC2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0UL) +#define LL_RCC_SDMMC2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_0) +#define LL_RCC_SDMMC2_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1) +#define LL_RCC_SDMMC2_CLKSOURCE_IC5 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1 |\ + RCC_CCIPR8_SDMMC2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1 0U +#define LL_RCC_SPDIFRX1_CLKSOURCE_CLKP RCC_CCIPR9_SPDIFRX1SEL_0 +#define LL_RCC_SPDIFRX1_CLKSOURCE_IC7 RCC_CCIPR9_SPDIFRX1SEL_1 +#define LL_RCC_SPDIFRX1_CLKSOURCE_IC8 (RCC_CCIPR9_SPDIFRX1SEL_1 | RCC_CCIPR9_SPDIFRX1SEL_0) +#define LL_RCC_SPDIFRX1_CLKSOURCE_MSI RCC_CCIPR9_SPDIFRX1SEL_2 +#define LL_RCC_SPDIFRX1_CLKSOURCE_HSI (RCC_CCIPR9_SPDIFRX1SEL_2 | RCC_CCIPR9_SPDIFRX1SEL_0) +#define LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN (RCC_CCIPR9_SPDIFRX1SEL_2 | RCC_CCIPR9_SPDIFRX1SEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPI clock source selection + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0UL) +#define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_0) +#define LL_RCC_SPI1_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1) +#define LL_RCC_SPI1_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1 |\ + RCC_CCIPR9_SPI1SEL_0) +#define LL_RCC_SPI1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2) +#define LL_RCC_SPI1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2 |\ + RCC_CCIPR9_SPI1SEL_0) +#define LL_RCC_SPI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2 |\ + RCC_CCIPR9_SPI1SEL_1) + +#define LL_RCC_SPI2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0UL) +#define LL_RCC_SPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_0) +#define LL_RCC_SPI2_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1) +#define LL_RCC_SPI2_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1 |\ + RCC_CCIPR9_SPI2SEL_0) +#define LL_RCC_SPI2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2) +#define LL_RCC_SPI2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2 |\ + RCC_CCIPR9_SPI2SEL_0) +#define LL_RCC_SPI2_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2 |\ + RCC_CCIPR9_SPI2SEL_1) + +#define LL_RCC_SPI3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0UL) +#define LL_RCC_SPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_0) +#define LL_RCC_SPI3_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1) +#define LL_RCC_SPI3_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1 |\ + RCC_CCIPR9_SPI3SEL_0) +#define LL_RCC_SPI3_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2) +#define LL_RCC_SPI3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2 |\ + RCC_CCIPR9_SPI3SEL_0) +#define LL_RCC_SPI3_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2 |\ + RCC_CCIPR9_SPI3SEL_1) + +#define LL_RCC_SPI4_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0UL) +#define LL_RCC_SPI4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_0) +#define LL_RCC_SPI4_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1) +#define LL_RCC_SPI4_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1 |\ + RCC_CCIPR9_SPI4SEL_0) +#define LL_RCC_SPI4_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2) +#define LL_RCC_SPI4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2 |\ + RCC_CCIPR9_SPI4SEL_0) +#define LL_RCC_SPI4_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2 |\ + RCC_CCIPR9_SPI4SEL_1) + +#define LL_RCC_SPI5_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0UL) +#define LL_RCC_SPI5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_0) +#define LL_RCC_SPI5_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1) +#define LL_RCC_SPI5_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1 |\ + RCC_CCIPR9_SPI5SEL_0) +#define LL_RCC_SPI5_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2) +#define LL_RCC_SPI5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2 |\ + RCC_CCIPR9_SPI5SEL_0) +#define LL_RCC_SPI5_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2 |\ + RCC_CCIPR9_SPI5SEL_1) + +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0UL) +#define LL_RCC_SPI6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1 |\ + RCC_CCIPR9_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2 |\ + RCC_CCIPR9_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2 |\ + RCC_CCIPR9_SPI6SEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UART clock source selection + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0UL) +#define LL_RCC_UART4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_0) +#define LL_RCC_UART4_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1) +#define LL_RCC_UART4_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1 |\ + RCC_CCIPR13_UART4SEL_0) +#define LL_RCC_UART4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2) +#define LL_RCC_UART4_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2 |\ + RCC_CCIPR13_UART4SEL_0) +#define LL_RCC_UART4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2 |\ + RCC_CCIPR13_UART4SEL_1) + +#define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0UL) +#define LL_RCC_UART5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_0) +#define LL_RCC_UART5_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1) +#define LL_RCC_UART5_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1 |\ + RCC_CCIPR13_UART5SEL_0) +#define LL_RCC_UART5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2) +#define LL_RCC_UART5_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2 |\ + RCC_CCIPR13_UART5SEL_0) +#define LL_RCC_UART5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2 |\ + RCC_CCIPR13_UART5SEL_1) + +#define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0UL) +#define LL_RCC_UART7_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_0) +#define LL_RCC_UART7_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1) +#define LL_RCC_UART7_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1 |\ + RCC_CCIPR13_UART7SEL_0) +#define LL_RCC_UART7_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2) +#define LL_RCC_UART7_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2 |\ + RCC_CCIPR13_UART7SEL_0) +#define LL_RCC_UART7_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2 |\ + RCC_CCIPR13_UART7SEL_1) + +#define LL_RCC_UART8_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0UL) +#define LL_RCC_UART8_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_0) +#define LL_RCC_UART8_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1) +#define LL_RCC_UART8_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1 |\ + RCC_CCIPR13_UART8SEL_0) +#define LL_RCC_UART8_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2) +#define LL_RCC_UART8_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2 |\ + RCC_CCIPR13_UART8SEL_0) +#define LL_RCC_UART8_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2 |\ + RCC_CCIPR13_UART8SEL_1) + +#define LL_RCC_UART9_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0UL) +#define LL_RCC_UART9_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_0) +#define LL_RCC_UART9_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1) +#define LL_RCC_UART9_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1 |\ + RCC_CCIPR14_UART9SEL_0) +#define LL_RCC_UART9_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2) +#define LL_RCC_UART9_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2 |\ + RCC_CCIPR14_UART9SEL_0) +#define LL_RCC_UART9_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2 |\ + RCC_CCIPR14_UART9SEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0UL) +#define LL_RCC_USART1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_0) +#define LL_RCC_USART1_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1) +#define LL_RCC_USART1_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1 |\ + RCC_CCIPR13_USART1SEL_0) +#define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2) +#define LL_RCC_USART1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2 |\ + RCC_CCIPR13_USART1SEL_0) +#define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2 |\ + RCC_CCIPR13_USART1SEL_1) + +#define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0UL) +#define LL_RCC_USART2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_0) +#define LL_RCC_USART2_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1) +#define LL_RCC_USART2_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1 |\ + RCC_CCIPR13_USART2SEL_0) +#define LL_RCC_USART2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2) +#define LL_RCC_USART2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2 |\ + RCC_CCIPR13_USART2SEL_0) +#define LL_RCC_USART2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2 |\ + RCC_CCIPR13_USART2SEL_1) + +#define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0UL) +#define LL_RCC_USART3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_0) +#define LL_RCC_USART3_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1) +#define LL_RCC_USART3_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1 |\ + RCC_CCIPR13_USART3SEL_0) +#define LL_RCC_USART3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2) +#define LL_RCC_USART3_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2 |\ + RCC_CCIPR13_USART3SEL_0) +#define LL_RCC_USART3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2 |\ + RCC_CCIPR13_USART3SEL_1) + +#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0UL) +#define LL_RCC_USART6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_0) +#define LL_RCC_USART6_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1) +#define LL_RCC_USART6_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1 |\ + RCC_CCIPR13_USART6SEL_0) +#define LL_RCC_USART6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2) +#define LL_RCC_USART6_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2 |\ + RCC_CCIPR13_USART6SEL_0) +#define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2 |\ + RCC_CCIPR13_USART6SEL_1) + +#define LL_RCC_USART10_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0UL) +#define LL_RCC_USART10_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_0) +#define LL_RCC_USART10_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1) +#define LL_RCC_USART10_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1 |\ + RCC_CCIPR14_USART10SEL_0) +#define LL_RCC_USART10_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2) +#define LL_RCC_USART10_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2 |\ + RCC_CCIPR14_USART10SEL_0) +#define LL_RCC_USART10_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2 |\ + RCC_CCIPR14_USART10SEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_XSPI_CLKSOURCE Peripheral XSPI clock source selection + * @{ + */ +#define LL_RCC_XSPI1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0UL) +#define LL_RCC_XSPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_0) +#define LL_RCC_XSPI1_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1) +#define LL_RCC_XSPI1_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1 |\ + RCC_CCIPR6_XSPI1SEL_0) + +#define LL_RCC_XSPI2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0UL) +#define LL_RCC_XSPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_0) +#define LL_RCC_XSPI2_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1) +#define LL_RCC_XSPI2_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1 |\ + RCC_CCIPR6_XSPI2SEL_0) + +#define LL_RCC_XSPI3_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0UL) +#define LL_RCC_XSPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_0) +#define LL_RCC_XSPI3_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1) +#define LL_RCC_XSPI3_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1 |\ + RCC_CCIPR6_XSPI3SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR1_ADC12SEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADF Peripheral ADF get clock source + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR1_ADF1SEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source + * @{ + */ +#define LL_RCC_CLKP_CLKSOURCE RCC_CCIPR7_PERSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DCMIPP Peripheral DCMIPP get clock source + * @{ + */ +#define LL_RCC_DCMIPP_CLKSOURCE RCC_CCIPR1_DCMIPPSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETH Peripheral ETH get clock source + * @{ + */ +#define LL_RCC_ETH1_CLKSOURCE RCC_CCIPR2_ETH1CLKSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHPHY Peripheral ETH PHY get interface + * @{ + */ +#define LL_RCC_ETH1PHY_IF RCC_CCIPR2_ETH1SEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHPTP Peripheral ETHPTP get clock source + * @{ + */ +#define LL_RCC_ETH1PTP_CLKSOURCE RCC_CCIPR2_ETH1PTPSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHREFRX Peripheral ETH Reference RX get clock source + * @{ + */ +#define LL_RCC_ETH1REFRX_CLKSOURCE RCC_CCIPR2_ETH1REFCLKSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHREFTX Peripheral ETH Reference TX get clock source + * @{ + */ +#define LL_RCC_ETH1REFTX_CLKSOURCE RCC_CCIPR2_ETH1GTXCLKSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR3_FDCANSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source + * @{ + */ +#define LL_RCC_FMC_CLKSOURCE RCC_CCIPR3_FMCSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0UL) +#define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0UL) +#define LL_RCC_I2C3_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0UL) +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I3C Peripheral I3C get clock source + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0UL) +#define LL_RCC_I3C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0UL) +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0UL) +#define LL_RCC_LPTIM3_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0UL) +#define LL_RCC_LPTIM4_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0UL) +#define LL_RCC_LPTIM5_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART Peripheral LPUART get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR14_LPUART1SEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR4_LTDCSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MDF Peripheral MDF get clock source + * @{ + */ +#define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR5_MDF1SEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OTGPHY Peripheral OTGPHY get clock source + * @{ + */ +#define LL_RCC_OTGPHY1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0UL) +#define LL_RCC_OTGPHY2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OTGPHYCKREF Peripheral OTGPHYCKREF get clock source + * @{ + */ +#define LL_RCC_OTGPHY1CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0UL) +#define LL_RCC_OTGPHY2CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PSSI Peripheral PSSI get clock source + * @{ + */ +#define LL_RCC_PSSI_CLKSOURCE RCC_CCIPR7_PSSISEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAI Peripheral SAI get clock source + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0UL) +#define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0UL) +#define LL_RCC_SDMMC2_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_CCIPR9_SPDIFRX1SEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPI Peripheral SPI get clock source + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0UL) +#define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0UL) +#define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0UL) +#define LL_RCC_SPI4_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0UL) +#define LL_RCC_SPI5_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0UL) +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UART Peripheral UART get clock source + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0UL) +#define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0UL) +#define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0UL) +#define LL_RCC_UART8_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0UL) +#define LL_RCC_UART9_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USART Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0UL) +#define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0UL) +#define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0UL) +#define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0UL) +#define LL_RCC_USART10_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_XSPI Peripheral XSPI get clock source + * @{ + */ +#define LL_RCC_XSPI1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0UL) +#define LL_RCC_XSPI2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0UL) +#define LL_RCC_XSPI3_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0UL) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_1 0U +#define LL_RCC_TIM_PRESCALER_2 1U +#define LL_RCC_TIM_PRESCALER_4 2U +#define LL_RCC_TIM_PRESCALER_8 3U +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI 0U +#define LL_RCC_PLLSOURCE_MSI RCC_PLL1CFGR1_PLL1SEL_0 +#define LL_RCC_PLLSOURCE_HSE RCC_PLL1CFGR1_PLL1SEL_1 +#define LL_RCC_PLLSOURCE_I2S_CKIN (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ICSOURCE All ICs entry clock source + * @{ + */ +#define LL_RCC_ICCLKSOURCE_PLL1 0U +#define LL_RCC_ICCLKSOURCE_PLL2 RCC_IC1CFGR_IC1SEL_0 +#define LL_RCC_ICCLKSOURCE_PLL3 RCC_IC1CFGR_IC1SEL_1 +#define LL_RCC_ICCLKSOURCE_PLL4 (RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency. + * @param __HPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_32 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @retval HCLK clock frequency (in Hz) + */ +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> (((__HPRESCALER__) &\ + RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @arg @ref LL_RCC_APB1_DIV_32 + * @arg @ref LL_RCC_APB1_DIV_64 + * @arg @ref LL_RCC_APB1_DIV_128 + * @retval PCLK1 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (((__APB1PRESCALER__) &\ + RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos)) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @arg @ref LL_RCC_APB2_DIV_32 + * @arg @ref LL_RCC_APB2_DIV_64 + * @arg @ref LL_RCC_APB2_DIV_128 + * @retval PCLK2 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (((__APB2PRESCALER__) &\ + RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos)) + +/** + * @brief Helper macro to calculate the PCLK4 frequency (ABP4) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB4PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @arg @ref LL_RCC_APB4_DIV_32 + * @arg @ref LL_RCC_APB4_DIV_64 + * @arg @ref LL_RCC_APB4_DIV_128 + * @retval PCLK1 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> (((__APB4PRESCALER__) &\ + RCC_CFGR2_PPRE4) >> RCC_CFGR2_PPRE4_Pos)) + +/** + * @brief Helper macro to calculate the PCLK5 frequency (APB5) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB5PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB5_DIV_1 + * @arg @ref LL_RCC_APB5_DIV_2 + * @arg @ref LL_RCC_APB5_DIV_4 + * @arg @ref LL_RCC_APB5_DIV_8 + * @arg @ref LL_RCC_APB5_DIV_16 + * @arg @ref LL_RCC_APB5_DIV_32 + * @arg @ref LL_RCC_APB5_DIV_64 + * @arg @ref LL_RCC_APB5_DIV_128 + * @retval PCLK1 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK5_FREQ(__HCLKFREQ__, __APB5PRESCALER__) ((__HCLKFREQ__) >> (((__APB5PRESCALER__) &\ + RCC_CFGR2_PPRE5) >> RCC_CFGR2_PPRE5_Pos)) + +/** + * @brief Helper macro to calculate the TIMG frequency (timer group1 and group2) + * @param __SYSCLKFREQ__ SYSCLK frequency. + * @param __TIMPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_1 + * @arg @ref LL_RCC_TIM_PRESCALER_2 + * @arg @ref LL_RCC_TIM_PRESCALER_4 + * @arg @ref LL_RCC_TIM_PRESCALER_8 + * @retval TIMG clock frequency (in Hz) + */ +#define LL_RCC_CALC_TIMG_FREQ(__SYSCLKFREQ__, __TIMPRESCALER__) ((__SYSCLKFREQ__) >> (__TIMPRESCALER__)) + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFUL /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the HSE Clock Security System. + * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless + * a reset occurs or system enter in standby mode. + * @rmtoll HSECFGR HSECSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSON); +} + +/** + * @brief Check if HSE failure is detected by Clock Security System + * @rmtoll HSECFGR HSECSSD LL_RCC_HSE_IsFailureDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsFailureDetected(void) +{ + return ((READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSD) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable the HSE Clock Security System bypass. + * @note Bypass the HSE oscillator when a failure is detected and get the clock from + * the HSI oscillator (HSI injection) + * @rmtoll HSECFGR HSECSSBYP LL_RCC_HSE_EnableCSSBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSSBypass(void) +{ + SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBYP); +} + +/** + * @brief Disable the HSE Clock Security System bypass. + * @rmtoll HSECFGR HSECSSBYP LL_RCC_HSE_DisableCSSBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableCSSBypass(void) +{ + CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBYP); +} + +/** + * @brief Set HSE Clock Security System bypass divider + * @note To divide the replacement internal HSI oscillator that + * bypasses the HSE oscillator when a failure is detected + * @rmtoll HSECFGR HSECSSBPRE LL_RCC_HSE_SetCSSBypassDivider + * @param Divider This parameter can be a value from RCC_LL_EC_HSECSSBYP_DIV. + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SetCSSBypassDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->HSECFGR, RCC_HSECFGR_HSECSSBPRE, Divider); +} + +/** + * @brief Get HSE Clock Security System bypass divider + * @note To divide the replacement internal HSI oscillator that + * bypasses the HSE oscillator when a failure is detected + * @rmtoll HSECFGR HSECSSBPRE LL_RCC_HSE_GetCSSBypassDivider + * @retval can be a value from RCC_LL_EC_HSECSSBYP_DIV. + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_GetCSSBypassDivider(void) +{ + return (READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBPRE)); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll HSECFGR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll HSECFGR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP); +} + +/** + * @brief Select the Analog HSE external clock type in Bypass mode + * @rmtoll HSECFGR HSEEXT LL_RCC_HSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT); +} + +/** + * @brief Select the Digital HSE external clock type in Bypass mode + * @rmtoll HSECFGR HSEEXT LL_RCC_HSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT); +} + +/** + * @brief Select the HSE as hse_div2_osc_ck output clock + * @rmtoll HSECFGR HSEDIV2SEL LL_RCC_HSE_SelectHSEAsDiv2Clock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectHSEAsDiv2Clock(void) +{ + CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL); +} + +/** + * @brief Select the HSE divided by 2 as hse_div2_osc_ck output clock + * @rmtoll HSECFGR HSEDIV2SEL LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(void) +{ + SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL); +} + +/** + * @brief Check if hse_div2_osc_ck output clock is divided by 2 + * @rmtoll HSECFGR HSEDIV2SEL LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock(void) +{ + return ((READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL) == RCC_HSECFGR_HSEDIV2SEL) ? 1UL : 0UL); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CSR HSEONS LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_HSEONS); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CCR HSEONC LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_HSEONC); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll SR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_HSERDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CSR HSIONS LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_HSIONS); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CCR HSIONC LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_HSIONC); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll SR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_HSIRDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Set HSI divider + * @rmtoll HSICFGR HSIDIV LL_RCC_HSI_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSIDIV, Divider); +} + +/** + * @brief Get HSI divider + * @rmtoll HSICFGR HSIDIV LL_RCC_HSI_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) +{ + return (READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSIDIV)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration + * @retval A value between 0 and 511 (0x1FF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 32, which, when added to the HSICAL value, + * should trim the HSI to 32 MHz +/- 1 % + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value This parameter can be a value between 0 and 63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +} + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll STOPCR HSISTOPEN LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll STOPCR HSISTOPEN LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN); +} + +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll STOPCR HSISTOPEN LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN) == RCC_STOPCR_HSISTOPEN) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSI MSI + * @{ + */ + +/** + * @brief Enable MSI oscillator + * @rmtoll CSR MSIONS LL_RCC_MSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_MSIONS); +} + +/** + * @brief Disable MSI oscillator + * @rmtoll CCR MSIONC LL_RCC_MSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_MSIONC); +} + +/** + * @brief Check if MSI clock is ready + * @rmtoll SR MSIRDY LL_RCC_MSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_MSIRDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Set MSI frequency + * @rmtoll MSICFGR MSIFREQSEL LL_RCC_MSI_SetFrequency + * @param Value This parameter can be one of the following values: + * @arg @ref LL_RCC_MSI_FREQ_4MHZ + * @arg @ref LL_RCC_MSI_FREQ_16MHZ + * @retval None. + */ +__STATIC_INLINE void LL_RCC_MSI_SetFrequency(uint32_t Value) +{ + MODIFY_REG(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL, Value); +} + +/** + * @brief Get HSI divider + * @rmtoll MSICFGR MSIFREQSEL LL_RCC_MSI_GetFrequency + * @retval can be one of the following values: + * @arg @ref LL_RCC_MSI_FREQ_4MHZ + * @arg @ref LL_RCC_MSI_FREQ_16MHZ + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetFrequency(void) +{ + return (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL)); +} + + +/** + * @brief Get MSI Calibration value + * @note When MSITRIM is written, MSICAL is updated with the sum of + * MSITRIM and the factory trim value + * @rmtoll MSICFGR MSICAL LL_RCC_MSI_GetCalibration + * @retval A value between 0 and 255 (0xFF) + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSICAL) >> RCC_MSICFGR_MSICAL_Pos); +} + +/** + * @brief Set MSI Calibration trimming + * @note user-programmable trimming value that is added to the MSICAL + * @note Default value is 16, which, when added to the MSICAL value, + * should trim the MSI to 4 MHz +/- 1 % + * @rmtoll MSICFGR MSITRIM LL_RCC_MSI_SetCalibTrimming + * @param Value can be a value between 0 and 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->MSICFGR, RCC_MSICFGR_MSITRIM, Value << RCC_MSICFGR_MSITRIM_Pos); +} + +/** + * @brief Get MSI Calibration trimming + * @rmtoll MSICFGR MSITRIM LL_RCC_MSI_GetCalibTrimming + * @retval A value between 0 and 31 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSITRIM) >> RCC_MSICFGR_MSITRIM_Pos); +} + +/** + * @brief Enable MSI even in stop mode + * @note MSI oscillator is forced ON even in Stop mode + * @rmtoll STOPCR MSISTOPEN LL_RCC_MSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_EnableInStopMode(void) +{ + SET_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN); +} + +/** + * @brief Disable MSI in stop mode + * @rmtoll STOPCR MSISTOPEN LL_RCC_MSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN); +} + +/** + * @brief Check if MSI is enabled in stop mode + * @rmtoll STOPCR MSISTOPEN LL_RCC_MSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN) == RCC_STOPCR_MSISTOPEN) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable the Clock Security System on LSE + * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless + * a clock failure is detected. + * @rmtoll LSECFGR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON); +} + +/** + * @brief Disable the Clock Security System on LSE + * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless + * a clock failure is detected. + * @rmtoll LSECFGR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON); +} + +/** + * @brief Check if LSE failure is detected by Clock Security System + * @rmtoll LSECFGR LSECSSD LL_RCC_LSE_IsFailureDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void) +{ + return ((READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSD) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Re-arm the Clock Security System on LSE + * @note Once a clock failure is detected, the LSE Clock Security System can be re-armed providing that + * LSECSSON is disabled. + * @rmtoll LSECFGR LSECSSRA LL_RCC_LSE_ReArmCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_ReArmCSS(void) +{ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSRA); +} + +/** + * @brief Enable external clock source (LSE bypass) + * @rmtoll LSECFGR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass) + * @rmtoll LSECFGR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); +} + +/** + * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll LSECFGR LSEEXT LL_RCC_LSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); +} + +/** + * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll LSECFGR LSEEXT LL_RCC_LSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll LSECFGR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->LSECFGR, RCC_LSECFGR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll LSECFGR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEDRV)); +} + +/** + * @brief Enable Low Speed External (LSE) crystal + * @rmtoll CSR LSEONS LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_LSEONS); +} + +/** + * @brief Disable Low Speed External (LSE) crystal + * @rmtoll CCR LSEONC LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_LSEONC); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll SR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_LSERDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable the LSE clock glitch filter + * @note This API shall be called only when LSE is disabled. + * @rmtoll LSECFGR LSEGFON LL_RCC_LSE_EnableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void) +{ + SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEGFON); +} + +/** + * @brief Disable the LSE clock glitch filter + * @note This API shall be called only when LSE is disabled. + * @rmtoll LSECFGR LSEGFON LL_RCC_LSE_DisableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void) +{ + CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEGFON); +} + +/** + * @brief Check if LSE clock glitch filter is enabled + * @rmtoll LSECFGR LSEGFON LL_RCC_LSE_IsEnabledGlitchFilter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabledGlitchFilter(void) +{ + return ((READ_BIT(RCC->STOPCR, RCC_LSECFGR_LSEGFON) == RCC_LSECFGR_LSEGFON) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSIONS LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_LSIONS); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CCR LSIONC LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_LSIONC); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll SR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_LSIRDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the CPU clock source + * @rmtoll CFGR1 CPUSW LL_RCC_SetCpuClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_CPU_CLKSOURCE_HSI + * @arg @ref LL_RCC_CPU_CLKSOURCE_MSI + * @arg @ref LL_RCC_CPU_CLKSOURCE_HSE + * @arg @ref LL_RCC_CPU_CLKSOURCE_IC1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCpuClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_CPUSW, Source); +} + +/** + * @brief Get the CPU clock source + * @rmtoll CFGR1 CPUSWS LL_RCC_GetCpuClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_MSI + * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_IC1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCpuClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_CPUSWS)); +} + +/** + * @brief Configure the system clock source (bus clock) + * @rmtoll CFGR1 SYSSW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SYSSW, Source); +} + +/** + * @brief Get the system clock source (bus clock) + * @rmtoll CFGR1 SYSSWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SYSSWS)); +} + +/** + * @brief Configure the system wakeup clock source + * @rmtoll CFGR1 STOPWUCK LL_RCC_SetSysWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_MSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Source); +} + +/** + * @brief Get the system wakeup clock source + * @rmtoll CFGR1 STOPWUCK LL_RCC_GetSysWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_MSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_32 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_32 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE)); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @arg @ref LL_RCC_APB1_DIV_32 + * @arg @ref LL_RCC_APB1_DIV_64 + * @arg @ref LL_RCC_APB1_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @arg @ref LL_RCC_APB1_DIV_32 + * @arg @ref LL_RCC_APB1_DIV_64 + * @arg @ref LL_RCC_APB1_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1)); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @arg @ref LL_RCC_APB2_DIV_32 + * @arg @ref LL_RCC_APB2_DIV_64 + * @arg @ref LL_RCC_APB2_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @arg @ref LL_RCC_APB2_DIV_32 + * @arg @ref LL_RCC_APB2_DIV_64 + * @arg @ref LL_RCC_APB2_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2)); +} + +/** + * @brief Set APB4 prescaler + * @rmtoll CFGR2 PPRE4 LL_RCC_SetAPB4Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @arg @ref LL_RCC_APB4_DIV_32 + * @arg @ref LL_RCC_APB4_DIV_64 + * @arg @ref LL_RCC_APB4_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, Prescaler); +} + +/** + * @brief Get APB4 prescaler + * @rmtoll CFGR2 PPRE4 LL_RCC_GetAPB4Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @arg @ref LL_RCC_APB4_DIV_32 + * @arg @ref LL_RCC_APB4_DIV_64 + * @arg @ref LL_RCC_APB4_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE4)); +} + +/** + * @brief Set APB5 prescaler + * @rmtoll CFGR2 PPRE5 LL_RCC_SetAPB5Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB5_DIV_1 + * @arg @ref LL_RCC_APB5_DIV_2 + * @arg @ref LL_RCC_APB5_DIV_4 + * @arg @ref LL_RCC_APB5_DIV_8 + * @arg @ref LL_RCC_APB5_DIV_16 + * @arg @ref LL_RCC_APB5_DIV_32 + * @arg @ref LL_RCC_APB5_DIV_64 + * @arg @ref LL_RCC_APB5_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB5Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, Prescaler); +} + +/** + * @brief Get APB5 prescaler + * @rmtoll CFGR2 PPRE5 LL_RCC_GetAPB5Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB5_DIV_1 + * @arg @ref LL_RCC_APB5_DIV_2 + * @arg @ref LL_RCC_APB5_DIV_4 + * @arg @ref LL_RCC_APB5_DIV_8 + * @arg @ref LL_RCC_APB5_DIV_16 + * @arg @ref LL_RCC_APB5_DIV_32 + * @arg @ref LL_RCC_APB5_DIV_64 + * @arg @ref LL_RCC_APB5_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB5Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE5)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Enable MCOx output + * @note The clock provided to the MCOx outputs must not exceed the maximum IO speed, + * refer to the product datasheet for information about the supported IO speed. + * @rmtoll MISCENSR MCO1ENS LL_RCC_EnableMCO\n + * MISCENSR MCO2ENS LL_RCC_EnableMCO + * @param MCOx This parameter can be one or a combination of the following values: + * @arg @ref LL_RCC_MCO1 + * @arg @ref LL_RCC_MCO2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableMCO(uint32_t MCOx) +{ + WRITE_REG(RCC->MISCENSR, MCOx); +} + +/** + * @brief Disable MCOx output + * @rmtoll MISCENCR MCO1ENC LL_RCC_DisableMCO\n + * MISCENCR MCO2ENC LL_RCC_DisableMCO + * @param MCOx This parameter can be one or a combination of the following values: + * @arg @ref LL_RCC_MCO1 + * @arg @ref LL_RCC_MCO2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableMCO(uint32_t MCOx) +{ + WRITE_REG(RCC->MISCENCR, MCOx); +} + +/** + * @brief Configure MCOx + * @note The clock provided to the MCOx outputs must not exceed the maximum IO speed, + * refer to the product datasheet for information about the supported IO speed. + * @note The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch). + * @rmtoll CCIPR5 MCO1SEL LL_RCC_ConfigMCO\n + * CCIPR5 MCO1PRE LL_RCC_ConfigMCO\n + * CCIPR5 MCO2SEL LL_RCC_ConfigMCO\n + * CCIPR5 MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_MSI + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_IC5 + * @arg @ref LL_RCC_MCO1SOURCE_IC10 + * @arg @ref LL_RCC_MCO1SOURCE_SYSA + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @arg @ref LL_RCC_MCO2SOURCE_LSE + * @arg @ref LL_RCC_MCO2SOURCE_MSI + * @arg @ref LL_RCC_MCO2SOURCE_HSI + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_IC15 + * @arg @ref LL_RCC_MCO2SOURCE_IC20 + * @arg @ref LL_RCC_MCO2SOURCE_SYSB + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO1_DIV_6 + * @arg @ref LL_RCC_MCO1_DIV_7 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_9 + * @arg @ref LL_RCC_MCO1_DIV_10 + * @arg @ref LL_RCC_MCO1_DIV_11 + * @arg @ref LL_RCC_MCO1_DIV_12 + * @arg @ref LL_RCC_MCO1_DIV_13 + * @arg @ref LL_RCC_MCO1_DIV_14 + * @arg @ref LL_RCC_MCO1_DIV_15 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_6 + * @arg @ref LL_RCC_MCO2_DIV_7 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_9 + * @arg @ref LL_RCC_MCO2_DIV_10 + * @arg @ref LL_RCC_MCO2_DIV_11 + * @arg @ref LL_RCC_MCO2_DIV_12 + * @arg @ref LL_RCC_MCO2_DIV_13 + * @arg @ref LL_RCC_MCO2_DIV_14 + * @arg @ref LL_RCC_MCO2_DIV_15 + * @arg @ref LL_RCC_MCO2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CCIPR5, ((MCOxSource | MCOxPrescaler) >> 16U), \ + (MCOxSource & (RCC_CCIPR5_MCO1SEL | RCC_CCIPR5_MCO2SEL)) | (MCOxPrescaler & (RCC_CCIPR5_MCO1PRE | RCC_CCIPR5_MCO2PRE))); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure periph clock source + * @rmtoll CCIPR4 * LL_RCC_SetClockSource\n + * CCIPR6 * LL_RCC_SetClockSource\n + * CCIPR8 * LL_RCC_SetClockSource\n + * CCIPR9 * LL_RCC_SetClockSource\n + * CCIPR12 * LL_RCC_SetClockSource\n + * CCIPR13 * LL_RCC_SetClockSource\n + * CCIPR14 * LL_RCC_SetClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) +{ + volatile uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource)); + MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); +} + +/** + * @brief Set ADC prescaler + * @rmtoll CCIPR1 ADCPRE LL_RCC_SetADCPrescaler + * @param Prescaler This parameter must be a number between Min_Data = 0 and Max_Data = 255 for prescaler 1 to 256 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCPRE, (Prescaler << RCC_CCIPR1_ADCPRE_Pos)); +} + +/** + * @brief Get ADC prescaler + * @rmtoll CCIPR1 ADCPRE LL_RCC_GetADCPrescaler + * @retval Returned value between Min_Data = 0 and Max_Data = 255 for prescaler 1 to 256 + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCPRE) >> RCC_CCIPR1_ADCPRE_Pos); +} + +/** + * @brief Configure ADCx Kernel clock source + * @rmtoll CCIPR1 ADC12SEL LL_RCC_SetADCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ADC_CLKSOURCE_IC7 + * @arg @ref LL_RCC_ADC_CLKSOURCE_IC8 + * @arg @ref LL_RCC_ADC_CLKSOURCE_MSI + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADC_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_ADC_CLKSOURCE_TIMG + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADC12SEL, ClkSource); +} + +/** + * @brief Configure ADFx Kernel clock source + * @rmtoll CCIPR1 ADF1SEL LL_RCC_SetADFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSI + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_ADF1_CLKSOURCE_TIMG + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADFClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL, ClkSource); +} + +/** + * @brief Configure CLKP Kernel clock source + * @rmtoll CCIPR7 PERSEL LL_RCC_SetCLKPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_MSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC19 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC5 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC10 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC15 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC20 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PERSEL, ClkSource); +} + +/** + * @brief Configure DCMIPP Kernel clock source + * @rmtoll CCIPR1 DCMIPPSEL LL_RCC_SetDCMIPPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_PCLK5 + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_CLKP + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_IC17 + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDCMIPPClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_DCMIPPSEL, ClkSource); +} + +/** + * @brief Configure ETHx Kernel clock source + * @rmtoll CCIPR2 ETH1CLKSEL LL_RCC_SetETHClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETH1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ETH1_CLKSOURCE_IC12 + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1CLKSEL, ClkSource); +} + +/** + * @brief Configure ETHx PTP Kernel clock source + * @rmtoll CCIPR2 ETH1PTPSEL LL_RCC_SetETHPTPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_IC13 + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHPTPClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPSEL, ClkSource); +} + +/** + * @brief Configure ETHx PHY interface + * @rmtoll CCIPR2 ETH1SEL LL_RCC_SetETHPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PHY_IF_MII + * @arg @ref LL_RCC_ETH1PHY_IF_RGMII + * @arg @ref LL_RCC_ETH1PHY_IF_RMII + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHPHYInterface(uint32_t Interface) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1SEL, Interface); +} + +/** + * @brief Set ETH1 PTP Kernel clock divider + * @rmtoll CCIPR2 ETH1PTPDIV LL_RCC_SetETH1PTPDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PTP_DIV_1 + * @arg @ref LL_RCC_ETH1PTP_DIV_2 + * @arg @ref LL_RCC_ETH1PTP_DIV_3 + * @arg @ref LL_RCC_ETH1PTP_DIV_4 + * @arg @ref LL_RCC_ETH1PTP_DIV_5 + * @arg @ref LL_RCC_ETH1PTP_DIV_6 + * @arg @ref LL_RCC_ETH1PTP_DIV_7 + * @arg @ref LL_RCC_ETH1PTP_DIV_8 + * @arg @ref LL_RCC_ETH1PTP_DIV_9 + * @arg @ref LL_RCC_ETH1PTP_DIV_10 + * @arg @ref LL_RCC_ETH1PTP_DIV_11 + * @arg @ref LL_RCC_ETH1PTP_DIV_12 + * @arg @ref LL_RCC_ETH1PTP_DIV_13 + * @arg @ref LL_RCC_ETH1PTP_DIV_14 + * @arg @ref LL_RCC_ETH1PTP_DIV_15 + * @arg @ref LL_RCC_ETH1PTP_DIV_16 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_SetETH1PTPDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPDIV, Divider); +} + +/** + * @brief Get ETH1 PTP Kernel clock divider + * @rmtoll CCIPR2 ETH1PTPDIV LL_RCC_GetETH1PTPDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_ETH1PTP_DIV_1 + * @arg @ref LL_RCC_ETH1PTP_DIV_2 + * @arg @ref LL_RCC_ETH1PTP_DIV_3 + * @arg @ref LL_RCC_ETH1PTP_DIV_4 + * @arg @ref LL_RCC_ETH1PTP_DIV_5 + * @arg @ref LL_RCC_ETH1PTP_DIV_6 + * @arg @ref LL_RCC_ETH1PTP_DIV_7 + * @arg @ref LL_RCC_ETH1PTP_DIV_8 + * @arg @ref LL_RCC_ETH1PTP_DIV_9 + * @arg @ref LL_RCC_ETH1PTP_DIV_10 + * @arg @ref LL_RCC_ETH1PTP_DIV_11 + * @arg @ref LL_RCC_ETH1PTP_DIV_12 + * @arg @ref LL_RCC_ETH1PTP_DIV_13 + * @arg @ref LL_RCC_ETH1PTP_DIV_14 + * @arg @ref LL_RCC_ETH1PTP_DIV_15 + * @arg @ref LL_RCC_ETH1PTP_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetETH1PTPDivider(void) +{ + return (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPDIV)); +} + +/** + * @brief Configure ETHx Reference RX Kernel clock source + * @rmtoll CCIPR2 ETH1REFCLKSEL LL_RCC_SetETHREFRXClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_EXT + * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_INT + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHREFRXClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1REFCLKSEL, ClkSource); +} + +/** + * @brief Configure ETHx Reference TX Kernel clock source + * @rmtoll CCIPR2 ETH1GTXCLKSEL LL_RCC_SetETHREFTXClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_EXT + * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_INT + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHREFTXClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1GTXCLKSEL, ClkSource); +} + +/** + * @brief Configure FDCANx Kernel clock source + * @rmtoll CCIPR3 FDCANSEL LL_RCC_SetFDCANClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_CLKP + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_IC19 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_FDCANSEL, ClkSource); +} + +/** + * @brief Configure FMCx Kernel clock source + * @rmtoll CCIPR3 FMCSEL LL_RCC_SetFMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + * @arg @ref LL_RCC_FMC_CLKSOURCE_IC3 + * @arg @ref LL_RCC_FMC_CLKSOURCE_IC4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_FMCSEL, ClkSource); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR4 I2C1SEL LL_RCC_SetI2CClockSource\n + * @rmtoll CCIPR4 I2C2SEL LL_RCC_SetI2CClockSource\n + * @rmtoll CCIPR4 I2C3SEL LL_RCC_SetI2CClockSource\n + * @rmtoll CCIPR4 I2C4SEL LL_RCC_SetI2CClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure I3Cx clock source + * @rmtoll CCIPR4 I3C1SEL LL_RCC_SetI3CClockSource\n + * @rmtoll CCIPR4 I3C2SEL LL_RCC_SetI3CClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR12 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR12 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR12 LPTIM3SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR12 LPTIM4SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR12 LPTIM5SEL LL_RCC_SetLPTIMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll CCIPR14 LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC14 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR14, RCC_CCIPR14_LPUART1SEL, ClkSource); +} + +/** + * @brief Configure LTDC clock source + * @rmtoll CCIPR4 LTDCSEL LL_RCC_SetLTDCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PCLK5 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LTDC_CLKSOURCE_IC16 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LTDCSEL, ClkSource); +} + +/** + * @brief Configure MDFx Kernel clock source + * @rmtoll CCIPR5 MDF1SEL LL_RCC_SetMDFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSI + * @arg @ref LL_RCC_MDF1_CLKSOURCE_HSI + * @arg @ref LL_RCC_MDF1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_MDF1_CLKSOURCE_TIMG + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetMDFClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL, ClkSource); +} + +/** + * @brief Configure OTGPHY clock source + * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_SetOTGPHYClockSource\n + * CCIPR6 OTGPHY2SEL LL_RCC_SetOTGPHYClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGPHYClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure OTGPHYCKREF clock source + * @rmtoll CCIPR6 OTGPHY1CKREFSEL LL_RCC_SetOTGPHYCKREFClockSource\n + * CCIPR6 OTGPHY2CKREFSEL LL_RCC_SetOTGPHYCKREFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGPHYCKREFClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure PSSI clock source + * @rmtoll CCIPR7 PSSISEL LL_RCC_SetPSSIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PSSI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP + * @arg @ref LL_RCC_PSSI_CLKSOURCE_IC20 + * @arg @ref LL_RCC_PSSI_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetPSSIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PSSISEL, ClkSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll CCIPR7 SAI1SEL LL_RCC_SetSAIClockSource\n + * CCIPR7 SAI2SEL LL_RCC_SetSAIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SDMMCx clock source + * @rmtoll CCIPR8 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n + * CCIPR8 SDMMC2SEL LL_RCC_SetSDMMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SPDIFRX1 Kernel clock source + * @rmtoll CCIPR9 SPDIFRX1SEL LL_RCC_SetSPDIFRXClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR9, RCC_CCIPR9_SPDIFRX1SEL, ClkSource); +} + +/** + * @brief Configure SPIx Kernel clock source + * @rmtoll CCIPR9 SPI1SEL LL_RCC_SetSPIClockSource\n + * CCIPR9 SPI2SEL LL_RCC_SetSPIClockSource\n + * CCIPR9 SPI3SEL LL_RCC_SetSPIClockSource\n + * CCIPR9 SPI4SEL LL_RCC_SetSPIClockSource\n + * CCIPR9 SPI5SEL LL_RCC_SetSPIClockSource\n + * CCIPR9 SPI6SEL LL_RCC_SetSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR13 USART1SEL LL_RCC_SetUSARTClockSource\n + * CCIPR13 USART2SEL LL_RCC_SetUSARTClockSource\n + * CCIPR13 USART3SEL LL_RCC_SetUSARTClockSource\n + * CCIPR13 USART6SEL LL_RCC_SetUSARTClockSource\n + * CCIPR14 USART10SEL LL_RCC_SetUSARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure UARTx clock source + * @rmtoll CCIPR13 UART4SEL LL_RCC_SetUARTClockSource\n + * CCIPR13 UART5SEL LL_RCC_SetUARTClockSource\n + * CCIPR13 UART7SEL LL_RCC_SetUARTClockSource\n + * CCIPR13 UART8SEL LL_RCC_SetUARTClockSource\n + * CCIPR14 UART9SEL LL_RCC_SetUARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure USBx clock source + * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_GetUSBClockSource\n + * CCIPR6 OTGPHY1CKREFSEL LL_RCC_GetUSBClockSource\n + * CCIPR6 OTGPHY2SEL LL_RCC_GetUSBClockSource\n + * CCIPR6 OTGPHY2CKREFSEL LL_RCC_GetUSBClockSource\n + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure XSPIx Kernel clock source + * @rmtoll CCIPR6 XSPI1SEL LL_RCC_SetXSPIClockSource\n + * CCIPR6 XSPI2SEL LL_RCC_SetXSPIClockSource\n + * CCIPR6 XSPI3SEL LL_RCC_SetXSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetXSPIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Get periph clock source + * @rmtoll CCIPR1 * LL_RCC_GetClockSource\n + * CCIPR3 * LL_RCC_GetClockSource\n + * CCIPR4 * LL_RCC_GetClockSource\n + * CCIPR6 * LL_RCC_GetClockSource\n + * CCIPR7 * LL_RCC_GetClockSource\n + * CCIPR8 * LL_RCC_GetClockSource\n + * CCIPR9 * LL_RCC_GetClockSource\n + * CCIPR12 * LL_RCC_GetClockSource\n + * CCIPR13 * LL_RCC_GetClockSource\n + * CCIPR14 * LL_RCC_GetClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @arg @ref LL_RCC_I3C1_CLKSOURCE + * @arg @ref LL_RCC_I3C2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI2_CLKSOURCE + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @arg @ref LL_RCC_SPI4_CLKSOURCE + * @arg @ref LL_RCC_SPI5_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @arg @ref LL_RCC_UART7_CLKSOURCE + * @arg @ref LL_RCC_UART8_CLKSOURCE + * @arg @ref LL_RCC_UART9_CLKSOURCE + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE + * @arg @ref LL_RCC_USART10_CLKSOURCE + * @arg @ref LL_RCC_XSPI1_CLKSOURCE + * @arg @ref LL_RCC_XSPI2_CLKSOURCE + * @arg @ref LL_RCC_XSPI3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4 + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) +{ + const volatile uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph))); + return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT)); +} + +/** + * @brief Get ADC Kernel clock source + * @rmtoll CCIPR1 ADC12SEL LL_RCC_GetADCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ADC_CLKSOURCE_IC7 + * @arg @ref LL_RCC_ADC_CLKSOURCE_IC8 + * @arg @ref LL_RCC_ADC_CLKSOURCE_MSI + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADC_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_ADC_CLKSOURCE_TIMG + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADC12SEL)); +} + +/** + * @brief Get ADFx clock source + * @rmtoll CCIPR1 ADF1SEL LL_RCC_GetADFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSI + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_ADF1_CLKSOURCE_TIMG + */ +__STATIC_INLINE uint32_t LL_RCC_GetADFClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL)); +} + +/** + * @brief Get CLKP Kernel clock source + * @rmtoll CCIPR7 PERSEL LL_RCC_GetCLKPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_MSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC19 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC5 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC10 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC15 + * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC20 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_PERSEL)); +} + +/** + * @brief Get DCMIPP clock source + * @rmtoll CCIPR1 DCMIPPSEL LL_RCC_GetDCMIPPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_PCLK5 + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_CLKP + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_IC17 + * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetDCMIPPClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_DCMIPPSEL)); +} + +/** + * @brief Get ETHx Kernel clock source + * @rmtoll CCIPR2 ETH1CLKSEL LL_RCC_GetETHClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETH1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ETH1_CLKSOURCE_IC12 + * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1CLKSEL)); +} + +/** + * @brief Get ETHx PTP Kernel clock source + * @rmtoll CCIPR2 ETH1PTPSEL LL_RCC_GetETHPTPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_CLKP + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_IC13 + * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHPTPClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPSEL)); +} + +/** + * @brief Get ETHx PHY interface + * @rmtoll CCIPR2 ETH1SEL LL_RCC_GetETHPHYInterface + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PHY_IF + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1PHY_IF_MII + * @arg @ref LL_RCC_ETH1PHY_IF_RGMII + * @arg @ref LL_RCC_ETH1PHY_IF_RMII + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHPHYInterface(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1SEL)); +} + +/** + * @brief Get ETHx Reference RX Kernel clock source + * @rmtoll CCIPR2 ETH1REFCLKSEL LL_RCC_GetETHREFRXClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_EXT + * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_INT + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHREFRXClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1REFCLKSEL)); +} + +/** + * @brief Get ETHx Reference TX Kernel clock source + * @rmtoll CCIPR2 ETH1GTXCLKSEL LL_RCC_GetETHREFTXClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_EXT + * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_INT + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHREFTXClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1GTXCLKSEL)); +} + +/** + * @brief Get FDCAN Kernel clock source + * @rmtoll CCIPR3 FDCANSEL LL_RCC_GetFDCANClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_CLKP + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_IC19 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_FDCANSEL)); +} + +/** + * @brief Get FMC Kernel clock source + * @rmtoll CCIPR3 FMCSEL LL_RCC_GetFMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + * @arg @ref LL_RCC_FMC_CLKSOURCE_IC3 + * @arg @ref LL_RCC_FMC_CLKSOURCE_IC4 + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_FMCSEL)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR4 I2C1SEL LL_RCC_GetI2CClockSource\n + * @rmtoll CCIPR4 I2C2SEL LL_RCC_GetI2CClockSource\n + * @rmtoll CCIPR4 I2C3SEL LL_RCC_GetI2CClockSource\n + * @rmtoll CCIPR4 I2C4SEL LL_RCC_GetI2CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get I3Cx clock source + * @rmtoll CCIPR4 I3C1SEL LL_RCC_GetI3CClockSource\n + * @rmtoll CCIPR4 I3C2SEL LL_RCC_GetI3CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE + * @arg @ref LL_RCC_I3C2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPTIM clock source + * @rmtoll CCIPR12 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR12 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR12 LPTIM3SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR12 LPTIM4SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR12 LPTIM5SEL LL_RCC_GetLPTIMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15 + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPUART clock source + * @rmtoll CCIPR14 LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC14 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR14, RCC_CCIPR14_LPUART1SEL)); +} + +/** + * @brief Get LTDC clock source + * @rmtoll CCIPR4 LTDCSEL LL_RCC_GetLTDCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PCLK5 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LTDC_CLKSOURCE_IC16 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LTDCSEL)); +} + +/** + * @brief Get MDFx clock source + * @rmtoll CCIPR5 MDF1SEL LL_RCC_GetMDFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSI + * @arg @ref LL_RCC_MDF1_CLKSOURCE_HSI + * @arg @ref LL_RCC_MDF1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_MDF1_CLKSOURCE_TIMG + */ +__STATIC_INLINE uint32_t LL_RCC_GetMDFClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL)); +} + +/** + * @brief Get OTGPHY clock source + * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_GetOTGPHYClockSource\n + * CCIPR6 OTGPHY2SEL LL_RCC_GetOTGPHYClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC + */ +__STATIC_INLINE uint32_t LL_RCC_GetOTGPHYClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get OTGPHYCKREF clock source + * @rmtoll CCIPR6 OTGPHY1CKREFSEL LL_RCC_GetOTGPHYCKREFClockSource\n + * CCIPR6 OTGPHY2CKREFSEL LL_RCC_GetOTGPHYCKREFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC + */ +__STATIC_INLINE uint32_t LL_RCC_GetOTGPHYCKREFClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get PSSI clock source + * @rmtoll CCIPR7 PSSISEL LL_RCC_GetPSSIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_PSSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PSSI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP + * @arg @ref LL_RCC_PSSI_CLKSOURCE_IC20 + * @arg @ref LL_RCC_PSSI_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetPSSIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_PSSISEL)); +} + +/** + * @brief Get SAIx clock source + * @rmtoll CCIPR7 SAI1SEL LL_RCC_GetSAIClockSource\n + * CCIPR7 SAI2SEL LL_RCC_GetSAIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SDMMC clock source + * @rmtoll CCIPR8 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n + * CCIPR8 SDMMC2SEL LL_RCC_GetSDMMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SPDIFRX Kernel clock source + * @rmtoll CCIPR9 SPDIFRX1SEL LL_RCC_GetSPDIFRXClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC7 + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR9, RCC_CCIPR9_SPDIFRX1SEL)); +} + +/** + * @brief Get SPIx Kernel clock source + * @rmtoll CCIPR9 SPI1SEL LL_RCC_GetSPIClockSource\n + * CCIPR9 SPI2SEL LL_RCC_GetSPIClockSource\n + * CCIPR9 SPI3SEL LL_RCC_GetSPIClockSource\n + * CCIPR9 SPI4SEL LL_RCC_GetSPIClockSource\n + * CCIPR9 SPI5SEL LL_RCC_GetSPIClockSource\n + * CCIPR9 SPI6SEL LL_RCC_GetSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI2_CLKSOURCE + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @arg @ref LL_RCC_SPI4_CLKSOURCE + * @arg @ref LL_RCC_SPI5_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR13 USART1SEL LL_RCC_GetUSARTClockSource\n + * CCIPR13 USART2SEL LL_RCC_GetUSARTClockSource\n + * CCIPR13 USART3SEL LL_RCC_GetUSARTClockSource\n + * CCIPR13 USART6SEL LL_RCC_GetUSARTClockSource\n + * CCIPR14 USART10SEL LL_RCC_GetUSARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE + * @arg @ref LL_RCC_USART10_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9 + * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14 + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR13 UART4SEL LL_RCC_GetUARTClockSource\n + * CCIPR13 UART5SEL LL_RCC_GetUARTClockSource\n + * CCIPR13 UART7SEL LL_RCC_GetUARTClockSource\n + * CCIPR13 UART8SEL LL_RCC_GetUARTClockSource\n + * CCIPR14 UART9SEL LL_RCC_GetUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @arg @ref LL_RCC_UART7_CLKSOURCE + * @arg @ref LL_RCC_UART8_CLKSOURCE + * @arg @ref LL_RCC_UART9_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9 + * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14 + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get USB clock source + * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_GetUSBClockSource\n + * CCIPR6 OTGPHY1CKREFSEL LL_RCC_GetUSBClockSource\n + * CCIPR6 OTGPHY2SEL LL_RCC_GetUSBClockSource\n + * CCIPR6 OTGPHY2CKREFSEL LL_RCC_GetUSBClockSource\n + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 + * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15 + * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 + * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + + +/** + * @brief Get XSPI Kernel clock source + * @rmtoll CCIPR6 XSPI1SEL LL_RCC_GetXSPIClockSource\n + * CCIPR6 XSPI2SEL LL_RCC_GetXSPIClockSource\n + * CCIPR6 XSPI3SEL LL_RCC_GetXSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE + * @arg @ref LL_RCC_XSPI2_CLKSOURCE + * @arg @ref LL_RCC_XSPI3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3 + * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4 + */ +__STATIC_INLINE uint32_t LL_RCC_GetXSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). + * @rmtoll CCIPR7 RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll CCIPR7 RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll APB4ENSR1 RTCENS LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + WRITE_REG(RCC->APB4ENSR1, RCC_APB4ENSR1_RTCENS); +} + +/** + * @brief Disable RTC + * @rmtoll APB4ENCR1 RTCENC LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + WRITE_REG(RCC->APB4ENCR1, RCC_APB4ENCR1_RTCENC); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll APB4ENR1 RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->APB4ENR1, RCC_APB4ENR1_RTCEN) == (RCC_APB4ENR1_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR VSWRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR VSWRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +} + +/** + * @brief Set HSE Prescaler for RTC Clock + * @rmtoll CCIPR7 RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_DIV_1 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_64 + * @arg @ref LL_RCC_RTC_HSE_DIV_81 + * @arg @ref LL_RCC_RTC_HSE_DIV_100 + * @arg @ref LL_RCC_RTC_HSE_DIV_121 + * @arg @ref LL_RCC_RTC_HSE_DIV_144 + * @arg @ref LL_RCC_RTC_HSE_DIV_169 + * @arg @ref LL_RCC_RTC_HSE_DIV_196 + * @arg @ref LL_RCC_RTC_HSE_DIV_225 + * @arg @ref LL_RCC_RTC_HSE_DIV_256 + * @arg @ref LL_RCC_RTC_HSE_DIV_289 + * @arg @ref LL_RCC_RTC_HSE_DIV_324 + * @arg @ref LL_RCC_RTC_HSE_DIV_361 + * @arg @ref LL_RCC_RTC_HSE_DIV_400 + * @arg @ref LL_RCC_RTC_HSE_DIV_441 + * @arg @ref LL_RCC_RTC_HSE_DIV_484 + * @arg @ref LL_RCC_RTC_HSE_DIV_529 + * @arg @ref LL_RCC_RTC_HSE_DIV_576 + * @arg @ref LL_RCC_RTC_HSE_DIV_625 + * @arg @ref LL_RCC_RTC_HSE_DIV_676 + * @arg @ref LL_RCC_RTC_HSE_DIV_729 + * @arg @ref LL_RCC_RTC_HSE_DIV_784 + * @arg @ref LL_RCC_RTC_HSE_DIV_841 + * @arg @ref LL_RCC_RTC_HSE_DIV_900 + * @arg @ref LL_RCC_RTC_HSE_DIV_961 + * @arg @ref LL_RCC_RTC_HSE_DIV_1024 + * @arg @ref LL_RCC_RTC_HSE_DIV_1089 + * @arg @ref LL_RCC_RTC_HSE_DIV_1156 + * @arg @ref LL_RCC_RTC_HSE_DIV_1225 + * @arg @ref LL_RCC_RTC_HSE_DIV_1296 + * @arg @ref LL_RCC_RTC_HSE_DIV_1369 + * @arg @ref LL_RCC_RTC_HSE_DIV_1444 + * @arg @ref LL_RCC_RTC_HSE_DIV_1521 + * @arg @ref LL_RCC_RTC_HSE_DIV_1600 + * @arg @ref LL_RCC_RTC_HSE_DIV_1681 + * @arg @ref LL_RCC_RTC_HSE_DIV_1764 + * @arg @ref LL_RCC_RTC_HSE_DIV_1849 + * @arg @ref LL_RCC_RTC_HSE_DIV_1936 + * @arg @ref LL_RCC_RTC_HSE_DIV_2025 + * @arg @ref LL_RCC_RTC_HSE_DIV_2116 + * @arg @ref LL_RCC_RTC_HSE_DIV_2209 + * @arg @ref LL_RCC_RTC_HSE_DIV_2304 + * @arg @ref LL_RCC_RTC_HSE_DIV_2401 + * @arg @ref LL_RCC_RTC_HSE_DIV_2500 + * @arg @ref LL_RCC_RTC_HSE_DIV_2601 + * @arg @ref LL_RCC_RTC_HSE_DIV_2704 + * @arg @ref LL_RCC_RTC_HSE_DIV_2809 + * @arg @ref LL_RCC_RTC_HSE_DIV_2916 + * @arg @ref LL_RCC_RTC_HSE_DIV_3025 + * @arg @ref LL_RCC_RTC_HSE_DIV_3136 + * @arg @ref LL_RCC_RTC_HSE_DIV_3249 + * @arg @ref LL_RCC_RTC_HSE_DIV_3364 + * @arg @ref LL_RCC_RTC_HSE_DIV_3481 + * @arg @ref LL_RCC_RTC_HSE_DIV_3600 + * @arg @ref LL_RCC_RTC_HSE_DIV_3721 + * @arg @ref LL_RCC_RTC_HSE_DIV_3844 + * @arg @ref LL_RCC_RTC_HSE_DIV_3969 + * @arg @ref LL_RCC_RTC_HSE_DIV_4096 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescaler for RTC Clock + * @rmtoll CCIPR7 RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_DIV_1 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_64 + * @arg @ref LL_RCC_RTC_HSE_DIV_81 + * @arg @ref LL_RCC_RTC_HSE_DIV_100 + * @arg @ref LL_RCC_RTC_HSE_DIV_121 + * @arg @ref LL_RCC_RTC_HSE_DIV_144 + * @arg @ref LL_RCC_RTC_HSE_DIV_169 + * @arg @ref LL_RCC_RTC_HSE_DIV_196 + * @arg @ref LL_RCC_RTC_HSE_DIV_225 + * @arg @ref LL_RCC_RTC_HSE_DIV_256 + * @arg @ref LL_RCC_RTC_HSE_DIV_289 + * @arg @ref LL_RCC_RTC_HSE_DIV_324 + * @arg @ref LL_RCC_RTC_HSE_DIV_361 + * @arg @ref LL_RCC_RTC_HSE_DIV_400 + * @arg @ref LL_RCC_RTC_HSE_DIV_441 + * @arg @ref LL_RCC_RTC_HSE_DIV_484 + * @arg @ref LL_RCC_RTC_HSE_DIV_529 + * @arg @ref LL_RCC_RTC_HSE_DIV_576 + * @arg @ref LL_RCC_RTC_HSE_DIV_625 + * @arg @ref LL_RCC_RTC_HSE_DIV_676 + * @arg @ref LL_RCC_RTC_HSE_DIV_729 + * @arg @ref LL_RCC_RTC_HSE_DIV_784 + * @arg @ref LL_RCC_RTC_HSE_DIV_841 + * @arg @ref LL_RCC_RTC_HSE_DIV_900 + * @arg @ref LL_RCC_RTC_HSE_DIV_961 + * @arg @ref LL_RCC_RTC_HSE_DIV_1024 + * @arg @ref LL_RCC_RTC_HSE_DIV_1089 + * @arg @ref LL_RCC_RTC_HSE_DIV_1156 + * @arg @ref LL_RCC_RTC_HSE_DIV_1225 + * @arg @ref LL_RCC_RTC_HSE_DIV_1296 + * @arg @ref LL_RCC_RTC_HSE_DIV_1369 + * @arg @ref LL_RCC_RTC_HSE_DIV_1444 + * @arg @ref LL_RCC_RTC_HSE_DIV_1521 + * @arg @ref LL_RCC_RTC_HSE_DIV_1600 + * @arg @ref LL_RCC_RTC_HSE_DIV_1681 + * @arg @ref LL_RCC_RTC_HSE_DIV_1764 + * @arg @ref LL_RCC_RTC_HSE_DIV_1849 + * @arg @ref LL_RCC_RTC_HSE_DIV_1936 + * @arg @ref LL_RCC_RTC_HSE_DIV_2025 + * @arg @ref LL_RCC_RTC_HSE_DIV_2116 + * @arg @ref LL_RCC_RTC_HSE_DIV_2209 + * @arg @ref LL_RCC_RTC_HSE_DIV_2304 + * @arg @ref LL_RCC_RTC_HSE_DIV_2401 + * @arg @ref LL_RCC_RTC_HSE_DIV_2500 + * @arg @ref LL_RCC_RTC_HSE_DIV_2601 + * @arg @ref LL_RCC_RTC_HSE_DIV_2704 + * @arg @ref LL_RCC_RTC_HSE_DIV_2809 + * @arg @ref LL_RCC_RTC_HSE_DIV_2916 + * @arg @ref LL_RCC_RTC_HSE_DIV_3025 + * @arg @ref LL_RCC_RTC_HSE_DIV_3136 + * @arg @ref LL_RCC_RTC_HSE_DIV_3249 + * @arg @ref LL_RCC_RTC_HSE_DIV_3364 + * @arg @ref LL_RCC_RTC_HSE_DIV_3481 + * @arg @ref LL_RCC_RTC_HSE_DIV_3600 + * @arg @ref LL_RCC_RTC_HSE_DIV_3721 + * @arg @ref LL_RCC_RTC_HSE_DIV_3844 + * @arg @ref LL_RCC_RTC_HSE_DIV_3969 + * @arg @ref LL_RCC_RTC_HSE_DIV_4096 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll CFGR2 TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_1 + * @arg @ref LL_RCC_TIM_PRESCALER_2 + * @arg @ref LL_RCC_TIM_PRESCALER_4 + * @arg @ref LL_RCC_TIM_PRESCALER_8 + * @retval None + * @note The clock ratio tim_ker_ck/tim_pclk must be an integer between 1 and 16 + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_TIMPRE, Prescaler << RCC_CFGR2_TIMPRE_Pos); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll CFGR2 TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_1 + * @arg @ref LL_RCC_TIM_PRESCALER_2 + * @arg @ref LL_RCC_TIM_PRESCALER_4 + * @arg @ref LL_RCC_TIM_PRESCALER_8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_TIMPRE) >> RCC_CFGR2_TIMPRE_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLL1SEL can be written only when All PLLs are disabled. + * @rmtoll PLL1CFGR1 PLL1SEL LL_RCC_PLL1_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1SEL, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLL1CFGR1 PLL1SEL LL_RCC_PLL1_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1SEL)); +} + +/** + * @brief Enable PLL1 + * @rmtoll CSR PLL1ONS LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS); +} + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CCR PLL1ONC LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC); +} + +/** + * @brief Check if PLL1 Ready + * @rmtoll SR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_PLL1RDY) == (RCC_SR_PLL1RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1 bypass (PLL1 output is driven by the PLL1 reference clock) + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR1 PLL1BYP LL_RCC_PLL1_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableBypass(void) +{ + SET_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP); +} + +/** + * @brief Disable PLL1 bypass (PLL1 output is driven by the VCO) + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR1 PLL1BYP LL_RCC_PLL1_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableBypass(void) +{ + CLEAR_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP); +} + +/** + * @brief Check if PLL1 bypass is enabled + * @rmtoll PLL1CFGR1 PLL1BYP LL_RCC_PLL1_IsEnabledBypass + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledBypass(void) +{ + return ((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP) == RCC_PLL1CFGR1_PLL1BYP) ? 1UL : 0UL); +} + +/** + * @brief Assert PLL1 modulation spread-spectrum reset + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1MODSSRST LL_RCC_PLL1_AssertModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_AssertModulationSpreadSpectrumReset(void) +{ + SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST); +} + +/** + * @brief Release PLL1 modulation spread-spectrum reset + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1MODSSRST LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset(void) +{ + CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST); +} + +/** + * @brief Enable PLL1 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1DACEN LL_RCC_PLL1_EnableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableDAC(void) +{ + SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN); +} + +/** + * @brief Disable PLL1 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1DACEN LL_RCC_PLL1_DisableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableDAC(void) +{ + CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN); +} + +/** + * @brief Check if PLL1 noise canceling DAC in fractional mode is enabled + * @rmtoll PLL1CFGR3 PLL1DACEN LL_RCC_PLL1_IsEnabledDAC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDAC(void) +{ + return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN) == RCC_PLL1CFGR3_PLL1DACEN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1 modulation spread-spectrum with fractional divide inactive + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1MODSSDIS LL_RCC_PLL1_EnableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS); +} + +/** + * @brief Disable PLL1 modulation spread-spectrum but active fractional divide + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1MODSSDIS LL_RCC_PLL1_DisableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS); +} + +/** + * @brief Check if PLL1 modulation spread-spectrum and inactive fractional divide is enabled + * @rmtoll PLL1CFGR3 PLL1MODSSDIS LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS) == 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1MODDSEN LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN); +} + +/** + * @brief Disable PLL1 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1MODDSEN LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN); +} + +/** + * @brief Check if PLL1 fractional divide and modulation spread-spectrum is enabled + * @rmtoll PLL1CFGR3 PLL1MODDSEN LL_RCC_PLL1_IsEnabledFractionalModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledFractionalModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN) == RCC_PLL1CFGR3_PLL1MODDSEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL1 DIVN Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR1 PLL1DIVN LL_RCC_PLL1_SetN + * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN, N << RCC_PLL1CFGR1_PLL1DIVN_Pos); +} + +/** + * @brief Get PLL1 DIVN Coefficient + * @rmtoll PLL1CFGR1 PLL1DIVN LL_RCC_PLL1_GetN + * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos)); +} + +/** + * @brief Set PLL1 DIVM Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR1 PLL1DIVM LL_RCC_PLL1_SetM + * @param M parameter can be a value between 1 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM, M << RCC_PLL1CFGR1_PLL1DIVM_Pos); +} + +/** + * @brief Get PLL1 DIVM Coefficient + * @rmtoll PLL1CFGR1 PLL1DIVM LL_RCC_PLL1_GetM + * @retval A value between 1 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos); +} + +/** + * @brief Set PLL1 PDIV1 Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1PDIV1 LL_RCC_PLL1_SetP1 + * @param P1 parameter can be a value between 1 and 7 when PLL1 is enabled, 0 when disabled + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP1(uint32_t P1) +{ + MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV1, P1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos); +} + +/** + * @brief Get PLL1 PDIV2 Coefficient + * @rmtoll PLL1CFGR3 PLL1PDIV1 LL_RCC_PLL1_GetP1 + * @retval A value between 0 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP1(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos); +} + +/** + * @brief Set PLL1 PDIV2 Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1PDIV2 LL_RCC_PLL1_SetP2 + * @param P2 parameter can be a value between 1 and 7 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP2(uint32_t P2) +{ + MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2, P2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos); +} + +/** + * @brief Get PLL1 PDIV2 Coefficient + * @rmtoll PLL1CFGR3 PLL1PDIV2 LL_RCC_PLL1_GetP2 + * @retval A value between 1 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP2(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos); +} + +/** + * @brief Enable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1PDIVEN LL_RCC_PLL1P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Enable(void) +{ + SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN); +} + +/** + * @brief Disable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR3 PLL1PDIVEN LL_RCC_PLL1P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Disable(void) +{ + CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN); +} + +/** + * @brief Check if PLL1 P is enabled + * @rmtoll PLL1CFGR3 PLL1PDIVEN LL_RCC_PLL1P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN) == RCC_PLL1CFGR3_PLL1PDIVEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL1 FRACN Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR2 PLL1DIVNFRAC LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC, FRACN << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos); +} + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1CFGR2 PLL1DIVNFRAC LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos); +} + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLL2SEL can be written only when All PLLs are disabled. + * @rmtoll PLL2CFGR1 PLL2SEL LL_RCC_PLL2_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLL2CFGR1 PLL2SEL LL_RCC_PLL2_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL)); +} + +/** + * @brief Enable PLL2 + * @rmtoll CSR PLL2ONS LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_PLL2ONS); +} + +/** + * @brief Disable PLL2 + * @note Cannot be disabled if the PLL2 clock is used as the system clock + * @rmtoll CCR PLL2ONC LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_PLL2ONC); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll SR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_PLL2RDY) == (RCC_SR_PLL2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 bypass (PLL2 output is driven by the PLL2 reference clock) + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR1 PLL2BYP LL_RCC_PLL2_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableBypass(void) +{ + SET_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP); +} + +/** + * @brief Disable PLL2 bypass (PLL2 output is driven by the VCO) + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR1 PLL2BYP LL_RCC_PLL2_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableBypass(void) +{ + CLEAR_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP); +} + +/** + * @brief Check if PLL2 bypass is enabled + * @rmtoll PLL2CFGR1 PLL2BYP LL_RCC_PLL2_IsEnabledBypass + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledBypass(void) +{ + return ((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP) == RCC_PLL2CFGR1_PLL2BYP) ? 1UL : 0UL); +} + +/** + * @brief Assert PLL2 modulation spread-spectrum reset + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2MODSSRST LL_RCC_PLL2_AssertModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_AssertModulationSpreadSpectrumReset(void) +{ + SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST); +} + +/** + * @brief Release PLL2 modulation spread-spectrum reset + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2MODSSRST LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset(void) +{ + CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST); +} + +/** + * @brief Enable PLL2 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2DACEN LL_RCC_PLL2_EnableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableDAC(void) +{ + SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN); +} + +/** + * @brief Disable PLL2 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2DACEN LL_RCC_PLL2_DisableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableDAC(void) +{ + CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN); +} + +/** + * @brief Check if PLL2 noise canceling DAC in fractional mode is enabled + * @rmtoll PLL2CFGR3 PLL2DACEN LL_RCC_PLL2_IsEnabledDAC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDAC(void) +{ + return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN) == RCC_PLL2CFGR3_PLL2DACEN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 modulation spread-spectrum with fractional divide inactive + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2MODSSDIS LL_RCC_PLL2_EnableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS); +} + +/** + * @brief Disable PLL2 modulation spread-spectrum but active fractional divide + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2MODSSDIS LL_RCC_PLL2_DisableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS); +} + +/** + * @brief Check if PLL2 modulation spread-spectrum and inactive fractional divide is enabled + * @rmtoll PLL2CFGR3 PLL2MODSSDIS LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS) == 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2MODDSEN LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN); +} + +/** + * @brief Disable PLL2 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2MODDSEN LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN); +} + +/** + * @brief Check if PLL2 fractional divide and modulation spread-spectrum is enabled + * @rmtoll PLL2CFGR3 PLL2MODDSEN LL_RCC_PLL2_IsEnabledFractionalModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledFractionalModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN) == RCC_PLL2CFGR3_PLL2MODDSEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL2 DIVN Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR1 PLL2DIVN LL_RCC_PLL2_SetN + * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN, N << RCC_PLL2CFGR1_PLL2DIVN_Pos); +} + +/** + * @brief Get PLL2 DIVN Coefficient + * @rmtoll PLL2CFGR1 PLL2DIVN LL_RCC_PLL2_GetN + * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos)); +} + +/** + * @brief Set PLL2 DIVM Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR1 PLL2DIVM LL_RCC_PLL2_SetM + * @param M parameter can be a value between 1 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM, M << RCC_PLL2CFGR1_PLL2DIVM_Pos); +} + +/** + * @brief Get PLL2 DIVM Coefficient + * @rmtoll PLL2CFGR1 PLL2DIVM LL_RCC_PLL2_GetM + * @retval A value between 1 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos); +} + +/** + * @brief Set PLL2 PDIV1 Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2PDIV1 LL_RCC_PLL2_SetP1 + * @param P1 parameter can be a value between 1 and 7 when PLL2 is enabled, 0 when disabled + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP1(uint32_t P1) +{ + MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1, P1 << RCC_PLL2CFGR3_PLL2PDIV1_Pos); +} + +/** + * @brief Get PLL2 PDIV2 Coefficient + * @rmtoll PLL2CFGR3 PLL2PDIV1 LL_RCC_PLL2_GetP1 + * @retval A value between 0 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP1(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos); +} + +/** + * @brief Set PLL2 PDIV2 Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2PDIV2 LL_RCC_PLL2_SetP2 + * @param P2 parameter can be a value between 1 and 7 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP2(uint32_t P2) +{ + MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV2, P2 << RCC_PLL2CFGR3_PLL2PDIV2_Pos); +} + +/** + * @brief Get PLL2 PDIV2 Coefficient + * @rmtoll PLL2CFGR3 PLL2PDIV2 LL_RCC_PLL2_GetP2 + * @retval A value between 1 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP2(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos); +} + +/** + * @brief Enable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2PDIVEN LL_RCC_PLL2P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Enable(void) +{ + SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN); +} + +/** + * @brief Disable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR3 PLL2PDIVEN LL_RCC_PLL2P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Disable(void) +{ + CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN); +} + +/** + * @brief Check if PLL2 P is enabled + * @rmtoll PLL2CFGR3 PLL2PDIVEN LL_RCC_PLL2P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN) == RCC_PLL2CFGR3_PLL2PDIVEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL2 FRACN Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR2 PLL2DIVNFRAC LL_RCC_PLL2_SetFRACN + * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC, FRACN << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos); +} + +/** + * @brief Get PLL2 FRACN Coefficient + * @rmtoll PLL2CFGR2 PLL2DIVNFRAC LL_RCC_PLL2_GetFRACN + * @retval A value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos); +} + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLL3SEL can be written only when All PLLs are disabled. + * @rmtoll PLL3CFGR1 PLL3SEL LL_RCC_PLL3_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3SEL, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLL3CFGR1 PLL3SEL LL_RCC_PLL3_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3SEL)); +} + +/** + * @brief Enable PLL3 + * @rmtoll CSR PLL3ONS LL_RCC_PLL3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_PLL3ONS); +} + +/** + * @brief Disable PLL3 + * @note Cannot be disabled if the PLL3 clock is used as the system clock + * @rmtoll CCR PLL3ONC LL_RCC_PLL3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_PLL3ONC); +} + +/** + * @brief Check if PLL3 Ready + * @rmtoll SR PLL3RDY LL_RCC_PLL3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_PLL3RDY) == (RCC_SR_PLL3RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3 bypass (PLL3 output is driven by the PLL3 reference clock) + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR1 PLL3BYP LL_RCC_PLL3_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableBypass(void) +{ + SET_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP); +} + +/** + * @brief Disable PLL3 bypass (PLL3 output is driven by the VCO) + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR1 PLL3BYP LL_RCC_PLL3_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableBypass(void) +{ + CLEAR_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP); +} + +/** + * @brief Check if PLL3 bypass is enabled + * @rmtoll PLL3CFGR1 PLL3BYP LL_RCC_PLL3_IsEnabledBypass + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledBypass(void) +{ + return ((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP) == RCC_PLL3CFGR1_PLL3BYP) ? 1UL : 0UL); +} + +/** + * @brief Assert PLL3 modulation spread-spectrum reset + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3MODSSRST LL_RCC_PLL3_AssertModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_AssertModulationSpreadSpectrumReset(void) +{ + SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSRST); +} + +/** + * @brief Release PLL3 modulation spread-spectrum reset + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3MODSSRST LL_RCC_PLL3_ReleaseModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_ReleaseModulationSpreadSpectrumReset(void) +{ + CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSRST); +} + +/** + * @brief Enable PLL3 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3DACEN LL_RCC_PLL3_EnableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableDAC(void) +{ + SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN); +} + +/** + * @brief Disable PLL3 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3DACEN LL_RCC_PLL3_DisableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableDAC(void) +{ + CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN); +} + +/** + * @brief Check if PLL3 noise canceling DAC in fractional mode is enabled + * @rmtoll PLL3CFGR3 PLL3DACEN LL_RCC_PLL3_IsEnabledDAC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDAC(void) +{ + return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN) == RCC_PLL3CFGR3_PLL3DACEN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3 modulation spread-spectrum with fractional divide inactive + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3MODSSDIS LL_RCC_PLL3_EnableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS); +} + +/** + * @brief Disable PLL3 modulation spread-spectrum but active fractional divide + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3MODSSDIS LL_RCC_PLL3_DisableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS); +} + +/** + * @brief Check if PLL3 modulation spread-spectrum and inactive fractional divide is enabled + * @rmtoll PLL3CFGR3 PLL3MODSSDIS LL_RCC_PLL3_IsEnabledModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS) == 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3MODDSEN LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN); +} + +/** + * @brief Disable PLL3 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3MODDSEN LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN); +} + +/** + * @brief Check if PLL3 fractional divide and modulation spread-spectrum is enabled + * @rmtoll PLL3CFGR3 PLL3MODDSEN LL_RCC_PLL3_IsEnabledFractionalModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledFractionalModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN) == RCC_PLL3CFGR3_PLL3MODDSEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL3 DIVN Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR1 PLL3DIVN LL_RCC_PLL3_SetN + * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN, N << RCC_PLL3CFGR1_PLL3DIVN_Pos); +} + +/** + * @brief Get PLL3 DIVN Coefficient + * @rmtoll PLL3CFGR1 PLL3DIVN LL_RCC_PLL3_GetN + * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos)); +} + +/** + * @brief Set PLL3 DIVM Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR1 PLL3DIVM LL_RCC_PLL3_SetM + * @param M parameter can be a value between 1 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM, M << RCC_PLL3CFGR1_PLL3DIVM_Pos); +} + +/** + * @brief Get PLL3 DIVM Coefficient + * @rmtoll PLL3CFGR1 PLL3DIVM LL_RCC_PLL3_GetM + * @retval A value between 1 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos); +} + +/** + * @brief Set PLL3 PDIV1 Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3PDIV1 LL_RCC_PLL3_SetP1 + * @param P1 parameter can be a value between 1 and 7 when PLL3 is enabled, 0 when disabled + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP1(uint32_t P1) +{ + MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1, P1 << RCC_PLL3CFGR3_PLL3PDIV1_Pos); +} + +/** + * @brief Get PLL3 PDIV2 Coefficient + * @rmtoll PLL3CFGR3 PLL3PDIV1 LL_RCC_PLL3_GetP1 + * @retval A value between 1 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP1(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos); +} + +/** + * @brief Set PLL3 PDIV2 Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3PDIV2 LL_RCC_PLL3_SetP2 + * @param P2 parameter can be a value between 0 and 7 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP2(uint32_t P2) +{ + MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2, P2 << RCC_PLL3CFGR3_PLL3PDIV2_Pos); +} + +/** + * @brief Get PLL3 PDIV2 Coefficient + * @rmtoll PLL3CFGR3 PLL3PDIV2 LL_RCC_PLL3_GetP2 + * @retval A value between 1 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP2(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos); +} + +/** + * @brief Enable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3PDIVEN LL_RCC_PLL3P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Enable(void) +{ + SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN); +} + +/** + * @brief Disable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR3 PLL3PDIVEN LL_RCC_PLL3P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Disable(void) +{ + CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN); +} + +/** + * @brief Check if PLL3 P is enabled + * @rmtoll PLL3CFGR3 PLL3PDIVEN LL_RCC_PLL3P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN) == RCC_PLL3CFGR3_PLL3PDIVEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL3 FRACN Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR2 PLL3DIVNFRAC LL_RCC_PLL3_SetFRACN + * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC, FRACN << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos); +} + +/** + * @brief Get PLL3 FRACN Coefficient + * @rmtoll PLL3CFGR2 PLL3DIVNFRAC LL_RCC_PLL3_GetFRACN + * @retval A value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos); +} + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLL4SEL can be written only when All PLLs are disabled. + * @rmtoll PLL4CFGR1 PLL4SEL LL_RCC_PLL4_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLL4CFGR1 PLL4SEL LL_RCC_PLL4_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL)); +} + +/** + * @brief Enable PLL4 + * @rmtoll CSR PLL4ONS LL_RCC_PLL4_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_Enable(void) +{ + WRITE_REG(RCC->CSR, RCC_CSR_PLL4ONS); +} + +/** + * @brief Disable PLL4 + * @note Cannot be disabled if the PLL4 clock is used as the system clock + * @rmtoll CCR PLL4ONC LL_RCC_PLL4_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_Disable(void) +{ + WRITE_REG(RCC->CCR, RCC_CCR_PLL4ONC); +} + +/** + * @brief Check if PLL4 Ready + * @rmtoll SR PLL4RDY LL_RCC_PLL4_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_IsReady(void) +{ + return ((READ_BIT(RCC->SR, RCC_SR_PLL4RDY) == (RCC_SR_PLL4RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL4 bypass (PLL4 output is driven by the PLL4 reference clock) + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR1 PLL4BYP LL_RCC_PLL4_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_EnableBypass(void) +{ + SET_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP); +} + +/** + * @brief Disable PLL4 bypass (PLL4 output is driven by the VCO) + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR1 PLL4BYP LL_RCC_PLL4_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_DisableBypass(void) +{ + CLEAR_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP); +} + +/** + * @brief Check if PLL4 bypass is enabled + * @rmtoll PLL4CFGR1 PLL4BYP LL_RCC_PLL4_IsEnabledBypass + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledBypass(void) +{ + return ((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP) == RCC_PLL4CFGR1_PLL4BYP) ? 1UL : 0UL); +} + +/** + * @brief Assert PLL4 modulation spread-spectrum reset + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4MODSSRST LL_RCC_PLL4_AssertModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_AssertModulationSpreadSpectrumReset(void) +{ + SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST); +} + +/** + * @brief Release PLL4 modulation spread-spectrum reset + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4MODSSRST LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset(void) +{ + CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST); +} + +/** + * @brief Enable PLL4 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4DACEN LL_RCC_PLL4_EnableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_EnableDAC(void) +{ + SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN); +} + +/** + * @brief Disable PLL4 noise canceling DAC in fractional mode + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4DACEN LL_RCC_PLL4_DisableDAC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_DisableDAC(void) +{ + CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN); +} + +/** + * @brief Check if PLL4 noise canceling DAC in fractional mode is enabled + * @rmtoll PLL4CFGR3 PLL4DACEN LL_RCC_PLL4_IsEnabledDAC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledDAC(void) +{ + return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN) == RCC_PLL4CFGR3_PLL4DACEN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL4 modulation spread-spectrum with fractional divide inactive + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4MODSSDIS LL_RCC_PLL4_EnableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_EnableModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS); +} + +/** + * @brief Disable PLL4 modulation spread-spectrum but active fractional divide + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4MODSSDIS LL_RCC_PLL4_DisableModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_DisableModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS); +} + +/** + * @brief Check if PLL4 modulation spread-spectrum and inactive fractional divide is enabled + * @rmtoll PLL4CFGR3 PLL4MODSSDIS LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS) == 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL4 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4MODDSEN LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum(void) +{ + SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN); +} + +/** + * @brief Disable PLL4 fractional divide and modulation spread-spectrum + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4MODDSEN LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN); +} + +/** + * @brief Check if PLL4 fractional divide and modulation spread-spectrum is enabled + * @rmtoll PLL4CFGR3 PLL4MODDSEN LL_RCC_PLL4_IsEnabledFractionalModulationSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledFractionalModulationSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN) == RCC_PLL4CFGR3_PLL4MODDSEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL4 DIVN Coefficient + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR1 PLL4DIVN LL_RCC_PLL4_SetN + * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE void LL_RCC_PLL4_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN, N << RCC_PLL4CFGR1_PLL4DIVN_Pos); +} + +/** + * @brief Get PLL4 DIVN Coefficient + * @rmtoll PLL4CFGR1 PLL4DIVN LL_RCC_PLL4_GetN + * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4). + * In fractional mode, a value between 20 (0x14) and 500 (0x1F4). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos)); +} + +/** + * @brief Set PLL4 DIVM Coefficient + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR1 PLL4DIVM LL_RCC_PLL4_SetM + * @param M parameter can be a value between 1 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL4_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM, M << RCC_PLL4CFGR1_PLL4DIVM_Pos); +} + +/** + * @brief Get PLL4 DIVM Coefficient + * @rmtoll PLL4CFGR1 PLL4DIVM LL_RCC_PLL4_GetM + * @retval A value between 1 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos); +} + +/** + * @brief Set PLL4 PDIV1 Coefficient + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4PDIV1 LL_RCC_PLL4_SetP1 + * @param P1 parameter can be a value between 1 and 7 when PLL4 is enabled, 0 when disabled + */ +__STATIC_INLINE void LL_RCC_PLL4_SetP1(uint32_t P1) +{ + MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1, P1 << RCC_PLL4CFGR3_PLL4PDIV1_Pos); +} + +/** + * @brief Get PLL4 PDIV2 Coefficient + * @rmtoll PLL4CFGR3 PLL4PDIV1 LL_RCC_PLL4_GetP1 + * @retval A value between 0 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_GetP1(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos); +} + +/** + * @brief Set PLL4 PDIV2 Coefficient + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4PDIV2 LL_RCC_PLL4_SetP2 + * @param P2 parameter can be a value between 1 and 7 + */ +__STATIC_INLINE void LL_RCC_PLL4_SetP2(uint32_t P2) +{ + MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2, P2 << RCC_PLL4CFGR3_PLL4PDIV2_Pos); +} + +/** + * @brief Get PLL4 PDIV2 Coefficient + * @rmtoll PLL4CFGR3 PLL4PDIV2 LL_RCC_PLL4_GetP2 + * @retval A value between 1 and 7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_GetP2(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos); +} + +/** + * @brief Enable PLL4P + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4PDIVEN LL_RCC_PLL4P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4P_Enable(void) +{ + SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN); +} + +/** + * @brief Disable PLL4P + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR3 PLL4PDIVEN LL_RCC_PLL4P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL4P_Disable(void) +{ + CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN); +} + +/** + * @brief Check if PLL4 P is enabled + * @rmtoll PLL4CFGR3 PLL4PDIVEN LL_RCC_PLL4P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN) == RCC_PLL4CFGR3_PLL4PDIVEN) ? 1UL : 0UL); +} + +/** + * @brief Set PLL4 FRACN Coefficient + * @note This API shall be called only when PLL4 is disabled. + * @rmtoll PLL4CFGR2 PLL4DIVNFRAC LL_RCC_PLL4_SetFRACN + * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE void LL_RCC_PLL4_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC, FRACN << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos); +} + +/** + * @brief Get PLL4 FRACN Coefficient + * @rmtoll PLL4CFGR2 PLL4DIVNFRAC LL_RCC_PLL4_GetFRACN + * @retval A value between 0 and 2^24 (0xFFFFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL4_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos); +} + +/** + * @brief Enable IC1 + * @rmtoll DIVENSR IC1ENS LL_RCC_IC1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC1_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC1ENS); +} + +/** + * @brief Disable IC1 + * @rmtoll DIVENCR IC1ENC LL_RCC_IC1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC1_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC1ENC); +} + +/** + * @brief Check if IC1 is enabled + * @rmtoll DIVENR IC1EN LL_RCC_IC1_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC1_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC1EN) == RCC_DIVENR_IC1EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC1 clock source. + * @rmtoll IC1CFGR IC1SEL LL_RCC_IC1_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC1_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL, Source); +} + +/** + * @brief Get the PLL source used as IC1 clock source. + * @rmtoll IC1CFGR IC1SEL LL_RCC_IC1_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC1_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC1CFGR IC1INT LL_RCC_IC1_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC1_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT, (Divider - 1UL) << RCC_IC1CFGR_IC1INT_Pos); +} + +/** + * @brief Get IC1 divider + * @rmtoll IC1CFGR IC1INT LL_RCC_IC1_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC1_GetDivider(void) +{ + return ((READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL); +} + +/** + * @brief Enable IC2 + * @rmtoll DIVENSR IC2ENS LL_RCC_IC2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC2_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC2ENS); +} + +/** + * @brief Disable IC2 + * @rmtoll DIVENCR IC2ENC LL_RCC_IC2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC2_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC2ENC); +} + +/** + * @brief Check if IC2 is enabled + * @rmtoll DIVENR IC2EN LL_RCC_IC2_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC2_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC2EN) == RCC_DIVENR_IC2EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC2 clock source. + * @rmtoll IC2CFGR IC2SEL LL_RCC_IC2_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC2_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC2CFGR, RCC_IC2CFGR_IC2SEL, Source); +} + +/** + * @brief Get the PLL source used as IC2 clock source. + * @rmtoll IC2CFGR IC2SEL LL_RCC_IC2_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC2_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC2CFGR, RCC_IC2CFGR_IC2SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC2CFGR IC2INT LL_RCC_IC2_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC2_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC2CFGR, RCC_IC2CFGR_IC2INT, (Divider - 1UL) << RCC_IC2CFGR_IC2INT_Pos); +} + +/** + * @brief Get IC2 divider + * @rmtoll IC2CFGR IC2INT LL_RCC_IC2_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC2_GetDivider(void) +{ + return ((READ_BIT(RCC->IC2CFGR, RCC_IC2CFGR_IC2INT) >> RCC_IC2CFGR_IC2INT_Pos) + 1UL); +} + +/** + * @brief Enable IC3 + * @rmtoll DIVENSR IC3ENS LL_RCC_IC3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC3_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC3ENS); +} + +/** + * @brief Disable IC3 + * @rmtoll DIVENCR IC3ENC LL_RCC_IC3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC3_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC3ENC); +} + +/** + * @brief Check if IC3 is enabled + * @rmtoll DIVENR IC3EN LL_RCC_IC3_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC3_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC3EN) == RCC_DIVENR_IC3EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC3 clock source. + * @rmtoll IC3CFGR IC3SEL LL_RCC_IC3_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC3_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL, Source); +} + +/** + * @brief Get the PLL source used as IC3 clock source. + * @rmtoll IC3CFGR IC3SEL LL_RCC_IC3_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC3_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC3CFGR IC3INT LL_RCC_IC3_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC3_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3INT, (Divider - 1UL) << RCC_IC3CFGR_IC3INT_Pos); +} + +/** + * @brief Get IC3 divider + * @rmtoll IC3CFGR IC3INT LL_RCC_IC3_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC3_GetDivider(void) +{ + return ((READ_BIT(RCC->IC3CFGR, RCC_IC3CFGR_IC3INT) >> RCC_IC3CFGR_IC3INT_Pos) + 1UL); +} + +/** + * @brief Enable IC4 + * @rmtoll DIVENSR IC4ENS LL_RCC_IC4_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC4_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC4ENS); +} + +/** + * @brief Disable IC4 + * @rmtoll DIVENCR IC4ENC LL_RCC_IC4_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC4_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC4ENC); +} + +/** + * @brief Check if IC4 is enabled + * @rmtoll DIVENR IC4EN LL_RCC_IC4_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC4_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC4EN) == RCC_DIVENR_IC4EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC4 clock source. + * @rmtoll IC4CFGR IC4SEL LL_RCC_IC4_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC4_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL, Source); +} + +/** + * @brief Get the PLL source used as IC4 clock source. + * @rmtoll IC4CFGR IC4SEL LL_RCC_IC4_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC4_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC4CFGR IC4INT LL_RCC_IC4_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC4_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4INT, (Divider - 1UL) << RCC_IC4CFGR_IC4INT_Pos); +} + +/** + * @brief Get IC4 divider + * @rmtoll IC4CFGR IC4INT LL_RCC_IC4_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC4_GetDivider(void) +{ + return ((READ_BIT(RCC->IC4CFGR, RCC_IC4CFGR_IC4INT) >> RCC_IC4CFGR_IC4INT_Pos) + 1UL); +} + +/** + * @brief Enable IC5 + * @rmtoll DIVENSR IC5ENS LL_RCC_IC5_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC5_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC5ENS); +} + +/** + * @brief Disable IC5 + * @rmtoll DIVENCR IC5ENC LL_RCC_IC5_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC5_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC5ENC); +} + +/** + * @brief Check if IC5 is enabled + * @rmtoll DIVENR IC5EN LL_RCC_IC5_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC5_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC5EN) == RCC_DIVENR_IC5EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC5 clock source. + * @rmtoll IC5CFGR IC5SEL LL_RCC_IC5_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC5_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL, Source); +} + +/** + * @brief Get the PLL source used as IC5 clock source. + * @rmtoll IC5CFGR IC5SEL LL_RCC_IC5_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC5_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC5CFGR IC5INT LL_RCC_IC5_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC5_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5INT, (Divider - 1UL) << RCC_IC5CFGR_IC5INT_Pos); +} + +/** + * @brief Get IC5 divider + * @rmtoll IC5CFGR IC5INT LL_RCC_IC5_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC5_GetDivider(void) +{ + return ((READ_BIT(RCC->IC5CFGR, RCC_IC5CFGR_IC5INT) >> RCC_IC5CFGR_IC5INT_Pos) + 1UL); +} + +/** + * @brief Enable IC6 + * @rmtoll DIVENSR IC6ENS LL_RCC_IC6_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC6_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC6ENS); +} + +/** + * @brief Disable IC6 + * @rmtoll DIVENCR IC6ENC LL_RCC_IC6_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC6_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC6ENC); +} + +/** + * @brief Check if IC6 is enabled + * @rmtoll DIVENR IC6EN LL_RCC_IC6_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC6_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC6EN) == RCC_DIVENR_IC6EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC6 clock source. + * @rmtoll IC6CFGR IC6SEL LL_RCC_IC6_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC6_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC6CFGR, RCC_IC6CFGR_IC6SEL, Source); +} + +/** + * @brief Get the PLL source used as IC6 clock source. + * @rmtoll IC6CFGR IC6SEL LL_RCC_IC6_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC6_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC6CFGR, RCC_IC6CFGR_IC6SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC6CFGR IC6INT LL_RCC_IC6_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC6_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC6CFGR, RCC_IC6CFGR_IC6INT, (Divider - 1UL) << RCC_IC6CFGR_IC6INT_Pos); +} + +/** + * @brief Get IC6 divider + * @rmtoll IC6CFGR IC6INT LL_RCC_IC6_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC6_GetDivider(void) +{ + return ((READ_BIT(RCC->IC6CFGR, RCC_IC6CFGR_IC6INT) >> RCC_IC6CFGR_IC6INT_Pos) + 1UL); +} + +/** + * @brief Enable IC7 + * @rmtoll DIVENSR IC7ENS LL_RCC_IC7_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC7_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC7ENS); +} + +/** + * @brief Disable IC7 + * @rmtoll DIVENCR IC7ENC LL_RCC_IC7_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC7_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC7ENC); +} + +/** + * @brief Check if IC7 is enabled + * @rmtoll DIVENR IC7EN LL_RCC_IC7_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC7_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC7EN) == RCC_DIVENR_IC7EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC7 clock source. + * @rmtoll IC7CFGR IC7SEL LL_RCC_IC7_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC7_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL, Source); +} + +/** + * @brief Get the PLL source used as IC7 clock source. + * @rmtoll IC7CFGR IC7SEL LL_RCC_IC7_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC7_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC7CFGR IC7INT LL_RCC_IC7_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC7_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7INT, (Divider - 1UL) << RCC_IC7CFGR_IC7INT_Pos); +} + +/** + * @brief Get IC7 divider + * @rmtoll IC7CFGR IC7INT LL_RCC_IC7_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC7_GetDivider(void) +{ + return ((READ_BIT(RCC->IC7CFGR, RCC_IC7CFGR_IC7INT) >> RCC_IC7CFGR_IC7INT_Pos) + 1UL); +} + +/** + * @brief Enable IC8 + * @rmtoll DIVENSR IC8ENS LL_RCC_IC8_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC8_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC8ENS); +} + +/** + * @brief Disable IC8 + * @rmtoll DIVENCR IC8ENC LL_RCC_IC8_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC8_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC8ENC); +} + +/** + * @brief Check if IC8 is enabled + * @rmtoll DIVENR IC8EN LL_RCC_IC8_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC8_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC8EN) == RCC_DIVENR_IC8EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC8 clock source. + * @rmtoll IC8CFGR IC8SEL LL_RCC_IC8_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC8_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL, Source); +} + +/** + * @brief Get the PLL source used as IC8 clock source. + * @rmtoll IC8CFGR IC8SEL LL_RCC_IC8_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC8_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC8CFGR IC8INT LL_RCC_IC8_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC8_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8INT, (Divider - 1UL) << RCC_IC8CFGR_IC8INT_Pos); +} + +/** + * @brief Get IC8 divider + * @rmtoll IC8CFGR IC8INT LL_RCC_IC8_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC8_GetDivider(void) +{ + return ((READ_BIT(RCC->IC8CFGR, RCC_IC8CFGR_IC8INT) >> RCC_IC8CFGR_IC8INT_Pos) + 1UL); +} + +/** + * @brief Enable IC9 + * @rmtoll DIVENSR IC9ENS LL_RCC_IC9_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC9_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC9ENS); +} + +/** + * @brief Disable IC9 + * @rmtoll DIVENCR IC9ENC LL_RCC_IC9_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC9_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC9ENC); +} + +/** + * @brief Check if IC9 is enabled + * @rmtoll DIVENR IC9EN LL_RCC_IC9_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC9_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC9EN) == RCC_DIVENR_IC9EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC9 clock source. + * @rmtoll IC9CFGR IC9SEL LL_RCC_IC9_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC9_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL, Source); +} + +/** + * @brief Get the PLL source used as IC9 clock source. + * @rmtoll IC9CFGR IC9SEL LL_RCC_IC9_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC9_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC9CFGR IC9INT LL_RCC_IC9_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC9_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9INT, (Divider - 1UL) << RCC_IC9CFGR_IC9INT_Pos); +} + +/** + * @brief Get IC9 divider + * @rmtoll IC9CFGR IC9INT LL_RCC_IC9_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC9_GetDivider(void) +{ + return ((READ_BIT(RCC->IC9CFGR, RCC_IC9CFGR_IC9INT) >> RCC_IC9CFGR_IC9INT_Pos) + 1UL); +} + +/** + * @brief Enable IC10 + * @rmtoll DIVENSR IC10ENS LL_RCC_IC10_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC10_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC10ENS); +} + +/** + * @brief Disable IC10 + * @rmtoll DIVENCR IC10ENC LL_RCC_IC10_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC10_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC10ENC); +} + +/** + * @brief Check if IC10 is enabled + * @rmtoll DIVENR IC10EN LL_RCC_IC10_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC10_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC10EN) == RCC_DIVENR_IC10EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC10 clock source. + * @rmtoll IC10CFGR IC10SEL LL_RCC_IC10_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC10_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL, Source); +} + +/** + * @brief Get the PLL source used as IC10 clock source. + * @rmtoll IC10CFGR IC10SEL LL_RCC_IC10_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC10_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC10CFGR IC10INT LL_RCC_IC10_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC10_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10INT, (Divider - 1UL) << RCC_IC10CFGR_IC10INT_Pos); +} + +/** + * @brief Get IC10 divider + * @rmtoll IC10CFGR IC10INT LL_RCC_IC10_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC10_GetDivider(void) +{ + return ((READ_BIT(RCC->IC10CFGR, RCC_IC10CFGR_IC10INT) >> RCC_IC10CFGR_IC10INT_Pos) + 1UL); +} + +/** + * @brief Enable IC11 + * @rmtoll DIVENSR IC11ENS LL_RCC_IC11_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC11_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC11ENS); +} + +/** + * @brief Disable IC11 + * @rmtoll DIVENCR IC11ENC LL_RCC_IC11_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC11_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC11ENC); +} + +/** + * @brief Check if IC11 is enabled + * @rmtoll DIVENR IC11EN LL_RCC_IC11_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC11_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC11EN) == RCC_DIVENR_IC11EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC11 clock source. + * @rmtoll IC11CFGR IC11SEL LL_RCC_IC11_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC11_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC11CFGR, RCC_IC11CFGR_IC11SEL, Source); +} + +/** + * @brief Get the PLL source used as IC11 clock source. + * @rmtoll IC11CFGR IC11SEL LL_RCC_IC11_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC11_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC11CFGR, RCC_IC11CFGR_IC11SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC11CFGR IC11INT LL_RCC_IC11_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC11_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC11CFGR, RCC_IC11CFGR_IC11INT, (Divider - 1UL) << RCC_IC11CFGR_IC11INT_Pos); +} + +/** + * @brief Get IC11 divider + * @rmtoll IC11CFGR IC11INT LL_RCC_IC11_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC11_GetDivider(void) +{ + return ((READ_BIT(RCC->IC11CFGR, RCC_IC11CFGR_IC11INT) >> RCC_IC11CFGR_IC11INT_Pos) + 1UL); +} + +/** + * @brief Enable IC12 + * @rmtoll DIVENSR IC12ENS LL_RCC_IC12_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC12_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC12ENS); +} + +/** + * @brief Disable IC12 + * @rmtoll DIVENCR IC12ENC LL_RCC_IC12_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC12_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC12ENC); +} + +/** + * @brief Check if IC12 is enabled + * @rmtoll DIVENR IC12EN LL_RCC_IC12_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC12_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC12EN) == RCC_DIVENR_IC12EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC12 clock source. + * @rmtoll IC12CFGR IC12SEL LL_RCC_IC12_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC12_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL, Source); +} + +/** + * @brief Get the PLL source used as IC12 clock source. + * @rmtoll IC12CFGR IC12SEL LL_RCC_IC12_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC12_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC12CFGR IC12INT LL_RCC_IC12_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC12_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12INT, (Divider - 1UL) << RCC_IC12CFGR_IC12INT_Pos); +} + +/** + * @brief Get IC12 divider + * @rmtoll IC12CFGR IC12INT LL_RCC_IC12_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC12_GetDivider(void) +{ + return ((READ_BIT(RCC->IC12CFGR, RCC_IC12CFGR_IC12INT) >> RCC_IC12CFGR_IC12INT_Pos) + 1UL); +} + +/** + * @brief Enable IC13 + * @rmtoll DIVENSR IC13ENS LL_RCC_IC13_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC13_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC13ENS); +} + +/** + * @brief Disable IC13 + * @rmtoll DIVENCR IC13ENC LL_RCC_IC13_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC13_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC13ENC); +} + +/** + * @brief Check if IC13 is enabled + * @rmtoll DIVENR IC13EN LL_RCC_IC13_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC13_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC13EN) == RCC_DIVENR_IC13EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC13 clock source. + * @rmtoll IC13CFGR IC13SEL LL_RCC_IC13_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC13_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL, Source); +} + +/** + * @brief Get the PLL source used as IC13 clock source. + * @rmtoll IC13CFGR IC13SEL LL_RCC_IC13_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC13_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC13CFGR IC13INT LL_RCC_IC13_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC13_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13INT, (Divider - 1UL) << RCC_IC13CFGR_IC13INT_Pos); +} + +/** + * @brief Get IC13 divider + * @rmtoll IC13CFGR IC13INT LL_RCC_IC13_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC13_GetDivider(void) +{ + return ((READ_BIT(RCC->IC13CFGR, RCC_IC13CFGR_IC13INT) >> RCC_IC13CFGR_IC13INT_Pos) + 1UL); +} + +/** + * @brief Enable IC14 + * @rmtoll DIVENSR IC14ENS LL_RCC_IC14_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC14_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC14ENS); +} + +/** + * @brief Disable IC14 + * @rmtoll DIVENCR IC14ENC LL_RCC_IC14_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC14_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC14ENC); +} + +/** + * @brief Check if IC14 is enabled + * @rmtoll DIVENR IC14EN LL_RCC_IC14_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC14_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC14EN) == RCC_DIVENR_IC14EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC14 clock source. + * @rmtoll IC14CFGR IC14SEL LL_RCC_IC14_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC14_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL, Source); +} + +/** + * @brief Get the PLL source used as IC14 clock source. + * @rmtoll IC14CFGR IC14SEL LL_RCC_IC14_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC14_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC14CFGR IC14INT LL_RCC_IC14_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC14_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14INT, (Divider - 1UL) << RCC_IC14CFGR_IC14INT_Pos); +} + +/** + * @brief Get IC14 divider + * @rmtoll IC14CFGR IC14INT LL_RCC_IC14_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC14_GetDivider(void) +{ + return ((READ_BIT(RCC->IC14CFGR, RCC_IC14CFGR_IC14INT) >> RCC_IC14CFGR_IC14INT_Pos) + 1UL); +} + +/** + * @brief Enable IC15 + * @rmtoll DIVENSR IC15ENS LL_RCC_IC15_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC15_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC15ENS); +} + +/** + * @brief Disable IC15 + * @rmtoll DIVENCR IC15ENC LL_RCC_IC15_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC15_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC15ENC); +} + +/** + * @brief Check if IC15 is enabled + * @rmtoll DIVENR IC15EN LL_RCC_IC15_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC15_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC15EN) == RCC_DIVENR_IC15EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC15 clock source. + * @rmtoll IC15CFGR IC15SEL LL_RCC_IC15_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC15_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL, Source); +} + +/** + * @brief Get the PLL source used as IC15 clock source. + * @rmtoll IC15CFGR IC15SEL LL_RCC_IC15_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC15_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC15CFGR IC15INT LL_RCC_IC15_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC15_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15INT, (Divider - 1UL) << RCC_IC15CFGR_IC15INT_Pos); +} + +/** + * @brief Get IC15 divider + * @rmtoll IC15CFGR IC15INT LL_RCC_IC15_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC15_GetDivider(void) +{ + return ((READ_BIT(RCC->IC15CFGR, RCC_IC15CFGR_IC15INT) >> RCC_IC15CFGR_IC15INT_Pos) + 1UL); +} + +/** + * @brief Enable IC16 + * @rmtoll DIVENSR IC16ENS LL_RCC_IC16_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC16_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC16ENS); +} + +/** + * @brief Disable IC16 + * @rmtoll DIVENCR IC16ENC LL_RCC_IC16_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC16_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC16ENC); +} + +/** + * @brief Check if IC16 is enabled + * @rmtoll DIVENR IC16EN LL_RCC_IC16_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC16_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC16EN) == RCC_DIVENR_IC16EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC16 clock source. + * @rmtoll IC16CFGR IC16SEL LL_RCC_IC16_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC16_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL, Source); +} + +/** + * @brief Get the PLL source used as IC16 clock source. + * @rmtoll IC16CFGR IC16SEL LL_RCC_IC16_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC16_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC16CFGR IC16INT LL_RCC_IC16_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC16_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16INT, (Divider - 1UL) << RCC_IC16CFGR_IC16INT_Pos); +} + +/** + * @brief Get IC16 divider + * @rmtoll IC16CFGR IC16INT LL_RCC_IC16_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC16_GetDivider(void) +{ + return ((READ_BIT(RCC->IC16CFGR, RCC_IC16CFGR_IC16INT) >> RCC_IC16CFGR_IC16INT_Pos) + 1UL); +} + +/** + * @brief Enable IC17 + * @rmtoll DIVENSR IC17ENS LL_RCC_IC17_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC17_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC17ENS); +} + +/** + * @brief Disable IC17 + * @rmtoll DIVENCR IC17ENC LL_RCC_IC17_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC17_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC17ENC); +} + +/** + * @brief Check if IC17 is enabled + * @rmtoll DIVENR IC17EN LL_RCC_IC17_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC17_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC17EN) == RCC_DIVENR_IC17EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC17 clock source. + * @rmtoll IC17CFGR IC17SEL LL_RCC_IC17_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC17_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL, Source); +} + +/** + * @brief Get the PLL source used as IC17 clock source. + * @rmtoll IC17CFGR IC17SEL LL_RCC_IC17_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC17_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC17CFGR IC17INT LL_RCC_IC17_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC17_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17INT, (Divider - 1UL) << RCC_IC17CFGR_IC17INT_Pos); +} + +/** + * @brief Get IC17 divider + * @rmtoll IC17CFGR IC17INT LL_RCC_IC17_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC17_GetDivider(void) +{ + return ((READ_BIT(RCC->IC17CFGR, RCC_IC17CFGR_IC17INT) >> RCC_IC17CFGR_IC17INT_Pos) + 1UL); +} + +/** + * @brief Enable IC18 + * @rmtoll DIVENSR IC18ENS LL_RCC_IC18_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC18_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC18ENS); +} + +/** + * @brief Disable IC18 + * @rmtoll DIVENCR IC18ENC LL_RCC_IC18_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC18_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC18ENC); +} + +/** + * @brief Check if IC18 is enabled + * @rmtoll DIVENR IC18EN LL_RCC_IC18_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC18_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC18EN) == RCC_DIVENR_IC18EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC18 clock source. + * @rmtoll IC18CFGR IC18SEL LL_RCC_IC18_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC18_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL, Source); +} + +/** + * @brief Get the PLL source used as IC18 clock source. + * @rmtoll IC18CFGR IC18SEL LL_RCC_IC18_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC18_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC18CFGR IC18INT LL_RCC_IC18_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC18_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18INT, (Divider - 1UL) << RCC_IC18CFGR_IC18INT_Pos); +} + +/** + * @brief Get IC18 divider + * @rmtoll IC18CFGR IC18INT LL_RCC_IC18_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC18_GetDivider(void) +{ + return ((READ_BIT(RCC->IC18CFGR, RCC_IC18CFGR_IC18INT) >> RCC_IC18CFGR_IC18INT_Pos) + 1UL); +} + +/** + * @brief Enable IC19 + * @rmtoll DIVENSR IC19ENS LL_RCC_IC19_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC19_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC19ENS); +} + +/** + * @brief Disable IC19 + * @rmtoll DIVENCR IC19ENC LL_RCC_IC19_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC19_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC19ENC); +} + +/** + * @brief Check if IC19 is enabled + * @rmtoll DIVENR IC19EN LL_RCC_IC19_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC19_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC19EN) == RCC_DIVENR_IC19EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC19 clock source. + * @rmtoll IC19CFGR IC19SEL LL_RCC_IC19_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC19_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL, Source); +} + +/** + * @brief Get the PLL source used as IC19 clock source. + * @rmtoll IC19CFGR IC19SEL LL_RCC_IC19_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC19_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC19CFGR IC19INT LL_RCC_IC19_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC19_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19INT, (Divider - 1UL) << RCC_IC19CFGR_IC19INT_Pos); +} + +/** + * @brief Get IC19 divider + * @rmtoll IC19CFGR IC19INT LL_RCC_IC19_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC19_GetDivider(void) +{ + return ((READ_BIT(RCC->IC19CFGR, RCC_IC19CFGR_IC19INT) >> RCC_IC19CFGR_IC19INT_Pos) + 1UL); +} + +/** + * @brief Enable IC20 + * @rmtoll DIVENSR IC20ENS LL_RCC_IC20_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC20_Enable(void) +{ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC20ENS); +} + +/** + * @brief Disable IC20 + * @rmtoll DIVENCR IC20ENC LL_RCC_IC20_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC20_Disable(void) +{ + WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC20ENC); +} + +/** + * @brief Check if IC20 is enabled + * @rmtoll DIVENR IC20EN LL_RCC_IC20_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IC20_IsEnabled(void) +{ + return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC20EN) == RCC_DIVENR_IC20EN) ? 1UL : 0UL); +} + +/** + * @brief Set the PLL source used as IC20 clock source. + * @rmtoll IC20CFGR IC20SEL LL_RCC_IC20_SetSource + * @param Source parameter can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC20_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL, Source); +} + +/** + * @brief Get the PLL source used as IC20 clock source. + * @rmtoll IC20CFGR IC20SEL LL_RCC_IC20_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ICCLKSOURCE_PLL1 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL2 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL3 + * @arg @ref LL_RCC_ICCLKSOURCE_PLL4 + */ +__STATIC_INLINE uint32_t LL_RCC_IC20_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL)); +} + +/** + * @brief Set divider + * @rmtoll IC20CFGR IC20INT LL_RCC_IC20_SetDivider + * @param Divider This parameter can be a value between 1 and 256. + * @retval None + */ +__STATIC_INLINE void LL_RCC_IC20_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20INT, (Divider - 1UL) << RCC_IC20CFGR_IC20INT_Pos); +} + +/** + * @brief Get IC20 divider + * @rmtoll IC20CFGR IC20INT LL_RCC_IC20_GetDivider + * @retval can be a value between 1 and 256. + */ +__STATIC_INLINE uint32_t LL_RCC_IC20_GetDivider(void) +{ + return ((READ_BIT(RCC->IC20CFGR, RCC_IC20CFGR_IC20INT) >> RCC_IC20CFGR_IC20INT_Pos) + 1UL); +} + +/** + * @brief Enable CLKP + * @rmtoll MISCENSR PERENS LL_RCC_CLKP_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CLKP_Enable(void) +{ + WRITE_REG(RCC->MISCENSR, RCC_MISCENSR_PERENS); +} + +/** + * @brief Disable CLKP + * @rmtoll MISCENCR PERENC LL_RCC_CLKP_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CLKP_Disable(void) +{ + WRITE_REG(RCC->MISCENCR, RCC_MISCENCR_PERENC); +} + +/** + * @brief Check if CLKP is enabled + * @rmtoll MISCENR PEREN LL_RCC_CLKP_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CLKP_IsEnabled(void) +{ + return ((READ_BIT(RCC->MISCENR, RCC_MISCENR_PEREN) == RCC_MISCENR_PEREN) ? 1UL : 0UL); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear MSI ready interrupt flag + * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_MSIRDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_PLL1RDYC); +} + +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_PLL2RDYC); +} + +/** + * @brief Clear PLL3 ready interrupt flag + * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_PLL3RDYC); +} + +/** + * @brief Clear PLL4 ready interrupt flag + * @rmtoll CICR PLL4RDYC LL_RCC_ClearFlag_PLL4RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL4RDY(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_PLL4RDYC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Clear HSE Clock security system interrupt flag + * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + +/** + * @brief Clear WKUP ready interrupt flag + * @rmtoll CICR WKUPFC LL_RCC_ClearFlag_WKUP + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_WKUP(void) +{ + WRITE_REG(RCC->CICR, RCC_CICR_WKUPFC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if MSI ready interrupt occurred or not + * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 ready interrupt occurred or not + * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL4 ready interrupt occurred or not + * @rmtoll CIFR PLL4RDYF LL_RCC_IsActiveFlag_PLL4RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL4RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL4RDYF) == RCC_CIFR_PLL4RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE Clock security system interrupt occurred or not + * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if WKUP from STOP interrupt occurred or not + * @rmtoll CIFR WKUPF LL_RCC_IsActiveFlag_WKUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WKUP(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_WKUPF) == RCC_CIFR_WKUPF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == RCC_RSR_PORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag CPU Lockup reset is set or not. + * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_LCKRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LCKRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_LCKRSTF) == (RCC_RSR_LCKRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC ETH1 power-down start acknowledged is set or not. + * @rmtoll CCIPR2 ETH1PWRDOWNACK LL_RCC_IsActiveFlag_ETH1PWRDOWNACK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_ETH1PWRDOWNACK(void) +{ + return ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PWRDOWNACK) == (RCC_CCIPR2_ETH1PWRDOWNACK)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear all reset flags. + * @rmtoll RSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Enable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Enable PLL4 ready interrupt + * @rmtoll CIER PLL4RDYIE LL_RCC_EnableIT_PLL4RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL4RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE); +} + +/** + * @brief Enable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Enable HSECSS interrupt + * @rmtoll CIER HSECSSIE LL_RCC_EnableIT_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSECSSIE); +} + +/** + * @brief Enable WKUP interrupt + * @rmtoll CIER WKUPIE LL_RCC_EnableIT_WKUP + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_WKUP(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_WKUPIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Disable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Disable PLL4 ready interrupt + * @rmtoll CIER PLL4RDYIE LL_RCC_DisableIT_PLL4RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL4RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE); +} + +/** + * @brief Disable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable HSECSS interrupt + * @rmtoll CIER HSECSSIE LL_RCC_DisableIT_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSECSSIE); +} + +/** + * @brief Disable WKUP interrupt + * @rmtoll CIER WKUPIE LL_RCC_DisableIT_WKUP + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_WKUP(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_WKUPIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if MSI ready interrupt source is enabled or disabled. + * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL3 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL4 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL4RDYIE LL_RCC_IsEnabledIT_PLL4RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL4RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE) == RCC_CIER_PLL4RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSECSS interrupt source is enabled or disabled. + * @rmtoll CIER HSECSSIE LL_RCC_IsEnabledIT_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSECSSIE) == RCC_CIER_HSECSSIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if WKUP interrupt source is enabled or disabled. + * @rmtoll CIER WKUPIE LL_RCC_IsEnabledIT_WKUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_WKUP(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_WKUPIE) == RCC_CIER_WKUPIE) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +void LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); + +uint32_t LL_RCC_GetCpuClockFreq(void); +uint32_t LL_RCC_GetSystemClockFreq(void); +uint32_t LL_RCC_GetPLL1ClockFreq(void); +uint32_t LL_RCC_GetPLL2ClockFreq(void); +uint32_t LL_RCC_GetPLL3ClockFreq(void); +uint32_t LL_RCC_GetPLL4ClockFreq(void); +uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1, + uint32_t P2); + +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource); +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); +uint32_t LL_RCC_GetDCMIPPClockFreq(uint32_t DCMIPPxSource); +uint32_t LL_RCC_GetETHClockFreq(uint32_t ETHxSource); +uint32_t LL_RCC_GetETHPTPClockFreq(uint32_t ETHxPTPSource); +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +uint32_t LL_RCC_GetMDFClockFreq(uint32_t MDFxSource); +uint32_t LL_RCC_GetOTGPHYClockFreq(uint32_t OTGPHYxSource); +uint32_t LL_RCC_GetOTGPHYCKREFClockFreq(uint32_t OTGPHYxCKREFSource); +uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_LL_RCC_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_system.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_system.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_system.h (revision 16) @@ -0,0 +1,750 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_SYSTEM_H +#define STM32N6xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ + +#if defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast Mode Plus on PA15 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast Mode Plus on PB3 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal + with Break Input of TIM1/16/17 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection + with TIM1/16/17 Break Input and also + the PVDE and PLS bits of the Power Control Interface */ +#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal + with Break Input of TIM1/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33 + with Break Input of TIM1/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes + * @note Only available when system implements security (TZEN=1) + * @{ + */ +#define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */ +#define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */ +#define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */ +#define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */ +#define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */ +#define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_DBGMCU_DBTRGIN 0U /*!< DBTRGIO connected to DBTRGIN */ +#define LL_DBGMCU_DBTRGOUT DBGMCU_CR_DBTRGOEN /*!< DBTRGIO connected to DBTRGOUT */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP /*!< TIM3 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP /*!< TIM4 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP /*!< TIM5 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP /*!< TIM6 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP /*!< TIM7 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP /*!< TIM12 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP /*!< TIM13 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP /*!< TIM14 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP /*!< LPTIM1 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP /*!< WWDG1 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP /*!< TIM10 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP /*!< TIM11 stop in debug */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout stop in debug */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout stop in debug */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout stop in debug */ +#define LL_DBGMCU_APB1_GRP1_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP /*!< I3C1 SMBUS timeout stop in debug */ +#define LL_DBGMCU_APB1_GRP1_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP /*!< I3C2 SMBUS timeout stop in debug */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP /*!< FDCAN stop in debug */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP /*!< TIM1 stop in debug */ +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP /*!< TIM8 stop in debug */ +#define LL_DBGMCU_APB2_GRP1_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP /*!< TIM18 stop in debug */ +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP /*!< TIM15 stop in debug */ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP /*!< TIM16 stop in debug */ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP /*!< TIM17 stop in debug */ +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP /*!< TIM9 stop in debug */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP /*!< I2C4 stop in debug */ +#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP /*!< LPTIM2 stop in debug */ +#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP /*!< LPTIM3 stop in debug */ +#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP /*!< LPTIM4 stop in debug */ +#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP /*!< LPTIM5 stop in debug */ +#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP /*!< RTC stop in debug */ +#define LL_DBGMCU_APB4_GRP1_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP /*!< IWDG stop in debug */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB5_GRP1_STOP_IP DBGMCU APB5 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB5_GRP1_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP /*!< GFXTIM stop in debug */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP /*!< GPDMA1_CH0 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP /*!< GPDMA1_CH1 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP /*!< GPDMA1_CH2 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP /*!< GPDMA1_CH3 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP /*!< GPDMA1_CH4 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP /*!< GPDMA1_CH5 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP /*!< GPDMA1_CH6 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP /*!< GPDMA1_CH7 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP /*!< GPDMA1_CH8 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP /*!< GPDMA1_CH9 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP /*!< GPDMA1_CH10 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP /*!< GPDMA1_CH11 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP /*!< GPDMA1_CH12 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP /*!< GPDMA1_CH13 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP /*!< GPDMA1_CH14 suspend in debug */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP /*!< GPDMA1_CH15 suspend in debug */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_AHB5_GRP1_STOP_IP DBGMCU AHB5 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP /*!< HPDMA1_CH0 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP /*!< HPDMA1_CH1 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP /*!< HPDMA1_CH2 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP /*!< HPDMA1_CH3 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP /*!< HPDMA1_CH4 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP /*!< HPDMA1_CH5 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP /*!< HPDMA1_CH6 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP /*!< HPDMA1_CH7 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP /*!< HPDMA1_CH8 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP /*!< HPDMA1_CH9 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP /*!< HPDMA1_CH10 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP /*!< HPDMA1_CH11 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP /*!< HPDMA1_CH12 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP /*!< HPDMA1_CH13 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP /*!< HPDMA1_CH14 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP /*!< HPDMA1_CH15 suspend in debug */ +#define LL_DBGMCU_AHB5_GRP1_NPU_STOP DBGMCU_AHB5FZ1_NPU_DBG_FREEZE /*!< NPU stop in debug mode */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Returns the device identifier + * @note The BSEC clock must be enabled before calling this function + * Returned Device ID can be + * 0x00006200 for STM32N645xx + * 0x00006000 for STM32N655xx + * 0x00002200 for STM32N647xx + * 0x00002000 for STM32N657xx + * 0xffffffff if an error occurs + * @retval Device identifier + */ +__STATIC_INLINE uint32_t LL_GetDeviceID(void) +{ + return (uint32_t)(READ_REG(BSEC->FVRw[9])); +} + + +/** + * @brief Returns the device revision identifier + * @note Returned Revision ID can be + * 0x00000100 for Cut1.0 + * 0x00000101 for Cut1.1 + * 0x00000200 for Cut2.0 + * @retval Device revision identifier + */ +__STATIC_INLINE uint32_t LL_GetRevisionID(void) +{ + return *(uint32_t *)(REVID_BASE); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enable the Debug clock through software + * @rmtoll DBGMCU_CR DBGCLKEN LL_DBGMCU_EnableDBGClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN); +} + +/** + * @brief Disable the Debug clock through software + * @rmtoll DBGMCU_CR DBGCLKEN LL_DBGMCU_DisableDBGClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN); +} + +/** + * @brief Enable the TPIU export clock enable through software + * @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_EnableTPIUExportClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTPIUExportClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN); +} + +/** + * @brief Disable the TPIU export clock enable through software + * @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_DisableTPIUExportClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTPIUExportClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN); +} + +/** + * @brief Set DBTRGIO connection control + * @rmtoll DBGMCU_CR DBTRGOEN LL_DBGMCU_SetDBTRGIOConnectionControl + * @param ConfigDBTRGIO This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_DBTRGIN + * @arg @ref LL_DBGMCU_DBTRGOUT + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetDBTRGIOConnectionControl(uint32_t ConfigDBTRGIO) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBTRGOEN, ConfigDBTRGIO); +} + +/** + * @brief Get DBTRGIO connection control + * @rmtoll DBGMCU_CR DBTRGOEN LL_DBGMCU_GetDBTRGIOConnectionControl + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_DBTRGIN + * @arg @ref LL_DBGMCU_DBTRGOUT + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDBTRGIOConnectionControl(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBTRGOEN)); +} + +/** + * @brief Enable TSGEN halt + * @rmtoll DBGMCU_CR HLT_TSGEN_EN LL_DBGMCU_EnableTSGENHalt + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTSGENHalt(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN); +} + +/** + * @brief Disable TSGEN halt + * @rmtoll DBGMCU_CR HLT_TSGEN_EN LL_DBGMCU_DisableTSGENHalt + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTSGENHalt(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1LFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1LFZ DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP LL_DBGMCU_APB2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP LL_DBGMCU_APB2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_UnFreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Freeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP LL_DBGMCU_APB4_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB4FZ1, Periphs); +} + +/** + * @brief Unreeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP LL_DBGMCU_APB4_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_UnFreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB4FZ1, Periphs); +} + +/** + * @brief Freeze APB5 peripherals + * @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP LL_DBGMCU_APB5_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB5_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB5FZ1, Periphs); +} + +/** + * @brief Unreeze APB5 peripherals + * @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP LL_DBGMCU_APB5_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB5_UnFreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB5FZ1, Periphs); +} + +/** + * @brief Freeze AHB1 peripherals + * @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB1FZ1, Periphs); +} + +/** + * @brief Unreeze AHB1 peripherals + * @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_UnFreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB1FZ1, Periphs); +} + +/** + * @brief Freeze AHB5 peripherals + * @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB5_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB5_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB5FZ1, Periphs); +} + +/** + * @brief Unreeze AHB5 peripherals + * @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB5_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB5_UnFreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB5FZ1, Periphs); +} + + +/** + * @} + */ + +#endif /* defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_LL_SYSTEM_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_utils.h =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_utils.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_utils.h (revision 16) @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file stm32n6xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_LL_UTILS_H +#define STM32N6xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx.h" +#include "stm32n6xx_ll_system.h" +#include "stm32n6xx_ll_bus.h" +#include "stm32n6xx_ll_rcc.h" + +/** @addtogroup STM32N6xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFUL + +/** + * @brief Unique device ID register base address + * Available from BSEC_OTP_DATA5...BSEC_OTP_DATA7 + */ +#define UID_BASE_ADDRESS (BSEC_BASE + 0x14U) + +/** + * @brief Device RPN register base address + * Available from BSEC_OTP_DATA9 + */ +#define RPN_BASE_ADDRESS (BSEC_BASE + 0x24U) + +/** + * @brief Package data register base address + * Available from BSEC_OTP_DATA122 + */ +#define PACKAGE_BASE_ADDRESS (BSEC_BASE + 0x1E8U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ + +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor M for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 + and shall ensure that VCO input is below 50 MHz. + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetM(). */ + + uint32_t PLLN; /*!< Multiplication factor N for PLL VCO output clock. + This parameter must be a number between Min_Data = 16 and Max_Data = 640 + in integer mode and between Min_Data = 20 and Max_Data = 320 in fractional mode + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetN(). */ + + uint32_t PLLP1; /*!< Division factor level 1 for PLL VCO output clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 7 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetP1(). */ + + uint32_t PLLP2; /*!< Division factor level 2 for PLL VCO output clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 7 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetP2(). */ + + uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO. + This parameter can be a value between 0 and (2^24)-1 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetFRACN(). */ + +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS IC structure definition + */ +typedef struct +{ + uint32_t IC1Source; /*!< The IC1 clock source for sysa_ck(cpu_ck) */ + uint32_t IC1Divider; /*!< The IC1 clock divider for sysa_ck(cpu_ck) */ + uint32_t IC2Source; /*!< The IC2 clock source for sysb_ck */ + uint32_t IC2Divider; /*!< The IC2 clock divider for sysb_ck */ + uint32_t IC6Source; /*!< The IC6 clock source for sysc_ck */ + uint32_t IC6Divider; /*!< The IC6 clock divider for sysc_ck */ + uint32_t IC11Source; /*!< The IC11 clock source for sysd_ck */ + uint32_t IC11Divider; /*!< The IC11 clock divider for sysd_ck */ + +} LL_UTILS_ICInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_AHB_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB4_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB4Prescaler(). */ + + uint32_t APB5CLKDivider; /*!< The APB5 clock (PCLK5) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB5_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB5Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 1U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_DEVICE_RPN DEVICE RPN + * @{ + */ +#define LL_UTILS_DEVICE_STM32N657 0x2000U /*!< STM32N657 */ +#define LL_UTILS_DEVICE_STM32N647 0x2200U /*!< STM32N647 */ +#define LL_UTILS_DEVICE_STM32N655 0x6000U /*!< STM32N655 */ +#define LL_UTILS_DEVICE_STM32N645 0x6200U /*!< STM32N645 */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_BGA142 2U /*!< BGA142 package type */ +#define LL_UTILS_PACKAGETYPE_BGA169 4U /*!< BGA169 package type */ +#define LL_UTILS_PACKAGETYPE_BGA178 6U /*!< BGA178 package type */ +#define LL_UTILS_PACKAGETYPE_BGA198 8U /*!< BGA198 package type */ +#define LL_UTILS_PACKAGETYPE_BGA223 10U /*!< BGA223 package type */ +#define LL_UTILS_PACKAGETYPE_BGA264 12U /*!< BGA264 package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @note The application must ensures that SYSCFG clock is enabled. + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @note The application must ensures that SYSCFG clock is enabled. + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @note The application must ensures that SYSCFG clock is enabled. + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Package type + * @note The application must ensures that SYSCFG clock is enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_BGA142 + * @arg @ref LL_UTILS_PACKAGETYPE_BGA169 + * @arg @ref LL_UTILS_PACKAGETYPE_BGA178 + * @arg @ref LL_UTILS_PACKAGETYPE_BGA198 + * @arg @ref LL_UTILS_PACKAGETYPE_BGA223 + * @arg @ref LL_UTILS_PACKAGETYPE_BGA264 + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0FUL); +} + +/** + * @brief Get Device Part Number (RPN) + * @note The application must ensures that SYSCFG clock is enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_DEVICE_STM32N657 + * @arg @ref LL_UTILS_DEVICE_STM32N647 + * @arg @ref LL_UTILS_DEVICE_STM32N645 + */ +__STATIC_INLINE uint32_t LL_GetDevicePartNumber(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)RPN_BASE_ADDRESS))); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + if (Ticks > 0U) + { + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ + } +} + +void LL_Init1msTick(uint32_t CPU_Frequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t CPU_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct, + const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct, + const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_MSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct, + const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct, + const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, + uint32_t HSEBypass, + const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct, + const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct, + const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_LL_UTILS_H */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/LICENSE.txt =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/LICENSE.txt (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/LICENSE.txt (revision 16) @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal.c (revision 16) @@ -0,0 +1,2167 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + [..] + All the SYSCFG functions have the same privilege and security attributes. + (+) Functions can operate in non-privileged code should + privileged and unprivileged data access are granted to the + peripheral (see HAL_RIF_RISC_SetSlaveSecureAttributes) + + (+) Functions can operate in non-secure code should + secure and non-secure data access are granted to the peripheral + (see HAL_RIF_RISC_SetSlaveSecureAttributes). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define HAL_TIMEOUT_SYSCFG_ABORT 5U /* 5 ms */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the NVIC allocation and initial clock configuration. + It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the time base source, NVIC and any required global low + * level hardware by calling the HAL_MspInit() callback function to be optionally defined + * in user file stm32n6xx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (Systick) is used as source of time base. + * The Systick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset and the NVIC configuration is set to Priority group 4. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Ensure time base clock coherency in SystemCoreClock global variable */ + SystemCoreClockUpdate(); + + /* Initialize 1ms tick time base (default SysTick based on HSI clock after Reset) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-initializes all peripherals and low level hardware resources. + * @note This function should only be called from code running in internal RAM + * since it resets the external peripheral memory interfaces. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB4_FORCE_RESET(); + __HAL_RCC_APB4_RELEASE_RESET(); + + __HAL_RCC_APB5_FORCE_RESET(); + __HAL_RCC_APB5_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + __HAL_RCC_AHB4_FORCE_RESET(); + __HAL_RCC_AHB4_RELEASE_RESET(); + + __HAL_RCC_AHB5_FORCE_RESET(); + __HAL_RCC_AHB5_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if ((uint32_t)uwTickFreq == 0UL) + { + return HAL_ERROR; + } + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @param Freq Tick frequency, value of @ref HAL_TickFreqTypeDef. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay Specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32N6xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier + * @note Returned Revision ID can be + * 0x00000100 for Cut1.0 + * 0x00000101 for Cut1.1 + * 0x00000200 for Cut2.0 + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return *(uint32_t *)(REVID_BASE); +} + +#if defined(CPU_IN_SECURE_STATE) +/** + * @brief Returns the device identifier + * @note This function can only be used if the HAL BSEC module is enabled in the hal configuration file. + * The BSEC clock must be enabled before calling this function + * Returned Device ID can be + * 0x00006200 for STM32N645xx + * 0x00006000 for STM32N655xx + * 0x00002200 for STM32N647xx + * 0x00002000 for STM32N657xx + * 0xFFFFFFFF if an error occurs + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ +#if defined(HAL_BSEC_MODULE_ENABLED) +#define BSEC_FUSE_ADDRESS 9U + uint32_t data; + if(__HAL_RCC_BSEC_IS_CLK_ENABLED() == 0UL){ + data = 0xFFFFFFFFU; + } + else + { + BSEC_HandleTypeDef sBsecHandler = {0}; + sBsecHandler.Instance = BSEC; + + if(HAL_BSEC_OTP_Read(&sBsecHandler, BSEC_FUSE_ADDRESS, &data) != HAL_OK){ + data = 0xFFFFFFFFU; + } + } + return data; +#else + return 0xFFFFFFFFU; +#endif /* HAL_BSEC_MODULE_ENABLED */ +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @note The application must ensures that SYSCFG clock is enabled. + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @note The application must ensures that SYSCFG clock is enabled. + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @note The application must ensures that SYSCFG clock is enabled. + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during Stop modes + (+) Enable/Disable Debug module during Stanby mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during Sleep mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during Sleep mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during Stop mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during Stop mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during Stanby mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during Stanby mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions + * @brief HAL SYSCFG configuration functions + * +@verbatim + =============================================================================== + ##### HAL SYSCFG configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable or disable BOOT pins pull-down. + (+) Lock and get locks status of system items. + (+) Set (and get) TCM size and DTCM size. + (+) Lock (and get) write accesses. + (+) Enable or disable wait state on extended ITCM and DTCM. + (+) Enable or disable external RW margin input for TCM memories. + (+) Set and get the TCM biasing level. + (+) Enable or disable the external RW for caches memories. + (+) Set and get the cache biasing level. + (+) Enable or disable the Power-on reset upon SW system request. + (+) Enable or disable that Lockup requests a warm reset to the RCC + (+) Enable or disable that Lockup generates a NMI on the core + (+) Clear Error capture in write posting buffer + (+) Reserve VENCRAM for VENC or release it (any use allowed) + (+) Enable or disable PKA, SAES, CRYP1/2 and HASH reset in case of potential tamper + (+) Set/Get write/read Qos for NP1, NP2 or CPU. + (+) Enable or disable SDMMC early-write response. + (+) Enable or disable USB early-write response. + (+) Enable or disable the NPU NIC, NPU NOC or CPU NOC clock gating. + (+) Enable or disable the VDDIOx compensation cell. + (+) Configure or get VDDIOx compensation cells. + (+) Get VDDIOx compensation ready status. + (+) Enable or disable the VDD compensation cell. + (+) Configure or get VDD compensation cells. + (+) Configure or get the Timer Break input for error flag + (+) Set and get secure OS allocation of specific CID to the DMA channel + (+) Set and get non-secure OS allocation of specific CID to the DMA channel + (+) Enable or disable Retiming on RX path. + (+) Enable or disable Retiming on TX path. + (+) Set and get Delay on feedback clock. + (+) Enable or disable the interleaving on NPU RAM. + (+) Get BOOT pin connection status + (+) Get the address of first error in P-AHB write-posting buffer + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Pull Down on BOOT pin. + * @param BootId Specifies the boot pins. + * This parameter can one of the following values: + * @arg SYSCFG_BOOT_0 boot 0 pin + * @arg SYSCFG_BOOT_1 boot 1 pin + * @retval None + */ +void HAL_SYSCFG_EnablePullDown(uint32_t BootId) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_ID(BootId)); + + SET_BIT(SYSCFG->BOOTCR, BootId); +} + +/** + * @brief Disable the Pull Down on BOOT pin. + * @param BootId Specifies the boot pins. + * This parameter can one of the following values: + * @arg SYSCFG_BOOT_0 boot 0 pin + * @arg SYSCFG_BOOT_1 boot 1 pin + * @retval None + */ +void HAL_SYSCFG_DisablePullDown(uint32_t BootId) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_ID(BootId)); + + CLEAR_BIT(SYSCFG->BOOTCR, BootId); +} + +/** + * @brief Lock the SYSCFG item(s). + * @note Lock(s) cleared only at system reset + * @param Item Item(s) to set lock on. + * This parameter can be a combination of @ref SYSCFG_Lock_items + * @retval None + */ +void HAL_SYSCFG_Lock(uint32_t Item) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_LOCK_ITEMS(Item)); + + MODIFY_REG(SYSCFG->CM55CR, SYSCFG_LOCK_ALL, Item); +} + +/** + * @brief Get the lock state of SYSCFG item. + * @param pItem Pointer to return locked items + * the return value can be a combination of @ref SYSCFG_Lock_items + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) +{ + /* Check null pointer */ + if (pItem == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + *pItem = READ_BIT(SYSCFG->CM55CR, SYSCFG_LOCK_ALL); + + return HAL_OK; +} + +/** + * @brief Set the DTCM and ITCM memory sizes. + * @note Write-once TCM configuration change. + * @note Effective change applied upon new power-on reset by calling + * HAL_SYSCFG_EnablePowerOnReset() and NVIC_SystemReset() + * @param DtcmSize DTCM memory size + * This parameter can one of the following values: + * @arg SYSCFG_DTCM_128K 128K + * @arg SYSCFG_DTCM_256K 256K + * @param ItcmSize ITCM memory size + * This parameter can one of the following values: + * @arg SYSCFG_ITCM_64K 64K + * @arg SYSCFG_ITCM_128K 128K + * @arg SYSCFG_ITCM_256K 256K + * @retval None + */ +void HAL_SYSCFG_SetTCMSize(uint32_t DtcmSize, uint32_t ItcmSize) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DTCM_SIZE(DtcmSize)); + assert_param(IS_SYSCFG_ITCM_SIZE(ItcmSize)); + + MODIFY_REG(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_CFGDTCMSZ | SYSCFG_CM55TCMCR_CFGITCMSZ, DtcmSize | ItcmSize); +} + +/** + * @brief Get the DTCM and ITCM memory sizes. + * @param pDtcmSize Pointer to return DTCM memory size + * This return value can be one of + * @arg SYSCFG_DTCM_128K 128K + * @arg SYSCFG_DTCM_256K 256K + * @param pItcmSize Pointer to return ITCM memory size + * This return value can be one of + * @arg SYSCFG_ITCM_64K 64K + * @arg SYSCFG_ITCM_128K 128K + * @arg SYSCFG_ITCM_256K 256K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetTCMSize(uint32_t *pDtcmSize, uint32_t *pItcmSize) +{ + uint32_t values; + + /* Check null pointer */ + if ((pDtcmSize == NULL) || (pItcmSize == NULL)) + { + return HAL_ERROR; + } + + values = READ_REG(SYSCFG->CM55TCMCR); + *pDtcmSize = (values & 0xF0U); + *pItcmSize = (values & 0xFU); + + return HAL_OK; +} + +/** + * @brief Lock the SYSCFG write access item(s). + * @note Lock(s) cleared only at system reset + * @param Item Item(s) to set lock on. + * This parameter can be a combination of @ref SYSCFG_WRITE_access + * @retval None + */ +void HAL_SYSCFG_LockWriteAccess(uint32_t Item) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_LOCK_WRACCESS(Item)); + + MODIFY_REG(SYSCFG->CM55TCMCR, SYSCFG_LOCK_WR_ALL, Item); +} + +/** + * @brief Get the lock state of SYSCFG write access item. + * @param pItem pointer to return locked items + * the return value can be a combination of @ref SYSCFG_WRITE_access + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetLockWriteAccess(uint32_t *pItem) +{ + /* Check null pointer */ + if (pItem == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + *pItem = READ_BIT(SYSCFG->CM55TCMCR, SYSCFG_LOCK_WR_ALL); + + return HAL_OK; +} + +/** + * @brief Enable the ITCM Wait State. + * @retval None + */ +void HAL_SYSCFG_EnableITCMWaiteState(void) +{ + SET_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_ITCMWSDISABLE); +} + +/** + * @brief Disable the ITCM Wait State. + * @retval None + */ +void HAL_SYSCFG_DisableITCMWaiteState(void) +{ + CLEAR_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_ITCMWSDISABLE); +} + +/** + * @brief Enable the DTCM Wait State. + * @retval None + */ +void HAL_SYSCFG_EnableDTCMWaiteState(void) +{ + SET_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_DTCMWSDISABLE); +} + +/** + * @brief Disable the DTCM Wait State. + * @retval None + */ +void HAL_SYSCFG_DisableDTCMWaiteState(void) +{ + CLEAR_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_DTCMWSDISABLE); +} + +/** + * @brief Enable external RW margin inputs for TCM memories + * @retval None + */ +void HAL_SYSCFG_EnableTCMExternalMargin(void) +{ + SET_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_TCM); +} + +/** + * @brief Disable external RW margin inputs for TCM memories + * @retval None + */ +void HAL_SYSCFG_DisableTCMExternalMargin(void) +{ + CLEAR_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_TCM); +} + +/** + * @brief Set external RW margin inputs for TCM memories. + * @param TcmRwMarginInput Input Margin. + * @retval None + */ +void HAL_SYSCFG_SetTCMRWMarginInput(uint32_t TcmRwMarginInput) +{ + assert_param(IS_TCM_MARGIN_INPUT(TcmRwMarginInput)); + + MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_TCM, (TcmRwMarginInput << 1U)); +} + +/** + * @brief Get the External RW margin inputs for TCM memories. + * @param pTcmRwMarginInput pointer to return Input Margin. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SYSCFG_GetTCMRWMarginInput(uint32_t *pTcmRwMarginInput) +{ + /* Check null pointer */ + if (pTcmRwMarginInput == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + *pTcmRwMarginInput = (READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_TCM) >> 1U); + + return HAL_OK; +} + +/** + * @brief Set the TCM biasing level adjust input. + * @param Level Biaising level adjust input + * This parameter can one of the following values: + * @arg SYSCFG_TCM_BIAS_VNOM : Biasing level adjust input recommended for Vnom + * @arg SYSCFG_TCM_BIAS_VNOM_10_PERCENT : Biasing level adjust input recommended for Vnom + 10% + * @retval None + */ +void HAL_SYSCFG_SetTCMBiasingLevel(uint32_t Level) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_TCM_BIASING_LEVEL(Level)); + + MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_TCM | SYSCFG_CM55RWMCR_BC1_TCM, Level); +} + +/** + * @brief Get the TCM biasing level adjust input. + * @param pLevel Pointer to return biasing level adjust input. + * The return value can be one of the following values: + * @arg SYSCFG_CACHE_BIAS_VNOM boot 0 pin: Biasing level adjust input recommended for Vnom + * @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10% + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetTCMBiasingLevel(uint32_t *pLevel) +{ + /* Check null pointer */ + if (pLevel == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + *pLevel = READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_TCM | SYSCFG_CM55RWMCR_BC1_TCM); + + return HAL_OK; +} + +/** + * @brief Enable external RW margin inputs for Cache memories + * @retval None + */ +void HAL_SYSCFG_EnableCacheExternalMargin(void) +{ + SET_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_CACHE); +} + +/** + * @brief Disable external RW margin inputs for Cache memories + * @retval None + */ +void HAL_SYSCFG_DisableCacheExternalMargin(void) +{ + CLEAR_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_CACHE); +} + +/** + * @brief Set External RW margin inputs for Cache memories. + * @param CacheRWMarginInput Input Margin. + * @retval None + */ +void HAL_SYSCFG_SetCacheRWMarginInput(uint32_t CacheRWMarginInput) +{ + assert_param(IS_TCM_MARGIN_INPUT(CacheRWMarginInput)); + + MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_CACHE, (CacheRWMarginInput << 8U)); +} + +/** + * @brief Get the External RW margin inputs for Cache memories. + * @param pCacheRWMarginInput Pointer to return Input Margin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetCacheRWMarginInput(uint32_t *pCacheRWMarginInput) +{ + /* Check null pointer */ + if (pCacheRWMarginInput == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + *pCacheRWMarginInput = (READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_CACHE) >> 8U); + + return HAL_OK; +} + +/** + * @brief Set the Cache biasing level adjust input. + * @param Level the biaising level adjust input + * This parameter can one of the following values: + * @arg SYSCFG_CACHE_BIAS_VNOM: Biasing level adjust input recommended for Vnom + * @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10% + * @retval None + */ +void HAL_SYSCFG_SetCacheBiasingLevel(uint32_t Level) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_CACHE_BIASING_LEVEL(Level)); + + MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_CACHE | SYSCFG_CM55RWMCR_BC1_CACHE, Level); +} + +/** + * @brief Get the Cache biasing level adjust input. + * @param pLevel Pointer to return Cache biasing level adjust input. + * The return value can be onr of the following values: + * @arg SYSCFG_CACHE_BIAS_VNOM boot: Biasing level adjust input recommended for Vnom + * @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10% + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetCacheBiasingLevel(uint32_t *pLevel) +{ + /* Check null pointer */ + if (pLevel == NULL) + { + return HAL_ERROR; + } + + /* Get the cache biaising */ + *pLevel = READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_CACHE | SYSCFG_CM55RWMCR_BC1_CACHE); + + return HAL_OK; +} + +/** + * @brief Set the secure vector table (VTOR) address. + * @note Secure vector table address must be set to ensure return from STANDBY state. + * @param Address Secure VTOR address + * @retval None + */ +void HAL_SYSCFG_SetSVTORAddress(uint32_t Address) +{ + /* Check the parameters */ + assert_param(IS_VTOR_ADDRESS(Address)); + + WRITE_REG(SYSCFG->INITSVTORCR, Address); +} + +/** + * @brief Get the secure vector table (VTOR) address. + * @param pAddress Pointer to return the secure vector table address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetSVTORAddress(uint32_t *pAddress) +{ + /* Check null pointer */ + if (pAddress == NULL) + { + return HAL_ERROR; + } + + /* Get the secure VTOR address */ + *pAddress = READ_REG(SYSCFG->INITSVTORCR); + + return HAL_OK; +} + +/** + * @brief Set the non secure vector table (VTOR) address. + * @param Address Non-secure VTOR address + * @retval None + */ +void HAL_SYSCFG_SetNSVTORAddress(uint32_t Address) +{ + /* Check the parameters */ + assert_param(IS_VTOR_ADDRESS(Address)); + + WRITE_REG(SYSCFG->INITNSVTORCR, Address); +} + +/** + * @brief Get the non secure VTOR address. + * @param pAddress Pointer to return the non-secure vector table address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetNSVTORAddress(uint32_t *pAddress) +{ + /* Check null pointer */ + if (pAddress == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure VTOR address */ + *pAddress = READ_REG(SYSCFG->INITNSVTORCR); + + return HAL_OK; +} + +/** + * @brief Enable the Power-on reset. + * @note Select power-on reset to apply on core upon SYSRESETREQ (NVIC_SystemReset()) + * @retval None + */ +void HAL_SYSCFG_EnablePowerOnReset(void) +{ + SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_CORE_RESET_TYPE); +} + +/** + * @brief Disable the Power-on reset. + * @note Select warm reset to apply on core upon SYSRESETREQ (NVIC_SystemReset()) + * @retval None + */ +void HAL_SYSCFG_DisablePowerOnReset(void) +{ + CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_CORE_RESET_TYPE); +} + +/** + * @brief Enable Lockup requests a warm reset to the RCC. + * @note Select action to perform on a lockup state on the core + * @retval None + */ +void HAL_SYSCFG_EnableLockupWarmResetonRCC(void) +{ + SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_RST_EN); +} + +/** + * @brief Disable Lockup requests a warm reset to the RCC. + * @note Select action to perform on a lockup state on the core + * @retval None + */ +void HAL_SYSCFG_DisableLockupWarmResetonRCC(void) +{ + CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_RST_EN); +} + +/** + * @brief Enable Lockup generates a NMI on the core. + * @note Select action to perform on a lockup state on the core + * @retval None + */ +void HAL_SYSCFG_EnableLockupGenerateNMI(void) +{ + SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_NMI_EN); +} + +/** + * @brief Disable Lockup generates a NMI on the core. + * @note Select action to perform on a lockup state on the core + * @retval None + */ +void HAL_SYSCFG_DisableLockupGenerateNMI(void) +{ + CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_NMI_EN); +} + +/** + * @brief Enable the capture mechanism upon write posting buffer error. + * @note Upon error detection, the erroneous address is logged on and + * the capture mechanism is on hold. + * The address error can be read thanks to + * HAL_SYSCFG_GetAddressWritePostingBuffer. + * @note This function enables the error capture mechanism again. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SYSCFG_ReEnableWritePostingErrorCapture(void) +{ + /* Re-enable HW write posting detection mechanism */ + SET_BIT(SYSCFG->CM55PAHBWPR, SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK); + + CLEAR_BIT(SYSCFG->CM55PAHBWPR, SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK); + + return HAL_OK; +} + +#if defined(VENC) +/** + * @brief Reserve the VENCRAM allocation to VENC. + * @retval None + */ +void HAL_SYSCFG_EnableVENCRAMReserved(void) +{ + CLEAR_BIT(SYSCFG->VENCRAMCR, SYSCFG_VENCRAMCR_VENCRAM_EN); +} + +/** + * @brief Release the VENCRAM allocation to VENC (any use allowed). + * @retval None + */ +void HAL_SYSCFG_DisableVENCRAMReserved(void) +{ + SET_BIT(SYSCFG->VENCRAMCR, SYSCFG_VENCRAMCR_VENCRAM_EN); +} + +#endif /* VENC */ + +/** + * @brief Enable PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper + * @retval None + */ +void HAL_SYSCFG_EnableCRYPPotentialTamper(void) +{ + CLEAR_BIT(SYSCFG->POTTAMPRSTCR, SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK); +} + +/** + * @brief Disable PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper + * @retval None + */ +void HAL_SYSCFG_DisableCRYPPotentialTamper(void) +{ + SET_BIT(SYSCFG->POTTAMPRSTCR, SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK); +} + +#if defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR) +/** + * @brief Set write QoS information for master port from NP1 NPUNIC + * @param QosValue Write QoS value (0 to 15). + * @retval None + */ +void HAL_SYSCFG_SetWriteQosNP1(uint32_t QosValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_QOS_CPU(QosValue)); + + MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSW, QosValue << 4U); +} + +/** + * @brief Get write QoS information for master port from NP1 NPUNIC + * @param pQosValue Pointer to return write QOS value (0 to 15) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP1(uint32_t *pQosValue) +{ + /* Check null pointer */ + if (pQosValue == NULL) + { + return HAL_ERROR; + } + + /* Get the QOS */ + *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSW) >> 4U); + + return HAL_OK; +} + +/** + * @brief Set read QoS information for master port from NP1 NPUNIC + * @param QosValue Read QoS value (0 to 15) + * @retval None + */ +void HAL_SYSCFG_SetReadQosNP1(uint32_t QosValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_QOS_CPU(QosValue)); + + MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSR, QosValue); +} + +/** + * @brief Get read QoS information for master port from NP1 NPUNIC + * @param pQosValue Pointer to return read QOS value (0 to 15) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP1(uint32_t *pQosValue) +{ + /* Check null pointer */ + if (pQosValue == NULL) + { + return HAL_ERROR; + } + + /* Get the QOS */ + *pQosValue = READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSR); + + return HAL_OK; +} + +/** + * @brief Set write QoS information for master port from NP2 NPUNIC + * @param QosValue Write Qos value (0 to 15) + * @retval None + */ +void HAL_SYSCFG_SetWriteQosNP2(uint32_t QosValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_QOS_CPU(QosValue)); + + MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSW, QosValue << 12U); +} + +/** + * @brief Get write QoS information for master port from NP2 NPUNIC + * @param pQosValue Pointer to return write QOS value (0 to 15) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP2(uint32_t *pQosValue) +{ + /* Check null pointer */ + if (pQosValue == NULL) + { + return HAL_ERROR; + } + + /* Get the QOS */ + *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSW) >> 12U); + + return HAL_OK; +} + +/** + * @brief Set read QoS information for master port from NP2 NPUNIC + * @param QosValue Read Qos value (0 to 15) + * @retval None + */ +void HAL_SYSCFG_SetReadQosNP2(uint32_t QosValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_QOS_CPU(QosValue)); + + MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSR, QosValue << 8U); +} + +/** + * @brief Get read QoS information for master port from NP2 NPUNIC + * @param pQosValue Pointer to return read QOS value (0 to 15) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP2(uint32_t *pQosValue) +{ + /* Check null pointer */ + if (pQosValue == NULL) + { + return HAL_ERROR; + } + + /* Get the QOS */ + *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSR) >> 8U); + + return HAL_OK; +} + +/** + * @brief Set write QoS information for master port from CPUSS NPUNIC + * @param QosValue Write QoS value (0 to 15) + * @retval None + */ +void HAL_SYSCFG_SetWriteQosCPUSS(uint32_t QosValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_QOS_CPU(QosValue)); + + MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW, QosValue << 20U); +} + +/** + * @brief Get write QoS information for master port from CPUSS NPUNIC + * @param pQosValue Pointer to return write QOS value (0 to 15) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetwriteQosCPUSS(uint32_t *pQosValue) +{ + /* Check null pointer */ + if (pQosValue == NULL) + { + return HAL_ERROR; + } + + /* Get the QOS */ + *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW) >> 20U); + + return HAL_OK; +} + +/** + * @brief Set read QoS information for master port from CPUSS NPUNIC + * @param QosValue Read QoS value (0 to 15) + * @retval None + */ +void HAL_SYSCFG_SetReadQosCPUSS(uint32_t QosValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_QOS_CPU(QosValue)); + + MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR, QosValue << 16U); +} + +/** + * @brief Get read QoS information for master port from CPUSS NPUNIC + * @param pQosValue Pointer to return read QOS value (0 to 15) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetReadQosCPUSS(uint32_t *pQosValue) +{ + /* Check null pointer */ + if (pQosValue == NULL) + { + return HAL_ERROR; + } + + /* Get the QOS */ + *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR) >> 16U); + + return HAL_OK; +} +#endif /* defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR) */ + +/** + * @brief Enable SDMMC early-write response. + * @param Sdmmc Selected SDMMC instance(s). + * This parameter can be a one of @ref SYSCFG_SDMMCId + * @retval None + */ +void HAL_SYSCFG_EnableSDMMCEarlyWRRESP(uint32_t Sdmmc) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_SDMMC(Sdmmc)); + + SET_BIT(SYSCFG->ICNEWRCR, Sdmmc); +} + +/** + * @brief Disable SDMMC early-write response. + * @param Sdmmc Selected SDMMC instance(s). + * This parameter can be a one of @ref SYSCFG_SDMMCId + * @retval None + */ +void HAL_SYSCFG_DisableSDMMCEarlyWRRSP(uint32_t Sdmmc) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_SDMMC(Sdmmc)); + + CLEAR_BIT(SYSCFG->ICNEWRCR, Sdmmc); +} + +/** + * @brief Enable USB early-write response. + * @param Usb Selected USB instance(s). + * This parameter can be a one of @ref SYSCFG_USBId + * @retval None + */ +void HAL_SYSCFG_EnableUSBEarlyEarlyWRRESP(uint32_t Usb) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_USB(Usb)); + + SET_BIT(SYSCFG->ICNEWRCR, Usb); +} + +/** + * @brief Disable USB early-write response. + * @param Usb Selected USB instance(s). + * This parameter can be a one of @ref SYSCFG_USBId + * @retval None + */ +void HAL_SYSCFG_DisableUSBEarlyEarlyWRRESP(uint32_t Usb) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_USB(Usb)); + + CLEAR_BIT(SYSCFG->ICNEWRCR, Usb); +} + +/** + * @brief Enable xPU clock gating. + * @param Xpu Selected CPU(s). + * This parameter can be a one of @ref SYSCFG_XPUId + * @retval None + */ +void HAL_SYSCFG_EnablexPUClockGating(uint32_t Xpu) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_CPU_CLK_GATING(Xpu)); + + SET_BIT(SYSCFG->ICNCGCR, Xpu); +} + +/** + * @brief Disable xPU clock gating. + * @param Xpu Selected CPU(s). + * This parameter can be a one of @ref SYSCFG_XPUId + * @retval None + */ +void HAL_SYSCFG_DisablexPUClockGating(uint32_t Xpu) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_CPU_CLK_GATING(Xpu)); + + CLEAR_BIT(SYSCFG->ICNCGCR, Xpu); +} + +/** + * @brief Enable the VDDIO2 compensation cell. + * @note This function is deprecated, please refer to Errata Sheet ES0620. + * I/O compensation cells must remain disabled. + * @retval None + */ +void HAL_SYSCFG_EnableVDDIO2CompensationCell(void) +{ + SET_BIT(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_EN); +} + +/** + * @brief Disable the VDDIO2 compensation cell. + * @retval None + */ +void HAL_SYSCFG_DisableVDDIO2CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_EN); +} + +/** + * @brief Enable the VDDIO3 compensation cell. + * @note This function is deprecated, please refer to Errata Sheet ES0620. + * I/O compensation cells must remain disabled. + * @retval None + */ +void HAL_SYSCFG_EnableVDDIO3CompensationCell(void) +{ + SET_BIT(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_EN); +} + +/** + * @brief Disable the VDDIO3 compensation cell. + * @retval None + */ +void HAL_SYSCFG_DisableVDDIO3CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_EN); +} + +/** + * @brief Enable the VDDIO4 compensation cell. + * @note This function is deprecated, please refer to Errata Sheet ES0620. + * I/O compensation cells must remain disabled. + * @retval None + */ +void HAL_SYSCFG_EnableVDDIO4CompensationCell(void) +{ + SET_BIT(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_EN); +} + +/** + * @brief Disable the VDDIO4 compensation cell. + * @retval None + */ +void HAL_SYSCFG_DisableVDDIO4CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_EN); +} + +/** + * @brief Enable the VDDIO5 compensation cell. + * @note This function is deprecated, please refer to Errata Sheet ES0620. + * I/O compensation cells must remain disabled. + * @retval None + */ +void HAL_SYSCFG_EnableVDDIO5CompensationCell(void) +{ + SET_BIT(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_EN); +} + +/** + * @brief Disable the VDDIO5 compensation cell. + * @retval None + */ +void HAL_SYSCFG_DisableVDDIO5CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_EN); +} + +/** + * @brief Configure the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the VDDIO2 + * @arg SYSCFG_IO_VDDIO3_CELL Compensation cell for the VDDIO3 + * @arg SYSCFG_IO_VDDIO4_CELL Compensation cell for the VDDIO4 + * @arg SYSCFG_IO_VDDIO5_CELL Compensation cell for the VDDIO5 + * @param Code code selection to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR) + * @param NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Nmos value + * to apply in range 0 to 15 else this parameter is not used + * @param PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Pmos value + * to apply in range 0 to 15 else this parameter is not used + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDIOCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, + uint32_t PmosValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code)); + + if (Code == SYSCFG_IO_REGISTER_CODE) + { + /* Check the parameters */ + assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue)); + assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue)); + + /* Reject forbidden Nmos = 0 and Pmos = 15 */ + if ((NmosValue == 0U) || (PmosValue == 0xFU)) + { + status = HAL_ERROR; + } + else + { + switch (Selection) + { + case SYSCFG_IO_VDDIO2_CELL: + { + MODIFY_REG(SYSCFG->VDDIO2CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO2CCCR_CS)); + break; + } + case SYSCFG_IO_VDDIO3_CELL: + { + MODIFY_REG(SYSCFG->VDDIO3CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO3CCCR_CS)); + break; + } + case SYSCFG_IO_VDDIO4_CELL: + { + MODIFY_REG(SYSCFG->VDDIO4CCCR, 0x2FFU, ((NmosValue) | (PmosValue << (4U)) | SYSCFG_VDDIO4CCCR_CS)); + break; + } + case SYSCFG_IO_VDDIO5_CELL: + { + MODIFY_REG(SYSCFG->VDDIO5CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO5CCCR_CS)); + break; + } + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + } + else + { + switch (Selection) + { + + case SYSCFG_IO_VDDIO2_CELL: + { + MODIFY_REG(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_CS, 0U); + break; + } + case SYSCFG_IO_VDDIO3_CELL: + { + MODIFY_REG(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_CS, 0U); + break; + } + case SYSCFG_IO_VDDIO4_CELL: + { + MODIFY_REG(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_CS, 0U); + break; + } + case SYSCFG_IO_VDDIO5_CELL: + { + MODIFY_REG(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_CS, 0U); + break; + } + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + return status; +} + +/** + * @brief Get the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the VDDIO2 + * @arg SYSCFG_IO_VDDIO3_CELL Compensation cell for the VDDIO3 + * @arg SYSCFG_IO_VDDIO4_CELL Compensation cell for the VDDIO4 + * @arg SYSCFG_IO_VDDIO5_CELL Compensation cell for the VDDIO5 + * @param pCode pointer to code selection + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR) + * @param pNmosValue pointer to the Nmos value in range 0 to 15 + * @param pPmosValue pointer to the Pmos value in range 0 to 15 + * @retval HAL_OK (all values available) or HAL_ERROR (check parameters) + */ +HAL_StatusTypeDef HAL_SYSCFG_GetVDDIOCompensationCell(uint32_t Selection, const uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t values = 0; + + /* Check the parameters */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(*pCode)); + + if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL)) + { + status = HAL_OK; + + if (*pCode == SYSCFG_IO_REGISTER_CODE) + { + switch (Selection) + { + case SYSCFG_IO_VDDIO2_CELL: + { + values = READ_REG(SYSCFG->VDDIO2CCCR) & 0xFFU; + break; + } + case SYSCFG_IO_VDDIO3_CELL: + { + values = READ_REG(SYSCFG->VDDIO3CCCR) & 0xFFU; + break; + } + case SYSCFG_IO_VDDIO4_CELL: + { + values = READ_REG(SYSCFG->VDDIO4CCCR) & 0xFFU; + break; + } + case SYSCFG_IO_VDDIO5_CELL: + { + values = READ_REG(SYSCFG->VDDIO5CCCR) & 0xFFU; + break; + } + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + switch (Selection) + { + case SYSCFG_IO_VDDIO2_CELL: + { + values = READ_REG(SYSCFG->VDDIO2CCSR) & 0xFFU; + break; + } + case SYSCFG_IO_VDDIO3_CELL: + { + values = READ_REG(SYSCFG->VDDIO3CCSR) & 0xFFU; + break; + } + case SYSCFG_IO_VDDIO4_CELL: + { + values = READ_REG(SYSCFG->VDDIO4CCSR) & 0xFFU; + break; + } + case SYSCFG_IO_VDDIO5_CELL: + { + values = READ_REG(SYSCFG->VDDIO5CCSR) & 0xFFU; + break; + } + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + *pNmosValue = (values & 0xFU); + *pPmosValue = ((values & 0xF0U) >> 4U); + } + return status; +} + +/** + * @brief Get the compensation cell ready status of VDDIO2. + * @retval Ready status (0 (not ready) or !=0 (ready)) + */ +uint32_t HAL_SYSCFG_GetCompVDDIO2CellReadyStatus(void) +{ + return READ_BIT(SYSCFG->VDDIO2CCSR, SYSCFG_VDDIO2CCSR_READY); +} + +/** + * @brief Get the compensation cell ready status of VDDIO3. + * @retval Ready status (0 (not ready) or !=0 (ready)) + */ +uint32_t HAL_SYSCFG_GetCompVDDIO3CellReadyStatus(void) +{ + return READ_BIT(SYSCFG->VDDIO3CCSR, SYSCFG_VDDIO3CCSR_READY); +} + +/** + * @brief Get the compensation cell ready status of VDDIO4. + * @retval Ready status (0 (not ready) or !=0 (ready)) + */ +uint32_t HAL_SYSCFG_GetCompVDDIO4CellReadyStatus(void) +{ + return READ_BIT(SYSCFG->VDDIO4CCSR, SYSCFG_VDDIO4CCSR_READY); +} + +/** + * @brief Get the compensation cell ready status of VDDIO5. + * @retval Ready status (0 (not ready) or !=0 (ready)) + */ +uint32_t HAL_SYSCFG_GetCompVDDIO5CellReadyStatus(void) +{ + return READ_BIT(SYSCFG->VDDIO5CCSR, SYSCFG_VDDIO5CCSR_READY); +} + +/** + * @brief Configure the code selection for the compensation cell of VDD + * @param Code code selection to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR) + * @param NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Nmos value + * to apply in range 0 to 15 else this parameter is not used + * @param PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Pmos value + * to apply in range 0 to 15 else this parameter is not used + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDCompensationCell(uint32_t Code, uint32_t NmosValue, uint32_t PmosValue) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code)); + + if (Code == SYSCFG_IO_REGISTER_CODE) + { + /* Check the parameters */ + assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue)); + assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue)); + + MODIFY_REG(SYSCFG->VDDCCCR, 0xFFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDCCCR_CS)); + + status = HAL_OK; + } + else + { + MODIFY_REG(SYSCFG->VDDCCCR, 0x200U, 0U); + status = HAL_OK; + } + return status; +} + +/** + * @brief Enable the VDD compensation cell. + * @note This function is deprecated, please refer to Errata Sheet ES0620. + * I/O compensation cells must remain disabled. + * @retval None + */ +void HAL_SYSCFG_EnableVDDCompensationCell(void) +{ + SET_BIT(SYSCFG->VDDCCCR, SYSCFG_VDDCCCR_EN); +} + +/** + * @brief Disable the VDD compensation cell. + * @retval None + */ +void HAL_SYSCFG_DisableVDDCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->VDDCCCR, SYSCFG_VDDCCCR_EN); +} + +/** + * @brief Get the code selection for the compensation cell of VDD + * @param Code code selection + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR) + * @param pNmosValue pointer to the Nmos value in range 0 to 15 + * @param pPmosValue pointer to the Pmos value in range 0 to 15 + * @retval HAL_OK (all values available) or HAL_ERROR (check parameters) + */ +HAL_StatusTypeDef HAL_SYSCFG_GetVDDCompensationCell(uint32_t Code, uint32_t *pNmosValue, + uint32_t *pPmosValue) +{ + uint32_t values; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code)); + + if ((pNmosValue != NULL) && (pPmosValue != NULL)) + { + if (Code == SYSCFG_IO_REGISTER_CODE) + { + values = READ_REG(SYSCFG->VDDCCCR) & 0xFFU; + } + else + { + values = READ_REG(SYSCFG->VDDCCSR) & 0xFFU; + } + + *pNmosValue = (values & 0xFU); + *pPmosValue = ((values >> 4U) & 0xFU); + + status = HAL_OK; + } + return status; +} + +/** + * @brief Get the compensation cell ready status of VDD. + * @retval Ready status (0 (not ready) or !=0 (ready)) + */ +uint32_t HAL_SYSCFG_GetCompensationVDDCellReadyStatus(void) +{ + return READ_BIT(SYSCFG->VDDCCSR, SYSCFG_VDDCCSR_READY); +} + +/** + * @brief Configure the Timer Break input for error flag(s). + * @note When a configuration is set, only a system reset can reset it. + * @param Input Input configuration + * This parameter can be one or a combination of the following values: + * @arg SYSCFG_CBR_BREAK_LOCK_CORE Cortex-CM55 lockup + * @arg SYSCFG_CBR_BREAK_LOCK_PVD PVD lock + * @arg SYSCFG_CBR_BREAK_LOCK_BKPRAM Backup SRAM ECC error + * @arg SYSCFG_CBR_BREAK_LOCK_CM55_CACHE CM55 cache double ECC error + * @arg SYSCFG_CBR_BREAK_LOCK_CM55_TCM DTCM double ECC error + * @retval None + */ +void HAL_SYSCFG_ConfigTimerBreakInput(uint32_t Input) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CBR_BREAK_INPUT(Input)); + + MODIFY_REG(SYSCFG->CBR, Input, Input); +} + +/** + * @brief Get the Timer Break input configuration. + * @note When a configuration is set, only a system reset can reset it. + * @retval Timer break input configuration + * This return value can be one or a combination of the following values: + * @arg SYSCFG_CBR_BREAK_LOCK_CORE Cortex-CM55 lockup + * @arg SYSCFG_CBR_BREAK_LOCK_PVD PVD lock + * @arg SYSCFG_CBR_BREAK_LOCK_BKPRAM Backup SRAM ECC error + * @arg SYSCFG_CBR_BREAK_LOCK_CM55_CACHE CM55 cache double ECC error + * @arg SYSCFG_CBR_BREAK_LOCK_CM55_TCM DTCM double ECC error + */ +uint32_t HAL_SYSCFG_GetTimerBreakInputConfig(void) +{ + return (SYSCFG->CBR & SYSCFG_CBR_BREAK_LOCK_ALL); +} + +/** + * @brief Set the perceived CID of the peripheral. + * @note Set the perceived CID so that all accesses which arrive at the peripheral + * (here HPDMA) appear to carry that CID. + * See Multi-tenancy section of the reference manual for further information. + * @param Cid CID in range 0 to 7 + * @retval None + */ +void HAL_SYSCFG_SetPerceivedCID(uint32_t Cid) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_DMA_CID_SEC(Cid)); + + MODIFY_REG(SYSCFG->SEC_AIDCR, SYSCFG_SEC_AIDCR_DMACID_SEC, Cid); +} + +/** + * @brief Get the perceived CID of the peripheral. + * @retval CID in range 0 to 7 + */ +uint32_t HAL_SYSCFG_GetPerceivedCID(void) +{ + return (SYSCFG->SEC_AIDCR & SYSCFG_SEC_AIDCR_DMACID_SEC); +} + +/** + * @brief Set the perceived CID of the peripheral as privileged. + * @note Set the perceived CID so that all accesses which arrive at the peripheral + * (here HPDMA) appear to carry that CID. + * This function shall be called in case of DMA channel interrupt (privileged) code + * to read the registers and clear the interrupt of this DMA channel. + * See Multi-tenancy section of the reference manual for forther information. + * @param Cid in range 0 to 7 + * @retval None + */ +void HAL_SYSCFG_SetPerceivedPrivCID(uint32_t Cid) +{ + MODIFY_REG(SYSCFG->SECPRIV_AIDCR, SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC, Cid); +} + +/** + * @brief Get the perceived CID of the peripheral as privileged. + * @retval CID in range 0 to 7 + */ +uint32_t HAL_SYSCFG_GetPerceivedPrivCID(void) +{ + return (SYSCFG->SECPRIV_AIDCR & SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC); +} + +/** + * @brief Enable Retiming on RX path. + * @retval None + */ +void HAL_SYSCFG_EnableReTimingRXpath(void) +{ + SET_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_RX); +} + +/** + * @brief Disable Retiming on RX path. + * @retval None + */ +void HAL_SYSCFG_DisableReTimingRXpath(void) +{ + CLEAR_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_RX); +} + +/** + * @brief Enable Retiming on TX path. + * @retval None + */ +void HAL_SYSCFG_EnableReTimingTXpath(void) +{ + SET_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_TX); +} + +/** + * @brief Disable Retiming on TX path. + * @retval None + */ +void HAL_SYSCFG_DisableReTimingTXpath(void) +{ + CLEAR_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_TX); +} + +/** + * @brief Set delay on feedback clock. + * @param Delay Delay on feedback clock + * @arg SYSCFG_DELAY_FEEDBACK_NONE None + * @arg SYSCFG_DELAY_FEEDBACK_HALF_CYCLE Half a cycle delay + * @retval None + */ +void HAL_SYSCFG_SetDelayOnFeedbackClock(uint32_t Delay) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_DMA_DELAY_FEEDBACK_CLOCK(Delay)); + + MODIFY_REG(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_SDFBCLK_180, Delay); +} + +/** + * @brief Get delay on feedback clock. + * @retval Delay on feedback clock + * @arg SYSCFG_DELAY_FEEDBACK_NONE None + * @arg SYSCFG_DELAY_FEEDBACK_HALF_CYCLE Half a cycle delay + */ +uint32_t HAL_SYSCFG_GetDelayOnFeedbackClock(void) +{ + return (SYSCFG->FMC_RETIMECR & SYSCFG_FMC_RETIMECR_SDFBCLK_180); +} + +#if defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR) +/** + * @brief Enable the interleaving on NPU RAM. + * @retval None + */ +void HAL_SYSCFG_EnableInterleavingCpuRam(void) +{ + SET_BIT(SYSCFG->NPU_ICNCR, SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE); +} + +/** + * @brief Disable the interleaving on NPU RAM. + * @retval None + */ +void HAL_SYSCFG_DisableInterleavingCpuRam(void) +{ + CLEAR_BIT(SYSCFG->NPU_ICNCR, SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE); +} +#endif /* SYSCFG_NPUNICQOSCR_NPU1_ARQOSR */ + +/** + * @brief Get BOOT pin connection status + * @param BootId specifies the boot pins. + * @retval BOOT pin connection configuration + * This return value can be one of the following values: + * @arg SYSCFG_BOOT_CONNECTION_VSS pin connected to VSS + * @arg SYSCFG_BOOT_CONNECTION_VDD pin connected to VDD + */ +uint32_t HAL_SYSCFG_GetBootPinConnection(uint32_t BootId) +{ + uint32_t Connection; + + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_ID(BootId)); + + Connection = READ_BIT(SYSCFG->BOOTSR, BootId); + + if (BootId == SYSCFG_BOOTCR_BOOT0_PD) + { + return Connection; + } + else + { + return (Connection >> 1U); + } +} + +/** + * @brief Get address of first error in P-AHB write-posting buffer + * @retval Address of the first error in P-AHB write-posting buffer + */ +uint32_t HAL_SYSCFG_GetAddressWritePostingBuffer(void) +{ + return READ_BIT(SYSCFG->AHBWP_ERROR_SR, SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group5 HAL FMC configuration functions + * @brief HAL FMC configuration functions + * +@verbatim + =============================================================================== + ##### HAL FMC configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the FMC Memory Bank Swapping mode + (+) Get current FMC Memory Bank Swapping Mode used +@endverbatim + * @{ + */ + +/** + * @brief Set the FMC Memory Bank Swapping mode. + * @param BankMapConfig specifies the FMC Memory Bank Swapping mode to configure + * This parameter can be one of the following values: + * @arg FMC_SWAPBANK_MODE0 : FMC memory default mapping is used + * @arg FMC_SWAPBANK_MODE1 : NOR/SRAM/PSRAM bank and SDRAM bank1 are swapped + * @note FMC bank mapping options + * | Start-End address | FMC_SWAPBANK_MODE0 | FMC_SWAPBANK_MODE1 | + * |-----------------------|---------------------|---------------------| + * | 0x60000000-0x6FFFFFFF | NOR/SRAM/PSRAM bank | SDRAM bank1 | + * | 0xC0000000-0xCFFFFFFF | SDRAM bank1 | NOR/SRAM/PSRAM bank | + * | 0xD0000000-0xDFFFFFFF | SDRAM bank2 | SDRAM bank2 | + * @retval None + */ +void HAL_FMC_SetBankSwapConfig(uint32_t BankMapConfig) +{ + /* Check the parameter */ + assert_param(IS_FMC_SWAPBANK_MODE(BankMapConfig)); + + /* Apply Memory Bank Swapping configuration */ + MODIFY_REG(FMC_Common_R->CFGR, FMC_CFGR_BMAP, BankMapConfig); +} + +/** + * @brief Get the FMC Memory Bank Swapping mode. + * @retval Return value is FMC Memory Bank Swapping mode + * This return value can be one of the following values: + * @arg FMC_SWAPBANK_MODE0 : FMC memory default mapping is used + * @arg FMC_SWAPBANK_MODE1 : NOR/SRAM/PSRAM bank and SDRAM bank1 are swapped + */ +uint32_t HAL_FMC_GetBankSwapConfig(void) +{ + return READ_BIT(FMC_Common_R->CFGR, FMC_CFGR_BMAP); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c (revision 16) @@ -0,0 +1,788 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M55 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure SysTick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32n6xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + [..] + *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** + ============================================================================ + [..] + This section provides functions allowing to configure both secure and non-secure MPUs. + + (#) Enable the MPU using HAL_MPU_Enable() function. + (#) Disable the MPU using HAL_MPU_Disable() function. + (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. + (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. + (#) Configure the MPU region using HAL_MPU_ConfigRegion() + and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. + (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() + and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. + + A device memory has the following attributes: + (#) G or nG: gathering or non-gathering. (multiple accesses to a device can be merged into a single + transaction except for operations with memory ordering semantics, for example, memory barrier + instructions, load acquire/store release). + (#) R or nR: reordering + (#) E or nE: early write acknowledge (similar to bufferable) + + Only four combinations of these attributes are valid: + (#) device-nGnRnE: equivalent to Armv7-M strongly ordered memory type + (#) device-nGnRE: equivalent to Armv7-M device memory + (#) device-nGRE: new to Armv8-M + (#) device-GRE: new to Armv8-M + + A normal memory has the following attributes: + (#) Cache Allocation attribute : set when a cache line is allocated (no allocation, read/write/read-write allocation) + (#) Cache write policy : write through (write to cache AND memory), write back (memory is written when the cache line is evicted) + (#) Transient : indicates that the region will be used for a short period of time + For normal memory, attributes can be set for inner and outer caches separately. + Note that outer attributes set to 0 change the memory to device mode. Both inner and outer attributes should be set for normal memory. + + Sample configurations + (#) Inner-outer cacheable, write back, read-write allocate INNER_OUTER(MPU_RW_ALLOCATE | MPU_WRITE_BACK) + (#) Inner write back, read allocation, outer non-cacheable (MPU_R_ALLOCATE | MPU_WRITE_BACK) | OUTER(MPU_NOT_CACHEABLE) + For detail on memory attributes, refer to the ARMv8-m MPU documentation. + + On STM32N6xx, the MPUs are split memory into regions (up to sixteen for both Secure and Non-Secure domains) + The secure MPU is only available when TrustZone is activated. + + (#) Enable the MPU using HAL_MPU_Enable() function or HAL_MPU_Enable_NS function for non-secure MPU. + (#) Disable the MPU using HAL_MPU_Disable() function or HAL_MPU_Disable_NS function for non-secure MPU. + (#) Enable the MPU region using HAL_MPU_EnableRegion() function or HAL_MPU_EnableRegion_NS function for non-secure MPU region. + (#) Disable the MPU region using HAL_MPU_DisableRegion() function or HAL_MPU_DisableRegion_NS function for non-secure MPU region. + (#) Configure the MPU region using HAL_MPU_ConfigRegion() function or HAL_MPU_ConfigRegion_NS function + for non-secure MPU. + (#) Configure the MPU memory attributes using HAL_MPU_ConfigMemoryAttributes() function or + HAL_MPU_ConfigMemoryAttributes_NS function for non-secure MPU. + + (#) The HAL_MPU_XXX_NS functions are only available when TrustZone is activated and CPU in secure state. + _NS functions are targeting non secure MPU, in any other cases APIs without NS shall be used. + + @endverbatim + ****************************************************************************** + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bit for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bit for subpriority + ========================================================================================================================== + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Functions CORTEX Private Functions + * @{ + */ +static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_RegionInit); +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *pMPU_AttributesInit); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + SysTick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Set the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority, + * 0 bit for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Set the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @param PreemptPriority The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_INTERRUPT(IRQn)); + + prioritygroup = (NVIC_GetPriorityGrouping() & 0x7U); + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup)); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +__NO_RETURN void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Get the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority, + * 0 bit for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_INTERRUPT(IRQn)); + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32n6xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8 AHB clock divided by 8 selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + + MODIFY_REG(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk, CLKSource); +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @brief Clear pending event(s). + * @retval None + */ +void HAL_CORTEX_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Force any outstanding transfers to complete before enabling MPU */ + + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Enable the non-secure MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Force any outstanding transfers to complete before enabling MPU */ + + /* Enable the MPU */ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Disable the non-secure MPU. + * @retval None + */ +void HAL_MPU_Disable_NS(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Enable the non-secure MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) +{ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Disable the non-secure MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* CPU_IN_SECURE_STATE */ + + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit) +{ + MPU_ConfigRegion(MPU, pMPU_RegionInit); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU. + * @param pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *pMPU_RegionInit) +{ + MPU_ConfigRegion(MPU_NS, pMPU_RegionInit); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Initialize and configure the memory attributes. + * @param pMPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit); +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Initialize and configure the memory attributes for non-secure MPU. + * @param pMPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit); +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CORTEX_Private_Functions + * @{ + */ +static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_RegionInit) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); + assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); + + /* Set the Region number */ + MPUx->RNR = pMPU_RegionInit->Number; + + /* Disable the Region */ + CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk); + + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_PRIV_INSTRUCTION_ACCESS(pMPU_RegionInit->DisablePrivExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); + assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_RegionInit->AttributesIndex)); + + MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->DisablePrivExec << MPU_RLAR_PXN_Pos) | + ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); +} + +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *pMPU_AttributesInit) +{ + __IO uint32_t *p_mair; + uint32_t attr_values; + uint32_t attr_number; + + /* Check the parameters */ + assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number)); + /* No need to check Attributes value as all 0x0..0xFF possible */ + + if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + p_mair = &(MPUx->MAIR0); + attr_number = pMPU_AttributesInit->Number; + } + else + { + /* Program MPU_MAIR1 */ + p_mair = &(MPUx->MAIR1); + attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U; + } + + attr_values = *(p_mair); + attr_values &= ~(0xFFU << (attr_number * 8U)); + *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U)); +} + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c (revision 16) @@ -0,0 +1,1812 @@ +/** + ********************************************************************************************************************** + * @file stm32n6xx_hal_dma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access + * (DMA) peripheral: + * + Initialization/De-Initialization Functions + * + I/O Operation Functions + * + State and Errors Functions + * + DMA Attributes Functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + (#) GPDMA and HPDMA are made available on this series. + Transfer could be done thanks to AXI or AHB ports. + + HPDMA support transmission through: + AXI port 0. + AHB port 1. + GPDMA allows transmission through: + GPDMA_P = port-0. + GPDMA_M = port-1 + + The supported configurations for GPDMA and HPDMA can be found + in the Connectivity matrix table of the reference manual. + Mind that DTCM and ITCM can be only be accessed thanks to HPDMA + AXI port 0. + [..] + DMA transfer modes are divided to 2 major categories : + (+) Normal transfers (legacy) + (+) Linked-list transfers + + [..] + Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended + module. + + [..] + Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended + module as extensions to normal mode. + Advanced features are : + (+) Repeated block feature. + (+) Trigger feature. + (+) Data handling feature. + + [..] + DMA Legacy circular transfer, is replaced by circular linked-list configuration. + + + *** Initialization and De-Initialization *** + ============================================ + [..] + For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal + SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between + peripherals and DMA requests. + + [..] + For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through + the following parameters: + + (+) Request : Specifies the DMA channel request + Request parameters : + (++) can be a value of DMA_Request_Selection + + (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel + (++) can be a value of DMA_Block_Request + + (+) Direction : Specifies the transfer direction for DMA channel + (++) can be a value of DMA_Transfer_Direction + + (+) SrcInc : Specifies the source increment mode for the DMA channel + (++) can be a value of DMA_Source_Increment_Mode + + (+) DestInc : Specifies the destination increment mode for the DMA channel + (++) can be a value of DMA_Destination_Increment_Mode + + (+) SrcDataWidth : Specifies the source data width for the DMA channel + (++) can be a value of DMA_Source_Data_Width + + (+) DestDataWidth : Specifies the destination data width for the DMA channel + (++) can be a value of DMA_Destination_Data_Width + + (+) Priority : Specifies the priority for the DMA channel + (++) can be a value of DMA_Priority_Level + + (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) TransferAllocatedPort : Specifies the source and destination allocated ports + (++) can be a value of DMA_Transfer_Allocated_Port + + (+) TransferEventMode : Specifies the transfer event mode for the DMA channel + (++) can be a value of DMA_Transfer_Event_Mode + + (+) Mode : Specifies the transfer mode for the DMA channel + (++) can be one of the following modes : + (+++) DMA_NORMAL : Normal Mode + (+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination + address and the size of data to be transferred. + + (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be + configured by User depending on his application. + Transfer level can be : + (++) HAL_DMA_HALF_TRANSFER + (++) HAL_DMA_FULL_TRANSFER + For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code. + + (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode. + This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA + channel. (This API should not be called from an interrupt service routine) + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + + (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferHalfCpltCallback : half transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + (++) XferSuspendCallback : transfer suspend complete callback. + + (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration + of source address,destination address and the size of data to be transferred. + + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt. + + (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode. + This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended, + an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback + XferAbortCallback. (This API could be called from an interrupt service routine) + + + *** State and errors *** + ======================== + [..] + (+) Use HAL_DMA_GetState() function to get the DMA state. + (+) Use HAL_DMA_GetError() function to get the DMA error code. + + + *** Security and privilege attributes *** + ========================================= + [..] + (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes. + (++) Security : at channel level, at source level and at destination level. + (++) Privilege : at channel level. + (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes. + (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes + configuration. This API can be called once after each system boot. + If called again, HAL_DMA_ConfigChannelAttributes() API has no effect. + Unlock is done either by a system boot or a by an RCC reset. + (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status. + (+) Use HAL_DMA_SetIsolationAttributes() function to configure the HPDMA channel isolation attribute. + (+) Use HAL_DMA_GetIsolationAttributes() function to get the HPDMA channel isolation attribute. + + *** Isolation attributes *** + ================================== + It is recommended to always enable the isolation feature of the DMA (CFEN = 1) of the HPDMA channel. + The default isolation shall be 1. i.e. the Cortex CID. + Indeed, should the isolation bit CFEN be equal to 0, a default isolation CID is still carried out and is 0 (zero). + the CID generated by a channel access is zero-ed when CFEN=0, even if SCID is different from 000. + + Similarly, it is recommended that all RIMU related IP (SDMMC, OTG, ETH, GPU, DMA2D, ...) to always enable and + generate (CID = 1). + + *** DMA HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not. + + *** Valid burst length *** + ================================== + [..] + HPDMA allowed AXI maximum burst length + (+) The maximum allowed AXI burst length shall not exceed 16. + (++) If either selected source or destination length is above 16, HAL_DMA_Init will return HAL_ERROR. + + [..] + (@) You can refer to the header file of the DMA HAL driver for more useful macros. + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +static void DMA_Init(DMA_HandleTypeDef const *const hdma); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Initialization and de-initialization functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. + + [..] + (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual. + (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and + * create the associated handle. + * @note Warning: the maximum allowed AXI burst length shall not exceed 16. + * Otherwise, an error will be returned and no initialization performed. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + } + assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest)); + assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + if (hdma->Init.Mode == DMA_PFCTRL) + { + assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance)); + } + /* Check DMA channel instance */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort)); + } + + /* Check if the burst length may face DMA AXI limitation */ + if (IS_HPDMA_INSTANCE(hdma->Instance) != 0U) + { + if (((hdma->Init.TransferAllocatedPort & DMA_CTR1_SAP) == DMA_SRC_ALLOCATED_PORT0) && + (hdma->Init.SrcBurstLength > 16U)) + { + return HAL_ERROR; + } + if (((hdma->Init.TransferAllocatedPort & DMA_CTR1_DAP) == DMA_DEST_ALLOCATED_PORT0) && + (hdma->Init.DestBurstLength > 16U)) + { + return HAL_ERROR; + } + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Initialize the callbacks */ + if (hdma->State == HAL_DMA_STATE_RESET) + { + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->Init.Mode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in normal mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CLBAR = 0U; + hdma->Instance->CCR = 0U; + /* As secure, privilege and CID configuration, bit field DSEC and SSEC are managed in */ + /* HAL_DMA_ConfigChannelAttributes function, so it mustn't be cleaned in HAL_DMA_DeInit */ + hdma->Instance->CTR1 = hdma->Instance->CTR1 & (0U | DMA_CTR1_DSEC | DMA_CTR1_SSEC); + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### IO operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure the source, destination address and data size and Start DMA transfer in normal mode + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + + [..] + (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode). + (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode). + (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode). + (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode). + (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode). + This API cannot be used for circular transfers. + (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode). + (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and + unregister user customized callbacks. + User callbacks are called under HAL_DMA_IRQHandler(). + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in normal mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If Half Transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check Half suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If Transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel + * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be + * effectively suspended only after the transfer of any on-going data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check if the DMA Channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Clear all status flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Suspend the channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer status (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CompleteLevel : Specifies the DMA level complete. + * @param Timeout : Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + uint32_t level_flag; + uint32_t tmp_csr; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Polling mode is not supported in circular mode */ + if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT); + + /* Get DMA channel status */ + tmp_csr = hdma->Instance->CSR; + + while ((tmp_csr & level_flag) == 0U) + { + /* Check for the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* + If timeout, abort the current transfer. + Note that the Abort function will + - Clear all transfer flags. + - Unlock. + - Set the State. + */ + (void)HAL_DMA_Abort(hdma); + + return HAL_ERROR; + } + } + + /* Get a newer CSR register value */ + tmp_csr = hdma->Instance->CSR; + } + + /* Check trigger overrun flag */ + if ((tmp_csr & DMA_FLAG_TO) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + } + + /* Check error flags */ + if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U) + { + /* Check the data transfer error flag */ + if ((tmp_csr & DMA_FLAG_DTE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + } + + /* Check the update link error flag */ + if ((tmp_csr & DMA_FLAG_ULE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + } + + /* Check the user setting error flag */ + if ((tmp_csr & DMA_FLAG_USE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear the transfer level flag */ + if (CompleteLevel == HAL_DMA_HALF_TRANSFER) + { + /* Clear the Half Transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + } + else if (CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) +{ + const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); + uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); +#if defined (CPU_IN_SECURE_STATE) + uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); +#endif /* CPU_IN_SECURE_STATE */ + + /* Global Interrupt Flag management *********************************************************************************/ +#if defined (CPU_IN_SECURE_STATE) + if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) +#else + if (global_active_flag_ns == 0U) +#endif /* CPU_IN_SECURE_STATE */ + { + return; /* the global interrupt flag for the current channel is down , nothing to do */ + } + + /* Data Transfer Error Interrupt management *************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) + { + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + } + } + + /* Update Linked-list Error Interrupt management ********************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) + { + /* Clear the update linked-list error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + } + } + + /* User Setting Error Interrupt management **************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) + { + /* Clear the user setting error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + } + } + + /* Trigger Overrun Interrupt management *****************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) + { + /* Clear the trigger overrun flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + } + } + + /* Half Transfer Complete Interrupt management **********************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Suspend Transfer Interrupt management ****************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_ABORT) + { + /* Disable the suspend transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP); + + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer abort callback */ + if (hdma->XferAbortCallback != NULL) + { + /* Transfer abort callback */ + hdma->XferAbortCallback(hdma); + } + + return; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check transfer suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* Transfer suspend callback */ + hdma->XferSuspendCallback(hdma); + } + } + } + } + + /* Transfer Complete Interrupt management ***************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* If linked-list transfer */ + if (hdma->Instance->CLLR == 0U) + { + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + } + } + else + { + /* If normal transfer */ + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + } + } + + /* Clear TC and HT transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer complete callback */ + if (hdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + + /* Manage error case ************************************************************************************************/ + if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer error callback */ + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callback according to specified ID. + * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. + * @param pCallback : Pointer to private callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* Register transfer complete callback */ + hdma->XferCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* Register half transfer callback */ + hdma->XferHalfCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* Register transfer error callback */ + hdma->XferErrorCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* Register abort callback */ + hdma->XferAbortCallback = pCallback; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* Register suspend callback */ + hdma->XferSuspendCallback = pCallback; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister callback according to specified ID. + * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* UnRegister transfer complete callback */ + hdma->XferCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* UnRegister half transfer callback */ + hdma->XferHalfCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* UnRegister transfer error callback */ + hdma->XferErrorCallback = NULL; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* UnRegister abort callback */ + hdma->XferAbortCallback = NULL; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* UnRegister suspend callback */ + hdma->XferSuspendCallback = NULL; + break; + } + + case HAL_DMA_XFER_ALL_CB_ID: + { + /* UnRegister all available callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### State and Errors functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Check the DMA state + (+) Get error code + + [..] + (+) The HAL_DMA_GetState() function allows to get the DMA channel state. + (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA channel state. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA state. + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel state */ + return hdma->State; +} + +/** + * @brief Return the DMA channel error code. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA Error Code. + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel error code */ + return hdma->ErrorCode; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### DMA Attributes functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel secure and privilege attributes. + (+) Get DMA channel secure and privilege attributes. + (+) Lock DMA channel secure and privilege attributes configuration. + (+) Check whether DMA channel secure and privilege attributes configuration is locked or not. + + [..] + (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege + attributes. + (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes + configuration. + (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes. + (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege + attributes lock status. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel security and privilege attribute(s). + * @note These attributes cannot be modified when the corresponding lock state is enabled. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Check DMA channel privilege attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK) + { + /* Configure DMA channel privilege attribute */ + if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV) + { + p_dma_instance->PRIVCFGR |= channel_idx; + } + else + { + p_dma_instance->PRIVCFGR &= (~channel_idx); + } + } + +#if defined (CPU_IN_SECURE_STATE) + /* Check DMA channel security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK) + { + /* Configure DMA channel security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC) + { + p_dma_instance->SECCFGR |= channel_idx; + } + else + { + p_dma_instance->SECCFGR &= (~channel_idx); + } + } + + /* Channel source security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK) + { + /* Configure DMA channel source security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_SSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); + } + } + + /* Channel destination security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK) + { + /* Configure DMA channel destination security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_DSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); + } + } +#endif /* CPU_IN_SECURE_STATE */ + + return HAL_OK; +} + +/** + * @brief Get the DMA channel security and privilege attributes. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pChannelAttributes : Pointer to the returned attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t attributes; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and channel attributes parameters */ + if ((hdma == NULL) || (pChannelAttributes == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get DMA channel privilege attribute */ + attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; + + /* Get DMA channel security attribute */ + attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; + + /* Get DMA channel source security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC; + + /* Get DMA channel destination security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; + + /* return value */ + *pChannelAttributes = attributes; + + return HAL_OK; +} + +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Set the DMA channel filtering CID (Isolation configuration). It can be + * - static: the CID passed as parameter is programmed; + * - disabled: the whole register is cleared. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * of the HPDMA channel. + * @param pConfig : Pointer on the DMA Isolation structure + * @retval None + */ +HAL_StatusTypeDef HAL_DMA_SetIsolationAttributes(DMA_HandleTypeDef *const hdma, + DMA_IsolationConfigTypeDef const *const pConfig) +{ + /* Check the DMA peripheral handle parameter */ + if ((hdma == NULL) || (pConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HPDMA_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_ISOLATION_MODE(pConfig->CidFiltering)); + assert_param(IS_DMA_ISOLATION_STATIC_CID(pConfig->StaticCid)); + + /* static CID field value used when filtering is enable */ + if ((pConfig->CidFiltering) == DMA_ISOLATION_ON) + { + /* Write static CID configuration */ + hdma->Instance->CCIDCFGR = ((pConfig->StaticCid & DMA_CCIDCFGR_SCID_Msk) | DMA_CCIDCFGR_CFEN); + } + else + { + /* CID configuration is off */ + hdma->Instance->CCIDCFGR = 0U; + } + + return HAL_OK; +} +#endif /* CPU_IN_SECURE_STATE */ +/** + * @brief Read the DMA channel filtering CID (Isolation configuration). It can be + * - static: the CID passed as parameter is programmed; + * - disabled: the whole register is cleared. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * of the HPDMA channel. + * @param pConfig : Pointer on the DMA Isolation structure + * @retval None + */ +HAL_StatusTypeDef HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const *const hdma, + DMA_IsolationConfigTypeDef *const pConfig) +{ + uint32_t ccidcfgr; + + /* Check the DMA peripheral handle parameter */ + if ((hdma == NULL) || (pConfig == NULL)) + { + return HAL_ERROR; + } + + ccidcfgr = hdma->Instance->CCIDCFGR; + + /* Check the parameters */ + assert_param(IS_HPDMA_INSTANCE(hdma->Instance)); + + if ((ccidcfgr & DMA_CCIDCFGR_CFEN) == DMA_CCIDCFGR_CFEN) + { + pConfig->CidFiltering = DMA_ISOLATION_ON; + } + else + { + pConfig->CidFiltering = DMA_ISOLATION_OFF; + } + pConfig->StaticCid = (ccidcfgr & DMA_CCIDCFGR_SCID_Msk); + + return HAL_OK; +} +#if defined (CPU_IN_SECURE_STATE) +/** + * @brief Lock the DMA channel security and privilege attribute(s). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Lock the DMA channel privilege and security attributes */ + p_dma_instance->RCFGLOCKR |= channel_idx; + + return HAL_OK; +} +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Get the security and privilege attribute lock state of a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or + * DMA_CHANNEL_ATTRIBUTE_LOCKED). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and lock state parameters */ + if ((hdma == NULL) || (pLockState == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get channel lock attribute state */ + *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \ + DMA_CHANNEL_ATTRIBUTE_LOCKED; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @brief Set the DMA channel normal transfer parameters. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval None. + */ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Configure the DMA channel data size */ + MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT)); + + /* Clear all interrupt flags */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO); + + /* Configure DMA channel source address */ + hdma->Instance->CSAR = SrcAddress; + + /* Configure DMA channel destination address */ + hdma->Instance->CDAR = DstAddress; +} + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/ + tmpreg = hdma->Init.Priority; + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/ + tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth; + + /* Add parameters specific to HPDMA and GPDMA */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + tmpreg |= (hdma->Init.TransferAllocatedPort | + (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + + /* Write DMA Channel Transfer Register 1 (CTR1) */ + MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); + + /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ + tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; + + /* Memory to Peripheral Transfer */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + tmpreg |= DMA_CTR2_DREQ; + } + } + /* Memory to Memory Transfer */ + else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + tmpreg |= DMA_CTR2_SWREQ; + } + else + { + /* Nothing to do */ + } + + /* Set DMA channel operation mode */ + tmpreg |= hdma->Init.Mode; + + /* Write DMA Channel Transfer Register 2 (CTR2) */ + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM | + DMA_CTR2_PFREQ | DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | + DMA_CTR2_REQSEL), tmpreg); + + + /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) ************************************************************/ + WRITE_REG(hdma->Instance->CLLR, 0U); +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c (revision 16) @@ -0,0 +1,4752 @@ +/** + ********************************************************************************************************************** + * @file stm32n6xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following functionalities of the DMA extension + * peripheral: + * + Linked-List Initialization and De-Initialization Functions + * + Linked-List I/O Operation Functions + * + Linked-List Management Functions + * + Data Handling, Repeated Block and Trigger Configuration Functions + * + Suspend and Resume Operation Functions + * + FIFO Status Function + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as + linked-list (list of Node items). Each node is defined by its data structure. + Each node specifies a standalone DMA channel. + When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the + next linked list node will be fetched and executed. This operation is repeated until the end of the whole + linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked + to another queue node or circular where the last linked-list node is linked to any linked-list queue node. + + (+) Linear linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node + (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another + transfer can be lunched. + + (+) Circular linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail + node). When last node is executed, the DMA channel fetches the first circular node another time and repeat + the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is + required. This linked-list mode replaces the legacy circular transfers. + + [..] + In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the + dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and + dynamic. + + (+) Static linked-list: + The static linked-list format refers to the full linked-list node where all DMA channel parameters are + fetched and executed independently of the redundancy of information. + + (+) Dynamic linked-list: + The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary + parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the + current node => No need to update it). + + For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named + link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory + then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the + DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is + circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature + is useful for debug purpose or asynchronously executing queue nodes. + + [..] + Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance + integrated in devices. These configuration can be : + + (+) Repeated block configuration : + If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2 + dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block + transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can + jump after at burst and block level. The jump length is a programmable parameter defined by DMA user. + (++) Jump at burst level : + The DMA channel keep an empty area, between each 2 consecutive bursts transmitted. + (++) Jump at block level : + The DMA channel keep an empty area, between each 2 consecutive blocks transmitted. + + (+) Trigger : + The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware + triggers. Trigger condition can be applied at : + (++) Single/Burst level : + Each single/burst data transmission is conditioned by a signal trigger hit. + (++) Block level : + Each block data transmission is conditioned by a signal trigger hit. + (++) Repeated block level : + Each repeated block data transmission is conditioned by a signal trigger hit. + (++) Node level : + Each node execution is conditioned by a signal trigger hit. + The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before + executing the current transfer. + + (+) Data handling : + The data handling feature is a FIFO capability that can be : + (++) Padding pattern : + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + (++) Exchange : + Exchange data at byte, half-word and word on the destination and at byte level on the source. + + [..] + Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time + application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete + the current ongoing single/burst then it stops. + When the DMA channel is suspended, the current transfer can be resumed instantly. + + [..] + The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output) + FIFO level. + + *** Linked-List Initialization and De-Initialization operation *** + ================================================================== + [..] + Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the + remaining transfer parameters are defined by linked-list nodes. + + (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields. + When called, the DMA channel will be ready to execute linked-list queues. + + (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode. + When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer. + + *** Linked-List I/O Operation *** + ================================= + [..] + (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in interrupt mode (Non-blocking mode). + + *** Linked-List Management *** + ============================== + [..] + The linked-list management is a software processing independently of DMA channel hardware. It allows to reset, + build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA + channel transfers in linked-list mode. + Linked-list APIs and types are adapted to reduce memory footprint. + + *** Linked-list nodes building *** + [..] + At node level, the operations that can be done are building a new linked-list node or get a linked-list node + information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing + capability. The linear addressing nodes contains the information of all DMA channel features except the 2 + dimension addressing features and the 2 dimensions addressing nodes contain the information of all available + features. + + (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters. + Build operation allow to convert the specified parameter in values known by the DMA channel and place them + in memory. + Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the + link access port can access to the specified SRAM. + (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + addressable space. + + (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. + This API can be used when need to change few parameter to build new node. + + *** Inserting nodes to linked-list queue *** + [..] + In order to build a sequence of DMA transaction with different configuration, we need to insert built node at + linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the + full flexibility of ordering nodes or extend the sequence of queue transactions. + + (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue + according to selecting previous node. When calling this API with previous node parameter is NULL, the + inserted node will be placed at the head of the linked-list queue. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of + footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head + node will not be overwritten but will be the second queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail + node will not be overwritten but will be the penultimate queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + *** Removing nodes from linked-list queue *** + [..] + There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA + transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node + can be reused for another queue or to be added to the same queue without need to rebuild it in next step. + + (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Replacing nodes on linked-list queue *** + [..] + There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA + transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be + replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused + for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot + be reused except when remove it or replaced in next step. + + (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or + HAL_DMAEx_List_ReplaceNode_Tail() instead). + + (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Reset linked-list queue *** + [..] + After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be + unlinked (NOT DELETED) and reused on another queue. + + (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + + *** Inserting linked-list queue *** + [..] + To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for + action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and + a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where + the management of linked-list at queue granularity is needed. + + (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue + according to selecting previous node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of + destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or + HAL_DMAEx_List_InsertQ_Tail() instead). + + (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list + destination queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list + destination queue. + (++) This API must be called for static queues format. + + *** Circularizing linked-list queue *** + [..] + In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues. + Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node + is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be + executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed + once and all remaining nodes are executed in an infinite loop. + + (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first + circular node selected. + (++) This API must be called for static queues format. + (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of + footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead). + + (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node + with first queue node. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration. + (++) This API must be called for static queues format. + + + *** Converting linked-list queue *** + [..] + To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue + to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are + optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes + parameters instead of the whole node. + + (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + (++) This API must be called as the last API before starting the DMA channel in linked-list mode. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format. + (++) This API must be called for ready state queues. + (++) This API must be called for dynamic queues format. + (++) This API must be called as the first API after the full execution of linked-list queue when the + execution mode is linear (not circular) if it is dynamic and a linked-list queue management is + needed. + (++) This API must be called as the first API after the aborting the execution of the current linked-list + queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue + management is needed. + + [..] + When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is + recommended to duplicate the last circular node in order to ensure the full optimization when calling + HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce + 4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per + node execution. + + + *** Linking linked-list queue to DMA channel *** + [..] + In order to have the possibility of the creation of an infinity queues (limited by available memory size), the + building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if + their size is less then available memory at startup time, then linking each time when needed a linked-list queue + to an idle DMA channel. + + (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + *** User sequence *** + [..] + To use cleanly the DMA linked-list library, ensure to apply the following call sequences : + + (+) Linear transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + (+) Circular transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + + *** Data Handling *** + ===================== + [..] + In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to + FIFO capabilities titled data handling. + (++) Padding pattern + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) + Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) + (Source : 0xFABA ------> Destination : 0xFFFFFABA) + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD) + Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB) + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD) + UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD) + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + Considering source and destination are both word type. Exchange operation can be as follows. + In examples below, one exchange setting is enabled at a time. + Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) + Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) + Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) + In addition, in case of double-word, Exchange data at word level on the destination is also + available. + Considering source and destination are both double-word type. + word exchange only (Source : 0xAB12CD34EF567890 ------> Destination : 0xEF567890AB12CD34) + + (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained + can be combined according to application needs. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as data handling information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel data handling, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigDataHandling() + (++) HAL_DMA_Start() + + *** Repeated Block *** + ====================== + [..] + When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for + scattering / gathering data. + (++) Gather data + Source Destination + 0xAA 0xAA + 0xBB 0xAA + 0xAA ==> 0xAA + 0xCC + 0xAA + (++) Scatter data + Source Destination + 0xAA 0xAA + 0xAA 0xBB + 0xAA ==> 0xAA + 0xBB + 0xAA + + (+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and + incrementing or decrementing on source and destination can be combined to have the need application + behavior. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as repeated block information are configured at + node level. + (++) This API must be called only for DMA channel that supports repeated block feature. + + *** User sequence *** + [..] + To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigRepeatBlock() + (++) HAL_DMA_Start() + + *** Trigger Configuration *** + ============================= + [..] + When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can + do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the + DMA transfers. + To setup a trigger transfers, three DMA channel parameters are needed: + + (+) Trigger mode + This parameter specifies the trig level. + (++) Block level + (++) Repeated block level + (++) Node level + (++) Single / Burst level + + (+) Trigger polarity + This parameter specifies the DMA trigger sensitivity (Rising or falling). + + (+) Trigger selection + This parameter specifies the DMA trigger hardware signal. + + (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature. + (++) This API is complementary to normal transfers APIs. + (++) This API must not be called for linked-list transfers as trigger information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel trigger, ensure to apply the following call sequence : + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigTrigger() + (++) HAL_DMA_Start() + + *** Suspend and resume operation *** + ==================================== + [..] + There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more + priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and + interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed. + + (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking + mode). + + (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution. + + *** FIFO status *** + =================== + [..] + In several cases, the information of FIFO level is useful to inform at application level how to process remaining + data. When not empty, the DMA channel FIFO cannot be flashed only by reset. + + (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO). + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private Constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma); +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3); +#else +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +#endif /* __GNUC__ && !__CC_ARM */ +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset); +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo); +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo); +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode); +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular); +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation); +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format); +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField); +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Initialization and De-Initialization Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. + [..] + (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as + described in reference manual. + (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the + * DMA_InitLinkedListTypeDef and create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA channel handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority)); + assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode)); + assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode)); + assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode)); + /* Check DMA channel instance */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_List_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->InitLinkedList.LinkedListMode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in linked-list mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) +{ + + /* Get DMA instance */ + DMA_TypeDef *p_dma_instance; + + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CCR = 0U; + hdma->Instance->CLBAR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + + /* Clear privilege attribute */ + CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); + + +#if defined (CPU_IN_SECURE_STATE) + /* Clear secure attribute */ + CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* CPU_IN_SECURE_STATE */ + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Check the linked-list queue */ + if (hdma->LinkedListQueue != NULL) + { + /* Update the queue state and error code */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + } + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### Linked-List IO Operation Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure to start DMA transfer in linked-list mode. + + [..] + (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking + mode). + (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode + (Non-blocking mode). + (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting + transfer otherwise a HAL_ERROR will be returned. + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in linked-list mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If half transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Management Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Build linked-list node. + (+) Get linked-list node configuration. + (+) Insert node to linked-list queue in any queue position. + (+) Remove any node from linked-list queue. + (+) Replace any node from linked-list queue. + (+) Reset linked-list queue. + (+) Insert linked-list queue in any queue position. + (+) Set circular mode configuration to linked-list queue. + (+) Clear circular mode configuration from linked-list queue. + (+) Convert static linked-list queue to dynamic format. + (+) Convert dynamic linked-list queue to static format. + (+) Link linked-list queue to DMA channel. + (+) Unlink linked-list queue from DMA channel. + + [..] + (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node. + Node type can be : + (++) 2 dimensions addressing node. + (++) Linear addressing node. + + (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node. + + (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue + according to selected position. + + (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built + linked-list node to the head (respectively the tail) of static linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head + (respectively the tail) built linked-list node from static linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the + head (respectively the tail) built linked-list node of static linked-list queue. + + (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list + nodes. + + (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list + destination queue according to selected position. + + (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static + linked-list source queue to the head (respectively the tail) of static linked-list destination queue. + + (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to + the selected first circular node. + + (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the + first static linked-list queue node. + + (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from + any first circular node position. + + (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic + format. (Optimized queue execution) + + (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static + format. (Not optimized queue execution) + + (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to + be executed. + + (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA + channel when execution is completed. + +@endverbatim + * @{ + */ + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + * addressable space. + * @note Warning if AXI port is selected with HPDMA, the maximum source (and destination) length should be less + * than 17. Otherwise, an error will be returned and no initialization performed. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check node type parameter */ + assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType)); + + /* Check DMA channel basic transfer parameters */ + assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth)); + assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment)); + assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction)); + assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode)); + assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest)); + assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode)); + + /* Check DMA channel parameters */ + if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U) + { + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength)); + assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort)); + } + + /* Check DMA channel trigger parameters */ + assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity)); + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection)); + } + + /* Check DMA channel repeated block parameters */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); + } + + /* Check DMA channel security and privilege attributes parameters */ +#if defined (CPU_IN_SECURE_STATE) + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); +#endif /* CPU_IN_SECURE_STATE */ + + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_HPDMA) == DMA_CHANNEL_TYPE_HPDMA) + { + if (((pNodeConfig->Init.TransferAllocatedPort & DMA_CTR1_SAP) == DMA_SRC_ALLOCATED_PORT0) && + (pNodeConfig->Init.SrcBurstLength > 16U)) + { + return HAL_ERROR; + } + if (((pNodeConfig->Init.TransferAllocatedPort & DMA_CTR1_DAP) == DMA_DEST_ALLOCATED_PORT0) && + (pNodeConfig->Init.DestBurstLength > 16U)) + { + return HAL_ERROR; + } + } + + /* Build the DMA channel node */ + DMA_List_BuildNode(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Get the DMA channel node configuration */ + DMA_List_GetNodeConfig(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Insert new node in any queue position of linked-list queue according to selecting previous node. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Empty queue */ + if (pQList->Head == NULL) + { + /* Add only new node to queue */ + if (pPrevNode == NULL) + { + pQList->Head = pNewNode; + pQList->NodeNumber = 1U; + } + /* Add previous node then new node to queue */ + else + { + pQList->Head = pPrevNode; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pQList->NodeNumber = 2U; + } + } + /* Not empty queue */ + else + { + /* Add new node at the head of queue */ + if (pPrevNode == NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + /* Add new node according to selected position */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U) + { + /* Selected node is the last queue node */ + if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + /* Selected node is not the last queue node */ + else + { + pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset]; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + + /* Increment queue node number */ + pQList->NodeNumber++; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the head of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the tail of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove node from any linked-list queue position. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode) +{ + uint32_t previousnode_addr; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the node parameters */ + if ((pQList == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U) + { + /* Removed node is the head node */ + if (node_info.currentnode_pos == 1U) + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Update the queue head node */ + pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) + + (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + /* Removed node is the last node */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + /* Removed node is in the middle */ + else + { + /* Store previous node address to be updated later */ + previousnode_addr = node_info.previousnode_addr; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Link previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset]; + + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + + /* Decrement node number */ + pQList->NodeNumber--; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the head node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t current_addr; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA))); + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the tail node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace node in linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the nodes parameters */ + if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U) + { + /* Replaced node is the head node */ + if (node_info.currentnode_pos == 1U) + { + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + pQList->Head = pNewNode; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + /* Replaced node is the last */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + } + /* Replaced node is in the middle */ + else + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Find last node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link last queue node to new node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the head node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_offset; + uint32_t cllr_mask; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + + /* Replace head node */ + pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset]; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = pNewNode; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the tail node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find last node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link previous node to new node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Clear CLLR for current node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check if queue contains one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head = pNewNode; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Reset the linked-list queue and unlink queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Check the queue */ + if (pQList->Head != NULL) + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Reset selected queue nodes */ + node_info.cllr_offset = cllr_offset; + DMA_List_ResetQueueNodes(pQList, &node_info); + } + + /* Reset head node address */ + pQList->Head = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset first circular node */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the source queue circularity */ + if (pSrcQList->FirstCircularNode != NULL) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Previous node is empty */ + if (pPrevNode == NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + /* Previous node is not empty */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U) + { + /* Selected node is the last destination queue node */ + if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber) + { + /* Link the first node of source queue to the last node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + /* Selected node is not the last destination queue node */ + else + { + /* Link the first node of source queue to the previous node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Link the last node of source queue to the next node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask; + + /* Update queues counter */ + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + } + else + { + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the head of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the tail of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Update source queue last node CLLR to link it with destination first node */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode configuration for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node + * registers configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the first circular node parameters */ + if ((pQList == NULL) || (pFirstCircularNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pFirstCircularNode) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset); + + /* Find the first circular node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U) + { + /* Find the last queue node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask; + + /* Update first circular node in queue */ + pQList->FirstCircularNode = pFirstCircularNode; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pQList->Head) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Update linked-list circular state */ + pQList->FirstCircularNode = pQList->Head; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Clear circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode == NULL) + { + return HAL_OK; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Update linked-list circular configuration */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + DMA_NodeInQInfoTypeDef node_info = {0U}; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is dynamic */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + return HAL_OK; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Store register value */ + DMA_List_FillNode(pQList->Head, &context_node); + + /* Convert all nodes to dyncamic (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Bypass the first circular node when first circular node isn't the last queue node */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) && + ((uint32_t)pQList->FirstCircularNode == currentnode_addr)) + { + /* Copy first circular node to context node */ + DMA_List_FillNode(pQList->FirstCircularNode, &context_node); + } + else + { + /* Convert current node to dynamic */ + DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + } + + /* Check if first circular node is the last node queue */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr)) + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR); + } + else + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR); + } + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_DYNAMIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to static (Not optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is static */ + if (pQList->Type == QUEUE_TYPE_STATIC) + { + return HAL_OK; + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Set all CLLR queue nodes to their default positions */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION); + + /* Convert all nodes to static (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update context node register values */ + DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node); + + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Convert current node to static */ + DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + + /* Set all CLLR queue nodes to their default values */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE); + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_STATIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Link linked-list queue to a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel handle and the queue parameters */ + if ((hdma == NULL) || (pQList == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check linearity compatibility */ + if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) && + ((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED; + + return HAL_ERROR; + } + + /* Check circularity compatibility */ + if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Check first circular node */ + if (pQList->FirstCircularNode == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + else + { + /* Check first circular node */ + if (pQList->FirstCircularNode != NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Register queue to DMA handle */ + hdma->LinkedListQueue = pQList; + + return HAL_OK; +} + +/** + * @brief Unlink linked-list queue from a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear queue information from DMA channel handle */ + hdma->LinkedListQueue = NULL; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### Data handling, repeated block and trigger configuration functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel data handling. + (+) Configure DMA channel repeated block. + (+) Configure DMA channel trigger. + + [..] + (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling. + (++) GPDMA or HPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, + sign extension and left/right alignment. + + (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers. + + (+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block. + (++) This feature is available only for channel that supports 2 dimensions addressing capability. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel data handling according to the specified parameters in the + * DMA_DataHandlingConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling) +{ + /* Check the DMA peripheral handle and data handling parameters */ + if ((hdma == NULL) || (pConfigDataHandling == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment)); + assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), + (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange)); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger) +{ + /* Check the DMA peripheral handle and trigger parameters */ + if ((hdma == NULL) || (pConfigTrigger == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity)); + assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM), + (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode | + (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos))); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel repeated block according to the specified parameters in the + * DMA_RepeatBlockConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + + /* Check the DMA peripheral handle and repeated block parameters */ + if ((hdma == NULL) || (pConfigRepeatBlock == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Store repeat block count */ + tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos); + + /* Check the sign of single/burst destination address offset value */ + if (pConfigRepeatBlock->DestAddrOffset < 0) + { + /* Store single/burst destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_DDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos; + } + else + { + /* Store single/burst destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos); + } + + /* Check the sign of single/burst source address offset value */ + if (pConfigRepeatBlock->SrcAddrOffset < 0) + { + /* Store single/burst source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_SDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset); + } + else + { + /* Store single/burst source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset; + } + + /* Write DMA Channel Transfer Register 3 (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, tmpreg2); + + /* Check the sign of block destination address offset value */ + if (pConfigRepeatBlock->BlkDestAddrOffset < 0) + { + /* Store block destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRDDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos; + } + else + { + /* Store block destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos); + } + + /* Check the sign of block source address offset value */ + if (pConfigRepeatBlock->BlkSrcAddrOffset < 0) + { + /* Store block source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRSDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset); + } + else + { + /* Store block source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset; + } + + /* Write DMA Channel block register 2 (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, tmpreg2); + + /* Write DMA Channel block register 1 (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, tmpreg1); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group5 + * +@verbatim + ====================================================================================================================== + ##### Suspend and resume operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Suspend any ongoing DMA channel transfer. + (+) Resume any suspended DMA channel transfer. + + [..] + (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking + mode). + + (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode + (Non-blocking mode). + + (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA channel. + * @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If + * a channel is suspended while a data transfer is ongoing, the current data will be transferred and the + * channel will be effectively suspended only after the transfer of this single/burst data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Check if the DMA channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + } + + return HAL_OK; +} + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the DMA channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Resume any suspended DMA channel transfer. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_SUSPEND) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Resume the DMA channel */ + hdma->Instance->CCR &= (~DMA_CCR_SUSP); + + /* Clear the suspend flag */ + hdma->Instance->CFCR |= DMA_CFCR_SUSPF; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group6 + * +@verbatim + ====================================================================================================================== + ##### Fifo status function ##### + ====================================================================================================================== + [..] + This section provides function allowing to get DMA channel FIFO level. + + [..] + (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in + units of the programmed destination data. + (++) This API is available only for DMA channels that supports FIFO. + +@endverbatim + * @{ + */ + +/** + * @brief Get and returns the DMA channel FIFO level. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval Returns the number of available beats in FIFO. + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma) +{ + return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value */ + tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; + + /* Check DMA channel instance */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; + } + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Write DMA Channel Control Register (CTR1) */ + WRITE_REG(hdma->Instance->CTR1, 0U); + + /* Write DMA Channel Control Register (CTR2) */ + WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode); + + /* Write DMA Channel Control Register (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* Write DMA Channel Control Register (CSAR) */ + WRITE_REG(hdma->Instance->CSAR, 0U); + + /* Write DMA Channel Control Register (CDAR) */ + WRITE_REG(hdma->Instance->CDAR, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Control Register (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Control Register (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) */ + WRITE_REG(hdma->Instance->CLLR, 0U); +} + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + int32_t blockoffset; + + /* Update CTR1 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | + pNodeConfig->Init.DestDataWidth | + pNodeConfig->DataHandlingConfig.DataAlignment | + pNodeConfig->Init.SrcInc | + pNodeConfig->Init.SrcDataWidth; + +#if defined (CPU_IN_SECURE_STATE) + /* set source channel security attribute */ + if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; + } + + /* set destination channel security attribute */ + if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; + } +#endif /* CPU_IN_SECURE_STATE */ + + /* Add parameters related to DMA configuration */ + if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U) + { + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= + (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange | + (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + /*********************************************************************************** CTR1 register value is updated */ + + + /* Update CTR2 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode | + (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ)); + + /* Check for memory to peripheral transfer */ + if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Check for GPDMA OR HPDMA */ + if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ; + } + } + /* Memory to memory transfer */ + else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Configure HW Peripheral flow control selection */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= pNodeConfig->Init.Mode; + + /* Check if trigger feature is active */ + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= + pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity | + ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); + } + /*********************************************************************************** CTR2 register value is updated */ + + + /* Update CBR1 register value ***************************************************************************************/ + /* Prepare DMA channel block register 1 (CBR1) value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT); + + /* If 2D addressing is supported by the selected DMA channel */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Set the new CBR1 Register value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= + (((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); + + /* If the source address offset is negative, set SDEC bit */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC); + } + + /* If the destination address offset is negative, set DDEC bit */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC); + } + + /* If the repeated block source address offset is negative, set BRSEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC); + } + + /* if the repeated block destination address offset is negative, set BRDEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC); + } + } + /*********************************************************************************** CBR1 register value is updated */ + + + /* Update CSAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress; + /*********************************************************************************** CSAR register value is updated */ + + + /* Update CDAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; + /*********************************************************************************** CDAR register value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CTR3 register value *************************************************************************************/ + /* Write new CTR3 Register value : source address offset */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); + } + + /* Write new CTR3 Register value : destination address offset */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + /********************************************************************************* CTR3 register value is updated */ + + + /* Update CBR2 register value *************************************************************************************/ + /* Write new CBR2 Register value : repeated block source address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO); + } + + /* Write new CBR2 Register value : repeated block destination address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); + } + /********************************************************************************* CBR2 register value is updated */ + + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + + /* Update node information value ************************************************************************************/ + /* Set node information */ + pNode->NodeInfo = pNodeConfig->NodeType; + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + else + { + pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + /******************************************************************************** Node information value is updated */ +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + uint16_t offset; + + /* Get node information *********************************************************************************************/ + pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK); + /*************************************************************************************** Node type value is updated */ + + + /* Get CTR1 fields values *******************************************************************************************/ + pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC; + pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC; + pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; + pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U; + pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U; + pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SAP | DMA_CTR1_DAP); + pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX | DMA_CTR1_DWX); + pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; +#if defined (CPU_IN_SECURE_STATE) + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC; + } + else + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC; + } + + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U) + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC; + } + else + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; + } +#endif /* CPU_IN_SECURE_STATE */ + /*********************************************************************************** CTR1 fields values are updated */ + + + /* Get CTR2 fields values *******************************************************************************************/ + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U) + { + pNodeConfig->Init.Request = DMA_REQUEST_SW; + pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY; + } + else + { + pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL; + + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U) + { + pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH; + } + else + { + pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY; + } + } + + pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ); + pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM; + pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL; + pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; + pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM; + /*********************************************************************************** CTR2 fields values are updated */ + + + /* Get CBR1 fields **************************************************************************************************/ + pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT; + + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNodeConfig->RepeatBlockConfig.RepeatCount = + ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U; + } + else + { + pNodeConfig->RepeatBlockConfig.RepeatCount = 1U; + } + /*********************************************************************************** CBR1 fields values are updated */ + + + /* Get CSAR field ***************************************************************************************************/ + pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]; + /************************************************************************************** CSAR field value is updated */ + + + /* Get CDAR field ***************************************************************************************************/ + pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]; + /************************************************************************************** CDAR field value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Get CTR3 field *************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); + pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1); + } + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO); + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1); + } + /************************************************************************************ CBR2 field value is updated */ + } + else + { + /* Get CTR3 field *************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.DestAddrOffset = 0; + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0; + /************************************************************************************ CBR2 field value is updated */ + } +} + +/** + * @brief Check nodes base addresses compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes addresses are compatible, 1 otherwise. + */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3) +#else +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +#endif /* __GNUC__ && !__CC_ARM */ +{ + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); + uint32_t ref = 0U; + + /* Check node 1 address */ + if ((uint32_t)pNode1 != 0U) + { + ref = (uint32_t)pNode1; + } + /* Check node 2 address */ + else if ((uint32_t)pNode2 != 0U) + { + ref = (uint32_t)pNode2; + } + /* Check node 3 address */ + else if ((uint32_t)pNode3 != 0U) + { + ref = (uint32_t)pNode3; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check addresses compatibility */ + if (temp != ((uint32_t)ref & DMA_CLBAR_LBA)) + { + return 1U; + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. + */ +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t ref = 0U; + + /* Check node 1 parameter */ + if (pNode1 != NULL) + { + ref = pNode1->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 2 parameter */ + else if (pNode2 != NULL) + { + ref = pNode2->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 3 parameter */ + else if (pNode3 != NULL) + { + ref = pNode3->NodeInfo & NODE_TYPE_MASK; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check node 2 parameter */ + if (pNode2 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK)) + { + return 2U; + } + } + + /* Check node 3 parameter */ + if (pNode3 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK)) + { + return 3U; + } + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param cllr_mask : Pointer to CLLR register mask value. + * @param cllr_offset : Pointer to CLLR register offset value. + * @retval None. + */ +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset) +{ + /* Check node type */ + if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | + DMA_CLLR_UB2 | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET; + } + } + /* Update CLLR and register number for linear addressing node */ + else + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; + } + } +} + +/** + * @brief Find node in queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval Return 0 when node is found in selected queue, otherwise node is not found. + */ +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address = 0U; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Find last node in queue */ + if (pNode == NULL) + { + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + /* Find selected node node in queue */ + else + { + /* Check that previous node is linked to the selected queue */ + while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + + /* Check stored address */ + if (pNode != NULL) + { + if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)) + { + return 1U; + } + } + + /* Update current node position */ + NodeInfo->currentnode_pos = node_idx; + + /* Update previous node address */ + NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update current node address */ + NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update next node address */ + if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U) + { + NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] & + DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + } + + return 0U; +} + +/** + * @brief Reset queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval None. + */ +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA); + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Reset node */ + ((DMA_NodeTypeDef *)(previousnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Fill source node registers values by destination nodes registers values. + * @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers + * configurations. + * @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers + * configurations. + * @retval None. + */ +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode) +{ + /* Repeat for all register nodes */ + for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx]; + } + + /* Fill node information */ + pDestNode->NodeInfo = pSrcNode->NodeInfo; +} + +/** + * @brief Convert node to dynamic. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t currentnode_reg_counter = 0U; + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx = RegisterNumber - 1U; + DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */ + if ((context_node->LinkRegisters[contextnode_reg_counter] == + current_node->LinkRegisters[currentnode_reg_counter]) && + (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != (RegisterNumber - 1U))) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT); + + /* Update CLLR index */ + cllr_idx --; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter]; + } + else + { + /* Update context node register fields with new values */ + context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter]; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter]; + + /* Increment current node number register counter */ + currentnode_reg_counter++; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS)); + + /* Clear unused node fields */ + DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter); +} + +/** + * @brief Convert node to static. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx; + uint32_t cllr_mask; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Get context node CLLR information */ + cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + cllr_mask = context_node->LinkRegisters[cllr_idx]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if node field is dynamic */ + if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT); + + /* Update node field */ + current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter]; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS)); +} + +/** + * @brief Format the node according to unused registers. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param RegisterIdx : The first register index to be formatted. + * @param RegisterNumber : The number of node registers. + * @param Format : The format type. + * @retval None. + */ +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format) +{ + if (Format == NODE_DYNAMIC_FORMAT) + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U]; + } + } + else + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U]; + } + } +} + +/** + * @brief Clear unused register fields. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param FirstUnusedField : The first unused field to be cleared. + * @retval None. + */ +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField) +{ + /* Repeat for all unused fields */ + for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pNode->LinkRegisters[reg_idx] = 0U; + } +} + +/** + * @brief Update CLLR for all dynamic queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param LastNode_IsCircular : The first circular node is the last queue node or not. + * @retval None. + */ +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular) +{ + uint32_t previous_cllr_offset; + uint32_t current_cllr_offset = 0U; + uint32_t previousnode_addr; + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Repeat for all register nodes */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + /* Get current node information */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + } + /* Calculate nodes addresses */ + else + { + /* Get previous node information */ + previousnode_addr = currentnode_addr; + previous_cllr_offset = current_cllr_offset; + + /* Get current node information */ + currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Calculate CLLR register value to be updated */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) | + (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA); + + /* Set new CLLR value to previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask; + } + + /* Increment node index */ + node_idx++; + } + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* First circular queue is not last queue node */ + if (LastNode_IsCircular == 0U) + { + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL); + + /* Update CLLR register for last circular node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + } + /* First circular queue is last queue node */ + else + { + /* Disable CLLR updating */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; + } + } + else + { + /* Clear CLLR register for last node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U; + } +} + +/** + * @brief Update CLLR for all static queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param operation : The operation type. + * @retval None. + */ +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation) +{ + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + uint32_t cllr_default_offset; + uint32_t cllr_default_mask; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset); + + /* Repeat for all register nodes (Bypass last queue node) */ + while (node_idx < pQList->NodeNumber) + { + if (operation == UPDATE_CLLR_POSITION) + { + /* Get CLLR value */ + cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset]; + } + else + { + /* Calculate CLLR value */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) | + cllr_default_mask; + } + + /* Set new CLLR value to default position */ + if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL)) + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U; + } + else + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask; + } + + /* Update current node address with next node address */ + currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA); + + /* Update current CLLR offset with next CLLR offset */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Clean linked-list queue variable. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval None. + */ +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList) +{ + /* Clear head node */ + pQList->Head = NULL; + + /* Clear first circular queue node */ + pQList->FirstCircularNode = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + /* Reset queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Reset queue type */ + pQList->Type = QUEUE_TYPE_STATIC; +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_exti.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_exti.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_exti.c (revision 16) @@ -0,0 +1,849 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_exti.c + * @author GPM Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04U /* byte offset between IMRx/EMRx registers */ +#define EXTI_CONFIG_OFFSET 0x08U /* byte offset between Rising/Falling configuration registers */ +#define EXTI_PRIVCFGR_OFFSET 0x08U /* byte offset between PRIVCFGRx/PRIVCFGRx registers */ +#define EXTI_SECCFGR_OFFSET 0x08U /* byte offset between SECCFGRx/SECCFGRx registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & EXTI_EXTICR1_EXTI0; + } + else + { + pExtiConfig->GPIOSel = 0U; + } + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0U; + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->RisingCallback = pPendingCbfn; + hexti->FallingCallback = pPendingCbfn; + break; + + case HAL_EXTI_RISING_CB_ID: + hexti->RisingCallback = pPendingCbfn; + break; + + case HAL_EXTI_FALLING_CB_ID: + hexti->FallingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->RisingCallback != NULL) + { + hexti->RisingCallback(); + } + } + + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call falling callback */ + if (hexti->FallingCallback != NULL) + { + hexti->FallingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @brief EXTI attributes management functions. + * +@verbatim + =============================================================================== + ##### EXTI attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configure the EXTI line attribute(s). + * @note Available attributes are to secure EXTI line and set EXTI line as privileged. + * Default state is not secure and unprivileged access allowed. + * @note Set an EXTI line to secure is only available in secure and privilege + * Set an EXTI line to privilege is only available in privilege + * @note Security and privilege attributes can be set independently. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param LineAttributes can be one or a combination of the following values: + * @arg @ref EXTI_LINE_PRIV Privileged-only access + * @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access + * @arg @ref EXTI_LINE_SEC Secure-only access + * @arg @ref EXTI_LINE_NSEC Secure/Non-secure access + * @retval None + */ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes)); + + /* compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure privilege or non-privilege attributes */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store privilege or non-privilege attribute */ + *regaddr = regval; + +#if defined CPU_IN_SECURE_STATE + /* Configure secure or non-secure attributes */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store secure or non-secure attribute */ + *regaddr = regval; +#endif /* CPU_IN_SECURE_STATE */ + +} + +/** + * @brief Get the EXTI line attribute(s). + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param pLineAttributes: pointer to return line attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes) +{ + const __IO uint32_t *regaddr; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t attributes; + + /* Check null pointer */ + if (pLineAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Get privilege or non-privilege attribute */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes = EXTI_LINE_PRIV; + } + else + { + attributes = EXTI_LINE_NPRIV; + } + + /* Get secure or non-secure attribute */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes |= EXTI_LINE_SEC; + } + else + { + attributes |= EXTI_LINE_NSEC; + } + + /* return value */ + *pLineAttributes = attributes; + + return HAL_OK; +} + +#if defined(CPU_IN_SECURE_STATE) +/** + * @brief Lock the secure and privilege configuration registers. + * @retval None + */ +void HAL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +uint32_t HAL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +#endif /* CPU_IN_SECURE_STATE */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_gpio.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_gpio.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_gpio.c (revision 16) @@ -0,0 +1,897 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_gpio.c + * @author GPM Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in analog mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 73 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in analog mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants + * @{ + */ +#define GPIO_NUMBER (16u) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @note If GPIOx peripheral pin is used in EXTI_MODE and the pin is secure/privilege, it is up + * to the application to insure that the corresponding EXTI line is set secure/privilege. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) || + (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP))) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + { + temp = EXTI->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos)); + temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos)); + EXTI->EXTICR[position >> 2u] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->IMR1 = temp; + + temp = EXTI->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->EMR1 = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = EXTI->EXTICR[position >> 2u]; + tmp &= (0x0FUL << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos); + EXTI->EXTICR[position >> 2u] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFUL << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + + /* Reset delay settings for the current IO */ + GPIOx->DELAYR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * GPIO_DELAYRL_DLY1_Pos)) ; + + /* Reset control settings for the current IO */ + GPIOx->ADVCFGR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)) ; + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL, GPIOx_AFRH, GPIOx_DELAYRL, GPIOx_DELAYRH, GPIOx_ADVCFGRL, GPIOx_ADVCFGRH. + * @note The configuration of the locked GPIO pins can no longer be modified until the next reset. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval HAL_OK if success, HAL_ERROR otherwise + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure GPIO retime on specified GPIO pin. + * @param GPIOx where x can be (A..H and N..Q) + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param pRet_Init pointer to a GPIO_RetimeTypeDef structure that contains + * the retime configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_SetRetime(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_RetimeTypeDef *pRet_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_RETIME(pRet_Init->Retime)); + assert_param(IS_GPIO_CLOCK(pRet_Init->Edge)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /* Configure the IO Retime */ + temp = GPIOx->ADVCFGR[position >> 3u]; + temp &= ~((GPIO_ADVCFGRL_RET0 | GPIO_ADVCFGRL_INVCLK0 | GPIO_ADVCFGRL_DE0) + << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); + temp |= (pRet_Init->Retime << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); + temp |= (pRet_Init->Edge << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); + GPIOx->ADVCFGR[position >> 3u] = temp; + } + position++; + } +} + +/** + * @brief Get GPIO retime configuration on specified GPIO pin. + * @param GPIOx where x can be (A..H and N..Q) + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @param pRet_Init pointer to the return GPIO_RetimeTypeDef structure that contains the retime information + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_GPIO_GetRetime(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_RetimeTypeDef *pRet_Init) +{ + uint32_t position; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + + /* Check null pointer */ + if (pRet_Init == NULL) + { + return HAL_ERROR; + } + + /* get IO position */ + position = POSITION_VAL(GPIO_Pin); + + /* Get the IO advanced configuration */ + index = (position & 0x07u) * GPIO_ADVCFGRL_1_Pos; + pRet_Init->Edge = ((GPIOx->ADVCFGR[position >> 3u] + & ((GPIO_ADVCFGRL_DE0 << index) | (GPIO_ADVCFGRL_INVCLK0 << index))) >> index); + pRet_Init->Retime = ((GPIOx->ADVCFGR[position >> 3u] & (GPIO_ADVCFGRL_RET0 << index)) >> index); + + return HAL_OK; +} + + +/** + * @brief Configure GPIO delay on specified GPIO pin. + * @param GPIOx where x can be (A..H and N..Q) + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param pDly_Init pointer to a GPIO_DelayTypeDef structure that contains + * the delay configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_SetDelay(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_DelayTypeDef *pDly_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_DELAY(pDly_Init->Delay)); + assert_param(IS_GPIO_PATH(pDly_Init->Path)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /* Configure the IO Delay path */ + temp = GPIOx->ADVCFGR[position >> 3u]; + temp &= ~(GPIO_ADVCFGRL_DLYPATH0 << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); + temp |= (pDly_Init->Path << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); + GPIOx->ADVCFGR[position >> 3u] = temp; + + /* Configure the IO Delay */ + temp = GPIOx->DELAYR[position >> 3u]; + temp &= ~(GPIO_DELAYRL_DLY0_Msk << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); + temp |= (pDly_Init->Delay << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)); + GPIOx->DELAYR[position >> 3u] = temp; + } + position++; + } +} + +/** + * @brief Get GPIO delay configuration on specified GPIO pin. + * @param GPIOx where x can be (A..H and N..Q) + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @param pDly_Init pointer to the return GPIO_DelayTypeDef structure that contains the delay information + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_GPIO_GetDelay(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_DelayTypeDef *pDly_Init) +{ + uint32_t position; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + + /* Check null pointer */ + if (pDly_Init == NULL) + { + return HAL_ERROR; + } + + /* get IO position */ + position = POSITION_VAL(GPIO_Pin); + + /* Get the IO advanced configuration */ + index = (position & 0x07u) * GPIO_ADVCFGRL_1_Pos; + pDly_Init->Delay = ((GPIOx->DELAYR[position >> 3u] & (GPIO_DELAYRL_DLY0_Msk << index)) >> index); + pDly_Init->Path = ((GPIOx->ADVCFGR[position >> 3u] & (GPIO_ADVCFGRL_DLYPATH0 << index)) >> index); + + return HAL_OK; +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + } + + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line rising detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + */ +} + +/** + * @brief EXTI line falling detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @brief GPIO attributes management functions. + * +@verbatim + =============================================================================== + ##### IO attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +#if defined (CPU_IN_SECURE_STATE) + +/** + * @brief Lock security and privilege configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the value of this port bit can no longer + * be modified until the next reset. Set sequence only available in secure and privilege. + * @note Each lock bit freezes a security configuration register (control and alternate function registers). + * @param GPIOx GPIO Port + * @param GPIO_Pin specifies the port bit to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_LockPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Lock the pins */ + GPIOx->RCFGLOCKR = (uint32_t)GPIO_Pin; +} + +/** + * @brief Get lock security and privilege configuration of several pins for a dedicated port. + * @param GPIOx GPIO Port + * @retval Lock status for all pins. Bitx are set to 1 for pinx locked, otherwise 0. + */ +uint32_t HAL_GPIO_GetLockPinAttributes(const GPIO_TypeDef *GPIOx) +{ + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Lock the pins */ + return (GPIOx->RCFGLOCKR); + +} + +#endif /* CPU_IN_SECURE_STATE */ + +/** + * @brief Configure the GPIO pins attributes. + * @note Set a pin to secure is only available in secure and privilege + * Set a pin to privilege is only available in privilege + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Pin : GPIO_Pin specifies the pin(s) to configure the secure/privilege attribute + * @param PinAttributes: PinAttributes can be one or a combination of the following values : + * @arg @ref GPIO_PIN_PRIV Privileged-only access + * @arg @ref GPIO_PIN_NPRIV Privileged/Non-privileged access + * @arg @ref GPIO_PIN_SEC Secure-only access + * @arg @ref GPIO_PIN_NSEC Secure/Non-secure access + * @retval None. + */ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes) +{ +#if defined CPU_IN_SECURE_STATE + uint32_t sec; +#endif /* CPU_IN_SECURE_STATE */ + uint32_t priv; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes)); + +#if defined CPU_IN_SECURE_STATE + /* Configure the port pins */ + sec = GPIOx->SECCFGR; + if ((PinAttributes & GPIO_PIN_SEC) == GPIO_PIN_SEC) + { + sec |= (uint32_t)GPIO_Pin; + } + else if ((PinAttributes & GPIO_PIN_NSEC) == GPIO_PIN_NSEC) + { + sec &= ~((uint32_t)GPIO_Pin); + } + else + { + /* do nothing */ + } + GPIOx->SECCFGR = sec; +#endif /* CPU_IN_SECURE_STATE */ + + priv = GPIOx->PRIVCFGR; + if ((PinAttributes & GPIO_PIN_PRIV) == GPIO_PIN_PRIV) + { + priv |= (uint32_t)GPIO_Pin; + } + else if ((PinAttributes & GPIO_PIN_NPRIV) == GPIO_PIN_NPRIV) + { + priv &= ~((uint32_t)GPIO_Pin); + } + else + { + /* do nothing */ + } + + GPIOx->PRIVCFGR = priv; +} + +/** + * @brief Get the GPIO pins attributes. + * @param GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @param pPinAttributes: pPinAttributes pointer to return the pin attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes) +{ + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + + /* Check null pointer */ + if (pPinAttributes == NULL) + { + return HAL_ERROR; + } + + if ((GPIOx->SECCFGR & GPIO_Pin) != 0x00U) + { + *pPinAttributes = GPIO_PIN_SEC; + } + else + { + *pPinAttributes = GPIO_PIN_NSEC; + } + + if ((GPIOx->PRIVCFGR & GPIO_Pin) != 0x00U) + { + *pPinAttributes |= GPIO_PIN_PRIV; + } + else + { + *pPinAttributes |= GPIO_PIN_NPRIV; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr.c (revision 16) @@ -0,0 +1,1035 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/De-Initialization Functions. + * + Peripheral Control Functions. + * + PWR Attributes Functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + + (#) Several low-power modes are available to save power when the CPU does not need to + execute code : + (+) Sleep (CPU clock stopped and still in RUN mode) + (+) Stop (System clock stopped) + (+) Standby (System powered down) + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RCC Backup domain control + register RCC_BDCR, RTC registers, TAMP registers, backup registers and + backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Programmed Voltage + Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() + functions to start and stop the PVD detection. + (+) PVD level on PVD_IN is compared to the internal VREFINT level. + PVDO flag is available in PWR_CR2 to indicate if the voltage level + on PVD_IN is higher or lower than the PVD threshold. + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High), the wake up pin selection and to enable and disable it. + + (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag() + functions to manage wake-up flag for the selected pin. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode. + Wake-up from Sleep mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop + mode. Wake-up from Stop mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). (Regulator state on STM32N6 devices is managed internally but + regulator parameter is kept for product compatibility). + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + Standby mode. Wake-up from Standby mode can be following only by an + interrupt. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-M55 re-entry in Sleep mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-M55 to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + (#) Call HAL_PWR_WAKEUP_PIN_IRQHandler() function to handle all wake-up + pins interrupts. + + (#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and + privilege attributes and call HAL_PWR_GetConfigAttributes() function to + get the attribute configuration for the selected item. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#if defined (HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT (0x00010000U) /*!< Mask for interruption yielded by PVD threshold crossing */ +#define PVD_MODE_EVT (0x00020000U) /*!< Mask for event yielded by PVD threshold crossing */ +#define PVD_RISING_EDGE (0x00000001U) /*!< Mask for rising edge set as PVD trigger */ +#define PVD_FALLING_EDGE (0x00000002U) /*!< Mask for falling edge set as PVD trigger */ +#define PVD_RISING_FALLING_EDGE (0x00000003U) /*!< Mask for rising & falling edge set as PVD trigger */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and de-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] + This section provides functions allowing to deinitialize power peripheral. + + [..] + After system reset, the backup domain (RCC Backup domain control register + RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM) + is protected against possible unwanted write accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit(void) +{ +} + +/** + * @brief Enable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @note After a system reset, the backup domain is protected against + * possible unwanted write accesses. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + WRITE_REG(PWR->DBPCR, PWR_DBPCR_DBP); +} + +/** + * @brief Disable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @retval None. + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_REG(PWR->DBPCR); +} +/** + * @} + */ + + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Power Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control Functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power peripheral. + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it + to the internal VREFINT. + + (+) A PVDO flag is available to indicate if VDD is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line 66 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + + (+) The PVD is stopped in STANDBY mode. + + *** Wake-up pin configuration *** + ================================= + [..] + (+) Wake-up pin is used to wake up the system from STANDBY mode. + The pin pull is configurable through the WKUPEPR register to be in + No-pull, Pull-up and Pull-down. + The pin polarity is configurable through the WKUPEPR register to be + active on rising or falling edges. + + (+) There are up to four Wake-up pin in the STM32N6 devices family. + + *** Low Power modes configuration *** + ===================================== + [..] + The device present 3 principles low-power modes : + (+) SLEEP mode : Cortex-M55 is stopped and all PWR domains are remaining + active (Powered and Clocked). + + (+) STOP mode : Cortex-M55 is stopped, clocks are stopped and the + regulator is running. The Main regulator or the LP + regulator could be selected. + + (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE + supply regulator is powered off. + + *** SLEEP mode *** + ================== + [..] + (+) Entry: + The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, + SLEEPEntry) function. + + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction. + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: enter SLEEP mode with WFE instruction + and no clear of pending event. + + -@@- The Regulator parameter is not used for the STM32N6 family + and is kept as parameter just to maintain compatibility with the + lower power families. + + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from SLEEP mode. + + *** STOP mode *** + ================= + [..] + In system STOP mode, the CPU clock is stopped. All CPU subsystem peripheral + clocks are stopped too. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption in STOP mode, FLASH can be powered off before + entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the STOP mode using + the HAL_PWREx_DisableFlashPowerDown() function. + (+) Entry: + The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, + STOPEntry) function with: + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON: Main regulator ON. + This parameter is not used for the STM32N6 family and is kept as parameter + just to maintain compatibility with the lower power families. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: enter STOP mode with WFE instruction + and no clear of pending event. + + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** STANDBY mode *** + ==================== + [..] + (+) + The system STANDBY mode allows to achieve the lowest power consumption. + It is based on the Cortex-M55 deep SLEEP mode, with the voltage regulator + disabled. The system is consequently powered off. The PLL, the HSI + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the RTC registers, RTC backup registers, + backup SRAM and standby circuitry. + + [..] + The voltage regulator is OFF. + + (++) Entry: + (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), + RTC wakeup, tamper event, time stamp event, external reset in NRST + pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an + RTC Wakeup event, a tamper event or a time-stamp event, without + depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes + + (++) To wake up from the STOP mode with an RTC alarm event, it is + necessary to configure the RTC to generate the RTC alarm using the + HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the STOP mode with an RTC Tamper or time stamp event, + it is necessary to configure the RTC to detect the tamper or time + stamp event using the HAL_RTCEx_SetTimeStamp_IT() or + HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the STOP mode with an RTC WakeUp event, it is + necessary to configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the voltage threshold detected by the Programmed Voltage + * Detector (PVD). + * @param pConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the + * PVD configuration information (EventMode). + * @retval None. + */ +void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *pConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_MODE(pConfigPVD->Mode)); + + /* Disable PVD Event/Interrupt */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the PVD in interrupt mode */ + if ((pConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure the PVD in event mode */ + if ((pConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Rising edge configuration */ + if ((pConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + /* Falling edge configuration */ + if ((pConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVDEN); +} + +/** + * @brief Disable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDEN); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which + * sets the default (rising edge): + * @arg PWR_WAKEUP_PIN1, + * PWR_WAKEUP_PIN2, + * PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* + Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge). + */ + SET_BIT(PWR->WKUPEPR, WakeUpPinPolarity); +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1, + * PWR_WAKEUP_PIN2, + * PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, + * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW. + * @retval None. + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable the wake up pin selected */ + CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); +} + +/** + * @brief Get the Wake-Up Pin pending flags. + * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PD2. + * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all + * wake up pins. + * @retval The Wake-Up pin flag. + */ +uint32_t HAL_PWR_GetWakeupFlag(uint32_t WakeUpFlag) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag)); + + /* Return the wake up pin flag */ + return (PWR->WKUPSR & WakeUpFlag); +} + +/** + * @brief Clear the Wake-Up pin pending flag. + * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PD2. + * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from all + * wake up pins. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWR_ClearWakeupFlag(uint32_t WakeUpFlag) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag)); + + /* Clear the wake up event received from wake up pin x */ + WRITE_REG(PWR->WKUPCR, WakeUpFlag); + + /* Check if the wake up event is well cleared */ + if ((PWR->WKUPSR & WakeUpFlag) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Enter the current core in SLEEP mode (CSLEEP). + * @param Regulator : NA in this family project + * Specifies the regulator state in SLEEP mode. + * @note This parameter is not used for the STM32N6 family and is kept as + * parameter just to maintain compatibility with the lower power + * families. + * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE and no clear of pending event before. + * + * @note Ensure to clear pending events before calling this API through + * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select Sleep mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enter the whole system to Stop mode. + * @note This API will enter the system in STOP mode + * @param Regulator : This parameter is not used for this product family. + and is kept as parameter just to maintain compatibility with the + lower power families. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE and no clear of pending event before. + * @note In System STOP mode, all I/O pins keep the same state as in Run mode. + * @note When exiting System STOP mode by issuing an interrupt or a wakeup + * event, the HSI RC oscillator is selected as default system wakeup + * clock. + * @note In System STOP mode, when the voltage regulator operates in low + * power mode, an additional startup delay is incurred when the system + * is waking up. By keeping the internal regulator ON during STOP mode, + * the consumption is higher although the startup time is reduced. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select Stop mode when device enters Deepsleep */ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB(); + __ISB(); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ + __WFE(); + } + + /* Clear SLEEPDEEP bit of Cortex-M55 in the System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enter the whole system to Standby mode. + * @note The Standby mode allows achieving the lowest power consumption. + * @note When the system enters in Standby mode, the voltage regulator is disabled. + * The complete VCORE domain is consequently powered off. + * The PLLs, HSI oscillator, CSI oscillator, HSI48 and the HSE oscillator are + * also switched off. + * SRAM and register contents are lost except for backup domain registers + * (RTC registers, RTC backup register and backup RAM), and Standby circuitry. + * @note When the System exit STANDBY mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock. + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby when device enters Deepsleep */ + SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STANDBY mode */ + __DSB(); + __ISB(); + + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex-M55 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * @retval None. + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex-M55 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEV-ON-PEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-M55. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex-M55 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-M55. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex-M55 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief PWR PVD interrupt Rising callback + * @retval None + */ +__weak void HAL_PWR_PVD_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR PVD interrupt Falling callback + * @retval None + */ +__weak void HAL_PWR_PVD_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + */ +} + +/** + * @brief This function handles the PWR WAKEUP PIN interrupt request. + * @note This API should be called under the WAKEUP_PIN_IRQHandler(). + * @retval None. + */ +void HAL_PWR_WAKEUP_PIN_IRQHandler(void) +{ + /* Wakeup pin EXTI line interrupt detected */ + if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF1) != 0U) + { + /* Clear PWR WKUPF1 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP1); + + /* PWR WKUP1 interrupt user callback */ + HAL_PWR_WKUP1_Callback(); + } + + if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF2) != 0U) + { + /* Clear PWR WKUPF2 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP2); + + /* PWR WKUP2 interrupt user callback */ + HAL_PWR_WKUP2_Callback(); + } + + if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF3) != 0U) + { + /* Clear PWR WKUPF3 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP3); + + /* PWR WKUP3 interrupt user callback */ + HAL_PWR_WKUP3_Callback(); + } + + if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF4) != 0U) + { + /* Clear PWR WKUPF4 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP4); + + /* PWR WKUP4 interrupt user callback */ + HAL_PWR_WKUP4_Callback(); + } +} + +/** + * @brief PWR WKUP1 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP1_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP1_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP2 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP2_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP2_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP3 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP3_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP3_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP4 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP4_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP4_Callback can be implemented in the user file + */ +} + +/** + * @} + */ +#if defined(PWR_PRIVCFGR_PRIV0) +/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions + * @brief Attributes management functions + * +@verbatim + =============================================================================== + ##### PWR Attributes Functions ##### + =============================================================================== + [..] + The PWR is able to protect register bits from being modified by non-secure + and unprivileged accesses. + The protection can be activated for the following features through PWR_SECCFGR and + PWR_PRIVCFGR: + + (++) System supply configuration. + (++) Voltage scaling. + (++) Low-power mode. + (++) Wake-up (WKUP) pins. + (++) Voltage detection and monitoring. + (++) VBAT mode. + + A non-secure access to a secure-protected register bit is denied : + (++) The secured bits are not written (WI) with a non-secure write access. + (++) The secured bits are read as 0 (RAZ) with a non-secure read access. + + [..] + After any application reset or system reset, the PWR does not filter any access + (default configuration: non-secure, any privileged) until the trusted agent has + programmed the security and privileged protection. + + [..] Secure/non-secure access filtering + To enable the filtering access based on this attribute, the authorized master + agent must set SECx in PWR_SECCFGR related to the PWR feature. + + When a register is configured as secure, read and write operations are only + allowed by a secure access. + Non-secure read or write accesses are denied (RAZ/WI). + An illegal secure access event is generated to the IAC (illegal access controller). + There is no bus error generated. + When a register is configured as non-secure, read and write operations are + allowed by both secure and non-secure accesses. + + [..] Privileged/unprivileged access filtering + To enable the filtering access based on this attribute, the authorized master + agent has to set PRIVx in PWR_PRIVCFGR related to the PWR feature. + When a register is configured as privileged, read and write operations are only + allowed by a privileged access. + Unprivileged read or write accesses are denied (RAZ/WI). + An illegal privileged access event is generated to the IAC. + There is no bus error generated. + When a register is configured as unprivileged, read and write operations are + allowed by both privileged and unprivileged accesses. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the PWR item attributes. + * @note Available attributes are security and privilege protection. + * @note Security attribute can only be set only by secure access. + * @note Privilege attribute for secure items can be managed only by a secure + * privileged access. + * @note Privilege attribute for nsecure items can be managed by a secure + * privileged access or by a nsecure privileged access. + * @param Item : Specifies the item(s) to set attributes on. + * This parameter can be a combination of PWR_ITEMS. + * @param Attributes : Specifies the available attribute(s). + * This parameter can be one of PWR_ATTRIBUTES. + * @retval None. + */ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + /* Check the parameters */ + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); + assert_param(IS_PWR_ATTRIBUTES(Attributes)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure item management (TZEN = 1) */ + if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV) + { + SET_BIT(PWR_S->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, Item); + } + else + { + SET_BIT(PWR_S->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, Item); + } + } + /* NSecure item management */ + else + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + CLEAR_BIT(PWR_S->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, Item); + } + else + { + CLEAR_BIT(PWR_S->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, Item); + } + } +#else + /* NSecure item management (TZEN = 0) */ + if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + SET_BIT(PWR->PRIVCFGR, Item); + } + else + { + CLEAR_BIT(PWR->PRIVCFGR, Item); + } + } +#endif /* __ARM_FEATURE_CMSE */ +} + + +/** + * @brief Get attribute(s) of a PWR item. + * @param Item : Specifies the item(s) to get attributes on. + * This parameter can be one of PWR_ITEMS. + * @param pAttributes : Pointer to return attribute(s). + * Returned value could be on of PWR_ATTRIBUTES. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes; + + /* Check attribute pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Check item security */ + if ((PWR->SECCFGR & Item) == Item) + { + if ((PWR->PRIVCFGR & Item) == Item) + { + attributes = PWR_SEC_PRIV; + } + else + { + attributes = PWR_SEC_NPRIV; + } + } + else + { + if ((PWR->PRIVCFGR & Item) == Item) + { + attributes = PWR_NSEC_PRIV; + } + else + { + attributes = PWR_NSEC_NPRIV; + } + } +#else + if ((PWR->PRIVCFGR & Item) == Item) + { + attributes = PWR_NSEC_PRIV; + } + else + { + attributes = PWR_NSEC_NPRIV; + } +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pAttributes = attributes; + + return HAL_OK; +} +/** + * @} + */ +#endif /* #if defined(PWR_PRIVCFGR_PRIV0) */ + +/** + * @} + */ +#endif /* defined (HAL_PWR_MODULE_ENABLED) */ +/** + * @} + */ + +/** + * @} + */ + Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr_ex.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr_ex.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr_ex.c (revision 16) @@ -0,0 +1,1798 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller extension peripheral : + * + Power Supply Control Functions + * + Low Power Control Functions + * + Voltage Monitoring Functions + * + Memories Retention Functions + * + I/O Pull-Up Pull-Down Configuration Functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply + with the following different setups according to hardware: + (+) PWR_SMPS_SUPPLY + (+) PWR_EXTERNAL_SOURCE_SUPPLY + + (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup. + + (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main + internal regulator output voltage. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_VOLTAGE_SCALE0 + (+) PWR_REGULATOR_VOLTAGE_SCALE1 + + (#) Call HAL_PWREx_GetVoltageRange() function to get the current output + voltage applied to the main regulator. + + (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the main + internal regulator output voltage in STOP mode. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE3 + (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE5 + + (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current output + voltage applied to the main regulator in STOP mode. + + (#) Call HAL_PWREx_EnableWakeUpPin() functions to enable the Wake-up pin + functionality for the selected pin. + + (#) Call HAL_PWREx_EnableBkupRAMRetention() and HAL_PWREx_DisableBkupRAMRetention() + functions to enable and disable BKPSRAM retention in Standby mode. + + (#) Call HAL_PWREx_EnableTCMRetention() and HAL_PWREx_DisableTCMRetention() functions + to enable and disable the I-TCM and D-TCM RAMs retention in Standby mode. + + (#) Call HAL_PWREx_EnableTCMFLXRetention() and HAL_PWREx_DisableTCMFLXRetention() + functions to enable and disable the I-TCM FLEXMEM retention in Standby mode. + + (#) Call HAL_PWREx_SetPulseLow() function to configure the minimum guaranteed + duration of the pwr_on low pulse in Standby mode ( between ~ 0 -> 31 ms). + + (#) Call HAL_PWREx_GetPulseLow() function to get the minimum guaranteed + duration of the pwr_on low pulse in Standby mode. + + (#) Call HAL_PWREx_EnableTCMFLXRetention() and HAL_PWREx_DisableTCMFLXRetention() + functions to enable and disable the I-TCM FLEXMEM retention in Standby mode. + + (#) Call HAL_PWREx_EnableSMPSPWM() and HAL_PWREx_DisableSMPSPWM() functions to + enable and disable the SMPS low-power mode in Stop SVOS range 3. + + (#) Call HAL_PWREx_EnablePullDownOutput() and HAL_PWREx_DisablePullDownOutput() + functions to enable and disable the pull down on output voltage during + power-down mode. + + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() + functions to enable and disable the VBAT and Temperature monitoring. + When VBAT and Temperature monitoring feature is enables, use + HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get + respectively the Temperature level and VBAT level. + + (#) Call HAL_PWREx_EnableVDDCOREMonitoring() and HAL_PWREx_EnableVDDCOREMonitoring() + functions to enable and disable the VCORE monitoring. + When VDDCORE monitoring feature is enables, use HAL_PWREx_GetVDDCORELevel() + function to get the current VDDCORE level. + + (#) Call HAL_PWREx_ConfigVDDCORELevel() function to configure the VDDCORE + voltage detector low-level selection. + + (#) Call HAL_PWREx_ConfigVddIORange() functions to configure the Vdd IO range: + (+) PWR_VDDIO + (+) PWR_VDDIO2 + (+) PWR_VDDIO3 + (+) PWR_VDDIO4 + (+) PWR_VDDIO5 + The voltage range setting could be one of the following values: + (+) PWR_VDDIO_RANGE_3V3 + (+) PWR_VDDIO_RANGE_1V8 + + (#) Call HAL_PWREx_GetVddIORange() function to get the current + voltage range setting on the selected Vdd IO. + + (#) Call HAL_PWREx_EnableVddIO4RangeSTBY() and HAL_PWREx_DisableVddIO4RangeSTBY() + functions to enable and disable the VDD IO4 voltage range Standby mode. + + (#) Call HAL_PWREx_EnableVddIO5RangeSTBY() and HAL_PWREx_DisableVddIO5RangeSTBY() + functions to enable and disable the VDD IO5 voltage range Standby mode. + + (#) Call HAL_PWREx_EnableVddUSB() and HAL_PWREx_DisableVddUSB() + functions to enable and disable the VDD33USB supply valid. + + (#) Call HAL_PWREx_EnableVddIO2() and HAL_PWREx_DisableVddIO2() + functions to enable and disable the VDDIO2 supply valid. + + (#) Call HAL_PWREx_EnableVddIO3() and HAL_PWREx_DisableVddIO3() + functions to enable and disable the VDDIO3 supply valid. + + (#) Call HAL_PWREx_EnableVddIO4() and HAL_PWREx_DisableVddIO4() + functions to enable and disable the VDDIO4 supply valid. + + (#) Call HAL_PWREx_EnableVddIO5() and HAL_PWREx_DisableVddIO5() + functions to enable and disable the VDDIO5 supply valid. + + (#) Call HAL_PWREx_EnableVddA() and HAL_PWREx_DisableVddA() + functions to enable and disable the VDDA18ADC supply valid. + + (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured + (event mode and PVD type) in order to set up the Peripheral Voltage + Monitor, then use HAL_PWREx_EnableVddUSBVMEN(), HAL_PWREx_EnableVddIO2VMEN(), + HAL_PWREx_EnableVddIO3VMEN(), HAL_PWREx_EnableVddIO4VMEN(), + HAL_PWREx_EnableVddIO5VMEN() and HAL_PWREx_EnableVddAVMEN() functions to + start the PVM VDDx monitoring. + Use HAL_PWREx_DisableVddUSBVMEN(), HAL_PWREx_DisableVddIO2VMEN(), + HAL_PWREx_DisableVddIO3VMEN(), HAL_PWREx_DisableVddIO4VMEN(), + HAL_PWREx_DisableVddIO5VMEN() and HAL_PWREx_DisableVddAVMEN() to stop + the PVM VDDx monitoring. + (+) PVM monitored voltages are : + (++) VDDUSB + (++) VDDIO2 + (++) VDDIO3 + (++) VDDIO4 + (++) VDDIO5 + (++) VDDA + + (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and + PVM interrupt request. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#if defined (HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value + * @{ + */ +#define PWR_FLAG_SETTING_DELAY (1000U) +/** + * @} + */ + +/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets + * @{ + */ +/* Wake-Up Pins EXTI register mask */ +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM60 | EXTI_IMR2_IM61 |\ + EXTI_IMR2_IM62 | EXTI_IMR2_IM63 ) + +/* Wake-Up Pins PWR Pin Pull shift offsets */ +#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) +/** + * @} + */ + +/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +#define PVM_RISING_EDGE (1U) /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE (2U) /*!< Mask for falling edge set as PVM trigger */ +#define PVM_MODE_IT (4U) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_MODE_EVT (8U) /*!< Mask for event yielded by PVM threshold crossing */ +/** + * @} + */ + +/** @defgroup PWR_VDDCOREVM_Mode_Mask PWR VddCORE VM Mode Mask + * @{ + */ +#define VDDCOREVM_RISING_EDGE (1U) /*!< Mask for rising edge set as PVM trigger */ +#define VDDCOREVM_FALLING_EDGE (2U) /*!< Mask for falling edge set as PVM trigger */ +#define VDDCOREVM_MODE_IT (4U) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define VDDCOREVM_MODE_EVT (8U) /*!< Mask for event yielded by PVM threshold crossing */ +/** + * @} + */ + + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power supply. + + (+) The STM32N6 series devices allows two different supply configurations: + Direct SMPS supply and external supply. + + (#) After a system reset, the software must configure the used supply configuration + in PWR_CR1 using HAL_PWREx_ConfigSupply() function before changing VOS in PWR_VOSCR, + or the RCC sys_ck frequency. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg @ref PWR_SMPS_SUPPLY : VCORE power domains are supplied + * from SMPS step-down converter + * according to VOS. + * @arg @ref PWR_EXTERNAL_SOURCE_SUPPLY : VCORE supplied from external source. + * SMPS step-down converter disabled. + * @note: The power supply configuration can be written only one time after POR. + * @note: The power supply configuration is not reset by wakeup from Standby mode and + * application reset, but only reset by VDD POR. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_PWR_SUPPLY(SupplySource)); + + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR1, PWR_SUPPLY_CONFIG_MASK, SupplySource); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till voltage level flag is set */ + while ((PWR->VOSCR & PWR_VOSCR_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configuration. + */ +uint32_t HAL_PWREx_GetSupplyConfig(void) +{ + return (PWR->CR1 & PWR_SUPPLY_CONFIG_MASK); +} + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling : Specifies the regulator output voltage to achieve + * a tradeoff between performance and power + * consumption. + * This parameter can be one of the following values : + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage scaling range 0 (highest frequency). + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage scaling range 1 (lowest power). + * @note After reset, the system starts from HSI with VOS low. + * @note When increasing the performance, the voltage scaling must be changed + * before increasing the system frequency. + * When decreasing performance, the system frequency must first be decreased + * before changing the voltage scaling. + * @note When exiting from Stop mode or Standby mode, the Run mode voltage + * scaling is reset to the default VOS low value. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Set the voltage range */ + MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till voltage level flag is set */ + while ((PWR->VOSCR & PWR_VOSCR_VOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @retval The current applied VOS selection. + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + /* Get the active voltage scaling */ + return ((PWR->VOSCR & PWR_VOSCR_ACTVOS) >> PWR_VOSCR_ACTVOS_Pos); +} + +/** + * @brief Configure the main internal regulator output voltage in STOP mode. + * @param VoltageScaling : Specifies the regulator output voltage when the + * system enters Stop mode to achieve a tradeoff between performance + * and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE3 : System Stop mode voltage scaling range 3 (highest frequency). + * @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE5 : System Stop mode voltage scaling range 5 (lowest power). + * @retval None. + */ +void HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Return the stop mode voltage range */ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling); +} + +/** + * @brief Get the main internal regulator output voltage in STOP mode. + * @retval The actual applied SVOS selection. + */ +uint32_t HAL_PWREx_GetStopModeVoltageRange(void) +{ + /* Return the stop voltage scaling */ + return (PWR->CPUCR & PWR_CPUCR_SVOS); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group2 Wakeup Pins configuration functions + * @brief Wakeup Pins configuration functions + * +@verbatim + =============================================================================== + ##### Wakeup Pins configuration functions ##### + =============================================================================== + [..] + + *** Wakeup Pins configuration **** + =================================== + [..] + Wakeup pins allow the system to exit from Standby mode. The configuration + of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) + function with: + (+) sPinParams: structure to enable and configure a wakeup pin: + (++) WakeUpPin: Wakeup pin to be enabled. + (++) PinPolarity: Wakeup pin polarity (rising or falling edge). + (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down). + [..] + The wakeup pins are internally connected to the EXTI lines [60-63] to + generate an interrupt if enabled. + [..] + When a wakeup pin event is received the HAL_PWR_WAKEUP_PIN_IRQHandler is + called and the appropriate flag is set in the PWR_WKUPSR register. Then in + the HAL_PWR_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be + cleared and the appropriate user callback will be called. The user can add + his own code by customization of function pointer HAL_PWR_WKUPx_Callback. + +@endverbatim + * @{ + */ +/** + * @brief Enable the Wake-up PINx functionality. + * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that + * contains the configuration information for the wake-up + * Pin. + * @retval None. + */ +void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams) +{ + uint32_t pinConfig; + uint32_t regMask; + const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1; + + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin)); + assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity)); + assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull)); + + pinConfig = sPinParams->WakeUpPin | \ + (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \ + (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + \ + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU)); + + regMask = sPinParams->WakeUpPin | \ + (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU)); + + /* Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge) */ + MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig); + + /* Configure the Wakeup Pin EXTI Line */ + MODIFY_REG(EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM60_Pos)); +} +/** + * @} + */ + + +/** @defgroup PWREx_Exported_Functions_Group3 Memories Retention Functions + * @brief Memories Retention Functions + * +@verbatim + =============================================================================== + ##### Memories Retention Functions ##### + =============================================================================== + [..] + + *** Backup RAM (BKPSRAM) retention **** + ======================================= + [..] + By default the content of BKPSRAM memories aren't retained in Standby mode. + By setting the BKPRBSEN bit in the PWR_BDCR2 register using the + HAL_PWREx_EnableBkupRAMRetention() function, the content of these memories + are retained even in Standby mode. + + *** TCM RAMs and I-TCM FLEXMEM retention **** + ======================================= + [..] + By default the content of TCM RAMs and I-TCM FLEXMEM aren't retained in + Standby mode. + + By setting the TCMRBSEN bit in the PWR_CR4 register using the + HAL_PWREx_EnableTCMRetention() function, the content of these memories + are retained even in Standby mode. + + By setting the TCMFLXRBSEN bit in the PWR_CR4 register using the + HAL_PWREx_EnableTCMFLXRetention () function, the content of these memories + are retained even in Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Backup RAM retention in Standby and VBAT modes. + * @note After reset, PWR_BDCR2 is write-protected. + * DBP must be set in PWR_DBPCR to disable the write protection. + * @retval None. + */ +void HAL_PWREx_EnableBkupRAMRetention(void) +{ + SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); +} + +/** + * @brief Disable the Backup RAM retention in Standby and VBAT modes. + * @note After reset, PWR_BDCR2 is write-protected. + * DBP must be set in PWR_DBPCR to disable the write protection. + * @retval None. + */ +void HAL_PWREx_DisableBkupRAMRetention(void) +{ + CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); +} + +/** + * @brief Enable the TCM RAMs retention in Standby mode. + * @retval None. + */ +void HAL_PWREx_EnableTCMRetention(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_TCMRBSEN); +} + +/** + * @brief Disable the TCM RAMs retention in Standby mode. + * @retval None. + */ +void HAL_PWREx_DisableTCMRetention(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_TCMRBSEN); +} + +/** + * @brief Enable the I-TCM FLEXMEM retention in Standby mode. + * @retval None. + */ +void HAL_PWREx_EnableTCMFLXRetention(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN); +} + +/** + * @brief Disable the I-TCM FLEXMEM retention in Standby mode. + * @retval None. + */ +void HAL_PWREx_DisableTCMFLXRetention(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN); +} +/** + * @} + */ + + +/** @defgroup PWREx_Exported_Functions_Group4 Low Power Control Functions + * @brief Low Power Control Functions + * +@verbatim + =============================================================================== + ##### Low Power Control Functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Configure the pwr_on pulse low configuration. + * @param Pulselowtime : Specifies minimum guaranteed duration of + the pwr_on low pulse in Standby mode. + * This parameter can be a value between 0 and 31: + * 0: No guaranteed minimum low time. + * 1: 1* 32 LSI cycles= ~ 1 ms guaranteed minimum low time. + * X: X* 32 LSI cycles= ~ X ms guaranteed minimum low time. + * @retval None. + */ +void HAL_PWREx_SetPulseLow(uint32_t Pulselowtime) +{ + assert_param(IS_PWR_PULSE_LOW_TIME(Pulselowtime)); + + /* Set the pwr_on pulse low configuration */ + MODIFY_REG(PWR->CR1, PWR_CR1_POPL_Msk, (Pulselowtime << PWR_CR1_POPL_Pos)); +} + +/** + * @brief Get the pwr_on pulse low configuration. + * @retval The actual applied minimum guaranteed duration of the + * pwr_on low pulse in Standby mode. + */ +uint32_t HAL_PWREx_GetPulseLow(void) +{ + /* Return the stop voltage scaling */ + return ((PWR->CR1 & PWR_CR1_POPL_Msk) >> PWR_CR1_POPL_Pos); +} + +/** + * @brief Enable SMPS low-power mode (SVOS range 3 only). + * @note LPDS08V bit is used to keep the SMPS in PWM mode (MR) in Stop SVOS range 3. + * @retval None. + */ +void HAL_PWREx_EnableSMPSPWM(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_LPDS08V); +} + +/** + * @brief Disable SMPS low-power mode (SVOS range 3 only). + * @retval None. + */ +void HAL_PWREx_DisableSMPSPWM(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS08V); +} + +/** + * @brief Enable the pull down on output voltage during power-down mode. + * @retval None. + */ +void HAL_PWREx_EnablePullDownOutput(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_MODE_PDN); +} + +/** + * @brief Disable the pull down on output voltage during power-down mode. + * @retval None. + */ +void HAL_PWREx_DisablePullDownOutput(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_MODE_PDN); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group5 Power Monitoring functions + * @brief Power Monitoring functions + * +@verbatim + =============================================================================== + ##### Power Monitoring functions ##### + =============================================================================== + + *** VBAT and Temperature supervision *** + ======================================== + [..] + (+) The VBAT battery voltage supply can be monitored by comparing it with + two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags + in the PWR control register 2 (PWR_BDCR1), indicate if VBAT is higher or + lower than the threshold. + (+) The temperature can be monitored by comparing it with two threshold + levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR + control register 2 (PWR_BDCR1), indicate whether the device temperature + is higher or lower than the threshold. + (+) The VBAT and the temperature monitoring is enabled by + HAL_PWREx_EnableMonitoring() function and disabled by + HAL_PWREx_DisableMonitoring() function. + (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can + be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or + PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD. + (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature + level which can be : + PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or + PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the VBAT and temperature monitoring. + * @note After reset, PWR_BDCR1 is write-protected. + * DBP must be set in PWR_DBPCR to disable the write protection. + * @retval HAL status. + */ +void HAL_PWREx_EnableMonitoring(void) +{ + /* Enable the VBAT and Temperature monitoring */ + SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +/** + * @brief Disable the VBAT and temperature monitoring. + * @note After reset, PWR_BDCR1 is write-protected. + * DBP must be set in PWR_DBPCR to disable the write protection. + * @retval HAL status. + */ +void HAL_PWREx_DisableMonitoring(void) +{ + /* Disable the VBAT and Temperature monitoring */ + CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); +} + +/** + * @brief Indicate whether the junction temperature is between, above or below + * the thresholds. + * @retval Temperature level. + */ +uint32_t HAL_PWREx_GetTemperatureLevel(void) +{ + uint32_t tempLevel; + uint32_t regValue; + + /* Read the temperature flags */ + regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_TEMPH | PWR_BDCR1_TEMPL)); + + /* Check if the temperature is below the threshold */ + if (regValue == PWR_BDCR1_TEMPL) + { + tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD; + } + /* Check if the temperature is above the threshold */ + else if (regValue == PWR_BDCR1_TEMPH) + { + tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD; + } + /* The temperature is between the thresholds */ + else + { + tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return tempLevel; +} + +/** + * @brief Indicate whether the Battery voltage level is between, above or below + * the thresholds. + * @retval VBAT level. + */ +uint32_t HAL_PWREx_GetVBATLevel(void) +{ + uint32_t vbatLevel; + uint32_t regValue; + + /* Read the VBAT flags */ + regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_VBATH | PWR_BDCR1_VBATL)); + + /* Check if the VBAT is below the threshold */ + if (regValue == PWR_BDCR1_VBATL) + { + vbatLevel = PWR_VBAT_BELOW_LOW_THRESHOLD; + } + /* Check if the VBAT is above the threshold */ + else if (regValue == PWR_BDCR1_VBATH) + { + vbatLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD; + } + /* The VBAT is between the thresholds */ + else + { + vbatLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return vbatLevel; +} + +/** + * @brief Enable the VDDCORE monitoring. + * @retval HAL status. + */ +void HAL_PWREx_EnableVDDCOREMonitoring(void) +{ + /* Enable the VDDCORE monitoring */ + SET_BIT(PWR->CR3, PWR_CR3_VCOREMONEN); +} + +/** + * @brief Disable the VDDCORE monitoring. + * @retval HAL status. + */ +void HAL_PWREx_DisableVDDCOREMonitoring(void) +{ + /* Disable the VDDCORE monitoring */ + CLEAR_BIT(PWR->CR3, PWR_CR3_VCOREMONEN); +} + +/** + * @brief Configure the VDDCORE voltage detector low-level selection. + * @param pConfigVddCOREVM : Pointer to a PWR_VddCOREVMTypeDef structure that contains the + * PVM configuration information (LowVoltageThreshold and Mode). + * @retval None. + */ +void HAL_PWREx_ConfigVDDCOREVM(const PWR_VddCOREVMTypeDef *pConfigVddCOREVM) +{ + assert_param(IS_PWR_VDDCOREVM_LEVEL(pConfigVddCOREVM->LowVoltageThreshold)); + assert_param(IS_PWR_VDDCOREVM_MODE(pConfigVddCOREVM->Mode)); + + /* Disable VDDCORE monitoring Event/Interrupt */ + __HAL_PWR_VCOREVM_EXTI_DISABLE_EVENT(); + __HAL_PWR_VCOREVM_EXTI_DISABLE_IT(); + __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_VCOREVM_EXTI_DISABLE_FALLING_EDGE(); + + /* Set the VDDCORE voltage detector low-level selection */ + MODIFY_REG(PWR->CR3, PWR_CR3_VCORELLS_Msk, pConfigVddCOREVM->LowVoltageThreshold); + + /* Configure the VDDCORE monitoring in interrupt mode */ + if ((pConfigVddCOREVM->Mode & VDDCOREVM_MODE_IT) == VDDCOREVM_MODE_IT) + { + __HAL_PWR_VCOREVM_EXTI_ENABLE_IT(); + } + + /* Configure the VDDCORE monitoring in event mode */ + if ((pConfigVddCOREVM->Mode & VDDCOREVM_MODE_EVT) == VDDCOREVM_MODE_EVT) + { + __HAL_PWR_VCOREVM_EXTI_ENABLE_EVENT(); + } + + /* Rising edge configuration */ + if ((pConfigVddCOREVM->Mode & VDDCOREVM_RISING_EDGE) == VDDCOREVM_RISING_EDGE) + { + __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Falling edge configuration */ + if ((pConfigVddCOREVM->Mode & VDDCOREVM_FALLING_EDGE) == VDDCOREVM_FALLING_EDGE) + { + __HAL_PWR_VCOREVM_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Indicate whether the VDDCORE level is between, above or below + * the thresholds. + * @retval VDDCORE level. + */ +uint32_t HAL_PWREx_GetVDDCORELevel(void) +{ + uint32_t vcoreLevel; + uint32_t regValue; + + /* Read the VCORE flags */ + regValue = READ_BIT(PWR->CR3, (PWR_CR3_VCOREH | PWR_CR3_VCOREL)); + + /* Check if the VCORE is below the threshold */ + if (regValue == PWR_CR3_VCOREL) + { + vcoreLevel = PWR_VDDCORE_BELOW_LOW_THRESHOLD; + } + /* Check if the VCORE is above the threshold */ + else if (regValue == PWR_CR3_VCOREH) + { + vcoreLevel = PWR_VDDCORE_ABOVE_HIGH_THRESHOLD; + } + /* The VCORE is between the thresholds */ + else + { + vcoreLevel = PWR_VDDCORE_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return vcoreLevel; +} + +/** + * @brief Configure the VDD I/O voltage range. + * @param VddIOPort VDD I/O + * This parameter can be one of the following values: + * @arg @ref PWR_VDDIO Vdd IO + * @arg @ref PWR_VDDIO2 Vdd IO2 + * @arg @ref PWR_VDDIO3 Vdd IO3 + * @arg @ref PWR_VDDIO4 Vdd IO4 + * @arg @ref PWR_VDDIO5 Vdd IO5 + * @param VoltageRange Voltage range + * This parameter can be one of the following values: + * @arg @ref PWR_VDDIO_RANGE_3V3 3v3 voltage range + * @arg @ref PWR_VDDIO_RANGE_1V8 1v8 voltage range + * @note HSLV_VDDIOx option bit must be set to allow 1v8 voltage + * range operation. + * @note Setting this configuration while VDDIOx is in 3v3 range + * damages the device. + * @retval None. + */ +void HAL_PWREx_ConfigVddIORange(uint32_t VddIOPort, uint32_t VoltageRange) +{ + /* Check the parameters */ + assert_param(IS_PWR_VDDIO(VddIOPort)); + assert_param(IS_PWR_VDDIO_RANGE(VoltageRange)); + + switch (VddIOPort) + { + case PWR_VDDIO: + MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL, VoltageRange << PWR_SVMCR3_VDDIOVRSEL_Pos); + break; + + case PWR_VDDIO2: + MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL, VoltageRange << PWR_SVMCR3_VDDIO2VRSEL_Pos); + break; + + case PWR_VDDIO3: + MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL, VoltageRange << PWR_SVMCR3_VDDIO3VRSEL_Pos); + break; + + case PWR_VDDIO4: + MODIFY_REG(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL, VoltageRange << PWR_SVMCR1_VDDIO4VRSEL_Pos); + break; + + case PWR_VDDIO5: + MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos); + break; + + default: + break; + } +} + +/** + * @brief Configure the VDD I/O voltage range. + * @param VddIOPort VDD I/O + * This parameter can be one of the following values: + * @arg @ref PWR_VDDIO Vdd IO + * @arg @ref PWR_VDDIO2 Vdd IO2 + * @arg @ref PWR_VDDIO3 Vdd IO3 + * @arg @ref PWR_VDDIO4 Vdd IO4 + * @arg @ref PWR_VDDIO5 Vdd IO5 + * @retval The voltage range: + * @arg @ref PWR_VDDIO_RANGE_3V3 3v3 voltage range + * @arg @ref PWR_VDDIO_RANGE_1V8 1v8 voltage range + */ +uint32_t HAL_PWREx_GetVddIORange(uint32_t VddIOPort) +{ + uint32_t voltage_range = 0U; + + /* Check the parameters */ + assert_param(IS_PWR_VDDIO(VddIOPort)); + + switch (VddIOPort) + { + case PWR_VDDIO: + voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL) >> PWR_SVMCR3_VDDIOVRSEL_Pos); + break; + + case PWR_VDDIO2: + voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL) >> PWR_SVMCR3_VDDIO2VRSEL_Pos); + break; + + case PWR_VDDIO3: + voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL) >> PWR_SVMCR3_VDDIO3VRSEL_Pos); + break; + + case PWR_VDDIO4: + voltage_range = (READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL) >> PWR_SVMCR1_VDDIO4VRSEL_Pos); + break; + + case PWR_VDDIO5: + voltage_range = (READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos); + break; + + default: + break; + } + return voltage_range; +} + +/** + * @brief Enable VDD IO4 voltage range Standby mode. + * @note When this bit is set, the VDDIO4VRSEL configuration + * is retained in Standby mode. + * @note This bit must be set if the VDDIO4 is in 1v8 range + * in Standby mode, and when exiting Standby mode. + * @note It must not be set when VDDIO4 is in 3v3 range in + * Standby mode, or when exiting Standby mode. + * @retval None. + */ +void HAL_PWREx_EnableVddIO4RangeSTBY(void) +{ + SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY); +} + +/** + * @brief Disable VDD IO4 voltage range Standby mode. + * @retval None. + */ +void HAL_PWREx_DisableVddIO4RangeSTBY(void) +{ + CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY); +} + +/** + * @brief Enable VDD IO5 voltage range Standby mode. + * @note When this bit is set, the VDDIO5VRSEL configuration + * is retained in Standby mode. + * @note This bit must be set if the VDDIO5 is in 1v8 range + * in Standby mode, and when exiting Standby mode. + * @note It must not be set when VDDIO5 is in 3v3 range in + * Standby mode, or when exiting Standby mode. + * @retval None. + */ +void HAL_PWREx_EnableVddIO5RangeSTBY(void) +{ + SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); +} + +/** + * @brief Disable VDD IO5 voltage range Standby mode. + * @retval None. + */ +void HAL_PWREx_DisableVddIO5RangeSTBY(void) +{ + CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); +} + +/** + * @brief Enable VDDUSB supply valid. + * @note Setting this bit is mandatory to use the USB2 HS PHYs. + * is present for consumption saving. + * @retval None. + */ +void HAL_PWREx_EnableVddUSB(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV); +} + +/** + * @brief Disable VDDUSB supply valid. + * @retval None. + */ +void HAL_PWREx_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV); +} + +/** + * @brief Enable VDDIO2 supply valid. + * @note Setting this bit is mandatory to use PO[5:0] and PP[15:0] I/Os. + * @retval None. + */ +void HAL_PWREx_EnableVddIO2(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV); +} + +/** + * @brief Disable VDDIO2 supply valid. + * @retval None. + */ +void HAL_PWREx_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV); +} + +/** + * @brief Enable VDDIO3 supply valid. + * @note Setting this bit is mandatory to use PN[12:0] I/Os. + * @retval None. + */ +void HAL_PWREx_EnableVddIO3(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV); +} + +/** + * @brief Disable VDDIO3 supply valid. + * @retval None. + */ +void HAL_PWREx_DisableVddIO3(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV); +} + +/** + * @brief Enable VDDIO4 supply valid. + * @note Setting this bit is mandatory to use PB[9,8], PC[12:6], and PD[2] I/Os. + * @retval None. + */ +void HAL_PWREx_EnableVddIO4(void) +{ + SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV); +} + +/** + * @brief Disable VDDIO4 supply valid. + * @retval None. + */ +void HAL_PWREx_DisableVddIO4(void) +{ + CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV); +} + +/** + * @brief Enable VDDIO5 supply valid. + * @note Setting this bit is mandatory to use PN[12:0] I/Os. + * @retval None. + */ +void HAL_PWREx_EnableVddIO5(void) +{ + SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); +} + +/** + * @brief Disable VDDIO5 supply valid. + * @retval None. + */ +void HAL_PWREx_DisableVddIO5(void) +{ + CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); +} + +/** + * @brief Enable VDDA supply valid. + * @note Setting this bit is mandatory to use the analog to digital converters. + * @retval None. + */ +void HAL_PWREx_EnableVddA(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV); +} + +/** + * @brief Disable VDDA supply valid. + * @retval None. + */ +void HAL_PWREx_DisableVddA(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV); +} + +/** + * @brief Enable the VDD33USB independent USB 33 voltage monitor. + * @retval None. + */ +void HAL_PWREx_EnableVddUSBVMEN(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN); +} + +/** + * @brief Disable the VDD33USB independent USB 33 voltage monitor. + * @retval None. + */ +void HAL_PWREx_DisableVddUSBVMEN(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN); +} + +/** + * @brief Enable the VDDIO2 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_EnableVddIO2VMEN(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN); +} + +/** + * @brief Disable the VDDIO2 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_DisableVddIO2VMEN(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN); +} + +/** + * @brief Enable the VDDIO3 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_EnableVddIO3VMEN(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN); +} + +/** + * @brief Disable the VDDIO3 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_DisableVddIO3VMEN(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN); +} + +/** + * @brief Enable the VDDIO4 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_EnableVddIO4VMEN(void) +{ + SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN); +} + +/** + * @brief Disable the VDDIO4 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_DisableVddIO4VMEN(void) +{ + CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN); +} + +/** + * @brief Enable the VDDIO5 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_EnableVddIO5VMEN(void) +{ + SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); +} + +/** + * @brief Disable the VDDIO5 independent voltage monitor. + * @retval None. + */ +void HAL_PWREx_DisableVddIO5VMEN(void) +{ + CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); +} + +/** + * @brief Enable the VDDA18ADC independent ADC voltage monitor. + * @retval None. + */ +void HAL_PWREx_EnableVddAVMEN(void) +{ + SET_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN); +} + +/** + * @brief Disable the VDDA18ADC independent ADC voltage monitor. + * @retval None. + */ +void HAL_PWREx_DisableVddAVMEN(void) +{ + CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN); +} + +/** + * @brief Configure the voltage monitor threshold detected by the Peripheral + * voltage monitoring (PVM). + * @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the + * PVM configuration information (PVMType and EventMode). + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *pConfigPVM) +{ + + /* Check the parameters */ + assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType)); + assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode)); + + /* Check the peripheral voltage monitor type */ + switch (pConfigPVM->PVMType) + { + case PWR_VDDUSB_VM: /* Independent USB voltage monitor */ + + /* Disable EXTI USBVM event and interrupt */ + __HAL_PWR_USBVM_EXTI_DISABLE_EVENT(); + __HAL_PWR_USBVM_EXTI_DISABLE_IT(); + __HAL_PWR_USBVM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_USBVM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the USBVM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_USBVM_EXTI_ENABLE_IT(); + } + + /* Configure the USBVM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_USBVM_EXTI_ENABLE_EVENT(); + } + + /* Configure the USBVM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the USBVM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + case PWR_VDDIO2_VM: /* Independent I/Os voltage monitor */ + + /* Disable EXTI IO2VM event and interrupt */ + __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT(); + __HAL_PWR_IO2VM_EXTI_DISABLE_IT(); + __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the IO2VM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_IT(); + } + + /* Configure the IO2VM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT(); + } + + /* Configure the IO2VM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the IO2VM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + case PWR_VDDIO3_VM: /* Independent I/Os voltage monitor */ + + /* Disable EXTI IO3VM event and interrupt */ + __HAL_PWR_IO3VM_EXTI_DISABLE_EVENT(); + __HAL_PWR_IO3VM_EXTI_DISABLE_IT(); + __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_IO3VM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the IO3VM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_IO3VM_EXTI_ENABLE_IT(); + } + + /* Configure the IO3VM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_IO3VM_EXTI_ENABLE_EVENT(); + } + + /* Configure the IO3VM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the IO3VM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_IO3VM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + case PWR_VDDIO4_VM: /* Independent I/Os voltage monitor */ + + /* Disable EXTI IO4VM event and interrupt */ + __HAL_PWR_IO4VM_EXTI_DISABLE_EVENT(); + __HAL_PWR_IO4VM_EXTI_DISABLE_IT(); + __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_IO4VM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the IO4VM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_IO4VM_EXTI_ENABLE_IT(); + } + + /* Configure the IO4VM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_IO4VM_EXTI_ENABLE_EVENT(); + } + + /* Configure the IO4VM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the IO4VM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_IO4VM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + case PWR_VDDIO5_VM: /* Independent I/Os voltage monitor */ + + /* Disable EXTI IO5VM event and interrupt */ + __HAL_PWR_IO5VM_EXTI_DISABLE_EVENT(); + __HAL_PWR_IO5VM_EXTI_DISABLE_IT(); + __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_IO5VM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the IO5VM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_IO5VM_EXTI_ENABLE_IT(); + } + + /* Configure the IO5VM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_IO5VM_EXTI_ENABLE_EVENT(); + } + + /* Configure the IO5VM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the IO5VM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_IO5VM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + case PWR_VDDA_VM: /* Independent ADC voltage monitor */ + + /* Disable EXTI ADCVM event and interrupt */ + __HAL_PWR_ADCVM_EXTI_DISABLE_EVENT(); + __HAL_PWR_ADCVM_EXTI_DISABLE_IT(); + __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_ADCVM_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the ADCVM in interrupt mode */ + if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_ADCVM_EXTI_ENABLE_IT(); + } + + /* Configure the ADCVM in event mode */ + if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_ADCVM_EXTI_ENABLE_EVENT(); + } + + /* Configure the ADCVM in rising edge */ + if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the ADCVM in falling edge */ + if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_ADCVM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + default: /* No valid voltage monitor selected */ + return HAL_ERROR; + break; + } + + return HAL_OK; +} + +/** + * @brief This function handles the PWR PVD/PVM interrupt request. + * @retval None. + */ +void HAL_PWREx_PVD_PVM_IRQHandler(void) +{ + uint32_t rising_flag; + uint32_t falling_flag; + + rising_flag = READ_REG(EXTI->RPR3); + falling_flag = READ_REG(EXTI->FPR3); + + /* Check PWR VDDCORE monitoring exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_VCOREVM) != 0U) + { + /* Clear VDDCORE monitoring exti pending bit */ + __HAL_PWR_VCOREVM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR VDDCORE monitoring interrupt rising user callback */ + HAL_PWREx_VDDCORE_Rising_Callback(); + } + + /* Check PWR VDDCORE monitoring exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_VCOREVM) != 0U) + { + /* Clear VDDCORE monitoring exti pending bit */ + __HAL_PWR_VCOREVM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR VDDCORE monitoring interrupt falling user callback */ + HAL_PWREx_VDDCORE_Falling_Callback(); + } + + /* Check PWR PVD exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVD) != 0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD interrupt rising user callback */ + HAL_PWR_PVD_Rising_Callback(); + } + + /* Check PWR PVD exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVD) != 0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVD interrupt falling user callback */ + HAL_PWR_PVD_Falling_Callback(); + } + + /* Check PWR PVM USB exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVM_VDDUSB) != 0U) + { + /* Clear PVM USB exti pending bit */ + __HAL_PWR_USBVM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVM USB interrupt rising user callback */ + HAL_PWREx_USBVM_Rising_Callback(); + } + + /* Check PWR PVM USB exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVM_VDDUSB) != 0U) + { + /* Clear PVM USB exti pending bit */ + __HAL_PWR_USBVM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM USB interrupt falling user callback */ + HAL_PWREx_USBVM_Falling_Callback(); + } + + /* Check PWR PVM IO2 exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO2) != 0U) + { + /* Clear PVM IO2 exti pending bit */ + __HAL_PWR_IO2VM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVM IO2 interrupt rising user callback */ + HAL_PWREx_IO2VM_Rising_Callback(); + } + + /* Check PWR PVM IO2 exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO2) != 0U) + { + /* Clear PVM IO2 exti pending bit */ + __HAL_PWR_IO2VM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM IO2 interrupt falling user callback */ + HAL_PWREx_IO2VM_Falling_Callback(); + } + + /* Check PWR PVM IO3 exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO3) != 0U) + { + /* Clear PVM IO3 exti pending bit */ + __HAL_PWR_IO3VM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVM IO3 interrupt rising user callback */ + HAL_PWREx_IO3VM_Rising_Callback(); + } + + /* Check PWR PVM IO3 exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO3) != 0U) + { + /* Clear PVM IO3 exti pending bit */ + __HAL_PWR_IO3VM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM IO3 interrupt falling user callback */ + HAL_PWREx_IO3VM_Falling_Callback(); + } + + /* Check PWR PVM IO4 exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO4) != 0U) + { + /* Clear PVM IO4 exti pending bit */ + __HAL_PWR_IO4VM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVM IO4 interrupt rising user callback */ + HAL_PWREx_IO4VM_Rising_Callback(); + } + + /* Check PWR PVM IO4 exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO4) != 0U) + { + /* Clear PVM IO4 exti pending bit */ + __HAL_PWR_IO4VM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM IO4 interrupt falling user callback */ + HAL_PWREx_IO4VM_Falling_Callback(); + } + + /* Check PWR PVM IO5 exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO5) != 0U) + { + /* Clear PVM IO5 exti pending bit */ + __HAL_PWR_IO5VM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVM IO5 interrupt rising user callback */ + HAL_PWREx_IO5VM_Rising_Callback(); + } + + /* Check PWR PVM IO5 exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO5) != 0U) + { + /* Clear PVM IO5 exti pending bit */ + __HAL_PWR_IO5VM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM IO5 interrupt falling user callback */ + HAL_PWREx_IO5VM_Falling_Callback(); + + } + + /* Check PWR PVM ADC VM exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVM_VDDA) != 0U) + { + /* Clear PVM ADC VM exti pending bit */ + __HAL_PWR_ADCVM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVM ADC VM interrupt rising user callback */ + HAL_PWREx_ADCVM_Rising_Callback(); + } + + /* Check PWR PVM ADC VM exti falling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVM_VDDA) != 0U) + { + /* Clear PVM ADC VM exti pending bit */ + __HAL_PWR_ADCVM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM ADC VM interrupt falling user callback */ + HAL_PWREx_ADCVM_Falling_Callback(); + } +} + +/** + * @brief PWR VDDCORE interrupt Rising callback. + * @retval None. + */ +__weak void HAL_PWREx_VDDCORE_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_VDDCORE_Rising_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR VDDCORE interrupt Falling callback. + * @retval None. + */ +__weak void HAL_PWREx_VDDCORE_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_VDDCORE_Falling_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR USBVM interrupt Rising callback. + * @retval None. + */ +__weak void HAL_PWREx_USBVM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_USBVM_Rising_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR USBVM interrupt Falling callback. + * @retval None. + */ +__weak void HAL_PWREx_USBVM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_USBVM_Falling_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO2VM interrupt Rising callback. + * @retval None. + */ +__weak void HAL_PWREx_IO2VM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO2VM_Rising_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO2VM interrupt Falling callback. + * @retval None. + */ +__weak void HAL_PWREx_IO2VM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO2VM_Falling_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO3VM interrupt Rising callback. + * @retval None. + */ +__weak void HAL_PWREx_IO3VM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO3VM_Rising_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO3VM interrupt Falling callback. + * @retval None. + */ +__weak void HAL_PWREx_IO3VM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO3VM_Falling_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO4VM interrupt Rising callback. + * @retval None. + */ +__weak void HAL_PWREx_IO4VM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO4VM_Rising_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO4VM interrupt Falling callback. + * @retval None. + */ +__weak void HAL_PWREx_IO4VM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO4VM_Falling_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO5VM interrupt Rising callback. + * @retval None. + */ +__weak void HAL_PWREx_IO5VM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO5VM_Rising_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR IO5VM interrupt Falling callback. + * @retval None. + */ +__weak void HAL_PWREx_IO5VM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_IO5VM_Falling_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR ADCVM interrupt Rising callback. + * @retval None. + */ +__weak void HAL_PWREx_ADCVM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_ADCVM_Rising_Callback() API can be implemented in the user file + */ +} + +/** + * @brief PWR ADCVM interrupt Falling callback. + * @retval None. + */ +__weak void HAL_PWREx_ADCVM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + HAL_PWREx_ADCVM_Falling_Callback() API can be implemented in the user file + */ +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#endif /* defined (HAL_PWR_MODULE_ENABLED) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c (revision 16) @@ -0,0 +1,2612 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 64MHz) and all peripherals are off except internal SRAM, BSEC, PWR, IAC, + RIFSC, RISAF and JTAG + (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) All GPIOs are in analog mode , except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance than HSI) + (+) Configure the CPU and System bus clock frequencies + (+) Configure the AHB and APB buses pre-scalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock kernel source(s) for peripherals which clocks are not + derived from the System clock + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + [..] + Incorrect APB prescaler setting: + (+) As described in the product errata, after enabling the bus clock to the + peripheral and changing the default APB prescaler setting, performing a + configuration on the bus peripheral does not update the peripheral registers, + resulting in unexpected behavior. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define RCC_MSI_TIMEOUT_VALUE 1U /* 1 ms */ +#define RCC_HSI_TIMEOUT_VALUE 1U /* 1 ms */ +#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define RCC_HSE_LATENCY_VALUE 2U /* 2 ms */ +#define RCC_LSI_TIMEOUT_VALUE 1U /* 1 ms */ +#define RCC_CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ + +#define RCC_PLL1_CONFIG 0U +#define RCC_PLL2_CONFIG 1U +#define RCC_PLL3_CONFIG 2U +#define RCC_PLL4_CONFIG 3U + +#define RCC_ITEM_GROUP_IDX_OSC 0x0UL +#define RCC_ITEM_GROUP_IDX_PLL 0x1UL +#define RCC_ITEM_GROUP_IDX_IC 0x2UL +#define RCC_ITEM_GROUP_IDX_SYSCFG 0x3UL +#define RCC_ITEM_GROUP_IDX_BUS 0x4UL +#define RCC_ITEM_GROUP_IDX_MEM 0x5UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define RCC_MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define RCC_MCO1_GPIO_PORT GPIOA +#define RCC_MCO1_PIN GPIO_PIN_8 + +#define RCC_MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define RCC_MCO2_GPIO_PORT GPIOC +#define RCC_MCO2_PIN GPIO_PIN_9 + +#define RCC_GET_MSI_FREQUENCY() (HAL_IS_BIT_SET(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) ? (MSI_VALUE << 2U) : MSI_VALUE) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint32_t RCC_GetSysClockFreq(uint32_t icx_source, uint32_t icx_divider); +static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit); +static HAL_StatusTypeDef RCC_PLL_Enable(uint32_t PLLnumber); +static uint32_t RCC_PLL_IsNewConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit); +static uint32_t RCC_PLL_Source_IsReady(uint32_t PLLSource); +static uint32_t RCC_IC_CheckPLLSources(uint32_t PLLSource1, uint32_t PLLSource2); +static void RCC_ATTR_ConfigItemGroup(uint32_t ItemGroup, uint32_t Item, uint32_t Attributes); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the CPU and System buses clocks (SYSCLK, AHB1, + AHB2, AHB3, AHB4, AHB5, APB1, APB2, APB4 and APB5). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) MSI is a low-power RC oscillator which can be used directly as system clock, peripheral + clock, or PLL input.But even with frequency calibration, is less accurate than an + external crystal oscillator or ceramic resonator. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or MSI), + featuring three different output clocks and able to work either in integer or Fractional mode. + (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU + and to some peripherals via the ICx mux. + (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals. + + (#) HSE CSS (Clock security system), once enabled and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M NMI (Non-Maskable Interrupt) + exception vector. + + (#) LSE CSS (Clock security system), once enabled and if a LSE clock failure occurs + the LSE is no more provided to RTC, it allows to wake-up from standby mode and protect the + backup registers and BKPSRAM via TAMP. The LSE CSS may be re-armed for further attempt(s) to use LSE. + + (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, LSI, MSI, CPU (SYSA), IC5 mux + or IC10 mux clock (through a configurable pre-scaler) on PA8 pin. + + (#) MCO2 (micro controller clock output), used to output HSI, LSE, HSE, LSI, MSI, System Bus (SYSB), + IC15 mux or IC20 mux clock (through a configurable pre-scaler) on PC9 pin. + + [..] CPU, System bus, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive independently the CPU (CPUCLK) and System bus clock (SYSCLK): + HSI, MSI, HSE or ICx mux. + The AHB clock (HCLK) is derived from System core clock through configurable + pre-scaler and used to clock the CPU, memory and peripherals mapped + on AHB and APB bus through configurable pre-scalers + and used to clock the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. + + -@- All the peripheral clocks are derived from the System bus clock (SYSCLK). + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as CPU and system clock source + * - MSI and HSE OFF + * - PLL1, PLL2, PLL3 and PLL4 bypassed + * - AHB, APB Bus prescalers set to 1 + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - Memory clocks + * - Misc clocks + * - LSI, LSE and RTC clocks + * - ICx selections and dividers + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Disable all interrupts except default one */ + WRITE_REG(RCC->CIER, RCC_CIER_HSECSSIE); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \ + RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | RCC_CICR_PLL3RDYC | RCC_CICR_PLL4RDYC | \ + RCC_CICR_LSECSSC | RCC_CICR_HSECSSC | RCC_CICR_WKUPFC); + + /* Clear reset source flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + /* Restore default HSI */ + LL_RCC_HSI_SetDivider(LL_RCC_HSI_DIV_1); + LL_RCC_HSI_Enable(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait for HSI READY bit */ + while (LL_RCC_HSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset CFGR1 register to select HSI as CPU and system bus clock */ + CLEAR_REG(RCC->CFGR1); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR1, (RCC_CFGR1_CPUSWS | RCC_CFGR1_SYSSWS)) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Reset PLL1 registers to default value */ + WRITE_REG(RCC->PLL1CFGR1, 0x08202500U); + WRITE_REG(RCC->PLL1CFGR2, 0x00800000U); + WRITE_REG(RCC->PLL1CFGR3, 0x4900000DU); + /* Reset PLL2 registers to default value */ + WRITE_REG(RCC->PLL2CFGR1, 0x08000000U); + WRITE_REG(RCC->PLL2CFGR2, 0x00000000U); + WRITE_REG(RCC->PLL2CFGR3, 0x49000005U); + /* Reset PLL3 registers to default value */ + WRITE_REG(RCC->PLL3CFGR1, 0x08000000U); + WRITE_REG(RCC->PLL3CFGR2, 0x00000000U); + WRITE_REG(RCC->PLL3CFGR3, 0x49000005U); + /* Reset PLL4 registers to default value */ + WRITE_REG(RCC->PLL4CFGR1, 0x08000000U); + WRITE_REG(RCC->PLL4CFGR2, 0x00000000U); + WRITE_REG(RCC->PLL4CFGR3, 0x49000005U); + + /* Reset MSION, HSEON, PLL1ON, PLL2ON, PLL3ON and PLL4ON bits */ + WRITE_REG(RCC->CCR, RCC_CCR_MSIONC | RCC_CCR_HSEONC | \ + RCC_CCR_PLL1ONC | RCC_CCR_PLL2ONC | RCC_CCR_PLL3ONC | RCC_CCR_PLL4ONC); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait for all PLL ready bits to be reset */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY | RCC_SR_PLL2RDY | RCC_SR_PLL3RDY | RCC_SR_PLL4RDY)) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset prescalers in CFGR2 register to default values*/ + WRITE_REG(RCC->CFGR2, 0x00100000U); + + /* Reset MSICFGR register */ + CLEAR_REG(RCC->MSICFGR); + + /* Reset HSIMCR register to default value */ + WRITE_REG(RCC->HSIMCR, 0x001F07A1U); + + /* Reset HSECFGR register to default value */ + WRITE_REG(RCC->HSECFGR, 0x00000800U); + + /* Reset STOPCR register to default value */ + WRITE_REG(RCC->STOPCR, 0x00000002U); + + /* Disable MCO1 and MCO2 */ + CLEAR_BIT(RCC->MISCENR, RCC_MISCENR_MCO1EN | RCC_MISCENR_MCO2EN); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param pRCC_OscInitStruct Pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note LSE control requires that the backup domain shall be previously enabled + * with HAL_PWR_EnableBkUpAccess(). + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note This function does not protect the MCOxSEL, the PERSEL and the PPPSEL glitch-free muxes + * (Mux selection cannot be changed if selected input clock is inactive). + * @note This function activates HSE but does not wait for the startup time defined in the datasheet. + * This must be ensured by the application when the HSE is selected as PLL source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t sysclksrc; + uint32_t cpuclksrc; + uint32_t pll1src; + uint32_t pll2src; + uint32_t pll3src; + uint32_t pll4src; + uint32_t rccsr; + + /* Check Null pointer */ + if (pRCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(pRCC_OscInitStruct->OscillatorType)); + + cpuclksrc = LL_RCC_GetCpuClkSource(); + sysclksrc = LL_RCC_GetSysClkSource(); + pll1src = LL_RCC_PLL1_GetSource(); + pll2src = LL_RCC_PLL2_GetSource(); + pll3src = LL_RCC_PLL3_GetSource(); + pll4src = LL_RCC_PLL4_GetSource(); + rccsr = RCC->SR; + + /*------------------------------- HSE Configuration ------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(pRCC_OscInitStruct->HSEState)); + + /* When the HSE is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled */ + if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_HSE) || (sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || + ((pll1src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL1RDY) == RCC_SR_PLL1RDY))) || + ((pll2src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL2RDY) == RCC_SR_PLL2RDY))) || + ((pll3src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL3RDY) == RCC_SR_PLL3RDY))) || + ((pll4src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL4RDY) == RCC_SR_PLL4RDY)))) + { + if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF) + { + return HAL_ERROR; + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while ((READ_BIT(RCC->SR, RCC_SR_HSERDY) == 0U)) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait 2 ms latency after HSE ready */ + while ((HAL_GetTick() - tickstart) < RCC_HSE_LATENCY_VALUE) + {} + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(pRCC_OscInitStruct->HSEState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Check the HSE State */ + if (pRCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Wait till HSE is ready */ + while (READ_BIT(RCC->SR, RCC_SR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->SR, RCC_SR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(pRCC_OscInitStruct->HSIState)); + + /* When the HSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled */ + if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_HSI) || (sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || + ((pll1src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL1RDY) == RCC_SR_PLL1RDY))) || + ((pll2src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL2RDY) == RCC_SR_PLL2RDY))) || + ((pll3src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL3RDY) == RCC_SR_PLL3RDY))) || + ((pll4src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL4RDY) == RCC_SR_PLL4RDY)))) + { + /* When HSI is used as system clock it will not be disabled */ + if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, just the divider and calibration is allowed */ + else + { + /* Check the parameters */ + assert_param(IS_RCC_HSI_DIV(pRCC_OscInitStruct->HSIDiv)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue)); + + /* Set the HSI Divider */ + __HAL_RCC_HSI_DIVIDER_CONFIG(pRCC_OscInitStruct->HSIDiv); + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (pRCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI_DIV(pRCC_OscInitStruct->HSIDiv)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue)); + + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the HSI Divider */ + __HAL_RCC_HSI_DIVIDER_CONFIG(pRCC_OscInitStruct->HSIDiv); + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (LL_RCC_HSI_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*----------------------------- MSI Configuration --------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + { + /* Check the parameters */ + assert_param(IS_RCC_MSI(pRCC_OscInitStruct->MSIState)); + + /* When the MSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled */ + /* but just to update the MSI calibration value */ + if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_MSI) || (sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) || + ((pll1src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL1RDY) == RCC_SR_PLL1RDY))) || + ((pll2src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL2RDY) == RCC_SR_PLL2RDY))) || + ((pll3src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL3RDY) == RCC_SR_PLL3RDY))) || + ((pll4src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL4RDY) == RCC_SR_PLL4RDY)))) + { + /* When MSI is used as system clock it will not disabled */ + if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Check the parameters */ + assert_param(IS_RCC_MSI_CALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue)); + + /* Adjusts the Internal High Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->MSICalibrationValue); + } + } + else + { + /* Check the MSI State */ + if ((pRCC_OscInitStruct->MSIState) != RCC_MSI_OFF) + { + /* Check the parameters */ + assert_param(IS_RCC_MSI_FREQUENCY(pRCC_OscInitStruct->MSIFrequency)); + assert_param(IS_RCC_MSI_CALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue)); + + /* Set the frequency */ + __HAL_RCC_MSI_FREQUENCY_CONFIG(pRCC_OscInitStruct->MSIFrequency); + + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->MSICalibrationValue); + } + else + { + /* Ignore MSI frequency and calibration values in disable case */ + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till MSI is disabled */ + while (LL_RCC_MSI_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*------------------------------ LSI Configuration -------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(pRCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((pRCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (LL_RCC_LSI_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (LL_RCC_LSI_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(pRCC_OscInitStruct->LSEState)); + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(pRCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((pRCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (LL_RCC_LSE_IsReady() != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*-------------------------------- PLL1 Configuration ----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL1.PLLState)); + + if (pRCC_OscInitStruct->PLL1.PLLState != RCC_PLL_NONE) + { + uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL1_CONFIG, &(pRCC_OscInitStruct->PLL1)); + uint32_t pll1_ready = LL_RCC_PLL1_IsReady(); + if (new_pll_config == 1U) + { + uint32_t ic1src = LL_RCC_IC1_GetSource(); + uint32_t ic2src = LL_RCC_IC2_GetSource(); + uint32_t ic6src = LL_RCC_IC6_GetSource(); + uint32_t ic11src = LL_RCC_IC11_GetSource(); + /* PLL1 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */ + if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL1)) + { + return HAL_ERROR; + } + + /* PLL1 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL1) || + (ic6src == LL_RCC_ICCLKSOURCE_PLL1) || + (ic11src == LL_RCC_ICCLKSOURCE_PLL1))) + { + return HAL_ERROR; + } + /* PLL1 is not used, it can be configured */ + if (RCC_PLL_Config(RCC_PLL1_CONFIG, &(pRCC_OscInitStruct->PLL1)) != HAL_OK) + { + return HAL_ERROR; + } + } + else if ((pRCC_OscInitStruct->PLL1.PLLState == RCC_PLL_ON) && (pll1_ready == 0U)) + { + if (RCC_PLL_Enable(RCC_PLL1_CONFIG) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Nothing to do */ + } + } + + /*-------------------------------- PLL2 Configuration ----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL2.PLLState)); + + if (pRCC_OscInitStruct->PLL2.PLLState != RCC_PLL_NONE) + { + uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL2_CONFIG, &(pRCC_OscInitStruct->PLL2)); + uint32_t pll2_ready = LL_RCC_PLL2_IsReady(); + if (new_pll_config == 1U) + { + uint32_t ic1src = LL_RCC_IC1_GetSource(); + uint32_t ic2src = LL_RCC_IC2_GetSource(); + uint32_t ic6src = LL_RCC_IC6_GetSource(); + uint32_t ic11src = LL_RCC_IC11_GetSource(); + /* PLL2 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */ + if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL2)) + { + return HAL_ERROR; + } + + /* PLL2 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL2) || + (ic6src == LL_RCC_ICCLKSOURCE_PLL2) || + (ic11src == LL_RCC_ICCLKSOURCE_PLL2))) + { + return HAL_ERROR; + } + /* PLL2 is not used, it can be configured */ + if (RCC_PLL_Config(RCC_PLL2_CONFIG, &(pRCC_OscInitStruct->PLL2)) != HAL_OK) + { + return HAL_ERROR; + } + } + else if ((pRCC_OscInitStruct->PLL2.PLLState == RCC_PLL_ON) && (pll2_ready == 0U)) + { + if (RCC_PLL_Enable(RCC_PLL2_CONFIG) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Nothing to do */ + } + } + + /*-------------------------------- PLL3 Configuration ----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL3.PLLState)); + + if (pRCC_OscInitStruct->PLL3.PLLState != RCC_PLL_NONE) + { + uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL3_CONFIG, &(pRCC_OscInitStruct->PLL3)); + uint32_t pll3_ready = LL_RCC_PLL3_IsReady(); + if (new_pll_config == 1U) + { + uint32_t ic1src = LL_RCC_IC1_GetSource(); + uint32_t ic2src = LL_RCC_IC2_GetSource(); + uint32_t ic6src = LL_RCC_IC6_GetSource(); + uint32_t ic11src = LL_RCC_IC11_GetSource(); + /* PLL3 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */ + if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL3)) + { + return HAL_ERROR; + } + /* PLL3 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL3) || + (ic6src == LL_RCC_ICCLKSOURCE_PLL3) || + (ic11src == LL_RCC_ICCLKSOURCE_PLL3))) + { + return HAL_ERROR; + } + /* PLL3 is not used, it can be configured */ + if (RCC_PLL_Config(RCC_PLL3_CONFIG, &(pRCC_OscInitStruct->PLL3)) != HAL_OK) + { + return HAL_ERROR; + } + } + else if ((pRCC_OscInitStruct->PLL3.PLLState == RCC_PLL_ON) && (pll3_ready == 0U)) + { + if (RCC_PLL_Enable(RCC_PLL3_CONFIG) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Nothing to do */ + } + } + + /*-------------------------------- PLL4 Configuration ----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL4.PLLState)); + + if (pRCC_OscInitStruct->PLL4.PLLState != RCC_PLL_NONE) + { + uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL4_CONFIG, &(pRCC_OscInitStruct->PLL4)); + uint32_t pll4_ready = LL_RCC_PLL4_IsReady(); + + if (new_pll_config == 1U) + { + uint32_t ic1src = LL_RCC_IC1_GetSource(); + uint32_t ic2src = LL_RCC_IC2_GetSource(); + uint32_t ic6src = LL_RCC_IC6_GetSource(); + uint32_t ic11src = LL_RCC_IC11_GetSource(); + /* PLL4 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */ + if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL4)) + { + return HAL_ERROR; + } + /* PLL4 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL4) || + (ic6src == LL_RCC_ICCLKSOURCE_PLL4) || + (ic11src == LL_RCC_ICCLKSOURCE_PLL4))) + { + return HAL_ERROR; + } + /* PLL4 is not used, it can be configured */ + if (RCC_PLL_Config(RCC_PLL4_CONFIG, &(pRCC_OscInitStruct->PLL4)) != HAL_OK) + { + return HAL_ERROR; + } + } + else if ((pRCC_OscInitStruct->PLL4.PLLState == RCC_PLL_ON) && (pll4_ready == 0U)) + { + if (RCC_PLL_Enable(RCC_PLL4_CONFIG) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Nothing to do */ + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, System AXI, AHB, APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param pRCC_ClkInitStruct Pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * + * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency + * and updated by HAL_InitTick() function called within this function. + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP (unless MSI is selected) and STANDBY mode, + * or in case of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *pRCC_ClkInitStruct) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (pRCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(pRCC_ClkInitStruct->ClockType)); + + /* Increasing the BUS frequency divider ? */ + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK1(pRCC_ClkInitStruct->APB1CLKDivider)); + if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, (pRCC_ClkInitStruct->APB1CLKDivider)); + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK2(pRCC_ClkInitStruct->APB2CLKDivider)); + if ((pRCC_ClkInitStruct->APB2CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE2)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, (pRCC_ClkInitStruct->APB2CLKDivider)); + } + } + + /*-------------------------- PCLK4 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) + { + assert_param(IS_RCC_PCLK4(pRCC_ClkInitStruct->APB4CLKDivider)); + if ((pRCC_ClkInitStruct->APB4CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE4)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, (pRCC_ClkInitStruct->APB4CLKDivider)); + } + } + + /*-------------------------- PCLK5 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) + { + assert_param(IS_RCC_PCLK5(pRCC_ClkInitStruct->APB5CLKDivider)); + if ((pRCC_ClkInitStruct->APB5CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE5)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, (pRCC_ClkInitStruct->APB5CLKDivider)); + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + /* Set the new HCLK clock divider */ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + + /*------------------------- CPUCLK Configuration -------------------------*/ + if ((pRCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_CPUCLK) == RCC_CLOCKTYPE_CPUCLK) + { + assert_param(IS_RCC_CPUCLKSOURCE(pRCC_ClkInitStruct->CPUCLKSource)); + + /* HSE is selected as CPU Clock Source */ + if (pRCC_ClkInitStruct->CPUCLKSource == RCC_CPUCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as CPU Clock Source */ + else if (pRCC_ClkInitStruct->CPUCLKSource == RCC_CPUCLKSOURCE_IC1) + { + /* Check parameters */ + assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC1Selection.ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC1Selection.ClockDivider)); + + /* ICx clock switch requires both origin and destination clock source to be active */ + /* Check IC1 origin and target clock sources availability */ + if (RCC_IC_CheckPLLSources(LL_RCC_IC1_GetSource(), pRCC_ClkInitStruct->IC1Selection.ClockSelection) != 1U) + { + return HAL_ERROR; + } + + /* Configure IC1 source and divider */ + WRITE_REG(RCC->IC1CFGR, pRCC_ClkInitStruct->IC1Selection.ClockSelection | \ + ((pRCC_ClkInitStruct->IC1Selection.ClockDivider - 1U) << RCC_IC1CFGR_IC1INT_Pos)); + + /* Enable IC1 */ + LL_RCC_IC1_Enable(); + } + /* MSI is selected as CPU Clock Source */ + else if (pRCC_ClkInitStruct->CPUCLKSource == RCC_CPUCLKSOURCE_MSI) + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as CPU Clock Source */ + else + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + { + return HAL_ERROR; + } + } + + /* Switch the CPU clock */ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_CPUSW, pRCC_ClkInitStruct->CPUCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_CPUCLK_SOURCE() != (pRCC_ClkInitStruct->CPUCLKSource << 4U)) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable with CPU clock */ + SystemCoreClock = HAL_RCC_GetCpuClockFreq(); + + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if ((pRCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System bus clock source */ + if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + { + return HAL_ERROR; + } + } + /* PLL output is selected as System bus clock source */ + else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11) + { + /* Check parameters */ + assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC2Selection.ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC2Selection.ClockDivider)); + assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC6Selection.ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC6Selection.ClockDivider)); + assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC11Selection.ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC11Selection.ClockDivider)); + + /* ICx clock switch requires both origin and destination clock source to be active */ + /* Check IC2/IC6/IC11 origin and target clock sources availability */ + if (RCC_IC_CheckPLLSources(LL_RCC_IC2_GetSource(), pRCC_ClkInitStruct->IC2Selection.ClockSelection) != 1U) + { + return HAL_ERROR; + } + if (RCC_IC_CheckPLLSources(LL_RCC_IC6_GetSource(), pRCC_ClkInitStruct->IC6Selection.ClockSelection) != 1U) + { + return HAL_ERROR; + } + if (RCC_IC_CheckPLLSources(LL_RCC_IC11_GetSource(), pRCC_ClkInitStruct->IC11Selection.ClockSelection) != 1U) + { + return HAL_ERROR; + } + + /* Configure IC2, IC6 and IC11 sources and dividers */ + WRITE_REG(RCC->IC2CFGR, pRCC_ClkInitStruct->IC2Selection.ClockSelection | \ + ((pRCC_ClkInitStruct->IC2Selection.ClockDivider - 1U) << RCC_IC2CFGR_IC2INT_Pos)); + WRITE_REG(RCC->IC6CFGR, pRCC_ClkInitStruct->IC6Selection.ClockSelection | \ + ((pRCC_ClkInitStruct->IC6Selection.ClockDivider - 1U) << RCC_IC6CFGR_IC6INT_Pos)); + WRITE_REG(RCC->IC11CFGR, pRCC_ClkInitStruct->IC11Selection.ClockSelection | \ + ((pRCC_ClkInitStruct->IC11Selection.ClockDivider - 1U) << RCC_IC11CFGR_IC11INT_Pos)); + + /* Require to have IC2, IC6 and IC11 outputs enabled */ + WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC2ENS | RCC_DIVENSR_IC6ENS | RCC_DIVENSR_IC11ENS); + } + /* HSI is selected as System bus clock source */ + else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + { + return HAL_ERROR; + } + } + /* MSI is selected as System bus clock source */ + else + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + { + return HAL_ERROR; + } + } + + /* Switch the system bus clocks */ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SYSSW, pRCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (pRCC_ClkInitStruct->SYSCLKSource << 4U)) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the BUS frequency divider ? */ + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + /* Set the new HCLK clock divider */ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK1(pRCC_ClkInitStruct->APB1CLKDivider)); + if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, (pRCC_ClkInitStruct->APB1CLKDivider)); + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK2(pRCC_ClkInitStruct->APB2CLKDivider)); + if ((pRCC_ClkInitStruct->APB2CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE2)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, (pRCC_ClkInitStruct->APB2CLKDivider)); + } + } + + /*-------------------------- PCLK4 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) + { + assert_param(IS_RCC_PCLK4(pRCC_ClkInitStruct->APB4CLKDivider)); + if ((pRCC_ClkInitStruct->APB4CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE4)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, (pRCC_ClkInitStruct->APB4CLKDivider)); + } + } + + /*-------------------------- PCLK5 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) + { + assert_param(IS_RCC_PCLK5(pRCC_ClkInitStruct->APB5CLKDivider)); + if ((pRCC_ClkInitStruct->APB5CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE5)) + { + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, (pRCC_ClkInitStruct->APB5CLKDivider)); + } + } + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(uwTickPrio); +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PWR VDDIO4 Input Independent I/O supply 4 shall be previously set up for PC9 + * with HAL_PWREx_EnableVddIO4() + * @note The MCO switch to the new clock source only occurs when the previous clock source is active + * (dynamic switch). + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2 Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_LSI LSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_MSI MSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_IC5 IC5 clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_IC10 IC10 clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_SYSA CPU clock (SYSA) selected as MCO1 source + * @arg RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_MSI MSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_IC15 IC15 clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_IC20 IC20 clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_SYSB Bus clock (SYSB) selected as MCO2 source + * @param RCC_MCODiv specifies the MCOx pre-scaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_16 : divider applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + RCC_MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = RCC_MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(RCC_MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Configure MCO1 */ + LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); + + /* Enable IC5 if requested as source to MCO1 */ + if (RCC_MCOSource == RCC_MCO1SOURCE_IC5) + { + LL_RCC_IC5_Enable(); + } + /* Enable IC10 if requested as source to MCO1 */ + else if (RCC_MCOSource == RCC_MCO1SOURCE_IC10) + { + LL_RCC_IC10_Enable(); + } + else + { + /* Nothing to do as not ICx source */ + } + /* Enable MC01 output */ + LL_RCC_EnableMCO(LL_RCC_MCO1); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + RCC_MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = RCC_MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(RCC_MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Configure MCO2 */ + LL_RCC_ConfigMCO(RCC_MCOSource, ((RCC_CCIPR5_MCO2PRE << 16U) | ((RCC_MCODiv & RCC_CCIPR5_MCO1PRE) << 8U))); + + /* Enable IC15 if requested as source to MCO2 */ + if (RCC_MCOSource == RCC_MCO2SOURCE_IC15) + { + LL_RCC_IC15_Enable(); + } + /* Enable IC20 if requested as source to MCO2 */ + else if (RCC_MCOSource == RCC_MCO2SOURCE_IC20) + { + LL_RCC_IC20_Enable(); + } + else + { + /* Nothing to do as not ICx source */ + } + /* Enable MC02 output */ + LL_RCC_EnableMCO(LL_RCC_MCO2); + } +} + +/** + * @brief Enable the HSE Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector. + * @note The HSE Clock Security System may be enabled even if the HSE is not enabled + * but will be activated when the HSE is enabled and ready. + * @note It is not possible to disable the HSE Clock Security System. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + LL_RCC_HSE_EnableCSS(); +} + +/** + * @brief Returns the CPU clock (sysa_ck) frequency + * + * @note The CPU clock frequency computed by this function may be not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If CPUCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If CPUCLK source is MSI, function returns values based on MSI_VALUE(*) + * @note If CPUCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If CPUCLK source is IC1, function returns values based on HSI_VALUE(*), + * MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time CPUCLK changes, this function must be called by the user application + * to update the CPUCLK value. Otherwise, any configuration based on this function + * will be incorrect. + * + * @retval CPUCLK frequency + */ +uint32_t HAL_RCC_GetCpuClockFreq(void) +{ + uint32_t frequency = 0U; + uint32_t ic_divider; + + /* Get CPUCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetCpuClkSource()) + { + /* No check on Ready: Won't be selected by hardware if not */ + case LL_RCC_CPU_CLKSOURCE_STATUS_HSI: + frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + break; + + case LL_RCC_CPU_CLKSOURCE_STATUS_MSI: + frequency = RCC_GET_MSI_FREQUENCY(); + break; + + case LL_RCC_CPU_CLKSOURCE_STATUS_HSE: + frequency = HSE_VALUE; + break; + + case LL_RCC_CPU_CLKSOURCE_STATUS_IC1: + ic_divider = LL_RCC_IC1_GetDivider(); + switch (LL_RCC_IC1_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + frequency = HAL_RCCEx_GetPLL1CLKFreq(); + frequency = frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + frequency = HAL_RCCEx_GetPLL2CLKFreq(); + frequency = frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + frequency = HAL_RCCEx_GetPLL3CLKFreq(); + frequency = frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + frequency = HAL_RCCEx_GetPLL4CLKFreq(); + frequency = frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + break; + + default: + /* Unexpected case */ + break; + } + + return frequency; +} + +/** + * @brief Returns the SYSCLK bus (sysb_ck) frequency + * + * @note The system bus frequency computed by this function may be not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is IC2, function returns values based on HSI_VALUE(*), + * MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called by the user application + * to update the SYSCLK bus value. Otherwise, any configuration based on this function + * will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + return RCC_GetSysClockFreq(LL_RCC_IC2_GetSource(), LL_RCC_IC2_GetDivider()); +} + +/** + * @brief Returns the NPU clock (sysc_ck) frequency + * + * @note The NPU clock frequency computed by this function may be not the real frequency in the chip. + * It is calculated based on the predefined constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is IC6, function returns values based on HSI_VALUE(*), + * MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application. + * + * @note Each time SYSCLK changes, this function must be called by the user application + * to update the NPU clock value. Otherwise, any configuration based on this function + * will be incorrect. + * + * @retval NPU clock frequency + */ +uint32_t HAL_RCC_GetNPUClockFreq(void) +{ + return RCC_GetSysClockFreq(LL_RCC_IC6_GetSource(), LL_RCC_IC6_GetDivider()); +} + +/** + * @brief Returns the NPU RAMS clock (sysd_ck) frequency + * + * @note The NPU RAMS rams clock frequency computed by this function may be not the real frequency in the chip. + * It is calculated based on the predefined constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is IC11, function returns values based on HSI_VALUE(*), + * MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called by the user application + * to update the NPU RAMS clock value. Otherwise, any configuration based on this function + * will be incorrect. + * + * @retval NPU RAMS clock frequency + */ +uint32_t HAL_RCC_GetNPURAMSClockFreq(void) +{ + return RCC_GetSysClockFreq(LL_RCC_IC11_GetSource(), LL_RCC_IC11_GetDivider()); +} + +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + return LL_RCC_CALC_PCLK1_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()), + LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return the PCLK2 frequency. + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + return LL_RCC_CALC_PCLK2_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()), + LL_RCC_GetAPB2Prescaler()); +} + +/** + * @brief Return the PCLK4 frequency. + * @note Each time PCLK4 changes, this function must be called to update the + * right PCLK4 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK4 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK4Freq(void) +{ + return LL_RCC_CALC_PCLK4_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()), + LL_RCC_GetAPB4Prescaler()); +} + +/** + * @brief Return the PCLK5 frequency. + * @note Each time PCLK5 changes, this function must be called to update the + * right PCLK5 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK5 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK5Freq(void) +{ + return LL_RCC_CALC_PCLK5_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()), + LL_RCC_GetAPB5Prescaler()); +} + +/** + * @brief Get the oscillators status configuration in RCC_OscInitStruct according to + * the internal RCC configuration registers. + * @param pRCC_OscInitStruct Pointer to an RCC_OscInitTypeDef structure that + * will return the configuration. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) +{ + uint32_t sr_value; + uint32_t cfgr_value; + + /* Get the status register value */ + sr_value = RCC->SR; + + /* Set all possible values for the Oscillator type parameters --------------*/ + pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_HSERDY) != 0UL) + { + cfgr_value = RCC->HSECFGR; + if ((cfgr_value & (RCC_HSECFGR_HSEBYP | RCC_HSECFGR_HSEEXT)) == RCC_HSECFGR_HSEBYP) + { + pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((cfgr_value & (RCC_HSECFGR_HSEBYP | RCC_HSECFGR_HSEEXT)) == (RCC_HSECFGR_HSEBYP | RCC_HSECFGR_HSEEXT)) + { + pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; + } + else + { + pRCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + } + else + { + pRCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the MSI configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_MSIRDY) != 0UL) + { + pRCC_OscInitStruct->MSIState = RCC_MSI_ON; + } + else + { + pRCC_OscInitStruct->MSIState = RCC_MSI_OFF; + } + + cfgr_value = RCC->MSICFGR; + pRCC_OscInitStruct->MSIFrequency = (cfgr_value & RCC_MSICFGR_MSIFREQSEL); + pRCC_OscInitStruct->MSICalibrationValue = ((cfgr_value & RCC_MSICFGR_MSITRIM) >> RCC_MSICFGR_MSITRIM_Pos); + + /* Get the HSI configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_HSIRDY) != 0UL) + { + pRCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + pRCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + cfgr_value = RCC->HSICFGR; + pRCC_OscInitStruct->HSIDiv = (cfgr_value & RCC_HSICFGR_HSIDIV); + pRCC_OscInitStruct->HSICalibrationValue = ((cfgr_value & RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_LSERDY) != 0UL) + { + cfgr_value = RCC->LSECFGR; + if ((cfgr_value & (RCC_LSECFGR_LSEBYP | RCC_LSECFGR_LSEEXT)) == RCC_LSECFGR_LSEBYP) + { + pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((cfgr_value & (RCC_LSECFGR_LSEBYP | RCC_LSECFGR_LSEEXT)) == (RCC_LSECFGR_LSEBYP | RCC_LSECFGR_LSEEXT)) + { + pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL; + } + else + { + pRCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + } + else + { + pRCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_LSIRDY) != 0UL) + { + pRCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + pRCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL1 configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_PLL1RDY) != 0UL) + { + cfgr_value = RCC->PLL1CFGR1; + pRCC_OscInitStruct->PLL1.PLLState = RCC_PLL_ON; + pRCC_OscInitStruct->PLL1.PLLSource = (cfgr_value & RCC_PLL1CFGR1_PLL1SEL); + pRCC_OscInitStruct->PLL1.PLLM = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos); + pRCC_OscInitStruct->PLL1.PLLN = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos); + pRCC_OscInitStruct->PLL1.PLLFractional = (READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> \ + RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos); + cfgr_value = RCC->PLL1CFGR3; + pRCC_OscInitStruct->PLL1.PLLP1 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos); + pRCC_OscInitStruct->PLL1.PLLP2 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos); + } + else + { + cfgr_value = RCC->PLL1CFGR1; + if ((cfgr_value & RCC_PLL1CFGR1_PLL1BYP) != 0UL) + { + pRCC_OscInitStruct->PLL1.PLLState = RCC_PLL_BYPASS; + } + else + { + pRCC_OscInitStruct->PLL1.PLLState = RCC_PLL_OFF; + } + } + + /* Get the PLL2 configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_PLL2RDY) != 0UL) + { + cfgr_value = RCC->PLL2CFGR1; + pRCC_OscInitStruct->PLL2.PLLState = RCC_PLL_ON; + pRCC_OscInitStruct->PLL2.PLLSource = (cfgr_value & RCC_PLL2CFGR1_PLL2SEL); + pRCC_OscInitStruct->PLL2.PLLM = ((cfgr_value & RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos); + pRCC_OscInitStruct->PLL2.PLLN = ((cfgr_value & RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos); + pRCC_OscInitStruct->PLL2.PLLFractional = (READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> \ + RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos); + cfgr_value = RCC->PLL2CFGR3; + pRCC_OscInitStruct->PLL2.PLLP1 = ((cfgr_value & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos); + pRCC_OscInitStruct->PLL2.PLLP2 = ((cfgr_value & RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos); + } + else + { + cfgr_value = RCC->PLL2CFGR1; + if ((cfgr_value & RCC_PLL2CFGR1_PLL2BYP) != 0UL) + { + pRCC_OscInitStruct->PLL2.PLLState = RCC_PLL_BYPASS; + } + else + { + pRCC_OscInitStruct->PLL2.PLLState = RCC_PLL_OFF; + } + } + + /* Get the PLL3 configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_PLL3RDY) != 0UL) + { + cfgr_value = RCC->PLL3CFGR1; + pRCC_OscInitStruct->PLL3.PLLState = RCC_PLL_ON; + pRCC_OscInitStruct->PLL3.PLLSource = (cfgr_value & RCC_PLL3CFGR1_PLL3SEL); + pRCC_OscInitStruct->PLL3.PLLM = ((cfgr_value & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos); + pRCC_OscInitStruct->PLL3.PLLN = ((cfgr_value & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos); + pRCC_OscInitStruct->PLL3.PLLFractional = (READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> \ + RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos); + cfgr_value = RCC->PLL3CFGR3; + pRCC_OscInitStruct->PLL3.PLLP1 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos); + pRCC_OscInitStruct->PLL3.PLLP2 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos); + } + else + { + cfgr_value = RCC->PLL3CFGR1; + if ((cfgr_value & RCC_PLL3CFGR1_PLL3BYP) != 0UL) + { + pRCC_OscInitStruct->PLL3.PLLState = RCC_PLL_BYPASS; + } + else + { + pRCC_OscInitStruct->PLL3.PLLState = RCC_PLL_OFF; + } + } + + /* Get the PLL4 configuration -----------------------------------------------*/ + if ((sr_value & RCC_SR_PLL4RDY) != 0UL) + { + cfgr_value = RCC->PLL4CFGR1; + pRCC_OscInitStruct->PLL4.PLLState = RCC_PLL_ON; + pRCC_OscInitStruct->PLL4.PLLSource = (cfgr_value & RCC_PLL4CFGR1_PLL4SEL); + pRCC_OscInitStruct->PLL4.PLLM = ((cfgr_value & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos); + pRCC_OscInitStruct->PLL4.PLLN = ((cfgr_value & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos); + pRCC_OscInitStruct->PLL4.PLLFractional = (READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> \ + RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos); + cfgr_value = RCC->PLL4CFGR3; + pRCC_OscInitStruct->PLL4.PLLP1 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos); + pRCC_OscInitStruct->PLL4.PLLP2 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos); + } + else + { + cfgr_value = RCC->PLL4CFGR1; + if ((cfgr_value & RCC_PLL4CFGR1_PLL4BYP) != 0UL) + { + pRCC_OscInitStruct->PLL4.PLLState = RCC_PLL_BYPASS; + } + else + { + pRCC_OscInitStruct->PLL4.PLLState = RCC_PLL_OFF; + } + } +} + +/** + * @brief Get the clocks status configuration in RCC_ClkInitStruct according to + * the internal RCC configuration registers. + * @param pRCC_ClkInitStruct Pointer to an RCC_ClkInitTypeDef structure that + * will return the configuration. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct) +{ + uint32_t cfgr_value; + + /* Set all possible values for the Clock type parameter --------------------*/ + pRCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | \ + RCC_CLOCKTYPE_HCLK | \ + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ + RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5; + + /* Get the configuration register 1 value */ + cfgr_value = RCC->CFGR1; + + /* Get the active CPU source -----------------------------------------------*/ + pRCC_ClkInitStruct->CPUCLKSource = (cfgr_value & RCC_CFGR1_CPUSWS) >> 4U; + + /* Get the active SYSCLK bus source ----------------------------------------*/ + pRCC_ClkInitStruct->SYSCLKSource = (cfgr_value & RCC_CFGR1_SYSSWS) >> 4U; + + /* Get the configuration register 2 value */ + cfgr_value = RCC->CFGR2; + + /* Get the HCLK configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->AHBCLKDivider = (cfgr_value & RCC_CFGR2_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->APB1CLKDivider = (cfgr_value & RCC_CFGR2_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->APB2CLKDivider = (cfgr_value & RCC_CFGR2_PPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->APB4CLKDivider = (cfgr_value & RCC_CFGR2_PPRE4); + + /* Get the APB5 configuration ----------------------------------------------*/ + pRCC_ClkInitStruct->APB5CLKDivider = (cfgr_value & RCC_CFGR2_PPRE5); + + /* Get the IC1 configuration -----------------------------------------------*/ + cfgr_value = RCC->IC1CFGR; + pRCC_ClkInitStruct->IC1Selection.ClockSelection = cfgr_value & RCC_IC1CFGR_IC1SEL; + pRCC_ClkInitStruct->IC1Selection.ClockDivider = ((cfgr_value & RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1U; + + /* Get the IC2 configuration -----------------------------------------------*/ + cfgr_value = RCC->IC2CFGR; + pRCC_ClkInitStruct->IC2Selection.ClockSelection = cfgr_value & RCC_IC2CFGR_IC2SEL; + pRCC_ClkInitStruct->IC2Selection.ClockDivider = ((cfgr_value & RCC_IC2CFGR_IC2INT) >> RCC_IC2CFGR_IC2INT_Pos) + 1U; + + /* Get the IC6 configuration -----------------------------------------------*/ + cfgr_value = RCC->IC6CFGR; + pRCC_ClkInitStruct->IC6Selection.ClockSelection = cfgr_value & RCC_IC6CFGR_IC6SEL; + pRCC_ClkInitStruct->IC6Selection.ClockDivider = ((cfgr_value & RCC_IC6CFGR_IC6INT) >> RCC_IC6CFGR_IC6INT_Pos) + 1U; + + /* Get the IC11 configuration ----------------------------------------------*/ + cfgr_value = RCC->IC11CFGR; + pRCC_ClkInitStruct->IC11Selection.ClockSelection = cfgr_value & RCC_IC11CFGR_IC11SEL; + pRCC_ClkInitStruct->IC11Selection.ClockDivider = ((cfgr_value & RCC_IC11CFGR_IC11INT) >> RCC_IC11CFGR_IC11INT_Pos) + 1U; +} + +/** + * @brief This function handles the RCC HSE CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC HCECSSF interrupt flag */ + if (LL_RCC_IsActiveFlag_HSECSS() == 1U) + { + /* Clear RCC HSE Clock Security System pending flag */ + LL_RCC_ClearFlag_HSECSS(); + + /* RCC HSE Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + } +} + +/** + * @brief RCC HSE Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions + * @brief Attributes management functions. + * +@verbatim + =============================================================================== + ##### RCC attributes functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Configure the RCC item(s) attribute(s). + (+) Get the attribute of an RCC item. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the RCC item(s) attribute(s). + * @note Available attributes are to control the secure, privileged, public and lock access rights of items. + * Default access rights are non-secure, unprivileged, non-public and unlocked. + * @note Secure/non-secure, privileged/unprivileged and public/non-public attributes can be set and reset + * from the secure/privileged state only. + * @note Lock Item attribute can be set from the secure/privileged state only. + * @param Item Item(s) to set attributes on. + * This parameter can be a one value or a combination of @ref RCC_items belonging to the same group of items + * (eg. RCC_ITEM_GROUP_OSC) + * @param Attributes specifies the RCC secure/privilege/public attributes. + * This parameter can be a combination of @ref RCC_attributes + * @retval None + * + */ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + /* Check the parameters */ + assert_param(IS_RCC_ATTRIBUTES(Attributes)); + assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); + + /* Check then configure items groups */ + /* Oscillators group */ + if ((Item & RCC_ITEM_GROUP_OSC) == RCC_ITEM_GROUP_OSC) + { + RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_OSC, Item & RCC_ITEM_GROUP_OSC_MASK, Attributes); + } + + /* PLLs group */ + if ((Item & RCC_ITEM_GROUP_PLL) == RCC_ITEM_GROUP_PLL) + { + RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_PLL, Item & RCC_ITEM_GROUP_PLL_MASK, Attributes); + } + + /* ICxs group */ + if ((Item & RCC_ITEM_GROUP_IC) == RCC_ITEM_GROUP_IC) + { + RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_IC, Item & RCC_ITEM_GROUP_IC_MASK, Attributes); + } + + /* System configs group */ + if ((Item & RCC_ITEM_GROUP_SYSCFG) == RCC_ITEM_GROUP_SYSCFG) + { + RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_SYSCFG, Item & RCC_ITEM_GROUP_SYSCFG_MASK, Attributes); + } + + /* Buses group */ + if ((Item & RCC_ITEM_GROUP_BUS) == RCC_ITEM_GROUP_BUS) + { + RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_BUS, Item & RCC_ITEM_GROUP_BUS_MASK, Attributes); + } + + /* Memories group */ + if ((Item & RCC_ITEM_GROUP_MEM) == RCC_ITEM_GROUP_MEM) + { + RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_MEM, Item & RCC_ITEM_GROUP_MEM_MASK, Attributes); + } +} + +/** + * @brief Get the attributes of an RCC item. + * @note Secured items are available from non-secure state when set as public + * @param Item A single item to get secure/non-secure, public/non-public, privilege/non-privilege and locked + attributes from. This parameter can be a value of RCC_items. + * @param pAttributes pointer to return the attributes (this is a combination of @ref RCC_attributes). + * @retval HAL Status. + * + */ +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes = 0UL; + + /* Check null pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_SINGLE_ITEM_ATTRIBUTES(Item)); + + /* Get the item group index and compute the attribute base register address*/ + uint32_t ItemGroup = (Item & RCC_ITEM_GROUP_MASK) >> RCC_ITEM_GROUP_POS; + uint32_t ItemGroupIdx = 0UL; + while ((ItemGroup >> ItemGroupIdx) != 1UL) + { + ItemGroupIdx++; + } + + __IO const uint32_t *p_rcc_reg = &(RCC->SECCFGR0) + (0x4UL * ItemGroupIdx); + + if ((Item & RCC_ITEM_GROUP_MASK) != RCC_ITEM_GROUP_MEM) + { + /* Get secure attribute */ + attributes |= ((p_rcc_reg[0] & Item) == 0U) ? RCC_ATTR_NSEC : RCC_ATTR_SEC; + + /* Get privilege attribute */ + attributes |= ((p_rcc_reg[1] & Item) == 0U) ? RCC_ATTR_NPRIV : RCC_ATTR_PRIV; + + /* Get lock attribute */ + attributes |= ((p_rcc_reg[2] & Item) == 0U) ? RCC_ATTR_NLOCK : RCC_ATTR_LOCK; + + /* Get public attribute */ + attributes |= ((p_rcc_reg[3] & Item) == 0U) ? RCC_ATTR_NPUB : RCC_ATTR_PUB; + } + else + { + /* For memory group, only public attribute is available */ + attributes |= ((*p_rcc_reg & Item) == 0U) ? RCC_ATTR_NPUB : RCC_ATTR_PUB; + } + + /* Return value */ + *pAttributes = attributes; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_functions RCC Private Functions + * @{ + */ +/** + * @brief Returns the SYSCLK frequency divided, if icx is selected, by icx_divider. + * @param icx_source The intermediate clock source + * @param icx_divider The intermediate clock divider + * + * @retval SYSCLK frequency + */ +static uint32_t RCC_GetSysClockFreq(uint32_t icx_source, uint32_t icx_divider) +{ + uint32_t frequency = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + /* No check on Ready: Won't be selected by hardware if not */ + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: + frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: + frequency = RCC_GET_MSI_FREQUENCY(); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11: + switch (icx_source) + { + case LL_RCC_ICCLKSOURCE_PLL1: + frequency = HAL_RCCEx_GetPLL1CLKFreq(); + frequency = frequency / icx_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + frequency = HAL_RCCEx_GetPLL2CLKFreq(); + frequency = frequency / icx_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + frequency = HAL_RCCEx_GetPLL3CLKFreq(); + frequency = frequency / icx_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + frequency = HAL_RCCEx_GetPLL4CLKFreq(); + frequency = frequency / icx_divider; + break; + default: + /* Unexpected case */ + break; + } + break; + + default: + /* Unexpected case */ + break; + } + + return frequency; +} + +/** + * @brief Configure the requested PLL + * @param PLLnumber PLL number to configure + * @param pPLLInit Pointer to an RCC_PLLInitTypeDef structure that + * contains the configuration parameters. + * @note PLL is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit) +{ + __IO uint32_t *p_rcc_pll_cfgr1_reg; + __IO uint32_t *p_rcc_pll_cfgr2_reg; + __IO uint32_t *p_rcc_pll_cfgr3_reg; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t tickstart; + + p_rcc_pll_cfgr1_reg = &(RCC->PLL1CFGR1) + (((uint32_t)0x4) * PLLnumber); + p_rcc_pll_cfgr2_reg = &(RCC->PLL1CFGR2) + (((uint32_t)0x4) * PLLnumber); + p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber); + + /* !!! WARNING: ONLY INTEGER AND FRACTIONAL MODES MANAGED TODAY !!! */ + if (pPLLInit->PLLState == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource)); + assert_param(IS_RCC_PLLFRACN_VALUE(pPLLInit->PLLFractional)); + assert_param(IS_RCC_PLLM_VALUE(pPLLInit->PLLM)); + assert_param(IS_RCC_PLLN_VALUE(pPLLInit->PLLN)); + assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP1)); + assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2)); + + /* Ensure PLLx is disabled */ + WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is disabled */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber)) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Ensure PLLxMODSSDIS='1' */ + SET_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS); + + /* Clear bypass mode */ + CLEAR_BIT(*p_rcc_pll_cfgr1_reg, RCC_PLL1CFGR1_PLL1BYP); + + /* Configure the PLLx clock source, multiplication and division factors. */ + MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \ + (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \ + | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos))); + MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \ + ((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos))); + + /* Configure PLLx DIVNFRAC */ + MODIFY_REG(*p_rcc_pll_cfgr2_reg, RCC_PLL1CFGR2_PLL1DIVNFRAC, \ + pPLLInit->PLLFractional << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos); + + /* Clear PLLxMODDSEN (Also clear in Fractional Mode to ensure the latch of updated FRAC value when set again) */ + CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODDSEN); + + /* Fractional Mode specificities Management */ + if (pPLLInit->PLLFractional != 0U) + { + /* Set PLLxMODDSEN and DACEN */ + SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN)); + } + + /* Ensure PLLxMODSSRST='1' and Enable PLLx post divider output */ + SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODSSRST | RCC_PLL1CFGR3_PLL1PDIVEN)); + + /* Enable the PLLx */ + WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS << PLLnumber); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is ready */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if (pPLLInit->PLLState == RCC_PLL_BYPASS) + { + assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource)); + + /* Check selected source is ready */ + if (RCC_PLL_Source_IsReady(pPLLInit->PLLSource) == 1U) + { + /* Ensure PLLx is disabled */ + WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is disabled */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber)) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set bypass mode with selected source */ + MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1BYP | RCC_PLL1CFGR1_PLL1SEL), \ + (RCC_PLL1CFGR1_PLL1BYP | pPLLInit->PLLSource)); + } + else + { + ret = HAL_ERROR; + } + } + else if (pPLLInit->PLLState == RCC_PLL_OFF) + { + /* Disable PLLx post divider output */ + CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1PDIVEN); + + /* Ensure PLLx is disabled */ + WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is disabled */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber)) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Clear bypass mode */ + CLEAR_BIT(*p_rcc_pll_cfgr1_reg, RCC_PLL1CFGR1_PLL1BYP); + } + else + { + /* Nothing to do */ + } + + return ret; +} + +/** + * @brief Enable the requested PLL + * @param PLLnumber PLL number to enable + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_PLL_Enable(uint32_t PLLnumber) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t tickstart; + + /* Enable the PLLx */ + WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS << PLLnumber); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is ready */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return ret; +} + +/** + * @brief Check for a new PLL configuration + * @param PLLnumber PLL number + * @param pPLLInit Pointer to an RCC_PLLInitTypeDef structure that + * contains the configuration parameters. * + * @retval 1 if success else 0 + */ +static uint32_t RCC_PLL_IsNewConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit) +{ + __IO const uint32_t *p_rcc_pll_cfgr1_reg, *p_rcc_pll_cfgr2_reg, *p_rcc_pll_cfgr3_reg; + uint32_t ret = 0U; + + /* No assert since done in calling function */ + + p_rcc_pll_cfgr1_reg = &(RCC->PLL1CFGR1) + (((uint32_t)0x4) * PLLnumber); + p_rcc_pll_cfgr2_reg = &(RCC->PLL1CFGR2) + (((uint32_t)0x4) * PLLnumber); + p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber); + + /* !!! WARNING: ONLY INTEGER AND FRACTIONAL MODES MANAGED TODAY !!! */ + + /* Check for PLLCFGR1, PLLCFGR2 and PLLCFGR3 parameters updates */ + if ((*p_rcc_pll_cfgr1_reg & (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN)) != \ + (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \ + | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos))) + { + ret = 1U; /* New PLL configuration */ + } + else if ((*p_rcc_pll_cfgr2_reg & RCC_PLL1CFGR2_PLL1DIVNFRAC) != \ + (pPLLInit->PLLFractional << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)) + { + ret = 1U; /* New PLL configuration */ + } + else if ((*p_rcc_pll_cfgr3_reg & (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2)) != \ + ((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos))) + { + ret = 1U; /* New PLL configuration */ + } + else + { + /* Mode change detection*/ + uint32_t pllState; + + /* Get current Mode*/ + if (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber)) + { + pllState = RCC_PLL_ON; + } + else + { + if ((*p_rcc_pll_cfgr1_reg & RCC_PLL1CFGR1_PLL1BYP) != 0UL) + { + pllState = RCC_PLL_BYPASS; + } + else + { + pllState = RCC_PLL_OFF; + } + } + + /* Compare with new mode */ + if (pllState != pPLLInit->PLLState) + { + ret = 1U; /* New PLL configuration */ + } + } + + return ret; +} + +/** + * @brief Check whether the PLL source is ready + * @param PLLSource PLL source + * @retval 1 if success else 0 + */ +static uint32_t RCC_PLL_Source_IsReady(uint32_t PLLSource) +{ + uint32_t ret = 1U; + + /* No assert since done in calling function */ + + switch (PLLSource) + { + case RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() == 0U) + { + ret = 0U; + } + break; + case RCC_PLLSOURCE_MSI: + if (LL_RCC_MSI_IsReady() == 0U) + { + ret = 0U; + } + break; + case RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() == 0U) + { + ret = 0U; + } + break; + case RCC_PLLSOURCE_PIN: + default: + break; + } + + return ret; +} + +/** + * @brief Check whether PLL sources are available + * @param PLLSource1 First PLL source + * @param PLLSource2 Second PLL source + * @retval 1 if success else 0 + */ +static uint32_t RCC_IC_CheckPLLSources(uint32_t PLLSource1, uint32_t PLLSource2) +{ + uint32_t ret = 1U; + + /* No assert since done in calling function */ + + /* Check PLLSource1 clock source */ + switch (PLLSource1) + { + case LL_RCC_ICCLKSOURCE_PLL1: + if (LL_RCC_PLL1_IsReady() == 0U) + { + if (LL_RCC_PLL1_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + case LL_RCC_ICCLKSOURCE_PLL2: + if (LL_RCC_PLL2_IsReady() == 0U) + { + if (LL_RCC_PLL2_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + case LL_RCC_ICCLKSOURCE_PLL3: + if (LL_RCC_PLL3_IsReady() == 0U) + { + if (LL_RCC_PLL3_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + case LL_RCC_ICCLKSOURCE_PLL4: + if (LL_RCC_PLL4_IsReady() == 0U) + { + if (LL_RCC_PLL4_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + default: + /* Unexpected */ + ret = 0U; + break; + } + + /* Check PLLSource2 clock source */ + switch (PLLSource2) + { + case LL_RCC_ICCLKSOURCE_PLL1: + if (LL_RCC_PLL1_IsReady() == 0U) + { + if (LL_RCC_PLL1_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + case LL_RCC_ICCLKSOURCE_PLL2: + if (LL_RCC_PLL2_IsReady() == 0U) + { + if (LL_RCC_PLL2_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + case LL_RCC_ICCLKSOURCE_PLL3: + if (LL_RCC_PLL3_IsReady() == 0U) + { + if (LL_RCC_PLL3_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + case LL_RCC_ICCLKSOURCE_PLL4: + if (LL_RCC_PLL4_IsReady() == 0U) + { + if (LL_RCC_PLL4_IsEnabledBypass() == 0U) + { + ret = 0U; + } + } + break; + default: + /* Unexpected */ + ret = 0U; + break; + } + + return ret; +} + +/** + * @brief Attribute configuration of a group of Items. + * @param ItemGroupIdx the Item group Index to configure + * @param Item Item(s) to set attributes on. + * This parameter can be a one or a combination of @ref RCC_items, masked with RCC_ITEM_MASK + * @param Attributes specifies the RCC secure/privilege/public/lock attributes. + * This parameter can be a combination of @ref RCC_attributes + * @retval None + */ +static void RCC_ATTR_ConfigItemGroup(uint32_t ItemGroupIdx, uint32_t Item, uint32_t Attributes) +{ + __IO uint32_t *p_rcc_reg = &(RCC->SECCFGR0) + (0x4UL * ItemGroupIdx); + + if (ItemGroupIdx != RCC_ITEM_GROUP_IDX_MEM) + { +#if defined (CPU_IN_SECURE_STATE) + /* Check item security attribute management */ + if ((Attributes & RCC_ATTR_SEC_MASK) == RCC_ATTR_SEC_MASK) + { + /* Configure item security attribute */ + if ((Attributes & RCC_ATTR_SEC) == RCC_ATTR_SEC) + { + SET_BIT(p_rcc_reg[0], Item); + } + else + { + CLEAR_BIT(p_rcc_reg[0], Item); + } + } +#endif /* CPU_IN_SECURE_STATE */ + + /* Check item privilege attribute management */ + if ((Attributes & RCC_ATTR_PRIV_MASK) == RCC_ATTR_PRIV_MASK) + { + /* Configure item privilege attribute */ + if ((Attributes & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) + { + SET_BIT(p_rcc_reg[1], Item); + } + else + { + CLEAR_BIT(p_rcc_reg[1], Item); + } + } + +#if defined (CPU_IN_SECURE_STATE) + /* Check item lock attribute management */ + if ((Attributes & RCC_ATTR_LOCK_MASK) == RCC_ATTR_LOCK_MASK) + { + /* Configure item lock attribute */ + if ((Attributes & RCC_ATTR_LOCK) == RCC_ATTR_LOCK) + { + SET_BIT(p_rcc_reg[2], Item); + } + } + + /* Check item public attribute management */ + if ((Attributes & RCC_ATTR_PUB_MASK) == RCC_ATTR_PUB_MASK) + { + /* Configure item public attribute */ + if ((Attributes & RCC_ATTR_PUB) == RCC_ATTR_PUB) + { + SET_BIT(p_rcc_reg[3], Item); + } + else + { + CLEAR_BIT(p_rcc_reg[3], Item); + } + } +#endif /* CPU_IN_SECURE_STATE */ + } + else + { + /* For memory group, only public attribute is available */ +#if defined (CPU_IN_SECURE_STATE) + /* Check item public attribute management */ + if ((Attributes & RCC_ATTR_PUB_MASK) == RCC_ATTR_PUB_MASK) + { + /* Configure item public attribute */ + if ((Attributes & RCC_ATTR_PUB) == RCC_ATTR_PUB) + { + SET_BIT(*(p_rcc_reg), Item); + } + else + { + CLEAR_BIT(*(p_rcc_reg), Item); + } + } +#endif /* CPU_IN_SECURE_STATE */ + } +} + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c (revision 16) @@ -0,0 +1,5926 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCCEx_Private_Functions_Prototypes RCCEx Private Functions Prototypes + * @{ + */ +static uint32_t RCCEx_GetHCLKFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCCEx_GetPCLK1Freq(uint32_t HCLK_Frequency); +static uint32_t RCCEx_GetPCLK2Freq(uint32_t PCLK_Frequency); +static uint32_t RCCEx_GetPCLK4Freq(uint32_t PCLK_Frequency); +static uint32_t RCCEx_GetPCLK5Freq(uint32_t PCLK_Frequency); +static uint32_t RCCEx_GetPLLSourceFreq(uint32_t PLLsource); +static uint32_t RCCEx_CalcPLLFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, + uint32_t FRACN, uint32_t P1, uint32_t P2); +static uint32_t RCCEx_GetADCCLKFreq(uint32_t ADCxSource); +static uint32_t RCCEx_GetADFCLKFreq(uint32_t ADFxSource); +static uint32_t RCCEx_GetCLKPCLKFreq(uint32_t CLKPxSource); +static uint32_t RCCEx_GetCSICLKFreq(void); +static uint32_t RCCEx_GetDCMIPPCLKFreq(uint32_t DCMIPPxSource); +static uint32_t RCCEx_GetETH1CLKFreq(uint32_t ETH1xSource); +static uint32_t RCCEx_GetETH1PTPCLKFreq(uint32_t ETH1PTPxSource); +static uint32_t RCCEx_GetFDCANCLKFreq(uint32_t FDCANxSource); +static uint32_t RCCEx_GetFMCCLKFreq(uint32_t FMCxSource); +static uint32_t RCCEx_GetI2CCLKFreq(uint32_t I2CxSource); +static uint32_t RCCEx_GetI3CCLKFreq(uint32_t I3CxSource); +static uint32_t RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource); +static uint32_t RCCEx_GetLPUARTCLKFreq(uint32_t LPUARTxSource); +static uint32_t RCCEx_GetLTDCCLKFreq(uint32_t LPTIMxSource); +static uint32_t RCCEx_GetMDFCLKFreq(uint32_t MDFxSource); +static uint32_t RCCEx_GetPSSICLKFreq(uint32_t PSSIxSource); +static uint32_t RCCEx_GetRTCCLKFreq(void); +static uint32_t RCCEx_GetSAICLKFreq(uint32_t SAIxSource); +static uint32_t RCCEx_GetSDMMCCLKFreq(uint32_t SDMMCxSource); +static uint32_t RCCEx_GetSPDIFRXCLKFreq(uint32_t SPDIFRXxSource); +static uint32_t RCCEx_GetSPICLKFreq(uint32_t SPIxSource); +static uint32_t RCCEx_GetUARTCLKFreq(uint32_t UARTxSource); +static uint32_t RCCEx_GetUSARTCLKFreq(uint32_t USARTxSource); +static uint32_t RCCEx_GetOTGPHYCLKFreq(uint32_t OTGPHYxSource); +static uint32_t RCCEx_GetOTGPHYCKREFCLKFreq(uint32_t OTGPHYxCKREFSource); +static uint32_t RCCEx_GetXSPICLKFreq(uint32_t XSPIxSource); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks + * (ADC, ADF1, CKPER, DCMI, DCMIPP, FDCAN, FMC, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, + * LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LTDC, LPUART1, MDF1, PSSI, RTC, SAI1, SAI2, + * SDMMC1, SDMMC2, SPDIFRX1, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, TIM, + * USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, UART9, USART10, + * USBPHY1, USBPHY2, USB OTGHS1, USB OTGHS2, XSPI1, XSPI2, XSPI3). + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * @note Dynamic switches are used for peripheral input clock selection meaning the switch setting + * can only be changed if both input clocks are present during transition time. + * @note Care must be taken when RCC_PPPCLKSOURCE_ICx is selected. The ICx ClockSelection and ClockDivider fields + * modification indeed impacts all peripherals using this ICx as clock source. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* As the RTC clock source selection can be changed only if the Backup Domain is reset */ + /* reset the Backup domain only if the RTC Clock source selection is modified from default reset value */ + tmpreg = LL_RCC_GetRTCClockSource(); + + if ((tmpreg != RCC_RTCCLKSOURCE_DISABLE) && (tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CCIPR7_RTCSEL))) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); + + /* Read back to check Backup domain enabled */ + if (READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == 0U) + { + ret = HAL_ERROR; + } + else + { +#if 0 /* TO DO */ + /* Store the content of BDCR register before the reset of Backup Domain */ + /* excepted the RTC clock source selection that will be changed */ + tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the content of BDCR register */ + WRITE_REG(RCC->BDCR, tmpreg); +#endif /* #if 0 TO DO */ + } + } + + if (ret == HAL_OK) + { + /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ + if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------------ CKPER configuration --------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + { + /* Check the parameters */ + assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection)); + + if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC5) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider)); + + /* Set IC5 configuration */ + MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT, + PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos)); + + LL_RCC_IC5_Enable(); + } + else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC10) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider)); + + /* Set IC10 configuration */ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT, + PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos)); + + LL_RCC_IC10_Enable(); + } + else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC19) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC19].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC19].ClockDivider)); + + /* Set IC19 configuration */ + MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL | RCC_IC19CFGR_IC19INT, + PeriphClkInit->ICSelection[RCC_IC19].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC19].ClockDivider - 1U) << RCC_IC19CFGR_IC19INT_Pos)); + + LL_RCC_IC19_Enable(); + } + else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC20) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC20].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC20].ClockDivider)); + + /* Set IC20 configuration */ + MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL | RCC_IC20CFGR_IC20INT, + PeriphClkInit->ICSelection[RCC_IC20].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC20].ClockDivider - 1U) << RCC_IC20CFGR_IC20INT_Pos)); + + LL_RCC_IC20_Enable(); + } + else + { + /* No ICx selected as source */ + } + + /* Configure the CKPER clock source */ + __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); + } + + /*-------------------------- XSPI1 clock source configuration ----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1) + { + /* Check the parameters */ + assert_param(IS_RCC_XSPI1CLKSOURCE(PeriphClkInit->Xspi1ClockSelection)); + + if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_IC3) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider)); + + /* Set IC3 configuration */ + MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT, + PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos)); + + LL_RCC_IC3_Enable(); + } + else if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_IC4) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider)); + + /* Set IC4 configuration */ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT, + PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos)); + + LL_RCC_IC4_Enable(); + } + else if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Configure the XSPI1 clock source */ + __HAL_RCC_XSPI1_CONFIG(PeriphClkInit->Xspi1ClockSelection); + } + + /*-------------------------- XSPI2 clock source configuration ----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2) + { + /* Check the parameters */ + assert_param(IS_RCC_XSPI2CLKSOURCE(PeriphClkInit->Xspi2ClockSelection)); + + if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_IC3) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider)); + + /* Set IC3 configuration */ + MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT, + PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos)); + + LL_RCC_IC3_Enable(); + } + else if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_IC4) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider)); + + /* Set IC4 configuration */ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT, + PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos)); + + LL_RCC_IC4_Enable(); + } + else if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Configure the XSPI2 clock source */ + __HAL_RCC_XSPI2_CONFIG(PeriphClkInit->Xspi2ClockSelection); + } + + /*-------------------------- XSPI3 clock source configuration ----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI3) == RCC_PERIPHCLK_XSPI3) + { + /* Check the parameters */ + assert_param(IS_RCC_XSPI3CLKSOURCE(PeriphClkInit->Xspi3ClockSelection)); + + if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_IC3) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider)); + + /* Set IC3 configuration */ + MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT, + PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos)); + + LL_RCC_IC3_Enable(); + } + else if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_IC4) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider)); + + /* Set IC4 configuration */ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT, + PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos)); + + LL_RCC_IC4_Enable(); + } + else if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Configure the XSPI3 clock source */ + __HAL_RCC_XSPI3_CONFIG(PeriphClkInit->Xspi3ClockSelection); + } + + /*---------------------------- FMC configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + { + /* Check the parameters */ + assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection)); + + if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_IC3) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider)); + + /* Set IC3 configuration */ + MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT, + PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos)); + + LL_RCC_IC3_Enable(); + } + else if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_IC4) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider)); + + /* Set IC4 configuration */ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT, + PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos)); + + LL_RCC_IC4_Enable(); + } + else if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of FMC kernel clock*/ + __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_IC4) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider)); + + /* Set IC4 configuration */ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT, + PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos)); + + LL_RCC_IC4_Enable(); + } + else if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_IC5) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider)); + + /* Set IC5 configuration */ + MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT, + PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos)); + + LL_RCC_IC5_Enable(); + } + else if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SDMMC1 clock*/ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_IC4) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider)); + + /* Set IC4 configuration */ + MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT, + PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos)); + + LL_RCC_IC4_Enable(); + } + else if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_IC5) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider)); + + /* Set IC5 configuration */ + MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT, + PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos)); + + LL_RCC_IC5_Enable(); + } + else if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SDMMC2 clock*/ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*---------------------------- ADC configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + assert_param(IS_RCC_ADCDIVIDER(PeriphClkInit->AdcDivider)); + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_IC7) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider)); + + /* Set IC7 configuration */ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT, + PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos)); + + LL_RCC_IC7_Enable(); + } + else if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Configure the ADC clock source and divider */ + MODIFY_REG(RCC->CCIPR1, (RCC_CCIPR1_ADCPRE | RCC_CCIPR1_ADC12SEL), \ + (((PeriphClkInit->AdcDivider - 1U) << RCC_CCIPR1_ADCPRE_Pos) | (PeriphClkInit->AdcClockSelection))); + } + + /*---------------------------- ADF1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) + { + /* Check the parameters */ + assert_param(IS_RCC_ADF1CLKSOURCE(PeriphClkInit->Adf1ClockSelection)); + + if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_IC7) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider)); + + /* Set IC7 configuration */ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT, + PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos)); + + LL_RCC_IC7_Enable(); + } + else if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of ADF1 clock*/ + __HAL_RCC_ADF1_CONFIG(PeriphClkInit->Adf1ClockSelection); + } + + /*------------------------------------ CSI configuration --------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CSI) == RCC_PERIPHCLK_CSI) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC18].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC18].ClockDivider)); + + /* Set IC18 configuration */ + MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL | RCC_IC18CFGR_IC18INT, + PeriphClkInit->ICSelection[RCC_IC18].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC18].ClockDivider - 1U) << RCC_IC18CFGR_IC18INT_Pos)); + + LL_RCC_IC18_Enable(); + } + + /*---------------------- DCMIPP configuration ------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_DCMIPP) == RCC_PERIPHCLK_DCMIPP) + { + /* Check the parameters */ + assert_param(IS_RCC_DCMIPPCLKSOURCE(PeriphClkInit->DcmippClockSelection)); + + if (PeriphClkInit->DcmippClockSelection == RCC_DCMIPPCLKSOURCE_IC17) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC17].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC17].ClockDivider)); + + /* Set IC17 configuration */ + MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL | RCC_IC17CFGR_IC17INT, + PeriphClkInit->ICSelection[RCC_IC17].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC17].ClockDivider - 1U) << RCC_IC17CFGR_IC17INT_Pos)); + + LL_RCC_IC17_Enable(); + } + else if (PeriphClkInit->DcmippClockSelection == RCC_DCMIPPCLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Configure the CEC clock source */ + __HAL_RCC_DCMIPP_CONFIG(PeriphClkInit->DcmippClockSelection); + } + + /*---------------------- ETH1 configuration --------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1) == RCC_PERIPHCLK_ETH1) + { + /* Check the parameters */ + assert_param(IS_RCC_ETH1CLKSOURCE(PeriphClkInit->Eth1ClockSelection)); + + if (PeriphClkInit->Eth1ClockSelection == RCC_ETH1CLKSOURCE_IC12) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC12].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC12].ClockDivider)); + + /* Set IC12 configuration */ + MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL | RCC_IC12CFGR_IC12INT, + PeriphClkInit->ICSelection[RCC_IC12].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC12].ClockDivider - 1U) << RCC_IC12CFGR_IC12INT_Pos)); + + LL_RCC_IC12_Enable(); + } + else if (PeriphClkInit->Eth1ClockSelection == RCC_ETH1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Configure the ETH1 clock source */ + __HAL_RCC_ETH1_CONFIG(PeriphClkInit->Eth1ClockSelection); + } + + /*---------------------- ETH1PHY configuration -----------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY) + { + /* Check the parameters */ + assert_param(IS_RCC_ETH1PHYIF(PeriphClkInit->Eth1PhyInterfaceSelection)); + + /* Configure the source of ETH1 PHY interface */ + __HAL_RCC_ETH1PHY_CONFIG(PeriphClkInit->Eth1PhyInterfaceSelection); + } + + /*---------------------- ETH1 RX configuration -----------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1RX) == RCC_PERIPHCLK_ETH1RX) + { + /* Check the parameters */ + assert_param(IS_RCC_ETH1RXCLKSOURCE(PeriphClkInit->Eth1RxClockSelection)); + + /* Configure the ETH1 RX clock source */ + __HAL_RCC_ETH1RX_CONFIG(PeriphClkInit->Eth1RxClockSelection); + } + + /*---------------------- ETH1 TX configuration -----------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1TX) == RCC_PERIPHCLK_ETH1TX) + { + /* Check the parameters */ + assert_param(IS_RCC_ETH1TXCLKSOURCE(PeriphClkInit->Eth1TxClockSelection)); + + /* Configure the ETH1 TX clock source */ + __HAL_RCC_ETH1TX_CONFIG(PeriphClkInit->Eth1TxClockSelection); + } + + /*---------------------- ETH1 PTP configuration ----------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PTP) == RCC_PERIPHCLK_ETH1PTP) + { + /* Check the parameters */ + assert_param(IS_RCC_ETH1PTPCLKSOURCE(PeriphClkInit->Eth1PtpClockSelection)); + assert_param(IS_RCC_ETH1PTPDIVIDER(PeriphClkInit->Eth1PtpDivider)); + + if (PeriphClkInit->Eth1PtpClockSelection == RCC_ETH1PTPCLKSOURCE_IC13) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC13].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC13].ClockDivider)); + + /* Set IC13 configuration */ + MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL | RCC_IC13CFGR_IC13INT, + PeriphClkInit->ICSelection[RCC_IC13].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC13].ClockDivider - 1U) << RCC_IC13CFGR_IC13INT_Pos)); + + LL_RCC_IC13_Enable(); + } + else if (PeriphClkInit->Eth1PtpClockSelection == RCC_ETH1PTPCLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Configure the ETH1 PTP clock source and divider */ + MODIFY_REG(RCC->CCIPR2, (RCC_CCIPR2_ETH1PTPDIV | RCC_CCIPR2_ETH1PTPSEL), \ + (((PeriphClkInit->Eth1PtpDivider - 1U) << RCC_CCIPR2_ETH1PTPDIV_Pos) | \ + PeriphClkInit->Eth1PtpClockSelection)); + } + + /*---------------------- FDCAN configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + /* Check the parameters */ + assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); + + if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_IC19) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC19].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC19].ClockDivider)); + + /* Set IC19 configuration */ + MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL | RCC_IC19CFGR_IC19INT, + PeriphClkInit->ICSelection[RCC_IC19].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC19].ClockDivider - 1U) << RCC_IC19CFGR_IC19INT_Pos)); + + LL_RCC_IC19_Enable(); + } + else if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of FDCAN clock*/ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + } + + /*------------------------------ I2C1 Configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_IC10) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider)); + + /* Set IC10 configuration */ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT, + PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos)); + + LL_RCC_IC10_Enable(); + } + else if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of I2C1 clock*/ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*------------------------------ I2C2 Configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_IC10) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider)); + + /* Set IC10 configuration */ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT, + PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos)); + + LL_RCC_IC10_Enable(); + } + else if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of I2C2 clock*/ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*------------------------------ I2C3 Configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_IC10) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider)); + + /* Set IC10 configuration */ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT, + PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos)); + + LL_RCC_IC10_Enable(); + } + else if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of I2C3 clock*/ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*------------------------------ I2C4 Configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_IC10) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider)); + + /* Set IC10 configuration */ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT, + PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos)); + + LL_RCC_IC10_Enable(); + } + else if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of I2C4 clock*/ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + } + + /*------------------------------ I3C1 Configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I3C1CLKSOURCE(PeriphClkInit->I3c1ClockSelection)); + + if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_IC10) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider)); + + /* Set IC10 configuration */ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT, + PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos)); + + LL_RCC_IC10_Enable(); + } + else if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of I3C1 clock*/ + __HAL_RCC_I3C1_CONFIG(PeriphClkInit->I3c1ClockSelection); + } + + /*------------------------------ I3C2 Configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I3C2CLKSOURCE(PeriphClkInit->I3c2ClockSelection)); + + if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_IC10) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider)); + + /* Set IC10 configuration */ + MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT, + PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos)); + + LL_RCC_IC10_Enable(); + } + else if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of I3C2 clock*/ + __HAL_RCC_I3C2_CONFIG(PeriphClkInit->I3c2ClockSelection); + } + + /*---------------------------- LPTIM1 configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + if (PeriphClkInit->Lptim1ClockSelection == RCC_LPTIM1CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->Lptim1ClockSelection == RCC_LPTIM1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of LPTIM1 clock*/ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*---------------------------- LPTIM2 configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + + if (PeriphClkInit->Lptim2ClockSelection == RCC_LPTIM2CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->Lptim2ClockSelection == RCC_LPTIM2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of LPTIM2 clock*/ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } + + /*---------------------------- LPTIM3 configuration -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection)); + + if (PeriphClkInit->Lptim3ClockSelection == RCC_LPTIM3CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->Lptim3ClockSelection == RCC_LPTIM3CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of LPTIM3 clock */ + __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection); + } + + /*---------------------------- LPTIM4 configuration -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM4CLKSOURCE(PeriphClkInit->Lptim4ClockSelection)); + + if (PeriphClkInit->Lptim4ClockSelection == RCC_LPTIM4CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->Lptim4ClockSelection == RCC_LPTIM4CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of LPTIM4 clock */ + __HAL_RCC_LPTIM4_CONFIG(PeriphClkInit->Lptim4ClockSelection); + } + + /*---------------------------- LPTIM5 configuration -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM5CLKSOURCE(PeriphClkInit->Lptim5ClockSelection)); + + if (PeriphClkInit->Lptim5ClockSelection == RCC_LPTIM5CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->Lptim5ClockSelection == RCC_LPTIM5CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of LPTIM5 clock */ + __HAL_RCC_LPTIM5_CONFIG(PeriphClkInit->Lptim5ClockSelection); + } + + /*-------------------------- LPUART1 Configuration -------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of LPUART1 clock */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + + /*-------------------------- LTDC Configuration ----------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + /* Check the parameters */ + assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection)); + + if (PeriphClkInit->LtdcClockSelection == RCC_LTDCCLKSOURCE_IC16) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC16].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC16].ClockDivider)); + + /* Set IC16 configuration */ + MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL | RCC_IC16CFGR_IC16INT, + PeriphClkInit->ICSelection[RCC_IC16].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC16].ClockDivider - 1U) << RCC_IC16CFGR_IC16INT_Pos)); + + LL_RCC_IC16_Enable(); + } + else if (PeriphClkInit->LtdcClockSelection == RCC_LTDCCLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of LTDC clock */ + __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); + } + + /*---------------------------- MDF1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1) + { + /* Check the parameters */ + assert_param(IS_RCC_MDF1CLKSOURCE(PeriphClkInit->Mdf1ClockSelection)); + + if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_IC7) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider)); + + /* Set IC7 configuration */ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT, + PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos)); + + LL_RCC_IC7_Enable(); + } + else if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of MDF1 clock*/ + __HAL_RCC_MDF1_CONFIG(PeriphClkInit->Mdf1ClockSelection); + } + + /*---------------------------- PSSI configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI) + { + /* Check the parameters */ + assert_param(IS_RCC_PSSICLKSOURCE(PeriphClkInit->PssiClockSelection)); + + if (PeriphClkInit->PssiClockSelection == RCC_PSSICLKSOURCE_IC20) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC20].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC20].ClockDivider)); + + /* Set IC20 configuration */ + MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL | RCC_IC20CFGR_IC20INT, + PeriphClkInit->ICSelection[RCC_IC20].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC20].ClockDivider - 1U) << RCC_IC20CFGR_IC20INT_Pos)); + + LL_RCC_IC20_Enable(); + } + else if (PeriphClkInit->PssiClockSelection == RCC_PSSICLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of PSSI clock*/ + __HAL_RCC_PSSI_CONFIG(PeriphClkInit->PssiClockSelection); + } + + /*---------------------------- SAI1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_IC7) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider)); + + /* Set IC7 configuration */ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT, + PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos)); + + LL_RCC_IC7_Enable(); + } + else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + } + + /*---------------------------- SAI2 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_IC7) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider)); + + /* Set IC7 configuration */ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT, + PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos)); + + LL_RCC_IC7_Enable(); + } + else if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SAI2 clock*/ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + } + + /*---------------------------- SPDIFRX1 configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPDIFRX1) == RCC_PERIPHCLK_SPDIFRX1) + { + /* Check the parameters */ + assert_param(IS_RCC_SPDIFRX1CLKSOURCE(PeriphClkInit->Spdifrx1ClockSelection)); + + if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_IC7) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider)); + + /* Set IC7 configuration */ + MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT, + PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos)); + + LL_RCC_IC7_Enable(); + } + else if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SPDIFRX1 clock */ + __HAL_RCC_SPDIFRX1_CONFIG(PeriphClkInit->Spdifrx1ClockSelection); + } + + /*---------------------------- SPI1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection)); + + if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SPI1 clock*/ + __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection); + } + + /*---------------------------- SPI2 configuration ---------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI2CLKSOURCE(PeriphClkInit->Spi2ClockSelection)); + + if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SPI2 clock*/ + __HAL_RCC_SPI2_CONFIG(PeriphClkInit->Spi2ClockSelection); + } + + /*---------------------------- SPI3 configuration ---------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI3CLKSOURCE(PeriphClkInit->Spi3ClockSelection)); + + if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SPI3 clock*/ + __HAL_RCC_SPI3_CONFIG(PeriphClkInit->Spi3ClockSelection); + } + + /*---------------------------- SPI4 configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI4CLKSOURCE(PeriphClkInit->Spi4ClockSelection)); + + if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SPI4 clock */ + __HAL_RCC_SPI4_CONFIG(PeriphClkInit->Spi4ClockSelection); + } + + /*---------------------------- SPI5 configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI5CLKSOURCE(PeriphClkInit->Spi5ClockSelection)); + + if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SPI5 clock */ + __HAL_RCC_SPI5_CONFIG(PeriphClkInit->Spi5ClockSelection); + } + + /*---------------------------- SPI6 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection)); + + if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_IC8) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider)); + + /* Set IC8 configuration */ + MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT, + PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos)); + + LL_RCC_IC8_Enable(); + } + else if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of SPI6 clock*/ + __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); + } + + /*-------------------------- USART1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of USART1 clock */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------- USART2 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of USART2 clock */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------- USART3 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of USART3 clock */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------- UART4 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of UART4 clock */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------- UART5 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of UART5 clock */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------- USART6 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of USART6 clock */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------- UART7 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of UART7 clock */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------- UART8 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of UART8 clock */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*-------------------------- UART9 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9) + { + /* Check the parameters */ + assert_param(IS_RCC_UART9CLKSOURCE(PeriphClkInit->Uart9ClockSelection)); + + if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of UART9 clock */ + __HAL_RCC_UART9_CONFIG(PeriphClkInit->Uart9ClockSelection); + } + + /*-------------------------- USART10 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10) + { + /* Check the parameters */ + assert_param(IS_RCC_USART10CLKSOURCE(PeriphClkInit->Usart10ClockSelection)); + + if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_IC9) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider)); + + /* Set IC9 configuration */ + MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT, + PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos)); + + LL_RCC_IC9_Enable(); + } + else if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_IC14) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider)); + + /* Set IC14 configuration */ + MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT, + PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos)); + + LL_RCC_IC14_Enable(); + } + else if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of USART10 clock */ + __HAL_RCC_USART10_CONFIG(PeriphClkInit->Usart10ClockSelection); + } + + /*------------------------------ USBPHY1 Configuration ---------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHY1) == RCC_PERIPHCLK_USBPHY1) + { + /* Check the parameters */ + assert_param(IS_RCC_USBPHY1CLKSOURCE(PeriphClkInit->UsbPhy1ClockSelection)); + + if (PeriphClkInit->UsbPhy1ClockSelection == RCC_USBPHY1CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->UsbPhy1ClockSelection == RCC_USBPHY1CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of USBPHY1 clock*/ + __HAL_RCC_USBPHY1_CONFIG(PeriphClkInit->UsbPhy1ClockSelection); + } + + /*------------------------------ USBPHY2 Configuration ---------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHY2) == RCC_PERIPHCLK_USBPHY2) + { + /* Check the parameters */ + assert_param(IS_RCC_USBPHY2CLKSOURCE(PeriphClkInit->UsbPhy2ClockSelection)); + + if (PeriphClkInit->UsbPhy2ClockSelection == RCC_USBPHY2CLKSOURCE_IC15) + { + /* Check the parameters */ + assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection)); + assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider)); + + /* Set IC15 configuration */ + MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT, + PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \ + ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos)); + + LL_RCC_IC15_Enable(); + } + else if (PeriphClkInit->UsbPhy2ClockSelection == RCC_USBPHY2CLKSOURCE_CLKP) + { + LL_RCC_CLKP_Enable(); + } + else + { + /* No specific enable to do on other sources */ + } + + /* Set the source of USBPHY2 clock*/ + __HAL_RCC_USBPHY2_CONFIG(PeriphClkInit->UsbPhy2ClockSelection); + } + + /*------------------------------ USBOTGHS1 Configuration -------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGHS1) == RCC_PERIPHCLK_USBOTGHS1) + { + /* Check the parameters */ + assert_param(IS_RCC_USBOTGHS1CLKSOURCE(PeriphClkInit->UsbOtgHs1ClockSelection)); + + /* Set the source of USBOTGHS1 clock */ + __HAL_RCC_USBOTGHS1_CONFIG(PeriphClkInit->UsbOtgHs1ClockSelection); + } + + /*------------------------------ USBOTGHS2 Configuration -------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGHS2) == RCC_PERIPHCLK_USBOTGHS2) + { + /* Check the parameters */ + assert_param(IS_RCC_USBOTGHS2CLKSOURCE(PeriphClkInit->UsbOtgHs2ClockSelection)); + + /* Set the source of USBOTGHS2 clock */ + __HAL_RCC_USBOTGHS2_CONFIG(PeriphClkInit->UsbOtgHs2ClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER_CONFIG(PeriphClkInit->TIMPresSelection); + } + + if (status == HAL_OK) + { + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks : + * (ADC, ADF1, CKPER, DCMI, DCMIPP, FDCAN, FMC, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, + * LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LTDC, LPUART1, MDF1, PSSI, RTC, SAI1, SAI2, + * SDMMC1, SDMMC2, SPDIFRX1, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, TIM, + * USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, UART9, USART10, + * USBPHYC, USB OTGFS, XSPI1, XSPI2, XSPI3). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + const __IO uint32_t *p_icxcfgr; + uint32_t icx_val; + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_CKPER | \ + RCC_PERIPHCLK_CSI | RCC_PERIPHCLK_DCMIPP | RCC_PERIPHCLK_ETH1 | \ + RCC_PERIPHCLK_ETH1PHY | RCC_PERIPHCLK_ETH1RX | RCC_PERIPHCLK_ETH1TX | \ + RCC_PERIPHCLK_ETH1PTP | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_FMC | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3 | \ + RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_PSSI | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | RCC_PERIPHCLK_SPDIFRX1 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | \ + RCC_PERIPHCLK_UART9 | RCC_PERIPHCLK_USART10 | \ + RCC_PERIPHCLK_XSPI1 | RCC_PERIPHCLK_XSPI2 | RCC_PERIPHCLK_XSPI3 | \ + RCC_PERIPHCLK_USBPHY1 | RCC_PERIPHCLK_USBOTGHS1 | \ + RCC_PERIPHCLK_USBPHY2 | RCC_PERIPHCLK_USBOTGHS2; + + /* Get IC x dividers */ + p_icxcfgr = &(RCC->IC1CFGR); + for (uint32_t i = 0; i < 20U; i++) + { + icx_val = *p_icxcfgr; + PeriphClkInit->ICSelection[i].ClockSelection = (icx_val & RCC_IC1CFGR_IC1SEL); + PeriphClkInit->ICSelection[i].ClockDivider = ((icx_val & RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1U; + p_icxcfgr++; + } + + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + /* Get the ADC divider ------------------------------------------------*/ + PeriphClkInit->AdcDivider = __HAL_RCC_GET_ADC_DIVIDER(); + /* Get the ADF1 clock source -----------------------------------------------*/ + PeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); + /* Get the CKPER clock source ----------------------------------------------*/ + PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); + /* Get the DCMIPP clock source ---------------------------------------------*/ + PeriphClkInit->DcmippClockSelection = __HAL_RCC_GET_DCMIPP_SOURCE(); + /* Get the ETH1 clock source -----------------------------------------------*/ + PeriphClkInit->Eth1ClockSelection = __HAL_RCC_GET_ETH1_SOURCE(); + /* Get the ETH1 PHY interface ----------------------------------------------*/ + PeriphClkInit->Eth1PhyInterfaceSelection = __HAL_RCC_GET_ETH1PHY_INTERFACE(); + /* Get the ETH1 RX clock source --------------------------------------------*/ + PeriphClkInit->Eth1RxClockSelection = __HAL_RCC_GET_ETH1RX_SOURCE(); + /* Get the ETH1 TX clock source --------------------------------------------*/ + PeriphClkInit->Eth1TxClockSelection = __HAL_RCC_GET_ETH1TX_SOURCE(); + /* Get the ETH1 PTP clock source -------------------------------------------*/ + PeriphClkInit->Eth1PtpClockSelection = __HAL_RCC_GET_ETH1PTP_SOURCE(); + /* Get the ETH1 PTP divider ------------------------------------------------*/ + PeriphClkInit->Eth1PtpDivider = __HAL_RCC_GET_ETH1PTP_DIVIDER(); + /* Get the FDCAN kernel clock source ---------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + /* Get the FMC kernel clock source -----------------------------------------*/ + PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + /* Get the I2C2 clock source -----------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + /* Get the I2C3 clock source -----------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + /* Get the I2C4 clock source -----------------------------------------------*/ + PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); + /* Get the I3C1 clock source -----------------------------------------------*/ + PeriphClkInit->I3c1ClockSelection = __HAL_RCC_GET_I3C1_SOURCE(); + /* Get the I3C2 clock source -----------------------------------------------*/ + PeriphClkInit->I3c2ClockSelection = __HAL_RCC_GET_I3C2_SOURCE(); + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + /* Get the LPTIM3 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE(); + /* Get the LPTIM4 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim4ClockSelection = __HAL_RCC_GET_LPTIM4_SOURCE(); + /* Get the LPTIM5 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim5ClockSelection = __HAL_RCC_GET_LPTIM5_SOURCE(); + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); + /* Get the LTDC clock source -----------------------------------------------*/ + PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); + /* Get the MDF1 clock source -----------------------------------------------*/ + PeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE(); + /* Get the PSSI clock source -----------------------------------------------*/ + PeriphClkInit->PssiClockSelection = __HAL_RCC_GET_PSSI_SOURCE(); + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the SAI1 clock source -----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + /* Get the SAI2 clock source -----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + /* Get the SDMMC1 clock source ---------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + /* Get the SDMMC2 clock source ---------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + /* Get the SPDIFRX1 clock source -------------------------------------------*/ + PeriphClkInit->Spdifrx1ClockSelection = __HAL_RCC_GET_SPDIFRX1_SOURCE(); + /* Get the SPI1 clock source -----------------------------------------------*/ + PeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE(); + /* Get the SPI2 clock source -----------------------------------------------*/ + PeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE(); + /* Get the SPI3 clock source -----------------------------------------------*/ + PeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE(); + /* Get the SPI4 clock source -----------------------------------------------*/ + PeriphClkInit->Spi4ClockSelection = __HAL_RCC_GET_SPI4_SOURCE(); + /* Get the SPI5 clock source -----------------------------------------------*/ + PeriphClkInit->Spi5ClockSelection = __HAL_RCC_GET_SPI5_SOURCE(); + /* Get the SPI6 clock source -----------------------------------------------*/ + PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); + /* Get the TIM Prescaler configuration -------------------------------------*/ + PeriphClkInit->TIMPresSelection = __HAL_RCC_GET_TIMCLKPRESCALER(); + /* Get the USART1 clock source ---------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + /* Get the USART3 clock source ---------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + /* Get the UART4 clock source ----------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + /* Get the UART5 clock source ----------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + /* Get the USART6 clock source ---------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + /* Get the UART7 clock source ----------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + /* Get the UART8 clock source ----------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + /* Get the UART9 clock source ----------------------------------------------*/ + PeriphClkInit->Uart9ClockSelection = __HAL_RCC_GET_UART9_SOURCE(); + /* Get the USART10 clock source --------------------------------------------*/ + PeriphClkInit->Usart10ClockSelection = __HAL_RCC_GET_USART10_SOURCE(); + /* Get the USBPHY1 clock source --------------------------------------------*/ + PeriphClkInit->UsbPhy1ClockSelection = __HAL_RCC_GET_USBPHY1_SOURCE(); + /* Get the USB OTGHS1 clock source -----------------------------------------*/ + PeriphClkInit->UsbOtgHs1ClockSelection = __HAL_RCC_GET_USBOTGHS1_SOURCE(); + /* Get the USBPHY2 clock source --------------------------------------------*/ + PeriphClkInit->UsbPhy2ClockSelection = __HAL_RCC_GET_USBPHY2_SOURCE(); + /* Get the USB OTGHS2 clock source -----------------------------------------*/ + PeriphClkInit->UsbOtgHs2ClockSelection = __HAL_RCC_GET_USBOTGHS2_SOURCE(); + /* Get the XSPI1 clock source ----------------------------------------------*/ + PeriphClkInit->Xspi1ClockSelection = __HAL_RCC_GET_XSPI1_SOURCE(); + /* Get the XSPI2 clock source ----------------------------------------------*/ + PeriphClkInit->Xspi2ClockSelection = __HAL_RCC_GET_XSPI2_SOURCE(); + /* Get the XSPI3 clock source ----------------------------------------------*/ + PeriphClkInit->Xspi3ClockSelection = __HAL_RCC_GET_XSPI3_SOURCE(); +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral (SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API or + * if the selected clock source is not enabled (HSI, PLLs clock output..) + * @param PeriphClk: Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock + * @arg RCC_PERIPHCLK_ADF1 : ADF1 peripheral clock + * @arg RCC_PERIPHCLK_CSI : CSI peripheral clock + * @arg RCC_PERIPHCLK_DCMIPP : DCMIPP peripheral clock + * @arg RCC_PERIPHCLK_I2C1 : I2C1 peripheral clock + * @arg RCC_PERIPHCLK_I2C2 : I2C2 peripheral clock + * @arg RCC_PERIPHCLK_I2C3 : I2C3 peripheral clock + * @arg RCC_PERIPHCLK_I2C4 : I2C4 peripheral clock + * @arg RCC_PERIPHCLK_I3C1 : I3C1 peripheral clock + * @arg RCC_PERIPHCLK_I3C2 : I3C2 peripheral clock + * @arg RCC_PERIPHCLK_FDCAN : FDCAN peripheral clock + * @arg RCC_PERIPHCLK_FMC : FMC peripheral clock + * @arg RCC_PERIPHCLK_LPTIM1 : LPTIM1 peripheral clock + * @arg RCC_PERIPHCLK_LPTIM2 : LPTIM2 peripheral clock + * @arg RCC_PERIPHCLK_LPTIM3 : LPTIM3 peripheral clock + * @arg RCC_PERIPHCLK_LPTIM4 : LPTIM4 peripheral clock + * @arg RCC_PERIPHCLK_LPTIM5 : LPTIM5 peripheral clock + * @arg RCC_PERIPHCLK_LPUART1 : LPUART1 peripheral clock + * @arg RCC_PERIPHCLK_LTDC : LTDC peripheral clock + * @arg RCC_PERIPHCLK_MDF1 : MDF1 peripheral clock + * @arg RCC_PERIPHCLK_PSSI : PSSI peripheral clock + * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2 : SAI2 peripheral clock + * @arg RCC_PERIPHCLK_SDMMC1 : SDMMC1 peripheral clock + * @arg RCC_PERIPHCLK_SDMMC2 : SDMMC2 peripheral clock + * @arg RCC_PERIPHCLK_SPDIFRX1 : SPDIFRX1 peripheral clock + * @arg RCC_PERIPHCLK_SPI1 : SPI1 peripheral clock + * @arg RCC_PERIPHCLK_SPI2 : SPI2 peripheral clock + * @arg RCC_PERIPHCLK_SPI3 : SPI3 peripheral clock + * @arg RCC_PERIPHCLK_SPI4 : SPI4 peripheral clock + * @arg RCC_PERIPHCLK_SPI5 : SPI5 peripheral clock + * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock + * @arg RCC_PERIPHCLK_USART1 : USART1 peripheral clock + * @arg RCC_PERIPHCLK_USART2 : USART2 peripheral clock + * @arg RCC_PERIPHCLK_USART3 : USART3 peripheral clock + * @arg RCC_PERIPHCLK_UART4 : UART4 peripheral clock + * @arg RCC_PERIPHCLK_UART5 : UART5 peripheral clock + * @arg RCC_PERIPHCLK_USART6 : USART6 peripheral clock + * @arg RCC_PERIPHCLK_UART7 : UART7 peripheral clock + * @arg RCC_PERIPHCLK_UART8 : UART8 peripheral clock + * @arg RCC_PERIPHCLK_UART9 : UART9 peripheral clock + * @arg RCC_PERIPHCLK_USART10 : USART10 peripheral clock + * @arg RCC_PERIPHCLK_XSPI1 : XSPI1 peripheral clock + * @arg RCC_PERIPHCLK_XSPI2 : XSPI2 peripheral clock + * @arg RCC_PERIPHCLK_XSPI3 : XSPI3 peripheral clock + * @retval Frequency in Hz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) +{ + uint32_t frequency = 0; /* Set to 0 for returned value if no source clock */ + + switch (PeriphClk) + { + case RCC_PERIPHCLK_ADC: + frequency = RCCEx_GetADCCLKFreq(LL_RCC_ADC_CLKSOURCE); + break; + + case RCC_PERIPHCLK_ADF1: + frequency = RCCEx_GetADFCLKFreq(LL_RCC_ADF1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_CSI: + frequency = RCCEx_GetCSICLKFreq(); + break; + + case RCC_PERIPHCLK_CKPER: + frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case RCC_PERIPHCLK_DCMIPP: + frequency = RCCEx_GetDCMIPPCLKFreq(LL_RCC_DCMIPP_CLKSOURCE); + break; + + case RCC_PERIPHCLK_ETH1: + frequency = RCCEx_GetETH1CLKFreq(LL_RCC_ETH1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_ETH1PTP: + frequency = RCCEx_GetETH1PTPCLKFreq(LL_RCC_ETH1PTP_CLKSOURCE); + break; + + case RCC_PERIPHCLK_FDCAN: + frequency = RCCEx_GetFDCANCLKFreq(LL_RCC_FDCAN_CLKSOURCE); + break; + + case RCC_PERIPHCLK_FMC: + frequency = RCCEx_GetFMCCLKFreq(LL_RCC_FMC_CLKSOURCE); + break; + + case RCC_PERIPHCLK_I2C1: + frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_I2C2: + frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_I2C3: + frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C3_CLKSOURCE); + break; + + case RCC_PERIPHCLK_I2C4: + frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C4_CLKSOURCE); + break; + + case RCC_PERIPHCLK_I3C1: + frequency = RCCEx_GetI3CCLKFreq(LL_RCC_I3C1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_I3C2: + frequency = RCCEx_GetI3CCLKFreq(LL_RCC_I3C2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_LPTIM1: + frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_LPTIM2: + frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_LPTIM3: + frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM3_CLKSOURCE); + break; + + case RCC_PERIPHCLK_LPTIM4: + frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM4_CLKSOURCE); + break; + + case RCC_PERIPHCLK_LPTIM5: + frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM5_CLKSOURCE); + break; + + case RCC_PERIPHCLK_LPUART1: + frequency = RCCEx_GetLPUARTCLKFreq(LL_RCC_LPUART1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_LTDC: + frequency = RCCEx_GetLTDCCLKFreq(LL_RCC_LTDC_CLKSOURCE); + break; + + case RCC_PERIPHCLK_MDF1: + frequency = RCCEx_GetMDFCLKFreq(LL_RCC_MDF1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_PSSI: + frequency = RCCEx_GetPSSICLKFreq(LL_RCC_PSSI_CLKSOURCE); + break; + + case RCC_PERIPHCLK_RTC: + frequency = RCCEx_GetRTCCLKFreq(); + break; + + case RCC_PERIPHCLK_SAI1: + frequency = RCCEx_GetSAICLKFreq(LL_RCC_SAI1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SAI2: + frequency = RCCEx_GetSAICLKFreq(LL_RCC_SAI2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SDMMC1: + frequency = RCCEx_GetSDMMCCLKFreq(LL_RCC_SDMMC1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SDMMC2: + frequency = RCCEx_GetSDMMCCLKFreq(LL_RCC_SDMMC2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SPDIFRX1: + frequency = RCCEx_GetSPDIFRXCLKFreq(LL_RCC_SPDIFRX1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SPI1: + frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SPI2: + frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SPI3: + frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI3_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SPI4: + frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI4_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SPI5: + frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI5_CLKSOURCE); + break; + + case RCC_PERIPHCLK_SPI6: + frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI6_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USART1: + frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USART2: + frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USART3: + frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART3_CLKSOURCE); + break; + + case RCC_PERIPHCLK_UART4: + frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART4_CLKSOURCE); + break; + + case RCC_PERIPHCLK_UART5: + frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART5_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USART6: + frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART6_CLKSOURCE); + break; + + case RCC_PERIPHCLK_UART7: + frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART7_CLKSOURCE); + break; + + case RCC_PERIPHCLK_UART8: + frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART8_CLKSOURCE); + break; + + case RCC_PERIPHCLK_UART9: + frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART9_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USART10: + frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART10_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USBPHY1: + frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USBOTGHS1: + frequency = RCCEx_GetOTGPHYCKREFCLKFreq(LL_RCC_OTGPHY1CKREF_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USBPHY2: + frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_USBOTGHS2: + frequency = RCCEx_GetOTGPHYCKREFCLKFreq(LL_RCC_OTGPHY2CKREF_CLKSOURCE); + break; + + case RCC_PERIPHCLK_XSPI1: + frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI1_CLKSOURCE); + break; + + case RCC_PERIPHCLK_XSPI2: + frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI2_CLKSOURCE); + break; + + case RCC_PERIPHCLK_XSPI3: + frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI3_CLKSOURCE); + break; + + default: + /* Unexpected case, frequency is by default set to 0 */ + break; + } + + return frequency; +} + +/** + * @brief Return PLL1 clock frequency + * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval PLL1 output clock frequency + */ +uint32_t HAL_RCCEx_GetPLL1CLKFreq(void) +{ + uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO; + uint32_t divm; + + /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP1 / PLLP2 + */ + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1P_IsEnabled() != 0U) + { + uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL1_GetSource()); + + if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) + { + divm = LL_RCC_PLL1_GetM(); + + if (divm != 0U) + { + plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetFRACN(), \ + LL_RCC_PLL1_GetP1(), LL_RCC_PLL1_GetP2()); + } + } + } + } + else if (LL_RCC_PLL1_IsEnabledBypass() != 0U) + { + plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL1_GetSource()); + } + else + { + /* Nothing to do */ + } + + return plloutputfreq; +} + +/** + * @brief Return PLL2 clock frequency + * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval PLL2 output clock frequency + */ +uint32_t HAL_RCCEx_GetPLL2CLKFreq(void) +{ + uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO; + uint32_t divm; + + /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP1 / PLLP2 + */ + if (LL_RCC_PLL2_IsReady() != 0U) + { + if (LL_RCC_PLL2P_IsEnabled() != 0U) + { + uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL2_GetSource()); + + if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) + { + + divm = LL_RCC_PLL2_GetM(); + + if (divm != 0U) + { + plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetFRACN(), \ + LL_RCC_PLL2_GetP1(), LL_RCC_PLL2_GetP2()); + } + } + } + } + else if (LL_RCC_PLL2_IsEnabledBypass() != 0U) + { + plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL2_GetSource()); + } + else + { + /* Nothing to do */ + } + + return plloutputfreq; +} + +/** + * @brief Return PLL3 clock frequency + * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval PLL3 output clock frequency + */ +uint32_t HAL_RCCEx_GetPLL3CLKFreq(void) +{ + uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO; + uint32_t divm; + + /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP1 / PLLP2 + */ + if (LL_RCC_PLL3_IsReady() != 0U) + { + if (LL_RCC_PLL3P_IsEnabled() != 0U) + { + uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL3_GetSource()); + + if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) + { + divm = LL_RCC_PLL3_GetM(); + + if (divm != 0U) + { + plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetFRACN(), \ + LL_RCC_PLL3_GetP1(), LL_RCC_PLL3_GetP2()); + } + } + } + } + else if (LL_RCC_PLL3_IsEnabledBypass() != 0U) + { + plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL3_GetSource()); + } + else + { + /* Nothing to do */ + } + + return plloutputfreq; +} + +/** + * @brief Return PLL4 clock frequency + * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval PLL4 output clock frequency + */ +uint32_t HAL_RCCEx_GetPLL4CLKFreq(void) +{ + uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO; + uint32_t divm; + + /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP1 / PLLP2 + */ + if (LL_RCC_PLL4_IsReady() != 0U) + { + if (LL_RCC_PLL4P_IsEnabled() != 0U) + { + uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL4_GetSource()); + + if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) + { + + divm = LL_RCC_PLL4_GetM(); + + if (divm != 0U) + { + plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL4_GetN(), LL_RCC_PLL4_GetFRACN(), \ + LL_RCC_PLL4_GetP1(), LL_RCC_PLL4_GetP2()); + } + } + } + } + else if (LL_RCC_PLL4_IsEnabledBypass() != 0U) + { + plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL4_GetSource()); + } + else + { + /* Nothing to do */ + } + + return plloutputfreq; +} + +/** + * @brief Return the Timer group frequency. + * @retval Timer group frequency in Hz + */ +uint32_t HAL_RCCEx_GetTIMGFreq(void) +{ + return LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions + * @brief Extended Peripheral Control functions + * @{ + */ +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock + * @param WakeUpClk Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI oscillator selection + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled and the system clock is HSE or a switch on HSE is requested. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Enable the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @note Backup domain access should be enabled + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + LL_RCC_LSE_EnableCSS(); +} + +/** + * @brief Disable the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @note Backup domain access should be enabled + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + /* Disable LSE CSS IT if any */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); + + LL_RCC_LSE_DisableCSS(); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 65 which must be + * enabled at application level to wake up from low power modes + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + LL_RCC_LSE_EnableCSS(); +} + +/** + * @brief Disable the LSE Clock Security System Interrupt. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS_IT(void) +{ + /* Disable LSE CSS IT */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); + + LL_RCC_LSE_DisableCSS(); +} + +/** + * @brief Rearm the LSE Clock Security System + * @note Allow to re-arm the LSE Clock Security System after a LSE failure detection + * @retval None + */ +void HAL_RCCEx_ReArmLSECSS(void) +{ + LL_RCC_LSE_ReArmCSS(); +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + +/** + * @brief Configure the requested PLL to SSCG Mode + * @param PLLnumber PLL number to configure. + * This parameter can be one of the following values: + * @ref RCC_PLL_Selection + * @param pPLLInit Pointer to an RCC_PLLInitTypeDef structure that + * contains the configuration parameters. + * @param pPLLSSCGInit Pointer to an RCC_PLLSSCGInitTypeDef structure that + * contains the configuration parameters specific to SSCG. + * @note PLL is temporary disabled to apply new parameters + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PLLSSCGConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit, + const RCC_PLLSSCGInitTypeDef *pPLLSSCGInit) +{ + __IO uint32_t *p_rcc_pll_cfgr1_reg; + __IO uint32_t *p_rcc_pll_cfgr2_reg; + __IO uint32_t *p_rcc_pll_cfgr3_reg; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t tickstart; + + p_rcc_pll_cfgr1_reg = &(RCC->PLL1CFGR1) + (((uint32_t)0x4) * PLLnumber); + p_rcc_pll_cfgr2_reg = &(RCC->PLL1CFGR2) + (((uint32_t)0x4) * PLLnumber); + p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber); + + if (pPLLInit->PLLState == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource)); + assert_param(IS_RCC_PLLFRACN_VALUE(pPLLInit->PLLFractional)); + assert_param(IS_RCC_PLLM_VALUE(pPLLInit->PLLM)); + assert_param(IS_RCC_PLLN_VALUE(pPLLInit->PLLN)); + assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP1)); + assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2)); + assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2)); + + /* Ensure PLLx is disabled */ + WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is disabled */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber)) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Ensure PLLxMODSSDIS='1' */ + SET_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS); + + /* Clear bypass mode */ + CLEAR_BIT(*p_rcc_pll_cfgr1_reg, RCC_PLL1CFGR1_PLL1BYP); + + /* Configure the PLLx clock source, multiplication and division factors. */ + MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \ + (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \ + | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos))); + MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \ + ((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos))); + + /* Configure PLLx DIVNFRAC */ + MODIFY_REG(*p_rcc_pll_cfgr2_reg, RCC_PLL1CFGR2_PLL1DIVNFRAC, \ + pPLLInit->PLLFractional << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos); + + /* Configure PLLx SSCG Parameters */ + MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDIV | RCC_PLL1CFGR3_PLL1MODSPR | RCC_PLL1CFGR3_PLL1MODSPR), \ + ((pPLLSSCGInit->PLLModDiv << RCC_PLL1CFGR3_PLL1MODDIV_Pos) \ + | (pPLLSSCGInit->PLLModSpreadDepth << RCC_PLL1CFGR3_PLL1MODSPR_Pos) + | (pPLLSSCGInit->PLLModSpreadMode << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos))); + + /* Clear PLLxMODSSDIS, PLLxMODDSEN and DACEN to 0 */ + CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS | RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN); + + /* Ensure PLLxMODSSRST='1' and Enable PLLx post divider output */ + SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODSSRST | RCC_PLL1CFGR3_PLL1PDIVEN)); + + /* Set PLLxMODDSEN and DACEN */ + SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN)); + + /* Enable the PLLx */ + WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS << PLLnumber); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is ready */ + while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* When PLL is Ready, deassert the PLLxMODSSRST */ + CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSRST); + } + else if (pPLLInit->PLLState == RCC_PLL_BYPASS) + { + ret = HAL_ERROR; + } + else + { + /* other states are not managed this function */ + } + + return ret; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCCEx_Private_Functions RCCEx Private Functions + * @{ + */ + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +static uint32_t RCCEx_GetHCLKFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +static uint32_t RCCEx_GetPCLK1Freq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return PCLK2 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK2 clock frequency (in Hz) + */ +static uint32_t RCCEx_GetPCLK2Freq(uint32_t HCLK_Frequency) +{ + /* PCLK2 clock frequency */ + return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); +} + +/** + * @brief Return PCLK4 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK4 clock frequency (in Hz) + */ +static uint32_t RCCEx_GetPCLK4Freq(uint32_t HCLK_Frequency) +{ + /* PCLK4 clock frequency */ + return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler()); +} + +/** + * @brief Return PCLK5 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK5 clock frequency (in Hz) + */ +static uint32_t RCCEx_GetPCLK5Freq(uint32_t HCLK_Frequency) +{ + /* PCLK5 clock frequency */ + return LL_RCC_CALC_PCLK5_FREQ(HCLK_Frequency, LL_RCC_GetAPB5Prescaler()); +} + +/** + * @brief Return PLL source clock frequency + * @param PLLsource PLL source clock + * @retval PLL source clock frequency (in Hz) + */ +static uint32_t RCCEx_GetPLLSourceFreq(uint32_t PLLsource) +{ + uint32_t pllinputfreq = RCC_PERIPH_FREQUENCY_NO; + + switch (PLLsource) + { + case LL_RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_PLLSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + if (LL_RCC_MSI_GetFrequency() == LL_RCC_MSI_FREQ_4MHZ) + { + pllinputfreq = MSI_VALUE; + } + else + { + pllinputfreq = 16000000UL; + } + } + break; + + case LL_RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_I2S_CKIN: + pllinputfreq = EXTERNAL_CLOCK_VALUE; + break; + + default: + /* unexpected case */ + break; + } + + return pllinputfreq; +} + +/** + * @brief Calculate the PLL frequency output when used in integer or fractional mode + * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/MSI) + * @param M Between 1 and 63 + * @param N Between 16 and 640 in integer mode, 20 to 320 in fractional mode + * @param FRACN 0 in integer mode, between 0 and 0xFFFFFF in fractional mode + * @param P1 VCO output divider P1 between 1 and 7 + * @param P2 VCO output divider P2 between 1 and 7 + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCCEx_CalcPLLFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1, + uint32_t P2) +{ + float_t freq; + + freq = ((float_t)PLLInputFreq * ((float_t)N + ((float_t)FRACN / (float_t)0x1000000))) / (float_t)M; + + freq = freq / (float_t)P1; + freq = freq / (float_t)P2; + + return (uint32_t)freq; +} + +/** + * @brief Return ADC clock frequency + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref RCCEx_ADC_Clock_Source + * @retval ADC clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetADCCLKFreq(uint32_t ADCxSource) +{ + uint32_t adc_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetADCClockSource(ADCxSource)) + { + case LL_RCC_ADC_CLKSOURCE_HCLK: + adc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_ADC_CLKSOURCE_CLKP: + adc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_ADC_CLKSOURCE_IC7: + if (LL_RCC_IC7_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC7_GetDivider(); + switch (LL_RCC_IC7_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + adc_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + adc_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + adc_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + adc_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_ADC_CLKSOURCE_IC8: + if (LL_RCC_IC8_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC8_GetDivider(); + switch (LL_RCC_IC8_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + adc_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + adc_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + adc_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + adc_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + adc_frequency = adc_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_ADC_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + adc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_ADC_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + adc_frequency = MSI_VALUE; + } + break; + + case LL_RCC_ADC_CLKSOURCE_I2S_CKIN: + adc_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_ADC_CLKSOURCE_TIMG: + adc_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); + break; + + default: + /* Unexpected case */ + break; + } + + return (adc_frequency / __HAL_RCC_GET_ADC_DIVIDER()); +} + +/** + * @brief Return ADFx clock frequency + * @param ADFxSource This parameter can be one of the following values: + * @arg @ref RCCEx_ADF1_Clock_Source + * @retval ADF clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetADFCLKFreq(uint32_t ADFxSource) +{ + uint32_t adf_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetADFClockSource(ADFxSource)) + { + case LL_RCC_ADF1_CLKSOURCE_HCLK: + adf_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_ADF1_CLKSOURCE_CLKP: + adf_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_ADF1_CLKSOURCE_IC7: + if (LL_RCC_IC7_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC7_GetDivider(); + switch (LL_RCC_IC7_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + adf_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + adf_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + adf_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + adf_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_ADF1_CLKSOURCE_IC8: + if (LL_RCC_IC8_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC8_GetDivider(); + switch (LL_RCC_IC8_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + adf_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + adf_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + adf_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + adf_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_ADF1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_ADF1_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + adf_frequency = MSI_VALUE; + } + break; + + case LL_RCC_ADF1_CLKSOURCE_I2S_CKIN: + adf_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_ADF1_CLKSOURCE_TIMG: + adf_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); + break; + + default: + /* Unexpected case */ + break; + } + + return adf_frequency; +} + +/** + * @brief Return CLKP clock frequency + * @param CLKPxSource This parameter can be one of the following values: + * @arg @ref RCCEx_CLKP_Clock_Source + * @retval CLKP clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetCLKPCLKFreq(uint32_t CLKPxSource) +{ + uint32_t clkp_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + if (LL_RCC_CLKP_IsEnabled() == 1U) + { + switch (LL_RCC_GetCLKPClockSource(CLKPxSource)) + { + case LL_RCC_CLKP_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_CLKP_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + clkp_frequency = MSI_VALUE; + } + break; + + case LL_RCC_CLKP_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + clkp_frequency = HSE_VALUE; + } + break; + + case LL_RCC_CLKP_CLKSOURCE_IC5: + if (LL_RCC_IC5_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC5_GetDivider(); + switch (LL_RCC_IC5_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_CLKP_CLKSOURCE_IC10: + if (LL_RCC_IC10_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC10_GetDivider(); + switch (LL_RCC_IC10_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_CLKP_CLKSOURCE_IC15: + if (LL_RCC_IC15_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC15_GetDivider(); + switch (LL_RCC_IC15_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_CLKP_CLKSOURCE_IC19: + if (LL_RCC_IC19_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC19_GetDivider(); + switch (LL_RCC_IC19_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_CLKP_CLKSOURCE_IC20: + if (LL_RCC_IC20_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC20_GetDivider(); + switch (LL_RCC_IC20_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + default: + /* Unexpected case */ + break; + } + } + + return clkp_frequency; +} + +/** + * @brief Return CSI clock frequency + * @retval CLKP clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetCSICLKFreq(void) +{ + uint32_t clkp_frequency = RCC_PERIPH_FREQUENCY_NO; + + if (LL_RCC_IC18_IsEnabled() != 0U) + { + uint32_t ic_divider = LL_RCC_IC18_GetDivider(); + switch (LL_RCC_IC18_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + clkp_frequency = clkp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + + return clkp_frequency; +} + +/** + * @brief Return DCMIPP clock frequency + * @param DCMIPPxSource This parameter can be one of the following values: + * @arg @ref RCCEx_DCMIPP_Clock_Source + * @retval DCMIPP clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetDCMIPPCLKFreq(uint32_t DCMIPPxSource) +{ + uint32_t dcmipp_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetDCMIPPClockSource(DCMIPPxSource)) + { + case LL_RCC_DCMIPP_CLKSOURCE_PCLK5: + dcmipp_frequency = RCCEx_GetPCLK5Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_DCMIPP_CLKSOURCE_CLKP: + dcmipp_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_DCMIPP_CLKSOURCE_IC17: + if (LL_RCC_IC17_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC17_GetDivider(); + switch (LL_RCC_IC17_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + dcmipp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + dcmipp_frequency = dcmipp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + dcmipp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + dcmipp_frequency = dcmipp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + dcmipp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + dcmipp_frequency = dcmipp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + dcmipp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + dcmipp_frequency = dcmipp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_DCMIPP_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + dcmipp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + default: + /* Unexpected case */ + break; + } + + return dcmipp_frequency; +} + +/** + * @brief Return ETH1 clock frequency + * @param ETH1xSource This parameter can be one of the following values: + * @arg @ref RCCEx_ETH1_Clock_Source + * @retval ETH1 clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetETH1CLKFreq(uint32_t ETH1xSource) +{ + uint32_t eth1_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetETHClockSource(ETH1xSource)) + { + case LL_RCC_ETH1_CLKSOURCE_HCLK: + eth1_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_ETH1_CLKSOURCE_CLKP: + eth1_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_ETH1_CLKSOURCE_IC12: + if (LL_RCC_IC12_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC12_GetDivider(); + switch (LL_RCC_IC12_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + eth1_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + eth1_frequency = eth1_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + eth1_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + eth1_frequency = eth1_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + eth1_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + eth1_frequency = eth1_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + eth1_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + eth1_frequency = eth1_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_ETH1_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + eth1_frequency = HSE_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return eth1_frequency; +} + +/** + * @brief Return ETH1PTP clock frequency + * @param ETH1PTPxSource This parameter can be one of the following values: + * @arg @ref RCCEx_ETH1_PTP_Clock_Source + * @retval ETH1PTP clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetETH1PTPCLKFreq(uint32_t ETH1PTPxSource) +{ + uint32_t eth1ptp_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetETHPTPClockSource(ETH1PTPxSource)) + { + case LL_RCC_ETH1PTP_CLKSOURCE_HCLK: + eth1ptp_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_ETH1PTP_CLKSOURCE_CLKP: + eth1ptp_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_ETH1PTP_CLKSOURCE_IC13: + if (LL_RCC_IC13_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC13_GetDivider(); + switch (LL_RCC_IC13_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + eth1ptp_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + eth1ptp_frequency = eth1ptp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + eth1ptp_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + eth1ptp_frequency = eth1ptp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + eth1ptp_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + eth1ptp_frequency = eth1ptp_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + eth1ptp_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + eth1ptp_frequency = eth1ptp_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_ETH1PTP_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + eth1ptp_frequency = HSE_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return (eth1ptp_frequency / __HAL_RCC_GET_ETH1PTP_DIVIDER()); +} + +/** + * @brief Return FDCAN clock frequency + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref RCCEx_FDCAN_Clock_Source + * @retval FDCAN clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetFDCANCLKFreq(uint32_t FDCANxSource) +{ + uint32_t fdcan_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetFDCANClockSource(FDCANxSource)) + { + case LL_RCC_FDCAN_CLKSOURCE_PCLK1: + fdcan_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_FDCAN_CLKSOURCE_CLKP: + fdcan_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_FDCAN_CLKSOURCE_IC19: + if (LL_RCC_IC19_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC19_GetDivider(); + switch (LL_RCC_IC19_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + fdcan_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + fdcan_frequency = fdcan_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + fdcan_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + fdcan_frequency = fdcan_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + fdcan_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + fdcan_frequency = fdcan_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + fdcan_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + fdcan_frequency = fdcan_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + fdcan_frequency = HSE_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return fdcan_frequency; +} + +/** + * @brief Return FMC clock frequency + * @param FMCxSource This parameter can be one of the following values: + * @arg @ref RCCEx_FMC_Clock_Source + * @retval FMC clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetFMCCLKFreq(uint32_t FMCxSource) +{ + uint32_t fmc_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetFMCClockSource(FMCxSource)) + { + case LL_RCC_FMC_CLKSOURCE_HCLK: + fmc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_FMC_CLKSOURCE_CLKP: + fmc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_FMC_CLKSOURCE_IC3: + if (LL_RCC_IC3_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC3_GetDivider(); + switch (LL_RCC_IC3_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + fmc_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + fmc_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + fmc_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + fmc_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_FMC_CLKSOURCE_IC4: + if (LL_RCC_IC4_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC4_GetDivider(); + switch (LL_RCC_IC4_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + fmc_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + fmc_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + fmc_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + fmc_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + fmc_frequency = fmc_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + default: + /* Unexpected case */ + break; + } + + return fmc_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref RCCEx_I2C1_Clock_Source + * @arg @ref RCCEx_I2C2_Clock_Source + * @arg @ref RCCEx_I2C3_Clock_Source + * @arg @ref RCCEx_I2C4_Clock_Source + * @retval I2C clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetI2CCLKFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_PCLK1: + case LL_RCC_I2C2_CLKSOURCE_PCLK1: + case LL_RCC_I2C3_CLKSOURCE_PCLK1: + case LL_RCC_I2C4_CLKSOURCE_PCLK1: + i2c_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_I2C1_CLKSOURCE_CLKP: + case LL_RCC_I2C2_CLKSOURCE_CLKP: + case LL_RCC_I2C3_CLKSOURCE_CLKP: + case LL_RCC_I2C4_CLKSOURCE_CLKP: + i2c_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_I2C1_CLKSOURCE_IC10: + case LL_RCC_I2C2_CLKSOURCE_IC10: + case LL_RCC_I2C3_CLKSOURCE_IC10: + case LL_RCC_I2C4_CLKSOURCE_IC10: + if (LL_RCC_IC10_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC10_GetDivider(); + switch (LL_RCC_IC10_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + i2c_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + i2c_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + i2c_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + i2c_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_I2C1_CLKSOURCE_IC15: + case LL_RCC_I2C2_CLKSOURCE_IC15: + case LL_RCC_I2C3_CLKSOURCE_IC15: + case LL_RCC_I2C4_CLKSOURCE_IC15: + if (LL_RCC_IC15_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC15_GetDivider(); + switch (LL_RCC_IC15_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + i2c_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + i2c_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + i2c_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + i2c_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + i2c_frequency = i2c_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: + case LL_RCC_I2C2_CLKSOURCE_HSI: + case LL_RCC_I2C3_CLKSOURCE_HSI: + case LL_RCC_I2C4_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_I2C1_CLKSOURCE_MSI: + case LL_RCC_I2C2_CLKSOURCE_MSI: + case LL_RCC_I2C3_CLKSOURCE_MSI: + case LL_RCC_I2C4_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + i2c_frequency = MSI_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return i2c_frequency; +} + +/** + * @brief Return I3Cx clock frequency + * @param I3CxSource This parameter can be one of the following values: + * @arg @ref RCCEx_I3C1_Clock_Source + * @arg @ref RCCEx_I3C2_Clock_Source + * @retval I3C clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetI3CCLKFreq(uint32_t I3CxSource) +{ + uint32_t i3c_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetI3CClockSource(I3CxSource)) + { + case LL_RCC_I3C1_CLKSOURCE_PCLK1: + case LL_RCC_I3C2_CLKSOURCE_PCLK1: + i3c_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_I3C1_CLKSOURCE_CLKP: + case LL_RCC_I3C2_CLKSOURCE_CLKP: + i3c_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_I3C1_CLKSOURCE_IC10: + case LL_RCC_I3C2_CLKSOURCE_IC10: + if (LL_RCC_IC10_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC10_GetDivider(); + switch (LL_RCC_IC10_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + i3c_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + i3c_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + i3c_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + i3c_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_I3C1_CLKSOURCE_IC15: + case LL_RCC_I3C2_CLKSOURCE_IC15: + if (LL_RCC_IC15_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC15_GetDivider(); + switch (LL_RCC_IC15_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + i3c_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + i3c_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + i3c_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + i3c_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + i3c_frequency = i3c_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_I3C1_CLKSOURCE_HSI: + case LL_RCC_I3C2_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + i3c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_I3C1_CLKSOURCE_MSI: + case LL_RCC_I3C2_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + i3c_frequency = MSI_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return i3c_frequency; +} + +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref RCCEx_LPTIM1_Clock_Source + * @arg @ref RCCEx_LPTIM2_Clock_Source + * @arg @ref RCCEx_LPTIM3_Clock_Source + * @arg @ref RCCEx_LPTIM4_Clock_Source + * @arg @ref RCCEx_LPTIM5_Clock_Source + * @retval LPTIM clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: + lptim_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_LPTIM2_CLKSOURCE_PCLK4: + case LL_RCC_LPTIM3_CLKSOURCE_PCLK4: + case LL_RCC_LPTIM4_CLKSOURCE_PCLK4: + case LL_RCC_LPTIM5_CLKSOURCE_PCLK4: + lptim_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_LPTIM1_CLKSOURCE_CLKP: + case LL_RCC_LPTIM2_CLKSOURCE_CLKP: + case LL_RCC_LPTIM3_CLKSOURCE_CLKP: + case LL_RCC_LPTIM4_CLKSOURCE_CLKP: + case LL_RCC_LPTIM5_CLKSOURCE_CLKP: + lptim_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_LPTIM1_CLKSOURCE_IC15: + case LL_RCC_LPTIM2_CLKSOURCE_IC15: + case LL_RCC_LPTIM3_CLKSOURCE_IC15: + case LL_RCC_LPTIM4_CLKSOURCE_IC15: + case LL_RCC_LPTIM5_CLKSOURCE_IC15: + if (LL_RCC_IC15_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC15_GetDivider(); + switch (LL_RCC_IC15_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + lptim_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + lptim_frequency = lptim_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + lptim_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + lptim_frequency = lptim_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + lptim_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + lptim_frequency = lptim_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + lptim_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + lptim_frequency = lptim_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: + case LL_RCC_LPTIM2_CLKSOURCE_LSE: + case LL_RCC_LPTIM3_CLKSOURCE_LSE: + case LL_RCC_LPTIM4_CLKSOURCE_LSE: + case LL_RCC_LPTIM5_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSI: + case LL_RCC_LPTIM2_CLKSOURCE_LSI: + case LL_RCC_LPTIM3_CLKSOURCE_LSI: + case LL_RCC_LPTIM4_CLKSOURCE_LSI: + case LL_RCC_LPTIM5_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_TIMG: + case LL_RCC_LPTIM2_CLKSOURCE_TIMG: + case LL_RCC_LPTIM3_CLKSOURCE_TIMG: + case LL_RCC_LPTIM4_CLKSOURCE_TIMG: + case LL_RCC_LPTIM5_CLKSOURCE_TIMG: + lptim_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); + break; + + default: + /* Unexpected case */ + break; + } + + return lptim_frequency; +} + +/** + * @brief Return LPUART clock frequency + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref RCCEx_LPUART1_Clock_Source + * @retval LPUART clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetLPUARTCLKFreq(uint32_t LPUARTxSource) +{ + uint32_t lpuart_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART1_CLKSOURCE_PCLK4: + lpuart_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_LPUART1_CLKSOURCE_CLKP: + lpuart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_LPUART1_CLKSOURCE_IC9: + if (LL_RCC_IC9_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC9_GetDivider(); + switch (LL_RCC_IC9_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + lpuart_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + lpuart_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + lpuart_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + lpuart_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_IC14: + if (LL_RCC_IC14_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC14_GetDivider(); + switch (LL_RCC_IC14_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + lpuart_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + lpuart_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + lpuart_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + lpuart_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + lpuart_frequency = lpuart_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + lpuart_frequency = MSI_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return lpuart_frequency; +} + +/** + * @brief Return LTDC clock frequency + * @param LTDCxSource This parameter can be one of the following values: + * @arg @ref RCCEx_LTDC_Clock_Source + * @retval LTDC clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetLTDCCLKFreq(uint32_t LTDCxSource) +{ + uint32_t ltdc_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetLTDCClockSource(LTDCxSource)) + { + case LL_RCC_LTDC_CLKSOURCE_PCLK5: + ltdc_frequency = RCCEx_GetPCLK5Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_LTDC_CLKSOURCE_CLKP: + ltdc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_LTDC_CLKSOURCE_IC16: + if (LL_RCC_IC16_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC16_GetDivider(); + switch (LL_RCC_IC16_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + ltdc_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + ltdc_frequency = ltdc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + ltdc_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + ltdc_frequency = ltdc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + ltdc_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + ltdc_frequency = ltdc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + ltdc_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + ltdc_frequency = ltdc_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_LTDC_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + ltdc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + default: + /* Unexpected case */ + break; + } + + return ltdc_frequency; +} + +/** + * @brief Return MDFx clock frequency + * @param MDFxSource This parameter can be one of the following values: + * @arg @ref RCCEx_MDF1_Clock_Source + * @retval MDF clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetMDFCLKFreq(uint32_t MDFxSource) +{ + uint32_t adf_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetMDFClockSource(MDFxSource)) + { + case LL_RCC_MDF1_CLKSOURCE_HCLK: + adf_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_MDF1_CLKSOURCE_CLKP: + adf_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_MDF1_CLKSOURCE_IC7: + if (LL_RCC_IC7_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC7_GetDivider(); + switch (LL_RCC_IC7_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + adf_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + adf_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + adf_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + adf_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_MDF1_CLKSOURCE_IC8: + if (LL_RCC_IC8_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC8_GetDivider(); + switch (LL_RCC_IC8_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + adf_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + adf_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + adf_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + adf_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + adf_frequency = adf_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_MDF1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_MDF1_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + adf_frequency = MSI_VALUE; + } + break; + + case LL_RCC_MDF1_CLKSOURCE_I2S_CKIN: + adf_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_MDF1_CLKSOURCE_TIMG: + adf_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); + break; + + default: + /* Unexpected case */ + break; + } + + return adf_frequency; +} + +/** + * @brief Return PSSI clock frequency + * @param PSSIxSource This parameter can be one of the following values: + * @arg @ref RCCEx_PSSI_Clock_Source + * @retval PSSI clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetPSSICLKFreq(uint32_t PSSIxSource) +{ + uint32_t pssi_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetPSSIClockSource(PSSIxSource)) + { + case LL_RCC_PSSI_CLKSOURCE_HCLK: + pssi_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_PSSI_CLKSOURCE_CLKP: + pssi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_PSSI_CLKSOURCE_IC20: + if (LL_RCC_IC20_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC20_GetDivider(); + switch (LL_RCC_IC20_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + pssi_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + pssi_frequency = pssi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + pssi_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + pssi_frequency = pssi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + pssi_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + pssi_frequency = pssi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + pssi_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + pssi_frequency = pssi_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_PSSI_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pssi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + default: + /* Unexpected case */ + break; + } + + return pssi_frequency; +} + +/** + * @brief Return RTC clock frequency + * @retval RTC clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetRTCCLKFreq(void) +{ + uint32_t rtc_frequency = RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetRTCClockSource()) + { + case LL_RCC_RTC_CLKSOURCE_NONE: + /* Nothing to do */ + break; + + case LL_RCC_RTC_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + rtc_frequency = LSE_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + rtc_frequency = LSI_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + uint32_t prescaler = (READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE) >> RCC_CCIPR7_RTCPRE_Pos) + 1U; + rtc_frequency = HSE_VALUE / prescaler; + } + break; + + default: + /* Unexpected case */ + break; + } + + return rtc_frequency; +} + +/** + * @brief Return SAIx clock frequency + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref RCCEx_SAI1_Clock_Source + * @arg @ref RCCEx_SAI2_Clock_Source + * @retval SAI clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetSAICLKFreq(uint32_t SAIxSource) +{ + uint32_t sai_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetSAIClockSource(SAIxSource)) + { + case LL_RCC_SAI1_CLKSOURCE_PCLK2: + case LL_RCC_SAI2_CLKSOURCE_PCLK2: + sai_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_SAI1_CLKSOURCE_CLKP: + case LL_RCC_SAI2_CLKSOURCE_CLKP: + sai_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_SAI1_CLKSOURCE_IC7: + case LL_RCC_SAI2_CLKSOURCE_IC7: + if (LL_RCC_IC7_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC7_GetDivider(); + switch (LL_RCC_IC7_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + sai_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + sai_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + sai_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + sai_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SAI1_CLKSOURCE_IC8: + case LL_RCC_SAI2_CLKSOURCE_IC8: + if (LL_RCC_IC8_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC8_GetDivider(); + switch (LL_RCC_IC8_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + sai_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + sai_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + sai_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + sai_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + sai_frequency = sai_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SAI1_CLKSOURCE_HSI: + case LL_RCC_SAI2_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + sai_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_SAI1_CLKSOURCE_MSI: + case LL_RCC_SAI2_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + sai_frequency = MSI_VALUE; + } + break; + + case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN: + case LL_RCC_SAI2_CLKSOURCE_I2S_CKIN: + sai_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_SAI1_CLKSOURCE_SPDIFRX1: + case LL_RCC_SAI2_CLKSOURCE_SPDIFRX1: + sai_frequency = RCCEx_GetSPDIFRXCLKFreq(LL_RCC_SPDIFRX1_CLKSOURCE); + break; + + default: + /* Unexpected case */ + break; + } + + return sai_frequency; +} + +/** + * @brief Return SDMMC clock frequency + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref RCCEx_SDMMC1_Clock_Source + * @arg @ref RCCEx_SDMMC2_Clock_Source + * @retval SDMMC clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetSDMMCCLKFreq(uint32_t SDMMCxSource) +{ + uint32_t sdmmc_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) + { + case LL_RCC_SDMMC1_CLKSOURCE_HCLK: + case LL_RCC_SDMMC2_CLKSOURCE_HCLK: + sdmmc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_SDMMC1_CLKSOURCE_CLKP: + case LL_RCC_SDMMC2_CLKSOURCE_CLKP: + sdmmc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_SDMMC1_CLKSOURCE_IC4: + case LL_RCC_SDMMC2_CLKSOURCE_IC4: + if (LL_RCC_IC4_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC4_GetDivider(); + switch (LL_RCC_IC4_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + sdmmc_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + sdmmc_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + sdmmc_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + sdmmc_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SDMMC1_CLKSOURCE_IC5: + case LL_RCC_SDMMC2_CLKSOURCE_IC5: + if (LL_RCC_IC5_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC5_GetDivider(); + switch (LL_RCC_IC5_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + sdmmc_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + sdmmc_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + sdmmc_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + sdmmc_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + sdmmc_frequency = sdmmc_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + default: + /* Unexpected case */ + break; + } + + return sdmmc_frequency; +} + +/** + * @brief Return SPDIFRX clock frequency + * @param SPDIFRXxSource This parameter can be one of the following values: + * @arg @ref RCCEx_SPDIFRX1_Clock_Source + * @retval SPDIF clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetSPDIFRXCLKFreq(uint32_t SPDIFRXxSource) +{ + uint32_t spdifrx_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource)) + { + case LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1: + spdifrx_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_SPDIFRX1_CLKSOURCE_CLKP: + spdifrx_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_SPDIFRX1_CLKSOURCE_IC7: + if (LL_RCC_IC7_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC7_GetDivider(); + switch (LL_RCC_IC7_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + spdifrx_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + spdifrx_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + spdifrx_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + spdifrx_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SPDIFRX1_CLKSOURCE_IC8: + if (LL_RCC_IC8_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC8_GetDivider(); + switch (LL_RCC_IC8_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + spdifrx_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + spdifrx_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + spdifrx_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + spdifrx_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + spdifrx_frequency = spdifrx_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SPDIFRX1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + spdifrx_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_SPDIFRX1_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + spdifrx_frequency = MSI_VALUE; + } + break; + + case LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN: + spdifrx_frequency = EXTERNAL_CLOCK_VALUE; + break; + + default: + /* Unexpected case */ + break; + } + + return spdifrx_frequency; +} + +/** + * @brief Return SPIx clock frequency + * @param SPIxSource This parameter can be one of the following values: + * @arg @ref RCCEx_SPI1_Clock_Source + * @arg @ref RCCEx_SPI2_Clock_Source + * @arg @ref RCCEx_SPI3_Clock_Source + * @arg @ref RCCEx_SPI4_Clock_Source + * @arg @ref RCCEx_SPI5_Clock_Source + * @arg @ref RCCEx_SPI6_Clock_Source + * @retval SPI clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetSPICLKFreq(uint32_t SPIxSource) +{ + uint32_t spi_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetSPIClockSource(SPIxSource)) + { + case LL_RCC_SPI2_CLKSOURCE_PCLK1: + case LL_RCC_SPI3_CLKSOURCE_PCLK1: + spi_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_SPI1_CLKSOURCE_PCLK2: + case LL_RCC_SPI4_CLKSOURCE_PCLK2: + case LL_RCC_SPI5_CLKSOURCE_PCLK2: + spi_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_SPI6_CLKSOURCE_PCLK4: + spi_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_SPI1_CLKSOURCE_CLKP: + case LL_RCC_SPI2_CLKSOURCE_CLKP: + case LL_RCC_SPI3_CLKSOURCE_CLKP: + case LL_RCC_SPI4_CLKSOURCE_CLKP: + case LL_RCC_SPI5_CLKSOURCE_CLKP: + case LL_RCC_SPI6_CLKSOURCE_CLKP: + spi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_SPI1_CLKSOURCE_IC8: + case LL_RCC_SPI2_CLKSOURCE_IC8: + case LL_RCC_SPI3_CLKSOURCE_IC8: + case LL_RCC_SPI6_CLKSOURCE_IC8: + if (LL_RCC_IC8_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC8_GetDivider(); + switch (LL_RCC_IC8_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + spi_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + spi_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + spi_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + spi_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SPI1_CLKSOURCE_IC9: + case LL_RCC_SPI2_CLKSOURCE_IC9: + case LL_RCC_SPI3_CLKSOURCE_IC9: + case LL_RCC_SPI4_CLKSOURCE_IC9: + case LL_RCC_SPI5_CLKSOURCE_IC9: + case LL_RCC_SPI6_CLKSOURCE_IC9: + if (LL_RCC_IC9_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC9_GetDivider(); + switch (LL_RCC_IC9_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + spi_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + spi_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + spi_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + spi_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SPI4_CLKSOURCE_IC14: + case LL_RCC_SPI5_CLKSOURCE_IC14: + if (LL_RCC_IC14_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC14_GetDivider(); + switch (LL_RCC_IC14_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + spi_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + spi_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + spi_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + spi_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + spi_frequency = spi_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_SPI1_CLKSOURCE_HSI: + case LL_RCC_SPI2_CLKSOURCE_HSI: + case LL_RCC_SPI3_CLKSOURCE_HSI: + case LL_RCC_SPI4_CLKSOURCE_HSI: + case LL_RCC_SPI5_CLKSOURCE_HSI: + case LL_RCC_SPI6_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_SPI1_CLKSOURCE_MSI: + case LL_RCC_SPI2_CLKSOURCE_MSI: + case LL_RCC_SPI3_CLKSOURCE_MSI: + case LL_RCC_SPI4_CLKSOURCE_MSI: + case LL_RCC_SPI5_CLKSOURCE_MSI: + case LL_RCC_SPI6_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + spi_frequency = MSI_VALUE; + } + break; + + case LL_RCC_SPI1_CLKSOURCE_I2S_CKIN: + case LL_RCC_SPI2_CLKSOURCE_I2S_CKIN: + case LL_RCC_SPI3_CLKSOURCE_I2S_CKIN: + case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN: + spi_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_SPI4_CLKSOURCE_HSE: + case LL_RCC_SPI5_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + spi_frequency = HSE_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return spi_frequency; +} + +/** + * @brief Return UARTx clock frequency + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref RCCEx_UART4_Clock_Source + * @arg @ref RCCEx_UART5_Clock_Source + * @arg @ref RCCEx_UART7_Clock_Source + * @arg @ref RCCEx_UART8_Clock_Source + * @arg @ref RCCEx_UART9_Clock_Source + * @retval USART clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetUARTCLKFreq(uint32_t UARTxSource) +{ + uint32_t uart_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetUARTClockSource(UARTxSource)) + { + case LL_RCC_UART4_CLKSOURCE_PCLK1: + case LL_RCC_UART5_CLKSOURCE_PCLK1: + case LL_RCC_UART7_CLKSOURCE_PCLK1: + case LL_RCC_UART8_CLKSOURCE_PCLK1: + uart_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_UART9_CLKSOURCE_PCLK2: + uart_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_UART4_CLKSOURCE_CLKP: + case LL_RCC_UART5_CLKSOURCE_CLKP: + case LL_RCC_UART7_CLKSOURCE_CLKP: + case LL_RCC_UART8_CLKSOURCE_CLKP: + case LL_RCC_UART9_CLKSOURCE_CLKP: + uart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_UART4_CLKSOURCE_IC9: + case LL_RCC_UART5_CLKSOURCE_IC9: + case LL_RCC_UART7_CLKSOURCE_IC9: + case LL_RCC_UART8_CLKSOURCE_IC9: + case LL_RCC_UART9_CLKSOURCE_IC9: + if (LL_RCC_IC9_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC9_GetDivider(); + switch (LL_RCC_IC9_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + uart_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + uart_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + uart_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + uart_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_UART4_CLKSOURCE_IC14: + case LL_RCC_UART5_CLKSOURCE_IC14: + case LL_RCC_UART7_CLKSOURCE_IC14: + case LL_RCC_UART8_CLKSOURCE_IC14: + case LL_RCC_UART9_CLKSOURCE_IC14: + if (LL_RCC_IC14_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC14_GetDivider(); + switch (LL_RCC_IC14_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + uart_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + uart_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + uart_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + uart_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + uart_frequency = uart_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_UART4_CLKSOURCE_HSI: + case LL_RCC_UART5_CLKSOURCE_HSI: + case LL_RCC_UART7_CLKSOURCE_HSI: + case LL_RCC_UART8_CLKSOURCE_HSI: + case LL_RCC_UART9_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + uart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_UART4_CLKSOURCE_MSI: + case LL_RCC_UART5_CLKSOURCE_MSI: + case LL_RCC_UART7_CLKSOURCE_MSI: + case LL_RCC_UART8_CLKSOURCE_MSI: + case LL_RCC_UART9_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + uart_frequency = MSI_VALUE; + } + break; + + case LL_RCC_UART4_CLKSOURCE_LSE: + case LL_RCC_UART5_CLKSOURCE_LSE: + case LL_RCC_UART7_CLKSOURCE_LSE: + case LL_RCC_UART8_CLKSOURCE_LSE: + case LL_RCC_UART9_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + uart_frequency = LSE_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return uart_frequency; +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref RCCEx_USART1_Clock_Source + * @arg @ref RCCEx_USART2_Clock_Source + * @arg @ref RCCEx_USART3_Clock_Source + * @arg @ref RCCEx_USART6_Clock_Source + * @arg @ref RCCEx_USART10_Clock_Source + * @retval USART clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +static uint32_t RCCEx_GetUSARTCLKFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_PCLK2: + case LL_RCC_USART6_CLKSOURCE_PCLK2: + case LL_RCC_USART10_CLKSOURCE_PCLK2: + usart_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: + case LL_RCC_USART3_CLKSOURCE_PCLK1: + usart_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq())); + break; + + case LL_RCC_USART1_CLKSOURCE_CLKP: + case LL_RCC_USART2_CLKSOURCE_CLKP: + case LL_RCC_USART3_CLKSOURCE_CLKP: + case LL_RCC_USART6_CLKSOURCE_CLKP: + case LL_RCC_USART10_CLKSOURCE_CLKP: + usart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_USART1_CLKSOURCE_IC9: + case LL_RCC_USART2_CLKSOURCE_IC9: + case LL_RCC_USART3_CLKSOURCE_IC9: + case LL_RCC_USART6_CLKSOURCE_IC9: + case LL_RCC_USART10_CLKSOURCE_IC9: + if (LL_RCC_IC9_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC9_GetDivider(); + switch (LL_RCC_IC9_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + usart_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + usart_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + usart_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + usart_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_USART1_CLKSOURCE_IC14: + case LL_RCC_USART2_CLKSOURCE_IC14: + case LL_RCC_USART3_CLKSOURCE_IC14: + case LL_RCC_USART6_CLKSOURCE_IC14: + case LL_RCC_USART10_CLKSOURCE_IC14: + if (LL_RCC_IC14_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC14_GetDivider(); + switch (LL_RCC_IC14_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + usart_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + usart_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + usart_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + usart_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + usart_frequency = usart_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: + case LL_RCC_USART2_CLKSOURCE_HSI: + case LL_RCC_USART3_CLKSOURCE_HSI: + case LL_RCC_USART6_CLKSOURCE_HSI: + case LL_RCC_USART10_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + } + break; + + case LL_RCC_USART1_CLKSOURCE_MSI: + case LL_RCC_USART2_CLKSOURCE_MSI: + case LL_RCC_USART3_CLKSOURCE_MSI: + case LL_RCC_USART6_CLKSOURCE_MSI: + case LL_RCC_USART10_CLKSOURCE_MSI: + if (LL_RCC_MSI_IsReady() != 0U) + { + usart_frequency = MSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: + case LL_RCC_USART2_CLKSOURCE_LSE: + case LL_RCC_USART3_CLKSOURCE_LSE: + case LL_RCC_USART6_CLKSOURCE_LSE: + case LL_RCC_USART10_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + usart_frequency = LSE_VALUE; + } + break; + + default: + /* Unexpected case */ + break; + } + + return usart_frequency; +} + +/** + * @brief Return OTGPHYx clock frequency + * @param OTGPHYxSource This parameter can be one of the following values: + * @arg @ref RCCEx_USB_OTGHS1_Clock_Source + * @arg @ref RCCEx_USB_OTGHS2_Clock_Source + * @retval OTGPHY clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled + */ +static uint32_t RCCEx_GetOTGPHYCLKFreq(uint32_t OTGPHYxSource) +{ + uint32_t usb_frequency = RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetUSBClockSource(OTGPHYxSource)) + { + case LL_RCC_OTGPHY1_CLKSOURCE_CLKP: + case LL_RCC_OTGPHY2_CLKSOURCE_CLKP: + usb_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2: + case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2: + if (LL_RCC_HSE_IsReady() != 0U) + { + usb_frequency = HSE_VALUE / 2U; + } + break; + case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC: + case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC: + if (LL_RCC_HSE_IsReady() != 0U) + { + if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL) + { + usb_frequency = HSE_VALUE; + } + else + { + usb_frequency = HSE_VALUE / 2U; + } + } + break; + case LL_RCC_OTGPHY1_CLKSOURCE_IC15: + case LL_RCC_OTGPHY2_CLKSOURCE_IC15: + if (LL_RCC_IC15_IsEnabled() != 0U) + { + uint32_t ic_divider = LL_RCC_IC15_GetDivider(); + switch (LL_RCC_IC15_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + usb_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + usb_frequency = usb_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + usb_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + usb_frequency = usb_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + usb_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + usb_frequency = usb_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + usb_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + usb_frequency = usb_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + default: + /* Unexpected case */ + break; + } + + return usb_frequency; +} + +/** + * @brief Return OTGPHYxCKREF clock frequency + * @param OTGPHYxCKREFSource This parameter can be one of the following values: + * @arg @ref RCCEx_USBPHY1_Clock_Source + * @arg @ref RCCEx_USBPHY2_Clock_Source + * @retval OTGPHYCKREF clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled + */ +static uint32_t RCCEx_GetOTGPHYCKREFCLKFreq(uint32_t OTGPHYxCKREFSource) +{ + uint32_t usb_frequency = RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetUSBClockSource(OTGPHYxCKREFSource)) + { + case LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC: + case LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC: + if (LL_RCC_HSE_IsReady() != 0U) + { + if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL) + { + usb_frequency = HSE_VALUE; + } + else + { + usb_frequency = HSE_VALUE / 2U; + } + } + break; + + case LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1: + usb_frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY1_CLKSOURCE); + break; + + case LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2: + usb_frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY2_CLKSOURCE); + break; + + default: + /* Unexpected case */ + break; + } + + return usb_frequency; +} + +/** + * @brief Return XSPI clock frequency + * @param XSPIxSource This parameter can be one of the following values: + * @arg @ref RCCEx_XSPI1_Clock_Source + * @arg @ref RCCEx_XSPI2_Clock_Source + * @arg @ref RCCEx_XSPI3_Clock_Source + * @retval XSPI clock frequency (in Hz) + * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ + +static uint32_t RCCEx_GetXSPICLKFreq(uint32_t XSPIxSource) +{ + uint32_t xspi_frequency = RCC_PERIPH_FREQUENCY_NO; + uint32_t ic_divider; + + switch (LL_RCC_GetXSPIClockSource(XSPIxSource)) + { + case LL_RCC_XSPI1_CLKSOURCE_HCLK: + case LL_RCC_XSPI2_CLKSOURCE_HCLK: + case LL_RCC_XSPI3_CLKSOURCE_HCLK: + xspi_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()); + break; + + case LL_RCC_XSPI1_CLKSOURCE_CLKP: + case LL_RCC_XSPI2_CLKSOURCE_CLKP: + case LL_RCC_XSPI3_CLKSOURCE_CLKP: + xspi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_XSPI1_CLKSOURCE_IC3: + case LL_RCC_XSPI2_CLKSOURCE_IC3: + case LL_RCC_XSPI3_CLKSOURCE_IC3: + if (LL_RCC_IC3_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC3_GetDivider(); + switch (LL_RCC_IC3_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + xspi_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + xspi_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + xspi_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + xspi_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + case LL_RCC_XSPI1_CLKSOURCE_IC4: + case LL_RCC_XSPI2_CLKSOURCE_IC4: + case LL_RCC_XSPI3_CLKSOURCE_IC4: + if (LL_RCC_IC4_IsEnabled() != 0U) + { + ic_divider = LL_RCC_IC4_GetDivider(); + switch (LL_RCC_IC4_GetSource()) + { + case LL_RCC_ICCLKSOURCE_PLL1: + xspi_frequency = HAL_RCCEx_GetPLL1CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + xspi_frequency = HAL_RCCEx_GetPLL2CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + xspi_frequency = HAL_RCCEx_GetPLL3CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + xspi_frequency = HAL_RCCEx_GetPLL4CLKFreq(); + xspi_frequency = xspi_frequency / ic_divider; + break; + default: + /* Unexpected case */ + break; + } + } + break; + + default: + /* Nothing to do */ + break; + } + + return xspi_frequency; +} + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c =================================================================== --- trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c (revision 16) @@ -0,0 +1,3598 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_xspi.c + * @author MCD Application Team + * @brief XSPI HAL module driver. + This file provides firmware functions to manage the following + functionalities of the XSPI interface (XSPI). + + Initialization and de-initialization functions + + Hyperbus configuration + + Indirect functional mode management + + Memory-mapped functional mode management + + Auto-polling functional mode management + + Interrupts and flags management + + DMA channel configuration for indirect functional mode + + Errors management and abort functionality + + IO manager configuration + + HIGH-SPEED INTERFACE configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + *** Initialization *** + ====================== + [..] + As prerequisite, fill in the HAL_XSPI_MspInit() : + (+) Enable XSPI clocks interface with __HAL_RCC_XSPI_CLK_ENABLE(). + (+) Reset XSPI Peripheral with __HAL_RCC_XSPI_FORCE_RESET() and __HAL_RCC_XSPI_RELEASE_RESET(). + (+) Enable the clocks for the XSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (+) Configure these XSPI pins in alternate mode using HAL_GPIO_Init(). + (+) If interrupt or DMA mode is used, enable and configure XSPI global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (+) If DMA mode is used, enable the clocks for the XSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with XSPI handle using __HAL_LINKDMA(), enable and configure + DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + [..] + Configure the fifo threshold, the memory mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay + and the CS boundary using the HAL_XSPI_Init() function. + [..] + When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode using the HAL_XSPI_HyperbusCfg() + function. + + *** Indirect functional mode *** + ================================ + [..] + In regular mode, configure the command sequence using the HAL_XSPI_Command() + or HAL_XSPI_Command_IT() functions : + (+) Instruction phase : the mode used and if present the size, the instruction + opcode and the DTR mode. + (+) Address phase : the mode used and if present the size, the address + value and the DTR mode. + (+) Alternate-bytes phase : the mode used and if present the size, the + alternate bytes values and the DTR mode. + (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (+) Data phase : the mode used and if present the number of bytes and the DTR mode. + (+) Data strobe (DQS) mode : the activation (or not) of this mode + (+) IO selection : to access external memory. + (+) Operation type : always common configuration. + [..] + In Hyperbus mode, configure the command sequence using the HAL_XSPI_HyperbusCmd() + function : + (+) Address space : indicate if the access will be done in register or memory + (+) Address size + (+) Number of data + (+) Data strobe (DQS) mode : the activation (or not) of this mode + [..] + If no data is required for the command (only for regular mode, not for + Hyperbus mode), it is sent directly to the memory : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_CmdCpltCallback() will be called when the transfer is complete. + [..] + For the indirect write mode, use HAL_XSPI_Transmit(), HAL_XSPI_Transmit_DMA() or + HAL_XSPI_Transmit_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_XSPI_TxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_XSPI_TxHalfCpltCallback() will be called at the half transfer and + HAL_XSPI_TxCpltCallback() will be called when the transfer is complete. + [..] + For the indirect read mode, use HAL_XSPI_Receive(), HAL_XSPI_Receive_DMA() or + HAL_XSPI_Receive_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_XSPI_RxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_XSPI_RxHalfCpltCallback() will be called at the half transfer and + HAL_XSPI_RxCpltCallback() will be called when the transfer is complete. + + *** Auto-polling functional mode *** + ==================================== + [..] + Configure the command sequence by the same way than the indirect mode + [..] + Configure the auto-polling functional mode using the HAL_XSPI_AutoPolling() + or HAL_XSPI_AutoPolling_IT() functions : + (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), + the polling interval and the automatic stop activation. + [..] + After the configuration : + (+) In polling mode, the output of the function is done when the status match is reached. The + automatic stop is activated to avoid an infinite loop. + (+) In interrupt mode, HAL_XSPI_StatusMatchCallback() will be called each time the status match is reached. + + *** Memory-mapped functional mode *** + ===================================== + [..] + Configure the command sequence by the same way than the indirect mode except + for the operation type in regular mode : + (+) Operation type equals to read configuration : the command configuration + applies to read access in memory-mapped mode + (+) Operation type equals to write configuration : the command configuration + applies to write access in memory-mapped mode + (+) Both read and write configuration should be performed before activating + memory-mapped mode + [..] + Configure the memory-mapped functional mode using the HAL_XSPI_MemoryMapped() + functions : + (+) The timeout activation and the timeout period. + [..] + After the configuration, the XSPI will be used as soon as an access on the AHB is done on + the address range. HAL_XSPI_TimeOutCallback() will be called when the timeout expires. + HAL_XSPI_IsMemoryMapped() can be used to verify whether memory-mapped mode is configured or not. + + *** Errors management and abort functionality *** + ================================================= + [..] + HAL_XSPI_GetError() function gives the error raised during the last operation. + [..] + HAL_XSPI_Abort() and HAL_XSPI_AbortIT() functions aborts any on-going operation and + flushes the fifo : + (+) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (+) In interrupt mode, HAL_XSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. + + *** Control functions *** + ========================= + [..] + HAL_XSPI_GetState() function gives the current state of the HAL XSPI driver. + [..] + HAL_XSPI_SetTimeout() function configures the timeout value used in the driver. + [..] + HAL_XSPI_SetFifoThreshold() function configures the threshold on the Fifo of the XSPI Peripheral. + [..] + HAL_XSPI_SetMemoryType() function configures the type of the external memory. + [..] + HAL_XSPI_SetDeviceSize() function configures the size of the external memory. + [..] + HAL_XSPI_SetClockPrescaler() function configures the clock prescaler of the XSPI Peripheral. + [..] + HAL_XSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + + *** IO manager configuration functions *** + ========================================== + [..] + HAL_XSPIM_Config() function configures the IO manager for the XSPI instance. + + *** High-speed interface and calibration functions *** + ========================================== + [..] + The purpose of High-speed interface is primary to shift data or data strobe by one quarter of octal + bus clock period, with a correct timing accuracy. DLL must be calibrated versus this clock period. + The calibration process is automatically enabled when one of the three conditions below is met: + (+) The XSPI exits Reset state. + (+) The Prescaler is set. + (+) The configuration of communication is set. + [..] + HAL_XSPI_GetDelayValue() function Get the delay values of the high-speed interface DLLs.. + [..] + HAL_XSPI_SetDelayValue() function Set the delay values of the high-speed interface DLLs.. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_XSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use function HAL_XSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : XSPI MspInit. + (+) MspDeInitCallback : XSPI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_XSPI_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : XSPI MspInit. + (+) MspDeInitCallback : XSPI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle and the Callback ID. + + [..] + By default, after the HAL_XSPI_Init() and if the state is HAL_XSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_XSPI_Init() + and HAL_XSPI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_XSPI_Init() and HAL_XSPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_XSPI_RegisterCallback() before calling HAL_XSPI_DeInit() + or HAL_XSPI_Init() function. + + [..] + When The compilation define USE_HAL_XSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" +#include "stm32n6xx_hal_rcc.h" + +#if defined(XSPI) || defined(XSPI1) || defined(XSPI2) || defined(XSPI3) + +/** @addtogroup STM32N6xx_HAL_Driver + * @{ + */ + +/** @defgroup XSPI XSPI + * @brief XSPI HAL module driver + * @{ + */ + +#ifdef HAL_XSPI_MODULE_ENABLED + +/** + @cond 0 + */ +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)XSPI_CR_FMODE_0) /*!< Indirect read mode */ +#define XSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)XSPI_CR_FMODE_1) /*!< Automatic polling mode */ +#define XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)XSPI_CR_FMODE) /*!< Memory-mapped mode */ + +#define XSPI_CFG_STATE_MASK 0x00000004U +#define XSPI_BUSY_STATE_MASK 0x00000008U + +#define XSPI_NB_INSTANCE 3U +#define XSPI_IOM_NB_PORTS 2U +#define XSPI_IOM_PORT_MASK 0x1U + +/* Private macro -------------------------------------------------------------*/ +#define IS_XSPI_FUNCTIONAL_MODE(MODE) (((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +#if defined(HAL_DMA_MODULE_ENABLED) +static void XSPI_DMACplt(DMA_HandleTypeDef *hdma); +static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma); +static void XSPI_DMAError(DMA_HandleTypeDef *hdma); +static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, FlagStatus State, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd); +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *pCfg); +/** + @endcond + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup XSPI_Exported_Functions XSPI Exported Functions + * @{ + */ + +/** @defgroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Initialize the XSPI. + (+) De-initialize the XSPI. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the XSPI mode according to the specified parameters + * in the XSPI_InitTypeDef and initialize the associated handle. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + status = HAL_ERROR; + /* No error code can be set set as the handler is null */ + } + else + { + /* Check the parameters of the initialization structure */ + assert_param(IS_XSPI_MEMORY_MODE(hxspi->Init.MemoryMode)); + assert_param(IS_XSPI_MEMORY_TYPE(hxspi->Init.MemoryType)); + assert_param(IS_XSPI_MEMORY_SIZE(hxspi->Init.MemorySize)); + assert_param(IS_XSPI_CS_HIGH_TIME_CYCLE(hxspi->Init.ChipSelectHighTimeCycle)); + assert_param(IS_XSPI_FREE_RUN_CLK(hxspi->Init.FreeRunningClock)); + assert_param(IS_XSPI_CLOCK_MODE(hxspi->Init.ClockMode)); + assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize)); + assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler)); + assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting)); + assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); + assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); + assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran)); + assert_param(IS_XSPI_CSSEL(hxspi->Init.MemorySelect)); + assert_param(IS_XSPI_EXTENDMEM(hxspi->Init.MemoryExtended)); + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Check if the state is the reset state */ + if (hxspi->State == HAL_XSPI_STATE_RESET) + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_XSPI_STATE_RESET only */ + hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; + hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; + hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; + hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; + hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; + hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; + hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; + hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; + hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; + hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; + + if (hxspi->MspInitCallback == NULL) + { + hxspi->MspInitCallback = HAL_XSPI_MspInit; + } + + /* Init the low level hardware */ + hxspi->MspInitCallback(hxspi); +#else + /* Initialization of the low level hardware */ + HAL_XSPI_MspInit(hxspi); +#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + /* Configure the default timeout for the XSPI memory access */ + (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); + + /* Configure memory type, device size, chip select high time, free running clock, clock mode */ + MODIFY_REG(hxspi->Instance->DCR1, + (XSPI_DCR1_MTYP | XSPI_DCR1_DEVSIZE | XSPI_DCR1_CSHT | XSPI_DCR1_FRCK | XSPI_DCR1_CKMODE), + (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) | + ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); + + if (hxspi->Init.MemoryExtended == HAL_XSPI_CSSEL_HW) + { + SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_EXTENDMEM); + } + + /* Configure wrap size */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize); + + /* Configure chip select boundary */ + MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_CSBOUND_Pos)); + + /* Configure maximum transfer */ + MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_MAXTRAN, \ + (hxspi->Init.MaxTran << XSPI_DCR3_MAXTRAN_Pos)); + + /* Configure refresh */ + hxspi->Instance->DCR4 = hxspi->Init.Refresh; + + /* Configure FIFO threshold */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos)); + + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Configure clock prescaler */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, + ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); + + if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* The configuration of clock prescaler trigger automatically a calibration process. + So it is necessary to wait the calibration is complete */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + if (status != HAL_OK) + { + return status; + } + } + /* Configure Dual Memory mode and CS Selection */ + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_DMM | XSPI_CR_CSSEL), + (hxspi->Init.MemoryMode | hxspi->Init.MemorySelect)); + + /* Configure sample shifting */ + MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT), hxspi->Init.SampleShifting); + + /* Enable XSPI */ + HAL_XSPI_ENABLE(hxspi); + + /* Enable free running clock if needed : must be done after XSPI enable */ + if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE) + { + SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + } + + /* Initialize the XSPI state */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT; + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + } + return status; +} + +/** + * @brief Initialize the XSPI MSP. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_MspInit can be implemented in the user file + */ +} + +/** + * @brief De-Initialize the XSPI peripheral. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + status = HAL_ERROR; + /* No error code can be set as the handler is null */ + } + else + { + /* Disable XSPI */ + HAL_XSPI_DISABLE(hxspi); + + /* Disable free running clock if needed : must be done after XSPI disable */ + CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + if (hxspi->MspDeInitCallback == NULL) + { + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + } + + /* De-initialize the low level hardware */ + hxspi->MspDeInitCallback(hxspi); +#else + /* De-initialize the low-level hardware */ + HAL_XSPI_MspDeInit(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + /* Reset the driver state */ + hxspi->State = HAL_XSPI_STATE_RESET; + } + + return status; +} + +/** + * @brief DeInitialize the XSPI MSP. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief XSPI Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Handle the interrupts. + (+) Handle the command sequence (regular and Hyperbus). + (+) Handle the Hyperbus configuration. + (+) Transmit data in blocking, interrupt or DMA mode. + (+) Receive data in blocking, interrupt or DMA mode. + (+) Manage the auto-polling functional mode. + (+) Manage the memory-mapped functional mode. + +@endverbatim + * @{ + */ + +/** + * @brief Handle XSPI interrupt request. + * @param hxspi : XSPI handle + * @retval None + */ +void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) +{ + __IO uint32_t *data_reg = &hxspi->Instance->DR; + uint32_t flag = hxspi->Instance->SR; + uint32_t itsource = hxspi->Instance->CR; + uint32_t currentstate = hxspi->State; + + /* XSPI fifo threshold interrupt occurred -------------------------------*/ + if (((flag & HAL_XSPI_FLAG_FT) != 0U) && ((itsource & HAL_XSPI_IT_FT) != 0U)) + { + if (currentstate == HAL_XSPI_STATE_BUSY_TX) + { + /* Write a data in the fifo */ + *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else if (currentstate == HAL_XSPI_STATE_BUSY_RX) + { + /* Read a data from the fifo */ + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else + { + /* Nothing to do */ + } + + if (hxspi->XferCount == 0U) + { + /* All data have been received or transmitted for the transfer */ + /* Disable fifo threshold interrupt */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_FT); + } + + /* Fifo threshold callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->FifoThresholdCallback(hxspi); +#else + HAL_XSPI_FifoThresholdCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + /* XSPI transfer complete interrupt occurred ----------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TC) != 0U) && ((itsource & HAL_XSPI_IT_TC) != 0U)) + { + if (currentstate == HAL_XSPI_STATE_BUSY_RX) + { + if ((hxspi->XferCount > 0U) && ((flag & XSPI_SR_FLEVEL) != 0U)) + { + /* Read the last data received in the fifo */ + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else if (hxspi->XferCount == 0U) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; + + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* RX complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->RxCpltCallback(hxspi); +#else + HAL_XSPI_RxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Nothing to do */ + } + } + else + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; + + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + if (currentstate == HAL_XSPI_STATE_BUSY_TX) + { + /* TX complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TxCpltCallback(hxspi); +#else + HAL_XSPI_TxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else if (currentstate == HAL_XSPI_STATE_BUSY_CMD) + { + /* Command complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->CmdCpltCallback(hxspi); +#else + HAL_XSPI_CmdCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else if (currentstate == HAL_XSPI_STATE_ABORT) + { + if (hxspi->ErrorCode == HAL_XSPI_ERROR_NONE) + { + /* Abort called by the user */ + /* Abort complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Abort due to an error (eg : DMA error) */ + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + /* Nothing to do */ + } + } + } + /* XSPI status match interrupt occurred ---------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_SM) != 0U) && ((itsource & HAL_XSPI_IT_SM) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_SM; + + /* Check if automatic poll mode stop is activated */ + if ((hxspi->Instance->CR & XSPI_CR_APMS) != 0U) + { + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + } + + /* Status match callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->StatusMatchCallback(hxspi); +#else + HAL_XSPI_StatusMatchCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + /* XSPI transfer error interrupt occurred -------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TE) != 0U) && ((itsource & HAL_XSPI_IT_TE) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TE; + + /* Disable all interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); + + /* Set error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_TRANSFER; + + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the DMA transmit on the DMA side */ + hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* Disable the DMA receive on the DMA side */ + hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + /* XSPI timeout interrupt occurred --------------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TO) != 0U) && ((itsource & HAL_XSPI_IT_TO) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TO; + + /* Timeout callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TimeOutCallback(hxspi); +#else + HAL_XSPI_TimeOutCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Set the command configuration. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType)); + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect)); + } + + assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode)); + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth)); + assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode)); + } + + assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode)); + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode)); + } + + assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode)); + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth)); + assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode)); + } + + assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + } + assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode)); + assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles)); + } + + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + + /* Check the state of the driver */ + state = hxspi->State; + if (((state == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) || + ((state == HAL_XSPI_STATE_READ_CMD_CFG) && ((pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) || + (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG))) || + ((state == HAL_XSPI_STATE_WRITE_CMD_CFG) && + ((pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) || + (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG)))) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Configure the registers */ + status = XSPI_ConfigCmd(hxspi, pCmd); + + if (status == HAL_OK) + { + if (pCmd->DataMode == HAL_XSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so wait until BUSY flag is reset to go back in idle state. */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + /* Clear TC flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + } + else + { + /* Update the state */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) + { + if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG; + } + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG; + } + } + else + { + /* Wrap configuration, no state change */ + } + } + } + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Set the command configuration in interrupt mode. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @note This function is used only in Indirect Read or Write Modes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType)); + + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect)); + } + + assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode)); + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth)); + assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode)); + } + + assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode)); + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode)); + } + + assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode)); + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth)); + assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode)); + } + + assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode)); + assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles)); + } + + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + + /* Check the state of the driver */ + if ((hxspi->State == HAL_XSPI_STATE_READY) && (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) && + (pCmd->DataMode == HAL_XSPI_DATA_NONE) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Configure the registers */ + status = XSPI_ConfigCmd(hxspi, pCmd); + + if (status == HAL_OK) + { + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_CMD; + + /* Enable the transfer complete and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_TE); + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the Hyperbus parameters. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to Structure containing the Hyperbus configuration + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCfgTypeDef *pCfg, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus configuration structure */ + assert_param(IS_XSPI_RW_RECOVERY_TIME_CYCLE(pCfg->RWRecoveryTimeCycle)); + assert_param(IS_XSPI_ACCESS_TIME_CYCLE(pCfg->AccessTimeCycle)); + assert_param(IS_XSPI_WRITE_ZERO_LATENCY(pCfg->WriteZeroLatency)); + assert_param(IS_XSPI_LATENCY_MODE(pCfg->LatencyMode)); + + /* Check the state of the driver */ + state = hxspi->State; + if ((state == HAL_XSPI_STATE_HYPERBUS_INIT) || (state == HAL_XSPI_STATE_READY)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure Hyperbus configuration Latency register */ + WRITE_REG(hxspi->Instance->HLCR, ((pCfg->RWRecoveryTimeCycle << XSPI_HLCR_TRWR_Pos) | + (pCfg->AccessTimeCycle << XSPI_HLCR_TACC_Pos) | + pCfg->WriteZeroLatency | pCfg->LatencyMode)); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_READY; + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Set the Hyperbus command configuration. + * @param hxspi : XSPI handle + * @param pCmd : Structure containing the Hyperbus command + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCmdTypeDef *pCmd, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus command structure */ + assert_param(IS_XSPI_ADDRESS_SPACE(pCmd->AddressSpace)); + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + + /* Check the state of the driver */ + if ((hxspi->State == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); + + /* Configure the address space in the DCR1 register */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP_0, pCmd->AddressSpace); + + /* Configure the CCR and WCCR registers with the address size and the following configuration : + - DQS signal enabled (used as RWDS) + - DTR mode enabled on address and data */ + /* - address and data on 8 or 16 lines */ + WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | pCmd->DataMode | + pCmd->AddressWidth | XSPI_CCR_ADDTR | XSPI_CCR_ADMODE_2)); + WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | pCmd->DataMode | + pCmd->AddressWidth | XSPI_WCCR_ADDTR | XSPI_WCCR_ADMODE_2)); + + /* Configure the DLR register with the number of data */ + WRITE_REG(hxspi->Instance->DLR, (pCmd->DataLength - 1U)); + + /* Configure the AR register with the address value */ + WRITE_REG(hxspi->Instance->AR, pCmd->Address); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hxspi->Instance->DR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = (uint8_t *)pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + do + { + /* Wait till fifo threshold flag is set to send data */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; + hxspi->pBuffPtr++; + hxspi->XferCount--; + } while (hxspi->XferCount > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hxspi->Instance->DR; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + do + { + /* Wait till fifo threshold or transfer complete flags are set to read received data */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } while (hxspi->XferCount > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = (uint8_t *)pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_TX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_RX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = hxspi->Instance->DLR + 1U; + DMA_QListTypeDef *p_queue = {NULL}; + uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + p_queue = hxspi->hdmatx->LinkedListQueue; + if ((p_queue != NULL) && (p_queue->Head != NULL)) + { + data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + } + else + { + /* Set Error Code function status */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + data_width = hxspi->hdmatx->Init.DestDataWidth; + } + /* Configure counters and size */ + if (data_width == DMA_DEST_DATAWIDTH_BYTE) + { + hxspi->XferCount = data_size; + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else + { + /* Nothing to do */ + } + + if (status == HAL_OK) + { + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = (uint8_t *)pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_TX; + + /* Set the DMA transfer complete callback */ + hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hxspi->hdmatx->XferErrorCallback = XSPI_DMAError; + + /* Clear the DMA abort callback */ + hxspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the transmit DMA Channel */ + if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hxspi->hdmatx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ + (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED)); + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ + DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH); + /* Set DMA data size*/ + p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; + /* Set DMA source address */ + p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + /* Set DMA destination address */ + p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; + + status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx); + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && + (hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_FIXED)) + { + status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->XferSize); + } + else + { + /* no transmit possible with DMA peripheral, invalid configuration */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + if (status == HAL_OK) + { + /* Enable the transfer error interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer. + * @note This function is used only in Indirect Read Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = hxspi->Instance->DLR + 1U; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + DMA_QListTypeDef *p_queue = {NULL}; + uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + p_queue = hxspi->hdmarx->LinkedListQueue; + if ((p_queue != NULL) && (p_queue->Head != NULL)) + { + data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + data_width = hxspi->hdmarx->Init.DestDataWidth; + } + + /* Configure counters and size */ + if (data_width == DMA_DEST_DATAWIDTH_BYTE) + { + hxspi->XferCount = data_size; + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else + { + /* Nothing to do */ + } + + if (status == HAL_OK) + { + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_RX; + + /* Set the DMA transfer complete callback */ + hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hxspi->hdmarx->XferErrorCallback = XSPI_DMAError; + + /* Clear the DMA abort callback */ + hxspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the receive DMA Channel */ + if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hxspi->hdmarx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ + (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED)); + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ + DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY); + /* Set DMA data size */ + p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; + /* Set DMA source address */ + p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; + /* Set DMA destination address */ + p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx); + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_SINC_FIXED) + && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED)) + { + status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->XferSize); + } + else + { + /* no receive possible with DMA peripheral, invalid configuration */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + if (status == HAL_OK) + { + /* Enable the transfer error interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Configure the XSPI Automatic Polling Mode in blocking mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the polling configuration information. + * @param Timeout : Timeout duration + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hxspi->Instance->DLR; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode)); + assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop)); + assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime)); + assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); + + /* Check the state */ + if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_ENABLE)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); + WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); + WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), + (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + /* Wait till status match flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear status match flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the XSPI Automatic Polling Mode in non-blocking mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the polling configuration information. + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hxspi->Instance->DLR; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode)); + assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop)); + assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime)); + assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); + WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); + WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), + (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_SM); + + hxspi->State = HAL_XSPI_STATE_BUSY_AUTO_POLLING; + + /* Enable the status match and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the Memory Mapped mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the memory mapped configuration information. + * @note This function is used only in Memory mapped Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, const XSPI_MemoryMappedTypeDef *pCfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the memory-mapped configuration structure */ + assert_param(IS_XSPI_TIMEOUT_ACTIVATION(pCfg->TimeOutActivation)); + assert_param(IS_XSPI_NO_PREFETCH_DATA(pCfg->NoPrefetchData)); + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; + + if (pCfg->NoPrefetchData == HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE) + { + /* Configure register */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_NOPREF, pCfg->NoPrefetchData); + } + + else + { + assert_param(IS_XSPI_NO_PREFETCH_AXI(pCfg->NoPrefetchAXI)); + + /* Configure register */ + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_NOPREF | XSPI_CR_NOPREF_AXI), + (pCfg->NoPrefetchData | pCfg->NoPrefetchAXI)); + } + if (pCfg->TimeOutActivation == HAL_XSPI_TIMEOUT_COUNTER_ENABLE) + { + assert_param(IS_XSPI_TIMEOUT_PERIOD(pCfg->TimeoutPeriodClock)); + + /* Configure register */ + WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO); + + /* Enable the timeout interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO); + } + + /* Configure CR register with functional mode as memory-mapped */ + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), + (pCfg->TimeOutActivation | XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Check whether the XSPI is configured in Memory-mapped mode or not. + * @param hxspi : XSPI handle + * @retval Status (0: Memory-mapped disabled or XSPI not initialized, 1: Memory-mapped enabled) + */ +uint32_t HAL_XSPI_IsMemoryMapped(XSPI_HandleTypeDef *hxspi) +{ + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + return (0UL); + } + /* Check if driver is in Reset state */ + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + return (0UL); + } + else + { + return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FMODE) == XSPI_CR_FMODE) ? 1UL : 0UL); + } +} + +/** + * @brief Transfer Error callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Abort completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief FIFO Threshold callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_FIFOThresholdCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_CmdCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Status Match callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_StatusMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_TimeOutCallback could be implemented in the user file + */ +} + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User XSPI Callback + * To be used to override the weak predefined callback + * @param hxspi : XSPI handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_XSPI_ERROR_CB_ID XSPI Error Callback ID + * @arg @ref HAL_XSPI_ABORT_CB_ID XSPI Abort Callback ID + * @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID + * @arg @ref HAL_XSPI_CMD_CPLT_CB_ID XSPI Command Complete Callback ID + * @arg @ref HAL_XSPI_RX_CPLT_CB_ID XSPI Rx Complete Callback ID + * @arg @ref HAL_XSPI_TX_CPLT_CB_ID XSPI Tx Complete Callback ID + * @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID XSPI Rx Half Complete Callback ID + * @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID XSPI Tx Half Complete Callback ID + * @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID XSPI Status Match Callback ID + * @arg @ref HAL_XSPI_TIMEOUT_CB_ID XSPI Timeout Callback ID + * @arg @ref HAL_XSPI_MSP_INIT_CB_ID XSPI MspInit callback ID + * @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID XSPI MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, + pXSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hxspi->State == HAL_XSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_XSPI_ERROR_CB_ID : + hxspi->ErrorCallback = pCallback; + break; + case HAL_XSPI_ABORT_CB_ID : + hxspi->AbortCpltCallback = pCallback; + break; + case HAL_XSPI_FIFO_THRESHOLD_CB_ID : + hxspi->FifoThresholdCallback = pCallback; + break; + case HAL_XSPI_CMD_CPLT_CB_ID : + hxspi->CmdCpltCallback = pCallback; + break; + case HAL_XSPI_RX_CPLT_CB_ID : + hxspi->RxCpltCallback = pCallback; + break; + case HAL_XSPI_TX_CPLT_CB_ID : + hxspi->TxCpltCallback = pCallback; + break; + case HAL_XSPI_RX_HALF_CPLT_CB_ID : + hxspi->RxHalfCpltCallback = pCallback; + break; + case HAL_XSPI_TX_HALF_CPLT_CB_ID : + hxspi->TxHalfCpltCallback = pCallback; + break; + case HAL_XSPI_STATUS_MATCH_CB_ID : + hxspi->StatusMatchCallback = pCallback; + break; + case HAL_XSPI_TIMEOUT_CB_ID : + hxspi->TimeOutCallback = pCallback; + break; + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = pCallback; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = pCallback; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User XSPI Callback + * XSPI Callback is redirected to the weak predefined callback + * @param hxspi : XSPI handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_XSPI_ERROR_CB_ID XSPI Error Callback ID + * @arg @ref HAL_XSPI_ABORT_CB_ID XSPI Abort Callback ID + * @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID + * @arg @ref HAL_XSPI_CMD_CPLT_CB_ID XSPI Command Complete Callback ID + * @arg @ref HAL_XSPI_RX_CPLT_CB_ID XSPI Rx Complete Callback ID + * @arg @ref HAL_XSPI_TX_CPLT_CB_ID XSPI Tx Complete Callback ID + * @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID XSPI Rx Half Complete Callback ID + * @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID XSPI Tx Half Complete Callback ID + * @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID XSPI Status Match Callback ID + * @arg @ref HAL_XSPI_TIMEOUT_CB_ID XSPI Timeout Callback ID + * @arg @ref HAL_XSPI_MSP_INIT_CB_ID XSPI MspInit callback ID + * @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID XSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hxspi->State == HAL_XSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_XSPI_ERROR_CB_ID : + hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; + break; + case HAL_XSPI_ABORT_CB_ID : + hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; + break; + case HAL_XSPI_FIFO_THRESHOLD_CB_ID : + hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; + break; + case HAL_XSPI_CMD_CPLT_CB_ID : + hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; + break; + case HAL_XSPI_RX_CPLT_CB_ID : + hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; + break; + case HAL_XSPI_TX_CPLT_CB_ID : + hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; + break; + case HAL_XSPI_RX_HALF_CPLT_CB_ID : + hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; + break; + case HAL_XSPI_TX_HALF_CPLT_CB_ID : + hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; + break; + case HAL_XSPI_STATUS_MATCH_CB_ID : + hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; + break; + case HAL_XSPI_TIMEOUT_CB_ID : + hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; + break; + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = HAL_XSPI_MspInit; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = HAL_XSPI_MspInit; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief XSPI control and State functions + * +@verbatim + =============================================================================== + ##### Peripheral Control and State functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Check in run-time the state of the driver. + (+) Check the error code set during last operation. + (+) Abort any operation. + (+) Manage the Fifo threshold. + (+) Configure the timeout duration used in the driver. + +@endverbatim + * @{ + */ + +/** + * @brief Abort the current operation, return to the indirect mode. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) + { +#if defined(HAL_DMA_MODULE_ENABLED) + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA transmit on the DMA side */ + status = HAL_DMA_Abort(hxspi->hdmatx); + if (status != HAL_OK) + { + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + } + + /* Disable the DMA receive on the DMA side */ + status = HAL_DMA_Abort(hxspi->hdmarx); + if (status != HAL_OK) + { + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Abort the current operation, return to the indirect mode. (non-blocking function) + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) + { + /* Disable all interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); + + hxspi->State = HAL_XSPI_STATE_ABORT; + + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the DMA transmit on the DMA side */ + hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* Disable the DMA receive on the DMA side */ + hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +#endif /*HAL_DMA_MODULE_ENABLED*/ + } + else + { + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + } + else + { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Fifo threshold. + * @param hxspi : XSPI handle. + * @param Threshold : Threshold of the Fifo. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(Threshold)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new fifo threshold value */ + hxspi->Init.FifoThresholdByte = Threshold; + + /* Configure new fifo threshold */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos)); + + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Get XSPI Fifo threshold. + * @param hxspi : XSPI handle. + * @retval Fifo threshold + */ +uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi) +{ + return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U); +} + +/** @brief Set XSPI Memory Type. + * @param hxspi : XSPI handle. + * @param Type : Memory Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_MEMORY_TYPE(Type)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new memory type value */ + hxspi->Init.MemoryType = Type; + + /* Configure new memory type */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP, hxspi->Init.MemoryType); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Device Size. + * @param hxspi : XSPI handle. + * @param Size : Device Size. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_MEMORY_SIZE(Size)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new device size value */ + hxspi->Init.MemorySize = Size; + + /* Configure new device size */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, + (hxspi->Init.MemorySize << XSPI_DCR1_DEVSIZE_Pos)); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Clock prescaler. + * @param hxspi : XSPI handle. + * @param Prescaler : Clock prescaler. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_XSPI_CLK_PRESCALER(Prescaler)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new clock prescaler value */ + hxspi->Init.ClockPrescaler = Prescaler; + + /* Configure clock prescaler */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, + ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI timeout. + * @param hxspi : XSPI handle. + * @param Timeout : Timeout for the memory access. + * @retval HAL state + */ +HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout) +{ + hxspi->Timeout = Timeout; + return HAL_OK; +} + +/** + * @brief Return the XSPI error code. + * @param hxspi : XSPI handle + * @retval XSPI Error Code + */ +uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi) +{ + return hxspi->ErrorCode; +} + +/** + * @brief Return the XSPI handle state. + * @param hxspi : XSPI handle + * @retval HAL state + */ +uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) +{ + /* Return XSPI handle state */ + return hxspi->State; +} + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group4 IO Manager configuration function + * @brief XSPI IO Manager configuration function + * +@verbatim + =============================================================================== + ##### IO Manager configuration function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Configure the IO manager. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the XSPI IO manager. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to Configuration of the IO Manager for the instance + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, const XSPIM_CfgTypeDef *pCfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint8_t index; + uint8_t xspi_enabled = 0U; + + XSPIM_CfgTypeDef IOM_cfg[XSPI_NB_INSTANCE] = {0}; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + + /* Check the parameters of the XSPI IO Manager configuration structure */ + assert_param(IS_XSPIM_NCS_OVR(pCfg->nCSOverride)); + assert_param(IS_XSPIM_IO_PORT(pCfg->IOPort)); + assert_param(IS_XSPIM_REQ2ACKTIME(pCfg->Req2AckTime)); + + /**************** Get current configuration of the instances ****************/ + for (index = 0U; index < XSPI_NB_INSTANCE; index++) + { + XSPIM_GetConfig(index + 1U, &(IOM_cfg[index])); + } + + /********** Disable all XSPI to configure XSPI IO Manager **********/ + if (__HAL_RCC_XSPI1_IS_CLK_ENABLED() != 0U) + { + if ((XSPI1->CR & XSPI_CR_EN) != 0U) + { + CLEAR_BIT(XSPI1->CR, XSPI_CR_EN); + xspi_enabled |= 0x1U; + } + } + if (__HAL_RCC_XSPI2_IS_CLK_ENABLED() != 0U) + { + if ((XSPI2->CR & XSPI_CR_EN) != 0U) + { + CLEAR_BIT(XSPI2->CR, XSPI_CR_EN); + xspi_enabled |= 0x2U; + } + } + if (__HAL_RCC_XSPI3_IS_CLK_ENABLED() != 0U) + { + if ((XSPI3->CR & XSPI_CR_EN) != 0U) + { + CLEAR_BIT(XSPI3->CR, XSPI_CR_EN); + xspi_enabled |= 0x4U; + } + } + + /***************** Store Port assignment ***********************************/ + if (hxspi->Instance == XSPI1) + { + IOM_cfg[0].IOPort = pCfg->IOPort ; + } + else if (hxspi->Instance == XSPI2) + { + IOM_cfg[1].IOPort = pCfg->IOPort ; + } + else if (hxspi->Instance == XSPI3) + { + if (pCfg->IOPort == HAL_XSPIM_IOPORT_1) + { + IOM_cfg[0].IOPort = HAL_XSPIM_IOPORT_2 ; + IOM_cfg[1].IOPort = HAL_XSPIM_IOPORT_2 ; + } + else if (pCfg->IOPort == HAL_XSPIM_IOPORT_2) + { + IOM_cfg[0].IOPort = HAL_XSPIM_IOPORT_1 ; + IOM_cfg[1].IOPort = HAL_XSPIM_IOPORT_1 ; + } + else + { + /* Nothing to do */ + } + } + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /******************** Store CSSEL_OVR settings before configuration ********/ + uint32_t reg = XSPIM->CR; + uint32_t ovr_xspi1; + uint32_t ovr_xspi2; + if ((reg & XSPIM_CR_CSSEL_OVR_EN) == XSPIM_CR_CSSEL_OVR_EN) + { + if ((reg & XSPIM_CR_CSSEL_OVR_O1) == XSPIM_CR_CSSEL_OVR_O1) + { + ovr_xspi1 = HAL_XSPI_CSSEL_OVR_NCS2; + } + else + { + ovr_xspi1 = HAL_XSPI_CSSEL_OVR_NCS1; + } + if ((reg & XSPIM_CR_CSSEL_OVR_O2) == XSPIM_CR_CSSEL_OVR_O2) + { + ovr_xspi2 = HAL_XSPI_CSSEL_OVR_NCS2; + } + else + { + ovr_xspi2 = HAL_XSPI_CSSEL_OVR_NCS1; + } + } + else + { + ovr_xspi1 = HAL_XSPI_CSSEL_OVR_DISABLED; + ovr_xspi2 = HAL_XSPI_CSSEL_OVR_DISABLED; + } + + /***************** Reset of previous configuration *************************/ + CLEAR_REG(XSPIM->CR); + + /******************** Activation of new configuration **********************/ + MODIFY_REG(XSPIM->CR, XSPIM_CR_REQ2ACK_TIME, ((pCfg->Req2AckTime - 1U) << XSPIM_CR_REQ2ACK_TIME_Pos)); + + /******************** CSSEL_OVR management *********************************/ + if (hxspi->Instance == XSPI1) + { + ovr_xspi1 = pCfg->nCSOverride; + } + else if (hxspi->Instance == XSPI2) + { + ovr_xspi2 = pCfg->nCSOverride; + } + else + { + /* Nothing to do */ + } + + uint32_t ovr_en = 0U; + if ((ovr_xspi1 != HAL_XSPI_CSSEL_OVR_DISABLED) || (ovr_xspi2 != HAL_XSPI_CSSEL_OVR_DISABLED)) + { + ovr_en = XSPIM_CR_CSSEL_OVR_EN; + } + else + { + ovr_xspi1 = HAL_XSPI_CSSEL_OVR_NCS1; + ovr_xspi2 = HAL_XSPI_CSSEL_OVR_NCS1; + } + + reg &= ~(XSPIM_CR_CSSEL_OVR_EN | XSPIM_CR_CSSEL_OVR_O1 | XSPIM_CR_CSSEL_OVR_O2); + if (ovr_en == XSPIM_CR_CSSEL_OVR_EN) + { + reg |= XSPIM_CR_CSSEL_OVR_EN; + } + if (ovr_xspi1 == HAL_XSPI_CSSEL_OVR_NCS2) + { + reg |= XSPIM_CR_CSSEL_OVR_O1; + } + if (ovr_xspi2 == HAL_XSPI_CSSEL_OVR_NCS2) + { + reg |= XSPIM_CR_CSSEL_OVR_O2; + } + + MODIFY_REG(XSPIM->CR, (XSPIM_CR_CSSEL_OVR_EN | XSPIM_CR_CSSEL_OVR_O1 | XSPIM_CR_CSSEL_OVR_O2), + (reg & (XSPIM_CR_CSSEL_OVR_EN | XSPIM_CR_CSSEL_OVR_O1 | XSPIM_CR_CSSEL_OVR_O2))); + + /******************** Management of MUXEN and MODE *************************/ + for (index = 0U; index < (XSPI_NB_INSTANCE - 2U); index++) + { + if (IOM_cfg[index].IOPort == IOM_cfg[index + 1U].IOPort) + { + /*Mux*/ + SET_BIT(XSPIM->CR, XSPIM_CR_MUXEN); + } + else + { + /* Nothing to do */ + } + if (IOM_cfg[0].IOPort == HAL_XSPIM_IOPORT_2) + { + /*Mode*/ + SET_BIT(XSPIM->CR, XSPIM_CR_MODE); + } + else + { + /* Nothing to do */ + } + } + + /******* Re-enable all XSPI after configure XSPI IO Manager ***************/ + if ((xspi_enabled & 0x1U) != 0U) + { + SET_BIT(XSPI1->CR, XSPI_CR_EN); + } + if ((xspi_enabled & 0x2U) != 0U) + { + SET_BIT(XSPI2->CR, XSPI_CR_EN); + } + if ((xspi_enabled & 0x4U) != 0U) + { + SET_BIT(XSPI3->CR, XSPI_CR_EN); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions + * @brief XSPI high-speed interface and calibration functions + * +@verbatim + =============================================================================== + ##### High-speed interface and calibration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Get the delay values of the high-speed interface DLLs. + (+) Set a delay value for the high-speed interface DLLs. + +@endverbatim + * @{ + */ + +/** + * @brief Get the delay values of the high-speed interface DLLs. + * @param hxspi : XSPI handle + * @param pCfg : Current delay values corresponding to the DelayValueType field. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *pCfg) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t reg = 0; + + if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* Check the parameter specified in the structure */ + assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType)); + + switch (pCfg->DelayValueType) + { + case HAL_XSPI_CAL_FULL_CYCLE_DELAY: + reg = hxspi->Instance->CALFCR; + pCfg->MaxCalibration = (reg & XSPI_CALFCR_CALMAX); + break; + case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY: + reg = hxspi->Instance->CALMR; + break; + case HAL_XSPI_CAL_DATA_OUTPUT_DELAY: + reg = hxspi->Instance->CALSOR; + break; + case HAL_XSPI_CAL_DQS_INPUT_DELAY: + reg = hxspi->Instance->CALSIR; + break; + default: + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + break; + } + + if (status == HAL_OK) + { + pCfg->FineCalibrationUnit = (reg & XSPI_CALFCR_FINE); + pCfg->CoarseCalibrationUnit = ((reg & XSPI_CALFCR_COARSE) >> XSPI_CALFCR_COARSE_Pos); + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + + return status; +} + +/** + * @brief Set a delay value for the high-speed interface DLLs. + * @param hxspi : XSPI handle + * @param pCfg : Configuration of delay value specified in DelayValueType field. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, const XSPI_HSCalTypeDef *pCfg) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* Check the parameter specified in the structure */ + assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType)); + assert_param(IS_XSPI_FINECAL_VALUE(pCfg->FineCalibrationUnit)); + assert_param(IS_XSPI_COARSECAL_VALUE(pCfg->CoarseCalibrationUnit)); + + /* Check if the state isn't in one of the busy states */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + switch (pCfg->DelayValueType) + { + case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY: + MODIFY_REG(hxspi->Instance->CALMR, (XSPI_CALMR_COARSE | XSPI_CALMR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALMR_COARSE_Pos))); + break; + case HAL_XSPI_CAL_DATA_OUTPUT_DELAY: + MODIFY_REG(hxspi->Instance->CALSOR, (XSPI_CALSOR_COARSE | XSPI_CALSOR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALSOR_COARSE_Pos))); + break; + case HAL_XSPI_CAL_DQS_INPUT_DELAY: + MODIFY_REG(hxspi->Instance->CALSIR, (XSPI_CALSIR_COARSE | XSPI_CALSIR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALSIR_COARSE_Pos))); + break; + default: + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + break; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + + return status; +} + +/** + * @} + */ + +/** + @cond 0 + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA XSPI process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMACplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Enable the XSPI transfer complete Interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); +} + +/** + * @brief DMA XSPI process half complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = (hxspi->XferCount >> 1); + + if (hxspi->State == HAL_XSPI_STATE_BUSY_RX) + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->RxHalfCpltCallback(hxspi); +#else + HAL_XSPI_RxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TxHalfCpltCallback(hxspi); +#else + HAL_XSPI_TxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI communication error callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAError(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Abort the XSPI */ + if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) + { + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI abort complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_ABORT) + { + /* DMA abort called by XSPI abort */ + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + /* DMA abort called due to a transfer error interrupt */ + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Wait for a flag state until timeout. + * @param hxspi : XSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout + * @param Tickstart : Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is in expected state */ + while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hxspi->State = HAL_XSPI_STATE_READY; + hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the registers for the regular command mode. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @retval HAL status + */ +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ccr_reg; + __IO uint32_t *tcr_reg; + __IO uint32_t *ir_reg; + __IO uint32_t *abr_reg; + + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); + + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect)); + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_MSEL, pCmd->IOSelect); + } + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + ccr_reg = &(hxspi->Instance->WCCR); + tcr_reg = &(hxspi->Instance->WTCR); + ir_reg = &(hxspi->Instance->WIR); + abr_reg = &(hxspi->Instance->WABR); + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG) + { + ccr_reg = &(hxspi->Instance->WPCCR); + tcr_reg = &(hxspi->Instance->WPTCR); + ir_reg = &(hxspi->Instance->WPIR); + abr_reg = &(hxspi->Instance->WPABR); + } + else + { + ccr_reg = &(hxspi->Instance->CCR); + tcr_reg = &(hxspi->Instance->TCR); + ir_reg = &(hxspi->Instance->IR); + abr_reg = &(hxspi->Instance->ABR); + } + + /* Configure the CCR register with DQS mode */ + *ccr_reg = pCmd->DQSMode; + + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + /* Configure the ABR register with alternate bytes value */ + *abr_reg = pCmd->AlternateBytes; + + /* Configure the CCR register with alternate bytes communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ABMODE | XSPI_CCR_ABDTR | XSPI_CCR_ABSIZE), + (pCmd->AlternateBytesMode | pCmd->AlternateBytesDTRMode | pCmd->AlternateBytesWidth)); + } + + /* Configure the TCR register with the number of dummy cycles */ + MODIFY_REG((*tcr_reg), XSPI_TCR_DCYC, pCmd->DummyCycles); + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hxspi->Instance->DLR = (pCmd->DataLength - 1U); + } + } + + /* Configure SSHIFT register to handle SDR/DTR data transfer */ + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) + { + /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */ + CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) + { + /* Configure sample shifting */ + SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else + { + /* Do nothing */ + } + } + + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with instruction, address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with instruction and address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); + } + /* Configure the IR register with the instruction value */ + *ir_reg = pCmd->Instruction; + + /* Configure the AR register with the address value */ + hxspi->Instance->AR = pCmd->Address; + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Verify if programmed address fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_ADDR(hxspi->Instance->AR, pCmd->Address)); + } + } + else + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with instruction and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with only instruction ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth)); + } + + /* Configure the IR register with the instruction value */ + *ir_reg = pCmd->Instruction; + + } + } + else + { + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with only address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), + (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); + } + + /* Configure the AR register with the instruction value */ + hxspi->Instance->AR = pCmd->Address; + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Verify if programmed address fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_ADDR(hxspi->Instance->AR, pCmd->Address)); + } + } + else + { + /* ---- Invalid command configuration (no instruction, no address) ---- */ + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + } + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hxspi->Instance->DLR = (pCmd->DataLength - 1U); + + /* Verify if programmed data fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_DATA(hxspi->Instance->DLR, (pCmd->DataLength - 1U))); + } + } + + return status; +} + +/** + * @brief Get the current IOM configuration for an XSPI instance. + * @param instance_nb : number of the instance + * @param pCfg : configuration of the IO Manager for the instance + * @retval HAL status + */ +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *pCfg) +{ + uint32_t mux; + uint32_t mode; + + if (instance_nb == 1U) + { + if ((XSPIM->CR & XSPIM_CR_MODE) == 0U) + { + pCfg->IOPort = HAL_XSPIM_IOPORT_1; + } + else + { + pCfg->IOPort = HAL_XSPIM_IOPORT_2; + } + + if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED; + } + else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O1) == XSPIM_CR_CSSEL_OVR_O1) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2; + } + else + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; + } + } + else + { + mux = (XSPIM->CR & XSPIM_CR_MUXEN); + mode = ((XSPIM->CR & XSPIM_CR_MODE) >> XSPIM_CR_MODE_Pos); + if (mux != mode) + { + pCfg->IOPort = HAL_XSPIM_IOPORT_1; + } + else + { + pCfg->IOPort = HAL_XSPIM_IOPORT_2; + } + if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED; + } + else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O2) == XSPIM_CR_CSSEL_OVR_O2) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2; + } + else + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; + } + } +} +/** + @endcond + */ + +/** + * @} + */ + +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XSPI || XSPI1 || XSPI2 || XSPI3 */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Inc/gpio.h =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Inc/gpio.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Inc/gpio.h (revision 16) @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + Index: trunk/firmware/FSBL/CubeMX/FSBL/Inc/main.h =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Inc/main.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Inc/main.h (revision 16) @@ -0,0 +1,89 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined ( __ICCARM__ ) +# define CMSE_NS_CALL __cmse_nonsecure_call +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_CALL __attribute((cmse_nonsecure_call)) +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* Function pointer declaration in non-secure*/ +#if defined ( __ICCARM__ ) +typedef void (CMSE_NS_CALL *funcptr)(void); +#else +typedef void CMSE_NS_CALL (*funcptr)(void); +#endif + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS; + +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define GREEN_LED_Pin GPIO_PIN_0 +#define GREEN_LED_GPIO_Port GPIOG + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Inc/stm32n6xx_hal_conf.h =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Inc/stm32n6xx_hal_conf.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Inc/stm32n6xx_hal_conf.h (revision 16) @@ -0,0 +1,513 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_CONF_H +#define STM32N6xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_BSEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DCMIPP_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GFXTIM_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_ICACHE_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MCE_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +/*#define HAL_RIF_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_XSPI_MODULE_ENABLED +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_MDIOS_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */ +/* The real value may vary depending on the variations in voltage and temperature.*/ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32n6xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ######################### */ + +#define USE_SDIO_TRANSCEIVER 0U +#define SDIO_MAX_IO_NUMBER 7U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32n6xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_RIF_MODULE_ENABLED +#include "stm32n6xx_hal_rif.h" +#endif /* HAL_RIF_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32n6xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CACHEAXI_MODULE_ENABLED +#include "stm32n6xx_hal_cacheaxi.h" +#endif /* HAL_CACHEAXI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32n6xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32n6xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_BSEC_MODULE_ENABLED +#include "stm32n6xx_hal_bsec.h" +#endif /* HAL_BSEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32n6xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32n6xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32n6xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32n6xx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32n6xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32n6xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32n6xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32n6xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32n6xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32n6xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32n6xx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32n6xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32n6xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32n6xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32n6xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32n6xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32n6xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32n6xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32n6xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32n6xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32n6xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32n6xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32n6xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32n6xx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32n6xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED +#include "stm32n6xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32n6xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32n6xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32n6xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32n6xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32n6xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32n6xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32n6xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32n6xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32n6xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32n6xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32n6xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32n6xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32n6xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32n6xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#include "stm32n6xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32n6xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32n6xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32n6xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32n6xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32n6xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32n6xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macros -----------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_CONF_H */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Inc/stm32n6xx_it.h =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Inc/stm32n6xx_it.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Inc/stm32n6xx_it.h (revision 16) @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32N6xx_IT_H +#define __STM32N6xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SecureFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32N6xx_IT_H */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Inc/xspi.h =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Inc/xspi.h (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Inc/xspi.h (revision 16) @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file xspi.h + * @brief This file contains all the function prototypes for + * the xspi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __XSPI_H__ +#define __XSPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern XSPI_HandleTypeDef hxspi2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_XSPI2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __XSPI_H__ */ + Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/gpio.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/gpio.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/gpio.c (revision 16) @@ -0,0 +1,199 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOQ_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GREEN_LED_GPIO_Port, GREEN_LED_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PQ6 PQ3 PQ4 PQ5 + PQ2 PQ1 PQ0 PQ7 */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 + |GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOQ, &GPIO_InitStruct); + + /*Configure GPIO pins : PC10 PC1 PC4 PC11 + PC6 PC5 PC9 PC12 + PC7 PC0 PC8 PC2 + PC3 PC13 */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_11 + |GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_9|GPIO_PIN_12 + |GPIO_PIN_7|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_2 + |GPIO_PIN_3|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PE13 PE15 PE8 PE9 + PE14 PE12 PE7 PE10 + PE5 PE4 PE6 PE11 + PE3 PE2 PE0 PE1 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_9 + |GPIO_PIN_14|GPIO_PIN_12|GPIO_PIN_7|GPIO_PIN_10 + |GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_11 + |GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pins : PD10 PD1 PD15 PD4 + PD2 PD12 PD14 PD13 + PD6 PD0 PD5 PD7 + PD3 PD8 PD11 PD9 */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_4 + |GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_14|GPIO_PIN_13 + |GPIO_PIN_6|GPIO_PIN_0|GPIO_PIN_5|GPIO_PIN_7 + |GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : PH3 PH6 PH8 PH7 + PH9 PH2 PH4 PH5 */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_7 + |GPIO_PIN_9|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pins : PB14 PB13 PB2 PB9 + PB8 PB15 PB0 PB7 + PB6 PB3 PB11 PB12 + PB1 PB4 PB10 PB5 */ + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_2|GPIO_PIN_9 + |GPIO_PIN_8|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_7 + |GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_10|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PP7 PP6 PP0 PP4 + PP1 PP15 PP5 PP12 + PP3 PP2 PP13 PP11 + PP8 PP14 PP9 PP10 */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_0|GPIO_PIN_4 + |GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_5|GPIO_PIN_12 + |GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_13|GPIO_PIN_11 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOP, &GPIO_InitStruct); + + /*Configure GPIO pins : PO5 PO1 PO2 PO3 + PO0 PO4 */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_0|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOO, &GPIO_InitStruct); + + /*Configure GPIO pins : PG7 PG6 PG5 PG4 + PG14 PG3 PG15 PG1 + PG12 PG10 PG2 PG9 + PG8 PG13 PG11 */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4 + |GPIO_PIN_14|GPIO_PIN_3|GPIO_PIN_15|GPIO_PIN_1 + |GPIO_PIN_12|GPIO_PIN_10|GPIO_PIN_2|GPIO_PIN_9 + |GPIO_PIN_8|GPIO_PIN_13|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : PF4 PF10 PF6 PF7 + PF3 PF5 PF15 PF14 + PF8 PF2 PF9 PF11 + PF1 PF13 PF0 PF12 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_8|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_11 + |GPIO_PIN_1|GPIO_PIN_13|GPIO_PIN_0|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pins : PA9 PA6 PA1 PA15 + PA10 PA5 PA7 PA3 + PA11 PA2 PA12 PA8 + PA0 PA4 */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_6|GPIO_PIN_1|GPIO_PIN_15 + |GPIO_PIN_10|GPIO_PIN_5|GPIO_PIN_7|GPIO_PIN_3 + |GPIO_PIN_11|GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_8 + |GPIO_PIN_0|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : PN12 PN7 */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPION, &GPIO_InitStruct); + + /*Configure GPIO pin : GREEN_LED_Pin */ + GPIO_InitStruct.Pin = GREEN_LED_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GREEN_LED_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/main.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/main.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/main.c (revision 16) @@ -0,0 +1,253 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "xspi.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* Enable the CPU Cache */ + + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); + + /* Enable D-Cache---------------------------------------------------------*/ + SCB_EnableDCache(); + + /* MCU Configuration--------------------------------------------------------*/ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_XSPI2_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + HAL_GPIO_WritePin(GPIOG, GPIO_PIN_0, GPIO_PIN_SET); + HAL_Delay(25U); + HAL_GPIO_WritePin(GPIOG, GPIO_PIN_0, GPIO_PIN_RESET); + HAL_Delay(25U); + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} +/* USER CODE BEGIN CLK 1 */ +/* USER CODE END CLK 1 */ + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the System Power Supply + */ + if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) + { + Error_Handler(); + } + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) + { + Error_Handler(); + } + + /* Enable HSI */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Get current CPU/System buses clocks configuration and if necessary switch + to intermediate HSI clock to ensure target clock can be set + */ + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct); + if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) || + (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) + { + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } + } + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_NONE; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL1.PLLM = 4; + RCC_OscInitStruct.PLL1.PLLN = 75; + RCC_OscInitStruct.PLL1.PLLFractional = 0; + RCC_OscInitStruct.PLL1.PLLP1 = 1; + RCC_OscInitStruct.PLL1.PLLP2 = 1; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_CPUCLK|RCC_CLOCKTYPE_HCLK + |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2|RCC_CLOCKTYPE_PCLK5 + |RCC_CLOCKTYPE_PCLK4; + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1; + RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC1Selection.ClockDivider = 2; + RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC2Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC6Selection.ClockDivider = 4; + RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC11Selection.ClockDivider = 3; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/stm32n6xx_hal_msp.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/stm32n6xx_hal_msp.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/stm32n6xx_hal_msp.c (revision 16) @@ -0,0 +1,80 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + HAL_PWREx_EnableVddIO3(); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/stm32n6xx_it.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/stm32n6xx_it.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/stm32n6xx_it.c (revision 16) @@ -0,0 +1,218 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32n6xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Secure fault. + */ +void SecureFault_Handler(void) +{ + /* USER CODE BEGIN SecureFault_IRQn 0 */ + + /* USER CODE END SecureFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_SecureFault_IRQn 0 */ + /* USER CODE END W1_SecureFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32N6xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32n6xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/syscalls.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/syscalls.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/syscalls.c (revision 16) @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +clock_t _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(const char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} + +// --- Picolibc Specific Section --- +#if defined(__PICOLIBC__) + +/** + * @brief Picolibc helper function to output a character to a FILE stream. + * This redirects the output to the low-level __io_putchar function. + * @param c Character to write. + * @param file FILE stream pointer (ignored). + * @retval int The character written. + */ +static int starm_putc(char c, FILE *file) +{ + (void) file; + __io_putchar(c); + return c; +} + +/** + * @brief Picolibc helper function to input a character from a FILE stream. + * This redirects the input from the low-level __io_getchar function. + * @param file FILE stream pointer (ignored). + * @retval int The character read, cast to an unsigned char then int. + */ +static int starm_getc(FILE *file) +{ + unsigned char c; + (void) file; + c = __io_getchar(); + return c; +} + +// Define and initialize the standard I/O streams for Picolibc. +// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. +// _FDEV_SETUP_RW indicates the stream is for reading and writing. +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, + starm_getc, + NULL, + _FDEV_SETUP_RW); + +// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. +// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). +FILE *const stdin = &__stdio; +__strong_reference(stdin, stdout); +__strong_reference(stdin, stderr); + +// Create strong aliases mapping standard C library function names (without underscore) +// to the implemented system call stubs (with underscore). Picolibc uses these +// standard names internally, so this linking is required. +__strong_reference(_read, read); +__strong_reference(_write, write); +__strong_reference(_times, times); +__strong_reference(_execve, execve); +__strong_reference(_fork, fork); +__strong_reference(_link, link); +__strong_reference(_unlink, unlink); +__strong_reference(_stat, stat); +__strong_reference(_wait, wait); +__strong_reference(_open, open); +__strong_reference(_close, close); +__strong_reference(_lseek, lseek); +__strong_reference(_isatty, isatty); +__strong_reference(_fstat, fstat); +__strong_reference(_exit, exit); +__strong_reference(_kill, kill); +__strong_reference(_getpid, getpid); + +#endif //__PICOLIBC__ Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/sysmem.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/sysmem.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/sysmem.c (revision 16) @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} + +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/system_stm32n6xx_fsbl.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/system_stm32n6xx_fsbl.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/system_stm32n6xx_fsbl.c (revision 16) @@ -0,0 +1,500 @@ +/** + ****************************************************************************** + * @file system_stm32n6xx_fsbl.c + * @author MCD Application Team + * @brief CMSIS Cortex-M55 Device Peripheral Access Layer System Source File + * to be used after the boot ROM execution in an applicative code called + * "FSBL" for First Stage Boot Loader. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at secure startup just after the + * boot ROM execution and before branch to secure main program. + * This call is made inside the "startup_stm32n6xx_fsbl.s" file. + * This function does not manage security isolation (IDAU/SAU, + * interrupts, ...) unless USER_TZ_SAU_SETUP is defined at + * project level. + * + * - SystemCoreClock variable: Contains the CPU core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32n6xx_fsbl.s" file, to + * configure the system before to branch to main program. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32N6xx_System + * @{ + */ + +/** @addtogroup STM32N6xx_System_Private_Includes + * @{ + */ + +#include "stm32n6xx.h" +#if defined(USER_TZ_SAU_SETUP) +#include "partition_stm32n6xx.h" /* Trustzone-M core secure attributes */ +#endif /* USER_TZ_SAU_SETUP */ +#include + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_TypesDefinitions + * @{ + */ + +#if defined ( __ICCARM__ ) +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the High-Speed External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000UL /*!< Minimum value of the Low-power Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +#if !defined (EXTERNAL_I2S_CLOCK_VALUE) + #define EXTERNAL_I2S_CLOCK_VALUE 12288000UL /*!< Value of the External clock for I2S_CKIN in Hz */ +#endif /* EXTERNAL_I2S_CLOCK_VALUE */ + + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in memory, else the vector table is kept at the automatic + selected boot address */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +#if !defined(VECT_TAB_BASE_ADDRESS) +#define VECT_TAB_BASE_ADDRESS SRAM1_AXI_BASE_S /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#endif + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32N6xx_System_Private_Functions + * @{ + */ + +#if defined(__ICCARM__) +extern uint32_t __vector_table; +#define INTVECT_START ((uint32_t)&__vector_table) +#elif defined(__ARMCC_VERSION) +extern void *__Vectors; +#define INTVECT_START ((uint32_t)&__Vectors) +#elif defined(__GNUC__) +extern void *g_pfnVectors; +#define INTVECT_START ((uint32_t)&g_pfnVectors) +#endif + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#else + SCB->VTOR = INTVECT_START; +#endif /* USER_VECT_TAB_ADDRESS */ + + /* RNG reset */ + RCC->AHB3RSTSR = RCC_AHB3RSTSR_RNGRSTS; + RCC->AHB3RSTCR = RCC_AHB3RSTCR_RNGRSTC; + /* Deactivate RNG clock */ + RCC->AHB3ENCR = RCC_AHB3ENCR_RNGENC; + + /* Clear SAU regions */ + SAU->RNR = 0; + SAU->RBAR = 0; + SAU->RLAR = 0; + SAU->RNR = 1; + SAU->RBAR = 0; + SAU->RLAR = 0; + SAU->RNR = 2; + SAU->RBAR = 0; + SAU->RLAR = 0; + SAU->RNR = 3; + SAU->RBAR = 0; + SAU->RLAR = 0; + SAU->RNR = 4; + SAU->RBAR = 0; + SAU->RLAR = 0; + SAU->RNR = 5; + SAU->RBAR = 0; + SAU->RLAR = 0; + SAU->RNR = 6; + SAU->RBAR = 0; + SAU->RLAR = 0; + SAU->RNR = 7; + SAU->RBAR = 0; + SAU->RLAR = 0; + + /* System configuration setup */ + RCC->APB4ENSR2 = RCC_APB4ENSR2_SYSCFGENS; + /* Delay after an RCC peripheral clock enabling */ + (void)RCC->APB4ENR2; + + /* Set default Vector Table location after system reset or return from Standby */ + SYSCFG->INITSVTORCR = SCB->VTOR; + + /* Compensation cells setting according to Errata Sheet ES0620 */ + /* a/ Enable access and configuration of VDDIOxCCCR registers */ + PWR->SVMCR1 |= PWR_SVMCR1_VDDIO4SV; + PWR->SVMCR2 |= PWR_SVMCR2_VDDIO5SV; + PWR->SVMCR3 |= PWR_SVMCR3_VDDIO2SV | PWR_SVMCR3_VDDIO3SV; + + /* b/ Enable access and configuration of VDDIOxCCCR registers */ + SYSCFG->VDDIO2CCCR = 0x00000287UL; /* VDDIO2 power domain compensation */ + SYSCFG->VDDIO3CCCR = 0x00000287UL; /* VDDIO3 power domain compensation */ + SYSCFG->VDDIO4CCCR = 0x00000287UL; /* VDDIO4 power domain compensation */ + SYSCFG->VDDIO5CCCR = 0x00000287UL; /* VDDIO4 power domain compensation */ + SYSCFG->VDDCCCR = 0x00000287UL; /* VDD power domain compensation */ + + /* Enable VDDADC CLAMP */ + PWR->SVMCR3 |= PWR_SVMCR3_ASV; + PWR->SVMCR3 |= PWR_SVMCR3_AVMEN; + /* read back the register to make sure that the transaction has taken place */ + (void) PWR->SVMCR3; + /* enable VREF */ + RCC->APB4ENR1 |= RCC_APB4ENR1_VREFBUFEN; + + /* RCC Fix to lower power consumption */ + RCC->APB4ENR2 |= 0x00000010UL; + (void) RCC->APB4ENR2; + RCC->APB4ENR2 &= ~(0x00000010UL); + + /* XSPI2 & XSPIM reset */ + RCC->AHB5RSTSR = RCC_AHB5RSTSR_XSPIMRSTS | RCC_AHB5RSTSR_XSPI2RSTS; + RCC->AHB5RSTCR = RCC_AHB5RSTCR_XSPIMRSTC | RCC_AHB5RSTCR_XSPI2RSTC; + + /* TIM2 reset */ + RCC->APB1RSTSR1 = RCC_APB1RSTSR1_TIM2RSTS; + RCC->APB1RSTCR1 = RCC_APB1RSTCR1_TIM2RSTC; + /* Deactivate TIM2 clock */ + RCC->APB1ENCR1 = RCC_APB1ENCR1_TIM2ENC; + + /* Deactivate GPIOG clock */ + RCC->AHB4ENCR = RCC_AHB4ENCR_GPIOGENC; + + /* Read back the value to make sure it is written before deactivating SYSCFG */ + (void) SYSCFG->INITSVTORCR; + /* Deactivate SYSCFG clock */ + RCC->APB4ENCR2 = RCC_APB4ENCR2_SYSCFGENC; + +#if defined(USER_TZ_SAU_SETUP) + /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ + TZ_SAU_Setup(); +#endif /* USER_TZ_SAU_SETUP */ + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + + SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif /* __FPU_PRESENT && __FPU_USED */ + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the CPU core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If CPUCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If CPUCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(**) + * + * - If CPUCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If CPUCLK source is IC1, SystemCoreClock will contain the HSI_VALUE(*) + * or MSI_VALUE(**) or HSE_VALUE(***) or EXTERNAL_I2S_CLOCK_VALUE (****) + * multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE default value is 64 MHz. + * With the HAL, HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file + * but the real value may vary depending on the variations in voltage and temperature. + * + * (**) MSI_VALUE default value is 4 MHz. + * With the HAL, MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file + * but the real value may vary depending on the variations in voltage and temperature. + * + * (***) HSE_VALUE default value is 30 MHz. + * With the HAL, HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file. + * User has to ensure that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * (****) EXTERNAL_I2S_CLOCK_VALUE default value is 12.288 MHz. + * With the HAL, EXTERNAL_I2S_CLOCK_VALUE is a constant defined in stm32n6xx_hal_conf.h file. + * User has to ensure that EXTERNAL_I2S_CLOCK_VALUE is same as the real I2S_CKIN + * pin frequency. Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t sysclk = 0; + uint32_t pllm = 0; + uint32_t plln = 0; + uint32_t pllfracn = 0; + uint32_t pllp1 = 0; + uint32_t pllp2 = 0; + uint32_t pllcfgr, pllsource, pllbypass, ic_divider; + float_t pllvco; + + /* Get CPUCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_CPUSWS) + { + case 0: /* HSI used as system clock source (default after reset) */ + sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos); + break; + + case RCC_CFGR1_CPUSWS_0: /* MSI used as system clock source */ + if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) + { + sysclk = MSI_VALUE; + } + else + { + sysclk = 16000000UL; + } + break; + + case RCC_CFGR1_CPUSWS_1: /* HSE used as system clock source */ + sysclk = HSE_VALUE; + break; + + case (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0): /* IC1 used as system clock source */ + /* Get IC1 clock source parameters */ + switch (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL)) + { + case 0: /* PLL1 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL1CFGR1); + pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL; + pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos; + plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL1CFGR3); + pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos; + } + break; + case RCC_IC1CFGR_IC1SEL_0: /* PLL2 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL2CFGR1); + pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL; + pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos; + plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL2CFGR3); + pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos; + } + break; + + case RCC_IC1CFGR_IC1SEL_1: /* PLL3 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL3CFGR1); + pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL; + pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos; + plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL3CFGR3); + pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos; + } + break; + + default: /* RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0 */ /* PLL4 selected at IC1 clock source */ + pllcfgr = READ_REG(RCC->PLL4CFGR1); + pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL; + pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP; + if (pllbypass == 0U) + { + pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos; + plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos; + pllfracn = READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos; + pllcfgr = READ_REG(RCC->PLL4CFGR3); + pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos; + pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos; + } + break; + } + + /* Get oscillator frequency used as PLL clock source */ + switch (pllsource) + { + case 0: /* HSI selected as PLL clock source */ + sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos); + break; + case RCC_PLL1CFGR1_PLL1SEL_0: /* MSI selected as PLL clock source */ + if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) + { + sysclk = MSI_VALUE; + } + else + { + sysclk = 16000000UL; + } + break; + case RCC_PLL1CFGR1_PLL1SEL_1: /* HSE selected as PLL clock source */ + sysclk = HSE_VALUE; + break; + case (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0): /* I2S_CKIN selected as PLL clock source */ + sysclk = EXTERNAL_I2S_CLOCK_VALUE; + break; + default: + /* Nothing to do, should not occur */ + break; + } + + /* Check whether PLL is in bypass mode or not */ + if (pllbypass == 0U) + { + /* Compte PLL output frequency (Integer and fractional modes) */ + /* PLLVCO = (Freq * (DIVN + (FRACN / 0x1000000) / DIVM) / (DIVP1 * DIVP2)) */ + pllvco = ((float_t)sysclk * ((float_t)plln + ((float_t)pllfracn/(float_t)0x1000000UL))) / (float_t)pllm; + sysclk = (uint32_t)((float_t)(pllvco/(((float_t)pllp1) * ((float_t)pllp2)))); + } + /* Apply IC1 divider */ + ic_divider = (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL; + sysclk = sysclk / ic_divider; + break; + default: + /* Nothing to do, should not occur */ + break; + } + + /* Return system clock frequency (CPU frequency) */ + SystemCoreClock = sysclk; +} + +/** + * @brief Secure Non-Secure-Callable function to return the current + * SystemCoreClock value after SystemCoreClock update. + * The SystemCoreClock variable contains the CPU core clock, it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @retval SystemCoreClock value + */ +CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void) +{ + SystemCoreClockUpdate(); + + return SystemCoreClock; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ Index: trunk/firmware/FSBL/CubeMX/FSBL/Src/xspi.c =================================================================== --- trunk/firmware/FSBL/CubeMX/FSBL/Src/xspi.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/FSBL/Src/xspi.c (revision 16) @@ -0,0 +1,168 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file xspi.c + * @brief This file provides code for the configuration + * of the XSPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "xspi.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +XSPI_HandleTypeDef hxspi2; + +/* XSPI2 init function */ +void MX_XSPI2_Init(void) +{ + + /* USER CODE BEGIN XSPI2_Init 0 */ + + /* USER CODE END XSPI2_Init 0 */ + + XSPIM_CfgTypeDef sXspiManagerCfg = {0}; + + /* USER CODE BEGIN XSPI2_Init 1 */ + + /* USER CODE END XSPI2_Init 1 */ + hxspi2.Instance = XSPI2; + hxspi2.Init.FifoThresholdByte = 4; + hxspi2.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; + hxspi2.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX; + hxspi2.Init.MemorySize = HAL_XSPI_SIZE_512MB; + hxspi2.Init.ChipSelectHighTimeCycle = 2; + hxspi2.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE; + hxspi2.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0; + hxspi2.Init.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED; + hxspi2.Init.ClockPrescaler = 0; + hxspi2.Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE; + hxspi2.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE; + hxspi2.Init.ChipSelectBoundary = HAL_XSPI_BONDARYOF_NONE; + hxspi2.Init.MaxTran = 0; + hxspi2.Init.Refresh = 0; + hxspi2.Init.MemorySelect = HAL_XSPI_CSSEL_NCS1; + if (HAL_XSPI_Init(&hxspi2) != HAL_OK) + { + Error_Handler(); + } + sXspiManagerCfg.nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; + sXspiManagerCfg.IOPort = HAL_XSPIM_IOPORT_2; + sXspiManagerCfg.Req2AckTime = 1; + if (HAL_XSPIM_Config(&hxspi2, &sXspiManagerCfg, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN XSPI2_Init 2 */ + + /* USER CODE END XSPI2_Init 2 */ + +} + +void HAL_XSPI_MspInit(XSPI_HandleTypeDef* xspiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(xspiHandle->Instance==XSPI2) + { + /* USER CODE BEGIN XSPI2_MspInit 0 */ + + /* USER CODE END XSPI2_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_XSPI2; + PeriphClkInitStruct.Xspi2ClockSelection = RCC_XSPI2CLKSOURCE_IC3; + PeriphClkInitStruct.ICSelection[RCC_IC3].ClockSelection = RCC_ICCLKSOURCE_PLL1; + PeriphClkInitStruct.ICSelection[RCC_IC3].ClockDivider = 24; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* XSPI2 clock enable */ + __HAL_RCC_XSPIM_CLK_ENABLE(); + __HAL_RCC_XSPI2_CLK_ENABLE(); + + __HAL_RCC_GPION_CLK_ENABLE(); + /**XSPI2 GPIO Configuration + PN4 ------> XSPIM_P2_IO2 + PN6 ------> XSPIM_P2_CLK + PN8 ------> XSPIM_P2_IO4 + PN0 ------> XSPIM_P2_DQS0 + PN3 ------> XSPIM_P2_IO1 + PN5 ------> XSPIM_P2_IO3 + PN1 ------> XSPIM_P2_NCS1 + PN9 ------> XSPIM_P2_IO5 + PN2 ------> XSPIM_P2_IO0 + PN10 ------> XSPIM_P2_IO6 + PN11 ------> XSPIM_P2_IO7 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_0 + |GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1|GPIO_PIN_9 + |GPIO_PIN_2|GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_XSPIM_P2; + HAL_GPIO_Init(GPION, &GPIO_InitStruct); + + /* USER CODE BEGIN XSPI2_MspInit 1 */ + + /* USER CODE END XSPI2_MspInit 1 */ + } +} + +void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef* xspiHandle) +{ + + if(xspiHandle->Instance==XSPI2) + { + /* USER CODE BEGIN XSPI2_MspDeInit 0 */ + + /* USER CODE END XSPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_XSPIM_CLK_DISABLE(); + __HAL_RCC_XSPI2_CLK_DISABLE(); + + /**XSPI2 GPIO Configuration + PN4 ------> XSPIM_P2_IO2 + PN6 ------> XSPIM_P2_CLK + PN8 ------> XSPIM_P2_IO4 + PN0 ------> XSPIM_P2_DQS0 + PN3 ------> XSPIM_P2_IO1 + PN5 ------> XSPIM_P2_IO3 + PN1 ------> XSPIM_P2_NCS1 + PN9 ------> XSPIM_P2_IO5 + PN2 ------> XSPIM_P2_IO0 + PN10 ------> XSPIM_P2_IO6 + PN11 ------> XSPIM_P2_IO7 + */ + HAL_GPIO_DeInit(GPION, GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_0 + |GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1|GPIO_PIN_9 + |GPIO_PIN_2|GPIO_PIN_10|GPIO_PIN_11); + + /* USER CODE BEGIN XSPI2_MspDeInit 1 */ + + /* USER CODE END XSPI2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + Index: trunk/firmware/FSBL/CubeMX/Makefile/FSBL/Makefile =================================================================== --- trunk/firmware/FSBL/CubeMX/Makefile/FSBL/Makefile (revision 16) +++ trunk/firmware/FSBL/CubeMX/Makefile/FSBL/Makefile (revision 16) @@ -0,0 +1,198 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [4.10.0-B28] date: [Thu Oct 01 09:29:42 CEST 2026] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = blto2_FSBL_FSBL + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +../../FSBL/Src/main.c \ +../../FSBL/Src/gpio.c \ +../../FSBL/Src/xspi.c \ +../../FSBL/Src/stm32n6xx_it.c \ +../../FSBL/Src/stm32n6xx_hal_msp.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_gpio.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr_ex.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal.c \ +../../Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_exti.c \ +../../FSBL/Src/system_stm32n6xx_fsbl.c \ +../../FSBL/Src/sysmem.c \ +../../FSBL/Src/syscalls.c + +# ASM sources +ASM_SOURCES = \ +startup_stm32n657xx_fsbl.s + +# ASMM sources +ASMM_SOURCES = + + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m55 + +# fpu +FPU = -mfpu=fpv5-d16 + +# float-abi +FLOAT-ABI = -mfloat-abi=hard + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DUSE_HAL_DRIVER \ +-DSTM32N657xx + + +# AS includes +AS_INCLUDES = + +# C includes +C_INCLUDES = \ +-I../../FSBL/Inc \ +-I../../Drivers/STM32N6xx_HAL_Driver/Inc \ +-I../../Drivers/CMSIS/Device/ST/STM32N6xx/Include \ +-I../../Drivers/STM32N6xx_HAL_Driver/Inc/Legacy \ +-I../../Drivers/CMSIS/Include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS += $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -mcmse -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32N657XX_AXISRAM2_fsbl.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -Wl,--cmse-implib -Wl,--out-implib=./build/secure_nsclib.o + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASMM_SOURCES:.S=.o))) +vpath %.S $(sort $(dir $(ASMM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** Index: trunk/firmware/FSBL/CubeMX/Makefile/FSBL/STM32N657XX_AXISRAM2_fsbl.ld =================================================================== --- trunk/firmware/FSBL/CubeMX/Makefile/FSBL/STM32N657XX_AXISRAM2_fsbl.ld (revision 16) +++ trunk/firmware/FSBL/CubeMX/Makefile/FSBL/STM32N657XX_AXISRAM2_fsbl.ld (revision 16) @@ -0,0 +1,254 @@ +/* +****************************************************************************** +** +** @file : STM32N657XX_AXISRAM2_fsbl.ld +** +** @author : GPM Application Team +** +** @brief : Linker script for STM32N657XX Device from STM32N6 series +** 512 KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Memories definition */ +MEMORY +{ + ROM (xrw) : ORIGIN = 0x34180400, LENGTH = 255K + RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K +} +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + .gnu.sgstubs : + { + _sNSCVeneer = .; + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(32); + FILL(0x00); + } >ROM + _eNSCVeneer = .; + /* Uninitialized data section into "RAM" Ram type memory */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + + } >RAM AT> ROM + + /* Initialized TLS data section */ + .tdata : ALIGN(4) + { + *(.tdata .tdata.* .gnu.linkonce.td.*) + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM AT> ROM + + PROVIDE( __tdata_start = ADDR(.tdata) ); + PROVIDE( __tdata_size = __tdata_end - __tdata_start ); + + PROVIDE( __data_start = ADDR(.data) ); + PROVIDE( __data_size = __data_end - __data_start ); + + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source ); + + PROVIDE( __data_source = LOADADDR(.data) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + /* Uninitialized TLS data section */ + .tbss (NOLOAD) : ALIGN(4) + { + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.tbss .tbss.*) + . = ALIGN(4); + PROVIDE( __tbss_end = . ); + } >RAM + + PROVIDE( __tbss_start = ADDR(.tbss) ); + PROVIDE( __tbss_size = __tbss_end - __tbss_start ); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + + PROVIDE( __tls_base = __tdata_start ); + PROVIDE( __tls_end = __tbss_end ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + .bss (NOLOAD) : ALIGN(4) + { + /* This is used by the startup in order to initialize the .bss section */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + PROVIDE( __bss_end = .); + } >RAM + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + + PROVIDE( __bss_start = __tbss_start ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack (NOLOAD) : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a:* ( * ) + libm.a:* ( * ) + libgcc.a:* ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} Index: trunk/firmware/FSBL/CubeMX/Makefile/FSBL/startup_stm32n657xx_fsbl.s =================================================================== --- trunk/firmware/FSBL/CubeMX/Makefile/FSBL/startup_stm32n657xx_fsbl.s (revision 16) +++ trunk/firmware/FSBL/CubeMX/Makefile/FSBL/startup_stm32n657xx_fsbl.s (revision 16) @@ -0,0 +1,943 @@ +/** + ****************************************************************************** + * @file startup_stm32n657xx.s + * @author GPM Application Team + * @brief STM32N657XX device vector table for GCC toolchain. + * This startup file should be used for the FSBL (after bootROM execution). + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.arch armv8.1-m.main +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_sstack + msr MSPLIM, r0 + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32N657XX vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word PVD_PVM_IRQHandler /* PVDOUT through the EXTI line */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Thermal sensor interruption */ + .word RCC_IRQHandler /* RCC global interrupt */ + .word LOCKUP_IRQHandler /* LOCKUP - no overstack in Cortex-M55 */ + .word CACHE_ECC_IRQHandler /* Cache ECC error */ + .word TCM_ECC_IRQHandler /* TCM ECC error */ + .word BCK_ECC_IRQHandler /* Backup RAM interrupts (SEC and DED) */ + .word FPU_IRQHandler /* FPU safety flag */ + .word 0 /* Reserved */ + .word RTC_S_IRQHandler /* RTC secure interrupt */ + .word TAMP_IRQHandler /* TAMP secure and non-secure synchronous interrupt line */ + .word RIFSC_TAMPER_IRQHandler /* RIF can generate an interrupt when a laser attack is detected */ + .word IAC_IRQHandler /* IAC global interrupt */ + .word RCC_S_IRQHandler /* RCC global secure interrupt */ + .word 0 /* Reserved */ + .word RTC_IRQHandler /* RTC interrupt */ + .word 0 /* Reserved */ + .word IWDG_IRQHandler /* Independent watchdog interrupt */ + .word WWDG_IRQHandler /* Window watchdog interrupt */ + .word EXTI0_IRQHandler /* EXTI Line 0 interrupt through the EXTI line */ + .word EXTI1_IRQHandler /* EXTI Line 1 interrupt through the EXTI line */ + .word EXTI2_IRQHandler /* EXTI Line 2 interrupt through the EXTI line */ + .word EXTI3_IRQHandler /* EXTI Line 3 interrupt through the EXTI line */ + .word EXTI4_IRQHandler /* EXTI Line 4 interrupt through the EXTI line */ + .word EXTI5_IRQHandler /* EXTI Line 5 interrupt through the EXTI line */ + .word EXTI6_IRQHandler /* EXTI Line 6 interrupt through the EXTI line */ + .word EXTI7_IRQHandler /* EXTI Line 7 interrupt through the EXTI line */ + .word EXTI8_IRQHandler /* EXTI Line 8 interrupt through the EXTI line */ + .word EXTI9_IRQHandler /* EXTI Line 9 interrupt */ + .word EXTI10_IRQHandler /* EXTI Line 10 interrupt */ + .word EXTI11_IRQHandler /* EXTI Line 11 interrupt */ + .word EXTI12_IRQHandler /* EXTI Line 12 interrupt */ + .word EXTI13_IRQHandler /* EXTI Line 13 interrupt */ + .word EXTI14_IRQHandler /* EXTI Line 14 interrupt */ + .word EXTI15_IRQHandler /* EXTI Line 15 interrupt */ + .word SAES_IRQHandler /* SAES global interrupt */ + .word CRYP_IRQHandler /* CRYP global interrupt */ + .word PKA_IRQHandler /* PKA global interrupt */ + .word HASH_IRQHandler /* HASH global interrupt */ + .word RNG_IRQHandler /* RNG global interrupt */ + .word 0 /* Reserved */ + .word MCE1_IRQHandler /* MCE1 global interrupt */ + .word MCE2_IRQHandler /* MCE2 global interrupt */ + .word MCE3_IRQHandler /* MCE3 global interrupt */ + .word MCE4_IRQHandler /* MCE4 global interrupt */ + .word ADC1_2_IRQHandler /* ADC1/ADC2 global interrupt */ + .word CSI_IRQHandler /* CSI global interrupt */ + .word DCMIPP_IRQHandler /* DCMIPP global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PAHB_ERR_IRQHandler /* Write posting errors on Cortex-M55 PAHB interface */ + .word NPU0_IRQHandler /* NPU mst_ints[0] line */ + .word NPU1_IRQHandler /* NPU mst_ints[1] line */ + .word NPU2_IRQHandler /* NPU mst_ints[2] line */ + .word NPU3_IRQHandler /* NPU mst_ints[3] line */ + .word CACHEAXI_IRQHandler /* ATON interrupt cache */ + .word LTDC_LO_IRQHandler /* LCD low-layer global interrupt */ + .word LTDC_LO_ERR_IRQHandler /* LCD low-layer error interrupt */ + .word DMA2D_IRQHandler /* DMA2D global interrupt */ + .word JPEG_IRQHandler /* JPEG global interrupt */ + .word VENC_IRQHandler /* VENC global interrupt */ + .word GFXMMU_IRQHandler /* GFXMMU global interrupt */ + .word GFXTIM_IRQHandler /* GFXTIM global interrupt */ + .word GPU2D_IRQHandler /* GPU2D global interrupt */ + .word GPU2D_ER_IRQHandler /* GPU2D global interrupt */ + .word ICACHE_IRQHandler /* GPU cache interrupt */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 interrupt */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 interrupt */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 interrupt */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 interrupt */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 interrupt */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 interrupt */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 interrupt */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 interrupt */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 interrupt */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 interrupt */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 interrupt */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 interrupt */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 interrupt */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 interrupt */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 interrupt */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 interrupt */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 channel 0 interrupt */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 channel 1 interrupt */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 channel 2 interrupt */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 channel 3 interrupt */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 channel 4 interrupt */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 channel 5 interrupt */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 channel 6 interrupt */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 channel 7 interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 channel 8 interrupt */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 channel 9 interrupt */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 channel 10 interrupt */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 channel 11 interrupt */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 channel 12 interrupt */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 channel 13 interrupt */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 channel 14 interrupt */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 channel 15 interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word I2C4_EV_IRQHandler /* I2C4 event interrupt */ + .word I2C4_ER_IRQHandler /* I2C4 error interrupt */ + .word I3C1_EV_IRQHandler /* I3C1 event interrupt */ + .word I3C1_ER_IRQHandler /* I3C1 error interrupt */ + .word I3C2_EV_IRQHandler /* I3C2 event interrupt */ + .word I3C2_ER_IRQHandler /* I3C2 error interrupt */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_CCU_IRQHandler /* TIM1 Trigger and Commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM4_IRQHandler /* TIM4 global interrupt */ + .word TIM5_IRQHandler /* TIM5 global interrupt */ + .word TIM6_IRQHandler /* TIM6 Global interrupt */ + .word TIM7_IRQHandler /* TIM7 Global interrupt */ + .word TIM8_BRK_IRQHandler /* TIM8 Break interrupt */ + .word TIM8_UP_IRQHandler /* TIM8 Update interrupt */ + .word TIM8_TRG_CCU_IRQHandler /* TIM8 Trigger and Commutation interrupts */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */ + .word TIM9_IRQHandler /* TIM9 Global interrupt */ + .word TIM10_IRQHandler /* TIM10 Global interrupt */ + .word TIM11_IRQHandler /* TIM11 Global interrupt */ + .word TIM12_IRQHandler /* TIM12 Global interrupt */ + .word TIM13_IRQHandler /* TIM13 Global interrupt */ + .word TIM14_IRQHandler /* TIM14 Global interrupt */ + .word TIM15_IRQHandler /* TIM15 global interrupt */ + .word TIM16_IRQHandler /* TIM16 global interrupt */ + .word TIM17_IRQHandler /* TIM17 global interrupt */ + .word TIM18_IRQHandler /* TIM18 Global interrupt */ + .word LPTIM1_IRQHandler /* LPTIM1 global interrupt */ + .word LPTIM2_IRQHandler /* LPTIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LPTIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LPTIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LPTIM5 global interrupt */ + .word ADF1_FLT0_IRQHandler /* ADF1 filter 0 global interrupt */ + .word MDF1_FLT0_IRQHandler /* MDF global Interrupt for Filter0 */ + .word MDF1_FLT1_IRQHandler /* MDF global Interrupt for Filter1 */ + .word MDF1_FLT2_IRQHandler /* MDF global Interrupt for Filter2 */ + .word MDF1_FLT3_IRQHandler /* MDF global Interrupt for Filter3 */ + .word MDF1_FLT4_IRQHandler /* MDF global Interrupt for Filter4 */ + .word MDF1_FLT5_IRQHandler /* MDF global Interrupt for Filter5 */ + .word SAI1_A_IRQHandler /* SAI1 global interrupt A */ + .word SAI1_B_IRQHandler /* SAI1 global interrupt B */ + .word SAI2_A_IRQHandler /* SAI2 global interrupt A */ + .word SAI2_B_IRQHandler /* SAI2 global interrupt B */ + .word SPDIFRX_IRQHandler /* SPDIFRX global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt A */ + .word SPI2_IRQHandler /* SPI2 global interrupt A */ + .word SPI3_IRQHandler /* SPI3 global interrupt A */ + .word SPI4_IRQHandler /* SPI4 global interrupt A */ + .word SPI5_IRQHandler /* SPI5 global interrupt A */ + .word SPI6_IRQHandler /* SPI6 global interrupt A */ + .word USART1_IRQHandler /* USART1 Global interrupt */ + .word USART2_IRQHandler /* USART2 Global interrupt */ + .word USART3_IRQHandler /* USART3 Global interrupt */ + .word UART4_IRQHandler /* UART4 Global interrupt */ + .word UART5_IRQHandler /* UART5 Global interrupt */ + .word USART6_IRQHandler /* USART6 Global interrupt */ + .word UART7_IRQHandler /* UART7 Global interrupt */ + .word UART8_IRQHandler /* UART8 Global interrupt */ + .word UART9_IRQHandler /* UART9 Global interrupt */ + .word USART10_IRQHandler /* USART10 Global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt */ + .word XSPI1_IRQHandler /* XSPI1 global interrupt */ + .word XSPI2_IRQHandler /* XSPI2 global interrupt */ + .word XSPI3_IRQHandler /* XSPI3 global interrupt */ + .word FMC_IRQHandler /* FMC global interrupt */ + .word SDMMC1_IRQHandler /* SDMMC1 global interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 global interrupt */ + .word UCPD1_IRQHandler /* UCPD global interrupt */ + .word USB1_OTG_HS_IRQHandler /* USB OTG1 HS global interrupt */ + .word USB2_OTG_HS_IRQHandler /* USB OTG2 HS global interrupt */ + .word ETH1_IRQHandler /* Ethernet global interrupt */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt 1 */ + .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt 0 */ + .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt 1 */ + .word FDCAN_CU_IRQHandler /* Clock calibration unit interrupt line(FDCAN1 only) */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word DCMI_PSSI_IRQHandler /* DCMI/PSSI global interrupt */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pin interrupts */ + .word CTI_INT0_IRQHandler /* Debug monitor (Cortex-M55 related) */ + .word CTI_INT1_IRQHandler /* Debug monitor (Cortex-M55 related) */ + .word 0 /* Reserved */ + .word LTDC_UP_IRQHandler /* LCD up-layer global interrupt */ + .word LTDC_UP_ERR_IRQHandler /* LCD up-layer error interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak LOCKUP_IRQHandler + .thumb_set LOCKUP_IRQHandler,Default_Handler + + .weak CACHE_ECC_IRQHandler + .thumb_set CACHE_ECC_IRQHandler,Default_Handler + + .weak TCM_ECC_IRQHandler + .thumb_set TCM_ECC_IRQHandler,Default_Handler + + .weak BCK_ECC_IRQHandler + .thumb_set BCK_ECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RIFSC_TAMPER_IRQHandler + .thumb_set RIFSC_TAMPER_IRQHandler,Default_Handler + + .weak IAC_IRQHandler + .thumb_set IAC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak MCE1_IRQHandler + .thumb_set MCE1_IRQHandler,Default_Handler + + .weak MCE2_IRQHandler + .thumb_set MCE2_IRQHandler,Default_Handler + + .weak MCE3_IRQHandler + .thumb_set MCE3_IRQHandler,Default_Handler + + .weak MCE4_IRQHandler + .thumb_set MCE4_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CSI_IRQHandler + .thumb_set CSI_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak PAHB_ERR_IRQHandler + .thumb_set PAHB_ERR_IRQHandler,Default_Handler + + .weak NPU0_IRQHandler + .thumb_set NPU0_IRQHandler,Default_Handler + + .weak NPU1_IRQHandler + .thumb_set NPU1_IRQHandler,Default_Handler + + .weak NPU2_IRQHandler + .thumb_set NPU2_IRQHandler,Default_Handler + + .weak NPU3_IRQHandler + .thumb_set NPU3_IRQHandler,Default_Handler + + .weak CACHEAXI_IRQHandler + .thumb_set CACHEAXI_IRQHandler,Default_Handler + + .weak LTDC_LO_IRQHandler + .thumb_set LTDC_LO_IRQHandler,Default_Handler + + .weak LTDC_LO_ERR_IRQHandler + .thumb_set LTDC_LO_ERR_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak VENC_IRQHandler + .thumb_set VENC_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak GPU2D_IRQHandler + .thumb_set GPU2D_IRQHandler,Default_Handler + + .weak GPU2D_ER_IRQHandler + .thumb_set GPU2D_ER_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I3C2_EV_IRQHandler + .thumb_set I3C2_EV_IRQHandler,Default_Handler + + .weak I3C2_ER_IRQHandler + .thumb_set I3C2_ER_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_CCU_IRQHandler + .thumb_set TIM1_TRG_CCU_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_CCU_IRQHandler + .thumb_set TIM8_TRG_CCU_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak TIM18_IRQHandler + .thumb_set TIM18_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak MDF1_FLT0_IRQHandler + .thumb_set MDF1_FLT0_IRQHandler,Default_Handler + + .weak MDF1_FLT1_IRQHandler + .thumb_set MDF1_FLT1_IRQHandler,Default_Handler + + .weak MDF1_FLT2_IRQHandler + .thumb_set MDF1_FLT2_IRQHandler,Default_Handler + + .weak MDF1_FLT3_IRQHandler + .thumb_set MDF1_FLT3_IRQHandler,Default_Handler + + .weak MDF1_FLT4_IRQHandler + .thumb_set MDF1_FLT4_IRQHandler,Default_Handler + + .weak MDF1_FLT5_IRQHandler + .thumb_set MDF1_FLT5_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak SPDIFRX_IRQHandler + .thumb_set SPDIFRX_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak XSPI3_IRQHandler + .thumb_set XSPI3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak USB1_OTG_HS_IRQHandler + .thumb_set USB1_OTG_HS_IRQHandler,Default_Handler + + .weak USB2_OTG_HS_IRQHandler + .thumb_set USB2_OTG_HS_IRQHandler,Default_Handler + + .weak ETH1_IRQHandler + .thumb_set ETH1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak FDCAN_CU_IRQHandler + .thumb_set FDCAN_CU_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak CTI_INT0_IRQHandler + .thumb_set CTI_INT0_IRQHandler,Default_Handler + + .weak CTI_INT1_IRQHandler + .thumb_set CTI_INT1_IRQHandler,Default_Handler + + .weak LTDC_UP_IRQHandler + .thumb_set LTDC_UP_IRQHandler,Default_Handler + + .weak LTDC_UP_ERR_IRQHandler + .thumb_set LTDC_UP_ERR_IRQHandler,Default_Handler + + .weak SystemInit + +/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/ Index: trunk/firmware/FSBL/CubeMX/Makefile/Makefile =================================================================== --- trunk/firmware/FSBL/CubeMX/Makefile/Makefile (revision 16) +++ trunk/firmware/FSBL/CubeMX/Makefile/Makefile (revision 16) @@ -0,0 +1,111 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.20.0-B9] date: [Mon Apr 24 18:51:17 WAT 2023] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu + +# fpu + +# float-abi + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + + + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS += $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + + +####################################### +# LDFLAGS +####################################### + + +# default action: build all +all: + cd FSBL && $(MAKE) + + + +####################################### +# build the application +####################################### +# list of objects + +EXEC =main +main= cd Secure && $(MAKE) + + + +####################################### +# clean up +####################################### +clean: + -rm -fR $(EXEC) + +####################################### +# dependencies +###################################### + +# *** EOF *** Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/.project =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/.project (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/.project (revision 16) @@ -0,0 +1,26 @@ + + + blto2_FSBL + + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCURootPythonProjectNature + com.st.stm32cube.ide.mcu.MCUFsblEnabledProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + + + + blto2_FSBL.ioc + 1 + PARENT-1-PROJECT_LOC/blto2_FSBL.ioc + + + Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/.cproject =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/.cproject (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/.cproject (revision 16) @@ -0,0 +1,172 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/.project =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/.project (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/.project (revision 16) @@ -0,0 +1,126 @@ + + + blto2_FSBL + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUSecureProjectNature + com.st.stm32cube.ide.mcu.MCUFSBLProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Application/User/gpio.c + 1 + copy_PARENT/FSBL/Src/gpio.c + + + Application/User/main.c + 1 + copy_PARENT/FSBL/Src/main.c + + + Application/User/stm32n6xx_hal_msp.c + 1 + copy_PARENT/FSBL/Src/stm32n6xx_hal_msp.c + + + Application/User/stm32n6xx_it.c + 1 + copy_PARENT/FSBL/Src/stm32n6xx_it.c + + + Application/User/xspi.c + 1 + copy_PARENT/FSBL/Src/xspi.c + + + Drivers/CMSIS/system_stm32n6xx_fsbl.c + 1 + copy_PARENT/FSBL/Src/system_stm32n6xx_fsbl.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_dma.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_dma_ex.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_exti.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_exti.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_gpio.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pwr_ex.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c + + + Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.c + 1 + copy_PARENT/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c + + + + + copy_PARENT + file:/D:/Projekte/hadewe_blto2/trunk/firmware/FSBL/CubeMX + + + Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/Startup/startup_stm32n657x0hxq_fsbl.s =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/Startup/startup_stm32n657x0hxq_fsbl.s (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/Startup/startup_stm32n657x0hxq_fsbl.s (revision 16) @@ -0,0 +1,943 @@ +/** + ****************************************************************************** + * @file startup_stm32n657xx.s + * @author GPM Application Team + * @brief STM32N657XX device vector table for GCC toolchain. + * This startup file should be used for the FSBL (after bootROM execution). + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.arch armv8.1-m.main +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_sstack + msr MSPLIM, r0 + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32N657XX vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word PVD_PVM_IRQHandler /* PVDOUT through the EXTI line */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Thermal sensor interruption */ + .word RCC_IRQHandler /* RCC global interrupt */ + .word LOCKUP_IRQHandler /* LOCKUP - no overstack in Cortex-M55 */ + .word CACHE_ECC_IRQHandler /* Cache ECC error */ + .word TCM_ECC_IRQHandler /* TCM ECC error */ + .word BCK_ECC_IRQHandler /* Backup RAM interrupts (SEC and DED) */ + .word FPU_IRQHandler /* FPU safety flag */ + .word 0 /* Reserved */ + .word RTC_S_IRQHandler /* RTC secure interrupt */ + .word TAMP_IRQHandler /* TAMP secure and non-secure synchronous interrupt line */ + .word RIFSC_TAMPER_IRQHandler /* RIF can generate an interrupt when a laser attack is detected */ + .word IAC_IRQHandler /* IAC global interrupt */ + .word RCC_S_IRQHandler /* RCC global secure interrupt */ + .word 0 /* Reserved */ + .word RTC_IRQHandler /* RTC interrupt */ + .word 0 /* Reserved */ + .word IWDG_IRQHandler /* Independent watchdog interrupt */ + .word WWDG_IRQHandler /* Window watchdog interrupt */ + .word EXTI0_IRQHandler /* EXTI Line 0 interrupt through the EXTI line */ + .word EXTI1_IRQHandler /* EXTI Line 1 interrupt through the EXTI line */ + .word EXTI2_IRQHandler /* EXTI Line 2 interrupt through the EXTI line */ + .word EXTI3_IRQHandler /* EXTI Line 3 interrupt through the EXTI line */ + .word EXTI4_IRQHandler /* EXTI Line 4 interrupt through the EXTI line */ + .word EXTI5_IRQHandler /* EXTI Line 5 interrupt through the EXTI line */ + .word EXTI6_IRQHandler /* EXTI Line 6 interrupt through the EXTI line */ + .word EXTI7_IRQHandler /* EXTI Line 7 interrupt through the EXTI line */ + .word EXTI8_IRQHandler /* EXTI Line 8 interrupt through the EXTI line */ + .word EXTI9_IRQHandler /* EXTI Line 9 interrupt */ + .word EXTI10_IRQHandler /* EXTI Line 10 interrupt */ + .word EXTI11_IRQHandler /* EXTI Line 11 interrupt */ + .word EXTI12_IRQHandler /* EXTI Line 12 interrupt */ + .word EXTI13_IRQHandler /* EXTI Line 13 interrupt */ + .word EXTI14_IRQHandler /* EXTI Line 14 interrupt */ + .word EXTI15_IRQHandler /* EXTI Line 15 interrupt */ + .word SAES_IRQHandler /* SAES global interrupt */ + .word CRYP_IRQHandler /* CRYP global interrupt */ + .word PKA_IRQHandler /* PKA global interrupt */ + .word HASH_IRQHandler /* HASH global interrupt */ + .word RNG_IRQHandler /* RNG global interrupt */ + .word 0 /* Reserved */ + .word MCE1_IRQHandler /* MCE1 global interrupt */ + .word MCE2_IRQHandler /* MCE2 global interrupt */ + .word MCE3_IRQHandler /* MCE3 global interrupt */ + .word MCE4_IRQHandler /* MCE4 global interrupt */ + .word ADC1_2_IRQHandler /* ADC1/ADC2 global interrupt */ + .word CSI_IRQHandler /* CSI global interrupt */ + .word DCMIPP_IRQHandler /* DCMIPP global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PAHB_ERR_IRQHandler /* Write posting errors on Cortex-M55 PAHB interface */ + .word NPU0_IRQHandler /* NPU mst_ints[0] line */ + .word NPU1_IRQHandler /* NPU mst_ints[1] line */ + .word NPU2_IRQHandler /* NPU mst_ints[2] line */ + .word NPU3_IRQHandler /* NPU mst_ints[3] line */ + .word CACHEAXI_IRQHandler /* ATON interrupt cache */ + .word LTDC_LO_IRQHandler /* LCD low-layer global interrupt */ + .word LTDC_LO_ERR_IRQHandler /* LCD low-layer error interrupt */ + .word DMA2D_IRQHandler /* DMA2D global interrupt */ + .word JPEG_IRQHandler /* JPEG global interrupt */ + .word VENC_IRQHandler /* VENC global interrupt */ + .word GFXMMU_IRQHandler /* GFXMMU global interrupt */ + .word GFXTIM_IRQHandler /* GFXTIM global interrupt */ + .word GPU2D_IRQHandler /* GPU2D global interrupt */ + .word GPU2D_ER_IRQHandler /* GPU2D global interrupt */ + .word ICACHE_IRQHandler /* GPU cache interrupt */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 interrupt */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 interrupt */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 interrupt */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 interrupt */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 interrupt */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 interrupt */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 interrupt */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 interrupt */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 interrupt */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 interrupt */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 interrupt */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 interrupt */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 interrupt */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 interrupt */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 interrupt */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 interrupt */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 channel 0 interrupt */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 channel 1 interrupt */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 channel 2 interrupt */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 channel 3 interrupt */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 channel 4 interrupt */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 channel 5 interrupt */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 channel 6 interrupt */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 channel 7 interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 channel 8 interrupt */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 channel 9 interrupt */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 channel 10 interrupt */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 channel 11 interrupt */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 channel 12 interrupt */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 channel 13 interrupt */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 channel 14 interrupt */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 channel 15 interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word I2C4_EV_IRQHandler /* I2C4 event interrupt */ + .word I2C4_ER_IRQHandler /* I2C4 error interrupt */ + .word I3C1_EV_IRQHandler /* I3C1 event interrupt */ + .word I3C1_ER_IRQHandler /* I3C1 error interrupt */ + .word I3C2_EV_IRQHandler /* I3C2 event interrupt */ + .word I3C2_ER_IRQHandler /* I3C2 error interrupt */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_CCU_IRQHandler /* TIM1 Trigger and Commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM4_IRQHandler /* TIM4 global interrupt */ + .word TIM5_IRQHandler /* TIM5 global interrupt */ + .word TIM6_IRQHandler /* TIM6 Global interrupt */ + .word TIM7_IRQHandler /* TIM7 Global interrupt */ + .word TIM8_BRK_IRQHandler /* TIM8 Break interrupt */ + .word TIM8_UP_IRQHandler /* TIM8 Update interrupt */ + .word TIM8_TRG_CCU_IRQHandler /* TIM8 Trigger and Commutation interrupts */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */ + .word TIM9_IRQHandler /* TIM9 Global interrupt */ + .word TIM10_IRQHandler /* TIM10 Global interrupt */ + .word TIM11_IRQHandler /* TIM11 Global interrupt */ + .word TIM12_IRQHandler /* TIM12 Global interrupt */ + .word TIM13_IRQHandler /* TIM13 Global interrupt */ + .word TIM14_IRQHandler /* TIM14 Global interrupt */ + .word TIM15_IRQHandler /* TIM15 global interrupt */ + .word TIM16_IRQHandler /* TIM16 global interrupt */ + .word TIM17_IRQHandler /* TIM17 global interrupt */ + .word TIM18_IRQHandler /* TIM18 Global interrupt */ + .word LPTIM1_IRQHandler /* LPTIM1 global interrupt */ + .word LPTIM2_IRQHandler /* LPTIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LPTIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LPTIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LPTIM5 global interrupt */ + .word ADF1_FLT0_IRQHandler /* ADF1 filter 0 global interrupt */ + .word MDF1_FLT0_IRQHandler /* MDF global Interrupt for Filter0 */ + .word MDF1_FLT1_IRQHandler /* MDF global Interrupt for Filter1 */ + .word MDF1_FLT2_IRQHandler /* MDF global Interrupt for Filter2 */ + .word MDF1_FLT3_IRQHandler /* MDF global Interrupt for Filter3 */ + .word MDF1_FLT4_IRQHandler /* MDF global Interrupt for Filter4 */ + .word MDF1_FLT5_IRQHandler /* MDF global Interrupt for Filter5 */ + .word SAI1_A_IRQHandler /* SAI1 global interrupt A */ + .word SAI1_B_IRQHandler /* SAI1 global interrupt B */ + .word SAI2_A_IRQHandler /* SAI2 global interrupt A */ + .word SAI2_B_IRQHandler /* SAI2 global interrupt B */ + .word SPDIFRX_IRQHandler /* SPDIFRX global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt A */ + .word SPI2_IRQHandler /* SPI2 global interrupt A */ + .word SPI3_IRQHandler /* SPI3 global interrupt A */ + .word SPI4_IRQHandler /* SPI4 global interrupt A */ + .word SPI5_IRQHandler /* SPI5 global interrupt A */ + .word SPI6_IRQHandler /* SPI6 global interrupt A */ + .word USART1_IRQHandler /* USART1 Global interrupt */ + .word USART2_IRQHandler /* USART2 Global interrupt */ + .word USART3_IRQHandler /* USART3 Global interrupt */ + .word UART4_IRQHandler /* UART4 Global interrupt */ + .word UART5_IRQHandler /* UART5 Global interrupt */ + .word USART6_IRQHandler /* USART6 Global interrupt */ + .word UART7_IRQHandler /* UART7 Global interrupt */ + .word UART8_IRQHandler /* UART8 Global interrupt */ + .word UART9_IRQHandler /* UART9 Global interrupt */ + .word USART10_IRQHandler /* USART10 Global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt */ + .word XSPI1_IRQHandler /* XSPI1 global interrupt */ + .word XSPI2_IRQHandler /* XSPI2 global interrupt */ + .word XSPI3_IRQHandler /* XSPI3 global interrupt */ + .word FMC_IRQHandler /* FMC global interrupt */ + .word SDMMC1_IRQHandler /* SDMMC1 global interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 global interrupt */ + .word UCPD1_IRQHandler /* UCPD global interrupt */ + .word USB1_OTG_HS_IRQHandler /* USB OTG1 HS global interrupt */ + .word USB2_OTG_HS_IRQHandler /* USB OTG2 HS global interrupt */ + .word ETH1_IRQHandler /* Ethernet global interrupt */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt 1 */ + .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt 0 */ + .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt 1 */ + .word FDCAN_CU_IRQHandler /* Clock calibration unit interrupt line(FDCAN1 only) */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word DCMI_PSSI_IRQHandler /* DCMI/PSSI global interrupt */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pin interrupts */ + .word CTI_INT0_IRQHandler /* Debug monitor (Cortex-M55 related) */ + .word CTI_INT1_IRQHandler /* Debug monitor (Cortex-M55 related) */ + .word 0 /* Reserved */ + .word LTDC_UP_IRQHandler /* LCD up-layer global interrupt */ + .word LTDC_UP_ERR_IRQHandler /* LCD up-layer error interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak LOCKUP_IRQHandler + .thumb_set LOCKUP_IRQHandler,Default_Handler + + .weak CACHE_ECC_IRQHandler + .thumb_set CACHE_ECC_IRQHandler,Default_Handler + + .weak TCM_ECC_IRQHandler + .thumb_set TCM_ECC_IRQHandler,Default_Handler + + .weak BCK_ECC_IRQHandler + .thumb_set BCK_ECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RIFSC_TAMPER_IRQHandler + .thumb_set RIFSC_TAMPER_IRQHandler,Default_Handler + + .weak IAC_IRQHandler + .thumb_set IAC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak MCE1_IRQHandler + .thumb_set MCE1_IRQHandler,Default_Handler + + .weak MCE2_IRQHandler + .thumb_set MCE2_IRQHandler,Default_Handler + + .weak MCE3_IRQHandler + .thumb_set MCE3_IRQHandler,Default_Handler + + .weak MCE4_IRQHandler + .thumb_set MCE4_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CSI_IRQHandler + .thumb_set CSI_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak PAHB_ERR_IRQHandler + .thumb_set PAHB_ERR_IRQHandler,Default_Handler + + .weak NPU0_IRQHandler + .thumb_set NPU0_IRQHandler,Default_Handler + + .weak NPU1_IRQHandler + .thumb_set NPU1_IRQHandler,Default_Handler + + .weak NPU2_IRQHandler + .thumb_set NPU2_IRQHandler,Default_Handler + + .weak NPU3_IRQHandler + .thumb_set NPU3_IRQHandler,Default_Handler + + .weak CACHEAXI_IRQHandler + .thumb_set CACHEAXI_IRQHandler,Default_Handler + + .weak LTDC_LO_IRQHandler + .thumb_set LTDC_LO_IRQHandler,Default_Handler + + .weak LTDC_LO_ERR_IRQHandler + .thumb_set LTDC_LO_ERR_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak VENC_IRQHandler + .thumb_set VENC_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak GPU2D_IRQHandler + .thumb_set GPU2D_IRQHandler,Default_Handler + + .weak GPU2D_ER_IRQHandler + .thumb_set GPU2D_ER_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I3C2_EV_IRQHandler + .thumb_set I3C2_EV_IRQHandler,Default_Handler + + .weak I3C2_ER_IRQHandler + .thumb_set I3C2_ER_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_CCU_IRQHandler + .thumb_set TIM1_TRG_CCU_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_CCU_IRQHandler + .thumb_set TIM8_TRG_CCU_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak TIM18_IRQHandler + .thumb_set TIM18_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak MDF1_FLT0_IRQHandler + .thumb_set MDF1_FLT0_IRQHandler,Default_Handler + + .weak MDF1_FLT1_IRQHandler + .thumb_set MDF1_FLT1_IRQHandler,Default_Handler + + .weak MDF1_FLT2_IRQHandler + .thumb_set MDF1_FLT2_IRQHandler,Default_Handler + + .weak MDF1_FLT3_IRQHandler + .thumb_set MDF1_FLT3_IRQHandler,Default_Handler + + .weak MDF1_FLT4_IRQHandler + .thumb_set MDF1_FLT4_IRQHandler,Default_Handler + + .weak MDF1_FLT5_IRQHandler + .thumb_set MDF1_FLT5_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak SPDIFRX_IRQHandler + .thumb_set SPDIFRX_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak XSPI3_IRQHandler + .thumb_set XSPI3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak USB1_OTG_HS_IRQHandler + .thumb_set USB1_OTG_HS_IRQHandler,Default_Handler + + .weak USB2_OTG_HS_IRQHandler + .thumb_set USB2_OTG_HS_IRQHandler,Default_Handler + + .weak ETH1_IRQHandler + .thumb_set ETH1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak FDCAN_CU_IRQHandler + .thumb_set FDCAN_CU_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak CTI_INT0_IRQHandler + .thumb_set CTI_INT0_IRQHandler,Default_Handler + + .weak CTI_INT1_IRQHandler + .thumb_set CTI_INT1_IRQHandler,Default_Handler + + .weak LTDC_UP_IRQHandler + .thumb_set LTDC_UP_IRQHandler,Default_Handler + + .weak LTDC_UP_ERR_IRQHandler + .thumb_set LTDC_UP_ERR_IRQHandler,Default_Handler + + .weak SystemInit + +/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/ Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/User/syscalls.c =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/User/syscalls.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/User/syscalls.c (revision 16) @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/User/sysmem.c =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/User/sysmem.c (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Application/User/sysmem.c (revision 16) @@ -0,0 +1,86 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Debug/blto2_FSBL.map =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Debug/blto2_FSBL.map (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/Debug/blto2_FSBL.map (revision 16) @@ -0,0 +1,4711 @@ +Archive member included to satisfy reference by file (symbol) + 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C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard/crt0.o +LOAD ./Application/Startup/startup_stm32n657x0hxq_fsbl.o +LOAD ./Application/User/gpio.o +LOAD ./Application/User/main.o +LOAD ./Application/User/stm32n6xx_hal_msp.o +LOAD ./Application/User/stm32n6xx_it.o +LOAD ./Application/User/syscalls.o +LOAD ./Application/User/sysmem.o +LOAD ./Application/User/xspi.o +LOAD ./Drivers/CMSIS/system_stm32n6xx_fsbl.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_dma.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_dma_ex.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_exti.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o +LOAD ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o +START GROUP +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libm.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard\libgcc.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard\libgcc.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libnosys.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard\libgcc.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libnosys.a +END GROUP +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtend.o +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtn.o + 0x34200000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x341ff800 _sstack = (_estack - _Min_Stack_Size) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000800 _Min_Stack_Size = 0x800 + +.isr_vector 0x34180400 0x34c + 0x34180400 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x34180400 0x34c ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + 0x34180400 g_pfnVectors + 0x3418074c . = ALIGN (0x4) + +.text 0x3418074c 0xbc2c + 0x3418074c . = ALIGN (0x4) + *(.text) + .text 0x3418074c 0x40 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + *(.text*) + .text.Reset_Handler + 0x3418078c 0x5c ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + 0x3418078c Reset_Handler + .text.Default_Handler + 0x341807e8 0x2 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + 0x341807e8 HPDMA1_Channel13_IRQHandler + 0x341807e8 EXTI2_IRQHandler + 0x341807e8 MCE2_IRQHandler + 0x341807e8 TIM8_CC_IRQHandler + 0x341807e8 USB2_OTG_HS_IRQHandler + 0x341807e8 SAI1_A_IRQHandler + 0x341807e8 EXTI5_IRQHandler + 0x341807e8 I3C1_ER_IRQHandler + 0x341807e8 UART8_IRQHandler + 0x341807e8 CTI_INT0_IRQHandler + 0x341807e8 SPI4_IRQHandler + 0x341807e8 LTDC_LO_IRQHandler + 0x341807e8 NPU2_IRQHandler + 0x341807e8 FDCAN3_IT0_IRQHandler + 0x341807e8 EXTI13_IRQHandler + 0x341807e8 TIM1_CC_IRQHandler + 0x341807e8 XSPI1_IRQHandler + 0x341807e8 TIM10_IRQHandler + 0x341807e8 JPEG_IRQHandler + 0x341807e8 TAMP_IRQHandler + 0x341807e8 CACHE_ECC_IRQHandler + 0x341807e8 TIM6_IRQHandler + 0x341807e8 CSI_IRQHandler + 0x341807e8 EXTI12_IRQHandler + 0x341807e8 GFXTIM_IRQHandler + 0x341807e8 EXTI3_IRQHandler + 0x341807e8 LPTIM4_IRQHandler + 0x341807e8 GPDMA1_Channel5_IRQHandler + 0x341807e8 EXTI8_IRQHandler + 0x341807e8 LPTIM2_IRQHandler + 0x341807e8 GFXMMU_IRQHandler + 0x341807e8 LTDC_LO_ERR_IRQHandler + 0x341807e8 I2C3_ER_IRQHandler + 0x341807e8 RIFSC_TAMPER_IRQHandler + 0x341807e8 USART10_IRQHandler + 0x341807e8 MDF1_FLT2_IRQHandler + 0x341807e8 LPTIM3_IRQHandler + 0x341807e8 SAI2_A_IRQHandler + 0x341807e8 EXTI0_IRQHandler + 0x341807e8 HPDMA1_Channel9_IRQHandler + 0x341807e8 I2C2_EV_IRQHandler + 0x341807e8 GPU2D_IRQHandler + 0x341807e8 FPU_IRQHandler + 0x341807e8 GPDMA1_Channel3_IRQHandler + 0x341807e8 GPDMA1_Channel7_IRQHandler + 0x341807e8 MDF1_FLT4_IRQHandler + 0x341807e8 FDCAN1_IT1_IRQHandler + 0x341807e8 HPDMA1_Channel3_IRQHandler + 0x341807e8 ADC1_2_IRQHandler + 0x341807e8 GPDMA1_Channel9_IRQHandler + 0x341807e8 SPI1_IRQHandler + 0x341807e8 CACHEAXI_IRQHandler + 0x341807e8 SAI1_B_IRQHandler + 0x341807e8 GPDMA1_Channel2_IRQHandler + 0x341807e8 PAHB_ERR_IRQHandler + 0x341807e8 TIM8_UP_IRQHandler + 0x341807e8 RCC_S_IRQHandler + 0x341807e8 MDF1_FLT1_IRQHandler + 0x341807e8 LTDC_UP_IRQHandler + 0x341807e8 LOCKUP_IRQHandler + 0x341807e8 PKA_IRQHandler + 0x341807e8 USART6_IRQHandler + 0x341807e8 HPDMA1_Channel2_IRQHandler + 0x341807e8 MDF1_FLT5_IRQHandler + 0x341807e8 MCE4_IRQHandler + 0x341807e8 I3C2_ER_IRQHandler + 0x341807e8 EXTI15_IRQHandler + 0x341807e8 TIM17_IRQHandler + 0x341807e8 USART3_IRQHandler + 0x341807e8 HPDMA1_Channel6_IRQHandler + 0x341807e8 CRYP_IRQHandler + 0x341807e8 RTC_IRQHandler + 0x341807e8 XSPI2_IRQHandler + 0x341807e8 EXTI9_IRQHandler + 0x341807e8 IAC_IRQHandler + 0x341807e8 HPDMA1_Channel0_IRQHandler + 0x341807e8 LPTIM5_IRQHandler + 0x341807e8 HPDMA1_Channel1_IRQHandler + 0x341807e8 UART5_IRQHandler + 0x341807e8 TIM4_IRQHandler + 0x341807e8 NPU3_IRQHandler + 0x341807e8 I3C2_EV_IRQHandler + 0x341807e8 I2C1_EV_IRQHandler + 0x341807e8 FDCAN_CU_IRQHandler + 0x341807e8 GPDMA1_Channel12_IRQHandler + 0x341807e8 HPDMA1_Channel7_IRQHandler + 0x341807e8 GPDMA1_Channel1_IRQHandler + 0x341807e8 TIM16_IRQHandler + 0x341807e8 GPDMA1_Channel15_IRQHandler + 0x341807e8 UART4_IRQHandler + 0x341807e8 TCM_ECC_IRQHandler + 0x341807e8 TIM3_IRQHandler + 0x341807e8 RCC_IRQHandler + 0x341807e8 UART9_IRQHandler + 0x341807e8 NPU1_IRQHandler + 0x341807e8 SAI2_B_IRQHandler + 0x341807e8 Default_Handler + 0x341807e8 GPDMA1_Channel8_IRQHandler + 0x341807e8 HPDMA1_Channel8_IRQHandler + 0x341807e8 TIM18_IRQHandler + 0x341807e8 TIM14_IRQHandler + 0x341807e8 TIM13_IRQHandler + 0x341807e8 CTI_INT1_IRQHandler + 0x341807e8 GPDMA1_Channel11_IRQHandler + 0x341807e8 GPU2D_ER_IRQHandler + 0x341807e8 SPI5_IRQHandler + 0x341807e8 TIM12_IRQHandler + 0x341807e8 TIM7_IRQHandler + 0x341807e8 FDCAN3_IT1_IRQHandler + 0x341807e8 HPDMA1_Channel10_IRQHandler + 0x341807e8 SDMMC1_IRQHandler + 0x341807e8 SAES_IRQHandler + 0x341807e8 TIM5_IRQHandler + 0x341807e8 UCPD1_IRQHandler + 0x341807e8 GPDMA1_Channel0_IRQHandler + 0x341807e8 I3C1_EV_IRQHandler + 0x341807e8 HPDMA1_Channel5_IRQHandler + 0x341807e8 TIM15_IRQHandler + 0x341807e8 I2C3_EV_IRQHandler + 0x341807e8 HPDMA1_Channel4_IRQHandler + 0x341807e8 HPDMA1_Channel15_IRQHandler + 0x341807e8 TIM9_IRQHandler + 0x341807e8 ETH1_IRQHandler + 0x341807e8 USB1_OTG_HS_IRQHandler + 0x341807e8 PVD_PVM_IRQHandler + 0x341807e8 SPI2_IRQHandler + 0x341807e8 TIM1_TRG_CCU_IRQHandler + 0x341807e8 HPDMA1_Channel11_IRQHandler + 0x341807e8 EXTI14_IRQHandler + 0x341807e8 EXTI11_IRQHandler + 0x341807e8 VENC_IRQHandler + 0x341807e8 GPDMA1_Channel14_IRQHandler + 0x341807e8 EXTI4_IRQHandler + 0x341807e8 RTC_S_IRQHandler + 0x341807e8 GPDMA1_Channel13_IRQHandler + 0x341807e8 RNG_IRQHandler + 0x341807e8 XSPI3_IRQHandler + 0x341807e8 FDCAN2_IT1_IRQHandler + 0x341807e8 TIM1_UP_IRQHandler + 0x341807e8 NPU0_IRQHandler + 0x341807e8 BCK_ECC_IRQHandler + 0x341807e8 WWDG_IRQHandler + 0x341807e8 SPI6_IRQHandler + 0x341807e8 MDIOS_IRQHandler + 0x341807e8 I2C4_EV_IRQHandler + 0x341807e8 FDCAN2_IT0_IRQHandler + 0x341807e8 IWDG_IRQHandler + 0x341807e8 HPDMA1_Channel14_IRQHandler + 0x341807e8 LPUART1_IRQHandler + 0x341807e8 FDCAN1_IT0_IRQHandler + 0x341807e8 MDF1_FLT0_IRQHandler + 0x341807e8 TIM2_IRQHandler + 0x341807e8 MCE3_IRQHandler + 0x341807e8 GPDMA1_Channel4_IRQHandler + 0x341807e8 EXTI7_IRQHandler + 0x341807e8 DMA2D_IRQHandler + 0x341807e8 TIM1_BRK_IRQHandler + 0x341807e8 EXTI1_IRQHandler + 0x341807e8 SDMMC2_IRQHandler + 0x341807e8 TIM11_IRQHandler + 0x341807e8 LTDC_UP_ERR_IRQHandler + 0x341807e8 UART7_IRQHandler + 0x341807e8 DTS_IRQHandler + 0x341807e8 MDF1_FLT3_IRQHandler + 0x341807e8 USART2_IRQHandler + 0x341807e8 GPDMA1_Channel6_IRQHandler + 0x341807e8 ADF1_FLT0_IRQHandler + 0x341807e8 I2C2_ER_IRQHandler + 0x341807e8 MCE1_IRQHandler + 0x341807e8 SPDIFRX_IRQHandler + 0x341807e8 TIM8_BRK_IRQHandler + 0x341807e8 HPDMA1_Channel12_IRQHandler + 0x341807e8 USART1_IRQHandler + 0x341807e8 EXTI10_IRQHandler + 0x341807e8 SPI3_IRQHandler + 0x341807e8 WAKEUP_PIN_IRQHandler + 0x341807e8 DCMIPP_IRQHandler + 0x341807e8 I2C1_ER_IRQHandler + 0x341807e8 FMC_IRQHandler + 0x341807e8 EXTI6_IRQHandler + 0x341807e8 LPTIM1_IRQHandler + 0x341807e8 DCMI_PSSI_IRQHandler + 0x341807e8 TIM8_TRG_CCU_IRQHandler + 0x341807e8 I2C4_ER_IRQHandler + 0x341807e8 GPDMA1_Channel10_IRQHandler + 0x341807e8 ICACHE_IRQHandler + 0x341807e8 HASH_IRQHandler + *fill* 0x341807ea 0x2 + .text.LL_AHB4_GRP1_EnableClock + 0x341807ec 0x2c ./Application/User/gpio.o + .text.MX_GPIO_Init + 0x34180818 0x1dc ./Application/User/gpio.o + 0x34180818 MX_GPIO_Init + .text.main 0x341809f4 0x108 ./Application/User/main.o + 0x341809f4 main + .text.SystemClock_Config + 0x34180afc 0x158 ./Application/User/main.o + 0x34180afc SystemClock_Config + .text.Error_Handler + 0x34180c54 0xc ./Application/User/main.o + 0x34180c54 Error_Handler + .text.assert_failed + 0x34180c60 0x16 ./Application/User/main.o + 0x34180c60 assert_failed + .text.HAL_MspInit + 0x34180c76 0xc ./Application/User/stm32n6xx_hal_msp.o + 0x34180c76 HAL_MspInit + .text.NMI_Handler + 0x34180c82 0x8 ./Application/User/stm32n6xx_it.o + 0x34180c82 NMI_Handler + .text.HardFault_Handler + 0x34180c8a 0x8 ./Application/User/stm32n6xx_it.o + 0x34180c8a HardFault_Handler + .text.MemManage_Handler + 0x34180c92 0x8 ./Application/User/stm32n6xx_it.o + 0x34180c92 MemManage_Handler + .text.BusFault_Handler + 0x34180c9a 0x8 ./Application/User/stm32n6xx_it.o + 0x34180c9a BusFault_Handler + .text.UsageFault_Handler + 0x34180ca2 0x8 ./Application/User/stm32n6xx_it.o + 0x34180ca2 UsageFault_Handler + .text.SecureFault_Handler + 0x34180caa 0x8 ./Application/User/stm32n6xx_it.o + 0x34180caa SecureFault_Handler + .text.SVC_Handler + 0x34180cb2 0xe ./Application/User/stm32n6xx_it.o + 0x34180cb2 SVC_Handler + .text.DebugMon_Handler + 0x34180cc0 0xe ./Application/User/stm32n6xx_it.o + 0x34180cc0 DebugMon_Handler + .text.PendSV_Handler + 0x34180cce 0xe ./Application/User/stm32n6xx_it.o + 0x34180cce PendSV_Handler + .text.SysTick_Handler + 0x34180cdc 0xc ./Application/User/stm32n6xx_it.o + 0x34180cdc SysTick_Handler + .text.LL_AHB4_GRP1_EnableClock + 0x34180ce8 0x2c ./Application/User/xspi.o + .text.LL_AHB5_GRP1_EnableClock + 0x34180d14 0x2c ./Application/User/xspi.o + .text.MX_XSPI2_Init + 0x34180d40 0xb8 ./Application/User/xspi.o + 0x34180d40 MX_XSPI2_Init + .text.HAL_XSPI_MspInit + 0x34180df8 0xf0 ./Application/User/xspi.o + 0x34180df8 HAL_XSPI_MspInit + .text.SystemInit + 0x34180ee8 0x218 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + 0x34180ee8 SystemInit + .text.SystemCoreClockUpdate + 0x34181100 0x350 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + 0x34181100 SystemCoreClockUpdate + .text.SECURE_SystemCoreClockUpdate + 0x34181450 0x2c ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + 0x34181450 __acle_se_SECURE_SystemCoreClockUpdate + .text.HAL_Init + 0x3418147c 0x28 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x3418147c HAL_Init + .text.HAL_InitTick + 0x341814a4 0x6c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x341814a4 HAL_InitTick + .text.HAL_IncTick + 0x34181510 0x28 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x34181510 HAL_IncTick + .text.HAL_GetTick + 0x34181538 0x18 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x34181538 HAL_GetTick + .text.HAL_Delay + 0x34181550 0x48 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x34181550 HAL_Delay + .text.__NVIC_SetPriorityGrouping + 0x34181598 0x48 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .text.__NVIC_GetPriorityGrouping + 0x341815e0 0x1c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .text.__NVIC_SetPriority + 0x341815fc 0x54 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .text.NVIC_EncodePriority + 0x34181650 0x66 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + *fill* 0x341816b6 0x2 + .text.SysTick_Config + 0x341816b8 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x341816fc 0x40 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + 0x341816fc HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x3418173c 0xb4 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + 0x3418173c HAL_NVIC_SetPriority + .text.HAL_SYSTICK_Config + 0x341817f0 0x18 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + 0x341817f0 HAL_SYSTICK_Config + .text.HAL_GPIO_Init + 0x34181808 0x6c0 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + 0x34181808 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x34181ec8 0x58 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + 0x34181ec8 HAL_GPIO_WritePin + .text.HAL_PWREx_ConfigSupply + 0x34181f20 0x68 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + 0x34181f20 HAL_PWREx_ConfigSupply + .text.HAL_PWREx_ControlVoltageScaling + 0x34181f88 0x68 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + 0x34181f88 HAL_PWREx_ControlVoltageScaling + .text.HAL_PWREx_EnableVddIO3 + 0x34181ff0 0x20 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + 0x34181ff0 HAL_PWREx_EnableVddIO3 + .text.LL_RCC_HSE_IsReady + 0x34182010 0x24 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .text.LL_RCC_HSI_Enable + 0x34182034 0x1c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .text.LL_RCC_HSI_Disable + 0x34182050 0x20 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .text.LL_RCC_HSI_IsReady + 0x34182070 0x24 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .text.LL_RCC_HSI_SetDivider + 0x34182094 0x28 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .text.LL_RCC_HSI_GetDivider + 0x341820bc 0x1c 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./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + .text.memset 0x3418c308 0x10 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a(libc_a-memset.o) + 0x3418c308 memset + .text.__libc_init_array + 0x3418c318 0x48 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a(libc_a-init.o) + 0x3418c318 __libc_init_array + *(.glue_7) + .glue_7 0x3418c360 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x3418c360 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x3418c360 0x0 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + *(.RamFunc) + *(.RamFunc*) + *(.init) + .init 0x3418c360 0x4 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crti.o + 0x3418c360 _init + .init 0x3418c364 0x8 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtn.o + *(.fini) + .fini 0x3418c36c 0x4 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crti.o + 0x3418c36c _fini + .fini 0x3418c370 0x8 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtn.o + 0x3418c378 . = ALIGN (0x4) + 0x3418c378 _etext = . + +.vfp11_veneer 0x3418c378 0x0 + .vfp11_veneer 0x3418c378 0x0 linker stubs + +.v4_bx 0x3418c378 0x0 + .v4_bx 0x3418c378 0x0 linker stubs + +.iplt 0x3418c378 0x0 + .iplt 0x3418c378 0x0 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + +.rodata 0x3418c378 0x288 + 0x3418c378 . = ALIGN (0x4) + *(.rodata) + .rodata 0x3418c378 0x6c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .rodata 0x3418c3e4 0x6a ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + *fill* 0x3418c44e 0x2 + .rodata 0x3418c450 0x6c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .rodata 0x3418c4bc 0x69 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + *fill* 0x3418c525 0x3 + .rodata 0x3418c528 0x6c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .rodata 0x3418c594 0x6a ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + *(.rodata*) + 0x3418c600 . = ALIGN (0x4) + *fill* 0x3418c5fe 0x2 + +.ARM.extab 0x3418c600 0x0 + 0x3418c600 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x3418c600 . = ALIGN (0x4) + +.ARM 0x3418c600 0x0 + 0x3418c600 . = ALIGN (0x4) + 0x3418c600 __exidx_start = . + *(.ARM.exidx*) + 0x3418c600 __exidx_end = . + 0x3418c600 . = ALIGN (0x4) + +.preinit_array 0x3418c600 0x0 + 0x3418c600 . = ALIGN (0x4) + 0x3418c600 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x3418c600 PROVIDE (__preinit_array_end = .) + 0x3418c600 . = ALIGN (0x4) + +.init_array 0x3418c600 0x4 + 0x3418c600 . = ALIGN (0x4) + 0x3418c600 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x3418c600 0x4 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + 0x3418c604 PROVIDE (__init_array_end = .) + 0x3418c604 . = ALIGN (0x4) + +.fini_array 0x3418c604 0x4 + 0x3418c604 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x3418c604 0x4 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x3418c608 . = ALIGN (0x4) + 0x3418c608 _sidata = LOADADDR (.data) + +.rel.dyn 0x3418c608 0x0 + .rel.iplt 0x3418c608 0x0 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + +.data 0x341c0000 0xc load address 0x3418c608 + 0x341c0000 . = ALIGN (0x4) + 0x341c0000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x341c0000 0x4 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + 0x341c0000 SystemCoreClock + .data.uwTickPrio + 0x341c0004 0x4 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x341c0004 uwTickPrio + .data.uwTickFreq + 0x341c0008 0x1 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x341c0008 uwTickFreq + 0x341c000c . = ALIGN (0x4) + *fill* 0x341c0009 0x3 + 0x341c000c _edata = . + +.igot.plt 0x341c000c 0x0 load address 0x3418c614 + .igot.plt 0x341c000c 0x0 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C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + *(.bss*) + .bss.hxspi2 0x341c002c 0x64 ./Application/User/xspi.o + 0x341c002c hxspi2 + .bss.uwTick 0x341c0090 0x4 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + 0x341c0090 uwTick + *(COMMON) + 0x341c0094 . = ALIGN (0x4) + 0x341c0094 _ebss = . + 0x341c0094 __bss_end__ = _ebss + +._user_heap_stack + 0x341c0094 0xa04 + 0x341c0098 . = ALIGN (0x8) + *fill* 0x341c0094 0x4 + [!provide] PROVIDE (end = .) + 0x341c0098 PROVIDE (_end = .) + 0x341c0298 . = (. + _Min_Heap_Size) + *fill* 0x341c0098 0x200 + 0x341c0a98 . = (. + _Min_Stack_Size) + *fill* 0x341c0298 0x800 + 0x341c0a98 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x3a + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x24 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crti.o + .ARM.attributes + 0x00000024 0x36 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtbegin.o + .ARM.attributes + 0x0000005a 0x22 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + .ARM.attributes + 0x0000007c 0x3e ./Application/User/gpio.o + .ARM.attributes + 0x000000ba 0x3e ./Application/User/main.o + .ARM.attributes + 0x000000f8 0x3e ./Application/User/stm32n6xx_hal_msp.o + .ARM.attributes + 0x00000136 0x3e ./Application/User/stm32n6xx_it.o + .ARM.attributes + 0x00000174 0x3e ./Application/User/xspi.o + .ARM.attributes + 0x000001b2 0x3e ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .ARM.attributes + 0x000001f0 0x3e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .ARM.attributes + 0x0000022e 0x3e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .ARM.attributes + 0x0000026c 0x3e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .ARM.attributes + 0x000002aa 0x3e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .ARM.attributes + 0x000002e8 0x3e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .ARM.attributes + 0x00000326 0x3e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .ARM.attributes + 0x00000364 0x3e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + .ARM.attributes + 0x000003a2 0x36 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x000003d8 0x36 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x0000040e 0x24 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard/crtn.o +OUTPUT(blto2_FSBL.elf elf32-littlearm) +LOAD linker stubs +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libm.a +LOAD C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v8-m.main+dp/hard\libgcc.a + +.debug_line 0x00000000 0x14497 + .debug_line 0x00000000 0x7e ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + .debug_line 0x0000007e 0x9a7 ./Application/User/gpio.o + .debug_line 0x00000a25 0xafa ./Application/User/main.o + .debug_line 0x0000151f 0x8f3 ./Application/User/stm32n6xx_hal_msp.o + .debug_line 0x00001e12 0x9b8 ./Application/User/stm32n6xx_it.o + .debug_line 0x000027ca 0xa0c ./Application/User/xspi.o + .debug_line 0x000031d6 0xc0a ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_line 0x00003de0 0x18b5 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_line 0x00005695 0x132a ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_line 0x000069bf 0x1901 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_line 0x000082c0 0x14f1 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_line 0x000097b1 0x28c1 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_line 0x0000c072 0x5f44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_line 0x00011fb6 0x24e1 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.debug_line_str + 0x00000000 0x81 + .debug_line_str + 0x00000000 0x81 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + +.debug_info 0x00000000 0x13700 + .debug_info 0x00000000 0x30 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + .debug_info 0x00000030 0x11e1 ./Application/User/gpio.o + .debug_info 0x00001211 0xa27 ./Application/User/main.o + .debug_info 0x00001c38 0xa8 ./Application/User/stm32n6xx_hal_msp.o + .debug_info 0x00001ce0 0x138 ./Application/User/stm32n6xx_it.o + .debug_info 0x00001e18 0x22fb ./Application/User/xspi.o + .debug_info 0x00004113 0x1a83 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_info 0x00005b96 0x2824 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_info 0x000083ba 0x149b ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_info 0x00009855 0xb0e ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_info 0x0000a363 0xd22 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_info 0x0000b085 0x217d ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_info 0x0000d202 0x3876 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_info 0x00010a78 0x2c88 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.debug_abbrev 0x00000000 0x1cff + .debug_abbrev 0x00000000 0x24 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + .debug_abbrev 0x00000024 0x1bb ./Application/User/gpio.o + .debug_abbrev 0x000001df 0x267 ./Application/User/main.o + .debug_abbrev 0x00000446 0x58 ./Application/User/stm32n6xx_hal_msp.o + .debug_abbrev 0x0000049e 0x73 ./Application/User/stm32n6xx_it.o + .debug_abbrev 0x00000511 0x25b ./Application/User/xspi.o + .debug_abbrev 0x0000076c 0x164 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_abbrev 0x000008d0 0x2bd ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_abbrev 0x00000b8d 0x37f ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_abbrev 0x00000f0c 0x26c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_abbrev 0x00001178 0x266 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_abbrev 0x000013de 0x34d ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_abbrev 0x0000172b 0x321 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_abbrev 0x00001a4c 0x2b3 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.debug_aranges 0x00000000 0x1578 + .debug_aranges + 0x00000000 0x28 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + .debug_aranges + 0x00000028 0x28 ./Application/User/gpio.o + .debug_aranges + 0x00000050 0x38 ./Application/User/main.o + .debug_aranges + 0x00000088 0x20 ./Application/User/stm32n6xx_hal_msp.o + .debug_aranges + 0x000000a8 0x68 ./Application/User/stm32n6xx_it.o + .debug_aranges + 0x00000110 0x48 ./Application/User/xspi.o + .debug_aranges + 0x00000158 0x30 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_aranges + 0x00000188 0x3d0 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_aranges + 0x00000558 0x178 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_aranges + 0x000006d0 0xa8 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_aranges + 0x00000778 0x260 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_aranges + 0x000009d8 0x2a0 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_aranges + 0x00000c78 0x758 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_aranges + 0x000013d0 0x1a8 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.debug_str 0x00000000 0x2078d6 + .debug_str 0x00000000 0x2078d6 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + 0x9d (size before relaxing) + .debug_str 0x002078d6 0x201020 ./Application/User/gpio.o + .debug_str 0x002078d6 0x2009bd ./Application/User/main.o + .debug_str 0x002078d6 0x200468 ./Application/User/stm32n6xx_hal_msp.o + .debug_str 0x002078d6 0x200502 ./Application/User/stm32n6xx_it.o + .debug_str 0x002078d6 0x201b7e ./Application/User/xspi.o + .debug_str 0x002078d6 0x20126f ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_str 0x002078d6 0x202b73 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_str 0x002078d6 0x201635 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_str 0x002078d6 0x200890 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_str 0x002078d6 0x2010ca ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_str 0x002078d6 0x201db3 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_str 0x002078d6 0x202da1 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_str 0x002078d6 0x201eff ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.debug_rnglists + 0x00000000 0x1042 + .debug_rnglists + 0x00000000 0x19 ./Application/Startup/startup_stm32n657x0hxq_fsbl.o + .debug_rnglists + 0x00000019 0x1a ./Application/User/gpio.o + .debug_rnglists + 0x00000033 0x27 ./Application/User/main.o + .debug_rnglists + 0x0000005a 0x13 ./Application/User/stm32n6xx_hal_msp.o + .debug_rnglists + 0x0000006d 0x49 ./Application/User/stm32n6xx_it.o + .debug_rnglists + 0x000000b6 0x33 ./Application/User/xspi.o + .debug_rnglists + 0x000000e9 0x21 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_rnglists + 0x0000010a 0x2db ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_rnglists + 0x000003e5 0x11c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_rnglists + 0x00000501 0x84 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_rnglists + 0x00000585 0x1c9 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_rnglists + 0x0000074e 0x201 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_rnglists + 0x0000094f 0x5a2 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_rnglists + 0x00000ef1 0x151 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.debug_macro 0x00000000 0x5189f + .debug_macro 0x00000000 0x2aa ./Application/User/gpio.o + .debug_macro 0x000002aa 0xb5c ./Application/User/gpio.o + .debug_macro 0x00000e06 0x16 ./Application/User/gpio.o + .debug_macro 0x00000e1c 0x1e1 ./Application/User/gpio.o + .debug_macro 0x00000ffd 0x190 ./Application/User/gpio.o + .debug_macro 0x0000118d 0x63 ./Application/User/gpio.o + .debug_macro 0x000011f0 0x2e ./Application/User/gpio.o + .debug_macro 0x0000121e 0x6c ./Application/User/gpio.o + .debug_macro 0x0000128a 0x22 ./Application/User/gpio.o + .debug_macro 0x000012ac 0x8e ./Application/User/gpio.o + .debug_macro 0x0000133a 0x51 ./Application/User/gpio.o + .debug_macro 0x0000138b 0x103 ./Application/User/gpio.o + .debug_macro 0x0000148e 0x6a ./Application/User/gpio.o + .debug_macro 0x000014f8 0x1df ./Application/User/gpio.o + .debug_macro 0x000016d7 0x2e ./Application/User/gpio.o + .debug_macro 0x00001705 0x17 ./Application/User/gpio.o + .debug_macro 0x0000171c 0x58 ./Application/User/gpio.o + .debug_macro 0x00001774 0x26d ./Application/User/gpio.o + .debug_macro 0x000019e1 0x3a ./Application/User/gpio.o + .debug_macro 0x00001a1b 0x2f0c ./Application/User/gpio.o + .debug_macro 0x00004927 0x130 ./Application/User/gpio.o + .debug_macro 0x00004a57 0x344 ./Application/User/gpio.o + .debug_macro 0x00004d9b 0x146 ./Application/User/gpio.o + .debug_macro 0x00004ee1 0x22 ./Application/User/gpio.o + .debug_macro 0x00004f03 0x3e927 ./Application/User/gpio.o + .debug_macro 0x0004382a 0x6c ./Application/User/gpio.o + .debug_macro 0x00043896 0x349b ./Application/User/gpio.o + .debug_macro 0x00046d31 0x61 ./Application/User/gpio.o + .debug_macro 0x00046d92 0x29 ./Application/User/gpio.o + .debug_macro 0x00046dbb 0x43 ./Application/User/gpio.o + .debug_macro 0x00046dfe 0x34 ./Application/User/gpio.o + .debug_macro 0x00046e32 0x364 ./Application/User/gpio.o + .debug_macro 0x00047196 0x16 ./Application/User/gpio.o + .debug_macro 0x000471ac 0x4a ./Application/User/gpio.o + .debug_macro 0x000471f6 0x34 ./Application/User/gpio.o + .debug_macro 0x0004722a 0x10 ./Application/User/gpio.o + .debug_macro 0x0004723a 0x58 ./Application/User/gpio.o + .debug_macro 0x00047292 0x8e ./Application/User/gpio.o + .debug_macro 0x00047320 0x1c ./Application/User/gpio.o + .debug_macro 0x0004733c 0x17e ./Application/User/gpio.o + .debug_macro 0x000474ba 0x19b ./Application/User/gpio.o + .debug_macro 0x00047655 0x72 ./Application/User/gpio.o + .debug_macro 0x000476c7 0x47a ./Application/User/gpio.o + .debug_macro 0x00047b41 0x10f7 ./Application/User/gpio.o + .debug_macro 0x00048c38 0x27e2 ./Application/User/gpio.o + .debug_macro 0x0004b41a 0xfd4 ./Application/User/gpio.o + .debug_macro 0x0004c3ee 0x1af ./Application/User/gpio.o + .debug_macro 0x0004c59d 0x2c9 ./Application/User/gpio.o + .debug_macro 0x0004c866 0x2c4 ./Application/User/gpio.o + .debug_macro 0x0004cb2a 0xa36 ./Application/User/gpio.o + .debug_macro 0x0004d560 0x7b2 ./Application/User/gpio.o + .debug_macro 0x0004dd12 0xeb ./Application/User/gpio.o + .debug_macro 0x0004ddfd 0x216 ./Application/User/gpio.o + .debug_macro 0x0004e013 0x36b ./Application/User/gpio.o + .debug_macro 0x0004e37e 0x303 ./Application/User/gpio.o + .debug_macro 0x0004e681 0x46a ./Application/User/gpio.o + .debug_macro 0x0004eaeb 0x72d ./Application/User/gpio.o + .debug_macro 0x0004f218 0x5fb ./Application/User/gpio.o + .debug_macro 0x0004f813 0x10 ./Application/User/gpio.o + .debug_macro 0x0004f823 0x2b8 ./Application/User/main.o + .debug_macro 0x0004fadb 0x2a0 ./Application/User/stm32n6xx_hal_msp.o + .debug_macro 0x0004fd7b 0x2aa ./Application/User/stm32n6xx_it.o + .debug_macro 0x00050025 0x2aa ./Application/User/xspi.o + .debug_macro 0x000502cf 0x2a5 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_macro 0x00050574 0x298 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_macro 0x0005080c 0x293 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_macro 0x00050a9f 0x299 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_macro 0x00050d38 0x2e0 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_macro 0x00051018 0x31c ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_macro 0x00051334 0x292 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_macro 0x000515c6 0x2d9 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Application/User/gpio.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Application/User/main.o + .comment 0x00000043 0x44 ./Application/User/stm32n6xx_hal_msp.o + .comment 0x00000043 0x44 ./Application/User/stm32n6xx_it.o + .comment 0x00000043 0x44 ./Application/User/xspi.o + .comment 0x00000043 0x44 ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .comment 0x00000043 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + +.debug_frame 0x00000000 0x51c0 + .debug_frame 0x00000000 0x58 ./Application/User/gpio.o + .debug_frame 0x00000058 0x94 ./Application/User/main.o + .debug_frame 0x000000ec 0x2c ./Application/User/stm32n6xx_hal_msp.o + .debug_frame 0x00000118 0x110 ./Application/User/stm32n6xx_it.o + .debug_frame 0x00000228 0xec ./Application/User/xspi.o + .debug_frame 0x00000314 0x7c ./Drivers/CMSIS/system_stm32n6xx_fsbl.o + .debug_frame 0x00000390 0xeac ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal.o + .debug_frame 0x0000123c 0x5f4 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_cortex.o + .debug_frame 0x00001830 0x2a4 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_gpio.o + .debug_frame 0x00001ad4 0x878 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_pwr_ex.o + .debug_frame 0x0000234c 0x9d4 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc.o + .debug_frame 0x00002d20 0x1cfc ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_rcc_ex.o + .debug_frame 0x00004a1c 0x758 ./Drivers/STM32N6xx_HAL_Driver/stm32n6xx_hal_xspi.o + .debug_frame 0x00005174 0x20 C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a(libc_a-memset.o) + .debug_frame 0x00005194 0x2c C:/ST/STM32CubeIDE_2.1.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard\libc_nano.a(libc_a-init.o) Index: trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/STM32N657X0HXQ_AXISRAM2_fsbl.ld =================================================================== --- trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/STM32N657X0HXQ_AXISRAM2_fsbl.ld (revision 16) +++ trunk/firmware/FSBL/CubeMX/STM32CubeIDE/FSBL/STM32N657X0HXQ_AXISRAM2_fsbl.ld (revision 16) @@ -0,0 +1,203 @@ +/* +****************************************************************************** +** +** @file : STM32N6XX_AXISRAM2_fsbl.ld +** +** @author : GPM Application Team +** +** @brief : Linker script for STM32N6XX Device from STM32N6 series +** 512 KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2026 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + ROM (xrw) : ORIGIN = 0x34180400, LENGTH = 255K + RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} Index: trunk/firmware/FSBL/CubeMX/blto2_FSBL.ioc =================================================================== --- trunk/firmware/FSBL/CubeMX/blto2_FSBL.ioc (revision 16) +++ trunk/firmware/FSBL/CubeMX/blto2_FSBL.ioc (revision 16) @@ -0,0 +1,879 @@ +#MicroXplorer Configuration settings - do not modify +Appli.IPs=CORTEX_M55_S,GPDMA1,HPDMA1,LINKEDLIST,RCC,GPIO,NVIC1\:I,RIF,SAU +CAD.formats= +CAD.pinconfig= +CAD.provider= +CORTEX_M55_FSBL.CPU_DCache=Enabled +CORTEX_M55_FSBL.CPU_ICache=Enabled +CORTEX_M55_FSBL.IPParameters=CPU_ICache,CPU_DCache +CORTEX_M55_S.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ALL_RW +CORTEX_M55_S.Attributes0=MPU_ATTRIBUTES_NUMBER0 +CORTEX_M55_S.BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings=__NON_CACHEABLE_SECTION_BEGIN +CORTEX_M55_S.CPU_DCache=Enabled +CORTEX_M55_S.CPU_ICache=Enabled +CORTEX_M55_S.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE +CORTEX_M55_S.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Attributes0,BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings,LimitAddress-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings +CORTEX_M55_S.LimitAddress-Cortex_Memory_Protection_Unit_Region0_Settings=__NON_CACHEABLE_SECTION_END +CORTEX_M55_S.MPU_Control=MPU_HFNMI_PRIVDEF +ExtMemLoader.IPs=EXTMEM_LOADER,EXTMEM_MANAGER,RCC\:I,GPIO,TIM6 +FSBL.IPs=CORTEX_M55_FSBL,GPDMA1\:I,HDP,HPDMA1\:I,LINKEDLIST,RCC,GPIO\:I,NVIC\:I,XSPIM,XSPI2 +FSBL.Pins=PG0 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32N657X0H3Q +Mcu.Context0=FSBL +Mcu.Context1=Appli +Mcu.Context2=ExtMemLoader +Mcu.ContextNb=3 +Mcu.ContextProject=FullSecure +Mcu.Family=STM32N6 +Mcu.IP0=CORTEX_M55_FSBL +Mcu.IP1=CORTEX_M55_S +Mcu.IP2=NVIC1 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RIF +Mcu.IP6=XSPI2 +Mcu.IP7=XSPIM +Mcu.IPNb=8 +Mcu.Name=STM32N657X0HxQ +Mcu.Package=VFBGA264 +Mcu.Pin0=PN4 +Mcu.Pin1=PN6 +Mcu.Pin10=PN2 +Mcu.Pin11=PA13(JTMS/SWDIO) +Mcu.Pin12=PN10 +Mcu.Pin13=PN11 +Mcu.Pin14=VP_RIF_VS_RIF1 +Mcu.Pin15=VP_XSPI2_VS_octo +Mcu.Pin16=VP_XSPIM_VS_IO +Mcu.Pin2=PN8 +Mcu.Pin3=PN0 +Mcu.Pin4=PG0 +Mcu.Pin5=PN3 +Mcu.Pin6=PN5 +Mcu.Pin7=PN1 +Mcu.Pin8=PA14(JTCK/SWCLK) +Mcu.Pin9=PN9 +Mcu.PinsNb=17 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32N657X0HxQ +MxCube.Version=6.18.1 +MxDb.Version=DB.6.0.181 +NVIC.BFHFNMINS=0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PRIS=0 +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.BFHFNMINS=0 +NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.ForceEnableDMAVector=true +NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PRIS=0 +NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA13(JTMS/SWDIO).Locked=true +PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO +PA14(JTCK/SWCLK).Locked=true +PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK +PCC.Bar.Display=Horizontal Bar +PCC.Checker=false +PCC.Display=Plot\: All Steps +PCC.Line=STM32N6x7 +PCC.MCU=STM32N657X0HxQ +PCC.PartNumber=STM32N657X0HxQ +PCC.SequenceTime=1.0 ms +PCC.SequenceTime.Unit=ms +PCC.Series=STM32N6 +PCC.Temperature=25 +PCC.Vdd=1.8 +PG0.ContextOwner=FSBL +PG0.GPIOParameters=GPIO_Label,PinAttribute +PG0.GPIO_Label=GREEN_LED +PG0.Locked=true +PG0.PinAttribute=FSBL +PG0.Signal=GPIO_Output +PN0.GPIOParameters=PinAttribute +PN0.Mode=XSPI2_Port2Octo +PN0.PinAttribute=FSBL +PN0.Signal=XSPIM_P2_DQS0 +PN1.GPIOParameters=PinAttribute +PN1.Mode=XSPI2_NCS1_Port2 +PN1.PinAttribute=FSBL +PN1.Signal=XSPIM_P2_NCS1 +PN10.GPIOParameters=PinAttribute +PN10.Mode=XSPI2_Port2Octo +PN10.PinAttribute=FSBL +PN10.Signal=XSPIM_P2_IO6 +PN11.GPIOParameters=PinAttribute +PN11.Mode=XSPI2_Port2Octo +PN11.PinAttribute=FSBL +PN11.Signal=XSPIM_P2_IO7 +PN2.GPIOParameters=PinAttribute +PN2.Mode=XSPI2_Port2Octo +PN2.PinAttribute=FSBL +PN2.Signal=XSPIM_P2_IO0 +PN3.GPIOParameters=PinAttribute +PN3.Mode=XSPI2_Port2Octo +PN3.PinAttribute=FSBL +PN3.Signal=XSPIM_P2_IO1 +PN4.GPIOParameters=PinAttribute +PN4.Mode=XSPI2_Port2Octo +PN4.PinAttribute=FSBL +PN4.Signal=XSPIM_P2_IO2 +PN5.GPIOParameters=PinAttribute +PN5.Mode=XSPI2_Port2Octo +PN5.PinAttribute=FSBL +PN5.Signal=XSPIM_P2_IO3 +PN6.GPIOParameters=PinAttribute +PN6.Mode=XSPI2_Port2Octo +PN6.PinAttribute=FSBL +PN6.Signal=XSPIM_P2_CLK +PN8.GPIOParameters=PinAttribute +PN8.Mode=XSPI2_Port2Octo +PN8.PinAttribute=FSBL +PN8.Signal=XSPIM_P2_IO4 +PN9.GPIOParameters=PinAttribute +PN9.Mode=XSPI2_Port2Octo +PN9.PinAttribute=FSBL +PN9.Signal=XSPIM_P2_IO5 +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32N657X0HxQ +ProjectManager.Example=Template_FSBL_XIP +ProjectManager.ExampleSource=CubeFw +ProjectManager.FirmwarePackage=STM32Cube FW_N6 V1.4.1 +ProjectManager.FreePins=true +ProjectManager.FreePinsContext=FSBL +ProjectManager.HalAssertFull=true +ProjectManager.HeapSize=FSBL-0x200,Appli-0x200,ExtMemLoader-0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=blto2_FSBL.ioc +ProjectManager.ProjectName=blto2_FSBL +ProjectManager.ProjectStructure=FSBL\:FSBL\:true;Appli\:Appli\:false;ExtMemLoader\:ExtMemLoader\:false; +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=FSBL-0x800,Appli-0x800,ExtMemLoader-0x800 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-FSBL,2-MX_GPIO_Init-GPIO-false-HAL-true-FSBL,3-MX_XSPI2_Init-XSPI2-false-HAL-true-FSBL,false-4-MX_XSPIM_Init-XSPIM-false-HAL-true-FSBL,1-SystemIsolation_Config-RIF-false-HAL-true-Appli,2-MX_GPIO_Init-GPIO-false-HAL-true-Appli,0-MX_CORTEX_M55_FSBL_Init-CORTEX_M55_FSBL-false-HAL-true-FSBL,0-MX_CORTEX_M55_S_Init-CORTEX_M55_S-false-HAL-true-Appli,1-MX_GPIO_Init-GPIO-false-HAL-true-ExtMemLoader +RCC.ADC12Freq_Value=200000000 +RCC.ADFFreq_Value=200000000 +RCC.AHB1234Freq_Value=200000000 +RCC.AHBFreq_Value=75000000 +RCC.APB1Freq_Value=200000000 +RCC.APB2Freq_Value=200000000 +RCC.APB4Freq_Value=200000000 +RCC.APB5Freq_Value=200000000 +RCC.AXIClockFreq_Value=400000000 +RCC.CKPERFreq_Value=64000000 +RCC.CPUCLKSource=RCC_CPUCLKSOURCE_IC1 +RCC.CortexFreq_Value=75000000 +RCC.CpuClockFreq_Value=600000000 +RCC.DCMIPPFreq_Value=200000000 +RCC.ETH1Freq_Value=200000000 +RCC.FBDIV1=75 +RCC.FDCANFreq_Value=200000000 +RCC.FMCFreq_Value=200000000 +RCC.FOUTPOSTDIV1Freq_Value=1200000000 +RCC.FOUTPOSTDIV2Freq_Value=1600000000 +RCC.FOUTPOSTDIV3Freq_Value=1600000000 +RCC.FOUTPOSTDIV4Freq_Value=1600000000 +RCC.FREFDIV1=4 +RCC.FamilyName=M +RCC.HSE_VALUE=48000000 +RCC.HSI_VALUE=64000000 +RCC.I2C1Freq_Value=200000000 +RCC.I2C2Freq_Value=200000000 +RCC.I2C3Freq_Value=200000000 +RCC.I2C4Freq_Value=200000000 +RCC.I3C1Freq_Value=200000000 +RCC.I3C2Freq_Value=200000000 +RCC.IC10Freq_VALUE=1600000000 +RCC.IC11Div=3 +RCC.IC11Freq_VALUE=400000000 +RCC.IC12Freq_VALUE=1600000000 +RCC.IC13Freq_VALUE=1600000000 +RCC.IC14Freq_VALUE=1600000000 +RCC.IC15Freq_VALUE=1600000000 +RCC.IC16Freq_VALUE=1600000000 +RCC.IC17Freq_VALUE=1600000000 +RCC.IC18Freq_VALUE=1600000000 +RCC.IC19Freq_VALUE=1600000000 +RCC.IC1Div=2 +RCC.IC1Freq_VALUE=600000000 +RCC.IC20Freq_VALUE=1600000000 +RCC.IC2Div=3 +RCC.IC2Freq_VALUE=400000000 +RCC.IC3Div=24 +RCC.IC3Freq_VALUE=50000000 +RCC.IC4Freq_VALUE=1200000000 +RCC.IC5Freq_VALUE=1200000000 +RCC.IC6Freq_VALUE=300000000 +RCC.IC7Freq_VALUE=1600000000 +RCC.IC8Freq_VALUE=1600000000 +RCC.IC9Freq_VALUE=1600000000 +RCC.IPParameters=ADC12Freq_Value,ADFFreq_Value,AHB1234Freq_Value,AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,APB4Freq_Value,APB5Freq_Value,AXIClockFreq_Value,CKPERFreq_Value,CPUCLKSource,CortexFreq_Value,CpuClockFreq_Value,DCMIPPFreq_Value,ETH1Freq_Value,FBDIV1,FDCANFreq_Value,FMCFreq_Value,FOUTPOSTDIV1Freq_Value,FOUTPOSTDIV2Freq_Value,FOUTPOSTDIV3Freq_Value,FOUTPOSTDIV4Freq_Value,FREFDIV1,FamilyName,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,I3C2Freq_Value,IC10Freq_VALUE,IC11Div,IC11Freq_VALUE,IC12Freq_VALUE,IC13Freq_VALUE,IC14Freq_VALUE,IC15Freq_VALUE,IC16Freq_VALUE,IC17Freq_VALUE,IC18Freq_VALUE,IC19Freq_VALUE,IC1Div,IC1Freq_VALUE,IC20Freq_VALUE,IC2Div,IC2Freq_VALUE,IC3Div,IC3Freq_VALUE,IC4Freq_VALUE,IC5Freq_VALUE,IC6Freq_VALUE,IC7Freq_VALUE,IC8Freq_VALUE,IC9Freq_VALUE,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPUART1Freq_Value,LSE_VALUE,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,MDFFreq_Value,MSI_VALUE,OTGHS1Freq_Value,OTGHS2Freq_Value,OTGPHY1Freq_Value,OTGPHY2Freq_Value,PSSIFreq_Value,PWR_Regulator_Voltage_Scale,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPDIFRX1Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSBCLKFreq_VALUE,SYSBCLKSource,SYSCCLKFreq_VALUE,SYSDCLKFreq_VALUE,TIMGFreq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,USART10Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCO4OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInput4Freq_Value,XSPI1Freq_Value,XSPI2ClockSelection,XSPI2Freq_Value,XSPI3Freq_Value +RCC.LPTIM1Freq_Value=200000000 +RCC.LPTIM2Freq_Value=200000000 +RCC.LPTIM3Freq_Value=200000000 +RCC.LPTIM4Freq_Value=200000000 +RCC.LPTIM5Freq_Value=200000000 +RCC.LPUART1Freq_Value=200000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.LTDCFreq_Value=200000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=64000000 +RCC.MDFFreq_Value=200000000 +RCC.MSI_VALUE=16000000 +RCC.OTGHS1Freq_Value=24000000 +RCC.OTGHS2Freq_Value=24000000 +RCC.OTGPHY1Freq_Value=24000000 +RCC.OTGPHY2Freq_Value=24000000 +RCC.PSSIFreq_Value=200000000 +RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE0 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=200000000 +RCC.SAI2Freq_Value=200000000 +RCC.SDMMC1Freq_Value=200000000 +RCC.SDMMC2Freq_Value=200000000 +RCC.SPDIFRX1Freq_Value=200000000 +RCC.SPI1Freq_Value=200000000 +RCC.SPI2Freq_Value=200000000 +RCC.SPI3Freq_Value=200000000 +RCC.SPI4Freq_Value=200000000 +RCC.SPI5Freq_Value=200000000 +RCC.SPI6Freq_Value=200000000 +RCC.SYSBCLKFreq_VALUE=400000000 +RCC.SYSBCLKSource=RCC_SYSCLKSOURCE_IC2_IC6_IC11 +RCC.SYSCCLKFreq_VALUE=300000000 +RCC.SYSDCLKFreq_VALUE=400000000 +RCC.TIMGFreq_Value=400000000 +RCC.UART4Freq_Value=200000000 +RCC.UART5Freq_Value=200000000 +RCC.UART7Freq_Value=200000000 +RCC.UART8Freq_Value=200000000 +RCC.UART9Freq_Value=200000000 +RCC.USART10Freq_Value=200000000 +RCC.USART1Freq_Value=200000000 +RCC.USART2Freq_Value=200000000 +RCC.USART3Freq_Value=200000000 +RCC.USART6Freq_Value=200000000 +RCC.VCO1OutputFreq_Value=1200000000 +RCC.VCO2OutputFreq_Value=1600000000 +RCC.VCO3OutputFreq_Value=1600000000 +RCC.VCO4OutputFreq_Value=1600000000 +RCC.VCOInput1Freq_Value=16000000 +RCC.VCOInput2Freq_Value=64000000 +RCC.VCOInput3Freq_Value=64000000 +RCC.VCOInput4Freq_Value=64000000 +RCC.XSPI1Freq_Value=200000000 +RCC.XSPI2ClockSelection=RCC_XSPI2CLKSOURCE_IC3 +RCC.XSPI2Freq_Value=50000000 +RCC.XSPI3Freq_Value=200000000 +RIF.DCMIPP_CID_RIMU=0 +RIF.DMA2D_CID_RIMU=0 +RIF.ETH1_CID_RIMU=0 +RIF.ETR_CID_RIMU=0 +RIF.GPU_CID_RIMU=0 +RIF.IPParameters=ETR_CID_RIMU,SDMMC1_CID_RIMU,SDMMC2_CID_RIMU,OTG1_CID_RIMU,OTG2_CID_RIMU,ETH1_CID_RIMU,GPU_CID_RIMU,DMA2D_CID_RIMU,DCMIPP_CID_RIMU,VENC_CID_RIMU,LTDC_L1_CID_RIMU,LTDC_L2_CID_RIMU +RIF.LTDC_L1_CID_RIMU=0 +RIF.LTDC_L2_CID_RIMU=0 +RIF.OTG1_CID_RIMU=0 +RIF.OTG2_CID_RIMU=0 +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG0\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PG0\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PG0\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PG1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Secure=false +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Cid=- +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Secure=false +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Cid=- +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Secure=false +RIF.SDMMC1_CID_RIMU=0 +RIF.SDMMC2_CID_RIMU=0 +RIF.VENC_CID_RIMU=0 +RIF.default_config=false +VP_RIF_VS_RIF1.Mode=RISUP +VP_RIF_VS_RIF1.Signal=RIF_VS_RIF1 +VP_XSPI2_VS_octo.Mode=octo_mode +VP_XSPI2_VS_octo.Signal=XSPI2_VS_octo +VP_XSPIM_VS_IO.Mode=Direct +VP_XSPIM_VS_IO.Signal=XSPIM_VS_IO +XSPI2.ChipSelectHighTimeCycle=2 +XSPI2.ClockPrescaler=0 +XSPI2.DelayHoldQuarterCycle=HAL_XSPI_DHQC_ENABLE +XSPI2.FifoThresholdByte=4 +XSPI2.IPParameters=FifoThresholdByte,MemoryType,MemorySize,ClockPrescaler,DelayHoldQuarterCycle,MemoryMode,ChipSelectHighTimeCycle +XSPI2.MemoryMode=HAL_XSPI_SINGLE_MEM +XSPI2.MemorySize=HAL_XSPI_SIZE_512MB +XSPI2.MemoryType=HAL_XSPI_MEMTYPE_MACRONIX +board=custom