source: trunk/hardware/notizen.txt@ 1

Last change on this file since 1 was 1, checked in by f.jahn, 5 weeks ago
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[1]1EVAL Boards:
2--------------
3
4- STM32N6570-DK
5
6Mit STM32N657X0H3Q Controller. Controller ist bei mouser auf Lager. 13,67EUR
7Der größte Controller aus der Serie mit AI und Crypto
8VFBGA 264pins aber mit freundlichen 0,8mm Raster
9Der gleiche Chip ohne Crypto und ai 12,13, aber nicht auf Lager
10
11User Manual: https://www.st.com/resource/en/user_manual/um3300-discovery-kit-with-stm32n657x0-mcu-stmicroelectronics.pdf
12
13-> 128Mbit Flash über Okto SPI
14-> USB Type-C® with USB 2.0 HS interface, dual‑role‑power (DRP)
15-> USB Type-A with USB 2.0 HS interface, host, 0.5 A max
16-> 1‑Gbit Ethernet with TSN (time-sensitive networking) compliant with IEEE‑802.3‑2002 • SAI audio codec
17-> 256-Mbit Hexadeca‑SPI PSRAM
18-> microSD™ Card
19-> Stereo headset jack including analog microphone input
20
21
22The Octo‑SPI flash memory has the following characteristics: 1-Gbit, 1.8 V, 200 MHz, DTR, read while writing. It is connected to the OCTOSPI interface of the STM32N657X0H3Q microcontroller on the STM32N6570-DK board. Since the NRST (system reset) is at 3.3 V level, while the reset of the flash memory is 1.8 V in this design, a diode (D4) is used to adapt the reset signals.
23
24microSD™ card A slot (CN13) for microSD™ card (UHS-I supported) is available on the STM32N6570-DK board and is connected to the SDMMC2 interface of STM32N657X0H3Q. The uSD_Detect signal (PN12) manages the microSD™ card detection. When a microSD™ card is inserted into the slot, the uSD_Detect signal level is LOW, otherwise, it is HIGH. The SD_SEL signal (connected to PO5) manages the power selection (1.8/3.3 V). The system reset (NRST) and PWR_SD_EN(PQ7) signals enable or disable the power switch. PWR_ON pulls up these two signals.
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26
27The STM32N6570-DK board supports 10/100/1000-Mbit Ethernet communication with a PHY and integrates an RJ45 connector (CN16). The Ethernet PHY is connected to the STM32N657X0H3Q microcontroller via an RGMII interface. The 25 MHz clock of the PHY is generated from the X4 crystal.
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29
30Audio
31Audio STM32N6570-DK features audio characteristics such as: • An audio codec with an SAI interface and a 3.5 mm audio jack connector (for stereo earphones and one analog microphone) • A digital MEMS microphone and microphone daughterboard connector Audio codec An audio codec is driven through the I2C2 interface (100 kHz). The I2C write/read address is 0x34/0x35. An SAI interface transfers audio data. A dedicated I/O (Audio_INT, PB1, active LOW) is used for the IRQ interrupt. Warning: The SAI signals are multiplexed with trace signals.
32
33---------------------------------
34NUCLEO-N657X0-Q
35
36Mit STM32N657X0H3Q controller
37Usermanual: chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/https://www.st.com/resource/en/user_manual/um3417-stm32n6-nucleo144-board-mb1940-stmicroelectronics.pdf
38
39-> USB Type-C® DRP with USB 2.0 high-speed interface, dual‑role‑power (DRP)
40-> 64Mbit Flash über Okto SPI
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