source: trunk/hardware/blto2/ps_motor1_sch.kicad_sch

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        (text_box "Positive Strom Überwachung:\n- Normalbetrieb\n- Ausgang auf 0 bei ca. +7,5A (7,57A)\n- Ausgang auf 1 bei ca. +0,5A (0,39A)"
                (exclude_from_sim no)
                (at 292.735 92.71 0)
                (size 43.815 14.1714)
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        (text_box "Note:\nDu kannst den Timer so konfigurieren (über das AOE-Bit im Register TIMx_BDTR), dass er sich bei jedem neuen Timer-Update-Event (also zu Beginn der nächsten PWM-Periode) automatisch wieder einschaltet, \nsofern der Überstrom nicht mehr anliegt. Das realisiert eine echte Cycle-by-Cycle-Strombegrenzung. [1] (https://community.st.com/stm32-mcus-products-25/timers-break-and-clear-behavior-in-general-36669),\n[2] (https://deepbluembedded.com/stm32-timers-tutorial-hardware-timers-explained/)"
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        (text_box "- Wir wollen mit 48V Eingangsspannung kompatibel sein, Deshalb UDs der MOSFETS auf >= 75V erhöhen um genug Sicherheitsamrge zu haben\n- Design ist auf maximal 7,5A Ausgang und Delta T < 25°C ausgelegt\n- Highside auf geringen Qg achten. Insbesondere auch Qgd! Da wir jetzt mit 300Khz Zielfrequenz schalten\n- Lowside auf wenig RDSOn optimiert\n- ca. 3 cm²Cu Fläche als Kühlung\n- Ausgangsrippel nach Ki Berechnung < 50mV (Hier dominiert der ESR Rippel und nicht der Kapazitätsripel)\n- Ki Berechnet Eingangsrippel auf 46mV, Hier ist der kapazitive Faktor dominant. Deshalb 2 Stück Polymer Kondensatoren.\n- Leiterbahnbreite >= 1,5mm für ca. 5A Dauerstrom bei 35µm Kupfer"
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        (text_box "Negative Strom Überwachung:\n- Bremsbetrieb\n- Ausgang auf 0 bei -7,5A (7,52 A)\n- Ausgang auf 1 bei -0,5A"
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        (text_box "Achtung beim Layout:\nMinimale Leiterbahnlängen (wenige mm) für :\n- Bootstrap Kondensator zum Treiber IC\n- Gate Leitung zum IC\n- HS zum switching node\n- VSS zum Q2 Source!!!!\n\nAuch keine VIAS im Signalweg!\n\nFläche SW Node so klein wie möglich, aber groß genug für 5A"
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