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partition_stm32n657xx.h

Last change on this file was 16, checked in by Zed, 5 weeks ago

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1	/**
2	******************************************************************************
3	* @file partition_stm32n657xx.h
4	* @author MCD Application Team
5	* @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones
6	* for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
7	*
8	* This file contains:
9	* - Initialize Security Attribution Unit (SAU) CTRL register
10	* - Setup behavior of Sleep and Exception Handling
11	* - Setup behavior of Floating Point Unit
12	* - Setup Interrupt Target
13	*
14	******************************************************************************/
15	/*
16	* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
17	* Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
18	*
19	* SPDX-License-Identifier: Apache-2.0
20	*
21	* Licensed under the Apache License, Version 2.0 (the License); you may
22	* not use this file except in compliance with the License.
23	* You may obtain a copy of the License at
24	*
25	* http://www.apache.org/licenses/LICENSE-2.0
26	*
27	* Unless required by applicable law or agreed to in writing, software
28	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
29	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
30	* See the License for the specific language governing permissions and
31	* limitations under the License.
32	*/
33
34	#ifndef PARTITION_STM32N657XX_H
35	#define PARTITION_STM32N657XX_H
36
37	/*
38	//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
39	*/
40
41	/*
42	// <e>Initialize Security Attribution Unit (SAU) CTRL register
43	*/
44	#define SAU_INIT_CTRL 0
45
46	/*
47	// <q> Enable SAU
48	// <i> Value for SAU->CTRL register bit ENABLE
49	*/
50	#define SAU_INIT_CTRL_ENABLE 0
51
52	/*
53	// <o> When SAU is disabled
54	// <0=> All Memory is Secure
55	// <1=> All Memory is Non-Secure
56	// <i> Value for SAU->CTRL register bit ALLNS
57	// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
58	*/
59	#define SAU_INIT_CTRL_ALLNS 0
60
61	/*
62	// </e>
63	*/
64
65	/*
66	// <h>Initialize Security Attribution Unit (SAU) Address Regions
67	// <i>SAU configuration specifies regions to be one of:
68	// <i> - Secure and Non-Secure Callable
69	// <i> - Non-Secure
70	// <i>Note: All memory regions not configured by SAU are Secure
71	*/
72	#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
73
74	/*
75	// <e>Initialize SAU Region 0
76	// <i> Setup SAU Region 0 memory attributes
77	*/
78	#define SAU_INIT_REGION0 0
79
80	/*
81	// <o>Start Address <0-0xFFFFFFE0>
82	*/
83	#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
84
85	/*
86	// <o>End Address <0x1F-0xFFFFFFFF>
87	*/
88	#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */
89
90	/*
91	// <o>Region is
92	// <0=>Non-Secure
93	// <1=>Secure, Non-Secure Callable
94	*/
95	#define SAU_INIT_NSC0 0
96	/*
97	// </e>
98	*/
99
100	/*
101	// <e>Initialize SAU Region 1
102	// <i> Setup SAU Region 1 memory attributes
103	*/
104	#define SAU_INIT_REGION1 0
105
106	/*
107	// <o>Start Address <0-0xFFFFFFE0>
108	*/
109	#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */
110
111	/*
112	// <o>End Address <0x1F-0xFFFFFFFF>
113	*/
114	#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */
115
116	/*
117	// <o>Region is
118	// <0=>Non-Secure
119	// <1=>Secure, Non-Secure Callable
120	*/
121	#define SAU_INIT_NSC1 0
122	/*
123	// </e>
124	*/
125
126	/*
127	// <e>Initialize SAU Region 2
128	// <i> Setup SAU Region 2 memory attributes
129	*/
130	#define SAU_INIT_REGION2 0
131
132	/*
133	// <o>Start Address <0-0xFFFFFFE0>
134	*/
135	#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */
136
137	/*
138	// <o>End Address <0x1F-0xFFFFFFFF>
139	*/
140	#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */
141
142	/*
143	// <o>Region is
144	// <0=>Non-Secure
145	// <1=>Secure, Non-Secure Callable
146	*/
147	#define SAU_INIT_NSC2 0
148	/*
149	// </e>
150	*/
151
152	/*
153	// <e>Initialize SAU Region 3
154	// <i> Setup SAU Region 3 memory attributes
155	*/
156	#define SAU_INIT_REGION3 0
157
158	/*
159	// <o>Start Address <0-0xFFFFFFE0>
160	*/
161	#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */
162
163	/*
164	// <o>End Address <0x1F-0xFFFFFFFF>
165	*/
166	#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */
167
168	/*
169	// <o>Region is
170	// <0=>Non-Secure
171	// <1=>Secure, Non-Secure Callable
172	*/
173	#define SAU_INIT_NSC3 0
174	/*
175	// </e>
176	*/
177
178	/*
179	// <e>Initialize SAU Region 4
180	// <i> Setup SAU Region 4 memory attributes
181	*/
182	#define SAU_INIT_REGION4 0
183
184	/*
185	// <o>Start Address <0-0xFFFFFFE0>
186	*/
187	#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
188
189	/*
190	// <o>End Address <0x1F-0xFFFFFFFF>
191	*/
192	#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
193
194	/*
195	// <o>Region is
196	// <0=>Non-Secure
197	// <1=>Secure, Non-Secure Callable
198	*/
199	#define SAU_INIT_NSC4 0
200	/*
201	// </e>
202	*/
203
204	/*
205	// <e>Initialize SAU Region 5
206	// <i> Setup SAU Region 5 memory attributes
207	*/
208	#define SAU_INIT_REGION5 0
209
210	/*
211	// <o>Start Address <0-0xFFFFFFE0>
212	*/
213	#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */
214
215	/*
216	// <o>End Address <0x1F-0xFFFFFFFF>
217	*/
218	#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */
219
220	/*
221	// <o>Region is
222	// <0=>Non-Secure
223	// <1=>Secure, Non-Secure Callable
224	*/
225	#define SAU_INIT_NSC5 0
226	/*
227	// </e>
228	*/
229
230	/*
231	// <e>Initialize SAU Region 6
232	// <i> Setup SAU Region 6 memory attributes
233	*/
234	#define SAU_INIT_REGION6 0
235
236	/*
237	// <o>Start Address <0-0xFFFFFFE0>
238	*/
239	#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
240
241	/*
242	// <o>End Address <0x1F-0xFFFFFFFF>
243	*/
244	#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
245
246	/*
247	// <o>Region is
248	// <0=>Non-Secure
249	// <1=>Secure, Non-Secure Callable
250	*/
251	#define SAU_INIT_NSC6 0
252	/*
253	// </e>
254	*/
255
256	/*
257	// <e>Initialize SAU Region 7
258	// <i> Setup SAU Region 7 memory attributes
259	*/
260	#define SAU_INIT_REGION7 0
261
262	/*
263	// <o>Start Address <0-0xFFFFFFE0>
264	*/
265	#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
266
267	/*
268	// <o>End Address <0x1F-0xFFFFFFFF>
269	*/
270	#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
271
272	/*
273	// <o>Region is
274	// <0=>Non-Secure
275	// <1=>Secure, Non-Secure Callable
276	*/
277	#define SAU_INIT_NSC7 0
278	/*
279	// </e>
280	*/
281
282	/*
283	// </h>
284	*/
285
286	/*
287	// <e>Setup behaviour of Sleep and Exception Handling
288	*/
289	#define SCB_CSR_AIRCR_INIT 0
290
291	/*
292	// <o> Deep Sleep can be enabled by
293	// <0=>Secure and Non-Secure state
294	// <1=>Secure state only
295	// <i> Value for SCB->CSR register bit DEEPSLEEPS
296	*/
297	#define SCB_CSR_DEEPSLEEPS_VAL 0
298
299	/*
300	// <o>System reset request accessible from
301	// <0=> Secure and Non-Secure state
302	// <1=> Secure state only
303	// <i> Value for SCB->AIRCR register bit SYSRESETREQS
304	*/
305	#define SCB_AIRCR_SYSRESETREQS_VAL 0
306
307	/*
308	// <o>Priority of Non-Secure exceptions is
309	// <0=> Not altered
310	// <1=> Lowered to 0x04-0x07
311	// <i> Value for SCB->AIRCR register bit PRIS
312	*/
313	#define SCB_AIRCR_PRIS_VAL 0
314
315	/*
316	// <o>BusFault, HardFault, and NMI target
317	// <0=> Secure state
318	// <1=> Non-Secure state
319	// <i> Value for SCB->AIRCR register bit BFHFNMINS
320	*/
321	#define SCB_AIRCR_BFHFNMINS_VAL 0
322
323	/*
324	// </e>
325	*/
326
327	/*
328	// <e>Setup behaviour of Floating Point Unit
329	*/
330	#define TZ_FPU_NS_USAGE 1
331
332	/*
333	// <o>Floating Point Unit usage
334	// <0=> Secure state only
335	// <3=> Secure and Non-Secure state
336	// <i> Value for SCB->NSACR register bits CP10, CP11
337	*/
338	#define SCB_NSACR_CP10_11_VAL 3
339
340	/*
341	// <o>Treat floating-point registers as Secure
342	// <0=> Disabled
343	// <1=> Enabled
344	// <i> Value for FPU->FPCCR register bit TS
345	*/
346	#define FPU_FPCCR_TS_VAL 0
347
348	/*
349	// <o>Clear on return (CLRONRET) accessibility
350	// <0=> Secure and Non-Secure state
351	// <1=> Secure state only
352	// <i> Value for FPU->FPCCR register bit CLRONRETS
353	*/
354	#define FPU_FPCCR_CLRONRETS_VAL 0
355
356	/*
357	// <o>Clear floating-point caller saved registers on exception return
358	// <0=> Disabled
359	// <1=> Enabled
360	// <i> Value for FPU->FPCCR register bit CLRONRET
361	*/
362	#define FPU_FPCCR_CLRONRET_VAL 1
363
364	/*
365	// </e>
366	*/
367
368	/*
369	// <h>Setup Interrupt Target
370	*/
371
372	/*
373	// <e>Initialize ITNS 0 (Interrupts 0..31)
374	*/
375	#define NVIC_INIT_ITNS0 1
376
377	/*
378	// Interrupts 0..31
379	// <o.0> PVD_IRQn <0=> Secure state <1=> Non-Secure state
380	// <o.1> Reserved <0=> Secure state <1=> Non-Secure state
381	// <o.2> DTS_IRQn <0=> Secure state <1=> Non-Secure state
382	// <o.3> RCC_IRQn <0=> Secure state <1=> Non-Secure state
383	// <o.4> LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state
384	// <o.5> CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state
385	// <o.6> TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state
386	// <o.7> BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state
387	// <o.8> FPU_IRQn <0=> Secure state <1=> Non-Secure state
388	// <o.9> Reserved <0=> Secure state <1=> Non-Secure state
389	// <o.10> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
390	// <o.11> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
391	// <o.12> RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state
392	// <o.13> IAC_IRQn <0=> Secure state <1=> Non-Secure state
393	// <o.14> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
394	// <o.15> Reserved <0=> Secure state <1=> Non-Secure state
395	// <o.16> RTC_IRQn <0=> Secure state <1=> Non-Secure state
396	// <o.17> Reserved <0=> Secure state <1=> Non-Secure state
397	// <o.18> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
398	// <o.19> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
399	// <o.20> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
400	// <o.21> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
401	// <o.22> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
402	// <o.23> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
403	// <o.24> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
404	// <o.25> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
405	// <o.26> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
406	// <o.27> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
407	// <o.28> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
408	// <o.29> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
409	// <o.30> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
410	// <o.31> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
411	*/
412	#define NVIC_INIT_ITNS0_VAL 0x00000000
413
414	/*
415	// </e>
416	*/
417
418	/*
419	// <e>Initialize ITNS 1 (Interrupts 32..63)
420	*/
421	#define NVIC_INIT_ITNS1 1
422
423	/*
424	// Interrupts 32..63
425	// <o.0> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
426	// <o.1> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
427	// <o.2> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
428	// <o.3> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
429	// <o.4> SAES_IRQn <0=> Secure state <1=> Non-Secure state
430	// <o.5> CRYP_IRQn <0=> Secure state <1=> Non-Secure state
431	// <o.6> PKA_IRQn <0=> Secure state <1=> Non-Secure state
432	// <o.7> HASH_IRQn <0=> Secure state <1=> Non-Secure state
433	// <o.8> RNG_IRQn <0=> Secure state <1=> Non-Secure state
434	// <o.9> Reserved <0=> Secure state <1=> Non-Secure state
435	// <o.10> MCE1_IRQn <0=> Secure state <1=> Non-Secure state
436	// <o.11> MCE2_IRQn <0=> Secure state <1=> Non-Secure state
437	// <o.12> MCE3_IRQn <0=> Secure state <1=> Non-Secure state
438	// <o.13> MCE4_IRQn <0=> Secure state <1=> Non-Secure state
439	// <o.14> ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state
440	// <o.15> CSI_IRQn <0=> Secure state <1=> Non-Secure state
441	// <o.16> DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state
442	// <o.17> Reserved <0=> Secure state <1=> Non-Secure state
443	// <o.18> Reserved <0=> Secure state <1=> Non-Secure state
444	// <o.19> Reserved <0=> Secure state <1=> Non-Secure state
445	// <o.20> PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state
446	// <o.21> NPU0_IRQn <0=> Secure state <1=> Non-Secure state
447	// <o.22> NPU1_IRQn <0=> Secure state <1=> Non-Secure state
448	// <o.23> NPU2_IRQn <0=> Secure state <1=> Non-Secure state
449	// <o.24> NPU3_IRQn <0=> Secure state <1=> Non-Secure state
450	// <o.25> CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state
451	// <o.26> LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state
452	// <o.27> LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state
453	// <o.28> DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
454	// <o.29> JPEG_IRQn <0=> Secure state <1=> Non-Secure state
455	// <o.30> VENC_IRQn <0=> Secure state <1=> Non-Secure state
456	// <o.31> GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state
457	*/
458	#define NVIC_INIT_ITNS1_VAL 0x00000000
459
460	/*
461	// </e>
462	*/
463
464	/*
465	// <e>Initialize ITNS 2 (Interrupts 64..95)
466	*/
467	#define NVIC_INIT_ITNS2 1
468
469	/*
470	// Interrupts 64..95
471	// <o.0> GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state
472	// <o.1> GPU2D_IRQn <0=> Secure state <1=> Non-Secure state
473	// <o.2> GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state
474	// <o.3> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
475	// <o.4> HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
476	// <o.5> HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
477	// <o.6> HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
478	// <o.7> HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
479	// <o.8> HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
480	// <o.9> HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
481	// <o.10> HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
482	// <o.11> HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
483	// <o.12> HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
484	// <o.13> HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
485	// <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
486	// <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
487	// <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
488	// <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
489	// <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
490	// <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
491	// <o.20> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
492	// <o.21> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
493	// <o.22> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
494	// <o.23> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
495	// <o.24> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
496	// <o.25> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
497	// <o.26> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
498	// <o.27> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
499	// <o.28> GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
500	// <o.29> GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
501	// <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
502	// <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
503	*/
504	#define NVIC_INIT_ITNS2_VAL 0x00000000
505
506	/*
507	// </e>
508	*/
509
510	/*
511	// <e>Initialize ITNS 3 (Interrupts 96..127)
512	*/
513	#define NVIC_INIT_ITNS3 1
514
515	/*
516	// Interrupts 96..127
517	// <o.0> GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
518	// <o.1> GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
519	// <o.2> GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
520	// <o.3> GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
521	// <o.4> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
522	// <o.5> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
523	// <o.6> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
524	// <o.7> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
525	// <o.8> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
526	// <o.9> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
527	// <o.10> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
528	// <o.11> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
529	// <o.12> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
530	// <o.13> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
531	// <o.14> I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
532	// <o.15> I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
533	// <o.16> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
534	// <o.17> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
535	// <o.18> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
536	// <o.19> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
537	// <o.20> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
538	// <o.21> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
539	// <o.22> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
540	// <o.23> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
541	// <o.24> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
542	// <o.25> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
543	// <o.26> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
544	// <o.27> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
545	// <o.28> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
546	// <o.29> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
547	// <o.30> TIM9_IRQn <0=> Secure state <1=> Non-Secure state
548	// <o.31> TIM10_IRQn <0=> Secure state <1=> Non-Secure state
549
550	*/
551	#define NVIC_INIT_ITNS3_VAL 0x00000000
552
553	/*
554	// </e>
555	*/
556
557	/*
558	// <e>Initialize ITNS 4 (Interrupts 128..159)
559	*/
560	#define NVIC_INIT_ITNS4 1
561
562	/*
563	// Interrupts 128..159
564	// <o.0> TIM11_IRQn <0=> Secure state <1=> Non-Secure state
565	// <o.1> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
566	// <o.2> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
567	// <o.3> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
568	// <o.4> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
569	// <o.5> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
570	// <o.6> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
571	// <o.7> TIM18_IRQn <0=> Secure state <1=> Non-Secure state
572	// <o.8> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
573	// <o.9> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
574	// <o.10> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
575	// <o.11> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
576	// <o.12> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
577	// <o.13> ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
578	// <o.14> MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
579	// <o.15> MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
580	// <o.16> MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
581	// <o.17> MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
582	// <o.18> MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
583	// <o.19> MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
584	// <o.20> SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state
585	// <o.21> SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state
586	// <o.22> SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state
587	// <o.23> SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state
588	// <o.24> SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state
589	// <o.25> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
590	// <o.26> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
591	// <o.27> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
592	// <o.28> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
593	// <o.29> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
594	// <o.30> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
595	// <o.31> USART1_IRQn <0=> Secure state <1=> Non-Secure state
596
597	*/
598	#define NVIC_INIT_ITNS4_VAL 0x00000000
599
600	/*
601	// </e>
602	*/
603
604	/*
605	// <e>Initialize ITNS 5 (Interrupts 160..191)
606	*/
607	#define NVIC_INIT_ITNS5 1
608
609	/*
610	// Interrupts 160..191
611	// <o.0> USART2_IRQn <0=> Secure state <1=> Non-Secure state
612	// <o.1> USART3_IRQn <0=> Secure state <1=> Non-Secure state
613	// <o.2> UART4_IRQn <0=> Secure state <1=> Non-Secure state
614	// <o.3> UART5_IRQn <0=> Secure state <1=> Non-Secure state
615	// <o.4> USART6_IRQn <0=> Secure state <1=> Non-Secure state
616	// <o.5> UART7_IRQn <0=> Secure state <1=> Non-Secure state
617	// <o.6> UART8_IRQn <0=> Secure state <1=> Non-Secure state
618	// <o.7> UART9_IRQn <0=> Secure state <1=> Non-Secure state
619	// <o.8> USART10_IRQn <0=> Secure state <1=> Non-Secure state
620	// <o.9> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
621	// <o.10> XSPI1_IRQn <0=> Secure state <1=> Non-Secure state
622	// <o.11> XSPI2_IRQn <0=> Secure state <1=> Non-Secure state
623	// <o.12> XSPI3_IRQn <0=> Secure state <1=> Non-Secure state
624	// <o.13> FMC_IRQn <0=> Secure state <1=> Non-Secure state
625	// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
626	// <o.15> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
627	// <o.16> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
628	// <o.17> USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state
629	// <o.18> USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state
630	// <o.19> ETH1_IRQn <0=> Secure state <1=> Non-Secure state
631	// <o.20> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
632	// <o.21> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
633	// <o.22> FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state
634	// <o.23> FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state
635	// <o.24> FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state
636	// <o.25> FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state
637	// <o.26> FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state
638	// <o.27> MDIOS_IRQn <0=> Secure state <1=> Non-Secure state
639	// <o.28> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
640	// <o.29> WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state
641	// <o.30> CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state
642	// <o.31> CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state
643
644	*/
645	#define NVIC_INIT_ITNS5_VAL 0x00000000
646
647	/*
648	// </e>
649	*/
650
651	/*
652	// <e>Initialize ITNS 6 (Interrupts 192..223)
653	*/
654	#define NVIC_INIT_ITNS6 1
655
656	/*
657	// Interrupts 192..223
658	// <o.0> Reserved <0=> Secure state <1=> Non-Secure state
659	// <o.1> LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state
660	// <o.2> LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state
661
662	*/
663	#define NVIC_INIT_ITNS6_VAL 0x00000000
664
665	/*
666	// </e>
667	*/
668
669	/*
670	// </h>
671	*/
672
673
674
675	/*
676	max 8 SAU regions.
677	SAU regions are defined in partition.h
678	*/
679
680	#define SAU_INIT_REGION(n) \
681	SAU->RNR = (n & SAU_RNR_REGION_Msk); \
682	SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
683	SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) \| \
684	((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) \| 1U
685
686	/**
687	\brief Setup a SAU Region
688	\details Writes the region information contained in SAU_Region to the
689	registers SAU_RNR, SAU_RBAR, and SAU_RLAR
690	*/
691	__STATIC_INLINE void TZ_SAU_Setup (void)
692	{
693
694	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
695
696	#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
697	SAU_INIT_REGION(0);
698	#endif
699
700	#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
701	SAU_INIT_REGION(1);
702	#endif
703
704	#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
705	SAU_INIT_REGION(2);
706	#endif
707
708	#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
709	SAU_INIT_REGION(3);
710	#endif
711
712	#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
713	SAU_INIT_REGION(4);
714	#endif
715
716	#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
717	SAU_INIT_REGION(5);
718	#endif
719
720	#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
721	SAU_INIT_REGION(6);
722	#endif
723
724	#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
725	SAU_INIT_REGION(7);
726	#endif
727
728	/* repeat this for all possible SAU regions */
729
730	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
731
732
733	#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
734	SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) \|
735	((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
736	#endif
737
738	#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
739	SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) \|
740	((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
741
742	SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_SYSRESETREQS_Msk \|
743	SCB_AIRCR_BFHFNMINS_Msk \| SCB_AIRCR_PRIS_Msk) ) \|
744	((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) \|
745	((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) \|
746	((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) \|
747	((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
748	#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
749
750	#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
751	defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
752
753	SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk \| SCB_NSACR_CP11_Msk)) \|
754	((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk \| SCB_NSACR_CP11_Msk));
755
756	FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk \| FPU_FPCCR_CLRONRETS_Msk \| FPU_FPCCR_CLRONRET_Msk)) \|
757	((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) \|
758	((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) \|
759	((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
760	#endif
761
762	#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
763	NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
764	#endif
765
766	#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
767	NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
768	#endif
769
770	#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
771	NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
772	#endif
773
774	#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
775	NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
776	#endif
777
778	#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
779	NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
780	#endif
781
782	#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
783	NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
784	#endif
785
786	#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
787	NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
788	#endif
789
790	}
791
792	#endif /* PARTITION_STM32N657XX_H */

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source: trunk/firmware/FSBL/SES/STM32N6xx/Device/Include/Templates/partition_stm32n657xx.h

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