Changeset 55 for trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src
- Timestamp:
- Apr 1, 2026, 9:33:58 AM (5 weeks ago)
- Location:
- trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src
- Files:
-
- 22 edited
-
stm32g4xx_hal.c (modified) (1 diff)
-
stm32g4xx_hal_adc.c (modified) (1 diff)
-
stm32g4xx_hal_adc_ex.c (modified) (4 diffs)
-
stm32g4xx_hal_crc.c (modified) (10 diffs)
-
stm32g4xx_hal_dma.c (modified) (6 diffs)
-
stm32g4xx_hal_dma_ex.c (modified) (2 diffs)
-
stm32g4xx_hal_exti.c (modified) (7 diffs)
-
stm32g4xx_hal_gpio.c (modified) (3 diffs)
-
stm32g4xx_hal_i2c.c (modified) (9 diffs)
-
stm32g4xx_hal_iwdg.c (modified) (1 diff)
-
stm32g4xx_hal_pcd.c (modified) (34 diffs)
-
stm32g4xx_hal_pcd_ex.c (modified) (5 diffs)
-
stm32g4xx_hal_pwr.c (modified) (1 diff)
-
stm32g4xx_hal_pwr_ex.c (modified) (1 diff)
-
stm32g4xx_hal_rcc.c (modified) (2 diffs)
-
stm32g4xx_hal_rcc_ex.c (modified) (3 diffs)
-
stm32g4xx_hal_rtc.c (modified) (5 diffs)
-
stm32g4xx_hal_rtc_ex.c (modified) (1 diff)
-
stm32g4xx_hal_spi.c (modified) (11 diffs)
-
stm32g4xx_hal_uart.c (modified) (20 diffs)
-
stm32g4xx_hal_uart_ex.c (modified) (5 diffs)
-
stm32g4xx_ll_usb.c (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c
r20 r55 49 49 /* Private define ------------------------------------------------------------*/ 50 50 /** 51 * @brief STM32G4xx HAL Driver version number V1.2. 551 * @brief STM32G4xx HAL Driver version number V1.2.6 52 52 */ 53 53 #define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 54 54 #define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ 55 #define __STM32G4xx_HAL_VERSION_SUB2 (0x0 5U) /*!< [15:8] sub2 version */55 #define __STM32G4xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ 56 56 #define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 57 57 #define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
r20 r55 2775 2775 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset)); 2776 2776 2777 /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is2778 ignored (considered as reset) */2779 assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));2780 2781 2777 /* Verification of channel number */ 2782 2778 if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
r20 r55 857 857 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) 858 858 * @param pData Destination Buffer address. 859 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).859 * @param Length Length of data to be transferred from ADC peripheral to memory. 860 860 * @retval HAL status 861 861 */ … … 1053 1053 /* Note: DMA channel of ADC slave should be stopped after this function */ 1054 1054 /* with HAL_ADC_Stop_DMA() API. */ 1055 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 1056 1057 /* Check if DMA channel effectively disabled */ 1058 if (tmp_hal_status == HAL_ERROR) 1059 { 1060 /* Update ADC state machine to error */ 1061 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 1055 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) 1056 { 1057 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 1058 1059 /* Check if DMA channel effectively disabled */ 1060 if (tmp_hal_status == HAL_ERROR) 1061 { 1062 /* Update ADC state machine to error */ 1063 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 1064 } 1062 1065 } 1063 1066 … … 1409 1412 /* Disable the DMA channel (in case of DMA in circular mode or stop while */ 1410 1413 /* while DMA transfer is on going) */ 1411 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 1412 1413 /* Check if DMA channel effectively disabled */ 1414 if (tmp_hal_status != HAL_OK) 1415 { 1416 /* Update ADC state machine to error */ 1417 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 1414 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) 1415 { 1416 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 1417 1418 /* Check if DMA channel effectively disabled */ 1419 if (tmp_hal_status == HAL_ERROR) 1420 { 1421 /* Update ADC state machine to error */ 1422 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 1423 } 1418 1424 } 1419 1425 … … 1549 1555 /* Note: DMA channel of ADC slave should be stopped after this function */ 1550 1556 /* with HAL_ADCEx_RegularStop_DMA() API. */ 1551 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 1552 1553 /* Check if DMA channel effectively disabled */ 1554 if (tmp_hal_status != HAL_OK) 1555 { 1556 /* Update ADC state machine to error */ 1557 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 1557 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) 1558 { 1559 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 1560 1561 /* Check if DMA channel effectively disabled */ 1562 if (tmp_hal_status == HAL_ERROR) 1563 { 1564 /* Update ADC state machine to error */ 1565 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 1566 } 1558 1567 } 1559 1568 -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c
r20 r55 65 65 * @{ 66 66 */ 67 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);68 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);67 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength); 68 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength); 69 69 /** 70 70 * @} … … 285 285 * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) 286 286 */ 287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) 288 288 { 289 289 uint32_t index; /* CRC input data buffer index */ … … 305 305 306 306 case CRC_INPUTDATA_FORMAT_BYTES: 307 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);307 temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); 308 308 break; 309 309 310 310 case CRC_INPUTDATA_FORMAT_HALFWORDS: 311 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 311 temp = 312 CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 312 313 break; 313 314 default: … … 337 338 * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) 338 339 */ 339 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)340 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength) 340 341 { 341 342 uint32_t index; /* CRC input data buffer index */ … … 362 363 case CRC_INPUTDATA_FORMAT_BYTES: 363 364 /* Specific 8-bit input data handling */ 364 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);365 temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength); 365 366 break; 366 367 367 368 case CRC_INPUTDATA_FORMAT_HALFWORDS: 368 369 /* Specific 16-bit input data handling */ 369 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 370 temp = 371 CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 370 372 break; 371 373 … … 430 432 * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) 431 433 */ 432 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)434 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength) 433 435 { 434 436 uint32_t i; /* input data buffer index */ … … 453 455 *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 454 456 } 455 if ((BufferLength % 4U) == 2U)457 else if ((BufferLength % 4U) == 2U) 456 458 { 457 459 data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; … … 459 461 *pReg = data; 460 462 } 461 if ((BufferLength % 4U) == 3U)463 else if ((BufferLength % 4U) == 3U) 462 464 { 463 465 data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; … … 467 469 *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 468 470 } 471 else 472 { 473 /* Nothing to do */ 474 } 469 475 } 470 476 … … 481 487 * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) 482 488 */ 483 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)489 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength) 484 490 { 485 491 uint32_t i; /* input data buffer index */ -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c
r20 r55 493 493 HAL_StatusTypeDef status = HAL_OK; 494 494 495 if(hdma->State != HAL_DMA_STATE_BUSY) 495 /* Check the DMA peripheral handle parameter */ 496 if (hdma == NULL) 497 { 498 return HAL_ERROR; 499 } 500 501 if (hdma->State != HAL_DMA_STATE_BUSY) 496 502 { 497 503 /* no transfer ongoing */ … … 502 508 else 503 509 { 504 /* Disable DMA IT*/505 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));506 507 /* disable the DMAMUX sync overrun IT*/508 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;509 510 /* Disable the channel*/511 __HAL_DMA_DISABLE(hdma);512 513 /* Clear all flags */514 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));515 516 /* Clear the DMAMUX synchro overrun flag */517 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;518 519 if (hdma->DMAmuxRequestGen != 0U)520 {521 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/522 /* disable the request gen overrun IT*/523 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;524 525 /* Clear the DMAMUX request generator overrun flag */526 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;527 }528 } 510 /* Disable the channel */ 511 __HAL_DMA_DISABLE(hdma); 512 513 /* Disable DMA IT */ 514 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 515 516 /* disable the DMAMUX sync overrun IT*/ 517 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 518 519 /* Clear all flags */ 520 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 521 522 /* Clear the DMAMUX synchro overrun flag */ 523 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 524 525 if (hdma->DMAmuxRequestGen != 0U) 526 { 527 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ 528 /* disable the request gen overrun IT*/ 529 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 530 531 /* Clear the DMAMUX request generator overrun flag */ 532 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 533 } 534 } 529 535 /* Change the DMA state */ 530 536 hdma->State = HAL_DMA_STATE_READY; … … 561 567 else 562 568 { 569 570 /* Disable the channel */ 571 __HAL_DMA_DISABLE(hdma); 572 563 573 /* Disable DMA IT */ 564 574 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 565 566 /* Disable the channel */567 __HAL_DMA_DISABLE(hdma);568 575 569 576 /* disable the DMAMUX sync overrun IT*/ … … 937 944 * @} 938 945 */ 939 940 946 941 947 … … 1054 1060 /* DMA1 */ 1055 1061 DMAMUX1_ChannelBase = DMAMUX1_Channel0; 1062 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 1056 1063 } 1057 1064 else … … 1060 1067 #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) || defined (STM32G411xC) 1061 1068 DMAMUX1_ChannelBase = DMAMUX1_Channel8; 1069 channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 8U; 1062 1070 #elif defined (STM32G411xB) || defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) 1063 1071 DMAMUX1_ChannelBase = DMAMUX1_Channel6; 1072 channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 6U; 1064 1073 #else 1065 1074 DMAMUX1_ChannelBase = DMAMUX1_Channel7; 1075 channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U; 1066 1076 #endif /* STM32G4x1xx) */ 1067 1077 } 1078 1068 1079 dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase; 1069 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;1070 1080 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 1071 1081 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c
r20 r55 93 93 * @retval HAL status 94 94 */ 95 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)95 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, const HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) 96 96 { 97 97 /* Check the parameters */ … … 140 140 */ 141 141 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, 142 HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)142 const HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) 143 143 { 144 144 /* Check the parameters */ -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c
r20 r55 142 142 * @retval HAL Status. 143 143 */ 144 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)144 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef const *pExtiConfig) 145 145 { 146 146 __IO uint32_t *regaddr; … … 266 266 * @retval HAL Status. 267 267 */ 268 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)269 { 270 __IO uint32_t *regaddr;268 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef const *hexti, EXTI_ConfigTypeDef *pExtiConfig) 269 { 270 const __IO uint32_t *regaddr; 271 271 uint32_t regval; 272 272 uint32_t linepos; … … 362 362 * @retval HAL Status. 363 363 */ 364 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)364 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef const *hexti) 365 365 { 366 366 __IO uint32_t *regaddr; … … 502 502 * @retval none. 503 503 */ 504 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)504 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef const *hexti) 505 505 { 506 506 __IO uint32_t *regaddr; … … 537 537 * @retval 1 if interrupt is pending else 0. 538 538 */ 539 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)540 { 541 __IO uint32_t *regaddr;539 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge) 540 { 541 const __IO uint32_t *regaddr; 542 542 uint32_t regval; 543 543 uint32_t linepos; … … 572 572 * @retval None. 573 573 */ 574 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)574 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge) 575 575 { 576 576 __IO uint32_t *regaddr; … … 601 601 * @retval None. 602 602 */ 603 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)603 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef const *hexti) 604 604 { 605 605 __IO uint32_t *regaddr; -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c
r20 r55 160 160 * @retval None 161 161 */ 162 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef*GPIO_Init)162 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init) 163 163 { 164 164 uint32_t position = 0x00U; … … 199 199 } 200 200 201 if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 201 if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) || 202 (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP))) 202 203 { 203 204 /* Check the Pull parameter */ … … 371 372 * @retval The input port pin value. 372 373 */ 373 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)374 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef const *GPIOx, uint16_t GPIO_Pin) 374 375 { 375 376 GPIO_PinState bitstatus; -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c
r20 r55 3325 3325 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) 3326 3326 { 3327 return HAL_ERROR; 3327 /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ 3328 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 3329 { 3330 /* Clear STOP Flag */ 3331 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 3332 3333 /* Reset the error code for next trial */ 3334 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3335 } 3328 3336 } 3329 3330 /* Clear STOP Flag */ 3331 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 3332 3333 /* Device is ready */ 3334 hi2c->State = HAL_I2C_STATE_READY; 3335 3336 /* Process Unlocked */ 3337 __HAL_UNLOCK(hi2c); 3338 3339 return HAL_OK; 3337 else 3338 { 3339 /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ 3340 3341 /* Clear STOP Flag */ 3342 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 3343 3344 /* Device is ready */ 3345 hi2c->State = HAL_I2C_STATE_READY; 3346 3347 /* Process Unlocked */ 3348 __HAL_UNLOCK(hi2c); 3349 3350 return HAL_OK; 3351 } 3340 3352 } 3341 3353 else 3342 3354 { 3343 /* Wait until STOPF flag is reset */ 3344 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) 3345 { 3346 return HAL_ERROR; 3347 } 3355 /* A non acknowledge is detected, this mean that device not respond to its address, 3356 a new trial must be performed */ 3348 3357 3349 3358 /* Clear NACK Flag */ 3350 3359 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 3351 3360 3352 /* Clear STOP Flag, auto generated with autoend*/ 3353 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 3361 /* Wait until STOPF flag is reset */ 3362 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK) 3363 { 3364 /* Clear STOP Flag, auto generated with autoend*/ 3365 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 3366 } 3354 3367 } 3355 3368 … … 6350 6363 hi2c->pBuffPtr++; 6351 6364 6352 if ( (hi2c->XferSize > 0U))6365 if (hi2c->XferSize > 0U) 6353 6366 { 6354 6367 hi2c->XferSize--; … … 6506 6519 hi2c->pBuffPtr++; 6507 6520 6508 if ( (hi2c->XferSize > 0U))6521 if (hi2c->XferSize > 0U) 6509 6522 { 6510 6523 hi2c->XferSize--; … … 6954 6967 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 6955 6968 { 6956 if ( (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))6969 if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 6957 6970 { 6958 6971 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; … … 6994 7007 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 6995 7008 { 6996 if ( (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))7009 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) 6997 7010 { 6998 7011 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; … … 7033 7046 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 7034 7047 { 7035 if ( (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))7048 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 7036 7049 { 7037 7050 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; … … 7111 7124 if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) 7112 7125 { 7113 if ( (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))7126 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 7114 7127 { 7115 7128 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; … … 7278 7291 uint32_t Request) 7279 7292 { 7293 uint32_t tmp; 7294 7280 7295 /* Check the parameters */ 7281 7296 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); … … 7284 7299 7285 7300 /* Declaration of tmp to prevent undefined behavior of volatile usage */ 7286 uint32_ttmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \7287 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \7288 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));7301 tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 7302 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 7303 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); 7289 7304 7290 7305 /* update CR2 register */ -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.c
r38 r55 127 127 LSI startup time is also considered here by adding LSI_STARTUP_TIME 128 128 converted in milliseconds. */ 129 #define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) 129 #define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \ 130 ((LSI_STARTUP_TIME / 1000UL) + 1UL)) 130 131 #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) 131 132 /** -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c
r20 r55 50 50 (##) HAL_PCD_Start(); 51 51 52 (#)NOTE: For applications not using double buffer mode, define the symbol 53 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. 54 52 55 @endverbatim 53 56 ****************************************************************************** … … 312 315 return HAL_ERROR; 313 316 } 314 /* Process locked */315 __HAL_LOCK(hpcd);316 317 317 318 if (hpcd->State == HAL_PCD_STATE_READY) … … 391 392 } 392 393 393 /* Release Lock */394 __HAL_UNLOCK(hpcd);395 394 return status; 396 395 } … … 417 416 HAL_StatusTypeDef status = HAL_OK; 418 417 419 /* Process locked */420 __HAL_LOCK(hpcd);421 422 418 /* Setup Legacy weak Callbacks */ 423 419 if (hpcd->State == HAL_PCD_STATE_READY) … … 500 496 } 501 497 502 /* Release Lock */503 __HAL_UNLOCK(hpcd);504 498 return status; 505 499 } … … 525 519 } 526 520 527 /* Process locked */528 __HAL_LOCK(hpcd);529 530 521 if (hpcd->State == HAL_PCD_STATE_READY) 531 522 { … … 541 532 } 542 533 543 /* Release Lock */544 __HAL_UNLOCK(hpcd);545 546 534 return status; 547 535 } … … 557 545 HAL_StatusTypeDef status = HAL_OK; 558 546 559 /* Process locked */560 __HAL_LOCK(hpcd);561 562 547 if (hpcd->State == HAL_PCD_STATE_READY) 563 548 { … … 573 558 } 574 559 575 /* Release Lock */576 __HAL_UNLOCK(hpcd);577 578 560 return status; 579 561 } … … 599 581 } 600 582 601 /* Process locked */602 __HAL_LOCK(hpcd);603 604 583 if (hpcd->State == HAL_PCD_STATE_READY) 605 584 { … … 615 594 } 616 595 617 /* Release Lock */618 __HAL_UNLOCK(hpcd);619 620 596 return status; 621 597 } … … 631 607 HAL_StatusTypeDef status = HAL_OK; 632 608 633 /* Process locked */634 __HAL_LOCK(hpcd);635 636 609 if (hpcd->State == HAL_PCD_STATE_READY) 637 610 { … … 647 620 } 648 621 649 /* Release Lock */650 __HAL_UNLOCK(hpcd);651 652 622 return status; 653 623 } … … 673 643 } 674 644 675 /* Process locked */676 __HAL_LOCK(hpcd);677 678 645 if (hpcd->State == HAL_PCD_STATE_READY) 679 646 { … … 688 655 status = HAL_ERROR; 689 656 } 690 691 /* Release Lock */692 __HAL_UNLOCK(hpcd);693 657 694 658 return status; … … 706 670 HAL_StatusTypeDef status = HAL_OK; 707 671 708 /* Process locked */709 __HAL_LOCK(hpcd);710 711 672 if (hpcd->State == HAL_PCD_STATE_READY) 712 673 { … … 722 683 } 723 684 724 /* Release Lock */725 __HAL_UNLOCK(hpcd);726 727 685 return status; 728 686 } … … 748 706 } 749 707 750 /* Process locked */751 __HAL_LOCK(hpcd);752 753 708 if (hpcd->State == HAL_PCD_STATE_READY) 754 709 { … … 763 718 status = HAL_ERROR; 764 719 } 765 766 /* Release Lock */767 __HAL_UNLOCK(hpcd);768 720 769 721 return status; … … 781 733 HAL_StatusTypeDef status = HAL_OK; 782 734 783 /* Process locked */784 __HAL_LOCK(hpcd);785 786 735 if (hpcd->State == HAL_PCD_STATE_READY) 787 736 { … … 797 746 } 798 747 799 /* Release Lock */ 800 __HAL_UNLOCK(hpcd); 801 802 return status; 748 return status; 803 749 } 804 750 … … 822 768 } 823 769 824 /* Process locked */825 __HAL_LOCK(hpcd);826 827 770 if (hpcd->State == HAL_PCD_STATE_READY) 828 771 { … … 838 781 } 839 782 840 /* Release Lock */841 __HAL_UNLOCK(hpcd);842 843 783 return status; 844 784 } … … 854 794 HAL_StatusTypeDef status = HAL_OK; 855 795 856 /* Process locked */857 __HAL_LOCK(hpcd);858 859 796 if (hpcd->State == HAL_PCD_STATE_READY) 860 797 { … … 870 807 } 871 808 872 /* Release Lock */873 __HAL_UNLOCK(hpcd);874 875 809 return status; 876 810 } … … 895 829 } 896 830 897 /* Process locked */898 __HAL_LOCK(hpcd);899 900 831 if (hpcd->State == HAL_PCD_STATE_READY) 901 832 { … … 911 842 } 912 843 913 /* Release Lock */914 __HAL_UNLOCK(hpcd);915 916 844 return status; 917 845 } … … 927 855 HAL_StatusTypeDef status = HAL_OK; 928 856 929 /* Process locked */930 __HAL_LOCK(hpcd);931 932 857 if (hpcd->State == HAL_PCD_STATE_READY) 933 858 { … … 942 867 status = HAL_ERROR; 943 868 } 944 945 /* Release Lock */946 __HAL_UNLOCK(hpcd);947 869 948 870 return status; … … 1727 1649 epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); 1728 1650 1651 if (epindex >= 8U) 1652 { 1653 return HAL_ERROR; 1654 } 1655 1729 1656 if (epindex == 0U) 1730 1657 { … … 1770 1697 /* Get SETUP Packet */ 1771 1698 ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 1699 1700 if (ep->xfer_count != 8U) 1701 { 1702 /* Set Stall condition for EP0 IN/OUT */ 1703 PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); 1704 PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); 1705 1706 /* SETUP bit kept frozen while CTR_RX = 1 */ 1707 PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 1708 1709 return HAL_OK; 1710 } 1772 1711 1773 1712 USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, … … 1791 1730 ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 1792 1731 1793 if ( (ep->xfer_count != 0U) && (ep->xfer_buff != 0U))1732 if (ep->xfer_count == 0U) 1794 1733 { 1795 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 1796 ep->pmaadress, (uint16_t)ep->xfer_count); 1797 1798 ep->xfer_buff += ep->xfer_count; 1799 1800 /* Process Control Data OUT Packet */ 1734 /* Status phase re-arm for next setup */ 1735 PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); 1736 } 1737 else 1738 { 1739 if (ep->xfer_buff != 0U) 1740 { 1741 USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 1742 ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ 1743 1744 ep->xfer_buff += ep->xfer_count; 1745 1746 /* Process Control Data OUT Packet */ 1801 1747 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) 1802 hpcd->DataOutStageCallback(hpcd, 0U);1748 hpcd->DataOutStageCallback(hpcd, 0U); 1803 1749 #else 1804 HAL_PCD_DataOutStageCallback(hpcd, 0U);1750 HAL_PCD_DataOutStageCallback(hpcd, 0U); 1805 1751 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ 1806 } 1807 1808 wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); 1809 1810 if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) 1811 { 1812 PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); 1752 } 1813 1753 } 1814 1754 } … … 1876 1816 /* multi-packet on the NON control OUT endpoint */ 1877 1817 ep->xfer_count += count; 1878 ep->xfer_buff += count;1879 1818 1880 1819 if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) … … 1889 1828 else 1890 1829 { 1830 ep->xfer_buff += count; 1891 1831 (void)USB_EPStartXfer(hpcd->Instance, ep); 1892 1832 } -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c
r20 r55 83 83 PCD_EPTypeDef *ep; 84 84 85 /* initialize ep structure*/85 /* Initialize ep structure */ 86 86 if ((0x80U & ep_addr) == 0x80U) 87 87 { … … 98 98 /* Single Buffer */ 99 99 ep->doublebuffer = 0U; 100 100 101 /* Configure the PMA */ 101 102 ep->pmaadress = (uint16_t)pmaadress; … … 106 107 /* Double Buffer Endpoint */ 107 108 ep->doublebuffer = 1U; 109 108 110 /* Configure the PMA */ 109 111 ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); … … 125 127 hpcd->battery_charging_active = 1U; 126 128 129 USBx->BCDR &= ~(USB_BCDR_PDEN); 130 USBx->BCDR &= ~(USB_BCDR_SDEN); 131 127 132 /* Enable BCD feature */ 128 133 USBx->BCDR |= USB_BCDR_BCDEN; 129 134 130 /* Enable DCD : Data Contact Detect */131 USBx->BCDR &= ~(USB_BCDR_PDEN);132 USBx->BCDR &= ~(USB_BCDR_SDEN);133 USBx->BCDR |= USB_BCDR_DCDEN;134 135 135 return HAL_OK; 136 136 } … … 163 163 164 164 /* Wait for Min DCD Timeout */ 165 HAL_Delay(300U); 166 167 /* Data Pin Contact ? Check Detect flag */ 168 if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) 169 { 170 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) 171 hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); 172 #else 173 HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); 174 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ 175 } 165 HAL_Delay(350U); 166 176 167 /* Primary detection: checks if connected to Standard Downstream Port 177 168 (without charging capability) */ 178 USBx->BCDR &= ~(USB_BCDR_DCDEN);179 HAL_Delay(50U);180 169 USBx->BCDR |= (USB_BCDR_PDEN); 181 170 HAL_Delay(50U); -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c
r20 r55 306 306 * @retval None 307 307 */ 308 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)308 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef const *sConfigPVD) 309 309 { 310 310 /* Check the parameters */ -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c
r20 r55 672 672 * @retval HAL status 673 673 */ 674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef const *sConfigPVM) 675 675 { 676 676 HAL_StatusTypeDef status = HAL_OK; -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c
r20 r55 310 310 * @retval HAL status 311 311 */ 312 HAL_StatusTypeDef HAL_RCC_OscConfig( RCC_OscInitTypeDef *RCC_OscInitStruct)312 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) 313 313 { 314 314 uint32_t tickstart; … … 764 764 * @retval None 765 765 */ 766 HAL_StatusTypeDef HAL_RCC_ClockConfig( RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)766 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) 767 767 { 768 768 uint32_t tickstart; -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c
r20 r55 121 121 * @retval HAL status 122 122 */ 123 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)123 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit) 124 124 { 125 125 uint32_t tmpregister; … … 1406 1406 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) 1407 1407 { 1408 GPIO_InitTypeDef GPIO_InitStruct ;1408 GPIO_InitTypeDef GPIO_InitStruct = {0}; 1409 1409 FlagStatus pwrclkchanged = RESET; 1410 1410 FlagStatus backupchanged = RESET; … … 1559 1559 * @retval None 1560 1560 */ 1561 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)1561 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef const *pInit) 1562 1562 { 1563 1563 uint32_t value; -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc.c
r25 r55 971 971 * @retval HAL status 972 972 */ 973 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)973 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) 974 974 { 975 975 uint32_t tmpreg; … … 1099 1099 * @retval HAL status 1100 1100 */ 1101 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)1101 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) 1102 1102 { 1103 1103 uint32_t datetmpreg; … … 1619 1619 * @retval HAL status 1620 1620 */ 1621 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)1621 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) 1622 1622 { 1623 1623 uint32_t tmpreg, subsecondtmpreg; … … 1844 1844 * @retval HAL state 1845 1845 */ 1846 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)1846 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc) 1847 1847 { 1848 1848 /* Return RTC handle state */ … … 2020 2020 * @retval operation see RTC_StoreOperation_Definitions 2021 2021 */ 2022 uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)2022 uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc) 2023 2023 { 2024 2024 return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP); -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc_ex.c
r25 r55 1426 1426 tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); 1427 1427 1428 if ( sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)1428 if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) 1429 1429 { 1430 1430 tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c
r20 r55 816 816 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 817 817 * the configuration information for SPI module. 818 * @param pData pointer to data buffer 819 * @param Size amount of data to be sent820 * @param Timeout Timeout duration 818 * @param pData pointer to data buffer (u8 or u16 data elements) 819 * @param Size amount of data elements (u8 or u16) to be sent 820 * @param Timeout Timeout duration in ms 821 821 * @retval HAL status 822 822 */ … … 1002 1002 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 1003 1003 * the configuration information for SPI module. 1004 * @param pData pointer to data buffer 1005 * @param Size amount of data to be received1006 * @param Timeout Timeout duration 1004 * @param pData pointer to data buffer (u8 or u16 data elements) 1005 * @param Size amount of data elements (u8 or u16) to be received 1006 * @param Timeout Timeout duration in ms 1007 1007 * @retval HAL status 1008 * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES 1009 * the receive buffer is written to data register (DR) to generate 1010 * clock pulses and receive data 1008 1011 */ 1009 1012 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) … … 1244 1247 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 1245 1248 * the configuration information for SPI module. 1246 * @param pTxData pointer to transmission data buffer 1247 * @param pRxData pointer to reception data buffer 1248 * @param Size amount of data to be sent and received1249 * @param Timeout Timeout duration 1249 * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) 1250 * @param pRxData pointer to reception data buffer (u8 or u16 data elements) 1251 * @param Size amount of data elements (u8 or u16) to be sent and received 1252 * @param Timeout Timeout duration in ms 1250 1253 * @retval HAL status 1251 1254 */ … … 1594 1597 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 1595 1598 * the configuration information for SPI module. 1596 * @param pData pointer to data buffer 1597 * @param Size amount of data to be sent1599 * @param pData pointer to data buffer (u8 or u16 data elements) 1600 * @param Size amount of data elements (u8 or u16) to be sent 1598 1601 * @retval HAL status 1599 1602 */ … … 1676 1679 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 1677 1680 * the configuration information for SPI module. 1678 * @param pData pointer to data buffer 1679 * @param Size amount of data to be sent1681 * @param pData pointer to data buffer (u8 or u16 data elements) 1682 * @param Size amount of data elements (u8 or u16) to be received 1680 1683 * @retval HAL status 1681 1684 */ … … 1779 1782 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 1780 1783 * the configuration information for SPI module. 1781 * @param pTxData pointer to transmission data buffer 1782 * @param pRxData pointer to reception data buffer 1783 * @param Size amount of data to be sent and received1784 * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) 1785 * @param pRxData pointer to reception data buffer (u8 or u16 data elements) 1786 * @param Size amount of data elements (u8 or u16) to be sent and received 1784 1787 * @retval HAL status 1785 1788 */ … … 1888 1891 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 1889 1892 * the configuration information for SPI module. 1890 * @param pData pointer to data buffer 1891 * @param Size amount of data to be sent1893 * @param pData pointer to data buffer (u8 or u16 data elements) 1894 * @param Size amount of data elements (u8 or u16) to be sent 1892 1895 * @retval HAL status 1893 1896 */ … … 2008 2011 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 2009 2012 * the configuration information for SPI module. 2010 * @param pData pointer to data buffer 2013 * @param pData pointer to data buffer (u8 or u16 data elements) 2011 2014 * @note When the CRC feature is enabled the pData Length must be Size + 1. 2012 * @param Size amount of data to be sent2015 * @param Size amount of data elements (u8 or u16) to be received 2013 2016 * @retval HAL status 2014 2017 */ … … 2147 2150 * @param hspi pointer to a SPI_HandleTypeDef structure that contains 2148 2151 * the configuration information for SPI module. 2149 * @param pTxData pointer to transmission data buffer 2150 * @param pRxData pointer to reception data buffer 2152 * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) 2153 * @param pRxData pointer to reception data buffer (u8 or u16 data elements) 2151 2154 * @note When the CRC feature is enabled the pRxData Length must be Size + 1 2152 * @param Size amount of data to be sent2155 * @param Size amount of data elements (u8 or u16) to be sent and received 2153 2156 * @retval HAL status 2154 2157 */ … … 3996 3999 tmp_timeout = 0U; 3997 4000 } 3998 count--; 4001 else 4002 { 4003 count--; 4004 } 3999 4005 } 4000 4006 } … … 4078 4084 tmp_timeout = 0U; 4079 4085 } 4080 count--; 4086 else 4087 { 4088 count--; 4089 } 4081 4090 } 4082 4091 } -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
r20 r55 1023 1023 ##### IO operation functions ##### 1024 1024 =============================================================================== 1025 [..] 1025 1026 This subsection provides a set of functions allowing to manage the UART asynchronous 1026 1027 and Half duplex data transfers. 1027 1028 1028 (#) There are two mode of transfer:1029 (+ ) Blocking mode: The communication is performed in polling mode.1030 The HAL status of all data processing is returned by the same function1031 after finishing transfer.1032 (+ ) Non-Blocking mode: The communication is performed using Interrupts1033 or DMA, These API's return the HAL status.1034 The end of the data processing will be indicated through the1035 dedicated UART IRQ when using Interrupt mode or the DMA IRQ when1036 using DMA mode.1037 The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks1038 will be executed respectively at the end of the transmit or Receive process1039 The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected1029 (#) There are two modes of transfer: 1030 (++) Blocking mode: The communication is performed in polling mode. 1031 The HAL status of all data processing is returned by the same function 1032 after finishing transfer. 1033 (++) Non-Blocking mode: The communication is performed using Interrupts 1034 or DMA, These API's return the HAL status. 1035 The end of the data processing will be indicated through the 1036 dedicated UART IRQ when using Interrupt mode or the DMA IRQ when 1037 using DMA mode. 1038 The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks 1039 will be executed respectively at the end of the transmit or Receive process 1040 The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected 1040 1041 1041 1042 (#) Blocking mode API's are : 1042 (+ ) HAL_UART_Transmit()1043 (+ ) HAL_UART_Receive()1043 (++) HAL_UART_Transmit() 1044 (++) HAL_UART_Receive() 1044 1045 1045 1046 (#) Non-Blocking mode API's with Interrupt are : 1046 (+ ) HAL_UART_Transmit_IT()1047 (+ ) HAL_UART_Receive_IT()1048 (+ ) HAL_UART_IRQHandler()1047 (++) HAL_UART_Transmit_IT() 1048 (++) HAL_UART_Receive_IT() 1049 (++) HAL_UART_IRQHandler() 1049 1050 1050 1051 (#) Non-Blocking mode API's with DMA are : 1051 (+ ) HAL_UART_Transmit_DMA()1052 (+ ) HAL_UART_Receive_DMA()1053 (+ ) HAL_UART_DMAPause()1054 (+ ) HAL_UART_DMAResume()1055 (+ ) HAL_UART_DMAStop()1052 (++) HAL_UART_Transmit_DMA() 1053 (++) HAL_UART_Receive_DMA() 1054 (++) HAL_UART_DMAPause() 1055 (++) HAL_UART_DMAResume() 1056 (++) HAL_UART_DMAStop() 1056 1057 1057 1058 (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: 1058 (+ ) HAL_UART_TxHalfCpltCallback()1059 (+ ) HAL_UART_TxCpltCallback()1060 (+ ) HAL_UART_RxHalfCpltCallback()1061 (+ ) HAL_UART_RxCpltCallback()1062 (+ ) HAL_UART_ErrorCallback()1059 (++) HAL_UART_TxHalfCpltCallback() 1060 (++) HAL_UART_TxCpltCallback() 1061 (++) HAL_UART_RxHalfCpltCallback() 1062 (++) HAL_UART_RxCpltCallback() 1063 (++) HAL_UART_ErrorCallback() 1063 1064 1064 1065 (#) Non-Blocking mode transfers could be aborted using Abort API's : 1065 (+ ) HAL_UART_Abort()1066 (+ ) HAL_UART_AbortTransmit()1067 (+ ) HAL_UART_AbortReceive()1068 (+ ) HAL_UART_Abort_IT()1069 (+ ) HAL_UART_AbortTransmit_IT()1070 (+ ) HAL_UART_AbortReceive_IT()1066 (++) HAL_UART_Abort() 1067 (++) HAL_UART_AbortTransmit() 1068 (++) HAL_UART_AbortReceive() 1069 (++) HAL_UART_Abort_IT() 1070 (++) HAL_UART_AbortTransmit_IT() 1071 (++) HAL_UART_AbortReceive_IT() 1071 1072 1072 1073 (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: 1073 (+ ) HAL_UART_AbortCpltCallback()1074 (+ ) HAL_UART_AbortTransmitCpltCallback()1075 (+ ) HAL_UART_AbortReceiveCpltCallback()1074 (++) HAL_UART_AbortCpltCallback() 1075 (++) HAL_UART_AbortTransmitCpltCallback() 1076 (++) HAL_UART_AbortReceiveCpltCallback() 1076 1077 1077 1078 (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced 1078 1079 reception services: 1079 (+) HAL_UARTEx_RxEventCallback() 1080 (++) HAL_UARTEx_RxEventCallback() 1081 1082 (#) Wakeup from Stop mode Callback: 1083 (++) HAL_UARTEx_WakeupCallback() 1080 1084 1081 1085 (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. 1082 1086 Errors are handled as follows : 1083 (+ ) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is1084 to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error1085 in Interrupt mode reception .1086 Received character is then retrieved and stored in Rx buffer, Error code is set to allow user1087 to identify error type, and HAL_UART_ErrorCallback() user callback is executed.1088 Transfer is kept ongoing on UART side.1089 If user wants to abort it, Abort services should be called by user.1090 (+ ) Error is considered as Blocking : Transfer could not be completed properly and is aborted.1091 This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.1092 Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()1093 user callback is executed.1087 (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 1088 to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error 1089 in Interrupt mode reception . 1090 Received character is then retrieved and stored in Rx buffer, Error code is set to allow user 1091 to identify error type, and HAL_UART_ErrorCallback() user callback is executed. 1092 Transfer is kept ongoing on UART side. 1093 If user wants to abort it, Abort services should be called by user. 1094 (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. 1095 This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. 1096 Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() 1097 user callback is executed. 1094 1098 1095 1099 -@- In the Half duplex communication, it is forbidden to run the transmit … … 1169 1173 pdata8bits++; 1170 1174 } 1171 huart->TxXferCount--; 1175 if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) 1176 { 1177 huart->TxXferCount--; 1178 } 1179 else 1180 { 1181 /* Process was aborted during the transmission */ 1182 return HAL_ERROR; 1183 } 1172 1184 } 1173 1185 … … 1265 1277 pdata8bits++; 1266 1278 } 1267 huart->RxXferCount--; 1279 if (huart->RxState == HAL_UART_STATE_BUSY_RX) 1280 { 1281 huart->RxXferCount--; 1282 } 1283 else 1284 { 1285 /* Process was aborted during the reception */ 1286 return HAL_ERROR; 1287 } 1268 1288 } 1269 1289 … … 1705 1725 } 1706 1726 1707 /* Reset Tx and Rx transfer counters */1708 huart->TxXferCount = 0U;1709 huart->RxXferCount = 0U;1710 1711 1727 /* Clear the Error flags in the ICR register */ 1712 1728 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); … … 1775 1791 } 1776 1792 1777 /* Reset Tx transfer counter */1778 huart->TxXferCount = 0U;1779 1780 1793 /* Flush the whole TX FIFO (if needed) */ 1781 1794 if (huart->FifoMode == UART_FIFOMODE_ENABLE) … … 1839 1852 } 1840 1853 } 1841 1842 /* Reset Rx transfer counter */1843 huart->RxXferCount = 0U;1844 1854 1845 1855 /* Clear the Error flags in the ICR register */ … … 1968 1978 if (abortcplt == 1U) 1969 1979 { 1970 /* Reset Tx and Rx transfer counters */1971 huart->TxXferCount = 0U;1972 huart->RxXferCount = 0U;1973 1974 1980 /* Clear ISR function pointers */ 1975 1981 huart->RxISR = NULL; … … 2051 2057 else 2052 2058 { 2053 /* Reset Tx transfer counter */2054 huart->TxXferCount = 0U;2055 2059 2056 2060 /* Clear TxISR function pointers */ … … 2072 2076 else 2073 2077 { 2074 /* Reset Tx transfer counter */2075 huart->TxXferCount = 0U;2076 2077 2078 /* Clear TxISR function pointers */ 2078 2079 huart->TxISR = NULL; … … 2148 2149 else 2149 2150 { 2150 /* Reset Rx transfer counter */2151 huart->RxXferCount = 0U;2152 2153 2151 /* Clear RxISR function pointer */ 2154 2152 huart->pRxBuffPtr = NULL; … … 2176 2174 else 2177 2175 { 2178 /* Reset Rx transfer counter */2179 huart->RxXferCount = 0U;2180 2181 2176 /* Clear RxISR function pointer */ 2182 2177 huart->pRxBuffPtr = NULL; … … 3710 3705 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 3711 3706 { 3707 huart->RxXferCount = 0; 3708 3709 /* Check current nb of data still to be received on DMA side. 3710 DMA Normal mode, remaining nb of data will be 0 3711 DMA Circular mode, remaining nb of data is reset to RxXferSize */ 3712 uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); 3713 if (nb_remaining_rx_data < huart->RxXferSize) 3714 { 3715 /* Update nb of remaining data */ 3716 huart->RxXferCount = nb_remaining_rx_data; 3717 } 3718 3712 3719 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) 3713 3720 /*Call registered Rx Event callback*/ 3714 huart->RxEventCallback(huart, huart->RxXferSize);3721 huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 3715 3722 #else 3716 3723 /*Call legacy weak Rx Event callback*/ 3717 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);3724 HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 3718 3725 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 3719 3726 } … … 3748 3755 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 3749 3756 { 3757 huart->RxXferCount = huart->RxXferSize / 2U; 3758 3759 /* Check current nb of data still to be received on DMA side. */ 3760 uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); 3761 if (nb_remaining_rx_data <= huart->RxXferSize) 3762 { 3763 /* Update nb of remaining data */ 3764 huart->RxXferCount = nb_remaining_rx_data; 3765 } 3766 3750 3767 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) 3751 3768 /*Call registered Rx Event callback*/ 3752 huart->RxEventCallback(huart, huart->RxXferSize / 2U);3769 huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 3753 3770 #else 3754 3771 /*Call legacy weak Rx Event callback*/ 3755 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);3772 HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 3756 3773 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 3757 3774 } … … 3785 3802 (gstate == HAL_UART_STATE_BUSY_TX)) 3786 3803 { 3787 huart->TxXferCount = 0U;3788 3804 UART_EndTxTransfer(huart); 3789 3805 } … … 3793 3809 (rxstate == HAL_UART_STATE_BUSY_RX)) 3794 3810 { 3795 huart->RxXferCount = 0U;3796 3811 UART_EndRxTransfer(huart); 3797 3812 } … … 3817 3832 { 3818 3833 UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 3819 huart->RxXferCount = 0U;3820 3834 3821 3835 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) … … 3850 3864 } 3851 3865 } 3852 3853 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */3854 huart->TxXferCount = 0U;3855 huart->RxXferCount = 0U;3856 3866 3857 3867 /* Reset errorCode */ … … 3906 3916 } 3907 3917 3908 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */3909 huart->TxXferCount = 0U;3910 huart->RxXferCount = 0U;3911 3912 3918 /* Reset errorCode */ 3913 3919 huart->ErrorCode = HAL_UART_ERROR_NONE; … … 3947 3953 UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 3948 3954 3949 huart->TxXferCount = 0U;3950 3951 3955 /* Flush the whole TX FIFO (if needed) */ 3952 3956 if (huart->FifoMode == UART_FIFOMODE_ENABLE) … … 3979 3983 { 3980 3984 UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 3981 3982 huart->RxXferCount = 0U;3983 3985 3984 3986 /* Clear the Error flags in the ICR register */ -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
r20 r55 25 25 ##### UART peripheral extended features ##### 26 26 ============================================================================== 27 27 [..] 28 28 (#) Declare a UART_HandleTypeDef handle structure. 29 29 … … 254 254 ##### IO operation functions ##### 255 255 =============================================================================== 256 [..] 256 257 This subsection provides a set of Wakeup and FIFO mode related callback functions. 257 258 258 (#) Wakeup from Stop mode Callback: 259 (+) HAL_UARTEx_WakeupCallback() 260 259 (++) HAL_UARTEx_WakeupCallback() 261 260 (#) TX/RX Fifos Callbacks: 262 (+) HAL_UARTEx_RxFifoFullCallback() 263 (+) HAL_UARTEx_TxFifoEmptyCallback() 264 261 (++) HAL_UARTEx_RxFifoFullCallback() 262 (++) HAL_UARTEx_TxFifoEmptyCallback() 265 263 @endverbatim 266 264 * @{ … … 342 340 data elements as reception completion criteria, these functions also consider additional events 343 341 as triggers for updating reception status to caller : 344 (+ ) Detection of inactivity period (RX line has not been active for a given period).345 (++ ) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)342 (++) Detection of inactivity period (RX line has not been active for a given period). 343 (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) 346 344 for 1 frame time, after last received byte. 347 (++ ) RX inactivity detected by RTO, i.e. line has been in idle state345 (+++) RX inactivity detected by RTO, i.e. line has been in idle state 348 346 for a programmable time, after last received byte. 349 (+ ) Detection that a specific character has been received.350 351 (#) There are two mode of transfer:352 (+ ) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,347 (++) Detection that a specific character has been received. 348 349 (#) There are two modes of transfer: 350 (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, 353 351 or till IDLE event occurs. Reception is handled only during function execution. 354 352 When function exits, no data reception could occur. HAL status and number of actually received data elements, 355 353 are returned by function after finishing transfer. 356 (+ ) Non-Blocking mode: The reception is performed using Interrupts or DMA.354 (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. 357 355 These API's return the HAL status. 358 356 The end of the data processing will be indicated through the … … 362 360 363 361 (#) Blocking mode API: 364 (+ ) HAL_UARTEx_ReceiveToIdle()362 (++) HAL_UARTEx_ReceiveToIdle() 365 363 366 364 (#) Non-Blocking mode API with Interrupt: 367 (+ ) HAL_UARTEx_ReceiveToIdle_IT()365 (++) HAL_UARTEx_ReceiveToIdle_IT() 368 366 369 367 (#) Non-Blocking mode API with DMA: 370 (+ ) HAL_UARTEx_ReceiveToIdle_DMA()368 (++) HAL_UARTEx_ReceiveToIdle_DMA() 371 369 372 370 @endverbatim … … 943 941 * to Rx Event callback execution. 944 942 * @note This function is expected to be called within the user implementation of Rx Event Callback, 945 * in order to provide the accurate value : 946 * In Interrupt Mode : 947 * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) 948 * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of 949 * received data is lower than expected one) 950 * In DMA Mode : 951 * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) 952 * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received 953 * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of 954 * received data is lower than expected one). 955 * In DMA mode, RxEvent callback could be called several times; 943 * in order to provide the accurate value. 944 * @note In Interrupt Mode: 945 * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). 946 * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. 947 * @note In DMA Mode: 948 * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). 949 * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. 950 * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. 951 * @note In DMA mode, RxEvent callback could be called several times; 956 952 * When DMA is configured in Normal Mode, HT event does not stop Reception process; 957 953 * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; -
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c
r20 r55 34 34 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. 35 35 36 (#)NOTE: For applications not using double buffer mode, define the symbol 37 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. 38 36 39 @endverbatim 37 40 … … 62 65 * @retval HAL status 63 66 */ 64 HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)67 HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg) 65 68 { 66 69 /* Prevent unused argument(s) compilation warning */ … … 131 134 * @retval HAL status 132 135 */ 133 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)136 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode) 134 137 { 135 138 /* Prevent unused argument(s) compilation warning */
Note:
See TracChangeset
for help on using the changeset viewer.
