Ignore:
Timestamp:
Apr 1, 2026, 9:33:58 AM (5 weeks ago)
Author:
f.jahn
Message:

Fixing Projects.

Location:
trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src
Files:
22 edited

Legend:

Unmodified
Added
Removed
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c

    r20 r55  
    4949/* Private define ------------------------------------------------------------*/
    5050/**
    51   * @brief STM32G4xx HAL Driver version number V1.2.5
     51  * @brief STM32G4xx HAL Driver version number V1.2.6
    5252  */
    5353#define __STM32G4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
    5454#define __STM32G4xx_HAL_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
    55 #define __STM32G4xx_HAL_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */
     55#define __STM32G4xx_HAL_VERSION_SUB2   (0x06U) /*!< [15:8]  sub2 version */
    5656#define __STM32G4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
    5757#define __STM32G4xx_HAL_VERSION         ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c

    r20 r55  
    27752775  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
    27762776
    2777   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
    2778      ignored (considered as reset) */
    2779   assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
    2780 
    27812777  /* Verification of channel number */
    27822778  if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c

    r20 r55  
    857857  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
    858858  * @param pData Destination Buffer address.
    859   * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
     859  * @param Length Length of data to be transferred from ADC peripheral to memory.
    860860  * @retval HAL status
    861861  */
     
    10531053    /* Note: DMA channel of ADC slave should be stopped after this function   */
    10541054    /*       with HAL_ADC_Stop_DMA() API.                                     */
    1055     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
    1056 
    1057     /* Check if DMA channel effectively disabled */
    1058     if (tmp_hal_status == HAL_ERROR)
    1059     {
    1060       /* Update ADC state machine to error */
    1061       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1055    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
     1056    {
     1057      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
     1058
     1059      /* Check if DMA channel effectively disabled */
     1060      if (tmp_hal_status == HAL_ERROR)
     1061      {
     1062        /* Update ADC state machine to error */
     1063        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1064      }
    10621065    }
    10631066
     
    14091412    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
    14101413    /* while DMA transfer is on going)                                        */
    1411     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
    1412 
    1413     /* Check if DMA channel effectively disabled */
    1414     if (tmp_hal_status != HAL_OK)
    1415     {
    1416       /* Update ADC state machine to error */
    1417       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1414    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
     1415    {
     1416      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
     1417
     1418      /* Check if DMA channel effectively disabled */
     1419      if (tmp_hal_status == HAL_ERROR)
     1420      {
     1421        /* Update ADC state machine to error */
     1422        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1423      }
    14181424    }
    14191425
     
    15491555    /* Note: DMA channel of ADC slave should be stopped after this function   */
    15501556    /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
    1551     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
    1552 
    1553     /* Check if DMA channel effectively disabled */
    1554     if (tmp_hal_status != HAL_OK)
    1555     {
    1556       /* Update ADC state machine to error */
    1557       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1557    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
     1558    {
     1559      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
     1560
     1561      /* Check if DMA channel effectively disabled */
     1562      if (tmp_hal_status == HAL_ERROR)
     1563      {
     1564        /* Update ADC state machine to error */
     1565        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1566      }
    15581567    }
    15591568
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c

    r20 r55  
    6565  * @{
    6666  */
    67 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
    68 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
     67static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength);
     68static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength);
    6969/**
    7070  * @}
     
    285285  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    286286  */
    287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
     287uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength)
    288288{
    289289  uint32_t index;      /* CRC input data buffer index */
     
    305305
    306306    case CRC_INPUTDATA_FORMAT_BYTES:
    307       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
     307      temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength);
    308308      break;
    309309
    310310    case CRC_INPUTDATA_FORMAT_HALFWORDS:
    311       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
     311      temp =
     312        CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength);  /* Derogation MisraC2012 R.11.5 */
    312313      break;
    313314    default:
     
    337338  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    338339  */
    339 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
     340uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength)
    340341{
    341342  uint32_t index;      /* CRC input data buffer index */
     
    362363    case CRC_INPUTDATA_FORMAT_BYTES:
    363364      /* Specific 8-bit input data handling  */
    364       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
     365      temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength);
    365366      break;
    366367
    367368    case CRC_INPUTDATA_FORMAT_HALFWORDS:
    368369      /* Specific 16-bit input data handling  */
    369       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
     370      temp =
     371        CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength);  /* Derogation MisraC2012 R.11.5 */
    370372      break;
    371373
     
    430432  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    431433  */
    432 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
     434static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength)
    433435{
    434436  uint32_t i; /* input data buffer index */
     
    453455      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
    454456    }
    455     if ((BufferLength % 4U) == 2U)
     457    else if ((BufferLength % 4U) == 2U)
    456458    {
    457459      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
     
    459461      *pReg = data;
    460462    }
    461     if ((BufferLength % 4U) == 3U)
     463    else if ((BufferLength % 4U) == 3U)
    462464    {
    463465      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
     
    467469      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
    468470    }
     471    else
     472    {
     473      /* Nothing to do */
     474    }
    469475  }
    470476
     
    481487  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    482488  */
    483 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
     489static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength)
    484490{
    485491  uint32_t i;  /* input data buffer index */
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c

    r20 r55  
    493493  HAL_StatusTypeDef status = HAL_OK;
    494494
    495   if(hdma->State != HAL_DMA_STATE_BUSY)
     495  /* Check the DMA peripheral handle parameter */
     496  if (hdma == NULL)
     497  {
     498    return HAL_ERROR;
     499  }
     500
     501  if (hdma->State != HAL_DMA_STATE_BUSY)
    496502  {
    497503    /* no transfer ongoing */
     
    502508  else
    503509  {
    504      /* Disable DMA IT */
    505      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
    506      
    507      /* disable the DMAMUX sync overrun IT*/
    508      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
    509      
    510      /* Disable the channel */
    511      __HAL_DMA_DISABLE(hdma);
    512      
    513      /* Clear all flags */
    514      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
    515      
    516      /* Clear the DMAMUX synchro overrun flag */
    517      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
    518      
    519      if (hdma->DMAmuxRequestGen != 0U)
    520      {
    521        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
    522        /* disable the request gen overrun IT*/
    523        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
    524      
    525        /* Clear the DMAMUX request generator overrun flag */
    526        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
    527      }
    528   } 
     510    /* Disable the channel */
     511    __HAL_DMA_DISABLE(hdma);
     512
     513    /* Disable DMA IT */
     514    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
     515
     516    /* disable the DMAMUX sync overrun IT*/
     517    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
     518
     519    /* Clear all flags */
     520    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
     521
     522    /* Clear the DMAMUX synchro overrun flag */
     523    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
     524
     525    if (hdma->DMAmuxRequestGen != 0U)
     526    {
     527      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
     528      /* disable the request gen overrun IT*/
     529      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
     530
     531      /* Clear the DMAMUX request generator overrun flag */
     532      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
     533    }
     534  }
    529535  /* Change the DMA state */
    530536  hdma->State = HAL_DMA_STATE_READY;
     
    561567  else
    562568  {
     569
     570    /* Disable the channel */
     571    __HAL_DMA_DISABLE(hdma);
     572
    563573    /* Disable DMA IT */
    564574    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
    565 
    566     /* Disable the channel */
    567     __HAL_DMA_DISABLE(hdma);
    568575
    569576    /* disable the DMAMUX sync overrun IT*/
     
    937944  * @}
    938945  */
    939 
    940946
    941947
     
    10541060    /* DMA1 */
    10551061    DMAMUX1_ChannelBase = DMAMUX1_Channel0;
     1062    channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
    10561063  }
    10571064  else
     
    10601067#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) || defined (STM32G411xC)
    10611068    DMAMUX1_ChannelBase = DMAMUX1_Channel8;
     1069    channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 8U;
    10621070#elif defined (STM32G411xB) || defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
    10631071    DMAMUX1_ChannelBase = DMAMUX1_Channel6;
     1072    channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 6U;
    10641073#else
    10651074    DMAMUX1_ChannelBase = DMAMUX1_Channel7;
     1075    channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U;
    10661076#endif /* STM32G4x1xx) */
    10671077  }
     1078
    10681079  dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
    1069   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
    10701080  hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
    10711081  hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c

    r20 r55  
    9393  * @retval HAL status
    9494  */
    95 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
     95HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, const HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
    9696{
    9797  /* Check the parameters */
     
    140140  */
    141141HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
    142                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
     142                                                      const HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
    143143{
    144144  /* Check the parameters */
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c

    r20 r55  
    142142  * @retval HAL Status.
    143143  */
    144 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
     144HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef const *pExtiConfig)
    145145{
    146146  __IO uint32_t *regaddr;
     
    266266  * @retval HAL Status.
    267267  */
    268 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
    269 {
    270   __IO uint32_t *regaddr;
     268HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef const *hexti, EXTI_ConfigTypeDef *pExtiConfig)
     269{
     270  const __IO uint32_t *regaddr;
    271271  uint32_t regval;
    272272  uint32_t linepos;
     
    362362  * @retval HAL Status.
    363363  */
    364 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
     364HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef const *hexti)
    365365{
    366366  __IO uint32_t *regaddr;
     
    502502  * @retval none.
    503503  */
    504 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
     504void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef const *hexti)
    505505{
    506506  __IO uint32_t *regaddr;
     
    537537  * @retval 1 if interrupt is pending else 0.
    538538  */
    539 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
    540 {
    541   __IO uint32_t *regaddr;
     539uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge)
     540{
     541  const __IO uint32_t *regaddr;
    542542  uint32_t regval;
    543543  uint32_t linepos;
     
    572572  * @retval None.
    573573  */
    574 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
     574void HAL_EXTI_ClearPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge)
    575575{
    576576  __IO uint32_t *regaddr;
     
    601601  * @retval None.
    602602  */
    603 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
     603void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef const *hexti)
    604604{
    605605  __IO uint32_t *regaddr;
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c

    r20 r55  
    160160  * @retval None
    161161  */
    162 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
     162void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init)
    163163{
    164164  uint32_t position = 0x00U;
     
    199199      }
    200200
    201       if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
     201      if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
     202          (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
    202203      {
    203204        /* Check the Pull parameter */
     
    371372  * @retval The input port pin value.
    372373  */
    373 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
     374GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef const *GPIOx, uint16_t GPIO_Pin)
    374375{
    375376  GPIO_PinState bitstatus;
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c

    r20 r55  
    33253325        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
    33263326        {
    3327           return HAL_ERROR;
     3327          /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */
     3328          if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     3329          {
     3330            /* Clear STOP Flag */
     3331            __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3332
     3333            /* Reset the error code for next trial */
     3334            hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
     3335          }
    33283336        }
    3329 
    3330         /* Clear STOP Flag */
    3331         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
    3332 
    3333         /* Device is ready */
    3334         hi2c->State = HAL_I2C_STATE_READY;
    3335 
    3336         /* Process Unlocked */
    3337         __HAL_UNLOCK(hi2c);
    3338 
    3339         return HAL_OK;
     3337        else
     3338        {
     3339          /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
     3340
     3341          /* Clear STOP Flag */
     3342          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3343
     3344          /* Device is ready */
     3345          hi2c->State = HAL_I2C_STATE_READY;
     3346
     3347          /* Process Unlocked */
     3348          __HAL_UNLOCK(hi2c);
     3349
     3350          return HAL_OK;
     3351        }
    33403352      }
    33413353      else
    33423354      {
    3343         /* Wait until STOPF flag is reset */
    3344         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
    3345         {
    3346           return HAL_ERROR;
    3347         }
     3355        /* A non acknowledge is detected, this mean that device not respond to its address,
     3356           a new trial must be performed */
    33483357
    33493358        /* Clear NACK Flag */
    33503359        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
    33513360
    3352         /* Clear STOP Flag, auto generated with autoend*/
    3353         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3361        /* Wait until STOPF flag is reset */
     3362        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK)
     3363        {
     3364          /* Clear STOP Flag, auto generated with autoend*/
     3365          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3366        }
    33543367      }
    33553368
     
    63506363    hi2c->pBuffPtr++;
    63516364
    6352     if ((hi2c->XferSize > 0U))
     6365    if (hi2c->XferSize > 0U)
    63536366    {
    63546367      hi2c->XferSize--;
     
    65066519    hi2c->pBuffPtr++;
    65076520
    6508     if ((hi2c->XferSize > 0U))
     6521    if (hi2c->XferSize > 0U)
    65096522    {
    65106523      hi2c->XferSize--;
     
    69546967      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
    69556968      {
    6956         if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
     6969        if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
    69576970        {
    69586971          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     
    69947007      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
    69957008      {
    6996         if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
     7009        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
    69977010        {
    69987011          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     
    70337046    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
    70347047    {
    7035       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
     7048      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
    70367049      {
    70377050        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     
    71117124    if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
    71127125    {
    7113       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
     7126      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
    71147127      {
    71157128        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
     
    72787291                               uint32_t Request)
    72797292{
     7293  uint32_t tmp;
     7294
    72807295  /* Check the parameters */
    72817296  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
     
    72847299
    72857300  /* Declaration of tmp to prevent undefined behavior of volatile usage */
    7286   uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
    7287                              (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
    7288                              (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
     7301  tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
     7302                    (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
     7303                    (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
    72897304
    72907305  /* update CR2 register */
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.c

    r38 r55  
    127127   LSI startup time is also considered here by adding LSI_STARTUP_TIME
    128128   converted in milliseconds. */
    129 #define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
     129#define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
     130                                         ((LSI_STARTUP_TIME / 1000UL) + 1UL))
    130131#define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
    131132/**
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c

    r20 r55  
    5050         (##) HAL_PCD_Start();
    5151
     52     (#)NOTE: For applications not using double buffer mode, define the symbol
     53               'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint.
     54
    5255  @endverbatim
    5356  ******************************************************************************
     
    312315    return HAL_ERROR;
    313316  }
    314   /* Process locked */
    315   __HAL_LOCK(hpcd);
    316317
    317318  if (hpcd->State == HAL_PCD_STATE_READY)
     
    391392  }
    392393
    393   /* Release Lock */
    394   __HAL_UNLOCK(hpcd);
    395394  return status;
    396395}
     
    417416  HAL_StatusTypeDef status = HAL_OK;
    418417
    419   /* Process locked */
    420   __HAL_LOCK(hpcd);
    421 
    422418  /* Setup Legacy weak Callbacks  */
    423419  if (hpcd->State == HAL_PCD_STATE_READY)
     
    500496  }
    501497
    502   /* Release Lock */
    503   __HAL_UNLOCK(hpcd);
    504498  return status;
    505499}
     
    525519  }
    526520
    527   /* Process locked */
    528   __HAL_LOCK(hpcd);
    529 
    530521  if (hpcd->State == HAL_PCD_STATE_READY)
    531522  {
     
    541532  }
    542533
    543   /* Release Lock */
    544   __HAL_UNLOCK(hpcd);
    545 
    546534  return status;
    547535}
     
    557545  HAL_StatusTypeDef status = HAL_OK;
    558546
    559   /* Process locked */
    560   __HAL_LOCK(hpcd);
    561 
    562547  if (hpcd->State == HAL_PCD_STATE_READY)
    563548  {
     
    573558  }
    574559
    575   /* Release Lock */
    576   __HAL_UNLOCK(hpcd);
    577 
    578560  return status;
    579561}
     
    599581  }
    600582
    601   /* Process locked */
    602   __HAL_LOCK(hpcd);
    603 
    604583  if (hpcd->State == HAL_PCD_STATE_READY)
    605584  {
     
    615594  }
    616595
    617   /* Release Lock */
    618   __HAL_UNLOCK(hpcd);
    619 
    620596  return status;
    621597}
     
    631607  HAL_StatusTypeDef status = HAL_OK;
    632608
    633   /* Process locked */
    634   __HAL_LOCK(hpcd);
    635 
    636609  if (hpcd->State == HAL_PCD_STATE_READY)
    637610  {
     
    647620  }
    648621
    649   /* Release Lock */
    650   __HAL_UNLOCK(hpcd);
    651 
    652622  return status;
    653623}
     
    673643  }
    674644
    675   /* Process locked */
    676   __HAL_LOCK(hpcd);
    677 
    678645  if (hpcd->State == HAL_PCD_STATE_READY)
    679646  {
     
    688655    status =  HAL_ERROR;
    689656  }
    690 
    691   /* Release Lock */
    692   __HAL_UNLOCK(hpcd);
    693657
    694658  return status;
     
    706670  HAL_StatusTypeDef status = HAL_OK;
    707671
    708   /* Process locked */
    709   __HAL_LOCK(hpcd);
    710 
    711672  if (hpcd->State == HAL_PCD_STATE_READY)
    712673  {
     
    722683  }
    723684
    724   /* Release Lock */
    725   __HAL_UNLOCK(hpcd);
    726 
    727685  return status;
    728686}
     
    748706  }
    749707
    750   /* Process locked */
    751   __HAL_LOCK(hpcd);
    752 
    753708  if (hpcd->State == HAL_PCD_STATE_READY)
    754709  {
     
    763718    status =  HAL_ERROR;
    764719  }
    765 
    766   /* Release Lock */
    767   __HAL_UNLOCK(hpcd);
    768720
    769721  return status;
     
    781733  HAL_StatusTypeDef status = HAL_OK;
    782734
    783   /* Process locked */
    784   __HAL_LOCK(hpcd);
    785 
    786735  if (hpcd->State == HAL_PCD_STATE_READY)
    787736  {
     
    797746  }
    798747
    799   /* Release Lock */
    800   __HAL_UNLOCK(hpcd);
    801 
    802   return status;
     748   return status;
    803749}
    804750
     
    822768  }
    823769
    824   /* Process locked */
    825   __HAL_LOCK(hpcd);
    826 
    827770  if (hpcd->State == HAL_PCD_STATE_READY)
    828771  {
     
    838781  }
    839782
    840   /* Release Lock */
    841   __HAL_UNLOCK(hpcd);
    842 
    843783  return status;
    844784}
     
    854794  HAL_StatusTypeDef status = HAL_OK;
    855795
    856   /* Process locked */
    857   __HAL_LOCK(hpcd);
    858 
    859796  if (hpcd->State == HAL_PCD_STATE_READY)
    860797  {
     
    870807  }
    871808
    872   /* Release Lock */
    873   __HAL_UNLOCK(hpcd);
    874 
    875809  return status;
    876810}
     
    895829  }
    896830
    897   /* Process locked */
    898   __HAL_LOCK(hpcd);
    899 
    900831  if (hpcd->State == HAL_PCD_STATE_READY)
    901832  {
     
    911842  }
    912843
    913   /* Release Lock */
    914   __HAL_UNLOCK(hpcd);
    915 
    916844  return status;
    917845}
     
    927855  HAL_StatusTypeDef status = HAL_OK;
    928856
    929   /* Process locked */
    930   __HAL_LOCK(hpcd);
    931 
    932857  if (hpcd->State == HAL_PCD_STATE_READY)
    933858  {
     
    942867    status =  HAL_ERROR;
    943868  }
    944 
    945   /* Release Lock */
    946   __HAL_UNLOCK(hpcd);
    947869
    948870  return status;
     
    17271649    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
    17281650
     1651    if (epindex >= 8U)
     1652    {
     1653      return HAL_ERROR;
     1654    }
     1655
    17291656    if (epindex == 0U)
    17301657    {
     
    17701697          /* Get SETUP Packet */
    17711698          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
     1699
     1700          if (ep->xfer_count != 8U)
     1701          {
     1702            /* Set Stall condition for EP0 IN/OUT */
     1703            PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL);
     1704            PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL);
     1705
     1706            /* SETUP bit kept frozen while CTR_RX = 1 */
     1707            PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
     1708
     1709            return HAL_OK;
     1710          }
    17721711
    17731712          USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
     
    17911730          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
    17921731
    1793           if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
     1732          if (ep->xfer_count == 0U)
    17941733          {
    1795             USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
    1796                         ep->pmaadress, (uint16_t)ep->xfer_count);
    1797 
    1798             ep->xfer_buff += ep->xfer_count;
    1799 
    1800             /* Process Control Data OUT Packet */
     1734            /* Status phase re-arm for next setup */
     1735            PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
     1736          }
     1737          else
     1738          {
     1739            if (ep->xfer_buff != 0U)
     1740            {
     1741              USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
     1742                          ep->pmaadress, (uint16_t)ep->xfer_count);  /* max 64bytes */
     1743
     1744              ep->xfer_buff += ep->xfer_count;
     1745
     1746              /* Process Control Data OUT Packet */
    18011747#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
    1802             hpcd->DataOutStageCallback(hpcd, 0U);
     1748              hpcd->DataOutStageCallback(hpcd, 0U);
    18031749#else
    1804             HAL_PCD_DataOutStageCallback(hpcd, 0U);
     1750              HAL_PCD_DataOutStageCallback(hpcd, 0U);
    18051751#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
    1806           }
    1807 
    1808           wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
    1809 
    1810           if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
    1811           {
    1812             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
     1752            }
    18131753          }
    18141754        }
     
    18761816        /* multi-packet on the NON control OUT endpoint */
    18771817        ep->xfer_count += count;
    1878         ep->xfer_buff += count;
    18791818
    18801819        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
     
    18891828        else
    18901829        {
     1830          ep->xfer_buff += count;
    18911831          (void)USB_EPStartXfer(hpcd->Instance, ep);
    18921832        }
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c

    r20 r55  
    8383  PCD_EPTypeDef *ep;
    8484
    85   /* initialize ep structure*/
     85  /* Initialize ep structure */
    8686  if ((0x80U & ep_addr) == 0x80U)
    8787  {
     
    9898    /* Single Buffer */
    9999    ep->doublebuffer = 0U;
     100
    100101    /* Configure the PMA */
    101102    ep->pmaadress = (uint16_t)pmaadress;
     
    106107    /* Double Buffer Endpoint */
    107108    ep->doublebuffer = 1U;
     109
    108110    /* Configure the PMA */
    109111    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
     
    125127  hpcd->battery_charging_active = 1U;
    126128
     129  USBx->BCDR &= ~(USB_BCDR_PDEN);
     130  USBx->BCDR &= ~(USB_BCDR_SDEN);
     131
    127132  /* Enable BCD feature */
    128133  USBx->BCDR |= USB_BCDR_BCDEN;
    129134
    130   /* Enable DCD : Data Contact Detect */
    131   USBx->BCDR &= ~(USB_BCDR_PDEN);
    132   USBx->BCDR &= ~(USB_BCDR_SDEN);
    133   USBx->BCDR |= USB_BCDR_DCDEN;
    134 
    135135  return HAL_OK;
    136136}
     
    163163
    164164  /* Wait for Min DCD Timeout */
    165   HAL_Delay(300U);
    166 
    167   /* Data Pin Contact ? Check Detect flag */
    168   if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
    169   {
    170 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
    171     hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
    172 #else
    173     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
    174 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
    175   }
     165  HAL_Delay(350U);
     166
    176167  /* Primary detection: checks if connected to Standard Downstream Port
    177168  (without charging capability) */
    178   USBx->BCDR &= ~(USB_BCDR_DCDEN);
    179   HAL_Delay(50U);
    180169  USBx->BCDR |= (USB_BCDR_PDEN);
    181170  HAL_Delay(50U);
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c

    r20 r55  
    306306  * @retval None
    307307  */
    308 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
     308HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef const *sConfigPVD)
    309309{
    310310  /* Check the parameters */
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c

    r20 r55  
    672672  * @retval HAL status
    673673  */
    674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
     674HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef const *sConfigPVM)
    675675{
    676676  HAL_StatusTypeDef status = HAL_OK;
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c

    r20 r55  
    310310  * @retval HAL status
    311311  */
    312 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     312HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef  *RCC_OscInitStruct)
    313313{
    314314  uint32_t tickstart;
     
    764764  * @retval None
    765765  */
    766 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
     766HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
    767767{
    768768  uint32_t tickstart;
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c

    r20 r55  
    121121  * @retval HAL status
    122122  */
    123 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
     123HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit)
    124124{
    125125  uint32_t tmpregister;
     
    14061406void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
    14071407{
    1408   GPIO_InitTypeDef GPIO_InitStruct;
     1408  GPIO_InitTypeDef GPIO_InitStruct = {0};
    14091409  FlagStatus       pwrclkchanged = RESET;
    14101410  FlagStatus       backupchanged = RESET;
     
    15591559  * @retval None
    15601560  */
    1561 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
     1561void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef const *pInit)
    15621562{
    15631563  uint32_t value;
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc.c

    r25 r55  
    971971  * @retval HAL status
    972972  */
    973 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
     973HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
    974974{
    975975  uint32_t tmpreg;
     
    10991099  * @retval HAL status
    11001100  */
    1101 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
     1101HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
    11021102{
    11031103  uint32_t datetmpreg;
     
    16191619  * @retval HAL status
    16201620  */
    1621 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
     1621HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
    16221622{
    16231623  uint32_t tmpreg, subsecondtmpreg;
     
    18441844  * @retval HAL state
    18451845  */
    1846 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
     1846HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc)
    18471847{
    18481848  /* Return RTC handle state */
     
    20202020  * @retval operation see RTC_StoreOperation_Definitions
    20212021  */
    2022 uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
     2022uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc)
    20232023{
    20242024  return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc_ex.c

    r25 r55  
    14261426  tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
    14271427
    1428   if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
     1428  if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
    14291429  {
    14301430    tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c

    r20 r55  
    816816  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    817817  *               the configuration information for SPI module.
    818   * @param  pData pointer to data buffer
    819   * @param  Size amount of data to be sent
    820   * @param  Timeout Timeout duration
     818  * @param  pData pointer to data buffer (u8 or u16 data elements)
     819  * @param  Size amount of data elements (u8 or u16) to be sent
     820  * @param  Timeout Timeout duration in ms
    821821  * @retval HAL status
    822822  */
     
    10021002  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    10031003  *               the configuration information for SPI module.
    1004   * @param  pData pointer to data buffer
    1005   * @param  Size amount of data to be received
    1006   * @param  Timeout Timeout duration
     1004  * @param  pData pointer to data buffer (u8 or u16 data elements)
     1005  * @param  Size amount of data elements (u8 or u16) to be received
     1006  * @param  Timeout Timeout duration in ms
    10071007  * @retval HAL status
     1008  * @note   In master mode, if the direction is set to SPI_DIRECTION_2LINES
     1009  *         the receive buffer is written to data register (DR) to generate
     1010  *         clock pulses and receive data
    10081011  */
    10091012HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
     
    12441247  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    12451248  *               the configuration information for SPI module.
    1246   * @param  pTxData pointer to transmission data buffer
    1247   * @param  pRxData pointer to reception data buffer
    1248   * @param  Size amount of data to be sent and received
    1249   * @param  Timeout Timeout duration
     1249  * @param  pTxData pointer to transmission data buffer (u8 or u16 data elements)
     1250  * @param  pRxData pointer to reception data buffer (u8 or u16 data elements)
     1251  * @param  Size amount of data elements (u8 or u16) to be sent and received
     1252  * @param  Timeout Timeout duration in ms
    12501253  * @retval HAL status
    12511254  */
     
    15941597  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    15951598  *               the configuration information for SPI module.
    1596   * @param  pData pointer to data buffer
    1597   * @param  Size amount of data to be sent
     1599  * @param  pData pointer to data buffer (u8 or u16 data elements)
     1600  * @param  Size amount of data elements (u8 or u16) to be sent
    15981601  * @retval HAL status
    15991602  */
     
    16761679  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    16771680  *               the configuration information for SPI module.
    1678   * @param  pData pointer to data buffer
    1679   * @param  Size amount of data to be sent
     1681  * @param  pData pointer to data buffer (u8 or u16 data elements)
     1682  * @param  Size amount of data elements (u8 or u16) to be received
    16801683  * @retval HAL status
    16811684  */
     
    17791782  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    17801783  *               the configuration information for SPI module.
    1781   * @param  pTxData pointer to transmission data buffer
    1782   * @param  pRxData pointer to reception data buffer
    1783   * @param  Size amount of data to be sent and received
     1784  * @param  pTxData pointer to transmission data buffer (u8 or u16 data elements)
     1785  * @param  pRxData pointer to reception data buffer (u8 or u16 data elements)
     1786  * @param  Size amount of data elements (u8 or u16) to be sent and received
    17841787  * @retval HAL status
    17851788  */
     
    18881891  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    18891892  *               the configuration information for SPI module.
    1890   * @param  pData pointer to data buffer
    1891   * @param  Size amount of data to be sent
     1893  * @param  pData pointer to data buffer  (u8 or u16 data elements)
     1894  * @param  Size amount of data elements (u8 or u16) to be sent
    18921895  * @retval HAL status
    18931896  */
     
    20082011  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    20092012  *               the configuration information for SPI module.
    2010   * @param  pData pointer to data buffer
     2013  * @param  pData pointer to data buffer (u8 or u16 data elements)
    20112014  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
    2012   * @param  Size amount of data to be sent
     2015  * @param  Size amount of data elements (u8 or u16) to be received
    20132016  * @retval HAL status
    20142017  */
     
    21472150  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    21482151  *               the configuration information for SPI module.
    2149   * @param  pTxData pointer to transmission data buffer
    2150   * @param  pRxData pointer to reception data buffer
     2152  * @param  pTxData pointer to transmission data buffer (u8 or u16 data elements)
     2153  * @param  pRxData pointer to reception data buffer (u8 or u16 data elements)
    21512154  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
    2152   * @param  Size amount of data to be sent
     2155  * @param  Size amount of data elements (u8 or u16) to be sent and received
    21532156  * @retval HAL status
    21542157  */
     
    39963999        tmp_timeout = 0U;
    39974000      }
    3998       count--;
     4001      else
     4002      {
     4003        count--;
     4004      }
    39994005    }
    40004006  }
     
    40784084        tmp_timeout = 0U;
    40794085      }
    4080       count--;
     4086      else
     4087      {
     4088        count--;
     4089      }
    40814090    }
    40824091  }
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c

    r20 r55  
    10231023                      ##### IO operation functions #####
    10241024 ===============================================================================
     1025    [..]
    10251026    This subsection provides a set of functions allowing to manage the UART asynchronous
    10261027    and Half duplex data transfers.
    10271028
    1028     (#) There are two mode of transfer:
    1029        (+) Blocking mode: The communication is performed in polling mode.
    1030            The HAL status of all data processing is returned by the same function
    1031            after finishing transfer.
    1032        (+) Non-Blocking mode: The communication is performed using Interrupts
    1033            or DMA, These API's return the HAL status.
    1034            The end of the data processing will be indicated through the
    1035            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
    1036            using DMA mode.
    1037            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
    1038            will be executed respectively at the end of the transmit or Receive process
    1039            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
     1029    (#) There are two modes of transfer:
     1030       (++) Blocking mode: The communication is performed in polling mode.
     1031            The HAL status of all data processing is returned by the same function
     1032            after finishing transfer.
     1033       (++) Non-Blocking mode: The communication is performed using Interrupts
     1034            or DMA, These API's return the HAL status.
     1035            The end of the data processing will be indicated through the
     1036            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
     1037            using DMA mode.
     1038            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
     1039            will be executed respectively at the end of the transmit or Receive process
     1040            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
    10401041
    10411042    (#) Blocking mode API's are :
    1042         (+) HAL_UART_Transmit()
    1043         (+) HAL_UART_Receive()
     1043        (++) HAL_UART_Transmit()
     1044        (++) HAL_UART_Receive()
    10441045
    10451046    (#) Non-Blocking mode API's with Interrupt are :
    1046         (+) HAL_UART_Transmit_IT()
    1047         (+) HAL_UART_Receive_IT()
    1048         (+) HAL_UART_IRQHandler()
     1047        (++) HAL_UART_Transmit_IT()
     1048        (++) HAL_UART_Receive_IT()
     1049        (++) HAL_UART_IRQHandler()
    10491050
    10501051    (#) Non-Blocking mode API's with DMA are :
    1051         (+) HAL_UART_Transmit_DMA()
    1052         (+) HAL_UART_Receive_DMA()
    1053         (+) HAL_UART_DMAPause()
    1054         (+) HAL_UART_DMAResume()
    1055         (+) HAL_UART_DMAStop()
     1052        (++) HAL_UART_Transmit_DMA()
     1053        (++) HAL_UART_Receive_DMA()
     1054        (++) HAL_UART_DMAPause()
     1055        (++) HAL_UART_DMAResume()
     1056        (++) HAL_UART_DMAStop()
    10561057
    10571058    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
    1058         (+) HAL_UART_TxHalfCpltCallback()
    1059         (+) HAL_UART_TxCpltCallback()
    1060         (+) HAL_UART_RxHalfCpltCallback()
    1061         (+) HAL_UART_RxCpltCallback()
    1062         (+) HAL_UART_ErrorCallback()
     1059        (++) HAL_UART_TxHalfCpltCallback()
     1060        (++) HAL_UART_TxCpltCallback()
     1061        (++) HAL_UART_RxHalfCpltCallback()
     1062        (++) HAL_UART_RxCpltCallback()
     1063        (++) HAL_UART_ErrorCallback()
    10631064
    10641065    (#) Non-Blocking mode transfers could be aborted using Abort API's :
    1065         (+) HAL_UART_Abort()
    1066         (+) HAL_UART_AbortTransmit()
    1067         (+) HAL_UART_AbortReceive()
    1068         (+) HAL_UART_Abort_IT()
    1069         (+) HAL_UART_AbortTransmit_IT()
    1070         (+) HAL_UART_AbortReceive_IT()
     1066        (++) HAL_UART_Abort()
     1067        (++) HAL_UART_AbortTransmit()
     1068        (++) HAL_UART_AbortReceive()
     1069        (++) HAL_UART_Abort_IT()
     1070        (++) HAL_UART_AbortTransmit_IT()
     1071        (++) HAL_UART_AbortReceive_IT()
    10711072
    10721073    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
    1073         (+) HAL_UART_AbortCpltCallback()
    1074         (+) HAL_UART_AbortTransmitCpltCallback()
    1075         (+) HAL_UART_AbortReceiveCpltCallback()
     1074        (++) HAL_UART_AbortCpltCallback()
     1075        (++) HAL_UART_AbortTransmitCpltCallback()
     1076        (++) HAL_UART_AbortReceiveCpltCallback()
    10761077
    10771078    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
    10781079        reception services:
    1079         (+) HAL_UARTEx_RxEventCallback()
     1080        (++) HAL_UARTEx_RxEventCallback()
     1081
     1082    (#) Wakeup from Stop mode Callback:
     1083        (++) HAL_UARTEx_WakeupCallback()
    10801084
    10811085    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
    10821086        Errors are handled as follows :
    1083        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
    1084            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
    1085            in Interrupt mode reception .
    1086            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
    1087            to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
    1088            Transfer is kept ongoing on UART side.
    1089            If user wants to abort it, Abort services should be called by user.
    1090        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
    1091            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
    1092            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
    1093            user callback is executed.
     1087       (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
     1088            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
     1089            in Interrupt mode reception .
     1090            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
     1091            to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
     1092            Transfer is kept ongoing on UART side.
     1093            If user wants to abort it, Abort services should be called by user.
     1094       (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
     1095            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
     1096            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
     1097            user callback is executed.
    10941098
    10951099    -@- In the Half duplex communication, it is forbidden to run the transmit
     
    11691173        pdata8bits++;
    11701174      }
    1171       huart->TxXferCount--;
     1175      if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX)
     1176      {
     1177        huart->TxXferCount--;
     1178      }
     1179      else
     1180      {
     1181        /* Process was aborted during the transmission */
     1182        return HAL_ERROR;
     1183      }
    11721184    }
    11731185
     
    12651277        pdata8bits++;
    12661278      }
    1267       huart->RxXferCount--;
     1279      if (huart->RxState == HAL_UART_STATE_BUSY_RX)
     1280      {
     1281        huart->RxXferCount--;
     1282      }
     1283      else
     1284      {
     1285        /* Process was aborted during the reception */
     1286        return HAL_ERROR;
     1287      }
    12681288    }
    12691289
     
    17051725  }
    17061726
    1707   /* Reset Tx and Rx transfer counters */
    1708   huart->TxXferCount = 0U;
    1709   huart->RxXferCount = 0U;
    1710 
    17111727  /* Clear the Error flags in the ICR register */
    17121728  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
     
    17751791  }
    17761792
    1777   /* Reset Tx transfer counter */
    1778   huart->TxXferCount = 0U;
    1779 
    17801793  /* Flush the whole TX FIFO (if needed) */
    17811794  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
     
    18391852    }
    18401853  }
    1841 
    1842   /* Reset Rx transfer counter */
    1843   huart->RxXferCount = 0U;
    18441854
    18451855  /* Clear the Error flags in the ICR register */
     
    19681978  if (abortcplt == 1U)
    19691979  {
    1970     /* Reset Tx and Rx transfer counters */
    1971     huart->TxXferCount = 0U;
    1972     huart->RxXferCount = 0U;
    1973 
    19741980    /* Clear ISR function pointers */
    19751981    huart->RxISR = NULL;
     
    20512057    else
    20522058    {
    2053       /* Reset Tx transfer counter */
    2054       huart->TxXferCount = 0U;
    20552059
    20562060      /* Clear TxISR function pointers */
     
    20722076  else
    20732077  {
    2074     /* Reset Tx transfer counter */
    2075     huart->TxXferCount = 0U;
    2076 
    20772078    /* Clear TxISR function pointers */
    20782079    huart->TxISR = NULL;
     
    21482149    else
    21492150    {
    2150       /* Reset Rx transfer counter */
    2151       huart->RxXferCount = 0U;
    2152 
    21532151      /* Clear RxISR function pointer */
    21542152      huart->pRxBuffPtr = NULL;
     
    21762174  else
    21772175  {
    2178     /* Reset Rx transfer counter */
    2179     huart->RxXferCount = 0U;
    2180 
    21812176    /* Clear RxISR function pointer */
    21822177    huart->pRxBuffPtr = NULL;
     
    37103705  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
    37113706  {
     3707    huart->RxXferCount = 0;
     3708
     3709    /* Check current nb of data still to be received on DMA side.
     3710       DMA Normal mode, remaining nb of data will be 0
     3711       DMA Circular mode, remaining nb of data is reset to RxXferSize */
     3712    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
     3713    if (nb_remaining_rx_data < huart->RxXferSize)
     3714    {
     3715      /* Update nb of remaining data */
     3716      huart->RxXferCount = nb_remaining_rx_data;
     3717    }
     3718
    37123719#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    37133720    /*Call registered Rx Event callback*/
    3714     huart->RxEventCallback(huart, huart->RxXferSize);
     3721    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37153722#else
    37163723    /*Call legacy weak Rx Event callback*/
    3717     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
     3724    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37183725#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    37193726  }
     
    37483755  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
    37493756  {
     3757    huart->RxXferCount = huart->RxXferSize / 2U;
     3758
     3759    /* Check current nb of data still to be received on DMA side. */
     3760    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
     3761    if (nb_remaining_rx_data <= huart->RxXferSize)
     3762    {
     3763      /* Update nb of remaining data */
     3764      huart->RxXferCount = nb_remaining_rx_data;
     3765    }
     3766
    37503767#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    37513768    /*Call registered Rx Event callback*/
    3752     huart->RxEventCallback(huart, huart->RxXferSize / 2U);
     3769    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37533770#else
    37543771    /*Call legacy weak Rx Event callback*/
    3755     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
     3772    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37563773#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    37573774  }
     
    37853802      (gstate == HAL_UART_STATE_BUSY_TX))
    37863803  {
    3787     huart->TxXferCount = 0U;
    37883804    UART_EndTxTransfer(huart);
    37893805  }
     
    37933809      (rxstate == HAL_UART_STATE_BUSY_RX))
    37943810  {
    3795     huart->RxXferCount = 0U;
    37963811    UART_EndRxTransfer(huart);
    37973812  }
     
    38173832{
    38183833  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
    3819   huart->RxXferCount = 0U;
    38203834
    38213835#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
     
    38503864    }
    38513865  }
    3852 
    3853   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
    3854   huart->TxXferCount = 0U;
    3855   huart->RxXferCount = 0U;
    38563866
    38573867  /* Reset errorCode */
     
    39063916  }
    39073917
    3908   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
    3909   huart->TxXferCount = 0U;
    3910   huart->RxXferCount = 0U;
    3911 
    39123918  /* Reset errorCode */
    39133919  huart->ErrorCode = HAL_UART_ERROR_NONE;
     
    39473953  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
    39483954
    3949   huart->TxXferCount = 0U;
    3950 
    39513955  /* Flush the whole TX FIFO (if needed) */
    39523956  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
     
    39793983{
    39803984  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
    3981 
    3982   huart->RxXferCount = 0U;
    39833985
    39843986  /* Clear the Error flags in the ICR register */
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c

    r20 r55  
    2525               ##### UART peripheral extended features  #####
    2626  ==============================================================================
    27 
     27  [..]
    2828    (#) Declare a UART_HandleTypeDef handle structure.
    2929
     
    254254                      ##### IO operation functions #####
    255255 ===============================================================================
     256    [..]
    256257    This subsection provides a set of Wakeup and FIFO mode related callback functions.
    257 
    258258    (#) Wakeup from Stop mode Callback:
    259         (+) HAL_UARTEx_WakeupCallback()
    260 
     259        (++) HAL_UARTEx_WakeupCallback()
    261260    (#) TX/RX Fifos Callbacks:
    262         (+) HAL_UARTEx_RxFifoFullCallback()
    263         (+) HAL_UARTEx_TxFifoEmptyCallback()
    264 
     261        (++) HAL_UARTEx_RxFifoFullCallback()
     262        (++) HAL_UARTEx_TxFifoEmptyCallback()
    265263@endverbatim
    266264  * @{
     
    342340        data elements as reception completion criteria, these functions also consider additional events
    343341        as triggers for updating reception status to caller :
    344        (+) Detection of inactivity period (RX line has not been active for a given period).
    345           (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
     342       (++) Detection of inactivity period (RX line has not been active for a given period).
     343          (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
    346344               for 1 frame time, after last received byte.
    347           (++) RX inactivity detected by RTO, i.e. line has been in idle state
     345          (+++) RX inactivity detected by RTO, i.e. line has been in idle state
    348346               for a programmable time, after last received byte.
    349        (+) Detection that a specific character has been received.
    350 
    351     (#) There are two mode of transfer:
    352        (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
     347       (++) Detection that a specific character has been received.
     348
     349    (#) There are two modes of transfer:
     350       (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
    353351           or till IDLE event occurs. Reception is handled only during function execution.
    354352           When function exits, no data reception could occur. HAL status and number of actually received data elements,
    355353           are returned by function after finishing transfer.
    356        (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
     354       (++) Non-Blocking mode: The reception is performed using Interrupts or DMA.
    357355           These API's return the HAL status.
    358356           The end of the data processing will be indicated through the
     
    362360
    363361    (#) Blocking mode API:
    364         (+) HAL_UARTEx_ReceiveToIdle()
     362        (++) HAL_UARTEx_ReceiveToIdle()
    365363
    366364    (#) Non-Blocking mode API with Interrupt:
    367         (+) HAL_UARTEx_ReceiveToIdle_IT()
     365        (++) HAL_UARTEx_ReceiveToIdle_IT()
    368366
    369367    (#) Non-Blocking mode API with DMA:
    370         (+) HAL_UARTEx_ReceiveToIdle_DMA()
     368        (++) HAL_UARTEx_ReceiveToIdle_DMA()
    371369
    372370@endverbatim
     
    943941  *        to Rx Event callback execution.
    944942  * @note  This function is expected to be called within the user implementation of Rx Event Callback,
    945   *        in order to provide the accurate value :
    946   *        In Interrupt Mode :
    947   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
    948   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
    949   *             received data is lower than expected one)
    950   *        In DMA Mode :
    951   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
    952   *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
    953   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
    954   *             received data is lower than expected one).
    955   *        In DMA mode, RxEvent callback could be called several times;
     943  *        in order to provide the accurate value.
     944  * @note  In Interrupt Mode:
     945  *        - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received).
     946  *        - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed.
     947  * @note  In DMA Mode:
     948  *        - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received).
     949  *        - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received.
     950  *        - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed.
     951  * @note  In DMA mode, RxEvent callback could be called several times;
    956952  *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
    957953  *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c

    r20 r55  
    3434      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
    3535
     36      (#)NOTE: For applications not using double buffer mode, define the symbol
     37                'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint.
     38
    3639  @endverbatim
    3740
     
    6265  * @retval HAL status
    6366  */
    64 HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
     67HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg)
    6568{
    6669  /* Prevent unused argument(s) compilation warning */
     
    131134  * @retval HAL status
    132135  */
    133 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
     136HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode)
    134137{
    135138  /* Prevent unused argument(s) compilation warning */
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