Ignore:
Timestamp:
Apr 1, 2026, 9:33:58 AM (5 weeks ago)
Author:
f.jahn
Message:

Fixing Projects.

Location:
trunk/fw_g473rct/Drivers
Files:
47 edited

Legend:

Unmodified
Added
Removed

  • trunk/fw_g473rct/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g473xx.h

    r20 r55  
    33503350/********************  Bits definition for DMAMUX_CxCR register  **************/
    33513351#define DMAMUX_CxCR_DMAREQ_ID_Pos                    (0U)
    3352 #define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
     3352#define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
    33533353#define DMAMUX_CxCR_DMAREQ_ID                        DMAMUX_CxCR_DMAREQ_ID_Msk
    33543354#define DMAMUX_CxCR_DMAREQ_ID_0                      (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
    … …  
    33593359#define DMAMUX_CxCR_DMAREQ_ID_5                      (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
    33603360#define DMAMUX_CxCR_DMAREQ_ID_6                      (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
     3361
     3362/* Legacy defines */
    33613363#define DMAMUX_CxCR_DMAREQ_ID_7                      (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
    33623364
    … …  
    93459347#define RNG_CR_IE           RNG_CR_IE_Msk
    93469348#define RNG_CR_CED_Pos      (5U)
    9347 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000020 */
    9348 #define RNG_CR_CED          RNG_CR_IE_Msk
     9349#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                           /*!< 0x00000020 */
     9350#define RNG_CR_CED          RNG_CR_CED_Msk
    93499351
    93509352/********************  Bits definition for RNG_SR register  *******************/
    … …  
    1182311825/*******************  Bit definition for TIM_CCR1 register  *******************/
    1182411826#define TIM_CCR1_CCR1_Pos         (0U)
    11825 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
     11827#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
    1182611828#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
    1182711829
    1182811830/*******************  Bit definition for TIM_CCR2 register  *******************/
    1182911831#define TIM_CCR2_CCR2_Pos         (0U)
    11830 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
     11832#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
    1183111833#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
    1183211834
    1183311835/*******************  Bit definition for TIM_CCR3 register  *******************/
    1183411836#define TIM_CCR3_CCR3_Pos         (0U)
    11835 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
     11837#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
    1183611838#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
    1183711839
    1183811840/*******************  Bit definition for TIM_CCR4 register  *******************/
    1183911841#define TIM_CCR4_CCR4_Pos         (0U)
    11840 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
     11842#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
    1184111843#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
    1184211844
    1184311845/*******************  Bit definition for TIM_CCR5 register  *******************/
    1184411846#define TIM_CCR5_CCR5_Pos         (0U)
    11845 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
     11847#define TIM_CCR5_CCR5_Msk         (0xFFFFFUL << TIM_CCR5_CCR5_Pos)             /*!< 0x000FFFFF */
    1184611848#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
    1184711849#define TIM_CCR5_GC5C1_Pos        (29U)
    … …  
    1185711859/*******************  Bit definition for TIM_CCR6 register  *******************/
    1185811860#define TIM_CCR6_CCR6_Pos         (0U)
    11859 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
     11861#define TIM_CCR6_CCR6_Msk         (0xFFFFFUL << TIM_CCR6_CCR6_Pos)             /*!< 0x000FFFFF */
    1186011862#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
    1186111863

  • trunk/fw_g473rct/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h

    r20 r55  
    8989
    9090/**
    91   * @brief CMSIS Device version number V1.2.5
     91  * @brief CMSIS Device version number V1.2.6
    9292  */
    9393#define __STM32G4_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
    9494#define __STM32G4_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
    95 #define __STM32G4_CMSIS_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */
     95#define __STM32G4_CMSIS_VERSION_SUB2   (0x06U) /*!< [15:8]  sub2 version */
    9696#define __STM32G4_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
    9797#define __STM32G4_CMSIS_VERSION        ((__STM32G4_CMSIS_VERSION_MAIN << 24)\

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

    r20 r55  
    12801280#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
    12811281
    1282 #if defined(STM32H5) || defined(STM32H7RS)
     1282#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
    12831283#define TAMP_SECRETDEVICE_ERASE_NONE        TAMP_DEVICESECRETS_ERASE_NONE
    12841284#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM    TAMP_DEVICESECRETS_ERASE_BKPSRAM
    1285 #endif /* STM32H5 || STM32H7RS */
     1285#endif /* STM32H5 || STM32H7RS || STM32N6 */
    12861286
    12871287#if defined(STM32WBA)
    … …  
    12951295#endif /* STM32WBA */
    12961296
    1297 #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
     1297#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
    12981298#define TAMP_SECRETDEVICE_ERASE_DISABLE     TAMP_DEVICESECRETS_ERASE_NONE
    12991299#define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
    1300 #endif /* STM32H5 || STM32WBA || STM32H7RS */
     1300#endif /* STM32H5 || STM32WBA || STM32H7RS ||  STM32N6 */
    13011301
    13021302#if defined(STM32F7)
    … …  
    14821482#endif
    14831483
    1484 #if defined(STM32U5)
     1484#if defined(STM32U5) || defined(STM32MP2)
    14851485#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
    14861486#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
    … …  
    20302030  * @{
    20312031  */
    2032 #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
     2032#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
    20332033#define HAL_RTCEx_SetBoothardwareKey            HAL_RTCEx_LockBootHardwareKey
    20342034#define HAL_RTCEx_BKUPBlock_Enable              HAL_RTCEx_BKUPBlock
    20352035#define HAL_RTCEx_BKUPBlock_Disable             HAL_RTCEx_BKUPUnblock
    20362036#define HAL_RTCEx_Erase_SecretDev_Conf          HAL_RTCEx_ConfigEraseDeviceSecrets
    2037 #endif /* STM32H5 || STM32WBA || STM32H7RS */
     2037#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
    20382038
    20392039/**
    … …  
    36963696
    36973697#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
    3698     defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
     3698      defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
    36993699#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
    37003700#else
    … …  
    39473947#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
    39483948    defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
    3949     defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) ||  defined (STM32U0)
     3949    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) ||  \
     3950    defined (STM32U0) || defined (STM32U3)
    39503951#else
    39513952#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h

    r20 r55  
    828828#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
    829829#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
    830   ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
     830  ((((__HANDLE__)->Instance) != ADC2) && (((__HANDLE__)->Instance) != ADC4))
    831831#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
    832832#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) != ADC2)

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h

    r20 r55  
    309309  * @{
    310310  */
    311 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
    312 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
     311uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength);
     312uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength);
    313313/**
    314314  * @}

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h

    r20 r55  
    196196/* ------------------------- REQUEST -----------------------------------------*/
    197197HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
    198                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
     198                                                      const HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
    199199HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
    200200HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
    … …  
    202202
    203203/* ------------------------- SYNCHRO -----------------------------------------*/
    204 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
     204HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, const HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
    205205/* -------------------------------------------------------------------------- */
    206206

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h

    r20 r55  
    273273  */
    274274/* Configuration functions ****************************************************/
    275 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
    276 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
    277 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
     275HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef const *pExtiConfig);
     276HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef const *hexti, EXTI_ConfigTypeDef *pExtiConfig);
     277HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef const *hexti);
    278278HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
    279279HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
    … …  
    287287  */
    288288/* IO operation functions *****************************************************/
    289 void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
    290 uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
    291 void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
    292 void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
     289void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef const *hexti);
     290uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge);
     291void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge);
     292void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef const *hexti);
    293293
    294294/**

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h

    r20 r55  
    283283
    284284/* Initialization and de-initialization functions *****************************/
    285 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
     285void              HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init);
    286286void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
    287287
    … …  
    296296
    297297/* IO operation functions *****************************************************/
    298 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
     298GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef const *GPIOx, uint16_t GPIO_Pin);
    299299void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
    300300void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h

    r20 r55  
    165165#define PCD_PHY_ULPI                 1U
    166166#define PCD_PHY_EMBEDDED             2U
     167#define PCD_HS_PHY_EMBEDDED          3U
    167168#define PCD_PHY_UTMI                 3U
    168169/**
    … …  
    367368
    368369
    369 #define USB_WAKEUP_EXTI_LINE                                          (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
     370#define USB_WAKEUP_EXTI_LINE                                          (0x1UL << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
    370371
    371372
    … …  
    419420
    420421/********************  Bit definition for USB_COUNTn_RX register  *************/
    421 #define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)
    422 #define USB_CNTRX_BLSIZE                      (0x1U << 15)
     422#define USB_CNTRX_NBLK_MSK                    (0x1FUL << 10)
     423#define USB_CNTRX_BLSIZE                      (0x1UL << 15)
    423424
    424425/* SetENDPOINT */
    … …  
    809810    if ((wCount) == 0U) \
    810811    { \
    811       *(pdwReg) |= USB_CNTRX_BLSIZE; \
     812      *(pdwReg) |= (uint16_t)USB_CNTRX_BLSIZE; \
    812813    } \
    813814    else if ((wCount) <= 62U) \

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h

    r20 r55  
    365365
    366366/* Peripheral Control functions  ************************************************/
    367 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
     367HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef const *sConfigPVD);
    368368void HAL_PWR_EnablePVD(void);
    369369void HAL_PWR_DisablePVD(void);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h

    r20 r55  
    765765void HAL_PWREx_EnablePVM4(void);
    766766void HAL_PWREx_DisablePVM4(void);
    767 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
     767HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef const *sConfigPVM);
    768768
    769769/* Low Power modes configuration functions ************************************/

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h

    r20 r55  
    33563356/* Initialization and de-initialization functions  ******************************/
    33573357HAL_StatusTypeDef HAL_RCC_DeInit(void);
    3358 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
    3359 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
     3358HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct);
     3359HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
    33603360
    33613361/**

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h

    r20 r55  
    12691269  */
    12701270
    1271 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
     1271HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit);
    12721272void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
    12731273uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
    … …  
    12971297  */
    12981298
    1299 void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
     1299void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef const *pInit);
    13001300void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
    13011301void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h

    r25 r55  
    823823/* RTC Time and Date functions ************************************************/
    824824HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
    825 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
     825HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
    826826HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
    827 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
     827HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
    828828void              HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
    829829void              HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
    830830void              HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
    831831void              HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
    832 uint32_t          HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
     832uint32_t          HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc);
    833833/**
    834834  * @}
    … …  
    842842HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
    843843HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
    844 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
     844HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
    845845void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
    846846HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
    … …  
    863863  */
    864864/* Peripheral State functions *************************************************/
    865 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
     865HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc);
    866866/**
    867867  * @}

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h

    r20 r55  
    4848  uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
    4949                                         The baud rate register is computed using the following formula:
    50                                          LPUART:
    51                                          =======
     50                                         @note For LPUART :
    5251                                         Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
    53                                          where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
    54                                          UART:
    55                                          =====
     52                                         where lpuart_ker_ck_pres is the UART input clock divided by a prescaler.
     53                                         @note For UART :
    5654                                         - If oversampling is 16 or in LIN mode,
    5755                                            Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
    … …  
    12891287  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
    12901288  */
    1291 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
     1289#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
    12921290
    12931291/** @brief  Check UART assertion time.

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h

    r20 r55  
    8282#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
    8383
    84 
    85 
    8684/* Internal mask for ADC group injected sequencer:                            */
    8785/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
    … …  
    107105#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
    108106#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
    109 
    110 
    111107
    112108/* Internal mask for ADC group regular trigger:                               */
    … …  
    138134#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
    139135
    140 
    141 
    142136/* Internal mask for ADC group injected trigger:                              */
    143137/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
    … …  
    167161#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (ADC_JSQR_JEXTSEL_Pos)
    168162#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
    169 
    170 
    171 
    172 
    173 
    174163
    175164/* Internal mask for ADC channel:                                             */
    … …  
    368357/* ADC internal channels related definitions */
    369358/* Internal voltage reference VrefInt */
    370 #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
     359#define VREFINT_CAL_ADDR                   ((const uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
    371360                                           parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
    372361                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
    … …  
    375364                                           (tolerance: +-10 mV) (unit: mV). */
    376365/* Temperature sensor */
    377 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4,
     366#define TEMPSENSOR_CAL1_ADDR               ((const uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1:
    378367                                           temperature sensor ADC raw data acquired at temperature  30 DegC
    379368                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
    380 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4,
    381                                            temperature sensor ADC raw data acquired at temperature 110 DegC
     369#define TEMPSENSOR_CAL2_ADDR               ((const uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2:
     370                                           temperature sensor ADC raw data acquired at temperature 130 DegC
    382371                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
    383372#define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Temperature at which temperature sensor
    384373                                           has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
    385374                                           (tolerance: +-5 DegC) (unit: DegC). */
    386 #define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Temperature at which temperature sensor
     375#define TEMPSENSOR_CAL2_TEMP               (130L)                       /* Temperature at which temperature sensor
    387376                                           has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
    388377                                           (tolerance: +-5 DegC) (unit: DegC). */
    … …  
    394383  * @}
    395384  */
    396 
    397385
    398386/* Private macros ------------------------------------------------------------*/
    … …  
    415403  * @}
    416404  */
    417 
    418405
    419406/* Exported types ------------------------------------------------------------*/

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h

    r20 r55  
    77  * @attention
    88  *
    9   * Copyright (c) 2018 STMicroelectronics.
     9  * Copyright (c) 2019 STMicroelectronics.
    1010  * All rights reserved.
    1111  *
    … …  
    1818
    1919/* Define to prevent recursive inclusion -------------------------------------*/
    20 #ifndef __STM32G4xx_LL_CRS_H
    21 #define __STM32G4xx_LL_CRS_H
     20#ifndef STM32G4xx_LL_CRS_H
     21#define STM32G4xx_LL_CRS_H
    2222
    2323#ifdef __cplusplus
    … …  
    4242/* Private constants ---------------------------------------------------------*/
    4343/* Private macros ------------------------------------------------------------*/
    44 
    4544/* Exported types ------------------------------------------------------------*/
    4645/* Exported constants --------------------------------------------------------*/
    … …  
    7978  * @{
    8079  */
    81 #define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
     80#define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
    8281#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
    8382#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
    … …  
    9493  * @{
    9594  */
    96 #define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal source GPIO */
     95#define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal source GPIO */
    9796#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
    9897#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
    … …  
    104103  * @{
    105104  */
    106 #define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
     105#define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
    107106#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
    108107/**
    … …  
    113112  * @{
    114113  */
    115 #define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
    116 #define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
     114#define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */
     115#define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR      /*!< Downcounting direction, the actual frequency is below the target */
    117116/**
    118117  * @}
    … …  
    127126  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
    128127  */
    129 #define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)
     128#define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
    130129
    131130/**
    132131  * @brief Reset value of Frequency error limit.
    133132  */
    134 #define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)
     133#define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
    135134
    136135/**
    137136  * @brief Reset value of the HSI48 Calibration field
    138   * @note The default value is 64, which corresponds to the middle of the trimming interval.
     137  * @note The default value is 64,
     138  *       which corresponds to the middle of the trimming interval.
    139139  *       The trimming step is specified in the product datasheet.
    140   *       A higher TRIM value corresponds to a higher output frequency
    141   */
    142 #define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x40U)
    143 /**
    144   * @}
    145   */
     140  *       A higher TRIM value corresponds to a higher output frequency.
     141  */
     142#define LL_CRS_HSI48CALIBRATION_DEFAULT     0x00000040U
     143/**
     144  * @}
     145  */
     146
    146147/**
    147148  * @}
    … …  
    441442  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
    442443  * @param  Settings This parameter can be a combination of the following values:
    443   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
    444   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
     444  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4
     445  *              or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32
     446  *              or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
    445447  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
    446448  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
    … …  
    450452                                                  uint32_t ReloadValue, uint32_t Settings)
    451453{
    452   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
     454  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
     455
    453456  MODIFY_REG(CRS->CFGR,
    454457             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
    … …  
    778781#endif
    779782
    780 #endif /* __STM32G4xx_LL_CRS_H */
    781 
     783#endif /* STM32G4xx_LL_CRS_H */

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h

    r20 r55  
    555555  * @retval None
    556556  */
    557 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
     557__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
    558558{
    559559  (void)(DMAMUXx);
    … …  
    705705  *         (*) Not on all G4 devices
    706706  */
    707 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     707__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    708708{
    709709  (void)(DMAMUXx);
    … …  
    735735  * @retval None
    736736  */
    737 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
     737__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
    738738{
    739739  (void)(DMAMUXx);
    … …  
    764764  * @retval Between Min_Data = 1 and Max_Data = 32
    765765  */
    766 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     766__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    767767{
    768768  (void)(DMAMUXx);
    … …  
    798798  * @retval None
    799799  */
    800 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
     800__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
    801801{
    802802  (void)(DMAMUXx);
    … …  
    831831  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
    832832  */
    833 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     833__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    834834{
    835835  (void)(DMAMUXx);
    … …  
    860860  * @retval None
    861861  */
    862 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     862__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    863863{
    864864  (void)(DMAMUXx);
    … …  
    889889  * @retval None
    890890  */
    891 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     891__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    892892{
    893893  (void)(DMAMUXx);
    … …  
    918918  * @retval State of bit (1 or 0).
    919919  */
    920 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     920__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    921921{
    922922  (void)(DMAMUXx);
    … …  
    947947  * @retval None
    948948  */
    949 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     949__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    950950{
    951951  (void)(DMAMUXx);
    … …  
    976976  * @retval None
    977977  */
    978 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     978__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    979979{
    980980  (void)(DMAMUXx);
    … …  
    10051005  * @retval State of bit (1 or 0).
    10061006  */
    1007 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     1007__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    10081008{
    10091009  (void)(DMAMUXx);
    … …  
    10561056  * @retval None
    10571057  */
    1058 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
     1058__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
    10591059{
    10601060  (void)(DMAMUXx);
    … …  
    11061106  *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
    11071107  */
    1108 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     1108__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    11091109{
    11101110  (void)(DMAMUXx);
    … …  
    11231123  * @retval None
    11241124  */
    1125 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1125__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    11261126{
    11271127  (void)(DMAMUXx);
    … …  
    11401140  * @retval None
    11411141  */
    1142 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1142__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    11431143{
    11441144  (void)(DMAMUXx);
    … …  
    11571157  * @retval State of bit (1 or 0).
    11581158  */
    1159 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1159__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    11601160{
    11611161  (void)(DMAMUXx);
    … …  
    11791179  * @retval None
    11801180  */
    1181 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
     1181__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
    11821182                                                     uint32_t Polarity)
    11831183{
    … …  
    12021202  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
    12031203  */
    1204 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1204__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    12051205{
    12061206  UNUSED(DMAMUXx);
    … …  
    12221222  * @retval None
    12231223  */
    1224 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
     1224__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
    12251225                                               uint32_t RequestNb)
    12261226{
    … …  
    12411241  * @retval Between Min_Data = 1 and Max_Data = 32
    12421242  */
    1243 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1243__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    12441244{
    12451245  UNUSED(DMAMUXx);
    … …  
    12811281  * @retval None
    12821282  */
    1283 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
     1283__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
    12841284                                                  uint32_t RequestSignalID)
    12851285{
    … …  
    13211321  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
    13221322  */
    1323 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1323__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    13241324{
    13251325  UNUSED(DMAMUXx);
    … …  
    13421342  * @retval State of bit (1 or 0).
    13431343  */
    1344 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
     1344__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
    13451345{
    13461346  UNUSED(DMAMUXx);
    … …  
    13541354  * @retval State of bit (1 or 0).
    13551355  */
    1356 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
     1356__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
    13571357{
    13581358  UNUSED(DMAMUXx);
    … …  
    13661366  * @retval State of bit (1 or 0).
    13671367  */
    1368 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
     1368__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
    13691369{
    13701370  UNUSED(DMAMUXx);
    … …  
    13781378  * @retval State of bit (1 or 0).
    13791379  */
    1380 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
     1380__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
    13811381{
    13821382  UNUSED(DMAMUXx);
    … …  
    13901390  * @retval State of bit (1 or 0).
    13911391  */
    1392 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
     1392__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
    13931393{
    13941394  UNUSED(DMAMUXx);
    … …  
    14021402  * @retval State of bit (1 or 0).
    14031403  */
    1404 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
     1404__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14051405{
    14061406  UNUSED(DMAMUXx);
    … …  
    14141414  * @retval State of bit (1 or 0).
    14151415  */
    1416 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
     1416__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14171417{
    14181418  UNUSED(DMAMUXx);
    … …  
    14261426  * @retval State of bit (1 or 0).
    14271427  */
    1428 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
     1428__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14291429{
    14301430  UNUSED(DMAMUXx);
    … …  
    14381438  * @retval State of bit (1 or 0).
    14391439  */
    1440 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
     1440__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14411441{
    14421442  UNUSED(DMAMUXx);
    … …  
    14501450  * @retval State of bit (1 or 0).
    14511451  */
    1452 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
     1452__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14531453{
    14541454  UNUSED(DMAMUXx);
    … …  
    14621462  * @retval State of bit (1 or 0).
    14631463  */
    1464 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
     1464__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14651465{
    14661466  UNUSED(DMAMUXx);
    … …  
    14741474  * @retval State of bit (1 or 0).
    14751475  */
    1476 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
     1476__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14771477{
    14781478  UNUSED(DMAMUXx);
    … …  
    14871487  * @retval State of bit (1 or 0).
    14881488  */
    1489 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
     1489__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx)
    14901490{
    14911491  UNUSED(DMAMUXx);
    … …  
    15011501  * @retval State of bit (1 or 0).
    15021502  */
    1503 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
     1503__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15041504{
    15051505  UNUSED(DMAMUXx);
    … …  
    15151515  * @retval State of bit (1 or 0).
    15161516  */
    1517 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
     1517__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15181518{
    15191519  UNUSED(DMAMUXx);
    … …  
    15291529  * @retval State of bit (1 or 0).
    15301530  */
    1531 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
     1531__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15321532{
    15331533  UNUSED(DMAMUXx);
    … …  
    15421542  * @retval State of bit (1 or 0).
    15431543  */
    1544 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
     1544__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15451545{
    15461546  UNUSED(DMAMUXx);
    … …  
    15541554  * @retval State of bit (1 or 0).
    15551555  */
    1556 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
     1556__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15571557{
    15581558  UNUSED(DMAMUXx);
    … …  
    15661566  * @retval State of bit (1 or 0).
    15671567  */
    1568 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
     1568__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15691569{
    15701570  UNUSED(DMAMUXx);
    … …  
    15781578  * @retval State of bit (1 or 0).
    15791579  */
    1580 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
     1580__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15811581{
    15821582  UNUSED(DMAMUXx);
    … …  
    15901590  * @retval None
    15911591  */
    1592 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
     1592__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
    15931593{
    15941594  UNUSED(DMAMUXx);
    … …  
    16021602  * @retval None
    16031603  */
    1604 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
     1604__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16051605{
    16061606  UNUSED(DMAMUXx);
    … …  
    16141614  * @retval None
    16151615  */
    1616 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
     1616__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16171617{
    16181618  UNUSED(DMAMUXx);
    … …  
    16261626  * @retval None
    16271627  */
    1628 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
     1628__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16291629{
    16301630  UNUSED(DMAMUXx);
    … …  
    16381638  * @retval None
    16391639  */
    1640 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
     1640__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16411641{
    16421642  UNUSED(DMAMUXx);
    … …  
    16501650  * @retval None
    16511651  */
    1652 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
     1652__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16531653{
    16541654  UNUSED(DMAMUXx);
    … …  
    16621662  * @retval None
    16631663  */
    1664 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
     1664__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16651665{
    16661666  UNUSED(DMAMUXx);
    … …  
    16741674  * @retval None
    16751675  */
    1676 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
     1676__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16771677{
    16781678  UNUSED(DMAMUXx);
    … …  
    16861686  * @retval None
    16871687  */
    1688 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
     1688__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
    16891689{
    16901690  UNUSED(DMAMUXx);
    … …  
    16981698  * @retval None
    16991699  */
    1700 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
     1700__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17011701{
    17021702  UNUSED(DMAMUXx);
    … …  
    17101710  * @retval None
    17111711  */
    1712 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
     1712__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17131713{
    17141714  UNUSED(DMAMUXx);
    … …  
    17221722  * @retval None
    17231723  */
    1724 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
     1724__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17251725{
    17261726  UNUSED(DMAMUXx);
    … …  
    17351735  * @retval None
    17361736  */
    1737 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
     1737__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17381738{
    17391739  UNUSED(DMAMUXx);
    … …  
    17491749  * @retval None
    17501750  */
    1751 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
     1751__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17521752{
    17531753  UNUSED(DMAMUXx);
    … …  
    17631763  * @retval None
    17641764  */
    1765 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
     1765__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17661766{
    17671767  UNUSED(DMAMUXx);
    … …  
    17771777  * @retval None
    17781778  */
    1779 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
     1779__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17801780{
    17811781  UNUSED(DMAMUXx);
    … …  
    17901790  * @retval None
    17911791  */
    1792 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
     1792__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
    17931793{
    17941794  UNUSED(DMAMUXx);
    … …  
    18021802  * @retval None
    18031803  */
    1804 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
     1804__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
    18051805{
    18061806  UNUSED(DMAMUXx);
    … …  
    18141814  * @retval None
    18151815  */
    1816 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
     1816__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
    18171817{
    18181818  UNUSED(DMAMUXx);
    … …  
    18261826  * @retval None
    18271827  */
    1828 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
     1828__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
    18291829{
    18301830  UNUSED(DMAMUXx);
    … …  
    18631863  * @retval None
    18641864  */
    1865 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     1865__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    18661866{
    18671867  (void)(DMAMUXx);
    … …  
    18921892  * @retval None
    18931893  */
    1894 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     1894__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    18951895{
    18961896  (void)(DMAMUXx);
    … …  
    19211921  * @retval State of bit (1 or 0).
    19221922  */
    1923 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
     1923__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
    19241924{
    19251925  (void)(DMAMUXx);
    … …  
    19381938  * @retval None
    19391939  */
    1940 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1940__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    19411941{
    19421942  UNUSED(DMAMUXx);
    … …  
    19561956  * @retval None
    19571957  */
    1958 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1958__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    19591959{
    19601960  UNUSED(DMAMUXx);
    … …  
    19741974  * @retval State of bit (1 or 0).
    19751975  */
    1976 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
     1976__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
    19771977{
    19781978  UNUSED(DMAMUXx);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h

    r20 r55  
    317317  *         @arg @ref LL_GPIO_MODE_ANALOG
    318318  */
    319 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
     319__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef const *GPIOx, uint32_t Pin)
    320320{
    321321  return (uint32_t)(READ_BIT(GPIOx->MODER,
    … …  
    386386  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
    387387  */
    388 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
     388__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef const *GPIOx, uint32_t Pin)
    389389{
    390390  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
    … …  
    460460  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
    461461  */
    462 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
     462__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef const *GPIOx, uint32_t Pin)
    463463{
    464464  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
    … …  
    526526  *         @arg @ref LL_GPIO_PULL_DOWN
    527527  */
    528 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
     528__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef const *GPIOx, uint32_t Pin)
    529529{
    530530  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
    … …  
    603603  *         @arg @ref LL_GPIO_AF_15
    604604  */
    605 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
     605__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef const *GPIOx, uint32_t Pin)
    606606{
    607607  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
    … …  
    681681  *         @arg @ref LL_GPIO_AF_15
    682682  */
    683 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
     683__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef const *GPIOx, uint32_t Pin)
    684684{
    685685  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
    … …  
    752752  * @retval State of bit (1 or 0).
    753753  */
    754 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
     754__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef const *GPIOx, uint32_t PinMask)
    755755{
    756756  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
    … …  
    763763  * @retval State of bit (1 or 0).
    764764  */
    765 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
     765__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef const *GPIOx)
    766766{
    767767  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
    … …  
    782782  * @retval Input data register value of port
    783783  */
    784 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
     784__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef const *GPIOx)
    785785{
    786786  return (uint32_t)(READ_REG(GPIOx->IDR));
    … …  
    811811  * @retval State of bit (1 or 0).
    812812  */
    813 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
     813__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef const *GPIOx, uint32_t PinMask)
    814814{
    815815  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
    … …  
    834834  * @retval Output data register value of port
    835835  */
    836 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
     836__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef const *GPIOx)
    837837{
    838838  return (uint32_t)(READ_REG(GPIOx->ODR));
    … …  
    863863  * @retval State of bit (1 or 0).
    864864  */
    865 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
     865__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef const *GPIOx, uint32_t PinMask)
    866866{
    867867  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
    … …  
    965965  */
    966966
    967 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
     967ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef const *GPIOx);
    968968ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
    969969void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h

    r40 r55  
    309309  * @retval State of bits (1 or 0).
    310310  */
    311 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
     311__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
    312312{
    313313  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h

    r20 r55  
    5757  (uint16_t)64,
    5858  (uint16_t)128,
     59  (uint16_t)256,
     60  (uint16_t)256,
     61  (uint16_t)256,
     62  (uint16_t)256,
    5963  (uint16_t)256
    6064};

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rtc.h

    r25 r55  
    824824  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
    825825  */
    826 __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
     826__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef const *RTCx)
    827827{
    828828  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
    … …  
    856856  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
    857857  */
    858 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
     858__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef const *RTCx)
    859859{
    860860  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
    … …  
    883883  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
    884884  */
    885 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
     885__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef const *RTCx)
    886886{
    887887  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
    … …  
    939939  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
    940940  */
    941 __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
     941__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef const *RTCx)
    942942{
    943943  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
    … …  
    973973  * @retval State of bit (1 or 0).
    974974  */
    975 __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
     975__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef const *RTCx)
    976976{
    977977  return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U);
    … …  
    10341034  * @retval Value between Min_Data = 0 and Max_Data = 0x7F
    10351035  */
    1036 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
     1036__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef const *RTCx)
    10371037{
    10381038  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
    … …  
    10451045  * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
    10461046  */
    1047 __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
     1047__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef const *RTCx)
    10481048{
    10491049  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
    … …  
    11031103  * @retval State of bit (1 or 0).
    11041104  */
    1105 __STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
     1105__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef const *RTCx)
    11061106{
    11071107  return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U);
    … …  
    11361136  * @retval State of bit (1 or 0).
    11371137  */
    1138 __STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
     1138__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef const *RTCx)
    11391139{
    11401140  return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U);
    … …  
    11721172  * @retval State of bit (1 or 0).
    11731173  */
    1174 __STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
     1174__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef const *RTCx)
    11751175{
    11761176  return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U);
    … …  
    12131213  *         @arg @ref LL_RTC_TIME_FORMAT_PM
    12141214  */
    1215 __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
     1215__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef const *RTCx)
    12161216{
    12171217  return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
    … …  
    12481248  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
    12491249  */
    1250 __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
     1250__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef const *RTCx)
    12511251{
    12521252  return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
    … …  
    12831283  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    12841284  */
    1285 __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
     1285__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef const *RTCx)
    12861286{
    12871287  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
    … …  
    13181318  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    13191319  */
    1320 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
     1320__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef const *RTCx)
    13211321{
    13221322  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
    … …  
    13731373  * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
    13741374  */
    1375 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
     1375__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef const *RTCx)
    13761376{
    13771377  uint32_t temp;
    … …  
    14131413  * @retval State of bit (1 or 0).
    14141414  */
    1415 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
     1415__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef const *RTCx)
    14161416{
    14171417  return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U);
    … …  
    14551455  * @retval Sub second value (number between 0 and 65535)
    14561456  */
    1457 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
     1457__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef const *RTCx)
    14581458{
    14591459  return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
    … …  
    15121512  * @retval Value between Min_Data=0x00 and Max_Data=0x99
    15131513  */
    1514 __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
     1514__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef const *RTCx)
    15151515{
    15161516  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
    … …  
    15511551  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
    15521552  */
    1553 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
     1553__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef const *RTCx)
    15541554{
    15551555  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
    … …  
    16051605  *         @arg @ref LL_RTC_MONTH_DECEMBER
    16061606  */
    1607 __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
     1607__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef const *RTCx)
    16081608{
    16091609  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
    … …  
    16351635  * @retval Value between Min_Data=0x01 and Max_Data=0x31
    16361636  */
    1637 __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
     1637__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef const *RTCx)
    16381638{
    16391639  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
    … …  
    17041704  * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
    17051705  */
    1706 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
     1706__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef const *RTCx)
    17071707{
    17081708  uint32_t temp;
    … …  
    17831783  *         @arg @ref LL_RTC_ALMA_MASK_ALL
    17841784  */
    1785 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
     1785__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef const *RTCx)
    17861786{
    17871787  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
    … …  
    18331833  * @retval Value between Min_Data=0x01 and Max_Data=0x31
    18341834  */
    1835 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
     1835__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef const *RTCx)
    18361836{
    18371837  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
    … …  
    18701870  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
    18711871  */
    1872 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
     1872__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef const *RTCx)
    18731873{
    18741874  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
    … …  
    18971897  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
    18981898  */
    1899 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
     1899__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef const *RTCx)
    19001900{
    19011901  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
    … …  
    19251925  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
    19261926  */
    1927 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
     1927__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef const *RTCx)
    19281928{
    19291929  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
    … …  
    19531953  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    19541954  */
    1955 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
     1955__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef const *RTCx)
    19561956{
    19571957  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
    … …  
    19811981  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    19821982  */
    1983 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
     1983__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef const *RTCx)
    19841984{
    19851985  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
    … …  
    20302030  * @retval Combination of hours, minutes and seconds.
    20312031  */
    2032 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
     2032__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef const *RTCx)
    20332033{
    20342034  return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
    … …  
    20552055  * @retval Value between Min_Data=0x00 and Max_Data=0xF
    20562056  */
    2057 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
     2057__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef const *RTCx)
    20582058{
    20592059  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
    … …  
    20782078  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
    20792079  */
    2080 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
     2080__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef const *RTCx)
    20812081{
    20822082  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
    … …  
    21512151  *         @arg @ref LL_RTC_ALMB_MASK_ALL
    21522152  */
    2153 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
     2153__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef const *RTCx)
    21542154{
    21552155  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
    … …  
    22012201  * @retval Value between Min_Data=0x01 and Max_Data=0x31
    22022202  */
    2203 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
     2203__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef const *RTCx)
    22042204{
    22052205  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
    … …  
    22382238  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
    22392239  */
    2240 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
     2240__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef const *RTCx)
    22412241{
    22422242  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
    … …  
    22652265  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
    22662266  */
    2267 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
     2267__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef const *RTCx)
    22682268{
    22692269  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
    … …  
    22932293  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
    22942294  */
    2295 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
     2295__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef const *RTCx)
    22962296{
    22972297  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
    … …  
    23212321  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    23222322  */
    2323 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
     2323__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef const *RTCx)
    23242324{
    23252325  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
    … …  
    23492349  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    23502350  */
    2351 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
     2351__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef const *RTCx)
    23522352{
    23532353  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
    … …  
    24232423  * @retval Value between Min_Data=0x00 and Max_Data=0xF
    24242424  */
    2425 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
     2425__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef const *RTCx)
    24262426{
    24272427  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
    … …  
    24462446  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
    24472447  */
    2448 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
     2448__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef const *RTCx)
    24492449{
    24502450  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
    … …  
    25322532  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
    25332533  */
    2534 __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
     2534__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef const *RTCx)
    25352535{
    25362536  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
    … …  
    25452545  *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
    25462546  */
    2547 __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
     2547__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef const *RTCx)
    25482548{
    25492549  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
    … …  
    25582558  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
    25592559  */
    2560 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
     2560__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef const *RTCx)
    25612561{
    25622562  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
    … …  
    25712571  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    25722572  */
    2573 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
     2573__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef const *RTCx)
    25742574{
    25752575  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
    … …  
    25842584  * @retval Value between Min_Data=0x00 and Max_Data=0x59
    25852585  */
    2586 __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
     2586__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef const *RTCx)
    25872587{
    25882588  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
    … …  
    26022602  * @retval Combination of hours, minutes and seconds.
    26032603  */
    2604 __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
     2604__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef const *RTCx)
    26052605{
    26062606  return (uint32_t)(READ_BIT(RTCx->TSTR,
    … …  
    26212621  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
    26222622  */
    2623 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
     2623__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef const *RTCx)
    26242624{
    26252625  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
    … …  
    26462646  *         @arg @ref LL_RTC_MONTH_DECEMBER
    26472647  */
    2648 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
     2648__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef const *RTCx)
    26492649{
    26502650  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
    … …  
    26592659  * @retval Value between Min_Data=0x01 and Max_Data=0x31
    26602660  */
    2661 __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
     2661__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef const *RTCx)
    26622662{
    26632663  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
    … …  
    26762676  * @retval Combination of Weekday, Day and Month
    26772677  */
    2678 __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
     2678__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef const *RTCx)
    26792679{
    26802680  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
    … …  
    26872687  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
    26882688  */
    2689 __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
     2689__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef const *RTCx)
    26902690{
    26912691  return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
    … …  
    27342734  * @retval None
    27352735  */
    2736 __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
     2736__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef const *RTCx, uint32_t Tamper)
    27372737{
    27382738  UNUSED(RTCx);
    … …  
    27512751  * @retval None
    27522752  */
    2753 __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
     2753__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef const *RTCx, uint32_t Tamper)
    27542754{
    27552755  UNUSED(RTCx);
    … …  
    27692769  * @retval None
    27702770  */
    2771 __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
     2771__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef const *RTCx, uint32_t Mask)
    27722772{
    27732773  UNUSED(RTCx);
    … …  
    27862786  * @retval None
    27872787  */
    2788 __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
     2788__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef const *RTCx, uint32_t Mask)
    27892789{
    27902790  UNUSED(RTCx);
    … …  
    28032803  * @retval None
    28042804  */
    2805 __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
     2805__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef const *RTCx, uint32_t Tamper)
    28062806{
    28072807  UNUSED(RTCx);
    … …  
    28202820  * @retval None
    28212821  */
    2822 __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
     2822__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef const *RTCx, uint32_t Tamper)
    28232823{
    28242824  UNUSED(RTCx);
    … …  
    28322832  * @retval None
    28332833  */
    2834 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
     2834__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef const *RTCx)
    28352835{
    28362836  UNUSED(RTCx);
    … …  
    28442844  * @retval None
    28452845  */
    2846 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
     2846__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef const *RTCx)
    28472847{
    28482848  UNUSED(RTCx);
    … …  
    28612861  * @retval None
    28622862  */
    2863 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
     2863__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef const *RTCx, uint32_t Duration)
    28642864{
    28652865  UNUSED(RTCx);
    … …  
    28772877  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
    28782878  */
    2879 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
     2879__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef const *RTCx)
    28802880{
    28812881  UNUSED(RTCx);
    … …  
    28942894  * @retval None
    28952895  */
    2896 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
     2896__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef const *RTCx, uint32_t FilterCount)
    28972897{
    28982898  UNUSED(RTCx);
    … …  
    29102910  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
    29112911  */
    2912 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
     2912__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef const *RTCx)
    29132913{
    29142914  UNUSED(RTCx);
    … …  
    29312931  * @retval None
    29322932  */
    2933 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
     2933__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef const *RTCx, uint32_t SamplingFreq)
    29342934{
    29352935  UNUSED(RTCx);
    … …  
    29512951  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
    29522952  */
    2953 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
     2953__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef const *RTCx)
    29542954{
    29552955  UNUSED(RTCx);
    … …  
    29682968  * @retval None
    29692969  */
    2970 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
     2970__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef const *RTCx, uint32_t Tamper)
    29712971{
    29722972  UNUSED(RTCx);
    … …  
    29852985  * @retval None
    29862986  */
    2987 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
     2987__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef const *RTCx, uint32_t Tamper)
    29882988{
    29892989  UNUSED(RTCx);
    … …  
    30203020  * @retval None
    30213021  */
    3022 __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
     3022__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef const *RTCx, uint32_t InternalTamper)
    30233023{
    30243024  UNUSED(RTCx);
    … …  
    30473047  * @retval None
    30483048  */
    3049 __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
     3049__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef const *RTCx, uint32_t InternalTamper)
    30503050{
    30513051  UNUSED(RTCx);
    … …  
    30923092  * @retval State of bit (1 or 0).
    30933093  */
    3094 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
     3094__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef const *RTCx)
    30953095{
    30963096  return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U);
    … …  
    31293129  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
    31303130  */
    3131 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
     3131__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef const *RTCx)
    31323132{
    31333133  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
    … …  
    31533153  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
    31543154  */
    3155 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
     3155__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef const *RTCx)
    31563156{
    31573157  return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
    … …  
    31793179  * @retval None
    31803180  */
    3181 __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
     3181__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef const *RTCx, uint32_t BackupRegister, uint32_t Data)
    31823182{
    31833183  __IO uint32_t *tmp;
    … …  
    32033203  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
    32043204  */
    3205 __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
     3205__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef const *RTCx, uint32_t BackupRegister)
    32063206{
    32073207  const __IO uint32_t *tmp;
    … …  
    32503250  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
    32513251  */
    3252 __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
     3252__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef const *RTCx)
    32533253{
    32543254  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
    … …  
    32773277  * @retval State of bit (1 or 0).
    32783278  */
    3279 __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
     3279__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef const *RTCx)
    32803280{
    32813281  return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U);
    … …  
    33103310  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
    33113311  */
    3312 __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
     3312__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef const *RTCx)
    33133313{
    33143314  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
    … …  
    33353335  * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
    33363336  */
    3337 __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
     3337__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef const *RTCx)
    33383338{
    33393339  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
    … …  
    33543354  * @retval State of bit (1 or 0).
    33553355  */
    3356 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
     3356__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef const *RTCx)
    33573357{
    33583358  return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U);
    … …  
    33653365  * @retval State of bit (1 or 0).
    33663366  */
    3367 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
     3367__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef const *RTCx)
    33683368{
    33693369  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U);
    … …  
    33763376  * @retval State of bit (1 or 0).
    33773377  */
    3378 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
     3378__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef const *RTCx)
    33793379{
    33803380  return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U);
    … …  
    33873387  * @retval State of bit (1 or 0).
    33883388  */
    3389 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
     3389__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef const *RTCx)
    33903390{
    33913391  return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U);
    … …  
    33983398  * @retval State of bit (1 or 0).
    33993399  */
    3400 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
     3400__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef const *RTCx)
    34013401{
    34023402  return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U);
    … …  
    34093409  * @retval State of bit (1 or 0).
    34103410  */
    3411 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
     3411__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef const *RTCx)
    34123412{
    34133413  return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U);
    … …  
    34203420  * @retval State of bit (1 or 0).
    34213421  */
    3422 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
     3422__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef const *RTCx)
    34233423{
    34243424  return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U);
    … …  
    34973497  * @retval State of bit (1 or 0).
    34983498  */
    3499 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
     3499__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef const *RTCx)
    35003500{
    35013501  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U);
    … …  
    35083508  * @retval State of bit (1 or 0).
    35093509  */
    3510 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
     3510__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef const *RTCx)
    35113511{
    35123512  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U);
    … …  
    35303530  * @retval State of bit (1 or 0).
    35313531  */
    3532 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
     3532__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef const *RTCx)
    35333533{
    35343534  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U);
    … …  
    35413541  * @retval State of bit (1 or 0).
    35423542  */
    3543 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
     3543__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef const *RTCx)
    35443544{
    35453545  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U);
    … …  
    35523552  * @retval State of bit (1 or 0).
    35533553  */
    3554 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
     3554__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef const *RTCx)
    35553555{
    35563556  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U);
    … …  
    35633563  * @retval State of bit (1 or 0).
    35643564  */
    3565 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
     3565__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef const *RTCx)
    35663566{
    35673567  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1U : 0U);
    … …  
    35743574  * @retval State of bit (1 or 0).
    35753575  */
    3576 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
     3576__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef const *RTCx)
    35773577{
    35783578  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1U : 0U);
    … …  
    35853585  * @retval State of bit (1 or 0).
    35863586  */
    3587 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
     3587__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef const *RTCx)
    35883588{
    35893589  return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U);
    … …  
    35963596  * @retval State of bit (1 or 0).
    35973597  */
    3598 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
     3598__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef const *RTCx)
    35993599{
    36003600  return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U);
    … …  
    36073607  * @retval State of bit (1 or 0).
    36083608  */
    3609 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
     3609__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef const *RTCx)
    36103610{
    36113611  return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U);
    … …  
    36183618  * @retval State of bit (1 or 0).
    36193619  */
    3620 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
     3620__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef const *RTCx)
    36213621{
    36223622  return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U);
    … …  
    36293629  * @retval State of bit (1 or 0).
    36303630  */
    3631 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
     3631__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef const *RTCx)
    36323632{
    36333633  return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U);
    … …  
    36403640  * @retval State of bit (1 or 0).
    36413641  */
    3642 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
     3642__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef const *RTCx)
    36433643{
    36443644  return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U);
    … …  
    36513651  * @retval State of bit (1 or 0).
    36523652  */
    3653 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
     3653__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef const *RTCx)
    36543654{
    36553655  UNUSED(RTCx);
    … …  
    36633663  * @retval State of bit (1 or 0).
    36643664  */
    3665 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
     3665__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef const *RTCx)
    36663666{
    36673667  UNUSED(RTCx);
    … …  
    36763676  * @retval State of bit (1 or 0).
    36773677  */
    3678 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
     3678__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef const *RTCx)
    36793679{
    36803680  UNUSED(RTCx);
    … …  
    37003700  * @retval State of bit (1 or 0).
    37013701  */
    3702 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx)
     3702__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef const *RTCx)
    37033703{
    37043704  UNUSED(RTCx);
    … …  
    37113711  * @retval State of bit (1 or 0).
    37123712  */
    3713 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx)
     3713__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef const *RTCx)
    37143714{
    37153715  UNUSED(RTCx);
    … …  
    37223722  * @retval State of bit (1 or 0).
    37233723  */
    3724 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx)
     3724__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef const *RTCx)
    37253725{
    37263726  UNUSED(RTCx);
    … …  
    37333733  * @retval State of bit (1 or 0).
    37343734  */
    3735 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx)
     3735__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef const *RTCx)
    37363736{
    37373737  UNUSED(RTCx);
    … …  
    37443744  * @retval State of bit (1 or 0).
    37453745  */
    3746 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx)
     3746__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef const *RTCx)
    37473747{
    37483748  UNUSED(RTCx);
    … …  
    37583758  * @retval State of bit (1 or 0).
    37593759  */
    3760 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx)
     3760__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef const *RTCx)
    37613761{
    37623762  UNUSED(RTCx);
    … …  
    37723772  * @retval State of bit (1 or 0).
    37733773  */
    3774 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx)
     3774__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef const *RTCx)
    37753775{
    37763776  UNUSED(RTCx);
    … …  
    37853785  * @retval State of bit (1 or 0).
    37863786  */
    3787 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx)
     3787__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef const *RTCx)
    37883788{
    37893789  UNUSED(RTCx);
    … …  
    37973797  * @retval State of bit (1 or 0).
    37983798  */
    3799 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(RTC_TypeDef *RTCx)
     3799__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(RTC_TypeDef const *RTCx)
    38003800{
    38013801  UNUSED(RTCx);
    … …  
    38083808  * @retval State of bit (1 or 0).
    38093809  */
    3810 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx)
     3810__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef const *RTCx)
    38113811{
    38123812  UNUSED(RTCx);
    … …  
    38213821  * @retval State of bit (1 or 0).
    38223822  */
    3823 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx)
     3823__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef const *RTCx)
    38243824{
    38253825  UNUSED(RTCx);
    … …  
    38493849  * @retval State of bit (1 or 0).
    38503850  */
    3851 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx)
     3851__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef const *RTCx)
    38523852{
    38533853  UNUSED(RTCx);
    … …  
    39603960  * @retval State of bit (1 or 0).
    39613961  */
    3962 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx)
     3962__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef const *RTCx)
    39633963{
    39643964  UNUSED(RTCx);
    … …  
    39723972  * @retval State of bit (1 or 0).
    39733973  */
    3974 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx)
     3974__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef const *RTCx)
    39753975{
    39763976  UNUSED(RTCx);
    … …  
    39853985  * @retval State of bit (1 or 0).
    39863986  */
    3987 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx)
     3987__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef const *RTCx)
    39883988{
    39893989  UNUSED(RTCx);
    … …  
    40084008  * @retval State of bit (1 or 0).
    40094009  */
    4010 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx)
     4010__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef const *RTCx)
    40114011{
    40124012  UNUSED(RTCx);
    … …  
    40194019  * @retval State of bit (1 or 0).
    40204020  */
    4021 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx)
     4021__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef const *RTCx)
    40224022{
    40234023  UNUSED(RTCx);
    … …  
    40304030  * @retval State of bit (1 or 0).
    40314031  */
    4032 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx)
     4032__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef const *RTCx)
    40334033{
    40344034  UNUSED(RTCx);
    … …  
    40414041  * @retval State of bit (1 or 0).
    40424042  */
    4043 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx)
     4043__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef const *RTCx)
    40444044{
    40454045  UNUSED(RTCx);
    … …  
    40524052  * @retval State of bit (1 or 0).
    40534053  */
    4054 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx)
     4054__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef const *RTCx)
    40554055{
    40564056  UNUSED(RTCx);
    … …  
    40664066  * @retval State of bit (1 or 0).
    40674067  */
    4068 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx)
     4068__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef const *RTCx)
    40694069{
    40704070  UNUSED(RTCx);
    … …  
    40804080  * @retval State of bit (1 or 0).
    40814081  */
    4082 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx)
     4082__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef const *RTCx)
    40834083{
    40844084  UNUSED(RTCx);
    … …  
    40934093  * @retval State of bit (1 or 0).
    40944094  */
    4095 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx)
     4095__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef const *RTCx)
    40964096{
    40974097  UNUSED(RTCx);
    … …  
    41054105  * @retval State of bit (1 or 0).
    41064106  */
    4107 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(RTC_TypeDef *RTCx)
     4107__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(RTC_TypeDef const *RTCx)
    41084108{
    41094109  UNUSED(RTCx);
    … …  
    41174117  * @retval State of bit (1 or 0).
    41184118  */
    4119 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx)
     4119__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef const *RTCx)
    41204120{
    41214121  UNUSED(RTCx);
    … …  
    41304130  * @retval State of bit (1 or 0).
    41314131  */
    4132 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(RTC_TypeDef *RTCx)
     4132__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(RTC_TypeDef const *RTCx)
    41334133{
    41344134  UNUSED(RTCx);
    … …  
    41584158  * @retval State of bit (1 or 0).
    41594159  */
    4160 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx)
     4160__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef const *RTCx)
    41614161{
    41624162  UNUSED(RTCx);
    … …  
    41714171  * @retval None
    41724172  */
    4173 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
     4173__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef const *RTCx)
    41744174{
    41754175  UNUSED(RTCx);
    … …  
    41834183  * @retval None
    41844184  */
    4185 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
     4185__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef const *RTCx)
    41864186{
    41874187  UNUSED(RTCx);
    … …  
    41964196  * @retval None
    41974197  */
    4198 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
     4198__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef const *RTCx)
    41994199{
    42004200  UNUSED(RTCx);
    … …  
    42194219  * @retval None
    42204220  */
    4221 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx)
     4221__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef const *RTCx)
    42224222{
    42234223  UNUSED(RTCx);
    … …  
    42304230  * @retval None
    42314231  */
    4232 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx)
     4232__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef const *RTCx)
    42334233{
    42344234  UNUSED(RTCx);
    … …  
    42414241  * @retval None
    42424242  */
    4243 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx)
     4243__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef const *RTCx)
    42444244{
    42454245  UNUSED(RTCx);
    … …  
    42524252  * @retval None
    42534253  */
    4254 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx)
     4254__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef const *RTCx)
    42554255{
    42564256  UNUSED(RTCx);
    … …  
    42634263  * @retval None
    42644264  */
    4265 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx)
     4265__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef const *RTCx)
    42664266{
    42674267  UNUSED(RTCx);
    … …  
    42784278  * @retval None
    42794279  */
    4280 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx)
     4280__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef const *RTCx)
    42814281{
    42824282  UNUSED(RTCx);
    … …  
    42924292  * @retval None
    42934293  */
    4294 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx)
     4294__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef const *RTCx)
    42954295{
    42964296  UNUSED(RTCx);
    … …  
    43054305  * @retval None
    43064306  */
    4307 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx)
     4307__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef const *RTCx)
    43084308{
    43094309  UNUSED(RTCx);
    … …  
    43174317  * @retval None
    43184318  */
    4319 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(RTC_TypeDef *RTCx)
     4319__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(RTC_TypeDef const *RTCx)
    43204320{
    43214321  UNUSED(RTCx);
    … …  
    43294329  * @retval None
    43304330  */
    4331 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx)
     4331__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef const *RTCx)
    43324332{
    43334333  UNUSED(RTCx);
    … …  
    43424342  * @retval None
    43434343  */
    4344 __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(RTC_TypeDef *RTCx)
     4344__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(RTC_TypeDef const *RTCx)
    43454345{
    43464346  UNUSED(RTCx);
    … …  
    44874487  * @retval State of bit (1 or 0).
    44884488  */
    4489 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
     4489__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef const *RTCx)
    44904490{
    44914491  return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U);
    … …  
    44984498  * @retval State of bit (1 or 0).
    44994499  */
    4500 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
     4500__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef const *RTCx)
    45014501{
    45024502  return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U);
    … …  
    45094509  * @retval State of bit (1 or 0).
    45104510  */
    4511 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
     4511__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef const *RTCx)
    45124512{
    45134513  return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U);
    … …  
    45204520  * @retval State of bit (1 or 0).
    45214521  */
    4522 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
     4522__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef const *RTCx)
    45234523{
    45244524  return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U);
    … …  
    45314531  * @retval None
    45324532  */
    4533 __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
     4533__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef const *RTCx)
    45344534{
    45354535  UNUSED(RTCx);
    … …  
    45434543  * @retval None
    45444544  */
    4545 __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
     4545__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef const *RTCx)
    45464546{
    45474547  UNUSED(RTCx);
    … …  
    45554555  * @retval None
    45564556  */
    4557 __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
     4557__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef const *RTCx)
    45584558{
    45594559  UNUSED(RTCx);
    … …  
    45674567  * @retval None
    45684568  */
    4569 __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
     4569__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef const *RTCx)
    45704570{
    45714571  UNUSED(RTCx);
    … …  
    45804580  * @retval None
    45814581  */
    4582 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
     4582__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef const *RTCx)
    45834583{
    45844584  UNUSED(RTCx);
    … …  
    45914591  * @retval None
    45924592  */
    4593 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
     4593__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef const *RTCx)
    45944594{
    45954595  UNUSED(RTCx);
    … …  
    46254625  * @retval None
    46264626  */
    4627 __STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx)
     4627__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef const *RTCx)
    46284628{
    46294629  UNUSED(RTCx);
    … …  
    46364636  * @retval None
    46374637  */
    4638 __STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx)
     4638__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef const *RTCx)
    46394639{
    46404640  UNUSED(RTCx);
    … …  
    46484648  * @retval None
    46494649  */
    4650 __STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx)
     4650__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef const *RTCx)
    46514651{
    46524652  UNUSED(RTCx);
    … …  
    46594659  * @retval None
    46604660  */
    4661 __STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx)
     4661__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef const *RTCx)
    46624662{
    46634663  UNUSED(RTCx);
    … …  
    46714671  * @retval None
    46724672  */
    4673 __STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx)
     4673__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef const *RTCx)
    46744674{
    46754675  UNUSED(RTCx);
    … …  
    46824682  * @retval None
    46834683  */
    4684 __STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx)
     4684__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef const *RTCx)
    46854685{
    46864686  UNUSED(RTCx);
    … …  
    46944694  * @retval None
    46954695  */
    4696 __STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx)
     4696__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef const *RTCx)
    46974697{
    46984698  UNUSED(RTCx);
    … …  
    47054705  * @retval None
    47064706  */
    4707 __STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx)
     4707__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef const *RTCx)
    47084708{
    47094709  UNUSED(RTCx);
    … …  
    47174717  * @retval None
    47184718  */
    4719 __STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx)
     4719__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef const *RTCx)
    47204720{
    47214721  UNUSED(RTCx);
    … …  
    47284728  * @retval None
    47294729  */
    4730 __STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx)
     4730__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef const *RTCx)
    47314731{
    47324732  UNUSED(RTCx);
    … …  
    49294929  * @retval None
    49304930  */
    4931 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx)
     4931__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef const *RTCx)
    49324932{
    49334933  UNUSED(RTCx);
    … …  
    49404940  * @retval None
    49414941  */
    4942 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx)
     4942__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef const *RTCx)
    49434943{
    49444944  UNUSED(RTCx);
    … …  
    49544954  * @retval None
    49554955  */
    4956 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx)
     4956__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef const *RTCx)
    49574957{
    49584958  UNUSED(RTCx);
    … …  
    49654965  * @retval None
    49664966  */
    4967 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx)
     4967__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef const *RTCx)
    49684968{
    49694969  UNUSED(RTCx);
    … …  
    49784978  * @retval None
    49794979  */
    4980 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx)
     4980__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef const *RTCx)
    49814981{
    49824982  UNUSED(RTCx);
    … …  
    49894989  * @retval None
    49904990  */
    4991 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx)
     4991__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef const *RTCx)
    49924992{
    49934993  UNUSED(RTCx);
    … …  
    50015001  * @retval None
    50025002  */
    5003 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(RTC_TypeDef *RTCx)
     5003__STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(RTC_TypeDef const *RTCx)
    50045004{
    50055005  UNUSED(RTCx);
    … …  
    50125012  * @retval None
    50135013  */
    5014 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(RTC_TypeDef *RTCx)
     5014__STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(RTC_TypeDef const *RTCx)
    50155015{
    50165016  UNUSED(RTCx);
    … …  
    50245024  * @retval None
    50255025  */
    5026 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx)
     5026__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef const *RTCx)
    50275027{
    50285028  UNUSED(RTCx);
    … …  
    50355035  * @retval None
    50365036  */
    5037 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx)
     5037__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef const *RTCx)
    50385038{
    50395039  UNUSED(RTCx);
    … …  
    50485048  * @retval None
    50495049  */
    5050 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx)
     5050__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef const *RTCx)
    50515051{
    50525052  UNUSED(RTCx);
    … …  
    50595059  * @retval None
    50605060  */
    5061 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx)
     5061__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef const *RTCx)
    50625062{
    50635063  UNUSED(RTCx);
    … …  
    51005100  * @retval None
    51015101  */
    5102 __STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx)
     5102__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef const *RTCx)
    51035103{
    51045104  UNUSED(RTCx);
    … …  
    51115111  * @retval None
    51125112  */
    5113 __STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx)
     5113__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef const *RTCx)
    51145114{
    51155115  UNUSED(RTCx);
    … …  
    53105310  * @retval State of bit (1 or 0).
    53115311  */
    5312 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
     5312__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef const *RTCx)
    53135313{
    53145314  UNUSED(RTCx);
    … …  
    53225322  * @retval State of bit (1 or 0).
    53235323  */
    5324 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
     5324__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef const *RTCx)
    53255325{
    53265326  UNUSED(RTCx);
    … …  
    53365336  * @retval State of bit (1 or 0).
    53375337  */
    5338 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
     5338__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef const *RTCx)
    53395339{
    53405340  UNUSED(RTCx);
    … …  
    53605360  * @retval State of bit (1 or 0).
    53615361  */
    5362 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx)
     5362__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef const *RTCx)
    53635363{
    53645364  UNUSED(RTCx);
    … …  
    53715371  * @retval State of bit (1 or 0).
    53725372  */
    5373 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx)
     5373__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef const *RTCx)
    53745374{
    53755375  UNUSED(RTCx);
    … …  
    53825382  * @retval State of bit (1 or 0).
    53835383  */
    5384 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx)
     5384__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef const *RTCx)
    53855385{
    53865386  UNUSED(RTCx);
    … …  
    53935393  * @retval State of bit (1 or 0).
    53945394  */
    5395 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx)
     5395__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef const *RTCx)
    53965396{
    53975397  UNUSED(RTCx);
    … …  
    54045404  * @retval State of bit (1 or 0).
    54055405  */
    5406 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx)
     5406__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef const *RTCx)
    54075407{
    54085408  UNUSED(RTCx);
    … …  
    54205420  * @retval State of bit (1 or 0).
    54215421  */
    5422 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx)
     5422__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef const *RTCx)
    54235423{
    54245424  UNUSED(RTCx);
    … …  
    54345434  * @retval State of bit (1 or 0).
    54355435  */
    5436 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx)
     5436__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef const *RTCx)
    54375437{
    54385438  UNUSED(RTCx);
    … …  
    54475447  * @retval State of bit (1 or 0).
    54485448  */
    5449 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx)
     5449__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef const *RTCx)
    54505450{
    54515451  UNUSED(RTCx);
    … …  
    54585458  * @retval State of bit (1 or 0).
    54595459  */
    5460 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(RTC_TypeDef *RTCx)
     5460__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(RTC_TypeDef const *RTCx)
    54615461{
    54625462  UNUSED(RTCx);
    … …  
    54705470  * @retval State of bit (1 or 0).
    54715471  */
    5472 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx)
     5472__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef const *RTCx)
    54735473{
    54745474  UNUSED(RTCx);
    … …  
    54835483  * @retval State of bit (1 or 0).
    54845484  */
    5485 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx)
     5485__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef const *RTCx)
    54865486{
    54875487  UNUSED(RTCx);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h

    r20 r55  
    22682268
    22692269ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
    2270 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
     2270ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx,const LL_I2S_InitTypeDef *I2S_InitStruct);
    22712271void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
    22722272void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h

    r20 r55  
    5757  64UL,
    5858  128UL,
     59  256UL,
     60  256UL,
     61  256UL,
     62  256UL,
    5963  256UL
    6064};

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h

    r20 r55  
    7676} USB_CfgTypeDef;
    7777
     78#if defined (HAL_PCD_MODULE_ENABLED)
    7879typedef struct
    7980{
    … …  
    120121  uint8_t   xfer_fill_db;         /*!< double buffer Need to Fill new buffer  used with bulk_in                 */
    121122} USB_EPTypeDef;
     123#endif /* defined (HAL_PCD_MODULE_ENABLED) */
    122124
    123125/* Exported constants --------------------------------------------------------*/
    … …  
    162164
    163165#ifndef USB_EP_RX_STRX
    164 #define USB_EP_RX_STRX                         (0x3U << 12)
     166#define USB_EP_RX_STRX                         (0x3UL << 12)
    165167#endif /* USB_EP_RX_STRX */
    166168
    … …  
    187189
    188190
    189 HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
     191HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg);
    190192HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
    191193HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
    192194HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
    193 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
     195HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode);
    194196
    195197HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
    … …  
    240242#endif /* __cplusplus */
    241243
    242 
    243244#endif /* STM32G4xx_LL_USB_H */

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c

    r20 r55  
    4949/* Private define ------------------------------------------------------------*/
    5050/**
    51   * @brief STM32G4xx HAL Driver version number V1.2.5
     51  * @brief STM32G4xx HAL Driver version number V1.2.6
    5252  */
    5353#define __STM32G4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
    5454#define __STM32G4xx_HAL_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
    55 #define __STM32G4xx_HAL_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */
     55#define __STM32G4xx_HAL_VERSION_SUB2   (0x06U) /*!< [15:8]  sub2 version */
    5656#define __STM32G4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
    5757#define __STM32G4xx_HAL_VERSION         ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c

    r20 r55  
    27752775  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
    27762776
    2777   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
    2778      ignored (considered as reset) */
    2779   assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
    2780 
    27812777  /* Verification of channel number */
    27822778  if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c

    r20 r55  
    857857  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
    858858  * @param pData Destination Buffer address.
    859   * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
     859  * @param Length Length of data to be transferred from ADC peripheral to memory.
    860860  * @retval HAL status
    861861  */
    … …  
    10531053    /* Note: DMA channel of ADC slave should be stopped after this function   */
    10541054    /*       with HAL_ADC_Stop_DMA() API.                                     */
    1055     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
    1056 
    1057     /* Check if DMA channel effectively disabled */
    1058     if (tmp_hal_status == HAL_ERROR)
    1059     {
    1060       /* Update ADC state machine to error */
    1061       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1055    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
     1056    {
     1057      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
     1058
     1059      /* Check if DMA channel effectively disabled */
     1060      if (tmp_hal_status == HAL_ERROR)
     1061      {
     1062        /* Update ADC state machine to error */
     1063        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1064      }
    10621065    }
    10631066
    … …  
    14091412    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
    14101413    /* while DMA transfer is on going)                                        */
    1411     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
    1412 
    1413     /* Check if DMA channel effectively disabled */
    1414     if (tmp_hal_status != HAL_OK)
    1415     {
    1416       /* Update ADC state machine to error */
    1417       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1414    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
     1415    {
     1416      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
     1417
     1418      /* Check if DMA channel effectively disabled */
     1419      if (tmp_hal_status == HAL_ERROR)
     1420      {
     1421        /* Update ADC state machine to error */
     1422        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1423      }
    14181424    }
    14191425
    … …  
    15491555    /* Note: DMA channel of ADC slave should be stopped after this function   */
    15501556    /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
    1551     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
    1552 
    1553     /* Check if DMA channel effectively disabled */
    1554     if (tmp_hal_status != HAL_OK)
    1555     {
    1556       /* Update ADC state machine to error */
    1557       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1557    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
     1558    {
     1559      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
     1560
     1561      /* Check if DMA channel effectively disabled */
     1562      if (tmp_hal_status == HAL_ERROR)
     1563      {
     1564        /* Update ADC state machine to error */
     1565        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
     1566      }
    15581567    }
    15591568

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_crc.c

    r20 r55  
    6565  * @{
    6666  */
    67 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
    68 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
     67static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength);
     68static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength);
    6969/**
    7070  * @}
    … …  
    285285  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    286286  */
    287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
     287uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength)
    288288{
    289289  uint32_t index;      /* CRC input data buffer index */
    … …  
    305305
    306306    case CRC_INPUTDATA_FORMAT_BYTES:
    307       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
     307      temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength);
    308308      break;
    309309
    310310    case CRC_INPUTDATA_FORMAT_HALFWORDS:
    311       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
     311      temp =
     312        CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength);  /* Derogation MisraC2012 R.11.5 */
    312313      break;
    313314    default:
    … …  
    337338  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    338339  */
    339 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
     340uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, const uint32_t pBuffer[], uint32_t BufferLength)
    340341{
    341342  uint32_t index;      /* CRC input data buffer index */
    … …  
    362363    case CRC_INPUTDATA_FORMAT_BYTES:
    363364      /* Specific 8-bit input data handling  */
    364       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
     365      temp = CRC_Handle_8(hcrc, (uint8_t const *)pBuffer, BufferLength);
    365366      break;
    366367
    367368    case CRC_INPUTDATA_FORMAT_HALFWORDS:
    368369      /* Specific 16-bit input data handling  */
    369       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
     370      temp =
     371        CRC_Handle_16(hcrc, (uint16_t const *)(void const *)pBuffer, BufferLength);  /* Derogation MisraC2012 R.11.5 */
    370372      break;
    371373
    … …  
    430432  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    431433  */
    432 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
     434static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t const pBuffer[], uint32_t BufferLength)
    433435{
    434436  uint32_t i; /* input data buffer index */
    … …  
    453455      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
    454456    }
    455     if ((BufferLength % 4U) == 2U)
     457    else if ((BufferLength % 4U) == 2U)
    456458    {
    457459      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
    … …  
    459461      *pReg = data;
    460462    }
    461     if ((BufferLength % 4U) == 3U)
     463    else if ((BufferLength % 4U) == 3U)
    462464    {
    463465      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
    … …  
    467469      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
    468470    }
     471    else
     472    {
     473      /* Nothing to do */
     474    }
    469475  }
    470476
    … …  
    481487  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
    482488  */
    483 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
     489static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t const pBuffer[], uint32_t BufferLength)
    484490{
    485491  uint32_t i;  /* input data buffer index */

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c

    r20 r55  
    493493  HAL_StatusTypeDef status = HAL_OK;
    494494
    495   if(hdma->State != HAL_DMA_STATE_BUSY)
     495  /* Check the DMA peripheral handle parameter */
     496  if (hdma == NULL)
     497  {
     498    return HAL_ERROR;
     499  }
     500
     501  if (hdma->State != HAL_DMA_STATE_BUSY)
    496502  {
    497503    /* no transfer ongoing */
    … …  
    502508  else
    503509  {
    504      /* Disable DMA IT */
    505      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
    506      
    507      /* disable the DMAMUX sync overrun IT*/
    508      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
    509      
    510      /* Disable the channel */
    511      __HAL_DMA_DISABLE(hdma);
    512      
    513      /* Clear all flags */
    514      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
    515      
    516      /* Clear the DMAMUX synchro overrun flag */
    517      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
    518      
    519      if (hdma->DMAmuxRequestGen != 0U)
    520      {
    521        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
    522        /* disable the request gen overrun IT*/
    523        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
    524      
    525        /* Clear the DMAMUX request generator overrun flag */
    526        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
    527      }
    528   } 
     510    /* Disable the channel */
     511    __HAL_DMA_DISABLE(hdma);
     512
     513    /* Disable DMA IT */
     514    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
     515
     516    /* disable the DMAMUX sync overrun IT*/
     517    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
     518
     519    /* Clear all flags */
     520    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
     521
     522    /* Clear the DMAMUX synchro overrun flag */
     523    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
     524
     525    if (hdma->DMAmuxRequestGen != 0U)
     526    {
     527      /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
     528      /* disable the request gen overrun IT*/
     529      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
     530
     531      /* Clear the DMAMUX request generator overrun flag */
     532      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
     533    }
     534  }
    529535  /* Change the DMA state */
    530536  hdma->State = HAL_DMA_STATE_READY;
    … …  
    561567  else
    562568  {
     569
     570    /* Disable the channel */
     571    __HAL_DMA_DISABLE(hdma);
     572
    563573    /* Disable DMA IT */
    564574    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
    565 
    566     /* Disable the channel */
    567     __HAL_DMA_DISABLE(hdma);
    568575
    569576    /* disable the DMAMUX sync overrun IT*/
    … …  
    937944  * @}
    938945  */
    939 
    940946
    941947
    … …  
    10541060    /* DMA1 */
    10551061    DMAMUX1_ChannelBase = DMAMUX1_Channel0;
     1062    channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
    10561063  }
    10571064  else
    … …  
    10601067#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) || defined (STM32G411xC)
    10611068    DMAMUX1_ChannelBase = DMAMUX1_Channel8;
     1069    channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 8U;
    10621070#elif defined (STM32G411xB) || defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
    10631071    DMAMUX1_ChannelBase = DMAMUX1_Channel6;
     1072    channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 6U;
    10641073#else
    10651074    DMAMUX1_ChannelBase = DMAMUX1_Channel7;
     1075    channel_number = ((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U;
    10661076#endif /* STM32G4x1xx) */
    10671077  }
     1078
    10681079  dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
    1069   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
    10701080  hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
    10711081  hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c

    r20 r55  
    9393  * @retval HAL status
    9494  */
    95 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
     95HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, const HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
    9696{
    9797  /* Check the parameters */
    … …  
    140140  */
    141141HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
    142                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
     142                                                      const HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
    143143{
    144144  /* Check the parameters */

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c

    r20 r55  
    142142  * @retval HAL Status.
    143143  */
    144 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
     144HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef const *pExtiConfig)
    145145{
    146146  __IO uint32_t *regaddr;
    … …  
    266266  * @retval HAL Status.
    267267  */
    268 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
    269 {
    270   __IO uint32_t *regaddr;
     268HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef const *hexti, EXTI_ConfigTypeDef *pExtiConfig)
     269{
     270  const __IO uint32_t *regaddr;
    271271  uint32_t regval;
    272272  uint32_t linepos;
    … …  
    362362  * @retval HAL Status.
    363363  */
    364 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
     364HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef const *hexti)
    365365{
    366366  __IO uint32_t *regaddr;
    … …  
    502502  * @retval none.
    503503  */
    504 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
     504void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef const *hexti)
    505505{
    506506  __IO uint32_t *regaddr;
    … …  
    537537  * @retval 1 if interrupt is pending else 0.
    538538  */
    539 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
    540 {
    541   __IO uint32_t *regaddr;
     539uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge)
     540{
     541  const __IO uint32_t *regaddr;
    542542  uint32_t regval;
    543543  uint32_t linepos;
    … …  
    572572  * @retval None.
    573573  */
    574 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
     574void HAL_EXTI_ClearPending(EXTI_HandleTypeDef const *hexti, uint32_t Edge)
    575575{
    576576  __IO uint32_t *regaddr;
    … …  
    601601  * @retval None.
    602602  */
    603 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
     603void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef const *hexti)
    604604{
    605605  __IO uint32_t *regaddr;

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c

    r20 r55  
    160160  * @retval None
    161161  */
    162 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
     162void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init)
    163163{
    164164  uint32_t position = 0x00U;
    … …  
    199199      }
    200200
    201       if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
     201      if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
     202          (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
    202203      {
    203204        /* Check the Pull parameter */
    … …  
    371372  * @retval The input port pin value.
    372373  */
    373 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
     374GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef const *GPIOx, uint16_t GPIO_Pin)
    374375{
    375376  GPIO_PinState bitstatus;

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_i2c.c

    r20 r55  
    33253325        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
    33263326        {
    3327           return HAL_ERROR;
     3327          /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */
     3328          if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
     3329          {
     3330            /* Clear STOP Flag */
     3331            __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3332
     3333            /* Reset the error code for next trial */
     3334            hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
     3335          }
    33283336        }
    3329 
    3330         /* Clear STOP Flag */
    3331         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
    3332 
    3333         /* Device is ready */
    3334         hi2c->State = HAL_I2C_STATE_READY;
    3335 
    3336         /* Process Unlocked */
    3337         __HAL_UNLOCK(hi2c);
    3338 
    3339         return HAL_OK;
     3337        else
     3338        {
     3339          /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
     3340
     3341          /* Clear STOP Flag */
     3342          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3343
     3344          /* Device is ready */
     3345          hi2c->State = HAL_I2C_STATE_READY;
     3346
     3347          /* Process Unlocked */
     3348          __HAL_UNLOCK(hi2c);
     3349
     3350          return HAL_OK;
     3351        }
    33403352      }
    33413353      else
    33423354      {
    3343         /* Wait until STOPF flag is reset */
    3344         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
    3345         {
    3346           return HAL_ERROR;
    3347         }
     3355        /* A non acknowledge is detected, this mean that device not respond to its address,
     3356           a new trial must be performed */
    33483357
    33493358        /* Clear NACK Flag */
    33503359        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
    33513360
    3352         /* Clear STOP Flag, auto generated with autoend*/
    3353         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3361        /* Wait until STOPF flag is reset */
     3362        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK)
     3363        {
     3364          /* Clear STOP Flag, auto generated with autoend*/
     3365          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
     3366        }
    33543367      }
    33553368
    … …  
    63506363    hi2c->pBuffPtr++;
    63516364
    6352     if ((hi2c->XferSize > 0U))
     6365    if (hi2c->XferSize > 0U)
    63536366    {
    63546367      hi2c->XferSize--;
    … …  
    65066519    hi2c->pBuffPtr++;
    65076520
    6508     if ((hi2c->XferSize > 0U))
     6521    if (hi2c->XferSize > 0U)
    65096522    {
    65106523      hi2c->XferSize--;
    … …  
    69546967      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
    69556968      {
    6956         if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
     6969        if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
    69576970        {
    69586971          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
    … …  
    69947007      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
    69957008      {
    6996         if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
     7009        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
    69977010        {
    69987011          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
    … …  
    70337046    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
    70347047    {
    7035       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
     7048      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
    70367049      {
    70377050        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
    … …  
    71117124    if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
    71127125    {
    7113       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
     7126      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
    71147127      {
    71157128        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
    … …  
    72787291                               uint32_t Request)
    72797292{
     7293  uint32_t tmp;
     7294
    72807295  /* Check the parameters */
    72817296  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
    … …  
    72847299
    72857300  /* Declaration of tmp to prevent undefined behavior of volatile usage */
    7286   uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
    7287                              (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
    7288                              (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
     7301  tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
     7302                    (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
     7303                    (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
    72897304
    72907305  /* update CR2 register */

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_iwdg.c

    r38 r55  
    127127   LSI startup time is also considered here by adding LSI_STARTUP_TIME
    128128   converted in milliseconds. */
    129 #define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
     129#define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
     130                                         ((LSI_STARTUP_TIME / 1000UL) + 1UL))
    130131#define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
    131132/**

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd.c

    r20 r55  
    5050         (##) HAL_PCD_Start();
    5151
     52     (#)NOTE: For applications not using double buffer mode, define the symbol
     53               'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint.
     54
    5255  @endverbatim
    5356  ******************************************************************************
    … …  
    312315    return HAL_ERROR;
    313316  }
    314   /* Process locked */
    315   __HAL_LOCK(hpcd);
    316317
    317318  if (hpcd->State == HAL_PCD_STATE_READY)
    … …  
    391392  }
    392393
    393   /* Release Lock */
    394   __HAL_UNLOCK(hpcd);
    395394  return status;
    396395}
    … …  
    417416  HAL_StatusTypeDef status = HAL_OK;
    418417
    419   /* Process locked */
    420   __HAL_LOCK(hpcd);
    421 
    422418  /* Setup Legacy weak Callbacks  */
    423419  if (hpcd->State == HAL_PCD_STATE_READY)
    … …  
    500496  }
    501497
    502   /* Release Lock */
    503   __HAL_UNLOCK(hpcd);
    504498  return status;
    505499}
    … …  
    525519  }
    526520
    527   /* Process locked */
    528   __HAL_LOCK(hpcd);
    529 
    530521  if (hpcd->State == HAL_PCD_STATE_READY)
    531522  {
    … …  
    541532  }
    542533
    543   /* Release Lock */
    544   __HAL_UNLOCK(hpcd);
    545 
    546534  return status;
    547535}
    … …  
    557545  HAL_StatusTypeDef status = HAL_OK;
    558546
    559   /* Process locked */
    560   __HAL_LOCK(hpcd);
    561 
    562547  if (hpcd->State == HAL_PCD_STATE_READY)
    563548  {
    … …  
    573558  }
    574559
    575   /* Release Lock */
    576   __HAL_UNLOCK(hpcd);
    577 
    578560  return status;
    579561}
    … …  
    599581  }
    600582
    601   /* Process locked */
    602   __HAL_LOCK(hpcd);
    603 
    604583  if (hpcd->State == HAL_PCD_STATE_READY)
    605584  {
    … …  
    615594  }
    616595
    617   /* Release Lock */
    618   __HAL_UNLOCK(hpcd);
    619 
    620596  return status;
    621597}
    … …  
    631607  HAL_StatusTypeDef status = HAL_OK;
    632608
    633   /* Process locked */
    634   __HAL_LOCK(hpcd);
    635 
    636609  if (hpcd->State == HAL_PCD_STATE_READY)
    637610  {
    … …  
    647620  }
    648621
    649   /* Release Lock */
    650   __HAL_UNLOCK(hpcd);
    651 
    652622  return status;
    653623}
    … …  
    673643  }
    674644
    675   /* Process locked */
    676   __HAL_LOCK(hpcd);
    677 
    678645  if (hpcd->State == HAL_PCD_STATE_READY)
    679646  {
    … …  
    688655    status =  HAL_ERROR;
    689656  }
    690 
    691   /* Release Lock */
    692   __HAL_UNLOCK(hpcd);
    693657
    694658  return status;
    … …  
    706670  HAL_StatusTypeDef status = HAL_OK;
    707671
    708   /* Process locked */
    709   __HAL_LOCK(hpcd);
    710 
    711672  if (hpcd->State == HAL_PCD_STATE_READY)
    712673  {
    … …  
    722683  }
    723684
    724   /* Release Lock */
    725   __HAL_UNLOCK(hpcd);
    726 
    727685  return status;
    728686}
    … …  
    748706  }
    749707
    750   /* Process locked */
    751   __HAL_LOCK(hpcd);
    752 
    753708  if (hpcd->State == HAL_PCD_STATE_READY)
    754709  {
    … …  
    763718    status =  HAL_ERROR;
    764719  }
    765 
    766   /* Release Lock */
    767   __HAL_UNLOCK(hpcd);
    768720
    769721  return status;
    … …  
    781733  HAL_StatusTypeDef status = HAL_OK;
    782734
    783   /* Process locked */
    784   __HAL_LOCK(hpcd);
    785 
    786735  if (hpcd->State == HAL_PCD_STATE_READY)
    787736  {
    … …  
    797746  }
    798747
    799   /* Release Lock */
    800   __HAL_UNLOCK(hpcd);
    801 
    802   return status;
     748   return status;
    803749}
    804750
    … …  
    822768  }
    823769
    824   /* Process locked */
    825   __HAL_LOCK(hpcd);
    826 
    827770  if (hpcd->State == HAL_PCD_STATE_READY)
    828771  {
    … …  
    838781  }
    839782
    840   /* Release Lock */
    841   __HAL_UNLOCK(hpcd);
    842 
    843783  return status;
    844784}
    … …  
    854794  HAL_StatusTypeDef status = HAL_OK;
    855795
    856   /* Process locked */
    857   __HAL_LOCK(hpcd);
    858 
    859796  if (hpcd->State == HAL_PCD_STATE_READY)
    860797  {
    … …  
    870807  }
    871808
    872   /* Release Lock */
    873   __HAL_UNLOCK(hpcd);
    874 
    875809  return status;
    876810}
    … …  
    895829  }
    896830
    897   /* Process locked */
    898   __HAL_LOCK(hpcd);
    899 
    900831  if (hpcd->State == HAL_PCD_STATE_READY)
    901832  {
    … …  
    911842  }
    912843
    913   /* Release Lock */
    914   __HAL_UNLOCK(hpcd);
    915 
    916844  return status;
    917845}
    … …  
    927855  HAL_StatusTypeDef status = HAL_OK;
    928856
    929   /* Process locked */
    930   __HAL_LOCK(hpcd);
    931 
    932857  if (hpcd->State == HAL_PCD_STATE_READY)
    933858  {
    … …  
    942867    status =  HAL_ERROR;
    943868  }
    944 
    945   /* Release Lock */
    946   __HAL_UNLOCK(hpcd);
    947869
    948870  return status;
    … …  
    17271649    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
    17281650
     1651    if (epindex >= 8U)
     1652    {
     1653      return HAL_ERROR;
     1654    }
     1655
    17291656    if (epindex == 0U)
    17301657    {
    … …  
    17701697          /* Get SETUP Packet */
    17711698          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
     1699
     1700          if (ep->xfer_count != 8U)
     1701          {
     1702            /* Set Stall condition for EP0 IN/OUT */
     1703            PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL);
     1704            PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL);
     1705
     1706            /* SETUP bit kept frozen while CTR_RX = 1 */
     1707            PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
     1708
     1709            return HAL_OK;
     1710          }
    17721711
    17731712          USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
    … …  
    17911730          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
    17921731
    1793           if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
     1732          if (ep->xfer_count == 0U)
    17941733          {
    1795             USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
    1796                         ep->pmaadress, (uint16_t)ep->xfer_count);
    1797 
    1798             ep->xfer_buff += ep->xfer_count;
    1799 
    1800             /* Process Control Data OUT Packet */
     1734            /* Status phase re-arm for next setup */
     1735            PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
     1736          }
     1737          else
     1738          {
     1739            if (ep->xfer_buff != 0U)
     1740            {
     1741              USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
     1742                          ep->pmaadress, (uint16_t)ep->xfer_count);  /* max 64bytes */
     1743
     1744              ep->xfer_buff += ep->xfer_count;
     1745
     1746              /* Process Control Data OUT Packet */
    18011747#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
    1802             hpcd->DataOutStageCallback(hpcd, 0U);
     1748              hpcd->DataOutStageCallback(hpcd, 0U);
    18031749#else
    1804             HAL_PCD_DataOutStageCallback(hpcd, 0U);
     1750              HAL_PCD_DataOutStageCallback(hpcd, 0U);
    18051751#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
    1806           }
    1807 
    1808           wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
    1809 
    1810           if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
    1811           {
    1812             PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
     1752            }
    18131753          }
    18141754        }
    … …  
    18761816        /* multi-packet on the NON control OUT endpoint */
    18771817        ep->xfer_count += count;
    1878         ep->xfer_buff += count;
    18791818
    18801819        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
    … …  
    18891828        else
    18901829        {
     1830          ep->xfer_buff += count;
    18911831          (void)USB_EPStartXfer(hpcd->Instance, ep);
    18921832        }

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pcd_ex.c

    r20 r55  
    8383  PCD_EPTypeDef *ep;
    8484
    85   /* initialize ep structure*/
     85  /* Initialize ep structure */
    8686  if ((0x80U & ep_addr) == 0x80U)
    8787  {
    … …  
    9898    /* Single Buffer */
    9999    ep->doublebuffer = 0U;
     100
    100101    /* Configure the PMA */
    101102    ep->pmaadress = (uint16_t)pmaadress;
    … …  
    106107    /* Double Buffer Endpoint */
    107108    ep->doublebuffer = 1U;
     109
    108110    /* Configure the PMA */
    109111    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
    … …  
    125127  hpcd->battery_charging_active = 1U;
    126128
     129  USBx->BCDR &= ~(USB_BCDR_PDEN);
     130  USBx->BCDR &= ~(USB_BCDR_SDEN);
     131
    127132  /* Enable BCD feature */
    128133  USBx->BCDR |= USB_BCDR_BCDEN;
    129134
    130   /* Enable DCD : Data Contact Detect */
    131   USBx->BCDR &= ~(USB_BCDR_PDEN);
    132   USBx->BCDR &= ~(USB_BCDR_SDEN);
    133   USBx->BCDR |= USB_BCDR_DCDEN;
    134 
    135135  return HAL_OK;
    136136}
    … …  
    163163
    164164  /* Wait for Min DCD Timeout */
    165   HAL_Delay(300U);
    166 
    167   /* Data Pin Contact ? Check Detect flag */
    168   if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
    169   {
    170 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
    171     hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
    172 #else
    173     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
    174 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
    175   }
     165  HAL_Delay(350U);
     166
    176167  /* Primary detection: checks if connected to Standard Downstream Port
    177168  (without charging capability) */
    178   USBx->BCDR &= ~(USB_BCDR_DCDEN);
    179   HAL_Delay(50U);
    180169  USBx->BCDR |= (USB_BCDR_PDEN);
    181170  HAL_Delay(50U);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c

    r20 r55  
    306306  * @retval None
    307307  */
    308 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
     308HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef const *sConfigPVD)
    309309{
    310310  /* Check the parameters */

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c

    r20 r55  
    672672  * @retval HAL status
    673673  */
    674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
     674HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef const *sConfigPVM)
    675675{
    676676  HAL_StatusTypeDef status = HAL_OK;

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c

    r20 r55  
    310310  * @retval HAL status
    311311  */
    312 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     312HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef  *RCC_OscInitStruct)
    313313{
    314314  uint32_t tickstart;
    … …  
    764764  * @retval None
    765765  */
    766 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
     766HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
    767767{
    768768  uint32_t tickstart;

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c

    r20 r55  
    121121  * @retval HAL status
    122122  */
    123 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
     123HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit)
    124124{
    125125  uint32_t tmpregister;
    … …  
    14061406void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
    14071407{
    1408   GPIO_InitTypeDef GPIO_InitStruct;
     1408  GPIO_InitTypeDef GPIO_InitStruct = {0};
    14091409  FlagStatus       pwrclkchanged = RESET;
    14101410  FlagStatus       backupchanged = RESET;
    … …  
    15591559  * @retval None
    15601560  */
    1561 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
     1561void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef const *pInit)
    15621562{
    15631563  uint32_t value;

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc.c

    r25 r55  
    971971  * @retval HAL status
    972972  */
    973 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
     973HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
    974974{
    975975  uint32_t tmpreg;
    … …  
    10991099  * @retval HAL status
    11001100  */
    1101 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
     1101HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
    11021102{
    11031103  uint32_t datetmpreg;
    … …  
    16191619  * @retval HAL status
    16201620  */
    1621 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
     1621HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
    16221622{
    16231623  uint32_t tmpreg, subsecondtmpreg;
    … …  
    18441844  * @retval HAL state
    18451845  */
    1846 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
     1846HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc)
    18471847{
    18481848  /* Return RTC handle state */
    … …  
    20202020  * @retval operation see RTC_StoreOperation_Definitions
    20212021  */
    2022 uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
     2022uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc)
    20232023{
    20242024  return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rtc_ex.c

    r25 r55  
    14261426  tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
    14271427
    1428   if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
     1428  if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
    14291429  {
    14301430    tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi.c

    r20 r55  
    816816  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    817817  *               the configuration information for SPI module.
    818   * @param  pData pointer to data buffer
    819   * @param  Size amount of data to be sent
    820   * @param  Timeout Timeout duration
     818  * @param  pData pointer to data buffer (u8 or u16 data elements)
     819  * @param  Size amount of data elements (u8 or u16) to be sent
     820  * @param  Timeout Timeout duration in ms
    821821  * @retval HAL status
    822822  */
    … …  
    10021002  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    10031003  *               the configuration information for SPI module.
    1004   * @param  pData pointer to data buffer
    1005   * @param  Size amount of data to be received
    1006   * @param  Timeout Timeout duration
     1004  * @param  pData pointer to data buffer (u8 or u16 data elements)
     1005  * @param  Size amount of data elements (u8 or u16) to be received
     1006  * @param  Timeout Timeout duration in ms
    10071007  * @retval HAL status
     1008  * @note   In master mode, if the direction is set to SPI_DIRECTION_2LINES
     1009  *         the receive buffer is written to data register (DR) to generate
     1010  *         clock pulses and receive data
    10081011  */
    10091012HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
    … …  
    12441247  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    12451248  *               the configuration information for SPI module.
    1246   * @param  pTxData pointer to transmission data buffer
    1247   * @param  pRxData pointer to reception data buffer
    1248   * @param  Size amount of data to be sent and received
    1249   * @param  Timeout Timeout duration
     1249  * @param  pTxData pointer to transmission data buffer (u8 or u16 data elements)
     1250  * @param  pRxData pointer to reception data buffer (u8 or u16 data elements)
     1251  * @param  Size amount of data elements (u8 or u16) to be sent and received
     1252  * @param  Timeout Timeout duration in ms
    12501253  * @retval HAL status
    12511254  */
    … …  
    15941597  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    15951598  *               the configuration information for SPI module.
    1596   * @param  pData pointer to data buffer
    1597   * @param  Size amount of data to be sent
     1599  * @param  pData pointer to data buffer (u8 or u16 data elements)
     1600  * @param  Size amount of data elements (u8 or u16) to be sent
    15981601  * @retval HAL status
    15991602  */
    … …  
    16761679  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    16771680  *               the configuration information for SPI module.
    1678   * @param  pData pointer to data buffer
    1679   * @param  Size amount of data to be sent
     1681  * @param  pData pointer to data buffer (u8 or u16 data elements)
     1682  * @param  Size amount of data elements (u8 or u16) to be received
    16801683  * @retval HAL status
    16811684  */
    … …  
    17791782  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    17801783  *               the configuration information for SPI module.
    1781   * @param  pTxData pointer to transmission data buffer
    1782   * @param  pRxData pointer to reception data buffer
    1783   * @param  Size amount of data to be sent and received
     1784  * @param  pTxData pointer to transmission data buffer (u8 or u16 data elements)
     1785  * @param  pRxData pointer to reception data buffer (u8 or u16 data elements)
     1786  * @param  Size amount of data elements (u8 or u16) to be sent and received
    17841787  * @retval HAL status
    17851788  */
    … …  
    18881891  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    18891892  *               the configuration information for SPI module.
    1890   * @param  pData pointer to data buffer
    1891   * @param  Size amount of data to be sent
     1893  * @param  pData pointer to data buffer  (u8 or u16 data elements)
     1894  * @param  Size amount of data elements (u8 or u16) to be sent
    18921895  * @retval HAL status
    18931896  */
    … …  
    20082011  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    20092012  *               the configuration information for SPI module.
    2010   * @param  pData pointer to data buffer
     2013  * @param  pData pointer to data buffer (u8 or u16 data elements)
    20112014  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
    2012   * @param  Size amount of data to be sent
     2015  * @param  Size amount of data elements (u8 or u16) to be received
    20132016  * @retval HAL status
    20142017  */
    … …  
    21472150  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
    21482151  *               the configuration information for SPI module.
    2149   * @param  pTxData pointer to transmission data buffer
    2150   * @param  pRxData pointer to reception data buffer
     2152  * @param  pTxData pointer to transmission data buffer (u8 or u16 data elements)
     2153  * @param  pRxData pointer to reception data buffer (u8 or u16 data elements)
    21512154  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
    2152   * @param  Size amount of data to be sent
     2155  * @param  Size amount of data elements (u8 or u16) to be sent and received
    21532156  * @retval HAL status
    21542157  */
    … …  
    39963999        tmp_timeout = 0U;
    39974000      }
    3998       count--;
     4001      else
     4002      {
     4003        count--;
     4004      }
    39994005    }
    40004006  }
    … …  
    40784084        tmp_timeout = 0U;
    40794085      }
    4080       count--;
     4086      else
     4087      {
     4088        count--;
     4089      }
    40814090    }
    40824091  }

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c

    r20 r55  
    10231023                      ##### IO operation functions #####
    10241024 ===============================================================================
     1025    [..]
    10251026    This subsection provides a set of functions allowing to manage the UART asynchronous
    10261027    and Half duplex data transfers.
    10271028
    1028     (#) There are two mode of transfer:
    1029        (+) Blocking mode: The communication is performed in polling mode.
    1030            The HAL status of all data processing is returned by the same function
    1031            after finishing transfer.
    1032        (+) Non-Blocking mode: The communication is performed using Interrupts
    1033            or DMA, These API's return the HAL status.
    1034            The end of the data processing will be indicated through the
    1035            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
    1036            using DMA mode.
    1037            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
    1038            will be executed respectively at the end of the transmit or Receive process
    1039            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
     1029    (#) There are two modes of transfer:
     1030       (++) Blocking mode: The communication is performed in polling mode.
     1031            The HAL status of all data processing is returned by the same function
     1032            after finishing transfer.
     1033       (++) Non-Blocking mode: The communication is performed using Interrupts
     1034            or DMA, These API's return the HAL status.
     1035            The end of the data processing will be indicated through the
     1036            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
     1037            using DMA mode.
     1038            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
     1039            will be executed respectively at the end of the transmit or Receive process
     1040            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
    10401041
    10411042    (#) Blocking mode API's are :
    1042         (+) HAL_UART_Transmit()
    1043         (+) HAL_UART_Receive()
     1043        (++) HAL_UART_Transmit()
     1044        (++) HAL_UART_Receive()
    10441045
    10451046    (#) Non-Blocking mode API's with Interrupt are :
    1046         (+) HAL_UART_Transmit_IT()
    1047         (+) HAL_UART_Receive_IT()
    1048         (+) HAL_UART_IRQHandler()
     1047        (++) HAL_UART_Transmit_IT()
     1048        (++) HAL_UART_Receive_IT()
     1049        (++) HAL_UART_IRQHandler()
    10491050
    10501051    (#) Non-Blocking mode API's with DMA are :
    1051         (+) HAL_UART_Transmit_DMA()
    1052         (+) HAL_UART_Receive_DMA()
    1053         (+) HAL_UART_DMAPause()
    1054         (+) HAL_UART_DMAResume()
    1055         (+) HAL_UART_DMAStop()
     1052        (++) HAL_UART_Transmit_DMA()
     1053        (++) HAL_UART_Receive_DMA()
     1054        (++) HAL_UART_DMAPause()
     1055        (++) HAL_UART_DMAResume()
     1056        (++) HAL_UART_DMAStop()
    10561057
    10571058    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
    1058         (+) HAL_UART_TxHalfCpltCallback()
    1059         (+) HAL_UART_TxCpltCallback()
    1060         (+) HAL_UART_RxHalfCpltCallback()
    1061         (+) HAL_UART_RxCpltCallback()
    1062         (+) HAL_UART_ErrorCallback()
     1059        (++) HAL_UART_TxHalfCpltCallback()
     1060        (++) HAL_UART_TxCpltCallback()
     1061        (++) HAL_UART_RxHalfCpltCallback()
     1062        (++) HAL_UART_RxCpltCallback()
     1063        (++) HAL_UART_ErrorCallback()
    10631064
    10641065    (#) Non-Blocking mode transfers could be aborted using Abort API's :
    1065         (+) HAL_UART_Abort()
    1066         (+) HAL_UART_AbortTransmit()
    1067         (+) HAL_UART_AbortReceive()
    1068         (+) HAL_UART_Abort_IT()
    1069         (+) HAL_UART_AbortTransmit_IT()
    1070         (+) HAL_UART_AbortReceive_IT()
     1066        (++) HAL_UART_Abort()
     1067        (++) HAL_UART_AbortTransmit()
     1068        (++) HAL_UART_AbortReceive()
     1069        (++) HAL_UART_Abort_IT()
     1070        (++) HAL_UART_AbortTransmit_IT()
     1071        (++) HAL_UART_AbortReceive_IT()
    10711072
    10721073    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
    1073         (+) HAL_UART_AbortCpltCallback()
    1074         (+) HAL_UART_AbortTransmitCpltCallback()
    1075         (+) HAL_UART_AbortReceiveCpltCallback()
     1074        (++) HAL_UART_AbortCpltCallback()
     1075        (++) HAL_UART_AbortTransmitCpltCallback()
     1076        (++) HAL_UART_AbortReceiveCpltCallback()
    10761077
    10771078    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
    10781079        reception services:
    1079         (+) HAL_UARTEx_RxEventCallback()
     1080        (++) HAL_UARTEx_RxEventCallback()
     1081
     1082    (#) Wakeup from Stop mode Callback:
     1083        (++) HAL_UARTEx_WakeupCallback()
    10801084
    10811085    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
    10821086        Errors are handled as follows :
    1083        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
    1084            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
    1085            in Interrupt mode reception .
    1086            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
    1087            to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
    1088            Transfer is kept ongoing on UART side.
    1089            If user wants to abort it, Abort services should be called by user.
    1090        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
    1091            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
    1092            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
    1093            user callback is executed.
     1087       (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
     1088            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
     1089            in Interrupt mode reception .
     1090            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
     1091            to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
     1092            Transfer is kept ongoing on UART side.
     1093            If user wants to abort it, Abort services should be called by user.
     1094       (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
     1095            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
     1096            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
     1097            user callback is executed.
    10941098
    10951099    -@- In the Half duplex communication, it is forbidden to run the transmit
    … …  
    11691173        pdata8bits++;
    11701174      }
    1171       huart->TxXferCount--;
     1175      if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX)
     1176      {
     1177        huart->TxXferCount--;
     1178      }
     1179      else
     1180      {
     1181        /* Process was aborted during the transmission */
     1182        return HAL_ERROR;
     1183      }
    11721184    }
    11731185
    … …  
    12651277        pdata8bits++;
    12661278      }
    1267       huart->RxXferCount--;
     1279      if (huart->RxState == HAL_UART_STATE_BUSY_RX)
     1280      {
     1281        huart->RxXferCount--;
     1282      }
     1283      else
     1284      {
     1285        /* Process was aborted during the reception */
     1286        return HAL_ERROR;
     1287      }
    12681288    }
    12691289
    … …  
    17051725  }
    17061726
    1707   /* Reset Tx and Rx transfer counters */
    1708   huart->TxXferCount = 0U;
    1709   huart->RxXferCount = 0U;
    1710 
    17111727  /* Clear the Error flags in the ICR register */
    17121728  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
    … …  
    17751791  }
    17761792
    1777   /* Reset Tx transfer counter */
    1778   huart->TxXferCount = 0U;
    1779 
    17801793  /* Flush the whole TX FIFO (if needed) */
    17811794  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
    … …  
    18391852    }
    18401853  }
    1841 
    1842   /* Reset Rx transfer counter */
    1843   huart->RxXferCount = 0U;
    18441854
    18451855  /* Clear the Error flags in the ICR register */
    … …  
    19681978  if (abortcplt == 1U)
    19691979  {
    1970     /* Reset Tx and Rx transfer counters */
    1971     huart->TxXferCount = 0U;
    1972     huart->RxXferCount = 0U;
    1973 
    19741980    /* Clear ISR function pointers */
    19751981    huart->RxISR = NULL;
    … …  
    20512057    else
    20522058    {
    2053       /* Reset Tx transfer counter */
    2054       huart->TxXferCount = 0U;
    20552059
    20562060      /* Clear TxISR function pointers */
    … …  
    20722076  else
    20732077  {
    2074     /* Reset Tx transfer counter */
    2075     huart->TxXferCount = 0U;
    2076 
    20772078    /* Clear TxISR function pointers */
    20782079    huart->TxISR = NULL;
    … …  
    21482149    else
    21492150    {
    2150       /* Reset Rx transfer counter */
    2151       huart->RxXferCount = 0U;
    2152 
    21532151      /* Clear RxISR function pointer */
    21542152      huart->pRxBuffPtr = NULL;
    … …  
    21762174  else
    21772175  {
    2178     /* Reset Rx transfer counter */
    2179     huart->RxXferCount = 0U;
    2180 
    21812176    /* Clear RxISR function pointer */
    21822177    huart->pRxBuffPtr = NULL;
    … …  
    37103705  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
    37113706  {
     3707    huart->RxXferCount = 0;
     3708
     3709    /* Check current nb of data still to be received on DMA side.
     3710       DMA Normal mode, remaining nb of data will be 0
     3711       DMA Circular mode, remaining nb of data is reset to RxXferSize */
     3712    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
     3713    if (nb_remaining_rx_data < huart->RxXferSize)
     3714    {
     3715      /* Update nb of remaining data */
     3716      huart->RxXferCount = nb_remaining_rx_data;
     3717    }
     3718
    37123719#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    37133720    /*Call registered Rx Event callback*/
    3714     huart->RxEventCallback(huart, huart->RxXferSize);
     3721    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37153722#else
    37163723    /*Call legacy weak Rx Event callback*/
    3717     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
     3724    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37183725#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    37193726  }
    … …  
    37483755  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
    37493756  {
     3757    huart->RxXferCount = huart->RxXferSize / 2U;
     3758
     3759    /* Check current nb of data still to be received on DMA side. */
     3760    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
     3761    if (nb_remaining_rx_data <= huart->RxXferSize)
     3762    {
     3763      /* Update nb of remaining data */
     3764      huart->RxXferCount = nb_remaining_rx_data;
     3765    }
     3766
    37503767#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    37513768    /*Call registered Rx Event callback*/
    3752     huart->RxEventCallback(huart, huart->RxXferSize / 2U);
     3769    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37533770#else
    37543771    /*Call legacy weak Rx Event callback*/
    3755     HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
     3772    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
    37563773#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
    37573774  }
    … …  
    37853802      (gstate == HAL_UART_STATE_BUSY_TX))
    37863803  {
    3787     huart->TxXferCount = 0U;
    37883804    UART_EndTxTransfer(huart);
    37893805  }
    … …  
    37933809      (rxstate == HAL_UART_STATE_BUSY_RX))
    37943810  {
    3795     huart->RxXferCount = 0U;
    37963811    UART_EndRxTransfer(huart);
    37973812  }
    … …  
    38173832{
    38183833  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
    3819   huart->RxXferCount = 0U;
    38203834
    38213835#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
    … …  
    38503864    }
    38513865  }
    3852 
    3853   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
    3854   huart->TxXferCount = 0U;
    3855   huart->RxXferCount = 0U;
    38563866
    38573867  /* Reset errorCode */
    … …  
    39063916  }
    39073917
    3908   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
    3909   huart->TxXferCount = 0U;
    3910   huart->RxXferCount = 0U;
    3911 
    39123918  /* Reset errorCode */
    39133919  huart->ErrorCode = HAL_UART_ERROR_NONE;
    … …  
    39473953  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
    39483954
    3949   huart->TxXferCount = 0U;
    3950 
    39513955  /* Flush the whole TX FIFO (if needed) */
    39523956  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
    … …  
    39793983{
    39803984  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
    3981 
    3982   huart->RxXferCount = 0U;
    39833985
    39843986  /* Clear the Error flags in the ICR register */

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c

    r20 r55  
    2525               ##### UART peripheral extended features  #####
    2626  ==============================================================================
    27 
     27  [..]
    2828    (#) Declare a UART_HandleTypeDef handle structure.
    2929
    … …  
    254254                      ##### IO operation functions #####
    255255 ===============================================================================
     256    [..]
    256257    This subsection provides a set of Wakeup and FIFO mode related callback functions.
    257 
    258258    (#) Wakeup from Stop mode Callback:
    259         (+) HAL_UARTEx_WakeupCallback()
    260 
     259        (++) HAL_UARTEx_WakeupCallback()
    261260    (#) TX/RX Fifos Callbacks:
    262         (+) HAL_UARTEx_RxFifoFullCallback()
    263         (+) HAL_UARTEx_TxFifoEmptyCallback()
    264 
     261        (++) HAL_UARTEx_RxFifoFullCallback()
     262        (++) HAL_UARTEx_TxFifoEmptyCallback()
    265263@endverbatim
    266264  * @{
    … …  
    342340        data elements as reception completion criteria, these functions also consider additional events
    343341        as triggers for updating reception status to caller :
    344        (+) Detection of inactivity period (RX line has not been active for a given period).
    345           (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
     342       (++) Detection of inactivity period (RX line has not been active for a given period).
     343          (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
    346344               for 1 frame time, after last received byte.
    347           (++) RX inactivity detected by RTO, i.e. line has been in idle state
     345          (+++) RX inactivity detected by RTO, i.e. line has been in idle state
    348346               for a programmable time, after last received byte.
    349        (+) Detection that a specific character has been received.
    350 
    351     (#) There are two mode of transfer:
    352        (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
     347       (++) Detection that a specific character has been received.
     348
     349    (#) There are two modes of transfer:
     350       (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
    353351           or till IDLE event occurs. Reception is handled only during function execution.
    354352           When function exits, no data reception could occur. HAL status and number of actually received data elements,
    355353           are returned by function after finishing transfer.
    356        (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
     354       (++) Non-Blocking mode: The reception is performed using Interrupts or DMA.
    357355           These API's return the HAL status.
    358356           The end of the data processing will be indicated through the
    … …  
    362360
    363361    (#) Blocking mode API:
    364         (+) HAL_UARTEx_ReceiveToIdle()
     362        (++) HAL_UARTEx_ReceiveToIdle()
    365363
    366364    (#) Non-Blocking mode API with Interrupt:
    367         (+) HAL_UARTEx_ReceiveToIdle_IT()
     365        (++) HAL_UARTEx_ReceiveToIdle_IT()
    368366
    369367    (#) Non-Blocking mode API with DMA:
    370         (+) HAL_UARTEx_ReceiveToIdle_DMA()
     368        (++) HAL_UARTEx_ReceiveToIdle_DMA()
    371369
    372370@endverbatim
    … …  
    943941  *        to Rx Event callback execution.
    944942  * @note  This function is expected to be called within the user implementation of Rx Event Callback,
    945   *        in order to provide the accurate value :
    946   *        In Interrupt Mode :
    947   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
    948   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
    949   *             received data is lower than expected one)
    950   *        In DMA Mode :
    951   *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
    952   *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
    953   *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
    954   *             received data is lower than expected one).
    955   *        In DMA mode, RxEvent callback could be called several times;
     943  *        in order to provide the accurate value.
     944  * @note  In Interrupt Mode:
     945  *        - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received).
     946  *        - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed.
     947  * @note  In DMA Mode:
     948  *        - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received).
     949  *        - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received.
     950  *        - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed.
     951  * @note  In DMA mode, RxEvent callback could be called several times;
    956952  *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
    957953  *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;

  • trunk/fw_g473rct/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_usb.c

    r20 r55  
    3434      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
    3535
     36      (#)NOTE: For applications not using double buffer mode, define the symbol
     37                'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint.
     38
    3639  @endverbatim
    3740
    … …  
    6265  * @retval HAL status
    6366  */
    64 HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
     67HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg)
    6568{
    6669  /* Prevent unused argument(s) compilation warning */
    … …  
    131134  * @retval HAL status
    132135  */
    133 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
     136HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode)
    134137{
    135138  /* Prevent unused argument(s) compilation warning */
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