source: trunk/hardware/smartPro.kicad_pro

Last change on this file was 43, checked in by f.jahn, 5 weeks ago

Vor Änderung für amphenol surLockPlus
File size: 20.9 KB
RevLine 
[1]1{
2 "board": {
3 "3dviewports": [],
4 "design_settings": {
5 "defaults": {
6 "apply_defaults_to_fp_fields": false,
7 "apply_defaults_to_fp_shapes": false,
8 "apply_defaults_to_fp_text": false,
9 "board_outline_line_width": 0.05,
10 "copper_line_width": 0.2,
11 "copper_text_italic": false,
12 "copper_text_size_h": 1.5,
13 "copper_text_size_v": 1.5,
14 "copper_text_thickness": 0.3,
15 "copper_text_upright": false,
16 "courtyard_line_width": 0.05,
17 "dimension_precision": 4,
18 "dimension_units": 3,
19 "dimensions": {
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21 "extension_offset": 500000,
22 "keep_text_aligned": true,
23 "suppress_zeroes": false,
24 "text_position": 0,
25 "units_format": 1
26 },
27 "fab_line_width": 0.1,
28 "fab_text_italic": false,
29 "fab_text_size_h": 1.0,
30 "fab_text_size_v": 1.0,
31 "fab_text_thickness": 0.15,
32 "fab_text_upright": false,
33 "other_line_width": 0.1,
34 "other_text_italic": false,
35 "other_text_size_h": 1.0,
36 "other_text_size_v": 1.0,
37 "other_text_thickness": 0.15,
38 "other_text_upright": false,
39 "pads": {
40 "drill": 1.0,
41 "height": 2.0,
42 "width": 2.0
43 },
44 "silk_line_width": 0.1,
45 "silk_text_italic": false,
46 "silk_text_size_h": 1.0,
47 "silk_text_size_v": 1.0,
48 "silk_text_thickness": 0.1,
49 "silk_text_upright": false,
50 "zones": {
51 "min_clearance": 0.5
52 }
53 },
54 "diff_pair_dimensions": [
55 {
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57 "via_gap": 0.0,
58 "width": 0.0
59 }
60 ],
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102 ],
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105 },
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109 "connection_width": "warning",
110 "copper_edge_clearance": "error",
111 "copper_sliver": "warning",
112 "courtyards_overlap": "error",
113 "creepage": "error",
114 "diff_pair_gap_out_of_range": "error",
115 "diff_pair_uncoupled_length_too_long": "error",
116 "drill_out_of_range": "error",
117 "duplicate_footprints": "warning",
118 "extra_footprint": "warning",
119 "footprint": "error",
120 "footprint_filters_mismatch": "ignore",
121 "footprint_symbol_mismatch": "warning",
122 "footprint_type_mismatch": "ignore",
123 "hole_clearance": "error",
124 "hole_near_hole": "error",
125 "hole_to_hole": "error",
126 "holes_co_located": "warning",
127 "invalid_outline": "error",
128 "isolated_copper": "warning",
129 "item_on_disabled_layer": "error",
130 "items_not_allowed": "error",
131 "length_out_of_range": "error",
132 "lib_footprint_issues": "warning",
133 "lib_footprint_mismatch": "warning",
134 "malformed_courtyard": "error",
135 "microvia_drill_out_of_range": "error",
136 "mirrored_text_on_front_layer": "warning",
137 "missing_courtyard": "ignore",
138 "missing_footprint": "warning",
139 "net_conflict": "warning",
140 "nonmirrored_text_on_back_layer": "warning",
141 "npth_inside_courtyard": "ignore",
142 "padstack": "warning",
143 "pth_inside_courtyard": "ignore",
144 "shorting_items": "error",
145 "silk_edge_clearance": "warning",
146 "silk_over_copper": "warning",
147 "silk_overlap": "warning",
148 "skew_out_of_range": "error",
149 "solder_mask_bridge": "error",
150 "starved_thermal": "error",
151 "text_height": "warning",
[14]152 "text_on_edge_cuts": "error",
[1]153 "text_thickness": "warning",
154 "through_hole_pad_without_hole": "error",
155 "too_many_vias": "error",
156 "track_angle": "error",
157 "track_dangling": "warning",
158 "track_segment_length": "error",
159 "track_width": "error",
160 "tracks_crossing": "error",
161 "unconnected_items": "error",
162 "unresolved_variable": "error",
163 "via_dangling": "warning",
164 "zones_intersect": "error"
165 },
166 "rules": {
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169 "min_connection": 0.2,
170 "min_copper_edge_clearance": 0.5,
171 "min_groove_width": 0.0,
172 "min_hole_clearance": 0.25,
173 "min_hole_to_hole": 0.25,
174 "min_microvia_diameter": 0.2,
175 "min_microvia_drill": 0.1,
176 "min_resolved_spokes": 2,
177 "min_silk_clearance": 0.0,
178 "min_text_height": 0.8,
179 "min_text_thickness": 0.08,
180 "min_through_hole_diameter": 0.3,
181 "min_track_width": 0.2,
182 "min_via_annular_width": 0.15,
183 "min_via_diameter": 0.5,
184 "solder_mask_to_copper_clearance": 0.005,
185 "use_height_for_length_calcs": true
186 },
187 "teardrop_options": [
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190 "td_onroundshapesonly": false,
191 "td_onsmdpad": true,
192 "td_ontrackend": false,
193 "td_onvia": true
194 }
195 ],
196 "teardrop_parameters": [
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206 "td_width_to_size_filter_ratio": 0.9
207 },
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217 "td_width_to_size_filter_ratio": 0.9
218 },
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229 }
230 ],
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239 ],
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248 },
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254 "single_sided": false,
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256 },
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264 }
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270 },
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274 },
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278 }
279 ],
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281 },
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288 },
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292 },
293 "boards": [],
294 "cvpcb": {
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476 "bus_to_net_conflict": "error",
477 "conflicting_netclasses": "error",
478 "different_unit_footprint": "error",
479 "different_unit_net": "error",
480 "duplicate_reference": "error",
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486 "four_way_junction": "ignore",
487 "global_label_dangling": "warning",
488 "hier_label_mismatch": "error",
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490 "label_multiple_wires": "warning",
491 "lib_symbol_issues": "warning",
492 "lib_symbol_mismatch": "warning",
493 "missing_bidi_pin": "warning",
494 "missing_input_pin": "warning",
495 "missing_power_pin": "error",
496 "missing_unit": "warning",
497 "multiple_net_names": "warning",
498 "net_not_bus_member": "warning",
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504 "power_pin_not_driven": "error",
505 "same_local_global_label": "warning",
506 "similar_label_and_power": "warning",
507 "similar_labels": "warning",
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509 "simulation_model_issue": "ignore",
510 "single_global_label": "ignore",
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512 "unconnected_wire_endpoint": "warning",
[43]513 "undefined_netclass": "error",
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515 "unresolved_variable": "error",
516 "wire_dangling": "error"
517 }
518 },
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527 "net_settings": {
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545 "wire_width": 6
546 }
547 ],
548 "meta": {
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553 "netclass_patterns": []
554 },
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558 "idf": "",
559 "netlist": "",
560 "plot": "",
561 "pos_files": "",
562 "specctra_dsn": "",
563 "step": "smartPro.step",
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565 "vrml": ""
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768 "label": "Check_prices",
769 "name": "Check_prices",
770 "show": false
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772 {
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774 "label": "Sim.Library",
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807 },
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813 {
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817 }
818 ],
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841 "plot_directory": "",
842 "space_save_all_events": true,
843 "spice_current_sheet_as_root": false,
844 "spice_external_command": "spice \"%I\"",
845 "spice_model_current_sheet_as_root": true,
846 "spice_save_all_currents": false,
847 "spice_save_all_dissipations": false,
848 "spice_save_all_voltages": false,
849 "subpart_first_id": 65,
850 "subpart_id_separator": 0
851 },
852 "sheets": [
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889 ],
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891}
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