source: trunk/fw_g473rct/SES/STM32G4xx/Source/STM32G4xx_Startup.s@ 20

Last change on this file since 20 was 20, checked in by f.jahn, 4 months ago

adc dma funktioniert und modbus funktioniert
File size: 9.5 KB
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1/*********************************************************************
2* SEGGER Microcontroller GmbH *
3* The Embedded Experts *
4**********************************************************************
5* *
6* (c) 2014 - 2024 SEGGER Microcontroller GmbH *
7* *
8* www.segger.com Support: support@segger.com *
9* *
10**********************************************************************
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12* All rights reserved. *
13* *
14* Redistribution and use in source and binary forms, with or *
15* without modification, are permitted provided that the following *
16* condition is met: *
17* *
18* - Redistributions of source code must retain the above copyright *
19* notice, this condition and the following disclaimer. *
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21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
22* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
23* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
24* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
25* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
26* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
27* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
28* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
29* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
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33* DAMAGE. *
34* *
35**********************************************************************
36
37-------------------------- END-OF-HEADER -----------------------------
38
39File : STM32G4xx_Startup.s
40Purpose : Startup and exception handlers for STM32G4xx devices.
41
42Additional information:
43 Preprocessor Definitions
44 __NO_SYSTEM_INIT
45 If defined,
46 SystemInit is not called.
47 If not defined,
48 SystemInit is called.
49 SystemInit is usually supplied by the CMSIS files.
50 This file declares a weak implementation as fallback.
51
52 __NO_SYSTEM_CLK_UPDATE
53 If defined,
54 SystemCoreClockUpdate is not automatically called.
55 Should be defined if SystemCoreClockUpdate must not be called before main().
56 If not defined,
57 SystemCoreClockUpdate is called before the application entry point.
58
59 __MEMORY_INIT
60 If defined,
61 MemoryInit is called after SystemInit.
62 void MemoryInit(void) can be implemented to enable external
63 memory controllers.
64
65 __VECTORS_IN_RAM
66 If defined,
67 the vector table will be copied from Flash to RAM,
68 and the vector table offset register is adjusted.
69
70 __VTOR_CONFIG
71 If defined,
72 the vector table offset register is set to point to the
73 application's vector table.
74
75 __NO_FPU_ENABLE
76 If defined, the FPU is explicitly not enabled,
77 even if the compiler could use floating point operations.
78
79 __SOFTFP__
80 Defined by the build system.
81 If not defined, the FPU is enabled for floating point operations.
82*/
83
84 .syntax unified
85
86
87/*********************************************************************
88*
89* Global functions
90*
91**********************************************************************
92*/
93/*********************************************************************
94*
95* Reset_Handler
96*
97* Function description
98* Exception handler for reset.
99* Generic bringup of a Cortex-M system.
100*
101* Additional information
102* The stack pointer is expected to be initialized by hardware,
103* i.e. read from vectortable[0].
104* For manual initialization add
105* ldr R0, =__stack_end__
106* mov SP, R0
107*/
108 .global reset_handler
109 .global Reset_Handler
110 .equ reset_handler, Reset_Handler
111 .section .init.Reset_Handler, "ax"
112 .balign 2
113 .thumb_func
114Reset_Handler:
115#ifdef __SEGGER_STOP
116 .extern __SEGGER_STOP_Limit_MSP
117 //
118 // Initialize main stack limit to 0 to disable stack checks before runtime init
119 //
120 movs R0, #0
121 ldr R1, =__SEGGER_STOP_Limit_MSP
122 str R0, [R1]
123#endif
124#ifndef __NO_SYSTEM_INIT
125 //
126 // Call SystemInit
127 //
128 bl SystemInit
129#endif
130#ifdef __MEMORY_INIT
131 //
132 // Call MemoryInit
133 //
134 bl MemoryInit
135#endif
136#ifdef __VECTORS_IN_RAM
137 //
138 // Copy vector table (from Flash) to RAM
139 //
140 ldr R0, =__vectors_start__
141 ldr R1, =__vectors_end__
142 ldr R2, =__vectors_ram_start__
1431:
144 cmp R0, R1
145 beq 2f
146 ldr R3, [R0]
147 str R3, [R2]
148 adds R0, R0, #4
149 adds R2, R2, #4
150 b 1b
1512:
152#endif
153
154#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM)
155 //
156 // Configure vector table offset register
157 //
158#ifdef __ARM_ARCH_6M__
159 ldr R0, =0xE000ED08 // VTOR_REG
160#else
161 movw R0, 0xED08 // VTOR_REG
162 movt R0, 0xE000
163#endif
164#ifdef __VECTORS_IN_RAM
165 ldr R1, =_vectors_ram
166#else
167 ldr R1, =_vectors
168#endif
169 str R1, [R0]
170#endif
171#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE)
172 //
173 // Enable CP11 and CP10 with CPACR |= (0xf<<20)
174 //
175 movw R0, 0xED88 // CPACR
176 movt R0, 0xE000
177 ldr R1, [R0]
178 orrs R1, R1, #(0xf << 20)
179 str R1, [R0]
180#endif
181 //
182 // Call runtime initialization, which calls main().
183 //
184 bl _start
185
186 //
187 // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP,
188 // when there is no strong definition of SystemInit.
189 //
190 .weak SystemInit
191 //
192 // Place SystemCoreClockUpdate in .init_array
193 // to be called after runtime initialization
194 //
195#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE)
196 .section .init_array, "aw"
197 .balign 4
198 .word SystemCoreClockUpdate
199#endif
200
201/*********************************************************************
202*
203* HardFault_Handler
204*
205* Function description
206* Simple exception handler for HardFault.
207* In case of a HardFault caused by BKPT instruction without
208* debugger attached, return execution, otherwise stay in loop.
209*
210* Additional information
211* The stack pointer is expected to be initialized by hardware,
212* i.e. read from vectortable[0].
213* For manual initialization add
214* ldr R0, =__stack_end__
215* mov SP, R0
216*/
217
218#undef L
219#define L(label) .LHardFault_Handler_##label
220
221 .weak HardFault_Handler
222 .section .init.HardFault_Handler, "ax"
223 .balign 2
224 .thumb_func
225HardFault_Handler:
226 //
227 // Check if HardFault is caused by BKPT instruction
228 //
229 ldr R1, =0xE000ED2C // Load NVIC_HFSR
230 ldr R2, [R1]
231 cmp R2, #0 // Check NVIC_HFSR[31]
232
233L(hfLoop):
234 bmi L(hfLoop) // Not set? Stay in HardFault Handler.
235 //
236 // Continue execution after BKPT instruction
237 //
238#if defined(__thumb__) && !defined(__thumb2__)
239 movs R0, #4
240 mov R1, LR
241 tst R0, R1 // Check EXC_RETURN in Link register bit 2.
242 bne L(Uses_PSP)
243 mrs R0, MSP // Stacking was using MSP.
244 b L(Pass_StackPtr)
245L(Uses_PSP):
246 mrs R0, PSP // Stacking was using PSP.
247L(Pass_StackPtr):
248#else
249 tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack
250 ite eq
251 mrseq R0, MSP // Frame stored on MSP
252 mrsne R0, PSP // Frame stored on PSP
253#endif
254 //
255 // Reset HardFault Status
256 //
257#if defined(__thumb__) && !defined(__thumb2__)
258 movs R3, #1
259 lsls R3, R3, #31
260 orrs R2, R3
261 str R2, [R1]
262#else
263 orr R2, R2, #0x80000000
264 str R2, [R1]
265#endif
266 //
267 // Adjust return address
268 //
269 ldr R1, [R0, #24] // Get stored PC from stack
270 adds R1, #2 // Adjust PC by 2 to skip current BKPT
271 str R1, [R0, #24] // Write back adjusted PC to stack
272 //
273 bx LR // Return
274
275/*************************** End of file ****************************/
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