| 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file startup_stm32g070xx.s
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| 4 | * @author MCD Application Team
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| 5 | * @brief STM32G070xx devices vector table for SW4STM32 toolchain.
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| 6 | * This module performs:
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| 7 | * - Set the initial SP
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| 8 | * - Set the initial PC == Reset_Handler,
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| 9 | * - Set the vector table entries with the exceptions ISR address
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| 10 | * - Branches to main in the C library (which eventually
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| 11 | * calls main()).
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| 12 | * After Reset the Cortex-M0+ processor is in Thread mode,
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| 13 | * priority is Privileged, and the Stack is set to Main.
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| 14 | ******************************************************************************
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| 15 | * @attention
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| 16 | *
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| 17 | * Copyright (c) 2018 STMicroelectronics. All rights reserved.
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| 18 | *
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| 19 | * This software component is licensed by ST under BSD 3-Clause license,
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| 20 | * the "License"; You may not use this file except in compliance with the
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| 21 | * License. You may obtain a copy of the License at:
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| 22 | * opensource.org/licenses/BSD-3-Clause
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| 23 | *
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| 24 | ******************************************************************************
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| 25 | */
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| 26 |
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| 27 | .syntax unified
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| 28 | .cpu cortex-m0
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| 29 | .fpu softvfp
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| 30 | .thumb
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| 31 |
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| 32 | .global g_pfnVectors
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| 33 | .global Default_Handler
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| 34 |
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| 35 | /* start address for the initialization values of the .data section.
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| 36 | defined in linker script */
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| 37 | .word _sidata
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| 38 | /* start address for the .data section. defined in linker script */
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| 39 | .word _sdata
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| 40 | /* end address for the .data section. defined in linker script */
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| 41 | .word _edata
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| 42 | /* start address for the .bss section. defined in linker script */
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| 43 | .word _sbss
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| 44 | /* end address for the .bss section. defined in linker script */
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| 45 | .word _ebss
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| 46 |
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| 47 | .section .text.Reset_Handler
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| 48 | .weak Reset_Handler
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| 49 | .type Reset_Handler, %function
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| 50 | Reset_Handler:
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| 51 | ldr r0, =_estack
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| 52 | mov sp, r0 /* set stack pointer */
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| 53 |
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| 54 | /* Copy the data segment initializers from flash to SRAM */
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| 55 | movs r1, #0
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| 56 | b LoopCopyDataInit
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| 57 |
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| 58 | CopyDataInit:
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| 59 | ldr r3, =_sidata
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| 60 | ldr r3, [r3, r1]
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| 61 | str r3, [r0, r1]
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| 62 | adds r1, r1, #4
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| 63 |
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| 64 | LoopCopyDataInit:
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| 65 | ldr r0, =_sdata
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| 66 | ldr r3, =_edata
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| 67 | adds r2, r0, r1
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| 68 | cmp r2, r3
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| 69 | bcc CopyDataInit
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| 70 | ldr r2, =_sbss
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| 71 | b LoopFillZerobss
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| 72 | /* Zero fill the bss segment. */
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| 73 | FillZerobss:
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| 74 | movs r3, #0
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| 75 | str r3, [r2]
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| 76 | adds r2, r2, #4
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| 77 |
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| 78 |
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| 79 | LoopFillZerobss:
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| 80 | ldr r3, = _ebss
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| 81 | cmp r2, r3
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| 82 | bcc FillZerobss
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| 83 |
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| 84 | /* Call the clock system intitialization function.*/
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| 85 | bl SystemInit
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| 86 | /* Call static constructors */
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| 87 | bl __libc_init_array
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| 88 | /* Call the application's entry point.*/
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| 89 | bl main
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| 90 |
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| 91 | LoopForever:
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| 92 | b LoopForever
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| 93 |
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| 94 |
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| 95 | .size Reset_Handler, .-Reset_Handler
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| 96 |
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| 97 | /**
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| 98 | * @brief This is the code that gets called when the processor receives an
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| 99 | * unexpected interrupt. This simply enters an infinite loop, preserving
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| 100 | * the system state for examination by a debugger.
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| 101 | *
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| 102 | * @param None
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| 103 | * @retval : None
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| 104 | */
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| 105 | .section .text.Default_Handler,"ax",%progbits
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| 106 | Default_Handler:
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| 107 | Infinite_Loop:
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| 108 | b Infinite_Loop
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| 109 | .size Default_Handler, .-Default_Handler
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| 110 | /******************************************************************************
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| 111 | *
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| 112 | * The minimal vector table for a Cortex M0. Note that the proper constructs
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| 113 | * must be placed on this to ensure that it ends up at physical address
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| 114 | * 0x0000.0000.
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| 115 | *
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| 116 | ******************************************************************************/
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| 117 | .section .isr_vector,"a",%progbits
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| 118 | .type g_pfnVectors, %object
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| 119 | .size g_pfnVectors, .-g_pfnVectors
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| 120 |
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| 121 |
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| 122 | g_pfnVectors:
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| 123 | .word _estack
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| 124 | .word Reset_Handler
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| 125 | .word NMI_Handler
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| 126 | .word HardFault_Handler
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| 127 | .word 0
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| 128 | .word 0
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| 129 | .word 0
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| 130 | .word 0
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| 131 | .word 0
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| 132 | .word 0
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| 133 | .word 0
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| 134 | .word SVC_Handler
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| 135 | .word 0
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| 136 | .word 0
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| 137 | .word PendSV_Handler
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| 138 | .word SysTick_Handler
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| 139 | .word WWDG_IRQHandler /* Window WatchDog */
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| 140 | .word 0 /* reserved */
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| 141 | .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */
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| 142 | .word FLASH_IRQHandler /* FLASH */
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| 143 | .word RCC_IRQHandler /* RCC */
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| 144 | .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
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| 145 | .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
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| 146 | .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
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| 147 | .word 0 /* reserved */
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| 148 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
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| 149 | .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
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| 150 | .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */
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| 151 | .word ADC1_IRQHandler /* ADC1 */
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| 152 | .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
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| 153 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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| 154 | .word 0 /* reserved */
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| 155 | .word TIM3_IRQHandler /* TIM3 */
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| 156 | .word TIM6_IRQHandler /* TIM6 */
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| 157 | .word TIM7_IRQHandler /* TIM7 */
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| 158 | .word TIM14_IRQHandler /* TIM14 */
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| 159 | .word TIM15_IRQHandler /* TIM15 */
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| 160 | .word TIM16_IRQHandler /* TIM16 */
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| 161 | .word TIM17_IRQHandler /* TIM17 */
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| 162 | .word I2C1_IRQHandler /* I2C1 */
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| 163 | .word I2C2_IRQHandler /* I2C2 */
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| 164 | .word SPI1_IRQHandler /* SPI1 */
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| 165 | .word SPI2_IRQHandler /* SPI2 */
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| 166 | .word USART1_IRQHandler /* USART1 */
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| 167 | .word USART2_IRQHandler /* USART2 */
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| 168 | .word USART3_4_IRQHandler /* USART3, USART4 */
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| 169 |
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| 170 | /*******************************************************************************
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| 171 | *
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| 172 | * Provide weak aliases for each Exception handler to the Default_Handler.
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| 173 | * As they are weak aliases, any function with the same name will override
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| 174 | * this definition.
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| 175 | *
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| 176 | *******************************************************************************/
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| 177 |
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| 178 | .weak NMI_Handler
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| 179 | .thumb_set NMI_Handler,Default_Handler
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| 180 |
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| 181 | .weak HardFault_Handler
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| 182 | .thumb_set HardFault_Handler,Default_Handler
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| 183 |
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| 184 | .weak SVC_Handler
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| 185 | .thumb_set SVC_Handler,Default_Handler
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| 186 |
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| 187 | .weak PendSV_Handler
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| 188 | .thumb_set PendSV_Handler,Default_Handler
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| 189 |
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| 190 | .weak SysTick_Handler
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| 191 | .thumb_set SysTick_Handler,Default_Handler
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| 192 |
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| 193 | .weak WWDG_IRQHandler
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| 194 | .thumb_set WWDG_IRQHandler,Default_Handler
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| 195 |
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| 196 | .weak RTC_TAMP_IRQHandler
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| 197 | .thumb_set RTC_TAMP_IRQHandler,Default_Handler
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| 198 |
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| 199 | .weak FLASH_IRQHandler
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| 200 | .thumb_set FLASH_IRQHandler,Default_Handler
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| 201 |
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| 202 | .weak RCC_IRQHandler
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| 203 | .thumb_set RCC_IRQHandler,Default_Handler
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| 204 |
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| 205 | .weak EXTI0_1_IRQHandler
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| 206 | .thumb_set EXTI0_1_IRQHandler,Default_Handler
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| 207 |
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| 208 | .weak EXTI2_3_IRQHandler
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| 209 | .thumb_set EXTI2_3_IRQHandler,Default_Handler
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| 210 |
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| 211 | .weak EXTI4_15_IRQHandler
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| 212 | .thumb_set EXTI4_15_IRQHandler,Default_Handler
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| 213 |
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| 214 | .weak DMA1_Channel1_IRQHandler
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| 215 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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| 216 |
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| 217 | .weak DMA1_Channel2_3_IRQHandler
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| 218 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
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| 219 |
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| 220 | .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
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| 221 | .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler
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| 222 |
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| 223 | .weak ADC1_IRQHandler
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| 224 | .thumb_set ADC1_IRQHandler,Default_Handler
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| 225 |
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| 226 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler
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| 227 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
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| 228 |
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| 229 | .weak TIM1_CC_IRQHandler
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| 230 | .thumb_set TIM1_CC_IRQHandler,Default_Handler
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| 231 |
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| 232 | .weak TIM3_IRQHandler
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| 233 | .thumb_set TIM3_IRQHandler,Default_Handler
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| 234 |
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| 235 | .weak TIM6_IRQHandler
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| 236 | .thumb_set TIM6_IRQHandler,Default_Handler
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| 237 |
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| 238 | .weak TIM7_IRQHandler
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| 239 | .thumb_set TIM7_IRQHandler,Default_Handler
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| 240 |
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| 241 | .weak TIM14_IRQHandler
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| 242 | .thumb_set TIM14_IRQHandler,Default_Handler
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| 243 |
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| 244 | .weak TIM15_IRQHandler
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| 245 | .thumb_set TIM15_IRQHandler,Default_Handler
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| 246 |
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| 247 | .weak TIM16_IRQHandler
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| 248 | .thumb_set TIM16_IRQHandler,Default_Handler
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| 249 |
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| 250 | .weak TIM17_IRQHandler
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| 251 | .thumb_set TIM17_IRQHandler,Default_Handler
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| 252 |
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| 253 | .weak I2C1_IRQHandler
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| 254 | .thumb_set I2C1_IRQHandler,Default_Handler
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| 255 |
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| 256 | .weak I2C2_IRQHandler
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| 257 | .thumb_set I2C2_IRQHandler,Default_Handler
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| 258 |
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| 259 | .weak SPI1_IRQHandler
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| 260 | .thumb_set SPI1_IRQHandler,Default_Handler
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| 261 |
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| 262 | .weak SPI2_IRQHandler
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| 263 | .thumb_set SPI2_IRQHandler,Default_Handler
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| 264 |
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| 265 | .weak USART1_IRQHandler
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| 266 | .thumb_set USART1_IRQHandler,Default_Handler
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| 267 |
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| 268 | .weak USART2_IRQHandler
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| 269 | .thumb_set USART2_IRQHandler,Default_Handler
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| 270 |
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| 271 | .weak USART3_4_IRQHandler
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| 272 | .thumb_set USART3_4_IRQHandler,Default_Handler
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| 273 |
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| 274 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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| 275 |
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