| 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file system_stm32g0xx.c
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| 4 | * @author MCD Application Team
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| 5 | * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
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| 6 | *
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| 7 | * This file provides two functions and one global variable to be called from
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| 8 | * user application:
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| 9 | * - SystemInit(): This function is called at startup just after reset and
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| 10 | * before branch to main program. This call is made inside
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| 11 | * the "startup_stm32g0xx.s" file.
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| 12 | *
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| 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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| 14 | * by the user application to setup the SysTick
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| 15 | * timer or configure other parameters.
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| 16 | *
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| 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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| 18 | * be called whenever the core clock is changed
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| 19 | * during program execution.
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| 20 | *
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| 21 | * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
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| 22 | * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
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| 23 | * configure the system clock before to branch to main program.
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| 24 | *
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| 25 | * This file configures the system clock as follows:
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| 26 | *=============================================================================
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| 27 | *-----------------------------------------------------------------------------
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| 28 | * System Clock source | HSI
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| 29 | *-----------------------------------------------------------------------------
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| 30 | * SYSCLK(Hz) | 16000000
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| 31 | *-----------------------------------------------------------------------------
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| 32 | * HCLK(Hz) | 16000000
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| 33 | *-----------------------------------------------------------------------------
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| 34 | * AHB Prescaler | 1
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| 35 | *-----------------------------------------------------------------------------
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| 36 | * APB Prescaler | 1
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| 37 | *-----------------------------------------------------------------------------
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| 38 | * HSI Division factor | 1
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| 39 | *-----------------------------------------------------------------------------
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| 40 | * PLL_M | 1
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| 41 | *-----------------------------------------------------------------------------
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| 42 | * PLL_N | 8
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| 43 | *-----------------------------------------------------------------------------
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| 44 | * PLL_P | 7
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| 45 | *-----------------------------------------------------------------------------
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| 46 | * PLL_Q | 2
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| 47 | *-----------------------------------------------------------------------------
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| 48 | * PLL_R | 2
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| 49 | *-----------------------------------------------------------------------------
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| 50 | * Require 48MHz for RNG | Disabled
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| 51 | *-----------------------------------------------------------------------------
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| 52 | *=============================================================================
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| 53 | ******************************************************************************
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| 54 | * @attention
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| 55 | *
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| 56 | * Copyright (c) 2018-2021 STMicroelectronics.
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| 57 | * All rights reserved.
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| 58 | *
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| 59 | * This software is licensed under terms that can be found in the LICENSE file
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| 60 | * in the root directory of this software component.
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| 61 | * If no LICENSE file comes with this software, it is provided AS-IS.
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| 62 | *
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| 63 | ******************************************************************************
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| 64 | */
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| 65 | /** @addtogroup CMSIS
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| 66 | * @{
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| 67 | */
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| 68 |
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| 69 | /** @addtogroup stm32g0xx_system
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| 70 | * @{
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| 71 | */
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| 72 |
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| 73 | /** @addtogroup STM32G0xx_System_Private_Includes
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| 74 | * @{
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| 75 | */
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| 76 |
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| 77 | #include "stm32g0xx.h"
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| 78 |
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| 79 | #if !defined (HSE_VALUE)
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| 80 | #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
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| 81 | #endif /* HSE_VALUE */
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| 82 |
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| 83 | #if !defined (HSI_VALUE)
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| 84 | #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
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| 85 | #endif /* HSI_VALUE */
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| 86 |
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| 87 | #if !defined (LSI_VALUE)
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| 88 | #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
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| 89 | #endif /* LSI_VALUE */
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| 90 |
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| 91 | #if !defined (LSE_VALUE)
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| 92 | #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
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| 93 | #endif /* LSE_VALUE */
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| 94 |
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| 95 | /**
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| 96 | * @}
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| 97 | */
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| 98 |
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| 99 | /** @addtogroup STM32G0xx_System_Private_TypesDefinitions
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| 100 | * @{
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| 101 | */
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| 102 |
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| 103 | /**
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| 104 | * @}
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| 105 | */
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| 106 |
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| 107 | /** @addtogroup STM32G0xx_System_Private_Defines
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| 108 | * @{
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| 109 | */
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| 110 |
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| 111 | /************************* Miscellaneous Configuration ************************/
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| 112 | /* Note: Following vector table addresses must be defined in line with linker
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| 113 | configuration. */
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| 114 | /*!< Uncomment the following line if you need to relocate the vector table
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| 115 | anywhere in Flash or Sram, else the vector table is kept at the automatic
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| 116 | remap of boot address selected */
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| 117 | // #define USER_VECT_TAB_ADDRESS
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| 118 |
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| 119 | #if defined(USER_VECT_TAB_ADDRESS)
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| 120 | /*!< Uncomment the following line if you need to relocate your vector Table
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| 121 | in Sram else user remap will be done in Flash. */
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| 122 | /* #define VECT_TAB_SRAM */
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| 123 | #if defined(VECT_TAB_SRAM)
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| 124 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
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| 125 | This value must be a multiple of 0x200. */
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| 126 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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| 127 | This value must be a multiple of 0x200. */
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| 128 | #else
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| 129 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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| 130 | This value must be a multiple of 0x200. */
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| 131 | #define VECT_TAB_OFFSET 0x3000 /*!< Vector Table base offset field.
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| 132 | This value must be a multiple of 0x200. */
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| 133 | #endif /* VECT_TAB_SRAM */
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| 134 | #endif /* USER_VECT_TAB_ADDRESS */
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| 135 | /******************************************************************************/
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| 136 | /**
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| 137 | * @}
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| 138 | */
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| 139 |
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| 140 | /** @addtogroup STM32G0xx_System_Private_Macros
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| 141 | * @{
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| 142 | */
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| 143 |
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| 144 | /**
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| 145 | * @}
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| 146 | */
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| 147 |
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| 148 | /** @addtogroup STM32G0xx_System_Private_Variables
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| 149 | * @{
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| 150 | */
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| 151 | /* The SystemCoreClock variable is updated in three ways:
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| 152 | 1) by calling CMSIS function SystemCoreClockUpdate()
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| 153 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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| 154 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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| 155 | Note: If you use this function to configure the system clock; then there
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| 156 | is no need to call the 2 first functions listed above, since SystemCoreClock
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| 157 | variable is updated automatically.
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| 158 | */
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| 159 | uint32_t SystemCoreClock = 16000000UL;
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| 160 |
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| 161 | const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
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| 162 | const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
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| 163 |
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| 164 | /**
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| 165 | * @}
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| 166 | */
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| 167 |
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| 168 | /** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
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| 169 | * @{
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| 170 | */
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| 171 |
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| 172 | /**
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| 173 | * @}
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| 174 | */
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| 175 |
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| 176 | /** @addtogroup STM32G0xx_System_Private_Functions
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| 177 | * @{
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| 178 | */
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| 179 |
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| 180 | /**
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| 181 | * @brief Setup the microcontroller system.
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| 182 | * @param None
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| 183 | * @retval None
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| 184 | */
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| 185 | void SystemInit(void)
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| 186 | {
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| 187 | /* Configure the Vector Table location -------------------------------------*/
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| 188 | #if defined(USER_VECT_TAB_ADDRESS)
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| 189 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
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| 190 | #endif /* USER_VECT_TAB_ADDRESS */
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| 191 | }
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| 192 |
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| 193 | /**
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| 194 | * @brief Update SystemCoreClock variable according to Clock Register Values.
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| 195 | * The SystemCoreClock variable contains the core clock (HCLK), it can
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| 196 | * be used by the user application to setup the SysTick timer or configure
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| 197 | * other parameters.
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| 198 | *
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| 199 | * @note Each time the core clock (HCLK) changes, this function must be called
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| 200 | * to update SystemCoreClock variable value. Otherwise, any configuration
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| 201 | * based on this variable will be incorrect.
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| 202 | *
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| 203 | * @note - The system frequency computed by this function is not the real
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| 204 | * frequency in the chip. It is calculated based on the predefined
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| 205 | * constant and the selected clock source:
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| 206 | *
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| 207 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
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| 208 | *
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| 209 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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| 210 | *
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| 211 | * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
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| 212 | *
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| 213 | * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
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| 214 | *
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| 215 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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| 216 | * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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| 217 | *
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| 218 | * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
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| 219 | * 16 MHz) but the real value may vary depending on the variations
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| 220 | * in voltage and temperature.
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| 221 | *
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| 222 | * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
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| 223 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real
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| 224 | * frequency of the crystal used. Otherwise, this function may
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| 225 | * have wrong result.
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| 226 | *
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| 227 | * - The result of this function could be not correct when using fractional
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| 228 | * value for HSE crystal.
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| 229 | *
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| 230 | * @param None
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| 231 | * @retval None
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| 232 | */
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| 233 | void SystemCoreClockUpdate(void)
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| 234 | {
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| 235 | uint32_t tmp;
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| 236 | uint32_t pllvco;
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| 237 | uint32_t pllr;
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| 238 | uint32_t pllsource;
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| 239 | uint32_t pllm;
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| 240 | uint32_t hsidiv;
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| 241 |
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| 242 | /* Get SYSCLK source -------------------------------------------------------*/
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| 243 | switch (RCC->CFGR & RCC_CFGR_SWS)
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| 244 | {
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| 245 | case RCC_CFGR_SWS_0: /* HSE used as system clock */
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| 246 | SystemCoreClock = HSE_VALUE;
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| 247 | break;
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| 248 |
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| 249 | case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
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| 250 | SystemCoreClock = LSI_VALUE;
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| 251 | break;
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| 252 |
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| 253 | case RCC_CFGR_SWS_2: /* LSE used as system clock */
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| 254 | SystemCoreClock = LSE_VALUE;
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| 255 | break;
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| 256 |
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| 257 | case RCC_CFGR_SWS_1: /* PLL used as system clock */
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| 258 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
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| 259 | SYSCLK = PLL_VCO / PLLR
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| 260 | */
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| 261 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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| 262 | pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
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| 263 |
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| 264 | if(pllsource == 0x03UL) /* HSE used as PLL clock source */
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| 265 | {
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| 266 | pllvco = (HSE_VALUE / pllm);
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| 267 | }
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| 268 | else /* HSI used as PLL clock source */
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| 269 | {
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| 270 | pllvco = (HSI_VALUE / pllm);
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| 271 | }
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| 272 | pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
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| 273 | pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
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| 274 |
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| 275 | SystemCoreClock = pllvco/pllr;
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| 276 | break;
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| 277 |
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| 278 | case 0x00000000U: /* HSI used as system clock */
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| 279 | default: /* HSI used as system clock */
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| 280 | hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
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| 281 | SystemCoreClock = (HSI_VALUE/hsidiv);
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| 282 | break;
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| 283 | }
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| 284 | /* Compute HCLK clock frequency --------------------------------------------*/
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| 285 | /* Get HCLK prescaler */
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| 286 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
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| 287 | /* HCLK clock frequency */
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| 288 | SystemCoreClock >>= tmp;
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| 289 | }
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| 290 |
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| 291 |
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| 292 | /**
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| 293 | * @}
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| 294 | */
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| 295 |
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| 296 | /**
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| 297 | * @}
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| 298 | */
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| 299 |
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| 300 | /**
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| 301 | * @}
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| 302 | */
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