source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c

Last change on this file was 6, checked in by f.jahn, 8 months ago
File size: 21.6 KB
Line 
1/**
2 ******************************************************************************
3 * @file stm32g0xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19/* Includes ------------------------------------------------------------------*/
20#include "stm32g0xx_ll_utils.h"
21#include "stm32g0xx_ll_rcc.h"
22#include "stm32g0xx_ll_system.h"
23#include "stm32g0xx_ll_pwr.h"
24#ifdef USE_FULL_ASSERT
25#include "stm32_assert.h"
26#else
27#define assert_param(expr) ((void)0U)
28#endif /* USE_FULL_ASSERT */
29
30/** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34/** @addtogroup UTILS_LL
35 * @{
36 */
37
38/* Private types -------------------------------------------------------------*/
39/* Private variables ---------------------------------------------------------*/
40/* Private constants ---------------------------------------------------------*/
41/** @addtogroup UTILS_LL_Private_Constants
42 * @{
43 */
44#define UTILS_MAX_FREQUENCY 64000000U /*!< Maximum frequency for system clock, in Hz */
45
46/* Defines used for PLL range */
47#define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */
48#define UTILS_PLLVCO_INPUT_MAX 8000000U /*!< Frequency max for PLLVCO input, in Hz */
49#define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */
50#define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */
51
52/* Defines used for HSE range */
53#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
54#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
55
56/* Defines used for FLASH latency according to HCLK Frequency */
57#define UTILS_SCALE1_LATENCY1_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
58#define UTILS_SCALE1_LATENCY2_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
59#define UTILS_SCALE1_LATENCY3_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
60/**
61 * @}
62 */
63
64/* Private macros ------------------------------------------------------------*/
65/** @addtogroup UTILS_LL_Private_Macros
66 * @{
67 */
68#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
69 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
70 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
71 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
72 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
73 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
74 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
75 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
76 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
77
78#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
79 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
80 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
81 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
82 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
83
84#define IS_LL_UTILS_HSI_DIV(__VALUE__) (((__VALUE__) == LL_RCC_HSI_DIV_1) \
85 || ((__VALUE__) == LL_RCC_HSI_DIV_2) \
86 || ((__VALUE__) == LL_RCC_HSI_DIV_4) \
87 || ((__VALUE__) == LL_RCC_HSI_DIV_8) \
88 || ((__VALUE__) == LL_RCC_HSI_DIV_16) \
89 || ((__VALUE__) == LL_RCC_HSI_DIV_32) \
90 || ((__VALUE__) == LL_RCC_HSI_DIV_64) \
91 || ((__VALUE__) == LL_RCC_HSI_DIV_128))
92
93#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
94 || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
95 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
96 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
97 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
98 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
99 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
100 || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
101
102#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
103
104#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
105 || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
106 || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
107 || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \
108 || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
109 || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \
110 || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
111
112#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
113
114#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
115
116#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
117
118#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
119 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
120
121#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
122/**
123 * @}
124 */
125/* Private function prototypes -----------------------------------------------*/
126/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
127 * @{
128 */
129static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
130 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
131static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
132static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
133static ErrorStatus UTILS_PLL_IsBusy(void);
134/**
135 * @}
136 */
137
138/* Exported functions --------------------------------------------------------*/
139/** @addtogroup UTILS_LL_Exported_Functions
140 * @{
141 */
142
143/** @addtogroup UTILS_LL_EF_DELAY
144 * @{
145 */
146
147/**
148 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
149 * @note When a RTOS is used, it is recommended to avoid changing the Systick
150 * configuration by calling this function, for a delay use rather osDelay RTOS service.
151 * @param HCLKFrequency HCLK frequency in Hz
152 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
153 * @retval None
154 */
155void LL_Init1msTick(uint32_t HCLKFrequency)
156{
157 /* Use frequency provided in argument */
158 LL_InitTick(HCLKFrequency, 1000U);
159}
160
161/**
162 * @brief This function provides accurate delay (in milliseconds) based
163 * on SysTick counter flag
164 * @note When a RTOS is used, it is recommended to avoid using blocking delay
165 * and use rather osDelay service.
166 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
167 * will configure Systick to 1ms
168 * @param Delay specifies the delay time length, in milliseconds.
169 * @retval None
170 */
171void LL_mDelay(uint32_t Delay)
172{
173 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
174 uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
175 /* Add this code to indicate that local variable is not used */
176 ((void)tmp);
177 tmpDelay = Delay;
178 /* Add a period to guaranty minimum wait */
179 if (tmpDelay < LL_MAX_DELAY)
180 {
181 tmpDelay ++;
182 }
183
184 while (tmpDelay != 0U)
185 {
186 if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
187 {
188 tmpDelay --;
189 }
190 }
191}
192
193/**
194 * @}
195 */
196
197/** @addtogroup UTILS_EF_SYSTEM
198 * @brief System Configuration functions
199 *
200 @verbatim
201 ===============================================================================
202 ##### System Configuration functions #####
203 ===============================================================================
204 [..]
205 System, AHB and APB buses clocks configuration
206
207 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 64000000 Hz.
208 @endverbatim
209 @internal
210 Depending on the device voltage range, the maximum frequency should be
211 adapted accordingly:
212
213 (++) Table 1. HCLK clock frequency.
214 (++) +-------------------------------------------------------+
215 (++) | Latency | HCLK clock frequency (MHz) |
216 (++) | |-------------------------------------|
217 (++) | | voltage range 1 | voltage range 2 |
218 (++) | | 1.08V - 1.32V | 0.9 V - 1.10V |
219 (++) |-----------------|------------------|------------------|
220 (++) |0WS(1 CPU cycles)| HCLK <= 24 | HCLK <= 8 |
221 (++) |-----------------|------------------|------------------|
222 (++) |1WS(2 CPU cycles)| HCLK <= 48 | HCLK <= 16 |
223 (++) |-----------------|------------------|------------------|
224 (++) |2WS(3 CPU cycles)| HCLK <= 64 | - |
225 (++) |-----------------|------------------|------------------|
226
227 @endinternal
228 * @{
229 */
230
231/**
232 * @brief This function sets directly SystemCoreClock CMSIS variable.
233 * @note Variable can be calculated also through SystemCoreClockUpdate function.
234 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
235 * @retval None
236 */
237void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
238{
239 /* HCLK clock frequency */
240 SystemCoreClock = HCLKFrequency;
241}
242
243/**
244 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
245 * @note The application need to ensure that PLL is disabled.
246 * @note Function is based on the following formula:
247 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
248 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
249 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
250 * - PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
251 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
252 * the configuration information for the PLL.
253 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
254 * the configuration information for the BUS prescalers.
255 * @retval An ErrorStatus enumeration value:
256 * - SUCCESS: Max frequency configuration done
257 * - ERROR: Max frequency configuration not done
258 */
259ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
260 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
261{
262 ErrorStatus status;
263 uint32_t pllfreq;
264
265 /* Check if one of the PLL is enabled */
266 if (UTILS_PLL_IsBusy() == SUCCESS)
267 {
268 /* Calculate the new PLL output frequency */
269 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
270
271 /* Enable HSI if not enabled */
272 if (LL_RCC_HSI_IsReady() != 1U)
273 {
274 LL_RCC_HSI_Enable();
275 while (LL_RCC_HSI_IsReady() != 1U)
276 {
277 /* Wait for HSI ready */
278 }
279 }
280
281 /* Configure PLL */
282 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
283 UTILS_PLLInitStruct->PLLR);
284
285 /* Enable PLL and switch system clock to PLL */
286 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
287 }
288 else
289 {
290 /* Current PLL configuration cannot be modified */
291 status = ERROR;
292 }
293
294 return status;
295}
296
297/**
298 * @brief This function configures system clock with HSE as clock source of the PLL
299 * @note The application need to ensure that PLL is disabled.
300 * @note Function is based on the following formula:
301 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
302 * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
303 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
304 * - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
305 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
306 * @param HSEBypass This parameter can be one of the following values:
307 * @arg @ref LL_UTILS_HSEBYPASS_ON
308 * @arg @ref LL_UTILS_HSEBYPASS_OFF
309 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
310 * the configuration information for the PLL.
311 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
312 * the configuration information for the BUS prescalers.
313 * @retval An ErrorStatus enumeration value:
314 * - SUCCESS: Max frequency configuration done
315 * - ERROR: Max frequency configuration not done
316 */
317ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
318 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
319{
320 ErrorStatus status;
321 uint32_t pllfreq;
322
323 /* Check the parameters */
324 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
325 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
326
327 /* Check if one of the PLL is enabled */
328 if (UTILS_PLL_IsBusy() == SUCCESS)
329 {
330 /* Calculate the new PLL output frequency */
331 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
332
333 /* Enable HSE if not enabled */
334 if (LL_RCC_HSE_IsReady() != 1U)
335 {
336 /* Check if need to enable HSE bypass feature or not */
337 if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
338 {
339 LL_RCC_HSE_EnableBypass();
340 }
341 else
342 {
343 LL_RCC_HSE_DisableBypass();
344 }
345
346 /* Enable HSE */
347 LL_RCC_HSE_Enable();
348 while (LL_RCC_HSE_IsReady() != 1U)
349 {
350 /* Wait for HSE ready */
351 }
352 }
353
354 /* Configure PLL */
355 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
356 UTILS_PLLInitStruct->PLLR);
357
358 /* Enable PLL and switch system clock to PLL */
359 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
360 }
361 else
362 {
363 /* Current PLL configuration cannot be modified */
364 status = ERROR;
365 }
366
367 return status;
368}
369
370/**
371 * @}
372 */
373
374/**
375 * @}
376 */
377
378/** @addtogroup UTILS_LL_Private_Functions
379 * @{
380 */
381/**
382 * @brief Update number of Flash wait states in line with new frequency and current
383 voltage range.
384 * @param HCLK_Frequency HCLK frequency
385 * @retval An ErrorStatus enumeration value:
386 * - SUCCESS: Latency has been modified
387 * - ERROR: Latency cannot be modified
388 */
389static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
390{
391 ErrorStatus status = SUCCESS;
392
393 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
394
395 /* Frequency cannot be equal to 0 */
396 if (HCLK_Frequency == 0U)
397 {
398 status = ERROR;
399 }
400 else
401 {
402 if (HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
403 {
404 /* 48 < HCLK <= 64 => 2WS (3 CPU cycles) */
405 latency = LL_FLASH_LATENCY_2;
406 }
407 else
408 {
409 if (HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
410 {
411 /* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */
412 latency = LL_FLASH_LATENCY_1;
413 }
414 /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
415 }
416
417 LL_FLASH_SetLatency(latency);
418
419 /* Check that the new number of wait states is taken into account to access the Flash
420 memory by reading the FLASH_ACR register */
421 if (LL_FLASH_GetLatency() != latency)
422 {
423 status = ERROR;
424 }
425 }
426 return status;
427}
428
429/**
430 * @brief Function to check that PLL can be modified
431 * @param PLL_InputFrequency PLL input frequency (in Hz)
432 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
433 * the configuration information for the PLL.
434 * @retval PLL output frequency (in Hz)
435 */
436static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
437{
438 uint32_t pllfreq;
439
440 /* Check the parameters */
441 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
442 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
443 assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
444
445 /* Check different PLL parameters according to RM */
446 /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */
447 pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
448 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
449
450 /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
451 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
452 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
453
454 /* - PLLR: ensure that max frequency at 64000000 Hz is reached */
455 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U));
456 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
457
458 return pllfreq;
459}
460
461/**
462 * @brief Function to check that PLL can be modified
463 * @retval An ErrorStatus enumeration value:
464 * - SUCCESS: PLL modification can be done
465 * - ERROR: PLL is busy
466 */
467static ErrorStatus UTILS_PLL_IsBusy(void)
468{
469 ErrorStatus status = SUCCESS;
470
471 /* Check if PLL is busy*/
472 if (LL_RCC_PLL_IsReady() != 0U)
473 {
474 /* PLL configuration cannot be modified */
475 status = ERROR;
476 }
477
478 return status;
479}
480
481/**
482 * @brief Function to enable PLL and switch system clock to PLL
483 * @param SYSCLK_Frequency SYSCLK frequency
484 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
485 * the configuration information for the BUS prescalers.
486 * @retval An ErrorStatus enumeration value:
487 * - SUCCESS: No problem to switch system to PLL
488 * - ERROR: Problem to switch system to PLL
489 */
490static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
491{
492 ErrorStatus status = SUCCESS;
493 uint32_t hclk_frequency;
494
495 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
496 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
497
498 /* Calculate HCLK frequency */
499 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
500
501 /* Increasing the number of wait states because of higher CPU frequency */
502 if (SystemCoreClock < hclk_frequency)
503 {
504 /* Set FLASH latency to highest latency */
505 status = UTILS_SetFlashLatency(hclk_frequency);
506 }
507
508 /* Update system clock configuration */
509 if (status == SUCCESS)
510 {
511 /* Enable PLL */
512 LL_RCC_PLL_Enable();
513 LL_RCC_PLL_EnableDomain_SYS();
514 while (LL_RCC_PLL_IsReady() != 1U)
515 {
516 /* Wait for PLL ready */
517 }
518
519 /* Sysclk activation on the main PLL */
520 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
521 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
522 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
523 {
524 /* Wait for system clock switch to PLL */
525 }
526
527 /* Set APB1 & APB2 prescaler*/
528 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
529 }
530
531 /* Decreasing the number of wait states because of lower CPU frequency */
532 if (SystemCoreClock > hclk_frequency)
533 {
534 /* Set FLASH latency to lowest latency */
535 status = UTILS_SetFlashLatency(hclk_frequency);
536 }
537
538 /* Update SystemCoreClock variable */
539 if (status == SUCCESS)
540 {
541 LL_SetSystemCoreClock(hclk_frequency);
542 }
543
544 return status;
545}
546
547/**
548 * @}
549 */
550
551/**
552 * @}
553 */
554
555/**
556 * @}
557 */
558
559/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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