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stm32g0xx_ll_tim.c

Last change on this file was 6, checked in by f.jahn, 8 months ago

File size: 54.0 KB

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_ll_tim.c
4	* @author MCD Application Team
5	* @brief TIM LL module driver.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19	#if defined(USE_FULL_LL_DRIVER)
20
21	/* Includes ------------------------------------------------------------------*/
22	#include "stm32g0xx_ll_tim.h"
23	#include "stm32g0xx_ll_bus.h"
24
25	#ifdef USE_FULL_ASSERT
26	#include "stm32_assert.h"
27	#else
28	#define assert_param(expr) ((void)0U)
29	#endif
30
31	/** @addtogroup STM32G0xx_LL_Driver
32	* @{
33	*/
34
35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
36
37	/** @addtogroup TIM_LL
38	* @{
39	*/
40
41	/* Private types -------------------------------------------------------------*/
42	/* Private variables ---------------------------------------------------------*/
43	/* Private constants ---------------------------------------------------------*/
44	/* Private macros ------------------------------------------------------------*/
45	/** @addtogroup TIM_LL_Private_Macros
46	* @{
47	*/
48	#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53
54	#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57
58	#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59	\|\| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60	\|\| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61	\|\| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
66	\|\| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
67	\|\| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
68	\|\| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
69	\|\| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
70	\|\| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
71	\|\| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
72
73	#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
74	\|\| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
75
76	#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
77	\|\| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
78
79	#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
80	\|\| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
81
82	#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
83	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
84	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
85
86	#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
87	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
88	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
89	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
90
91	#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
92	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
93	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
94	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
95	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
96	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
97	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
98	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
99	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
100	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
101	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
102	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
103	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
104	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
105	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
106	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
107
108	#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
109	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
110	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
111
112	#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
113	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
114	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
115
116	#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
117	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
118
119	#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
120	\|\| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
121
122	#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
123	\|\| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
124
125	#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
126	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
127	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
128	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
129
130	#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
131	\|\| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
132
133	#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
134	\|\| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
135
136	#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
137	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
138	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
139	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
140	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
141	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
142	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
143	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
144	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
145	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
146	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
147	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
148	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
149	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
150	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
151	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
152
153	#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
154	\|\| ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
155
156	#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
157	\|\| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
158
159	#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
160	\|\| ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
161
162	#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
163	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
164	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
165	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
166	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
167	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
168	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
169	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
170	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
171	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
172	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
173	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
174	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
175	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
176	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
177	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
178
179	#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
180	\|\| ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
181
182	#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
183	\|\| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
184	/**
185	* @}
186	*/
187
188
189	/* Private function prototypes -----------------------------------------------*/
190	/** @defgroup TIM_LL_Private_Functions TIM Private Functions
191	* @{
192	*/
193	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
194	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
195	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
196	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
197	static ErrorStatus OC5Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
198	static ErrorStatus OC6Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
199	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
200	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
201	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
202	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
203	/**
204	* @}
205	*/
206
207	/* Exported functions --------------------------------------------------------*/
208	/** @addtogroup TIM_LL_Exported_Functions
209	* @{
210	*/
211
212	/** @addtogroup TIM_LL_EF_Init
213	* @{
214	*/
215
216	/**
217	* @brief Set TIMx registers to their reset values.
218	* @param TIMx Timer instance
219	* @retval An ErrorStatus enumeration value:
220	* - SUCCESS: TIMx registers are de-initialized
221	* - ERROR: invalid TIMx instance
222	*/
223	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
224	{
225	ErrorStatus result = SUCCESS;
226
227	/* Check the parameters */
228	assert_param(IS_TIM_INSTANCE(TIMx));
229
230	if (TIMx == TIM1)
231	{
232	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
233	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
234	}
235	#if defined(TIM2)
236	else if (TIMx == TIM2)
237	{
238	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
239	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
240	}
241	#endif
242	#if defined(TIM3)
243	else if (TIMx == TIM3)
244	{
245	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
246	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
247	}
248	#endif
249	#if defined(TIM6)
250	else if (TIMx == TIM6)
251	{
252	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
253	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
254	}
255	#endif
256	#if defined(TIM7)
257	else if (TIMx == TIM7)
258	{
259	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
260	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
261	}
262	#endif
263	else if (TIMx == TIM14)
264	{
265	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14);
266	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14);
267	}
268	#if defined(TIM15)
269	else if (TIMx == TIM15)
270	{
271	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
272	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
273	}
274	#endif
275	else if (TIMx == TIM16)
276	{
277	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
278	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
279	}
280	#if defined(TIM17)
281	else if (TIMx == TIM17)
282	{
283	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
284	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
285	}
286	#endif
287	else
288	{
289	result = ERROR;
290	}
291
292	return result;
293	}
294
295	/**
296	* @brief Set the fields of the time base unit configuration data structure
297	* to their default values.
298	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
299	* @retval None
300	*/
301	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
302	{
303	/* Set the default configuration */
304	TIM_InitStruct->Prescaler = (uint16_t)0x0000;
305	TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
306	TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
307	TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
308	TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
309	}
310
311	/**
312	* @brief Configure the TIMx time base unit.
313	* @param TIMx Timer Instance
314	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
315	* @retval An ErrorStatus enumeration value:
316	* - SUCCESS: TIMx registers are de-initialized
317	* - ERROR: not applicable
318	*/
319	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct)
320	{
321	uint32_t tmpcr1;
322
323	/* Check the parameters */
324	assert_param(IS_TIM_INSTANCE(TIMx));
325	assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
326	assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
327
328	tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
329
330	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
331	{
332	/* Select the Counter Mode */
333	MODIFY_REG(tmpcr1, (TIM_CR1_DIR \| TIM_CR1_CMS), TIM_InitStruct->CounterMode);
334	}
335
336	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
337	{
338	/* Set the clock division */
339	MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
340	}
341
342	/* Write to TIMx CR1 */
343	LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
344
345	/* Set the Autoreload value */
346	LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
347
348	/* Set the Prescaler value */
349	LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
350
351	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
352	{
353	/* Set the Repetition Counter value */
354	LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
355	}
356
357	/* Generate an update event to reload the Prescaler
358	and the repetition counter value (if applicable) immediately */
359	LL_TIM_GenerateEvent_UPDATE(TIMx);
360
361	return SUCCESS;
362	}
363
364	/**
365	* @brief Set the fields of the TIMx output channel configuration data
366	* structure to their default values.
367	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
368	* @retval None
369	*/
370	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
371	{
372	/* Set the default configuration */
373	TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
374	TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
375	TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
376	TIM_OC_InitStruct->CompareValue = 0x00000000U;
377	TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
378	TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
379	TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
380	TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
381	}
382
383	/**
384	* @brief Configure the TIMx output channel.
385	* @param TIMx Timer Instance
386	* @param Channel This parameter can be one of the following values:
387	* @arg @ref LL_TIM_CHANNEL_CH1
388	* @arg @ref LL_TIM_CHANNEL_CH2
389	* @arg @ref LL_TIM_CHANNEL_CH3
390	* @arg @ref LL_TIM_CHANNEL_CH4
391	* @arg @ref LL_TIM_CHANNEL_CH5
392	* @arg @ref LL_TIM_CHANNEL_CH6
393	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
394	* @retval An ErrorStatus enumeration value:
395	* - SUCCESS: TIMx output channel is initialized
396	* - ERROR: TIMx output channel is not initialized
397	*/
398	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct)
399	{
400	ErrorStatus result = ERROR;
401
402	switch (Channel)
403	{
404	case LL_TIM_CHANNEL_CH1:
405	result = OC1Config(TIMx, TIM_OC_InitStruct);
406	break;
407	case LL_TIM_CHANNEL_CH2:
408	result = OC2Config(TIMx, TIM_OC_InitStruct);
409	break;
410	case LL_TIM_CHANNEL_CH3:
411	result = OC3Config(TIMx, TIM_OC_InitStruct);
412	break;
413	case LL_TIM_CHANNEL_CH4:
414	result = OC4Config(TIMx, TIM_OC_InitStruct);
415	break;
416	case LL_TIM_CHANNEL_CH5:
417	result = OC5Config(TIMx, TIM_OC_InitStruct);
418	break;
419	case LL_TIM_CHANNEL_CH6:
420	result = OC6Config(TIMx, TIM_OC_InitStruct);
421	break;
422	default:
423	break;
424	}
425
426	return result;
427	}
428
429	/**
430	* @brief Set the fields of the TIMx input channel configuration data
431	* structure to their default values.
432	* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
433	* @retval None
434	*/
435	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
436	{
437	/* Set the default configuration */
438	TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
439	TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
440	TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
441	TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
442	}
443
444	/**
445	* @brief Configure the TIMx input channel.
446	* @param TIMx Timer Instance
447	* @param Channel This parameter can be one of the following values:
448	* @arg @ref LL_TIM_CHANNEL_CH1
449	* @arg @ref LL_TIM_CHANNEL_CH2
450	* @arg @ref LL_TIM_CHANNEL_CH3
451	* @arg @ref LL_TIM_CHANNEL_CH4
452	* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
453	* @retval An ErrorStatus enumeration value:
454	* - SUCCESS: TIMx output channel is initialized
455	* - ERROR: TIMx output channel is not initialized
456	*/
457	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct)
458	{
459	ErrorStatus result = ERROR;
460
461	switch (Channel)
462	{
463	case LL_TIM_CHANNEL_CH1:
464	result = IC1Config(TIMx, TIM_IC_InitStruct);
465	break;
466	case LL_TIM_CHANNEL_CH2:
467	result = IC2Config(TIMx, TIM_IC_InitStruct);
468	break;
469	case LL_TIM_CHANNEL_CH3:
470	result = IC3Config(TIMx, TIM_IC_InitStruct);
471	break;
472	case LL_TIM_CHANNEL_CH4:
473	result = IC4Config(TIMx, TIM_IC_InitStruct);
474	break;
475	default:
476	break;
477	}
478
479	return result;
480	}
481
482	/**
483	* @brief Fills each TIM_EncoderInitStruct field with its default value
484	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
485	* @retval None
486	*/
487	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
488	{
489	/* Set the default configuration */
490	TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
491	TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
492	TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
493	TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
494	TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
495	TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
496	TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
497	TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
498	TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
499	}
500
501	/**
502	* @brief Configure the encoder interface of the timer instance.
503	* @param TIMx Timer Instance
504	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
505	* @retval An ErrorStatus enumeration value:
506	* - SUCCESS: TIMx registers are de-initialized
507	* - ERROR: not applicable
508	*/
509	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct)
510	{
511	uint32_t tmpccmr1;
512	uint32_t tmpccer;
513
514	/* Check the parameters */
515	assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
516	assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
517	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
518	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
519	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
520	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
521	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
522	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
523	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
524	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
525
526	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
527	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
528
529	/* Get the TIMx CCMR1 register value */
530	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
531
532	/* Get the TIMx CCER register value */
533	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
534
535	/* Configure TI1 */
536	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
537	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
538	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
539	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
540
541	/* Configure TI2 */
542	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC);
543	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
544	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
545	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
546
547	/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
548	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
549	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
550	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
551	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
552
553	/* Set encoder mode */
554	LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
555
556	/* Write to TIMx CCMR1 */
557	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
558
559	/* Write to TIMx CCER */
560	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
561
562	return SUCCESS;
563	}
564
565	/**
566	* @brief Set the fields of the TIMx Hall sensor interface configuration data
567	* structure to their default values.
568	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
569	* @retval None
570	*/
571	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
572	{
573	/* Set the default configuration */
574	TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
575	TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
576	TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
577	TIM_HallSensorInitStruct->CommutationDelay = 0U;
578	}
579
580	/**
581	* @brief Configure the Hall sensor interface of the timer instance.
582	* @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
583	* to the TI1 input channel
584	* @note TIMx slave mode controller is configured in reset mode.
585	Selected internal trigger is TI1F_ED.
586	* @note Channel 1 is configured as input, IC1 is mapped on TRC.
587	* @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
588	* between 2 changes on the inputs. It gives information about motor speed.
589	* @note Channel 2 is configured in output PWM 2 mode.
590	* @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
591	* @note OC2REF is selected as trigger output on TRGO.
592	* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
593	* when TIMx operates in Hall sensor interface mode.
594	* @param TIMx Timer Instance
595	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
596	* @retval An ErrorStatus enumeration value:
597	* - SUCCESS: TIMx registers are de-initialized
598	* - ERROR: not applicable
599	*/
600	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct)
601	{
602	uint32_t tmpcr2;
603	uint32_t tmpccmr1;
604	uint32_t tmpccer;
605	uint32_t tmpsmcr;
606
607	/* Check the parameters */
608	assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
609	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
610	assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
611	assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
612
613	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
614	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
615
616	/* Get the TIMx CR2 register value */
617	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
618
619	/* Get the TIMx CCMR1 register value */
620	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
621
622	/* Get the TIMx CCER register value */
623	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
624
625	/* Get the TIMx SMCR register value */
626	tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
627
628	/* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
629	tmpcr2 \|= TIM_CR2_TI1S;
630
631	/* OC2REF signal is used as trigger output (TRGO) */
632	tmpcr2 \|= LL_TIM_TRGO_OC2REF;
633
634	/* Configure the slave mode controller */
635	tmpsmcr &= (uint32_t)~(TIM_SMCR_TS \| TIM_SMCR_SMS);
636	tmpsmcr \|= LL_TIM_TS_TI1F_ED;
637	tmpsmcr \|= LL_TIM_SLAVEMODE_RESET;
638
639	/* Configure input channel 1 */
640	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
641	tmpccmr1 \|= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
642	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
643	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
644
645	/* Configure input channel 2 */
646	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M \| TIM_CCMR1_OC2FE \| TIM_CCMR1_OC2PE \| TIM_CCMR1_OC2CE);
647	tmpccmr1 \|= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
648
649	/* Set Channel 1 polarity and enable Channel 1 and Channel2 */
650	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
651	tmpccer \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
652	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
653
654	/* Write to TIMx CR2 */
655	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
656
657	/* Write to TIMx SMCR */
658	LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
659
660	/* Write to TIMx CCMR1 */
661	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
662
663	/* Write to TIMx CCER */
664	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
665
666	/* Write to TIMx CCR2 */
667	LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
668
669	return SUCCESS;
670	}
671
672	/**
673	* @brief Set the fields of the Break and Dead Time configuration data structure
674	* to their default values.
675	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
676	* @retval None
677	*/
678	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
679	{
680	/* Set the default configuration */
681	TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
682	TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
683	TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
684	TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
685	TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
686	TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
687	TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
688	TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
689	TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
690	TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
691	TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
692	TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
693	TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
694	}
695
696	/**
697	* @brief Configure the Break and Dead Time feature of the timer instance.
698	* @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
699	* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
700	* can be necessary to configure all of them during the first write access to
701	* the TIMx_BDTR register.
702	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
703	* a timer instance provides a break input.
704	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
705	* a timer instance provides a second break input.
706	* @param TIMx Timer Instance
707	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
708	* @retval An ErrorStatus enumeration value:
709	* - SUCCESS: Break and Dead Time is initialized
710	* - ERROR: not applicable
711	*/
712	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct)
713	{
714	uint32_t tmpbdtr = 0;
715
716	/* Check the parameters */
717	assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
718	assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
719	assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
720	assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
721	assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
722	assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
723	assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
724
725	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
726	the OSSI State, the dead time value and the Automatic Output Enable Bit */
727
728	/* Set the BDTR bits */
729	MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
730	MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
731	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
732	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
733	MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
734	MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
735	MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
736	MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
737	if (IS_TIM_ADVANCED_INSTANCE(TIMx))
738	{
739	assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
740	assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
741	MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
742	MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
743	}
744
745	if (IS_TIM_BKIN2_INSTANCE(TIMx))
746	{
747	assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
748	assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
749	assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
750	assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
751
752	/* Set the BREAK2 input related BDTR bit-fields */
753	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
754	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
755	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
756	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
757	}
758
759	/* Set TIMx_BDTR */
760	LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
761
762	return SUCCESS;
763	}
764	/**
765	* @}
766	*/
767
768	/**
769	* @}
770	*/
771
772	/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
773	* @brief Private functions
774	* @{
775	*/
776	/**
777	* @brief Configure the TIMx output channel 1.
778	* @param TIMx Timer Instance
779	* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
780	* @retval An ErrorStatus enumeration value:
781	* - SUCCESS: TIMx registers are de-initialized
782	* - ERROR: not applicable
783	*/
784	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
785	{
786	uint32_t tmpccmr1;
787	uint32_t tmpccer;
788	uint32_t tmpcr2;
789
790	/* Check the parameters */
791	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
792	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
793	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
794	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
795	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
796	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
797
798	/* Disable the Channel 1: Reset the CC1E Bit */
799	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
800
801	/* Get the TIMx CCER register value */
802	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
803
804	/* Get the TIMx CR2 register value */
805	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
806
807	/* Get the TIMx CCMR1 register value */
808	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
809
810	/* Reset Capture/Compare selection Bits */
811	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
812
813	/* Set the Output Compare Mode */
814	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
815
816	/* Set the Output Compare Polarity */
817	MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
818
819	/* Set the Output State */
820	MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
821
822	if (IS_TIM_BREAK_INSTANCE(TIMx))
823	{
824	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
825	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
826
827	/* Set the complementary output Polarity */
828	MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
829
830	/* Set the complementary output State */
831	MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
832
833	/* Set the Output Idle state */
834	MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
835
836	/* Set the complementary output Idle state */
837	MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
838	}
839
840	/* Write to TIMx CR2 */
841	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
842
843	/* Write to TIMx CCMR1 */
844	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
845
846	/* Set the Capture Compare Register value */
847	LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
848
849	/* Write to TIMx CCER */
850	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
851
852	return SUCCESS;
853	}
854
855	/**
856	* @brief Configure the TIMx output channel 2.
857	* @param TIMx Timer Instance
858	* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
859	* @retval An ErrorStatus enumeration value:
860	* - SUCCESS: TIMx registers are de-initialized
861	* - ERROR: not applicable
862	*/
863	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
864	{
865	uint32_t tmpccmr1;
866	uint32_t tmpccer;
867	uint32_t tmpcr2;
868
869	/* Check the parameters */
870	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
871	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
872	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
873	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
874	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
875	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
876
877	/* Disable the Channel 2: Reset the CC2E Bit */
878	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
879
880	/* Get the TIMx CCER register value */
881	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
882
883	/* Get the TIMx CR2 register value */
884	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
885
886	/* Get the TIMx CCMR1 register value */
887	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
888
889	/* Reset Capture/Compare selection Bits */
890	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
891
892	/* Select the Output Compare Mode */
893	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
894
895	/* Set the Output Compare Polarity */
896	MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
897
898	/* Set the Output State */
899	MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
900
901	if (IS_TIM_BREAK_INSTANCE(TIMx))
902	{
903	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
904	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
905
906	/* Set the complementary output Polarity */
907	MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
908
909	/* Set the complementary output State */
910	MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
911
912	/* Set the Output Idle state */
913	MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
914
915	/* Set the complementary output Idle state */
916	MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
917	}
918
919	/* Write to TIMx CR2 */
920	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
921
922	/* Write to TIMx CCMR1 */
923	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
924
925	/* Set the Capture Compare Register value */
926	LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
927
928	/* Write to TIMx CCER */
929	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
930
931	return SUCCESS;
932	}
933
934	/**
935	* @brief Configure the TIMx output channel 3.
936	* @param TIMx Timer Instance
937	* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
938	* @retval An ErrorStatus enumeration value:
939	* - SUCCESS: TIMx registers are de-initialized
940	* - ERROR: not applicable
941	*/
942	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
943	{
944	uint32_t tmpccmr2;
945	uint32_t tmpccer;
946	uint32_t tmpcr2;
947
948	/* Check the parameters */
949	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
950	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
951	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
952	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
953	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
954	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
955
956	/* Disable the Channel 3: Reset the CC3E Bit */
957	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
958
959	/* Get the TIMx CCER register value */
960	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
961
962	/* Get the TIMx CR2 register value */
963	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
964
965	/* Get the TIMx CCMR2 register value */
966	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
967
968	/* Reset Capture/Compare selection Bits */
969	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
970
971	/* Select the Output Compare Mode */
972	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
973
974	/* Set the Output Compare Polarity */
975	MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
976
977	/* Set the Output State */
978	MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
979
980	if (IS_TIM_BREAK_INSTANCE(TIMx))
981	{
982	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
983	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
984
985	/* Set the complementary output Polarity */
986	MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
987
988	/* Set the complementary output State */
989	MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
990
991	/* Set the Output Idle state */
992	MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
993
994	/* Set the complementary output Idle state */
995	MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
996	}
997
998	/* Write to TIMx CR2 */
999	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1000
1001	/* Write to TIMx CCMR2 */
1002	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1003
1004	/* Set the Capture Compare Register value */
1005	LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1006
1007	/* Write to TIMx CCER */
1008	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1009
1010	return SUCCESS;
1011	}
1012
1013	/**
1014	* @brief Configure the TIMx output channel 4.
1015	* @param TIMx Timer Instance
1016	* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1017	* @retval An ErrorStatus enumeration value:
1018	* - SUCCESS: TIMx registers are de-initialized
1019	* - ERROR: not applicable
1020	*/
1021	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
1022	{
1023	uint32_t tmpccmr2;
1024	uint32_t tmpccer;
1025	uint32_t tmpcr2;
1026
1027	/* Check the parameters */
1028	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1029	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1030	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1031	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1032	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1033	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1034
1035	/* Disable the Channel 4: Reset the CC4E Bit */
1036	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1037
1038	/* Get the TIMx CCER register value */
1039	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1040
1041	/* Get the TIMx CR2 register value */
1042	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1043
1044	/* Get the TIMx CCMR2 register value */
1045	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1046
1047	/* Reset Capture/Compare selection Bits */
1048	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1049
1050	/* Select the Output Compare Mode */
1051	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1052
1053	/* Set the Output Compare Polarity */
1054	MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1055
1056	/* Set the Output State */
1057	MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1058
1059	if (IS_TIM_BREAK_INSTANCE(TIMx))
1060	{
1061	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1062	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1063
1064	/* Set the Output Idle state */
1065	MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1066	}
1067
1068	/* Write to TIMx CR2 */
1069	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1070
1071	/* Write to TIMx CCMR2 */
1072	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1073
1074	/* Set the Capture Compare Register value */
1075	LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1076
1077	/* Write to TIMx CCER */
1078	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1079
1080	return SUCCESS;
1081	}
1082
1083	/**
1084	* @brief Configure the TIMx output channel 5.
1085	* @param TIMx Timer Instance
1086	* @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1087	* @retval An ErrorStatus enumeration value:
1088	* - SUCCESS: TIMx registers are de-initialized
1089	* - ERROR: not applicable
1090	*/
1091	static ErrorStatus OC5Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
1092	{
1093	uint32_t tmpccmr3;
1094	uint32_t tmpccer;
1095
1096	/* Check the parameters */
1097	assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1098	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1099	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1100	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1101	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1102	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1103
1104	/* Disable the Channel 5: Reset the CC5E Bit */
1105	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1106
1107	/* Get the TIMx CCER register value */
1108	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1109
1110	/* Get the TIMx CCMR3 register value */
1111	tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1112
1113	/* Select the Output Compare Mode */
1114	MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1115
1116	/* Set the Output Compare Polarity */
1117	MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1118
1119	/* Set the Output State */
1120	MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1121
1122	if (IS_TIM_BREAK_INSTANCE(TIMx))
1123	{
1124	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1125	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1126
1127	/* Set the Output Idle state */
1128	MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1129
1130	}
1131
1132	/* Write to TIMx CCMR3 */
1133	LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1134
1135	/* Set the Capture Compare Register value */
1136	LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1137
1138	/* Write to TIMx CCER */
1139	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1140
1141	return SUCCESS;
1142	}
1143
1144	/**
1145	* @brief Configure the TIMx output channel 6.
1146	* @param TIMx Timer Instance
1147	* @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1148	* @retval An ErrorStatus enumeration value:
1149	* - SUCCESS: TIMx registers are de-initialized
1150	* - ERROR: not applicable
1151	*/
1152	static ErrorStatus OC6Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
1153	{
1154	uint32_t tmpccmr3;
1155	uint32_t tmpccer;
1156
1157	/* Check the parameters */
1158	assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1159	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1160	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1161	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1162	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1163	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1164
1165	/* Disable the Channel 5: Reset the CC6E Bit */
1166	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1167
1168	/* Get the TIMx CCER register value */
1169	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1170
1171	/* Get the TIMx CCMR3 register value */
1172	tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1173
1174	/* Select the Output Compare Mode */
1175	MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1176
1177	/* Set the Output Compare Polarity */
1178	MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1179
1180	/* Set the Output State */
1181	MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1182
1183	if (IS_TIM_BREAK_INSTANCE(TIMx))
1184	{
1185	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1186	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1187
1188	/* Set the Output Idle state */
1189	MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1190	}
1191
1192	/* Write to TIMx CCMR3 */
1193	LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1194
1195	/* Set the Capture Compare Register value */
1196	LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1197
1198	/* Write to TIMx CCER */
1199	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1200
1201	return SUCCESS;
1202	}
1203
1204	/**
1205	* @brief Configure the TIMx input channel 1.
1206	* @param TIMx Timer Instance
1207	* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1208	* @retval An ErrorStatus enumeration value:
1209	* - SUCCESS: TIMx registers are de-initialized
1210	* - ERROR: not applicable
1211	*/
1212	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
1213	{
1214	/* Check the parameters */
1215	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1216	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1217	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1218	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1219	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1220
1221	/* Disable the Channel 1: Reset the CC1E Bit */
1222	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1223
1224	/* Select the Input and set the filter and the prescaler value */
1225	MODIFY_REG(TIMx->CCMR1,
1226	(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC),
1227	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
1228
1229	/* Select the Polarity and set the CC1E Bit */
1230	MODIFY_REG(TIMx->CCER,
1231	(TIM_CCER_CC1P \| TIM_CCER_CC1NP),
1232	(TIM_ICInitStruct->ICPolarity \| TIM_CCER_CC1E));
1233
1234	return SUCCESS;
1235	}
1236
1237	/**
1238	* @brief Configure the TIMx input channel 2.
1239	* @param TIMx Timer Instance
1240	* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1241	* @retval An ErrorStatus enumeration value:
1242	* - SUCCESS: TIMx registers are de-initialized
1243	* - ERROR: not applicable
1244	*/
1245	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
1246	{
1247	/* Check the parameters */
1248	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1249	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1250	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1251	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1252	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1253
1254	/* Disable the Channel 2: Reset the CC2E Bit */
1255	TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1256
1257	/* Select the Input and set the filter and the prescaler value */
1258	MODIFY_REG(TIMx->CCMR1,
1259	(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC),
1260	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
1261
1262	/* Select the Polarity and set the CC2E Bit */
1263	MODIFY_REG(TIMx->CCER,
1264	(TIM_CCER_CC2P \| TIM_CCER_CC2NP),
1265	((TIM_ICInitStruct->ICPolarity << 4U) \| TIM_CCER_CC2E));
1266
1267	return SUCCESS;
1268	}
1269
1270	/**
1271	* @brief Configure the TIMx input channel 3.
1272	* @param TIMx Timer Instance
1273	* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1274	* @retval An ErrorStatus enumeration value:
1275	* - SUCCESS: TIMx registers are de-initialized
1276	* - ERROR: not applicable
1277	*/
1278	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
1279	{
1280	/* Check the parameters */
1281	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1282	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1283	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1284	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1285	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1286
1287	/* Disable the Channel 3: Reset the CC3E Bit */
1288	TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1289
1290	/* Select the Input and set the filter and the prescaler value */
1291	MODIFY_REG(TIMx->CCMR2,
1292	(TIM_CCMR2_CC3S \| TIM_CCMR2_IC3F \| TIM_CCMR2_IC3PSC),
1293	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
1294
1295	/* Select the Polarity and set the CC3E Bit */
1296	MODIFY_REG(TIMx->CCER,
1297	(TIM_CCER_CC3P \| TIM_CCER_CC3NP),
1298	((TIM_ICInitStruct->ICPolarity << 8U) \| TIM_CCER_CC3E));
1299
1300	return SUCCESS;
1301	}
1302
1303	/**
1304	* @brief Configure the TIMx input channel 4.
1305	* @param TIMx Timer Instance
1306	* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1307	* @retval An ErrorStatus enumeration value:
1308	* - SUCCESS: TIMx registers are de-initialized
1309	* - ERROR: not applicable
1310	*/
1311	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
1312	{
1313	/* Check the parameters */
1314	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1315	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1316	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1317	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1318	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1319
1320	/* Disable the Channel 4: Reset the CC4E Bit */
1321	TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1322
1323	/* Select the Input and set the filter and the prescaler value */
1324	MODIFY_REG(TIMx->CCMR2,
1325	(TIM_CCMR2_CC4S \| TIM_CCMR2_IC4F \| TIM_CCMR2_IC4PSC),
1326	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
1327
1328	/* Select the Polarity and set the CC2E Bit */
1329	MODIFY_REG(TIMx->CCER,
1330	(TIM_CCER_CC4P \| TIM_CCER_CC4NP),
1331	((TIM_ICInitStruct->ICPolarity << 12U) \| TIM_CCER_CC4E));
1332
1333	return SUCCESS;
1334	}
1335
1336
1337	/**
1338	* @}
1339	*/
1340
1341	/**
1342	* @}
1343	*/
1344
1345	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
1346
1347	/**
1348	* @}
1349	*/
1350
1351	#endif /* USE_FULL_LL_DRIVER */
1352
1353	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c

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