| 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32g0xx_ll_spi.c
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| 4 | * @author MCD Application Team
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| 5 | * @brief SPI LL module driver.
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| 6 | ******************************************************************************
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| 7 | * @attention
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| 8 | *
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| 9 | * <h2><center>© Copyright (c) 2018 STMicroelectronics.
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| 10 | * All rights reserved.</center></h2>
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| 11 | *
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| 12 | * This software component is licensed by ST under BSD 3-Clause license,
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| 13 | * the "License"; You may not use this file except in compliance with the
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| 14 | * License. You may obtain a copy of the License at:
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| 15 | * opensource.org/licenses/BSD-3-Clause
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| 16 | *
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| 17 | ******************************************************************************
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| 18 | */
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| 19 | #if defined(USE_FULL_LL_DRIVER)
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| 20 |
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| 21 | /* Includes ------------------------------------------------------------------*/
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| 22 | #include "stm32g0xx_ll_spi.h"
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| 23 | #include "stm32g0xx_ll_bus.h"
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| 24 | #include "stm32g0xx_ll_rcc.h"
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| 25 |
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| 26 | #ifdef USE_FULL_ASSERT
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| 27 | #include "stm32_assert.h"
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| 28 | #else
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| 29 | #define assert_param(expr) ((void)0U)
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| 30 | #endif
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| 31 |
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| 32 | /** @addtogroup STM32G0xx_LL_Driver
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| 33 | * @{
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| 34 | */
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| 35 |
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| 36 | #if defined (SPI1) || defined (SPI2)
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| 37 |
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| 38 | /** @addtogroup SPI_LL
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| 39 | * @{
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| 40 | */
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| 41 |
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| 42 | /* Private types -------------------------------------------------------------*/
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| 43 | /* Private variables ---------------------------------------------------------*/
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| 44 |
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| 45 | /* Private constants ---------------------------------------------------------*/
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| 46 | /** @defgroup SPI_LL_Private_Constants SPI Private Constants
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| 47 | * @{
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| 48 | */
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| 49 | /* SPI registers Masks */
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| 50 | #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
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| 51 | SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
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| 52 | SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
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| 53 | SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
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| 54 | SPI_CR1_BIDIMODE)
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| 55 | /**
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| 56 | * @}
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| 57 | */
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| 58 |
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| 59 | /* Private macros ------------------------------------------------------------*/
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| 60 | /** @defgroup SPI_LL_Private_Macros SPI Private Macros
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| 61 | * @{
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| 62 | */
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| 63 | #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
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| 64 | || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
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| 65 | || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
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| 66 | || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
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| 67 |
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| 68 | #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
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| 69 | || ((__VALUE__) == LL_SPI_MODE_SLAVE))
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| 70 |
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| 71 | #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
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| 72 | || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
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| 73 | || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
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| 74 | || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
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| 75 | || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
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| 76 | || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
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| 77 | || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
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| 78 | || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
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| 79 | || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
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| 80 | || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
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| 81 | || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
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| 82 | || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
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| 83 | || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
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| 84 |
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| 85 | #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
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| 86 | || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
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| 87 |
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| 88 | #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
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| 89 | || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
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| 90 |
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| 91 | #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
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| 92 | || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
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| 93 | || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
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| 94 |
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| 95 | #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
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| 96 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
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| 97 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
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| 98 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
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| 99 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
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| 100 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
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| 101 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
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| 102 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
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| 103 |
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| 104 | #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
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| 105 | || ((__VALUE__) == LL_SPI_MSB_FIRST))
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| 106 |
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| 107 | #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
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| 108 | || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
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| 109 |
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| 110 | #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
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| 111 |
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| 112 | /**
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| 113 | * @}
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| 114 | */
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| 115 |
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| 116 | /* Private function prototypes -----------------------------------------------*/
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| 117 |
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| 118 | /* Exported functions --------------------------------------------------------*/
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| 119 | /** @addtogroup SPI_LL_Exported_Functions
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| 120 | * @{
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| 121 | */
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| 122 |
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| 123 | /** @addtogroup SPI_LL_EF_Init
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| 124 | * @{
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| 125 | */
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| 126 |
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| 127 | /**
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| 128 | * @brief De-initialize the SPI registers to their default reset values.
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| 129 | * @param SPIx SPI Instance
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| 130 | * @retval An ErrorStatus enumeration value:
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| 131 | * - SUCCESS: SPI registers are de-initialized
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| 132 | * - ERROR: SPI registers are not de-initialized
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| 133 | */
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| 134 | ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
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| 135 | {
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| 136 | ErrorStatus status = ERROR;
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| 137 |
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| 138 | /* Check the parameters */
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| 139 | assert_param(IS_SPI_ALL_INSTANCE(SPIx));
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| 140 |
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| 141 | #if defined(SPI1)
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| 142 | if (SPIx == SPI1)
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| 143 | {
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| 144 | /* Force reset of SPI clock */
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| 145 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
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| 146 |
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| 147 | /* Release reset of SPI clock */
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| 148 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
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| 149 |
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| 150 | status = SUCCESS;
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| 151 | }
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| 152 | #endif /* SPI1 */
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| 153 | #if defined(SPI2)
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| 154 | if (SPIx == SPI2)
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| 155 | {
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| 156 | /* Force reset of SPI clock */
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| 157 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
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| 158 |
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| 159 | /* Release reset of SPI clock */
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| 160 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
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| 161 |
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| 162 | status = SUCCESS;
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| 163 | }
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| 164 | #endif /* SPI2 */
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| 165 |
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| 166 | return status;
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| 167 | }
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| 168 |
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| 169 | /**
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| 170 | * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
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| 171 | * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
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| 172 | * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
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| 173 | * @param SPIx SPI Instance
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| 174 | * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
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| 175 | * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
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| 176 | */
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| 177 | ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
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| 178 | {
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| 179 | ErrorStatus status = ERROR;
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| 180 |
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| 181 | /* Check the SPI Instance SPIx*/
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| 182 | assert_param(IS_SPI_ALL_INSTANCE(SPIx));
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| 183 |
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| 184 | /* Check the SPI parameters from SPI_InitStruct*/
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| 185 | assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
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| 186 | assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
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| 187 | assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
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| 188 | assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
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| 189 | assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
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| 190 | assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
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| 191 | assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
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| 192 | assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
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| 193 | assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
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| 194 |
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| 195 | if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
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| 196 | {
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| 197 | /*---------------------------- SPIx CR1 Configuration ------------------------
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| 198 | * Configure SPIx CR1 with parameters:
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| 199 | * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
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| 200 | * - Master/Slave Mode: SPI_CR1_MSTR bit
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| 201 | * - ClockPolarity: SPI_CR1_CPOL bit
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| 202 | * - ClockPhase: SPI_CR1_CPHA bit
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| 203 | * - NSS management: SPI_CR1_SSM bit
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| 204 | * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
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| 205 | * - BitOrder: SPI_CR1_LSBFIRST bit
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| 206 | * - CRCCalculation: SPI_CR1_CRCEN bit
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| 207 | */
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| 208 | MODIFY_REG(SPIx->CR1,
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| 209 | SPI_CR1_CLEAR_MASK,
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| 210 | SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
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| 211 | SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
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| 212 | SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
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| 213 | SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
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| 214 |
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| 215 | /*---------------------------- SPIx CR2 Configuration ------------------------
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| 216 | * Configure SPIx CR2 with parameters:
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| 217 | * - DataWidth: DS[3:0] bits
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| 218 | * - NSS management: SSOE bit
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| 219 | */
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| 220 | MODIFY_REG(SPIx->CR2,
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| 221 | SPI_CR2_DS | SPI_CR2_SSOE,
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| 222 | SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
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| 223 |
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| 224 | /*---------------------------- SPIx CRCPR Configuration ----------------------
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| 225 | * Configure SPIx CRCPR with parameters:
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| 226 | * - CRCPoly: CRCPOLY[15:0] bits
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| 227 | */
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| 228 | if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
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| 229 | {
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| 230 | assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
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| 231 | LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
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| 232 | }
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| 233 | status = SUCCESS;
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| 234 | }
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| 235 |
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| 236 | #if defined (SPI_I2S_SUPPORT)
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| 237 | /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
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| 238 | CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
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| 239 | #endif /* SPI_I2S_SUPPORT */
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| 240 | return status;
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| 241 | }
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| 242 |
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| 243 | /**
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| 244 | * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
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| 245 | * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
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| 246 | * whose fields will be set to default values.
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| 247 | * @retval None
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| 248 | */
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| 249 | void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
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| 250 | {
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| 251 | /* Set SPI_InitStruct fields to default values */
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| 252 | SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
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| 253 | SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
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| 254 | SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
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| 255 | SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
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| 256 | SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
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| 257 | SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
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| 258 | SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
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| 259 | SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
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| 260 | SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
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| 261 | SPI_InitStruct->CRCPoly = 7U;
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| 262 | }
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| 263 |
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| 264 | /**
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| 265 | * @}
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| 266 | */
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| 267 |
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| 268 | /**
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| 269 | * @}
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| 270 | */
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| 271 |
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| 272 | /**
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| 273 | * @}
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| 274 | */
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| 275 |
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| 276 | #if defined(SPI_I2S_SUPPORT)
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| 277 | /** @addtogroup I2S_LL
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| 278 | * @{
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| 279 | */
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| 280 |
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| 281 | /* Private types -------------------------------------------------------------*/
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| 282 | /* Private variables ---------------------------------------------------------*/
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| 283 | /* Private constants ---------------------------------------------------------*/
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| 284 | /** @defgroup I2S_LL_Private_Constants I2S Private Constants
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| 285 | * @{
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| 286 | */
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| 287 | /* I2S registers Masks */
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| 288 | #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
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| 289 | SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
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| 290 | SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
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| 291 |
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| 292 | #define I2S_I2SPR_CLEAR_MASK 0x0002U
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| 293 | /**
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| 294 | * @}
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| 295 | */
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| 296 | /* Private macros ------------------------------------------------------------*/
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| 297 | /** @defgroup I2S_LL_Private_Macros I2S Private Macros
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| 298 | * @{
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| 299 | */
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| 300 |
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| 301 | #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
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| 302 | || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
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| 303 | || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
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| 304 | || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
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| 305 |
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| 306 | #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
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| 307 | || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
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| 308 |
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| 309 | #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
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| 310 | || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
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| 311 | || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
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| 312 | || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
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| 313 | || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
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| 314 |
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| 315 | #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
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| 316 | || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
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| 317 | || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
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| 318 | || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
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| 319 |
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| 320 | #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
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| 321 | || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
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| 322 |
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| 323 | #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
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| 324 | && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
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| 325 | || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
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| 326 |
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| 327 | #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
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| 328 |
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| 329 | #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
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| 330 | || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
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| 331 | /**
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| 332 | * @}
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| 333 | */
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| 334 |
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| 335 | /* Private function prototypes -----------------------------------------------*/
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| 336 |
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| 337 | /* Exported functions --------------------------------------------------------*/
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| 338 | /** @addtogroup I2S_LL_Exported_Functions
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| 339 | * @{
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| 340 | */
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| 341 |
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| 342 | /** @addtogroup I2S_LL_EF_Init
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| 343 | * @{
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| 344 | */
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| 345 |
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| 346 | /**
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| 347 | * @brief De-initialize the SPI/I2S registers to their default reset values.
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| 348 | * @param SPIx SPI Instance
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| 349 | * @retval An ErrorStatus enumeration value:
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| 350 | * - SUCCESS: SPI registers are de-initialized
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| 351 | * - ERROR: SPI registers are not de-initialized
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| 352 | */
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| 353 | ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
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| 354 | {
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| 355 | return LL_SPI_DeInit(SPIx);
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| 356 | }
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| 357 |
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| 358 | /**
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| 359 | * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
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| 360 | * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
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| 361 | * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
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| 362 | * @param SPIx SPI Instance
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| 363 | * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
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| 364 | * @retval An ErrorStatus enumeration value:
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| 365 | * - SUCCESS: SPI registers are Initialized
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| 366 | * - ERROR: SPI registers are not Initialized
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| 367 | */
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| 368 | ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
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| 369 | {
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| 370 | uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
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| 371 | uint32_t tmp;
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| 372 | LL_RCC_ClocksTypeDef rcc_clocks;
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| 373 | uint32_t sourceclock;
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| 374 | ErrorStatus status = ERROR;
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| 375 |
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| 376 | /* Check the I2S parameters */
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| 377 | assert_param(IS_I2S_ALL_INSTANCE(SPIx));
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| 378 | assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
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| 379 | assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
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| 380 | assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
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| 381 | assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
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| 382 | assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
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| 383 | assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
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| 384 |
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| 385 | if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
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| 386 | {
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| 387 | /*---------------------------- SPIx I2SCFGR Configuration --------------------
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| 388 | * Configure SPIx I2SCFGR with parameters:
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| 389 | * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
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| 390 | * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
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| 391 | * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
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| 392 | * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
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| 393 | */
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| 394 |
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| 395 | /* Write to SPIx I2SCFGR */
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| 396 | MODIFY_REG(SPIx->I2SCFGR,
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| 397 | I2S_I2SCFGR_CLEAR_MASK,
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| 398 | I2S_InitStruct->Mode | I2S_InitStruct->Standard |
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| 399 | I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
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| 400 | SPI_I2SCFGR_I2SMOD);
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| 401 |
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| 402 | /*---------------------------- SPIx I2SPR Configuration ----------------------
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| 403 | * Configure SPIx I2SPR with parameters:
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| 404 | * - MCLKOutput: SPI_I2SPR_MCKOE bit
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| 405 | * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
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| 406 | */
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| 407 |
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| 408 | /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
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| 409 | * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
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| 410 | */
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| 411 | if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
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| 412 | {
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| 413 | /* Check the frame length (For the Prescaler computing)
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| 414 | * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
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| 415 | */
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| 416 | if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
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| 417 | {
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| 418 | /* Packet length is 32 bits */
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| 419 | packetlength = 2U;
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| 420 | }
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| 421 |
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| 422 | /* I2S Clock source is System clock: Get System Clock frequency */
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| 423 | LL_RCC_GetSystemClocksFreq(&rcc_clocks);
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| 424 |
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| 425 | /* Get the source clock value: based on System Clock value */
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| 426 | sourceclock = rcc_clocks.SYSCLK_Frequency;
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| 427 |
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| 428 | /* Compute the Real divider depending on the MCLK output state with a floating point */
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| 429 | if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
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| 430 | {
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| 431 | /* MCLK output is enabled */
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| 432 | tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
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| 433 | }
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| 434 | else
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| 435 | {
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| 436 | /* MCLK output is disabled */
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| 437 | tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
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| 438 | }
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| 439 |
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| 440 | /* Remove the floating point */
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| 441 | tmp = tmp / 10U;
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| 442 |
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| 443 | /* Check the parity of the divider */
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| 444 | i2sodd = (tmp & (uint16_t)0x0001U);
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| 445 |
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| 446 | /* Compute the i2sdiv prescaler */
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| 447 | i2sdiv = ((tmp - i2sodd) / 2U);
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| 448 |
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| 449 | /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
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| 450 | i2sodd = (i2sodd << 8U);
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| 451 | }
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| 452 |
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| 453 | /* Test if the divider is 1 or 0 or greater than 0xFF */
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| 454 | if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
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| 455 | {
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| 456 | /* Set the default values */
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| 457 | i2sdiv = 2U;
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| 458 | i2sodd = 0U;
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| 459 | }
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| 460 |
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| 461 | /* Write to SPIx I2SPR register the computed value */
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| 462 | WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
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| 463 |
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| 464 | status = SUCCESS;
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| 465 | }
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| 466 | return status;
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| 467 | }
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| 468 |
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| 469 | /**
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| 470 | * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
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| 471 | * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
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| 472 | * whose fields will be set to default values.
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| 473 | * @retval None
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| 474 | */
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| 475 | void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
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| 476 | {
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| 477 | /*--------------- Reset I2S init structure parameters values -----------------*/
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| 478 | I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
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| 479 | I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
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| 480 | I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
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| 481 | I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
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| 482 | I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
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| 483 | I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
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| 484 | }
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| 485 |
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| 486 | /**
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| 487 | * @brief Set linear and parity prescaler.
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| 488 | * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
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| 489 | * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
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| 490 | * @param SPIx SPI Instance
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| 491 | * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
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| 492 | * @param PrescalerParity This parameter can be one of the following values:
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| 493 | * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
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| 494 | * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
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| 495 | * @retval None
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| 496 | */
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| 497 | void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
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| 498 | {
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| 499 | /* Check the I2S parameters */
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| 500 | assert_param(IS_I2S_ALL_INSTANCE(SPIx));
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|---|
| 501 | assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
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| 502 | assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
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| 503 |
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| 504 | /* Write to SPIx I2SPR */
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| 505 | MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
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| 506 | }
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| 507 |
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| 508 | /**
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| 509 | * @}
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| 510 | */
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|---|
| 511 |
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| 512 | /**
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| 513 | * @}
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| 514 | */
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| 515 |
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| 516 | /**
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| 517 | * @}
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| 518 | */
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| 519 | #endif /* SPI_I2S_SUPPORT */
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| 520 |
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| 521 | #endif /* defined (SPI1) || defined (SPI2) */
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| 522 |
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| 523 | /**
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| 524 | * @}
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| 525 | */
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| 526 |
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| 527 | #endif /* USE_FULL_LL_DRIVER */
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| 528 |
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| 529 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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