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stm32g0xx_ll_adc.c

Last change on this file was 6, checked in by f.jahn, 8 months ago

File size: 34.1 KB

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_ll_adc.c
4	* @author MCD Application Team
5	* @brief ADC LL module driver
6	******************************************************************************
7	* @attention
8	*
9	* Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.
11	*
12	* This software is licensed under terms that can be found in the LICENSE file
13	* in the root directory of this software component.
14	* If no LICENSE file comes with this software, it is provided AS-IS.
15	*
16	******************************************************************************
17	*/
18	#if defined(USE_FULL_LL_DRIVER)
19
20	/* Includes ------------------------------------------------------------------*/
21	#include "stm32g0xx_ll_adc.h"
22	#include "stm32g0xx_ll_bus.h"
23
24	#ifdef USE_FULL_ASSERT
25	#include "stm32_assert.h"
26	#else
27	#define assert_param(expr) ((void)0U)
28	#endif /* USE_FULL_ASSERT */
29
30	/** @addtogroup STM32G0xx_LL_Driver
31	* @{
32	*/
33
34	#if defined (ADC1)
35
36	/** @addtogroup ADC_LL ADC
37	* @{
38	*/
39
40	/* Private types -------------------------------------------------------------*/
41	/* Private variables ---------------------------------------------------------*/
42	/* Private constants ---------------------------------------------------------*/
43	/** @addtogroup ADC_LL_Private_Constants
44	* @{
45	*/
46
47	/* Definitions of ADC hardware constraints delays */
48	/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49	/* not timeout values: */
50	/* Timeout values for ADC operations are dependent to device clock */
51	/* configuration (system clock versus ADC clock), */
52	/* and therefore must be defined in user application. */
53	/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54	/* values definition. */
55	/* Note: ADC timeout values are defined here in CPU cycles to be independent */
56	/* of device clock setting. */
57	/* In user application, ADC timeout values should be defined with */
58	/* temporal values, in function of device clock settings. */
59	/* Highest ratio CPU clock frequency vs ADC clock frequency: */
60	/* - ADC clock from synchronous clock with AHB prescaler 512, */
61	/* APB prescaler 16, ADC prescaler 4. */
62	/* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
63	/* with highest ratio CPU clock frequency vs HSI clock frequency: */
64	/* CPU clock frequency max 56MHz, HSI frequency 16MHz: ratio 4. */
65	/* Unit: CPU cycles. */
66	#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67	#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68	#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69	/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
70	/* after the channel configuration has been changed. */
71	/* Driver timeout is approximated to 6 CPU cycles. */
72	#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
73
74	/**
75	* @}
76	*/
77
78	/* Private macros ------------------------------------------------------------*/
79
80	/** @addtogroup ADC_LL_Private_Macros
81	* @{
82	*/
83
84	/* Check of parameters for configuration of ADC hierarchical scope: */
85	/* common to several ADC instances. */
86	#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
87	(((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
88	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
89	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
90	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
91	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
92	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
93	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
94	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
95	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
96	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
97	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
98	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
99	)
100
101	#define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
102	(((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
103	\|\| ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
104	)
105
106	/* Check of parameters for configuration of ADC hierarchical scope: */
107	/* ADC instance. */
108	#define IS_LL_ADC_CLOCK(__CLOCK__) \
109	(((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
110	\|\| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
111	\|\| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
112	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
113	)
114
115	#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
116	(((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
117	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
118	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
119	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
120	)
121
122	#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
123	(((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
124	\|\| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
125	)
126
127	#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
128	(((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
129	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
130	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
131	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
132	)
133
134	/* Check of parameters for configuration of ADC hierarchical scope: */
135	/* ADC group regular */
136	#if defined(TIM15) && defined(TIM6) && defined(TIM2)
137	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
138	(((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
139	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
140	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
141	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
142	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
143	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
144	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
145	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
146	)
147	#elif defined(TIM15) && defined(TIM6)
148	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
149	(((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
150	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
151	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
152	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
153	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
154	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
155	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
156	)
157	#elif defined(TIM2)
158	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
159	(((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
160	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
161	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
162	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
163	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
164	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
165	)
166	#else
167	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
168	(((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
169	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
170	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
171	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
172	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
173	)
174	#endif /* TIM15 && TIM6 && TIM2 */
175
176	#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
177	(((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
178	\|\| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
179	)
180
181	#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
182	(((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
183	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
184	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
185	)
186
187	#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
188	(((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
189	\|\| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
190	)
191
192	#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
193	(((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
194	\|\| ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
195	)
196
197	#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
198	(((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
199	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
200	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
201	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
202	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
203	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
204	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
205	\|\| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
206	)
207
208	#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
209	(((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
210	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
211	)
212
213	/**
214	* @}
215	*/
216
217
218	/* Private function prototypes -----------------------------------------------*/
219
220	/* Exported functions --------------------------------------------------------*/
221	/** @addtogroup ADC_LL_Exported_Functions
222	* @{
223	*/
224
225	/** @addtogroup ADC_LL_EF_Init
226	* @{
227	*/
228
229	/**
230	* @brief De-initialize registers of all ADC instances belonging to
231	* the same ADC common instance to their default reset values.
232	* @note This function is performing a hard reset, using high level
233	* clock source RCC ADC reset.
234	* @param ADCxy_COMMON ADC common instance
235	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
236	* @retval An ErrorStatus enumeration value:
237	* - SUCCESS: ADC common registers are de-initialized
238	* - ERROR: not applicable
239	*/
240	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
241	{
242	/* Check the parameters */
243	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
244
245	/* Prevent unused argument(s) compilation warning if no assert_param check */
246	(void)(ADCxy_COMMON);
247
248	/* Force reset of ADC clock (core clock) */
249	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
250
251	/* Release reset of ADC clock (core clock) */
252	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
253
254	return SUCCESS;
255	}
256
257	/**
258	* @brief Initialize some features of ADC common parameters
259	* (all ADC instances belonging to the same ADC common instance)
260	* and multimode (for devices with several ADC instances available).
261	* @note The setting of ADC common parameters is conditioned to
262	* ADC instances state:
263	* All ADC instances belonging to the same ADC common instance
264	* must be disabled.
265	* @param ADCxy_COMMON ADC common instance
266	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
267	* @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
268	* @retval An ErrorStatus enumeration value:
269	* - SUCCESS: ADC common registers are initialized
270	* - ERROR: ADC common registers are not initialized
271	*/
272	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, const LL_ADC_CommonInitTypeDef pADC_CommonInitStruct)
273	{
274	ErrorStatus status = SUCCESS;
275
276	/* Check the parameters */
277	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
278	assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
279
280	/* Note: Hardware constraint (refer to description of functions */
281	/* "LL_ADC_SetCommonXXX()": */
282	/* On this STM32 series, setting of these features is conditioned to */
283	/* ADC state: */
284	/* All ADC instances of the ADC common group must be disabled. */
285	if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
286	{
287	/* Configuration of ADC hierarchical scope: */
288	/* - common to several ADC */
289	/* (all ADC instances belonging to the same ADC common instance) */
290	/* - Set ADC clock (conversion clock) */
291	LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
292	}
293	else
294	{
295	/* Initialization error: One or several ADC instances belonging to */
296	/* the same ADC common instance are not disabled. */
297	status = ERROR;
298	}
299
300	return status;
301	}
302
303	/**
304	* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
305	* @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
306	* whose fields will be set to default values.
307	* @retval None
308	*/
309	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
310	{
311	/* Set pADC_CommonInitStruct fields to default values */
312	/* Set fields of ADC common */
313	/* (all ADC instances belonging to the same ADC common instance) */
314	pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
315
316	}
317
318	/**
319	* @brief De-initialize registers of the selected ADC instance
320	* to their default reset values.
321	* @note To reset all ADC instances quickly (perform a hard reset),
322	* use function @ref LL_ADC_CommonDeInit().
323	* @note If this functions returns error status, it means that ADC instance
324	* is in an unknown state.
325	* In this case, perform a hard reset using high level
326	* clock source RCC ADC reset.
327	* Refer to function @ref LL_ADC_CommonDeInit().
328	* @param ADCx ADC instance
329	* @retval An ErrorStatus enumeration value:
330	* - SUCCESS: ADC registers are de-initialized
331	* - ERROR: ADC registers are not de-initialized
332	*/
333	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
334	{
335	ErrorStatus status = SUCCESS;
336
337	__IO uint32_t timeout_cpu_cycles = 0UL;
338
339	/* Check the parameters */
340	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
341
342	/* Disable ADC instance if not already disabled. */
343	if (LL_ADC_IsEnabled(ADCx) == 1UL)
344	{
345	/* Stop potential ADC conversion on going on ADC group regular. */
346	LL_ADC_REG_StopConversion(ADCx);
347
348	/* Wait for ADC conversions are effectively stopped */
349	timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
350	while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
351	{
352	timeout_cpu_cycles--;
353	if (timeout_cpu_cycles == 0UL)
354	{
355	/* Time-out error */
356	status = ERROR;
357	break;
358	}
359	}
360
361	/* Disable the ADC instance */
362	LL_ADC_Disable(ADCx);
363
364	/* Wait for ADC instance is effectively disabled */
365	timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
366	while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
367	{
368	timeout_cpu_cycles--;
369	if (timeout_cpu_cycles == 0UL)
370	{
371	/* Time-out error */
372	status = ERROR;
373	break;
374	}
375	}
376	}
377
378	/* Check whether ADC state is compliant with expected state */
379	if (READ_BIT(ADCx->CR,
380	(ADC_CR_ADSTP \| ADC_CR_ADSTART
381	\| ADC_CR_ADDIS \| ADC_CR_ADEN)
382	)
383	== 0UL)
384	{
385	/* ========== Reset ADC registers ========== */
386	/* Reset register IER */
387	CLEAR_BIT(ADCx->IER,
388	(LL_ADC_IT_ADRDY
389	\| LL_ADC_IT_EOC
390	\| LL_ADC_IT_EOS
391	\| LL_ADC_IT_OVR
392	\| LL_ADC_IT_EOSMP
393	\| LL_ADC_IT_AWD1
394	\| LL_ADC_IT_AWD2
395	\| LL_ADC_IT_AWD3
396	\| LL_ADC_IT_EOCAL
397	\| LL_ADC_IT_CCRDY
398	)
399	);
400
401	/* Reset register ISR */
402	SET_BIT(ADCx->ISR,
403	(LL_ADC_FLAG_ADRDY
404	\| LL_ADC_FLAG_EOC
405	\| LL_ADC_FLAG_EOS
406	\| LL_ADC_FLAG_OVR
407	\| LL_ADC_FLAG_EOSMP
408	\| LL_ADC_FLAG_AWD1
409	\| LL_ADC_FLAG_AWD2
410	\| LL_ADC_FLAG_AWD3
411	\| LL_ADC_FLAG_EOCAL
412	\| LL_ADC_FLAG_CCRDY
413	)
414	);
415
416	/* Reset register CR */
417	/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
418	/* "read-set": no direct reset applicable. */
419	CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
420
421	/* Reset register CFGR1 */
422	CLEAR_BIT(ADCx->CFGR1,
423	(ADC_CFGR1_AWD1CH \| ADC_CFGR1_AWD1EN \| ADC_CFGR1_AWD1SGL \| ADC_CFGR1_DISCEN
424	\| ADC_CFGR1_CHSELRMOD \| ADC_CFGR1_AUTOFF \| ADC_CFGR1_WAIT \| ADC_CFGR1_CONT \| ADC_CFGR1_OVRMOD
425	\| ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL \| ADC_CFGR1_ALIGN \| ADC_CFGR1_RES
426	\| ADC_CFGR1_SCANDIR \| ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN)
427	);
428
429	/* Reset register SMPR */
430	CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 \| ADC_SMPR_SMP2 \| ADC_SMPR_SMPSEL);
431
432	/* Reset register CHSELR */
433	CLEAR_BIT(ADCx->CHSELR,
434	(ADC_CHSELR_CHSEL18 \| ADC_CHSELR_CHSEL17 \| ADC_CHSELR_CHSEL16
435	\| ADC_CHSELR_CHSEL15 \| ADC_CHSELR_CHSEL14 \| ADC_CHSELR_CHSEL13 \| ADC_CHSELR_CHSEL12
436	\| ADC_CHSELR_CHSEL11 \| ADC_CHSELR_CHSEL10 \| ADC_CHSELR_CHSEL9 \| ADC_CHSELR_CHSEL8
437	\| ADC_CHSELR_CHSEL7 \| ADC_CHSELR_CHSEL6 \| ADC_CHSELR_CHSEL5 \| ADC_CHSELR_CHSEL4
438	\| ADC_CHSELR_CHSEL3 \| ADC_CHSELR_CHSEL2 \| ADC_CHSELR_CHSEL1 \| ADC_CHSELR_CHSEL0)
439	);
440
441	/* Reset register AWD1TR */
442	MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 \| ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
443
444	/* Reset register AWD2TR */
445	MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 \| ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
446
447	/* Reset register AWD3TR */
448	MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 \| ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
449
450	/* Wait for ADC channel configuration ready */
451	timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
452	while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
453	{
454	timeout_cpu_cycles--;
455	if (timeout_cpu_cycles == 0UL)
456	{
457	/* Time-out error */
458	status = ERROR;
459	break;
460	}
461	}
462
463	/* Clear flag ADC channel configuration ready */
464	LL_ADC_ClearFlag_CCRDY(ADCx);
465
466	/* Reset register DR */
467	/* bits in access mode read only, no direct reset applicable */
468
469	/* Reset register CALFACT */
470	CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
471
472	/* Reset register CFGR2 */
473	/* Note: CFGR2 reset done at the end of de-initialization due to */
474	/* clock source reset */
475	/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
476	/* already done above. */
477	CLEAR_BIT(ADCx->CFGR2,
478	(ADC_CFGR2_CKMODE
479	\| ADC_CFGR2_TOVS \| ADC_CFGR2_OVSS \| ADC_CFGR2_OVSR
480	\| ADC_CFGR2_OVSE)
481	);
482
483	}
484	else
485	{
486	/* ADC instance is in an unknown state */
487	/* Need to performing a hard reset of ADC instance, using high level */
488	/* clock source RCC ADC reset. */
489	/* Caution: On this STM32 series, if several ADC instances are available */
490	/* on the selected device, RCC ADC reset will reset */
491	/* all ADC instances belonging to the common ADC instance. */
492	status = ERROR;
493	}
494
495	return status;
496	}
497
498	/**
499	* @brief Initialize some features of ADC instance.
500	* @note These parameters have an impact on ADC scope: ADC instance.
501	* Refer to corresponding unitary functions into
502	* @ref ADC_LL_EF_Configuration_ADC_Instance .
503	* @note The setting of these parameters by function @ref LL_ADC_Init()
504	* is conditioned to ADC state:
505	* ADC instance must be disabled.
506	* This condition is applied to all ADC features, for efficiency
507	* and compatibility over all STM32 series. However, the different
508	* features can be set under different ADC state conditions
509	* (setting possible with ADC enabled without conversion on going,
510	* ADC enabled with conversion on going, ...)
511	* Each feature can be updated afterwards with a unitary function
512	* and potentially with ADC in a different state than disabled,
513	* refer to description of each function for setting
514	* conditioned to ADC state.
515	* @note After using this function, some other features must be configured
516	* using LL unitary functions.
517	* The minimum configuration remaining to be done is:
518	* - Set ADC group regular sequencer:
519	* Depending on the sequencer mode (refer to
520	* function @ref LL_ADC_REG_SetSequencerConfigurable() ):
521	* - map channel on the selected sequencer rank.
522	* Refer to function @ref LL_ADC_REG_SetSequencerRanks();
523	* - map channel on rank corresponding to channel number.
524	* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
525	* - Set ADC channel sampling time
526	* Refer to function LL_ADC_SetSamplingTimeCommonChannels();
527	* Refer to function LL_ADC_SetChannelSamplingTime();
528	* @param ADCx ADC instance
529	* @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
530	* @retval An ErrorStatus enumeration value:
531	* - SUCCESS: ADC registers are initialized
532	* - ERROR: ADC registers are not initialized
533	*/
534	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, const LL_ADC_InitTypeDef pADC_InitStruct)
535	{
536	ErrorStatus status = SUCCESS;
537
538	/* Check the parameters */
539	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
540
541	assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock));
542	assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
543	assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
544	assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
545
546	/* Note: Hardware constraint (refer to description of this function): */
547	/* ADC instance must be disabled. */
548	if (LL_ADC_IsEnabled(ADCx) == 0UL)
549	{
550	/* Configuration of ADC hierarchical scope: */
551	/* - ADC instance */
552	/* - Set ADC data resolution */
553	/* - Set ADC conversion data alignment */
554	/* - Set ADC low power mode */
555	MODIFY_REG(ADCx->CFGR1,
556	ADC_CFGR1_RES
557	\| ADC_CFGR1_ALIGN
558	\| ADC_CFGR1_WAIT
559	\| ADC_CFGR1_AUTOFF
560	,
561	pADC_InitStruct->Resolution
562	\| pADC_InitStruct->DataAlignment
563	\| pADC_InitStruct->LowPowerMode
564	);
565
566	MODIFY_REG(ADCx->CFGR2,
567	ADC_CFGR2_CKMODE
568	,
569	pADC_InitStruct->Clock
570	);
571	}
572	else
573	{
574	/* Initialization error: ADC instance is not disabled. */
575	status = ERROR;
576	}
577
578	return status;
579	}
580
581	/**
582	* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
583	* @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
584	* whose fields will be set to default values.
585	* @retval None
586	*/
587	void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
588	{
589	/* Set pADC_InitStruct fields to default values */
590	/* Set fields of ADC instance */
591	pADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
592	pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
593	pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
594	pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
595
596	}
597
598	/**
599	* @brief Initialize some features of ADC group regular.
600	* @note These parameters have an impact on ADC scope: ADC group regular.
601	* Refer to corresponding unitary functions into
602	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
603	* (functions with prefix "REG").
604	* @note The setting of these parameters by function @ref LL_ADC_Init()
605	* is conditioned to ADC state:
606	* ADC instance must be disabled.
607	* This condition is applied to all ADC features, for efficiency
608	* and compatibility over all STM32 series. However, the different
609	* features can be set under different ADC state conditions
610	* (setting possible with ADC enabled without conversion on going,
611	* ADC enabled with conversion on going, ...)
612	* Each feature can be updated afterwards with a unitary function
613	* and potentially with ADC in a different state than disabled,
614	* refer to description of each function for setting
615	* conditioned to ADC state.
616	* @note Before using this function, ADC group regular sequencer
617	* must be configured: refer to function
618	* @ref LL_ADC_REG_SetSequencerConfigurable().
619	* @note After using this function, other features must be configured
620	* using LL unitary functions.
621	* The minimum configuration remaining to be done is:
622	* - Set ADC group regular sequencer:
623	* Depending on the sequencer mode (refer to
624	* function @ref LL_ADC_REG_SetSequencerConfigurable() ):
625	* - map channel on the selected sequencer rank.
626	* Refer to function @ref LL_ADC_REG_SetSequencerRanks();
627	* - map channel on rank corresponding to channel number.
628	* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
629	* - Set ADC channel sampling time
630	* Refer to function LL_ADC_SetSamplingTimeCommonChannels();
631	* Refer to function LL_ADC_SetChannelSamplingTime();
632	* @param ADCx ADC instance
633	* @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
634	* @retval An ErrorStatus enumeration value:
635	* - SUCCESS: ADC registers are initialized
636	* - ERROR: ADC registers are not initialized
637	*/
638	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, const LL_ADC_REG_InitTypeDef pADC_RegInitStruct)
639	{
640	ErrorStatus status = SUCCESS;
641
642	/* Check the parameters */
643	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
644	assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
645	assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
646	assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
647	assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
648
649	if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
650	{
651	assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
652	}
653
654	if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
655	\|\| (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
656	)
657	{
658	assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
659
660	/* ADC group regular continuous mode and discontinuous mode */
661	/* can not be enabled simultenaeously */
662	assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
663	\|\| (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
664	}
665
666	/* Note: Hardware constraint (refer to description of this function): */
667	/* ADC instance must be disabled. */
668	if (LL_ADC_IsEnabled(ADCx) == 0UL)
669	{
670	/* Configuration of ADC hierarchical scope: */
671	/* - ADC group regular */
672	/* - Set ADC group regular trigger source */
673	/* - Set ADC group regular sequencer length */
674	/* - Set ADC group regular sequencer discontinuous mode */
675	/* - Set ADC group regular continuous mode */
676	/* - Set ADC group regular conversion data transfer: no transfer or */
677	/* transfer by DMA, and DMA requests mode */
678	/* - Set ADC group regular overrun behavior */
679	/* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
680	/* setting of trigger source to SW start. */
681	if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
682	\|\| (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
683	)
684	{
685	/* Case of sequencer mode fixed
686	or sequencer length >= 2 ranks with sequencer mode fully configurable:
687	discontinuous mode configured */
688	MODIFY_REG(ADCx->CFGR1,
689	ADC_CFGR1_EXTSEL
690	\| ADC_CFGR1_EXTEN
691	\| ADC_CFGR1_DISCEN
692	\| ADC_CFGR1_CONT
693	\| ADC_CFGR1_DMAEN
694	\| ADC_CFGR1_DMACFG
695	\| ADC_CFGR1_OVRMOD
696	,
697	pADC_RegInitStruct->TriggerSource
698	\| pADC_RegInitStruct->SequencerDiscont
699	\| pADC_RegInitStruct->ContinuousMode
700	\| pADC_RegInitStruct->DMATransfer
701	\| pADC_RegInitStruct->Overrun
702	);
703	}
704	else
705	{
706	/* Case of sequencer mode fully configurable
707	and sequencer length 1 rank (sequencer disabled):
708	discontinuous mode discarded (fixed to disable) */
709	MODIFY_REG(ADCx->CFGR1,
710	ADC_CFGR1_EXTSEL
711	\| ADC_CFGR1_EXTEN
712	\| ADC_CFGR1_DISCEN
713	\| ADC_CFGR1_CONT
714	\| ADC_CFGR1_DMAEN
715	\| ADC_CFGR1_DMACFG
716	\| ADC_CFGR1_OVRMOD
717	,
718	pADC_RegInitStruct->TriggerSource
719	\| LL_ADC_REG_SEQ_DISCONT_DISABLE
720	\| pADC_RegInitStruct->ContinuousMode
721	\| pADC_RegInitStruct->DMATransfer
722	\| pADC_RegInitStruct->Overrun
723	);
724	}
725
726	/* Set ADC group regular sequencer length */
727	if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
728	{
729	LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
730	}
731	}
732	else
733	{
734	/* Initialization error: ADC instance is not disabled. */
735	status = ERROR;
736	}
737	return status;
738	}
739
740	/**
741	* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
742	* @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
743	* whose fields will be set to default values.
744	* @retval None
745	*/
746	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
747	{
748	/* Set pADC_RegInitStruct fields to default values */
749	/* Set fields of ADC group regular */
750	/* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
751	/* setting of trigger source to SW start. */
752	pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
753	pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
754	pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
755	pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
756	pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
757	pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
758	}
759
760	/**
761	* @}
762	*/
763
764	/**
765	* @}
766	*/
767
768	/**
769	* @}
770	*/
771
772	#endif /* ADC1 */
773
774	/**
775	* @}
776	*/
777
778	#endif /* USE_FULL_LL_DRIVER */

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c

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