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stm32g0xx_ll_tim.h

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_ll_tim.h
4	* @author MCD Application Team
5	* @brief Header file of TIM LL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef __STM32G0xx_LL_TIM_H
22	#define __STM32G0xx_LL_TIM_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32g0xx.h"
30
31	/** @addtogroup STM32G0xx_LL_Driver
32	* @{
33	*/
34
35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
36
37	/** @defgroup TIM_LL TIM
38	* @{
39	*/
40
41	/* Private types -------------------------------------------------------------*/
42	/* Private variables ---------------------------------------------------------*/
43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
44	* @{
45	*/
46	static const uint8_t OFFSET_TAB_CCMRx[] =
47	{
48	0x00U, /* 0: TIMx_CH1 */
49	0x00U, /* 1: TIMx_CH1N */
50	0x00U, /* 2: TIMx_CH2 */
51	0x00U, /* 3: TIMx_CH2N */
52	0x04U, /* 4: TIMx_CH3 */
53	0x04U, /* 5: TIMx_CH3N */
54	0x04U, /* 6: TIMx_CH4 */
55	0x3CU, /* 7: TIMx_CH5 */
56	0x3CU /* 8: TIMx_CH6 */
57	};
58
59	static const uint8_t SHIFT_TAB_OCxx[] =
60	{
61	0U, /* 0: OC1M, OC1FE, OC1PE */
62	0U, /* 1: - NA */
63	8U, /* 2: OC2M, OC2FE, OC2PE */
64	0U, /* 3: - NA */
65	0U, /* 4: OC3M, OC3FE, OC3PE */
66	0U, /* 5: - NA */
67	8U, /* 6: OC4M, OC4FE, OC4PE */
68	0U, /* 7: OC5M, OC5FE, OC5PE */
69	8U /* 8: OC6M, OC6FE, OC6PE */
70	};
71
72	static const uint8_t SHIFT_TAB_ICxx[] =
73	{
74	0U, /* 0: CC1S, IC1PSC, IC1F */
75	0U, /* 1: - NA */
76	8U, /* 2: CC2S, IC2PSC, IC2F */
77	0U, /* 3: - NA */
78	0U, /* 4: CC3S, IC3PSC, IC3F */
79	0U, /* 5: - NA */
80	8U, /* 6: CC4S, IC4PSC, IC4F */
81	0U, /* 7: - NA */
82	0U /* 8: - NA */
83	};
84
85	static const uint8_t SHIFT_TAB_CCxP[] =
86	{
87	0U, /* 0: CC1P */
88	2U, /* 1: CC1NP */
89	4U, /* 2: CC2P */
90	6U, /* 3: CC2NP */
91	8U, /* 4: CC3P */
92	10U, /* 5: CC3NP */
93	12U, /* 6: CC4P */
94	16U, /* 7: CC5P */
95	20U /* 8: CC6P */
96	};
97
98	static const uint8_t SHIFT_TAB_OISx[] =
99	{
100	0U, /* 0: OIS1 */
101	1U, /* 1: OIS1N */
102	2U, /* 2: OIS2 */
103	3U, /* 3: OIS2N */
104	4U, /* 4: OIS3 */
105	5U, /* 5: OIS3N */
106	6U, /* 6: OIS4 */
107	8U, /* 7: OIS5 */
108	10U /* 8: OIS6 */
109	};
110	/**
111	* @}
112	*/
113
114	/* Private constants ---------------------------------------------------------*/
115	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
116	* @{
117	*/
118
119	/* Defines used for the bit position in the register and perform offsets */
120	#define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FU)
121
122	/* Generic bit definitions for TIMx_AF1 register */
123	#define TIMx_AF1_BKINE TIM1_AF1_BKINE /!< BRK BKIN input enable /
124	#if defined(COMP1) && defined(COMP2)
125	#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /!< BRK COMP1 enable /
126	#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /!< BRK COMP2 enable /
127	#endif /* COMP1 && COMP2 */
128	#define TIMx_AF1_BKINP TIM1_AF1_BKINP /!< BRK BKIN input polarity /
129	#if defined(COMP1) && defined(COMP2)
130	#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /!< BRK COMP1 input polarity /
131	#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /!< BRK COMP2 input polarity /
132	#endif /* COMP1 && COMP2 */
133	#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /!< TIMx ETR source selection /
134
135	/* Generic bit definitions for TIMx_AF2 register */
136	#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /!< BRK2 BKIN2 input enable /
137	#if defined(COMP1) && defined(COMP2)
138	#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /!< BRK2 COMP1 enable /
139	#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /!< BRK2 COMP2 enable /
140	#endif /* COMP1 && COMP2 */
141	#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /!< BRK2 BKIN2 input polarity /
142	#if defined(COMP1) && defined(COMP2)
143	#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /!< BRK2 COMP1 input polarity /
144	#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /!< BRK2 COMP2 input polarity /
145
146	#endif /* COMP1 && COMP2 */
147
148
149	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
150	#define DT_DELAY_1 ((uint8_t)0x7F)
151	#define DT_DELAY_2 ((uint8_t)0x3F)
152	#define DT_DELAY_3 ((uint8_t)0x1F)
153	#define DT_DELAY_4 ((uint8_t)0x1F)
154
155	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
156	#define DT_RANGE_1 ((uint8_t)0x00)
157	#define DT_RANGE_2 ((uint8_t)0x80)
158	#define DT_RANGE_3 ((uint8_t)0xC0)
159	#define DT_RANGE_4 ((uint8_t)0xE0)
160
161	/** Legacy definitions for compatibility purpose
162	@cond 0
163	*/
164	/**
165	@endcond
166	*/
167
168	#define OCREF_CLEAR_SELECT_Pos (16U)
169	#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /!< 0x00010000 /
170	/**
171	* @}
172	*/
173
174	/* Private macros ------------------------------------------------------------*/
175	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
176	* @{
177	*/
178	/** @brief Convert channel id into channel index.
179	* @param __CHANNEL__ This parameter can be one of the following values:
180	* @arg @ref LL_TIM_CHANNEL_CH1
181	* @arg @ref LL_TIM_CHANNEL_CH1N
182	* @arg @ref LL_TIM_CHANNEL_CH2
183	* @arg @ref LL_TIM_CHANNEL_CH2N
184	* @arg @ref LL_TIM_CHANNEL_CH3
185	* @arg @ref LL_TIM_CHANNEL_CH3N
186	* @arg @ref LL_TIM_CHANNEL_CH4
187	* @arg @ref LL_TIM_CHANNEL_CH5
188	* @arg @ref LL_TIM_CHANNEL_CH6
189	* @retval none
190	*/
191	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
192	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
193	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
194	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
195	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
196	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
197	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
198	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
199	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
200
201	/** @brief Calculate the deadtime sampling period(in ps).
202	* @param __TIMCLK__ timer input clock frequency (in Hz).
203	* @param __CKD__ This parameter can be one of the following values:
204	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
205	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
206	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
207	* @retval none
208	*/
209	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
210	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
211	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
212	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
213	/**
214	* @}
215	*/
216
217
218	/* Exported types ------------------------------------------------------------*/
219	#if defined(USE_FULL_LL_DRIVER)
220	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
221	* @{
222	*/
223
224	/**
225	* @brief TIM Time Base configuration structure definition.
226	*/
227	typedef struct
228	{
229	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
230	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
231
232	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
233
234	uint32_t CounterMode; /*!< Specifies the counter mode.
235	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
236
237	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
238
239	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
240	Auto-Reload Register at the next update event.
241	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
242	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
243
244	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
245
246	uint32_t ClockDivision; /*!< Specifies the clock division.
247	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
248
249	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
250
251	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
252	reaches zero, an update event is generated and counting restarts
253	from the RCR value (N).
254	This means in PWM mode that (N+1) corresponds to:
255	- the number of PWM periods in edge-aligned mode
256	- the number of half PWM period in center-aligned mode
257	This parameter must be a number between 0x00 and 0xFF.
258
259	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
260	} LL_TIM_InitTypeDef;
261
262	/**
263	* @brief TIM Output Compare configuration structure definition.
264	*/
265	typedef struct
266	{
267	uint32_t OCMode; /*!< Specifies the output mode.
268	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
269
270	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
271
272	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
273	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
274
275	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
276
277	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
278	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
279
280	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
281
282	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
283	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
284
285	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
286
287	uint32_t OCPolarity; /*!< Specifies the output polarity.
288	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
289
290	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
291
292	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
293	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
294
295	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
296
297
298	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
299	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
300
301	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
302
303	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
304	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
305
306	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
307	} LL_TIM_OC_InitTypeDef;
308
309	/**
310	* @brief TIM Input Capture configuration structure definition.
311	*/
312
313	typedef struct
314	{
315
316	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
317	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
318
319	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
320
321	uint32_t ICActiveInput; /*!< Specifies the input.
322	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
323
324	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
325
326	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
327	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
328
329	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
330
331	uint32_t ICFilter; /*!< Specifies the input capture filter.
332	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
333
334	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
335	} LL_TIM_IC_InitTypeDef;
336
337
338	/**
339	* @brief TIM Encoder interface configuration structure definition.
340	*/
341	typedef struct
342	{
343	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
344	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
345
346	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
347
348	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
349	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
350
351	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
352
353	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
354	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
355
356	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
357
358	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
359	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
360
361	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
362
363	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
364	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
365
366	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
367
368	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
369	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
370
371	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
372
373	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
374	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
375
376	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
377
378	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
379	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
380
381	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
382
383	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
384	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
385
386	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
387
388	} LL_TIM_ENCODER_InitTypeDef;
389
390	/**
391	* @brief TIM Hall sensor interface configuration structure definition.
392	*/
393	typedef struct
394	{
395
396	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
397	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
398
399	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
400
401	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
402	Prescaler must be set to get a maximum counter period longer than the
403	time interval between 2 consecutive changes on the Hall inputs.
404	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
405
406	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
407
408	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
409	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
410
411	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
412
413	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
414	A positive pulse (TRGO event) is generated with a programmable delay every time
415	a change occurs on the Hall inputs.
416	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
417
418	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
419	} LL_TIM_HALLSENSOR_InitTypeDef;
420
421	/**
422	* @brief BDTR (Break and Dead Time) structure definition
423	*/
424	typedef struct
425	{
426	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
427	This parameter can be a value of @ref TIM_LL_EC_OSSR
428
429	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
430
431	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
432
433	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
434	This parameter can be a value of @ref TIM_LL_EC_OSSI
435
436	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
437
438	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
439
440	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
441	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
442
443	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
444	has been written, their content is frozen until the next reset.*/
445
446	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
447	switching-on of the outputs.
448	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
449
450	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
451
452	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
453
454	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
455	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
456
457	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
458
459	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
460
461	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
462	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
463
464	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
465
466	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
467
468	uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
469	This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
470
471	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
472
473	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
474
475	uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
476	This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
477
478	This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK()
479
480	@note Bidirectional break input is only supported by advanced timers instances.
481
482	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
483
484	uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
485	This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
486
487	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
488
489	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
490
491	uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
492	This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
493
494	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
495
496	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
497
498	uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
499	This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
500
501	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
502
503	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
504
505	uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
506	This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
507
508	This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK2()
509
510	@note Bidirectional break input is only supported by advanced timers instances.
511
512	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
513
514	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
515	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
516
517	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
518
519	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
520	} LL_TIM_BDTR_InitTypeDef;
521
522	/**
523	* @}
524	*/
525	#endif /* USE_FULL_LL_DRIVER */
526
527	/* Exported constants --------------------------------------------------------*/
528	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
529	* @{
530	*/
531
532	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
533	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
534	* @{
535	*/
536	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
537	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
538	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
539	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
540	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
541	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
542	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
543	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
544	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
545	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
546	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
547	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
548	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
549	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
550	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
551	#define LL_TIM_SR_SBIF TIM_SR_SBIF /!< System Break interrupt flag /
552	/**
553	* @}
554	*/
555
556	#if defined(USE_FULL_LL_DRIVER)
557	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
558	* @{
559	*/
560	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
561	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
562	/**
563	* @}
564	*/
565
566	/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
567	* @{
568	*/
569	#define LL_TIM_BREAK2_DISABLE 0x00000000U /!< Break2 function disabled /
570	#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break2 function enabled /
571	/**
572	* @}
573	*/
574
575	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
576	* @{
577	*/
578	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
579	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
580	/**
581	* @}
582	*/
583	#endif /* USE_FULL_LL_DRIVER */
584
585	/** @defgroup TIM_LL_EC_IT IT Defines
586	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
587	* @{
588	*/
589	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
590	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
591	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
592	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
593	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
594	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
595	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
596	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
597	/**
598	* @}
599	*/
600
601	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
602	* @{
603	*/
604	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
605	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
606	/**
607	* @}
608	*/
609
610	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
611	* @{
612	*/
613	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
614	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
615	/**
616	* @}
617	*/
618
619	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
620	* @{
621	*/
622	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
623	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
624	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
625	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
626	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
627	/**
628	* @}
629	*/
630
631	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
632	* @{
633	*/
634	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
635	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
636	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
637	/**
638	* @}
639	*/
640
641	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
642	* @{
643	*/
644	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
645	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
646	/**
647	* @}
648	*/
649
650	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
651	* @{
652	*/
653	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
654	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
655	/**
656	* @}
657	*/
658
659	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
660	* @{
661	*/
662	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
663	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
664	/**
665	* @}
666	*/
667
668	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
669	* @{
670	*/
671	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
672	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
673	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
674	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
675	/**
676	* @}
677	*/
678
679	/** @defgroup TIM_LL_EC_CHANNEL Channel
680	* @{
681	*/
682	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
683	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
684	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
685	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
686	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
687	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
688	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
689	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
690	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
691	/**
692	* @}
693	*/
694
695	#if defined(USE_FULL_LL_DRIVER)
696	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
697	* @{
698	*/
699	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
700	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
701	/**
702	* @}
703	*/
704	#endif /* USE_FULL_LL_DRIVER */
705
706	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
707	* @{
708	*/
709	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
710	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
711	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
712	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
713	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
714	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
715	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
716	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
717	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
718	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
719	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
720	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
721	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
722	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
723	/**
724	* @}
725	*/
726
727	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
728	* @{
729	*/
730	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
731	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
732	/**
733	* @}
734	*/
735
736	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
737	* @{
738	*/
739	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
740	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
741	/**
742	* @}
743	*/
744
745	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
746	* @{
747	*/
748	#define LL_TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
749	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
750	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
751	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
752	/**
753	* @}
754	*/
755
756	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
757	* @{
758	*/
759	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
760	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
761	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
762	/**
763	* @}
764	*/
765
766	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
767	* @{
768	*/
769	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
770	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
771	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
772	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
773	/**
774	* @}
775	*/
776
777	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
778	* @{
779	*/
780	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
781	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
782	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
783	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
784	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
785	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
786	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
787	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
788	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
789	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
790	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
791	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
792	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
793	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
794	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
795	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
796	/**
797	* @}
798	*/
799
800	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
801	* @{
802	*/
803	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
804	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
805	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
806	/**
807	* @}
808	*/
809
810	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
811	* @{
812	*/
813	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
814	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
815	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
816	/**
817	* @}
818	*/
819
820	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
821	* @{
822	*/
823	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
824	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
825	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
826	/**
827	* @}
828	*/
829
830	/** @defgroup TIM_LL_EC_TRGO Trigger Output
831	* @{
832	*/
833	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
834	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
835	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
836	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
837	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
838	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
839	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
840	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
841	/**
842	* @}
843	*/
844
845	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
846	* @{
847	*/
848	#define LL_TIM_TRGO2_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
849	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
850	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
851	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
852	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
853	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
854	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
855	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
856	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
857	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
858	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
859	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
860	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
861	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
862	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
863	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
864	/**
865	* @}
866	*/
867
868	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
869	* @{
870	*/
871	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
872	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
873	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
874	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
875	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
876	/**
877	* @}
878	*/
879
880	/** @defgroup TIM_LL_EC_TS Trigger Selection
881	* @{
882	*/
883	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
884	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
885	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
886	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
887	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
888	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
889	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
890	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
891	/**
892	* @}
893	*/
894
895	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
896	* @{
897	*/
898	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
899	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
900	/**
901	* @}
902	*/
903
904	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
905	* @{
906	*/
907	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
908	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
909	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
910	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
911	/**
912	* @}
913	*/
914
915	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
916	* @{
917	*/
918	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
919	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
920	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
921	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
922	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
923	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
924	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
925	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
926	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
927	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
928	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
929	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
930	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
931	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
932	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
933	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
934	/**
935	* @}
936	*/
937
938	/** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
939	* @{
940	*/
941	#define LL_TIM_ETRSOURCE_GPIO 0x00000000U /!< ETR input is connected to GPIO /
942	#if defined(COMP1) && defined(COMP2)
943	#define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /!< ETR input is connected to COMP1_OUT /
944	#define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /!< ETR input is connected to COMP2_OUT /
945	#endif /* COMP1 && COMP2 */
946	#define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 \| TIM1_AF1_ETRSEL_0) /!< ETR input is connected to ADC1 analog watchdog 1 /
947	#define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /!< ETR input is connected to ADC1 analog watchdog 2 /
948	#define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 \| TIM1_AF1_ETRSEL_0) /!< ETR input is connected to ADC1 analog watchdog 3 /
949	#define LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 \| TIM1_AF1_ETRSEL_0) /!< ETR input is connected to LSE /
950	/**
951	* @}
952	*/
953
954	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
955	* @{
956	*/
957	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
958	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
959	/**
960	* @}
961	*/
962
963	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
964	* @{
965	*/
966	#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
967	#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /!< fSAMPLING=fCK_INT, N=2 /
968	#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /!< fSAMPLING=fCK_INT, N=4 /
969	#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /!< fSAMPLING=fCK_INT, N=8 /
970	#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /!< fSAMPLING=fDTS/2, N=6 /
971	#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /!< fSAMPLING=fDTS/2, N=8 /
972	#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /!< fSAMPLING=fDTS/4, N=6 /
973	#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /!< fSAMPLING=fDTS/4, N=8 /
974	#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /!< fSAMPLING=fDTS/8, N=6 /
975	#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /!< fSAMPLING=fDTS/8, N=8 /
976	#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /!< fSAMPLING=fDTS/16, N=5 /
977	#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /!< fSAMPLING=fDTS/16, N=6 /
978	#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /!< fSAMPLING=fDTS/16, N=8 /
979	#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /!< fSAMPLING=fDTS/32, N=5 /
980	#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /!< fSAMPLING=fDTS/32, N=6 /
981	#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /!< fSAMPLING=fDTS/32, N=8 /
982	/**
983	* @}
984	*/
985
986	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
987	* @{
988	*/
989	#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
990	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
991	/**
992	* @}
993	*/
994
995	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
996	* @{
997	*/
998	#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
999	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /!< fSAMPLING=fCK_INT, N=2 /
1000	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /!< fSAMPLING=fCK_INT, N=4 /
1001	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /!< fSAMPLING=fCK_INT, N=8 /
1002	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /!< fSAMPLING=fDTS/2, N=6 /
1003	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /!< fSAMPLING=fDTS/2, N=8 /
1004	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /!< fSAMPLING=fDTS/4, N=6 /
1005	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /!< fSAMPLING=fDTS/4, N=8 /
1006	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /!< fSAMPLING=fDTS/8, N=6 /
1007	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /!< fSAMPLING=fDTS/8, N=8 /
1008	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /!< fSAMPLING=fDTS/16, N=5 /
1009	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /!< fSAMPLING=fDTS/16, N=6 /
1010	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /!< fSAMPLING=fDTS/16, N=8 /
1011	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /!< fSAMPLING=fDTS/32, N=5 /
1012	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /!< fSAMPLING=fDTS/32, N=6 /
1013	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /!< fSAMPLING=fDTS/32, N=8 /
1014	/**
1015	* @}
1016	*/
1017
1018	/** @defgroup TIM_LL_EC_OSSI OSSI
1019	* @{
1020	*/
1021	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
1022	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
1023	/**
1024	* @}
1025	*/
1026
1027	/** @defgroup TIM_LL_EC_OSSR OSSR
1028	* @{
1029	*/
1030	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
1031	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
1032	/**
1033	* @}
1034	*/
1035
1036	/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1037	* @{
1038	*/
1039	#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /!< TIMx_BKIN input /
1040	#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /!< TIMx_BKIN2 input /
1041	/**
1042	* @}
1043	*/
1044
1045	/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1046	* @{
1047	*/
1048	#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /!< BKIN input from AF controller /
1049	#if defined(COMP1) && defined(COMP2)
1050	#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /!< internal signal: COMP1 output /
1051	#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /!< internal signal: COMP2 output /
1052	#endif /* COMP1 && COMP2 */
1053	/**
1054	* @}
1055	*/
1056
1057	/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1058	* @{
1059	*/
1060	#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /!< BRK BKIN input is active low /
1061	#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /!< BRK BKIN input is active high /
1062	/**
1063	* @}
1064	*/
1065
1066	/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1067	* @{
1068	*/
1069	#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /!< Break input BRK in input mode /
1070	#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /!< Break input BRK in bidirectional mode /
1071	/**
1072	* @}
1073	*/
1074
1075	/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1076	* @{
1077	*/
1078	#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /!< Break2 input BRK2 in input mode /
1079	#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /!< Break2 input BRK2 in bidirectional mode /
1080	/**
1081	* @}
1082	*/
1083
1084	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1085	* @{
1086	*/
1087	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
1088	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
1089	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
1090	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
1091	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
1092	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
1093	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
1094	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
1095	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
1096	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
1097	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
1098	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
1099	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
1100	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
1101	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
1102	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
1103	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
1104	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
1105	#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_OR1 register is the DMA base address for DMA burst /
1106	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
1107	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
1108	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
1109	#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) /!< TIMx_AF1 register is the DMA base address for DMA burst /
1110	#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_AF2 register is the DMA base address for DMA burst /
1111	#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_TISEL register is the DMA base address for DMA burst /
1112	/**
1113	* @}
1114	*/
1115
1116	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1117	* @{
1118	*/
1119	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
1120	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
1121	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
1122	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
1123	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
1124	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
1125	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
1126	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
1127	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
1128	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
1129	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
1130	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
1131	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
1132	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
1133	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
1134	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
1135	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
1136	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
1137	/**
1138	* @}
1139	*/
1140
1141	/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1142	* @{
1143	*/
1144	#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /!< TIM1 input 1 is connected to GPIO /
1145	#if defined(COMP1)
1146	#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /!< TIM1 input 1 is connected to COMP1_OUT /
1147	#endif
1148	/**
1149	* @}
1150	*/
1151
1152	/** @defgroup TIM_LL_EC_TIM1_TI2_RMP TIM1 Timer Input Ch2 Remap
1153	* @{
1154	*/
1155	#define LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U /!< TIM1 input 2 is connected to GPIO /
1156	#if defined(COMP2)
1157	#define LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /!< TIM1 input 2 is connected to COMP2_OUT /
1158	#endif
1159	/**
1160	* @}
1161	*/
1162
1163	#if defined(TIM2)
1164	/** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
1165	* @{
1166	*/
1167	#define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /!< TIM2 input 1 is connected to GPIO /
1168	#define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /!< TIM2 input 1 is connected to COMP1_OUT /
1169	/**
1170	* @}
1171	*/
1172
1173	/** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
1174	* @{
1175	*/
1176	#define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /!< TIM2 input 2 is connected to GPIO /
1177	#define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /!< TIM2 input 2 is connected to COMP2_OUT /
1178	/**
1179	* @}
1180	*/
1181	#endif
1182
1183	/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1184	* @{
1185	*/
1186	#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /!< TIM3 input 1 is connected to GPIO /
1187	#if defined(COMP1)
1188	#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /!< TIM3 input 1 is connected to COMP1_OUT /
1189	#endif
1190	/**
1191	* @}
1192	*/
1193
1194	/** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
1195	* @{
1196	*/
1197	#define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /!< TIM3 input 2 is connected to GPIO /
1198	#if defined(COMP2)
1199	#define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /!< TIM3 input 2 is connected to COMP2_OUT /
1200	#endif
1201	/**
1202	* @}
1203	*/
1204
1205	/** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input Ch1 Remap
1206	* @{
1207	*/
1208	#define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U /!< TIM14 input 1 is connected to GPIO /
1209	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0 /!< TIM14 input 1 is connected to RTC clock /
1210	#define LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /!< TIM14_TI1 is connected to HSE/32 clock /
1211	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 \| TIM_TISEL_TI1SEL_1) /!< TIM14 input 1 is connected to MCO /
1212	/**
1213	* @}
1214	*/
1215
1216	/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1217	* @{
1218	*/
1219	#if defined(TIM15)
1220	#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /!< TIM15 input 1 is connected to GPIO /
1221	#if defined(TIM2)
1222	#define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0 /!< TIM15 input 1 is connected to TIM2 input 1 /
1223	#endif
1224	#if defined(TIM3)
1225	#define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1 /!< TIM15 input 1 is connected to TIM3 input 1 /
1226	#endif
1227	#endif
1228	/**
1229	* @}
1230	*/
1231
1232	/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1233	* @{
1234	*/
1235	#if defined(TIM15)
1236	#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /!< TIM15 input 2 is connected to GPIO /
1237	#if defined(TIM2)
1238	#define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0 /!< TIM15 input 2 is connected to TIM2 input 2 /
1239	#endif
1240	#if defined(TIM3)
1241	#define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1 /!< TIM15 input 2 is connected to TIM3 input 2 /
1242	#endif
1243	#endif
1244	/**
1245	* @}
1246	*/
1247
1248	/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1249	* @{
1250	*/
1251	#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /!< TIM16 input 1 is connected to GPIO /
1252	#define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /!< TIM16 input 1 is connected to LSI /
1253	#define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /!< TIM16 input 1 is connected to LSE /
1254	#define LL_TIM_TIM16_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_0 \| TIM_TISEL_TI1SEL_1) /!< TIM16 input 1 is connected to RTC_WAKEUP /
1255	/**
1256	* @}
1257	*/
1258
1259	/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1260	* @{
1261	*/
1262	#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /!< TIM17 input 1 is connected to GPIO /
1263	#define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /!< TIM17 input 1 is connected to HSE/32 clock /
1264	#define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 \| TIM_TISEL_TI1SEL_1) /!< TIM17 input 1 is connected to MCO /
1265	/**
1266	* @}
1267	*/
1268
1269	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1270	* @{
1271	*/
1272	#define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /!< OCREF_CLR_INT is connected to ETRF /
1273	#if defined(COMP1) && defined(COMP2)
1274	#define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /!< OCREF clear input is connected to COMP1_OUT /
1275	#define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR /!< OCREF clear input is connected to COMP2_OUT /
1276	#endif /* COMP1 & COMP2 */
1277	/**
1278	* @}
1279	*/
1280
1281	/** Legacy definitions for compatibility purpose
1282	@cond 0
1283	*/
1284	#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1285	/**
1286	@endcond
1287	*/
1288	/**
1289	* @}
1290	*/
1291
1292	/* Exported macro ------------------------------------------------------------*/
1293	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1294	* @{
1295	*/
1296
1297	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1298	* @{
1299	*/
1300	/**
1301	* @brief Write a value in TIM register.
1302	* @param __INSTANCE__ TIM Instance
1303	* @param __REG__ Register to be written
1304	* @param __VALUE__ Value to be written in the register
1305	* @retval None
1306	*/
1307	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1308
1309	/**
1310	* @brief Read a value in TIM register.
1311	* @param __INSTANCE__ TIM Instance
1312	* @param __REG__ Register to be read
1313	* @retval Register value
1314	*/
1315	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1316	/**
1317	* @}
1318	*/
1319
1320	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1321	* @{
1322	*/
1323
1324	/**
1325	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1326	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1327	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1328	* to TIMx_CNT register bit 31)
1329	* @param __CNT__ Counter value
1330	* @retval UIF status bit
1331	*/
1332	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1333	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1334
1335	/**
1336	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1337	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1338	* @param __TIMCLK__ timer input clock frequency (in Hz)
1339	* @param __CKD__ This parameter can be one of the following values:
1340	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1341	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1342	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1343	* @param __DT__ deadtime duration (in ns)
1344	* @retval DTG[0:7]
1345	*/
1346	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1347	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1348	(((uint64_t)((__DT__)1000U)) < ((64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1349	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1350	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1351	0U)
1352
1353	/**
1354	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1355	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1356	* @param __TIMCLK__ timer input clock frequency (in Hz)
1357	* @param __CNTCLK__ counter clock frequency (in Hz)
1358	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1359	*/
1360	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1361	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1362
1363	/**
1364	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1365	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1366	* @param __TIMCLK__ timer input clock frequency (in Hz)
1367	* @param __PSC__ prescaler
1368	* @param __FREQ__ output signal frequency (in Hz)
1369	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1370	*/
1371	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1372	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1373
1374	/**
1375	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1376	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1377	* @param __TIMCLK__ timer input clock frequency (in Hz)
1378	* @param __PSC__ prescaler
1379	* @param __DELAY__ timer output compare active/inactive delay (in us)
1380	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
1381	*/
1382	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1383	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1384	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1385
1386	/**
1387	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1388	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1389	* @param __TIMCLK__ timer input clock frequency (in Hz)
1390	* @param __PSC__ prescaler
1391	* @param __DELAY__ timer output compare active/inactive delay (in us)
1392	* @param __PULSE__ pulse duration (in us)
1393	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1394	*/
1395	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1396	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1397	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1398
1399	/**
1400	* @brief HELPER macro retrieving the ratio of the input capture prescaler
1401	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1402	* @param __ICPSC__ This parameter can be one of the following values:
1403	* @arg @ref LL_TIM_ICPSC_DIV1
1404	* @arg @ref LL_TIM_ICPSC_DIV2
1405	* @arg @ref LL_TIM_ICPSC_DIV4
1406	* @arg @ref LL_TIM_ICPSC_DIV8
1407	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
1408	*/
1409	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1410	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1411
1412
1413	/**
1414	* @}
1415	*/
1416
1417
1418	/**
1419	* @}
1420	*/
1421
1422	/* Exported functions --------------------------------------------------------*/
1423	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1424	* @{
1425	*/
1426
1427	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1428	* @{
1429	*/
1430	/**
1431	* @brief Enable timer counter.
1432	* @rmtoll CR1 CEN LL_TIM_EnableCounter
1433	* @param TIMx Timer instance
1434	* @retval None
1435	*/
1436	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1437	{
1438	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1439	}
1440
1441	/**
1442	* @brief Disable timer counter.
1443	* @rmtoll CR1 CEN LL_TIM_DisableCounter
1444	* @param TIMx Timer instance
1445	* @retval None
1446	*/
1447	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1448	{
1449	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1450	}
1451
1452	/**
1453	* @brief Indicates whether the timer counter is enabled.
1454	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1455	* @param TIMx Timer instance
1456	* @retval State of bit (1 or 0).
1457	*/
1458	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1459	{
1460	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1461	}
1462
1463	/**
1464	* @brief Enable update event generation.
1465	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1466	* @param TIMx Timer instance
1467	* @retval None
1468	*/
1469	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1470	{
1471	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1472	}
1473
1474	/**
1475	* @brief Disable update event generation.
1476	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1477	* @param TIMx Timer instance
1478	* @retval None
1479	*/
1480	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1481	{
1482	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1483	}
1484
1485	/**
1486	* @brief Indicates whether update event generation is enabled.
1487	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1488	* @param TIMx Timer instance
1489	* @retval Inverted state of bit (0 or 1).
1490	*/
1491	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1492	{
1493	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1494	}
1495
1496	/**
1497	* @brief Set update event source
1498	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1499	* generate an update interrupt or DMA request if enabled:
1500	* - Counter overflow/underflow
1501	* - Setting the UG bit
1502	* - Update generation through the slave mode controller
1503	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1504	* overflow/underflow generates an update interrupt or DMA request if enabled.
1505	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
1506	* @param TIMx Timer instance
1507	* @param UpdateSource This parameter can be one of the following values:
1508	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1509	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1510	* @retval None
1511	*/
1512	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1513	{
1514	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1515	}
1516
1517	/**
1518	* @brief Get actual event update source
1519	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
1520	* @param TIMx Timer instance
1521	* @retval Returned value can be one of the following values:
1522	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1523	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1524	*/
1525	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1526	{
1527	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1528	}
1529
1530	/**
1531	* @brief Set one pulse mode (one shot v.s. repetitive).
1532	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1533	* @param TIMx Timer instance
1534	* @param OnePulseMode This parameter can be one of the following values:
1535	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1536	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1537	* @retval None
1538	*/
1539	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1540	{
1541	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1542	}
1543
1544	/**
1545	* @brief Get actual one pulse mode.
1546	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1547	* @param TIMx Timer instance
1548	* @retval Returned value can be one of the following values:
1549	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1550	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1551	*/
1552	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1553	{
1554	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1555	}
1556
1557	/**
1558	* @brief Set the timer counter counting mode.
1559	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1560	* check whether or not the counter mode selection feature is supported
1561	* by a timer instance.
1562	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1563	* requires a timer reset to avoid unexpected direction
1564	* due to DIR bit readonly in center aligned mode.
1565	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1566	* CR1 CMS LL_TIM_SetCounterMode
1567	* @param TIMx Timer instance
1568	* @param CounterMode This parameter can be one of the following values:
1569	* @arg @ref LL_TIM_COUNTERMODE_UP
1570	* @arg @ref LL_TIM_COUNTERMODE_DOWN
1571	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1572	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1573	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1574	* @retval None
1575	*/
1576	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1577	{
1578	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
1579	}
1580
1581	/**
1582	* @brief Get actual counter mode.
1583	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1584	* check whether or not the counter mode selection feature is supported
1585	* by a timer instance.
1586	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1587	* CR1 CMS LL_TIM_GetCounterMode
1588	* @param TIMx Timer instance
1589	* @retval Returned value can be one of the following values:
1590	* @arg @ref LL_TIM_COUNTERMODE_UP
1591	* @arg @ref LL_TIM_COUNTERMODE_DOWN
1592	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1593	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1594	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1595	*/
1596	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1597	{
1598	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
1599	}
1600
1601	/**
1602	* @brief Enable auto-reload (ARR) preload.
1603	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1604	* @param TIMx Timer instance
1605	* @retval None
1606	*/
1607	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1608	{
1609	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1610	}
1611
1612	/**
1613	* @brief Disable auto-reload (ARR) preload.
1614	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1615	* @param TIMx Timer instance
1616	* @retval None
1617	*/
1618	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1619	{
1620	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1621	}
1622
1623	/**
1624	* @brief Indicates whether auto-reload (ARR) preload is enabled.
1625	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1626	* @param TIMx Timer instance
1627	* @retval State of bit (1 or 0).
1628	*/
1629	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1630	{
1631	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1632	}
1633
1634	/**
1635	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1636	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1637	* whether or not the clock division feature is supported by the timer
1638	* instance.
1639	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
1640	* @param TIMx Timer instance
1641	* @param ClockDivision This parameter can be one of the following values:
1642	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1643	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1644	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1645	* @retval None
1646	*/
1647	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1648	{
1649	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1650	}
1651
1652	/**
1653	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1654	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1655	* whether or not the clock division feature is supported by the timer
1656	* instance.
1657	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
1658	* @param TIMx Timer instance
1659	* @retval Returned value can be one of the following values:
1660	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1661	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1662	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1663	*/
1664	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1665	{
1666	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1667	}
1668
1669	/**
1670	* @brief Set the counter value.
1671	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1672	* whether or not a timer instance supports a 32 bits counter.
1673	* @rmtoll CNT CNT LL_TIM_SetCounter
1674	* @param TIMx Timer instance
1675	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1676	* @retval None
1677	*/
1678	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1679	{
1680	WRITE_REG(TIMx->CNT, Counter);
1681	}
1682
1683	/**
1684	* @brief Get the counter value.
1685	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1686	* whether or not a timer instance supports a 32 bits counter.
1687	* @rmtoll CNT CNT LL_TIM_GetCounter
1688	* @param TIMx Timer instance
1689	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1690	*/
1691	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1692	{
1693	return (uint32_t)(READ_REG(TIMx->CNT));
1694	}
1695
1696	/**
1697	* @brief Get the current direction of the counter
1698	* @rmtoll CR1 DIR LL_TIM_GetDirection
1699	* @param TIMx Timer instance
1700	* @retval Returned value can be one of the following values:
1701	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
1702	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1703	*/
1704	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1705	{
1706	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1707	}
1708
1709	/**
1710	* @brief Set the prescaler value.
1711	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1712	* @note The prescaler can be changed on the fly as this control register is buffered. The new
1713	* prescaler ratio is taken into account at the next update event.
1714	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1715	* @rmtoll PSC PSC LL_TIM_SetPrescaler
1716	* @param TIMx Timer instance
1717	* @param Prescaler between Min_Data=0 and Max_Data=65535
1718	* @retval None
1719	*/
1720	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1721	{
1722	WRITE_REG(TIMx->PSC, Prescaler);
1723	}
1724
1725	/**
1726	* @brief Get the prescaler value.
1727	* @rmtoll PSC PSC LL_TIM_GetPrescaler
1728	* @param TIMx Timer instance
1729	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
1730	*/
1731	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1732	{
1733	return (uint32_t)(READ_REG(TIMx->PSC));
1734	}
1735
1736	/**
1737	* @brief Set the auto-reload value.
1738	* @note The counter is blocked while the auto-reload value is null.
1739	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1740	* whether or not a timer instance supports a 32 bits counter.
1741	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1742	* @rmtoll ARR ARR LL_TIM_SetAutoReload
1743	* @param TIMx Timer instance
1744	* @param AutoReload between Min_Data=0 and Max_Data=65535
1745	* @retval None
1746	*/
1747	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1748	{
1749	WRITE_REG(TIMx->ARR, AutoReload);
1750	}
1751
1752	/**
1753	* @brief Get the auto-reload value.
1754	* @rmtoll ARR ARR LL_TIM_GetAutoReload
1755	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1756	* whether or not a timer instance supports a 32 bits counter.
1757	* @param TIMx Timer instance
1758	* @retval Auto-reload value
1759	*/
1760	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1761	{
1762	return (uint32_t)(READ_REG(TIMx->ARR));
1763	}
1764
1765	/**
1766	* @brief Set the repetition counter value.
1767	* @note For advanced timer instances RepetitionCounter can be up to 65535.
1768	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1769	* whether or not a timer instance supports a repetition counter.
1770	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1771	* @param TIMx Timer instance
1772	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
1773	* @retval None
1774	*/
1775	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1776	{
1777	WRITE_REG(TIMx->RCR, RepetitionCounter);
1778	}
1779
1780	/**
1781	* @brief Get the repetition counter value.
1782	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1783	* whether or not a timer instance supports a repetition counter.
1784	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1785	* @param TIMx Timer instance
1786	* @retval Repetition counter value
1787	*/
1788	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1789	{
1790	return (uint32_t)(READ_REG(TIMx->RCR));
1791	}
1792
1793	/**
1794	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1795	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1796	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1797	* @param TIMx Timer instance
1798	* @retval None
1799	*/
1800	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1801	{
1802	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1803	}
1804
1805	/**
1806	* @brief Disable update interrupt flag (UIF) remapping.
1807	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1808	* @param TIMx Timer instance
1809	* @retval None
1810	*/
1811	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1812	{
1813	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1814	}
1815
1816	/**
1817	* @}
1818	*/
1819
1820	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1821	* @{
1822	*/
1823	/**
1824	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1825	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1826	* they are updated only when a commutation event (COM) occurs.
1827	* @note Only on channels that have a complementary output.
1828	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1829	* whether or not a timer instance is able to generate a commutation event.
1830	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1831	* @param TIMx Timer instance
1832	* @retval None
1833	*/
1834	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1835	{
1836	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1837	}
1838
1839	/**
1840	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1841	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1842	* whether or not a timer instance is able to generate a commutation event.
1843	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1844	* @param TIMx Timer instance
1845	* @retval None
1846	*/
1847	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1848	{
1849	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1850	}
1851
1852	/**
1853	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1854	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1855	* whether or not a timer instance is able to generate a commutation event.
1856	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1857	* @param TIMx Timer instance
1858	* @param CCUpdateSource This parameter can be one of the following values:
1859	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1860	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1861	* @retval None
1862	*/
1863	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1864	{
1865	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1866	}
1867
1868	/**
1869	* @brief Set the trigger of the capture/compare DMA request.
1870	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1871	* @param TIMx Timer instance
1872	* @param DMAReqTrigger This parameter can be one of the following values:
1873	* @arg @ref LL_TIM_CCDMAREQUEST_CC
1874	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1875	* @retval None
1876	*/
1877	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1878	{
1879	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1880	}
1881
1882	/**
1883	* @brief Get actual trigger of the capture/compare DMA request.
1884	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1885	* @param TIMx Timer instance
1886	* @retval Returned value can be one of the following values:
1887	* @arg @ref LL_TIM_CCDMAREQUEST_CC
1888	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1889	*/
1890	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1891	{
1892	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1893	}
1894
1895	/**
1896	* @brief Set the lock level to freeze the
1897	* configuration of several capture/compare parameters.
1898	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1899	* the lock mechanism is supported by a timer instance.
1900	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1901	* @param TIMx Timer instance
1902	* @param LockLevel This parameter can be one of the following values:
1903	* @arg @ref LL_TIM_LOCKLEVEL_OFF
1904	* @arg @ref LL_TIM_LOCKLEVEL_1
1905	* @arg @ref LL_TIM_LOCKLEVEL_2
1906	* @arg @ref LL_TIM_LOCKLEVEL_3
1907	* @retval None
1908	*/
1909	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1910	{
1911	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1912	}
1913
1914	/**
1915	* @brief Enable capture/compare channels.
1916	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1917	* CCER CC1NE LL_TIM_CC_EnableChannel\n
1918	* CCER CC2E LL_TIM_CC_EnableChannel\n
1919	* CCER CC2NE LL_TIM_CC_EnableChannel\n
1920	* CCER CC3E LL_TIM_CC_EnableChannel\n
1921	* CCER CC3NE LL_TIM_CC_EnableChannel\n
1922	* CCER CC4E LL_TIM_CC_EnableChannel\n
1923	* CCER CC5E LL_TIM_CC_EnableChannel\n
1924	* CCER CC6E LL_TIM_CC_EnableChannel
1925	* @param TIMx Timer instance
1926	* @param Channels This parameter can be a combination of the following values:
1927	* @arg @ref LL_TIM_CHANNEL_CH1
1928	* @arg @ref LL_TIM_CHANNEL_CH1N
1929	* @arg @ref LL_TIM_CHANNEL_CH2
1930	* @arg @ref LL_TIM_CHANNEL_CH2N
1931	* @arg @ref LL_TIM_CHANNEL_CH3
1932	* @arg @ref LL_TIM_CHANNEL_CH3N
1933	* @arg @ref LL_TIM_CHANNEL_CH4
1934	* @arg @ref LL_TIM_CHANNEL_CH5
1935	* @arg @ref LL_TIM_CHANNEL_CH6
1936	* @retval None
1937	*/
1938	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1939	{
1940	SET_BIT(TIMx->CCER, Channels);
1941	}
1942
1943	/**
1944	* @brief Disable capture/compare channels.
1945	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1946	* CCER CC1NE LL_TIM_CC_DisableChannel\n
1947	* CCER CC2E LL_TIM_CC_DisableChannel\n
1948	* CCER CC2NE LL_TIM_CC_DisableChannel\n
1949	* CCER CC3E LL_TIM_CC_DisableChannel\n
1950	* CCER CC3NE LL_TIM_CC_DisableChannel\n
1951	* CCER CC4E LL_TIM_CC_DisableChannel\n
1952	* CCER CC5E LL_TIM_CC_DisableChannel\n
1953	* CCER CC6E LL_TIM_CC_DisableChannel
1954	* @param TIMx Timer instance
1955	* @param Channels This parameter can be a combination of the following values:
1956	* @arg @ref LL_TIM_CHANNEL_CH1
1957	* @arg @ref LL_TIM_CHANNEL_CH1N
1958	* @arg @ref LL_TIM_CHANNEL_CH2
1959	* @arg @ref LL_TIM_CHANNEL_CH2N
1960	* @arg @ref LL_TIM_CHANNEL_CH3
1961	* @arg @ref LL_TIM_CHANNEL_CH3N
1962	* @arg @ref LL_TIM_CHANNEL_CH4
1963	* @arg @ref LL_TIM_CHANNEL_CH5
1964	* @arg @ref LL_TIM_CHANNEL_CH6
1965	* @retval None
1966	*/
1967	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1968	{
1969	CLEAR_BIT(TIMx->CCER, Channels);
1970	}
1971
1972	/**
1973	* @brief Indicate whether channel(s) is(are) enabled.
1974	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1975	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1976	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1977	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1978	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1979	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1980	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1981	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1982	* CCER CC6E LL_TIM_CC_IsEnabledChannel
1983	* @param TIMx Timer instance
1984	* @param Channels This parameter can be a combination of the following values:
1985	* @arg @ref LL_TIM_CHANNEL_CH1
1986	* @arg @ref LL_TIM_CHANNEL_CH1N
1987	* @arg @ref LL_TIM_CHANNEL_CH2
1988	* @arg @ref LL_TIM_CHANNEL_CH2N
1989	* @arg @ref LL_TIM_CHANNEL_CH3
1990	* @arg @ref LL_TIM_CHANNEL_CH3N
1991	* @arg @ref LL_TIM_CHANNEL_CH4
1992	* @arg @ref LL_TIM_CHANNEL_CH5
1993	* @arg @ref LL_TIM_CHANNEL_CH6
1994	* @retval State of bit (1 or 0).
1995	*/
1996	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1997	{
1998	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1999	}
2000
2001	/**
2002	* @}
2003	*/
2004
2005	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2006	* @{
2007	*/
2008	/**
2009	* @brief Configure an output channel.
2010	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2011	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2012	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2013	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2014	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2015	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2016	* CCER CC1P LL_TIM_OC_ConfigOutput\n
2017	* CCER CC2P LL_TIM_OC_ConfigOutput\n
2018	* CCER CC3P LL_TIM_OC_ConfigOutput\n
2019	* CCER CC4P LL_TIM_OC_ConfigOutput\n
2020	* CCER CC5P LL_TIM_OC_ConfigOutput\n
2021	* CCER CC6P LL_TIM_OC_ConfigOutput\n
2022	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2023	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2024	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2025	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2026	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2027	* CR2 OIS6 LL_TIM_OC_ConfigOutput
2028	* @param TIMx Timer instance
2029	* @param Channel This parameter can be one of the following values:
2030	* @arg @ref LL_TIM_CHANNEL_CH1
2031	* @arg @ref LL_TIM_CHANNEL_CH2
2032	* @arg @ref LL_TIM_CHANNEL_CH3
2033	* @arg @ref LL_TIM_CHANNEL_CH4
2034	* @arg @ref LL_TIM_CHANNEL_CH5
2035	* @arg @ref LL_TIM_CHANNEL_CH6
2036	* @param Configuration This parameter must be a combination of all the following values:
2037	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2038	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2039	* @retval None
2040	*/
2041	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2042	{
2043	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2044	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2045	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2046	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2047	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2048	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2049	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2050	}
2051
2052	/**
2053	* @brief Define the behavior of the output reference signal OCxREF from which
2054	* OCx and OCxN (when relevant) are derived.
2055	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2056	* CCMR1 OC2M LL_TIM_OC_SetMode\n
2057	* CCMR2 OC3M LL_TIM_OC_SetMode\n
2058	* CCMR2 OC4M LL_TIM_OC_SetMode\n
2059	* CCMR3 OC5M LL_TIM_OC_SetMode\n
2060	* CCMR3 OC6M LL_TIM_OC_SetMode
2061	* @param TIMx Timer instance
2062	* @param Channel This parameter can be one of the following values:
2063	* @arg @ref LL_TIM_CHANNEL_CH1
2064	* @arg @ref LL_TIM_CHANNEL_CH2
2065	* @arg @ref LL_TIM_CHANNEL_CH3
2066	* @arg @ref LL_TIM_CHANNEL_CH4
2067	* @arg @ref LL_TIM_CHANNEL_CH5
2068	* @arg @ref LL_TIM_CHANNEL_CH6
2069	* @param Mode This parameter can be one of the following values:
2070	* @arg @ref LL_TIM_OCMODE_FROZEN
2071	* @arg @ref LL_TIM_OCMODE_ACTIVE
2072	* @arg @ref LL_TIM_OCMODE_INACTIVE
2073	* @arg @ref LL_TIM_OCMODE_TOGGLE
2074	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2075	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2076	* @arg @ref LL_TIM_OCMODE_PWM1
2077	* @arg @ref LL_TIM_OCMODE_PWM2
2078	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2079	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2080	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2081	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2082	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2083	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2084	* @retval None
2085	*/
2086	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2087	{
2088	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2089	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2090	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2091	}
2092
2093	/**
2094	* @brief Get the output compare mode of an output channel.
2095	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2096	* CCMR1 OC2M LL_TIM_OC_GetMode\n
2097	* CCMR2 OC3M LL_TIM_OC_GetMode\n
2098	* CCMR2 OC4M LL_TIM_OC_GetMode\n
2099	* CCMR3 OC5M LL_TIM_OC_GetMode\n
2100	* CCMR3 OC6M LL_TIM_OC_GetMode
2101	* @param TIMx Timer instance
2102	* @param Channel This parameter can be one of the following values:
2103	* @arg @ref LL_TIM_CHANNEL_CH1
2104	* @arg @ref LL_TIM_CHANNEL_CH2
2105	* @arg @ref LL_TIM_CHANNEL_CH3
2106	* @arg @ref LL_TIM_CHANNEL_CH4
2107	* @arg @ref LL_TIM_CHANNEL_CH5
2108	* @arg @ref LL_TIM_CHANNEL_CH6
2109	* @retval Returned value can be one of the following values:
2110	* @arg @ref LL_TIM_OCMODE_FROZEN
2111	* @arg @ref LL_TIM_OCMODE_ACTIVE
2112	* @arg @ref LL_TIM_OCMODE_INACTIVE
2113	* @arg @ref LL_TIM_OCMODE_TOGGLE
2114	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2115	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2116	* @arg @ref LL_TIM_OCMODE_PWM1
2117	* @arg @ref LL_TIM_OCMODE_PWM2
2118	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2119	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2120	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2121	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2122	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2123	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2124	*/
2125	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2126	{
2127	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2128	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2129	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2130	}
2131
2132	/**
2133	* @brief Set the polarity of an output channel.
2134	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2135	* CCER CC1NP LL_TIM_OC_SetPolarity\n
2136	* CCER CC2P LL_TIM_OC_SetPolarity\n
2137	* CCER CC2NP LL_TIM_OC_SetPolarity\n
2138	* CCER CC3P LL_TIM_OC_SetPolarity\n
2139	* CCER CC3NP LL_TIM_OC_SetPolarity\n
2140	* CCER CC4P LL_TIM_OC_SetPolarity\n
2141	* CCER CC5P LL_TIM_OC_SetPolarity\n
2142	* CCER CC6P LL_TIM_OC_SetPolarity
2143	* @param TIMx Timer instance
2144	* @param Channel This parameter can be one of the following values:
2145	* @arg @ref LL_TIM_CHANNEL_CH1
2146	* @arg @ref LL_TIM_CHANNEL_CH1N
2147	* @arg @ref LL_TIM_CHANNEL_CH2
2148	* @arg @ref LL_TIM_CHANNEL_CH2N
2149	* @arg @ref LL_TIM_CHANNEL_CH3
2150	* @arg @ref LL_TIM_CHANNEL_CH3N
2151	* @arg @ref LL_TIM_CHANNEL_CH4
2152	* @arg @ref LL_TIM_CHANNEL_CH5
2153	* @arg @ref LL_TIM_CHANNEL_CH6
2154	* @param Polarity This parameter can be one of the following values:
2155	* @arg @ref LL_TIM_OCPOLARITY_HIGH
2156	* @arg @ref LL_TIM_OCPOLARITY_LOW
2157	* @retval None
2158	*/
2159	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2160	{
2161	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2162	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2163	}
2164
2165	/**
2166	* @brief Get the polarity of an output channel.
2167	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2168	* CCER CC1NP LL_TIM_OC_GetPolarity\n
2169	* CCER CC2P LL_TIM_OC_GetPolarity\n
2170	* CCER CC2NP LL_TIM_OC_GetPolarity\n
2171	* CCER CC3P LL_TIM_OC_GetPolarity\n
2172	* CCER CC3NP LL_TIM_OC_GetPolarity\n
2173	* CCER CC4P LL_TIM_OC_GetPolarity\n
2174	* CCER CC5P LL_TIM_OC_GetPolarity\n
2175	* CCER CC6P LL_TIM_OC_GetPolarity
2176	* @param TIMx Timer instance
2177	* @param Channel This parameter can be one of the following values:
2178	* @arg @ref LL_TIM_CHANNEL_CH1
2179	* @arg @ref LL_TIM_CHANNEL_CH1N
2180	* @arg @ref LL_TIM_CHANNEL_CH2
2181	* @arg @ref LL_TIM_CHANNEL_CH2N
2182	* @arg @ref LL_TIM_CHANNEL_CH3
2183	* @arg @ref LL_TIM_CHANNEL_CH3N
2184	* @arg @ref LL_TIM_CHANNEL_CH4
2185	* @arg @ref LL_TIM_CHANNEL_CH5
2186	* @arg @ref LL_TIM_CHANNEL_CH6
2187	* @retval Returned value can be one of the following values:
2188	* @arg @ref LL_TIM_OCPOLARITY_HIGH
2189	* @arg @ref LL_TIM_OCPOLARITY_LOW
2190	*/
2191	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2192	{
2193	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2194	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2195	}
2196
2197	/**
2198	* @brief Set the IDLE state of an output channel
2199	* @note This function is significant only for the timer instances
2200	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
2201	* can be used to check whether or not a timer instance provides
2202	* a break input.
2203	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2204	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
2205	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
2206	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
2207	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
2208	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
2209	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
2210	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
2211	* CR2 OIS6 LL_TIM_OC_SetIdleState
2212	* @param TIMx Timer instance
2213	* @param Channel This parameter can be one of the following values:
2214	* @arg @ref LL_TIM_CHANNEL_CH1
2215	* @arg @ref LL_TIM_CHANNEL_CH1N
2216	* @arg @ref LL_TIM_CHANNEL_CH2
2217	* @arg @ref LL_TIM_CHANNEL_CH2N
2218	* @arg @ref LL_TIM_CHANNEL_CH3
2219	* @arg @ref LL_TIM_CHANNEL_CH3N
2220	* @arg @ref LL_TIM_CHANNEL_CH4
2221	* @arg @ref LL_TIM_CHANNEL_CH5
2222	* @arg @ref LL_TIM_CHANNEL_CH6
2223	* @param IdleState This parameter can be one of the following values:
2224	* @arg @ref LL_TIM_OCIDLESTATE_LOW
2225	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
2226	* @retval None
2227	*/
2228	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2229	{
2230	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2231	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2232	}
2233
2234	/**
2235	* @brief Get the IDLE state of an output channel
2236	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2237	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
2238	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
2239	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
2240	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
2241	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
2242	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
2243	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
2244	* CR2 OIS6 LL_TIM_OC_GetIdleState
2245	* @param TIMx Timer instance
2246	* @param Channel This parameter can be one of the following values:
2247	* @arg @ref LL_TIM_CHANNEL_CH1
2248	* @arg @ref LL_TIM_CHANNEL_CH1N
2249	* @arg @ref LL_TIM_CHANNEL_CH2
2250	* @arg @ref LL_TIM_CHANNEL_CH2N
2251	* @arg @ref LL_TIM_CHANNEL_CH3
2252	* @arg @ref LL_TIM_CHANNEL_CH3N
2253	* @arg @ref LL_TIM_CHANNEL_CH4
2254	* @arg @ref LL_TIM_CHANNEL_CH5
2255	* @arg @ref LL_TIM_CHANNEL_CH6
2256	* @retval Returned value can be one of the following values:
2257	* @arg @ref LL_TIM_OCIDLESTATE_LOW
2258	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
2259	*/
2260	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2261	{
2262	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2263	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2264	}
2265
2266	/**
2267	* @brief Enable fast mode for the output channel.
2268	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2269	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2270	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2271	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2272	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2273	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2274	* CCMR3 OC6FE LL_TIM_OC_EnableFast
2275	* @param TIMx Timer instance
2276	* @param Channel This parameter can be one of the following values:
2277	* @arg @ref LL_TIM_CHANNEL_CH1
2278	* @arg @ref LL_TIM_CHANNEL_CH2
2279	* @arg @ref LL_TIM_CHANNEL_CH3
2280	* @arg @ref LL_TIM_CHANNEL_CH4
2281	* @arg @ref LL_TIM_CHANNEL_CH5
2282	* @arg @ref LL_TIM_CHANNEL_CH6
2283	* @retval None
2284	*/
2285	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2286	{
2287	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2288	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2289	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2290
2291	}
2292
2293	/**
2294	* @brief Disable fast mode for the output channel.
2295	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2296	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2297	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2298	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2299	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2300	* CCMR3 OC6FE LL_TIM_OC_DisableFast
2301	* @param TIMx Timer instance
2302	* @param Channel This parameter can be one of the following values:
2303	* @arg @ref LL_TIM_CHANNEL_CH1
2304	* @arg @ref LL_TIM_CHANNEL_CH2
2305	* @arg @ref LL_TIM_CHANNEL_CH3
2306	* @arg @ref LL_TIM_CHANNEL_CH4
2307	* @arg @ref LL_TIM_CHANNEL_CH5
2308	* @arg @ref LL_TIM_CHANNEL_CH6
2309	* @retval None
2310	*/
2311	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2312	{
2313	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2314	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2315	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2316
2317	}
2318
2319	/**
2320	* @brief Indicates whether fast mode is enabled for the output channel.
2321	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2322	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2323	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2324	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2325	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2326	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2327	* @param TIMx Timer instance
2328	* @param Channel This parameter can be one of the following values:
2329	* @arg @ref LL_TIM_CHANNEL_CH1
2330	* @arg @ref LL_TIM_CHANNEL_CH2
2331	* @arg @ref LL_TIM_CHANNEL_CH3
2332	* @arg @ref LL_TIM_CHANNEL_CH4
2333	* @arg @ref LL_TIM_CHANNEL_CH5
2334	* @arg @ref LL_TIM_CHANNEL_CH6
2335	* @retval State of bit (1 or 0).
2336	*/
2337	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2338	{
2339	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2340	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2341	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2342	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2343	}
2344
2345	/**
2346	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2347	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2348	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2349	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2350	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2351	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2352	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
2353	* @param TIMx Timer instance
2354	* @param Channel This parameter can be one of the following values:
2355	* @arg @ref LL_TIM_CHANNEL_CH1
2356	* @arg @ref LL_TIM_CHANNEL_CH2
2357	* @arg @ref LL_TIM_CHANNEL_CH3
2358	* @arg @ref LL_TIM_CHANNEL_CH4
2359	* @arg @ref LL_TIM_CHANNEL_CH5
2360	* @arg @ref LL_TIM_CHANNEL_CH6
2361	* @retval None
2362	*/
2363	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2364	{
2365	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2366	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2367	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2368	}
2369
2370	/**
2371	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2372	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2373	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2374	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2375	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2376	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2377	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
2378	* @param TIMx Timer instance
2379	* @param Channel This parameter can be one of the following values:
2380	* @arg @ref LL_TIM_CHANNEL_CH1
2381	* @arg @ref LL_TIM_CHANNEL_CH2
2382	* @arg @ref LL_TIM_CHANNEL_CH3
2383	* @arg @ref LL_TIM_CHANNEL_CH4
2384	* @arg @ref LL_TIM_CHANNEL_CH5
2385	* @arg @ref LL_TIM_CHANNEL_CH6
2386	* @retval None
2387	*/
2388	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2389	{
2390	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2391	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2392	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2393	}
2394
2395	/**
2396	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2397	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2398	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2399	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2400	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2401	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2402	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2403	* @param TIMx Timer instance
2404	* @param Channel This parameter can be one of the following values:
2405	* @arg @ref LL_TIM_CHANNEL_CH1
2406	* @arg @ref LL_TIM_CHANNEL_CH2
2407	* @arg @ref LL_TIM_CHANNEL_CH3
2408	* @arg @ref LL_TIM_CHANNEL_CH4
2409	* @arg @ref LL_TIM_CHANNEL_CH5
2410	* @arg @ref LL_TIM_CHANNEL_CH6
2411	* @retval State of bit (1 or 0).
2412	*/
2413	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2414	{
2415	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2416	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2417	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2418	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2419	}
2420
2421	/**
2422	* @brief Enable clearing the output channel on an external event.
2423	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2424	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2425	* or not a timer instance can clear the OCxREF signal on an external event.
2426	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2427	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2428	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2429	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2430	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2431	* CCMR3 OC6CE LL_TIM_OC_EnableClear
2432	* @param TIMx Timer instance
2433	* @param Channel This parameter can be one of the following values:
2434	* @arg @ref LL_TIM_CHANNEL_CH1
2435	* @arg @ref LL_TIM_CHANNEL_CH2
2436	* @arg @ref LL_TIM_CHANNEL_CH3
2437	* @arg @ref LL_TIM_CHANNEL_CH4
2438	* @arg @ref LL_TIM_CHANNEL_CH5
2439	* @arg @ref LL_TIM_CHANNEL_CH6
2440	* @retval None
2441	*/
2442	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2443	{
2444	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2445	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2446	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2447	}
2448
2449	/**
2450	* @brief Disable clearing the output channel on an external event.
2451	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2452	* or not a timer instance can clear the OCxREF signal on an external event.
2453	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2454	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2455	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2456	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2457	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2458	* CCMR3 OC6CE LL_TIM_OC_DisableClear
2459	* @param TIMx Timer instance
2460	* @param Channel This parameter can be one of the following values:
2461	* @arg @ref LL_TIM_CHANNEL_CH1
2462	* @arg @ref LL_TIM_CHANNEL_CH2
2463	* @arg @ref LL_TIM_CHANNEL_CH3
2464	* @arg @ref LL_TIM_CHANNEL_CH4
2465	* @arg @ref LL_TIM_CHANNEL_CH5
2466	* @arg @ref LL_TIM_CHANNEL_CH6
2467	* @retval None
2468	*/
2469	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2470	{
2471	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2472	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2473	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2474	}
2475
2476	/**
2477	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2478	* @note This function enables clearing the output channel on an external event.
2479	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2480	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2481	* or not a timer instance can clear the OCxREF signal on an external event.
2482	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2483	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2484	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2485	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2486	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2487	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2488	* @param TIMx Timer instance
2489	* @param Channel This parameter can be one of the following values:
2490	* @arg @ref LL_TIM_CHANNEL_CH1
2491	* @arg @ref LL_TIM_CHANNEL_CH2
2492	* @arg @ref LL_TIM_CHANNEL_CH3
2493	* @arg @ref LL_TIM_CHANNEL_CH4
2494	* @arg @ref LL_TIM_CHANNEL_CH5
2495	* @arg @ref LL_TIM_CHANNEL_CH6
2496	* @retval State of bit (1 or 0).
2497	*/
2498	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2499	{
2500	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2501	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2502	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2503	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2504	}
2505
2506	/**
2507	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2508	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2509	* dead-time insertion feature is supported by a timer instance.
2510	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2511	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2512	* @param TIMx Timer instance
2513	* @param DeadTime between Min_Data=0 and Max_Data=255
2514	* @retval None
2515	*/
2516	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2517	{
2518	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2519	}
2520
2521	/**
2522	* @brief Set compare value for output channel 1 (TIMx_CCR1).
2523	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2524	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2525	* whether or not a timer instance supports a 32 bits counter.
2526	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2527	* output channel 1 is supported by a timer instance.
2528	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2529	* @param TIMx Timer instance
2530	* @param CompareValue between Min_Data=0 and Max_Data=65535
2531	* @retval None
2532	*/
2533	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2534	{
2535	WRITE_REG(TIMx->CCR1, CompareValue);
2536	}
2537
2538	/**
2539	* @brief Set compare value for output channel 2 (TIMx_CCR2).
2540	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2541	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2542	* whether or not a timer instance supports a 32 bits counter.
2543	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2544	* output channel 2 is supported by a timer instance.
2545	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2546	* @param TIMx Timer instance
2547	* @param CompareValue between Min_Data=0 and Max_Data=65535
2548	* @retval None
2549	*/
2550	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2551	{
2552	WRITE_REG(TIMx->CCR2, CompareValue);
2553	}
2554
2555	/**
2556	* @brief Set compare value for output channel 3 (TIMx_CCR3).
2557	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2558	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2559	* whether or not a timer instance supports a 32 bits counter.
2560	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2561	* output channel is supported by a timer instance.
2562	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2563	* @param TIMx Timer instance
2564	* @param CompareValue between Min_Data=0 and Max_Data=65535
2565	* @retval None
2566	*/
2567	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2568	{
2569	WRITE_REG(TIMx->CCR3, CompareValue);
2570	}
2571
2572	/**
2573	* @brief Set compare value for output channel 4 (TIMx_CCR4).
2574	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2575	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2576	* whether or not a timer instance supports a 32 bits counter.
2577	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2578	* output channel 4 is supported by a timer instance.
2579	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2580	* @param TIMx Timer instance
2581	* @param CompareValue between Min_Data=0 and Max_Data=65535
2582	* @retval None
2583	*/
2584	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2585	{
2586	WRITE_REG(TIMx->CCR4, CompareValue);
2587	}
2588
2589	/**
2590	* @brief Set compare value for output channel 5 (TIMx_CCR5).
2591	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2592	* output channel 5 is supported by a timer instance.
2593	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2594	* @param TIMx Timer instance
2595	* @param CompareValue between Min_Data=0 and Max_Data=65535
2596	* @retval None
2597	*/
2598	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2599	{
2600	WRITE_REG(TIMx->CCR5, CompareValue);
2601	}
2602
2603	/**
2604	* @brief Set compare value for output channel 6 (TIMx_CCR6).
2605	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2606	* output channel 6 is supported by a timer instance.
2607	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2608	* @param TIMx Timer instance
2609	* @param CompareValue between Min_Data=0 and Max_Data=65535
2610	* @retval None
2611	*/
2612	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2613	{
2614	WRITE_REG(TIMx->CCR6, CompareValue);
2615	}
2616
2617	/**
2618	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
2619	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2620	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2621	* whether or not a timer instance supports a 32 bits counter.
2622	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2623	* output channel 1 is supported by a timer instance.
2624	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2625	* @param TIMx Timer instance
2626	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2627	*/
2628	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2629	{
2630	return (uint32_t)(READ_REG(TIMx->CCR1));
2631	}
2632
2633	/**
2634	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
2635	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2636	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2637	* whether or not a timer instance supports a 32 bits counter.
2638	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2639	* output channel 2 is supported by a timer instance.
2640	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2641	* @param TIMx Timer instance
2642	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2643	*/
2644	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2645	{
2646	return (uint32_t)(READ_REG(TIMx->CCR2));
2647	}
2648
2649	/**
2650	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
2651	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2652	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2653	* whether or not a timer instance supports a 32 bits counter.
2654	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2655	* output channel 3 is supported by a timer instance.
2656	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2657	* @param TIMx Timer instance
2658	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2659	*/
2660	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2661	{
2662	return (uint32_t)(READ_REG(TIMx->CCR3));
2663	}
2664
2665	/**
2666	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
2667	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2668	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2669	* whether or not a timer instance supports a 32 bits counter.
2670	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2671	* output channel 4 is supported by a timer instance.
2672	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2673	* @param TIMx Timer instance
2674	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2675	*/
2676	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2677	{
2678	return (uint32_t)(READ_REG(TIMx->CCR4));
2679	}
2680
2681	/**
2682	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
2683	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2684	* output channel 5 is supported by a timer instance.
2685	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2686	* @param TIMx Timer instance
2687	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2688	*/
2689	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2690	{
2691	return (uint32_t)(READ_REG(TIMx->CCR5));
2692	}
2693
2694	/**
2695	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
2696	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2697	* output channel 6 is supported by a timer instance.
2698	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2699	* @param TIMx Timer instance
2700	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2701	*/
2702	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2703	{
2704	return (uint32_t)(READ_REG(TIMx->CCR6));
2705	}
2706
2707	/**
2708	* @brief Select on which reference signal the OC5REF is combined to.
2709	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2710	* whether or not a timer instance supports the combined 3-phase PWM mode.
2711	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2712	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2713	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2714	* @param TIMx Timer instance
2715	* @param GroupCH5 This parameter can be one of the following values:
2716	* @arg @ref LL_TIM_GROUPCH5_NONE
2717	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
2718	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
2719	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
2720	* @retval None
2721	*/
2722	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2723	{
2724	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
2725	}
2726
2727	/**
2728	* @}
2729	*/
2730
2731	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2732	* @{
2733	*/
2734	/**
2735	* @brief Configure input channel.
2736	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2737	* CCMR1 IC1PSC LL_TIM_IC_Config\n
2738	* CCMR1 IC1F LL_TIM_IC_Config\n
2739	* CCMR1 CC2S LL_TIM_IC_Config\n
2740	* CCMR1 IC2PSC LL_TIM_IC_Config\n
2741	* CCMR1 IC2F LL_TIM_IC_Config\n
2742	* CCMR2 CC3S LL_TIM_IC_Config\n
2743	* CCMR2 IC3PSC LL_TIM_IC_Config\n
2744	* CCMR2 IC3F LL_TIM_IC_Config\n
2745	* CCMR2 CC4S LL_TIM_IC_Config\n
2746	* CCMR2 IC4PSC LL_TIM_IC_Config\n
2747	* CCMR2 IC4F LL_TIM_IC_Config\n
2748	* CCER CC1P LL_TIM_IC_Config\n
2749	* CCER CC1NP LL_TIM_IC_Config\n
2750	* CCER CC2P LL_TIM_IC_Config\n
2751	* CCER CC2NP LL_TIM_IC_Config\n
2752	* CCER CC3P LL_TIM_IC_Config\n
2753	* CCER CC3NP LL_TIM_IC_Config\n
2754	* CCER CC4P LL_TIM_IC_Config\n
2755	* CCER CC4NP LL_TIM_IC_Config
2756	* @param TIMx Timer instance
2757	* @param Channel This parameter can be one of the following values:
2758	* @arg @ref LL_TIM_CHANNEL_CH1
2759	* @arg @ref LL_TIM_CHANNEL_CH2
2760	* @arg @ref LL_TIM_CHANNEL_CH3
2761	* @arg @ref LL_TIM_CHANNEL_CH4
2762	* @param Configuration This parameter must be a combination of all the following values:
2763	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2764	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2765	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2766	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2767	* @retval None
2768	*/
2769	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2770	{
2771	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2772	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2773	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2774	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2775	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2776	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2777	}
2778
2779	/**
2780	* @brief Set the active input.
2781	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2782	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2783	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2784	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
2785	* @param TIMx Timer instance
2786	* @param Channel This parameter can be one of the following values:
2787	* @arg @ref LL_TIM_CHANNEL_CH1
2788	* @arg @ref LL_TIM_CHANNEL_CH2
2789	* @arg @ref LL_TIM_CHANNEL_CH3
2790	* @arg @ref LL_TIM_CHANNEL_CH4
2791	* @param ICActiveInput This parameter can be one of the following values:
2792	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2793	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2794	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
2795	* @retval None
2796	*/
2797	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2798	{
2799	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2800	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2801	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2802	}
2803
2804	/**
2805	* @brief Get the current active input.
2806	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2807	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2808	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2809	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
2810	* @param TIMx Timer instance
2811	* @param Channel This parameter can be one of the following values:
2812	* @arg @ref LL_TIM_CHANNEL_CH1
2813	* @arg @ref LL_TIM_CHANNEL_CH2
2814	* @arg @ref LL_TIM_CHANNEL_CH3
2815	* @arg @ref LL_TIM_CHANNEL_CH4
2816	* @retval Returned value can be one of the following values:
2817	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2818	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2819	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
2820	*/
2821	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2822	{
2823	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2824	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2825	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2826	}
2827
2828	/**
2829	* @brief Set the prescaler of input channel.
2830	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2831	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2832	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2833	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2834	* @param TIMx Timer instance
2835	* @param Channel This parameter can be one of the following values:
2836	* @arg @ref LL_TIM_CHANNEL_CH1
2837	* @arg @ref LL_TIM_CHANNEL_CH2
2838	* @arg @ref LL_TIM_CHANNEL_CH3
2839	* @arg @ref LL_TIM_CHANNEL_CH4
2840	* @param ICPrescaler This parameter can be one of the following values:
2841	* @arg @ref LL_TIM_ICPSC_DIV1
2842	* @arg @ref LL_TIM_ICPSC_DIV2
2843	* @arg @ref LL_TIM_ICPSC_DIV4
2844	* @arg @ref LL_TIM_ICPSC_DIV8
2845	* @retval None
2846	*/
2847	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2848	{
2849	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2850	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2851	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2852	}
2853
2854	/**
2855	* @brief Get the current prescaler value acting on an input channel.
2856	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2857	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2858	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2859	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2860	* @param TIMx Timer instance
2861	* @param Channel This parameter can be one of the following values:
2862	* @arg @ref LL_TIM_CHANNEL_CH1
2863	* @arg @ref LL_TIM_CHANNEL_CH2
2864	* @arg @ref LL_TIM_CHANNEL_CH3
2865	* @arg @ref LL_TIM_CHANNEL_CH4
2866	* @retval Returned value can be one of the following values:
2867	* @arg @ref LL_TIM_ICPSC_DIV1
2868	* @arg @ref LL_TIM_ICPSC_DIV2
2869	* @arg @ref LL_TIM_ICPSC_DIV4
2870	* @arg @ref LL_TIM_ICPSC_DIV8
2871	*/
2872	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2873	{
2874	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2875	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2876	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2877	}
2878
2879	/**
2880	* @brief Set the input filter duration.
2881	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2882	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
2883	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
2884	* CCMR2 IC4F LL_TIM_IC_SetFilter
2885	* @param TIMx Timer instance
2886	* @param Channel This parameter can be one of the following values:
2887	* @arg @ref LL_TIM_CHANNEL_CH1
2888	* @arg @ref LL_TIM_CHANNEL_CH2
2889	* @arg @ref LL_TIM_CHANNEL_CH3
2890	* @arg @ref LL_TIM_CHANNEL_CH4
2891	* @param ICFilter This parameter can be one of the following values:
2892	* @arg @ref LL_TIM_IC_FILTER_FDIV1
2893	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2894	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2895	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2896	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2897	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2898	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2899	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2900	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2901	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2902	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2903	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2904	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2905	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2906	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2907	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2908	* @retval None
2909	*/
2910	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2911	{
2912	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2913	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2914	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2915	}
2916
2917	/**
2918	* @brief Get the input filter duration.
2919	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2920	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
2921	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
2922	* CCMR2 IC4F LL_TIM_IC_GetFilter
2923	* @param TIMx Timer instance
2924	* @param Channel This parameter can be one of the following values:
2925	* @arg @ref LL_TIM_CHANNEL_CH1
2926	* @arg @ref LL_TIM_CHANNEL_CH2
2927	* @arg @ref LL_TIM_CHANNEL_CH3
2928	* @arg @ref LL_TIM_CHANNEL_CH4
2929	* @retval Returned value can be one of the following values:
2930	* @arg @ref LL_TIM_IC_FILTER_FDIV1
2931	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2932	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2933	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2934	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2935	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2936	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2937	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2938	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2939	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2940	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2941	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2942	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2943	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2944	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2945	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2946	*/
2947	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2948	{
2949	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2950	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2951	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2952	}
2953
2954	/**
2955	* @brief Set the input channel polarity.
2956	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2957	* CCER CC1NP LL_TIM_IC_SetPolarity\n
2958	* CCER CC2P LL_TIM_IC_SetPolarity\n
2959	* CCER CC2NP LL_TIM_IC_SetPolarity\n
2960	* CCER CC3P LL_TIM_IC_SetPolarity\n
2961	* CCER CC3NP LL_TIM_IC_SetPolarity\n
2962	* CCER CC4P LL_TIM_IC_SetPolarity\n
2963	* CCER CC4NP LL_TIM_IC_SetPolarity
2964	* @param TIMx Timer instance
2965	* @param Channel This parameter can be one of the following values:
2966	* @arg @ref LL_TIM_CHANNEL_CH1
2967	* @arg @ref LL_TIM_CHANNEL_CH2
2968	* @arg @ref LL_TIM_CHANNEL_CH3
2969	* @arg @ref LL_TIM_CHANNEL_CH4
2970	* @param ICPolarity This parameter can be one of the following values:
2971	* @arg @ref LL_TIM_IC_POLARITY_RISING
2972	* @arg @ref LL_TIM_IC_POLARITY_FALLING
2973	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2974	* @retval None
2975	*/
2976	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2977	{
2978	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2979	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2980	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2981	}
2982
2983	/**
2984	* @brief Get the current input channel polarity.
2985	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2986	* CCER CC1NP LL_TIM_IC_GetPolarity\n
2987	* CCER CC2P LL_TIM_IC_GetPolarity\n
2988	* CCER CC2NP LL_TIM_IC_GetPolarity\n
2989	* CCER CC3P LL_TIM_IC_GetPolarity\n
2990	* CCER CC3NP LL_TIM_IC_GetPolarity\n
2991	* CCER CC4P LL_TIM_IC_GetPolarity\n
2992	* CCER CC4NP LL_TIM_IC_GetPolarity
2993	* @param TIMx Timer instance
2994	* @param Channel This parameter can be one of the following values:
2995	* @arg @ref LL_TIM_CHANNEL_CH1
2996	* @arg @ref LL_TIM_CHANNEL_CH2
2997	* @arg @ref LL_TIM_CHANNEL_CH3
2998	* @arg @ref LL_TIM_CHANNEL_CH4
2999	* @retval Returned value can be one of the following values:
3000	* @arg @ref LL_TIM_IC_POLARITY_RISING
3001	* @arg @ref LL_TIM_IC_POLARITY_FALLING
3002	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3003	*/
3004	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
3005	{
3006	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3007	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3008	SHIFT_TAB_CCxP[iChannel]);
3009	}
3010
3011	/**
3012	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3013	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3014	* a timer instance provides an XOR input.
3015	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3016	* @param TIMx Timer instance
3017	* @retval None
3018	*/
3019	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3020	{
3021	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3022	}
3023
3024	/**
3025	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3026	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3027	* a timer instance provides an XOR input.
3028	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3029	* @param TIMx Timer instance
3030	* @retval None
3031	*/
3032	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3033	{
3034	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3035	}
3036
3037	/**
3038	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3039	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3040	* a timer instance provides an XOR input.
3041	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3042	* @param TIMx Timer instance
3043	* @retval State of bit (1 or 0).
3044	*/
3045	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3046	{
3047	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3048	}
3049
3050	/**
3051	* @brief Get captured value for input channel 1.
3052	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3053	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3054	* whether or not a timer instance supports a 32 bits counter.
3055	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3056	* input channel 1 is supported by a timer instance.
3057	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3058	* @param TIMx Timer instance
3059	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3060	*/
3061	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3062	{
3063	return (uint32_t)(READ_REG(TIMx->CCR1));
3064	}
3065
3066	/**
3067	* @brief Get captured value for input channel 2.
3068	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3069	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3070	* whether or not a timer instance supports a 32 bits counter.
3071	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3072	* input channel 2 is supported by a timer instance.
3073	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3074	* @param TIMx Timer instance
3075	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3076	*/
3077	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3078	{
3079	return (uint32_t)(READ_REG(TIMx->CCR2));
3080	}
3081
3082	/**
3083	* @brief Get captured value for input channel 3.
3084	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3085	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3086	* whether or not a timer instance supports a 32 bits counter.
3087	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3088	* input channel 3 is supported by a timer instance.
3089	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3090	* @param TIMx Timer instance
3091	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3092	*/
3093	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3094	{
3095	return (uint32_t)(READ_REG(TIMx->CCR3));
3096	}
3097
3098	/**
3099	* @brief Get captured value for input channel 4.
3100	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3101	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3102	* whether or not a timer instance supports a 32 bits counter.
3103	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3104	* input channel 4 is supported by a timer instance.
3105	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3106	* @param TIMx Timer instance
3107	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3108	*/
3109	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3110	{
3111	return (uint32_t)(READ_REG(TIMx->CCR4));
3112	}
3113
3114	/**
3115	* @}
3116	*/
3117
3118	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3119	* @{
3120	*/
3121	/**
3122	* @brief Enable external clock mode 2.
3123	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3124	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3125	* whether or not a timer instance supports external clock mode2.
3126	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3127	* @param TIMx Timer instance
3128	* @retval None
3129	*/
3130	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3131	{
3132	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3133	}
3134
3135	/**
3136	* @brief Disable external clock mode 2.
3137	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3138	* whether or not a timer instance supports external clock mode2.
3139	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3140	* @param TIMx Timer instance
3141	* @retval None
3142	*/
3143	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3144	{
3145	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3146	}
3147
3148	/**
3149	* @brief Indicate whether external clock mode 2 is enabled.
3150	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3151	* whether or not a timer instance supports external clock mode2.
3152	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3153	* @param TIMx Timer instance
3154	* @retval State of bit (1 or 0).
3155	*/
3156	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3157	{
3158	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3159	}
3160
3161	/**
3162	* @brief Set the clock source of the counter clock.
3163	* @note when selected clock source is external clock mode 1, the timer input
3164	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3165	* function. This timer input must be configured by calling
3166	* the @ref LL_TIM_IC_Config() function.
3167	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3168	* whether or not a timer instance supports external clock mode1.
3169	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3170	* whether or not a timer instance supports external clock mode2.
3171	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3172	* SMCR ECE LL_TIM_SetClockSource
3173	* @param TIMx Timer instance
3174	* @param ClockSource This parameter can be one of the following values:
3175	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3176	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3177	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3178	* @retval None
3179	*/
3180	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3181	{
3182	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
3183	}
3184
3185	/**
3186	* @brief Set the encoder interface mode.
3187	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3188	* whether or not a timer instance supports the encoder mode.
3189	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3190	* @param TIMx Timer instance
3191	* @param EncoderMode This parameter can be one of the following values:
3192	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3193	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3194	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3195	* @retval None
3196	*/
3197	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3198	{
3199	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3200	}
3201
3202	/**
3203	* @}
3204	*/
3205
3206	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3207	* @{
3208	*/
3209	/**
3210	* @brief Set the trigger output (TRGO) used for timer synchronization .
3211	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3212	* whether or not a timer instance can operate as a master timer.
3213	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3214	* @param TIMx Timer instance
3215	* @param TimerSynchronization This parameter can be one of the following values:
3216	* @arg @ref LL_TIM_TRGO_RESET
3217	* @arg @ref LL_TIM_TRGO_ENABLE
3218	* @arg @ref LL_TIM_TRGO_UPDATE
3219	* @arg @ref LL_TIM_TRGO_CC1IF
3220	* @arg @ref LL_TIM_TRGO_OC1REF
3221	* @arg @ref LL_TIM_TRGO_OC2REF
3222	* @arg @ref LL_TIM_TRGO_OC3REF
3223	* @arg @ref LL_TIM_TRGO_OC4REF
3224	* @retval None
3225	*/
3226	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3227	{
3228	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3229	}
3230
3231	/**
3232	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3233	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3234	* whether or not a timer instance can be used for ADC synchronization.
3235	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3236	* @param TIMx Timer Instance
3237	* @param ADCSynchronization This parameter can be one of the following values:
3238	* @arg @ref LL_TIM_TRGO2_RESET
3239	* @arg @ref LL_TIM_TRGO2_ENABLE
3240	* @arg @ref LL_TIM_TRGO2_UPDATE
3241	* @arg @ref LL_TIM_TRGO2_CC1F
3242	* @arg @ref LL_TIM_TRGO2_OC1
3243	* @arg @ref LL_TIM_TRGO2_OC2
3244	* @arg @ref LL_TIM_TRGO2_OC3
3245	* @arg @ref LL_TIM_TRGO2_OC4
3246	* @arg @ref LL_TIM_TRGO2_OC5
3247	* @arg @ref LL_TIM_TRGO2_OC6
3248	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3249	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3250	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3251	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3252	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3253	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3254	* @retval None
3255	*/
3256	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3257	{
3258	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3259	}
3260
3261	/**
3262	* @brief Set the synchronization mode of a slave timer.
3263	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3264	* a timer instance can operate as a slave timer.
3265	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3266	* @param TIMx Timer instance
3267	* @param SlaveMode This parameter can be one of the following values:
3268	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
3269	* @arg @ref LL_TIM_SLAVEMODE_RESET
3270	* @arg @ref LL_TIM_SLAVEMODE_GATED
3271	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3272	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3273	* @retval None
3274	*/
3275	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3276	{
3277	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3278	}
3279
3280	/**
3281	* @brief Set the selects the trigger input to be used to synchronize the counter.
3282	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3283	* a timer instance can operate as a slave timer.
3284	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
3285	* @param TIMx Timer instance
3286	* @param TriggerInput This parameter can be one of the following values:
3287	* @arg @ref LL_TIM_TS_ITR0
3288	* @arg @ref LL_TIM_TS_ITR1
3289	* @arg @ref LL_TIM_TS_ITR2
3290	* @arg @ref LL_TIM_TS_ITR3
3291	* @arg @ref LL_TIM_TS_TI1F_ED
3292	* @arg @ref LL_TIM_TS_TI1FP1
3293	* @arg @ref LL_TIM_TS_TI2FP2
3294	* @arg @ref LL_TIM_TS_ETRF
3295	* @retval None
3296	*/
3297	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3298	{
3299	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3300	}
3301
3302	/**
3303	* @brief Enable the Master/Slave mode.
3304	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3305	* a timer instance can operate as a slave timer.
3306	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3307	* @param TIMx Timer instance
3308	* @retval None
3309	*/
3310	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3311	{
3312	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3313	}
3314
3315	/**
3316	* @brief Disable the Master/Slave mode.
3317	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3318	* a timer instance can operate as a slave timer.
3319	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3320	* @param TIMx Timer instance
3321	* @retval None
3322	*/
3323	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3324	{
3325	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3326	}
3327
3328	/**
3329	* @brief Indicates whether the Master/Slave mode is enabled.
3330	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3331	* a timer instance can operate as a slave timer.
3332	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3333	* @param TIMx Timer instance
3334	* @retval State of bit (1 or 0).
3335	*/
3336	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3337	{
3338	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3339	}
3340
3341	/**
3342	* @brief Configure the external trigger (ETR) input.
3343	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3344	* a timer instance provides an external trigger input.
3345	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3346	* SMCR ETPS LL_TIM_ConfigETR\n
3347	* SMCR ETF LL_TIM_ConfigETR
3348	* @param TIMx Timer instance
3349	* @param ETRPolarity This parameter can be one of the following values:
3350	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3351	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3352	* @param ETRPrescaler This parameter can be one of the following values:
3353	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3354	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3355	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3356	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3357	* @param ETRFilter This parameter can be one of the following values:
3358	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
3359	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3360	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3361	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3362	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3363	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3364	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3365	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3366	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3367	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3368	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3369	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3370	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3371	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3372	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3373	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3374	* @retval None
3375	*/
3376	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3377	uint32_t ETRFilter)
3378	{
3379	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
3380	}
3381
3382	/**
3383	* @brief Select the external trigger (ETR) input source.
3384	* @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3385	* not a timer instance supports ETR source selection.
3386	* @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3387	* @param TIMx Timer instance
3388	* @param ETRSource This parameter can be one of the following values:
3389	* TIM1
3390	*
3391	* @arg @ref LL_TIM_ETRSOURCE_GPIO
3392	* @if STM32G081xx
3393	* @arg @ref LL_TIM_ETRSOURCE_COMP1
3394	* @arg @ref LL_TIM_ETRSOURCE_COMP2
3395	* @endif
3396	* @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3397	* @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3398	* @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3399	*
3400	* TIM2
3401	*
3402	* @arg @ref LL_TIM_ETRSOURCE_GPIO
3403	* @if STM32G081xx
3404	* @arg @ref LL_TIM_ETRSOURCE_COMP1
3405	* @arg @ref LL_TIM_ETRSOURCE_COMP2
3406	* @endif
3407	* @arg @ref LL_TIM_ETRSOURCE_LSE
3408	*
3409	* TIM3
3410	*
3411	* @arg @ref LL_TIM_ETRSOURCE_GPIO
3412	* @if STM32G081xx
3413	* @arg @ref LL_TIM_ETRSOURCE_COMP1
3414	* @arg @ref LL_TIM_ETRSOURCE_COMP2
3415	* @endif
3416	* @retval None
3417	*/
3418	__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3419	{
3420
3421	MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3422	}
3423
3424	/**
3425	* @}
3426	*/
3427
3428	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
3429	* @{
3430	*/
3431	/**
3432	* @brief Enable the break function.
3433	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3434	* a timer instance provides a break input.
3435	* @rmtoll BDTR BKE LL_TIM_EnableBRK
3436	* @param TIMx Timer instance
3437	* @retval None
3438	*/
3439	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3440	{
3441	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3442	}
3443
3444	/**
3445	* @brief Disable the break function.
3446	* @rmtoll BDTR BKE LL_TIM_DisableBRK
3447	* @param TIMx Timer instance
3448	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3449	* a timer instance provides a break input.
3450	* @retval None
3451	*/
3452	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3453	{
3454	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3455	}
3456
3457	/**
3458	* @brief Configure the break input.
3459	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3460	* a timer instance provides a break input.
3461	* @note Bidirectional mode is only supported by advanced timer instances.
3462	* Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3463	* a timer instance is an advanced-control timer.
3464	* @note In bidirectional mode (BKBID bit set), the Break input is configured both
3465	* in input mode and in open drain output mode. Any active Break event will
3466	* assert a low logic level on the Break input to indicate an internal break
3467	* event to external devices.
3468	* @note When bidirectional mode isn't supported, BreakAFMode must be set to
3469	* LL_TIM_BREAK_AFMODE_INPUT.
3470	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3471	* BDTR BKF LL_TIM_ConfigBRK\n
3472	* BDTR BKBID LL_TIM_ConfigBRK
3473	* @param TIMx Timer instance
3474	* @param BreakPolarity This parameter can be one of the following values:
3475	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
3476	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3477	* @param BreakFilter This parameter can be one of the following values:
3478	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3479	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3480	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3481	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3482	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3483	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3484	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3485	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3486	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3487	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3488	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3489	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3490	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3491	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3492	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3493	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3494	* @param BreakAFMode This parameter can be one of the following values:
3495	* @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3496	* @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3497	* @retval None
3498	*/
3499	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, uint32_t BreakAFMode)
3500	{
3501	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF \| TIM_BDTR_BKBID , BreakPolarity \| BreakFilter \| BreakAFMode);
3502	}
3503
3504	/**
3505	* @brief Disarm the break input (when it operates in bidirectional mode).
3506	* @note The break input can be disarmed only when it is configured in
3507	* bidirectional mode and when when MOE is reset.
3508	* @note Purpose is to be able to have the input voltage back to high-state,
3509	* whatever the time constant on the output .
3510	* @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3511	* @param TIMx Timer instance
3512	* @retval None
3513	*/
3514	__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3515	{
3516	SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3517	}
3518
3519	/**
3520	* @brief Re-arm the break input (when it operates in bidirectional mode).
3521	* @note The Break input is automatically armed as soon as MOE bit is set.
3522	* @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3523	* @param TIMx Timer instance
3524	* @retval None
3525	*/
3526	__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3527	{
3528	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3529	}
3530
3531	/**
3532	* @brief Enable the break 2 function.
3533	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3534	* a timer instance provides a second break input.
3535	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3536	* @param TIMx Timer instance
3537	* @retval None
3538	*/
3539	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3540	{
3541	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3542	}
3543
3544	/**
3545	* @brief Disable the break 2 function.
3546	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3547	* a timer instance provides a second break input.
3548	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3549	* @param TIMx Timer instance
3550	* @retval None
3551	*/
3552	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3553	{
3554	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3555	}
3556
3557	/**
3558	* @brief Configure the break 2 input.
3559	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3560	* a timer instance provides a second break input.
3561	* @note Bidirectional mode is only supported by advanced timer instances.
3562	* Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3563	* a timer instance is an advanced-control timer.
3564	* @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3565	* in input mode and in open drain output mode. Any active Break event will
3566	* assert a low logic level on the Break 2 input to indicate an internal break
3567	* event to external devices.
3568	* @note When bidirectional mode isn't supported, Break2AFMode must be set to
3569	* LL_TIM_BREAK2_AFMODE_INPUT.
3570	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3571	* BDTR BK2F LL_TIM_ConfigBRK2\n
3572	* BDTR BK2BID LL_TIM_ConfigBRK2
3573	* @param TIMx Timer instance
3574	* @param Break2Polarity This parameter can be one of the following values:
3575	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3576	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3577	* @param Break2Filter This parameter can be one of the following values:
3578	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3579	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3580	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3581	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3582	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3583	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3584	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3585	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3586	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3587	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3588	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3589	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3590	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3591	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3592	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3593	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3594	* @param Break2AFMode This parameter can be one of the following values:
3595	* @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3596	* @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3597	* @retval None
3598	*/
3599	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, uint32_t Break2AFMode)
3600	{
3601	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F \| TIM_BDTR_BK2BID, Break2Polarity \| Break2Filter \| Break2AFMode);
3602	}
3603
3604	/**
3605	* @brief Disarm the break 2 input (when it operates in bidirectional mode).
3606	* @note The break 2 input can be disarmed only when it is configured in
3607	* bidirectional mode and when when MOE is reset.
3608	* @note Purpose is to be able to have the input voltage back to high-state,
3609	* whatever the time constant on the output.
3610	* @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3611	* @param TIMx Timer instance
3612	* @retval None
3613	*/
3614	__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3615	{
3616	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3617	}
3618
3619	/**
3620	* @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3621	* @note The Break 2 input is automatically armed as soon as MOE bit is set.
3622	* @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3623	* @param TIMx Timer instance
3624	* @retval None
3625	*/
3626	__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3627	{
3628	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3629	}
3630
3631	/**
3632	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3633	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3634	* a timer instance provides a break input.
3635	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3636	* BDTR OSSR LL_TIM_SetOffStates
3637	* @param TIMx Timer instance
3638	* @param OffStateIdle This parameter can be one of the following values:
3639	* @arg @ref LL_TIM_OSSI_DISABLE
3640	* @arg @ref LL_TIM_OSSI_ENABLE
3641	* @param OffStateRun This parameter can be one of the following values:
3642	* @arg @ref LL_TIM_OSSR_DISABLE
3643	* @arg @ref LL_TIM_OSSR_ENABLE
3644	* @retval None
3645	*/
3646	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3647	{
3648	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
3649	}
3650
3651	/**
3652	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3653	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3654	* a timer instance provides a break input.
3655	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3656	* @param TIMx Timer instance
3657	* @retval None
3658	*/
3659	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3660	{
3661	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3662	}
3663
3664	/**
3665	* @brief Disable automatic output (MOE can be set only by software).
3666	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3667	* a timer instance provides a break input.
3668	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3669	* @param TIMx Timer instance
3670	* @retval None
3671	*/
3672	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3673	{
3674	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3675	}
3676
3677	/**
3678	* @brief Indicate whether automatic output is enabled.
3679	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3680	* a timer instance provides a break input.
3681	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3682	* @param TIMx Timer instance
3683	* @retval State of bit (1 or 0).
3684	*/
3685	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3686	{
3687	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3688	}
3689
3690	/**
3691	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3692	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3693	* software and is reset in case of break or break2 event
3694	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3695	* a timer instance provides a break input.
3696	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3697	* @param TIMx Timer instance
3698	* @retval None
3699	*/
3700	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3701	{
3702	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3703	}
3704
3705	/**
3706	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3707	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3708	* software and is reset in case of break or break2 event.
3709	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3710	* a timer instance provides a break input.
3711	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3712	* @param TIMx Timer instance
3713	* @retval None
3714	*/
3715	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3716	{
3717	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3718	}
3719
3720	/**
3721	* @brief Indicates whether outputs are enabled.
3722	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3723	* a timer instance provides a break input.
3724	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3725	* @param TIMx Timer instance
3726	* @retval State of bit (1 or 0).
3727	*/
3728	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3729	{
3730	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3731	}
3732
3733	/**
3734	* @brief Enable the signals connected to the designated timer break input.
3735	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3736	* or not a timer instance allows for break input selection.
3737	* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3738	* @if STM32G081xx
3739	* AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3740	* AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3741	* @endif
3742	* AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3743	* @if STM32G081xx
3744	* AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3745	* AF2 BK2CMP2E LL_TIM_EnableBreakInputSource
3746	* @endif
3747	* @param TIMx Timer instance
3748	* @param BreakInput This parameter can be one of the following values:
3749	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
3750	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3751	* @param Source This parameter can be one of the following values:
3752	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3753	* @if STM32G081xx
3754	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3755	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3756	* @endif
3757	* @retval None
3758	*/
3759	__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3760	{
3761	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3762	SET_BIT(*pReg, Source);
3763	}
3764
3765	/**
3766	* @brief Disable the signals connected to the designated timer break input.
3767	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3768	* or not a timer instance allows for break input selection.
3769	* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3770	* @if STM32G081xx
3771	* AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3772	* AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3773	* @endif
3774	* AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3775	* @if STM32G081xx
3776	* AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3777	* AF2 BK2CMP2E LL_TIM_DisableBreakInputSource
3778	* @endif
3779	* @param TIMx Timer instance
3780	* @param BreakInput This parameter can be one of the following values:
3781	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
3782	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3783	* @param Source This parameter can be one of the following values:
3784	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3785	* @if STM32G081xx
3786	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3787	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3788	* @endif
3789	* @retval None
3790	*/
3791	__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3792	{
3793	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3794	CLEAR_BIT(*pReg, Source);
3795	}
3796
3797	/**
3798	* @brief Set the polarity of the break signal for the timer break input.
3799	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3800	* or not a timer instance allows for break input selection.
3801	* @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3802	* @if STM32G081xx
3803	* AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3804	* AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3805	* @endif
3806	* AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3807	* @if STM32G081xx
3808	* AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3809	* AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3810	* @endif
3811	* @param TIMx Timer instance
3812	* @param BreakInput This parameter can be one of the following values:
3813	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
3814	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3815	* @param Source This parameter can be one of the following values:
3816	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3817	* @if STM32G081xx
3818	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3819	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3820	* @endif
3821	* @param Polarity This parameter can be one of the following values:
3822	* @arg @ref LL_TIM_BKIN_POLARITY_LOW
3823	* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3824	* @retval None
3825	*/
3826	__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3827	uint32_t Polarity)
3828	{
3829	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3830	MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE) , (Polarity << TIM_POSITION_BRK_SOURCE));
3831	}
3832	/**
3833	* @}
3834	*/
3835
3836	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3837	* @{
3838	*/
3839	/**
3840	* @brief Configures the timer DMA burst feature.
3841	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3842	* not a timer instance supports the DMA burst mode.
3843	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3844	* DCR DBA LL_TIM_ConfigDMABurst
3845	* @param TIMx Timer instance
3846	* @param DMABurstBaseAddress This parameter can be one of the following values:
3847	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3848	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3849	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3850	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3851	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3852	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3853	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3854	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3855	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3856	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3857	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3858	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3859	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3860	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3861	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3862	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3863	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3864	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3865	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3866	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3867	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3868	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3869	* @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3870	* @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3871	* @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3872	* @param DMABurstLength This parameter can be one of the following values:
3873	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3874	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3875	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3876	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3877	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3878	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3879	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3880	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3881	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3882	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3883	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3884	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3885	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3886	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3887	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3888	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3889	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3890	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3891	* @retval None
3892	*/
3893	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3894	{
3895	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
3896	}
3897
3898	/**
3899	* @}
3900	*/
3901
3902	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3903	* @{
3904	*/
3905	/**
3906	* @brief Remap TIM inputs (input channel, internal/external triggers).
3907	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3908	* a some timer inputs can be remapped.
3909	* @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
3910	* TIM1_TISEL TI2SEL LL_TIM_SetRemap\n
3911	* TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
3912	* TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
3913	* TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
3914	* TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
3915	* TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
3916	* TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
3917	* TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
3918	* TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
3919	* TIM17_TISEL TI1SEL LL_TIM_SetRemap
3920	* @param TIMx Timer instance
3921	* @param Remap Remap param depends on the TIMx. Description available only
3922	* in CHM version of the User Manual (not in .pdf).
3923	* Otherwise see Reference Manual description of TISEL registers.
3924	*
3925	* Below description summarizes "Timer Instance" and "Remap" param combinations:
3926	*
3927	* TIM1: any combination of TI1_RMP and TI2_RMP where
3928	*
3929	* . . TI1_RMP can be one of the following values
3930	* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3931	* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3932	*
3933	* . . TI2_RMP can be one of the following values
3934	* @arg @ref LL_TIM_TIM1_TI2_RMP_GPIO
3935	* @arg @ref LL_TIM_TIM1_TI2_RMP_COMP2
3936	*
3937	* TIM2: any combination of TI1_RMP and TI2_RMP where
3938	*
3939	* . . TI1_RMP can be one of the following values
3940	* @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
3941	* @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
3942	*
3943	* . . TI2_RMP can be one of the following values
3944	* @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
3945	* @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
3946	*
3947	* TIM3: any combination of TI1_RMP and TI2_RMP where
3948	*
3949	* . . TI1_RMP can be one of the following values
3950	* @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3951	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
3952	*
3953	* . . TI2_RMP can be one of the following values
3954	* @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
3955	* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
3956	*
3957	* TIM14: one of the following values
3958	*
3959	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
3960	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
3961	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32
3962	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
3963	*
3964	* TIM15: any combination of TI1_RMP and TI2_RMP where
3965	*
3966	* . . TI1_RMP can be one of the following values
3967	* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3968	* @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1
3969	* @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1
3970	*
3971	* . . TI2_RMP can be one of the following values
3972	* @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
3973	* @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2
3974	* @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2
3975	*
3976	* TIM16: one of the following values
3977	*
3978	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3979	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3980	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3981	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
3982	*
3983	* TIM17: one of the following values
3984	*
3985	* @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3986	* @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3987	* @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3988	*
3989	* @retval None
3990	*/
3991	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3992	{
3993	MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL \| TIM_TISEL_TI2SEL \| TIM_TISEL_TI3SEL \| TIM_TISEL_TI4SEL), Remap);
3994	}
3995
3996	/**
3997	* @}
3998	*/
3999
4000	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4001	* @{
4002	*/
4003	/**
4004	* @brief Set the OCREF clear input source
4005	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4006	* @note This function can only be used in Output compare and PWM modes.
4007	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4008	* @rmtoll OR1 OCREF_CLR LL_TIM_SetOCRefClearInputSource
4009	* @param TIMx Timer instance
4010	* @param OCRefClearInputSource This parameter can be one of the following values:
4011	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4012	* @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
4013	* @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
4014	* @retval None
4015	*/
4016	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4017	{
4018	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
4019	((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
4020	MODIFY_REG(TIMx->OR1, TIM1_OR1_OCREF_CLR, OCRefClearInputSource);
4021	}
4022	/**
4023	* @}
4024	*/
4025
4026	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4027	* @{
4028	*/
4029	/**
4030	* @brief Clear the update interrupt flag (UIF).
4031	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4032	* @param TIMx Timer instance
4033	* @retval None
4034	*/
4035	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4036	{
4037	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4038	}
4039
4040	/**
4041	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4042	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4043	* @param TIMx Timer instance
4044	* @retval State of bit (1 or 0).
4045	*/
4046	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
4047	{
4048	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4049	}
4050
4051	/**
4052	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4053	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4054	* @param TIMx Timer instance
4055	* @retval None
4056	*/
4057	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4058	{
4059	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4060	}
4061
4062	/**
4063	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4064	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4065	* @param TIMx Timer instance
4066	* @retval State of bit (1 or 0).
4067	*/
4068	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
4069	{
4070	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4071	}
4072
4073	/**
4074	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4075	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4076	* @param TIMx Timer instance
4077	* @retval None
4078	*/
4079	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4080	{
4081	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4082	}
4083
4084	/**
4085	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4086	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4087	* @param TIMx Timer instance
4088	* @retval State of bit (1 or 0).
4089	*/
4090	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
4091	{
4092	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4093	}
4094
4095	/**
4096	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4097	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4098	* @param TIMx Timer instance
4099	* @retval None
4100	*/
4101	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4102	{
4103	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4104	}
4105
4106	/**
4107	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4108	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4109	* @param TIMx Timer instance
4110	* @retval State of bit (1 or 0).
4111	*/
4112	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
4113	{
4114	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4115	}
4116
4117	/**
4118	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4119	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4120	* @param TIMx Timer instance
4121	* @retval None
4122	*/
4123	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4124	{
4125	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4126	}
4127
4128	/**
4129	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4130	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4131	* @param TIMx Timer instance
4132	* @retval State of bit (1 or 0).
4133	*/
4134	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
4135	{
4136	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4137	}
4138
4139	/**
4140	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4141	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4142	* @param TIMx Timer instance
4143	* @retval None
4144	*/
4145	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4146	{
4147	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4148	}
4149
4150	/**
4151	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4152	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4153	* @param TIMx Timer instance
4154	* @retval State of bit (1 or 0).
4155	*/
4156	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
4157	{
4158	return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4159	}
4160
4161	/**
4162	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4163	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4164	* @param TIMx Timer instance
4165	* @retval None
4166	*/
4167	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4168	{
4169	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4170	}
4171
4172	/**
4173	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4174	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4175	* @param TIMx Timer instance
4176	* @retval State of bit (1 or 0).
4177	*/
4178	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
4179	{
4180	return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4181	}
4182
4183	/**
4184	* @brief Clear the commutation interrupt flag (COMIF).
4185	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4186	* @param TIMx Timer instance
4187	* @retval None
4188	*/
4189	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4190	{
4191	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4192	}
4193
4194	/**
4195	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4196	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4197	* @param TIMx Timer instance
4198	* @retval State of bit (1 or 0).
4199	*/
4200	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
4201	{
4202	return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4203	}
4204
4205	/**
4206	* @brief Clear the trigger interrupt flag (TIF).
4207	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4208	* @param TIMx Timer instance
4209	* @retval None
4210	*/
4211	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4212	{
4213	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4214	}
4215
4216	/**
4217	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4218	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4219	* @param TIMx Timer instance
4220	* @retval State of bit (1 or 0).
4221	*/
4222	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
4223	{
4224	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4225	}
4226
4227	/**
4228	* @brief Clear the break interrupt flag (BIF).
4229	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4230	* @param TIMx Timer instance
4231	* @retval None
4232	*/
4233	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4234	{
4235	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4236	}
4237
4238	/**
4239	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4240	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4241	* @param TIMx Timer instance
4242	* @retval State of bit (1 or 0).
4243	*/
4244	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
4245	{
4246	return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4247	}
4248
4249	/**
4250	* @brief Clear the break 2 interrupt flag (B2IF).
4251	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4252	* @param TIMx Timer instance
4253	* @retval None
4254	*/
4255	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4256	{
4257	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4258	}
4259
4260	/**
4261	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4262	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4263	* @param TIMx Timer instance
4264	* @retval State of bit (1 or 0).
4265	*/
4266	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
4267	{
4268	return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4269	}
4270
4271	/**
4272	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4273	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4274	* @param TIMx Timer instance
4275	* @retval None
4276	*/
4277	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4278	{
4279	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4280	}
4281
4282	/**
4283	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
4284	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4285	* @param TIMx Timer instance
4286	* @retval State of bit (1 or 0).
4287	*/
4288	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
4289	{
4290	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4291	}
4292
4293	/**
4294	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4295	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4296	* @param TIMx Timer instance
4297	* @retval None
4298	*/
4299	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4300	{
4301	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4302	}
4303
4304	/**
4305	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
4306	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4307	* @param TIMx Timer instance
4308	* @retval State of bit (1 or 0).
4309	*/
4310	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
4311	{
4312	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4313	}
4314
4315	/**
4316	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4317	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4318	* @param TIMx Timer instance
4319	* @retval None
4320	*/
4321	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4322	{
4323	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4324	}
4325
4326	/**
4327	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
4328	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4329	* @param TIMx Timer instance
4330	* @retval State of bit (1 or 0).
4331	*/
4332	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
4333	{
4334	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4335	}
4336
4337	/**
4338	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4339	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4340	* @param TIMx Timer instance
4341	* @retval None
4342	*/
4343	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4344	{
4345	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4346	}
4347
4348	/**
4349	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
4350	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4351	* @param TIMx Timer instance
4352	* @retval State of bit (1 or 0).
4353	*/
4354	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
4355	{
4356	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4357	}
4358
4359	/**
4360	* @brief Clear the system break interrupt flag (SBIF).
4361	* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4362	* @param TIMx Timer instance
4363	* @retval None
4364	*/
4365	__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4366	{
4367	WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4368	}
4369
4370	/**
4371	* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4372	* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4373	* @param TIMx Timer instance
4374	* @retval State of bit (1 or 0).
4375	*/
4376	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
4377	{
4378	return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4379	}
4380
4381	/**
4382	* @}
4383	*/
4384
4385	/** @defgroup TIM_LL_EF_IT_Management IT-Management
4386	* @{
4387	*/
4388	/**
4389	* @brief Enable update interrupt (UIE).
4390	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4391	* @param TIMx Timer instance
4392	* @retval None
4393	*/
4394	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4395	{
4396	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4397	}
4398
4399	/**
4400	* @brief Disable update interrupt (UIE).
4401	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4402	* @param TIMx Timer instance
4403	* @retval None
4404	*/
4405	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4406	{
4407	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4408	}
4409
4410	/**
4411	* @brief Indicates whether the update interrupt (UIE) is enabled.
4412	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4413	* @param TIMx Timer instance
4414	* @retval State of bit (1 or 0).
4415	*/
4416	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4417	{
4418	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4419	}
4420
4421	/**
4422	* @brief Enable capture/compare 1 interrupt (CC1IE).
4423	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4424	* @param TIMx Timer instance
4425	* @retval None
4426	*/
4427	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4428	{
4429	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4430	}
4431
4432	/**
4433	* @brief Disable capture/compare 1 interrupt (CC1IE).
4434	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4435	* @param TIMx Timer instance
4436	* @retval None
4437	*/
4438	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4439	{
4440	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4441	}
4442
4443	/**
4444	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4445	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4446	* @param TIMx Timer instance
4447	* @retval State of bit (1 or 0).
4448	*/
4449	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4450	{
4451	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4452	}
4453
4454	/**
4455	* @brief Enable capture/compare 2 interrupt (CC2IE).
4456	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4457	* @param TIMx Timer instance
4458	* @retval None
4459	*/
4460	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4461	{
4462	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4463	}
4464
4465	/**
4466	* @brief Disable capture/compare 2 interrupt (CC2IE).
4467	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4468	* @param TIMx Timer instance
4469	* @retval None
4470	*/
4471	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4472	{
4473	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4474	}
4475
4476	/**
4477	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4478	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4479	* @param TIMx Timer instance
4480	* @retval State of bit (1 or 0).
4481	*/
4482	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4483	{
4484	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4485	}
4486
4487	/**
4488	* @brief Enable capture/compare 3 interrupt (CC3IE).
4489	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4490	* @param TIMx Timer instance
4491	* @retval None
4492	*/
4493	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4494	{
4495	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4496	}
4497
4498	/**
4499	* @brief Disable capture/compare 3 interrupt (CC3IE).
4500	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4501	* @param TIMx Timer instance
4502	* @retval None
4503	*/
4504	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4505	{
4506	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4507	}
4508
4509	/**
4510	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4511	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4512	* @param TIMx Timer instance
4513	* @retval State of bit (1 or 0).
4514	*/
4515	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4516	{
4517	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4518	}
4519
4520	/**
4521	* @brief Enable capture/compare 4 interrupt (CC4IE).
4522	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4523	* @param TIMx Timer instance
4524	* @retval None
4525	*/
4526	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4527	{
4528	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4529	}
4530
4531	/**
4532	* @brief Disable capture/compare 4 interrupt (CC4IE).
4533	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4534	* @param TIMx Timer instance
4535	* @retval None
4536	*/
4537	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4538	{
4539	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4540	}
4541
4542	/**
4543	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4544	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4545	* @param TIMx Timer instance
4546	* @retval State of bit (1 or 0).
4547	*/
4548	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4549	{
4550	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4551	}
4552
4553	/**
4554	* @brief Enable commutation interrupt (COMIE).
4555	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4556	* @param TIMx Timer instance
4557	* @retval None
4558	*/
4559	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4560	{
4561	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4562	}
4563
4564	/**
4565	* @brief Disable commutation interrupt (COMIE).
4566	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4567	* @param TIMx Timer instance
4568	* @retval None
4569	*/
4570	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4571	{
4572	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4573	}
4574
4575	/**
4576	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4577	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4578	* @param TIMx Timer instance
4579	* @retval State of bit (1 or 0).
4580	*/
4581	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4582	{
4583	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4584	}
4585
4586	/**
4587	* @brief Enable trigger interrupt (TIE).
4588	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4589	* @param TIMx Timer instance
4590	* @retval None
4591	*/
4592	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4593	{
4594	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4595	}
4596
4597	/**
4598	* @brief Disable trigger interrupt (TIE).
4599	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4600	* @param TIMx Timer instance
4601	* @retval None
4602	*/
4603	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4604	{
4605	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4606	}
4607
4608	/**
4609	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
4610	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4611	* @param TIMx Timer instance
4612	* @retval State of bit (1 or 0).
4613	*/
4614	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4615	{
4616	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4617	}
4618
4619	/**
4620	* @brief Enable break interrupt (BIE).
4621	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4622	* @param TIMx Timer instance
4623	* @retval None
4624	*/
4625	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4626	{
4627	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4628	}
4629
4630	/**
4631	* @brief Disable break interrupt (BIE).
4632	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4633	* @param TIMx Timer instance
4634	* @retval None
4635	*/
4636	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4637	{
4638	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4639	}
4640
4641	/**
4642	* @brief Indicates whether the break interrupt (BIE) is enabled.
4643	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4644	* @param TIMx Timer instance
4645	* @retval State of bit (1 or 0).
4646	*/
4647	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4648	{
4649	return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4650	}
4651
4652	/**
4653	* @}
4654	*/
4655
4656	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4657	* @{
4658	*/
4659	/**
4660	* @brief Enable update DMA request (UDE).
4661	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4662	* @param TIMx Timer instance
4663	* @retval None
4664	*/
4665	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4666	{
4667	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4668	}
4669
4670	/**
4671	* @brief Disable update DMA request (UDE).
4672	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4673	* @param TIMx Timer instance
4674	* @retval None
4675	*/
4676	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4677	{
4678	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4679	}
4680
4681	/**
4682	* @brief Indicates whether the update DMA request (UDE) is enabled.
4683	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4684	* @param TIMx Timer instance
4685	* @retval State of bit (1 or 0).
4686	*/
4687	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4688	{
4689	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4690	}
4691
4692	/**
4693	* @brief Enable capture/compare 1 DMA request (CC1DE).
4694	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4695	* @param TIMx Timer instance
4696	* @retval None
4697	*/
4698	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4699	{
4700	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4701	}
4702
4703	/**
4704	* @brief Disable capture/compare 1 DMA request (CC1DE).
4705	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4706	* @param TIMx Timer instance
4707	* @retval None
4708	*/
4709	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4710	{
4711	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4712	}
4713
4714	/**
4715	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4716	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4717	* @param TIMx Timer instance
4718	* @retval State of bit (1 or 0).
4719	*/
4720	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4721	{
4722	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4723	}
4724
4725	/**
4726	* @brief Enable capture/compare 2 DMA request (CC2DE).
4727	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4728	* @param TIMx Timer instance
4729	* @retval None
4730	*/
4731	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4732	{
4733	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4734	}
4735
4736	/**
4737	* @brief Disable capture/compare 2 DMA request (CC2DE).
4738	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4739	* @param TIMx Timer instance
4740	* @retval None
4741	*/
4742	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4743	{
4744	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4745	}
4746
4747	/**
4748	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4749	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4750	* @param TIMx Timer instance
4751	* @retval State of bit (1 or 0).
4752	*/
4753	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4754	{
4755	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4756	}
4757
4758	/**
4759	* @brief Enable capture/compare 3 DMA request (CC3DE).
4760	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4761	* @param TIMx Timer instance
4762	* @retval None
4763	*/
4764	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4765	{
4766	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4767	}
4768
4769	/**
4770	* @brief Disable capture/compare 3 DMA request (CC3DE).
4771	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4772	* @param TIMx Timer instance
4773	* @retval None
4774	*/
4775	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4776	{
4777	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4778	}
4779
4780	/**
4781	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4782	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4783	* @param TIMx Timer instance
4784	* @retval State of bit (1 or 0).
4785	*/
4786	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4787	{
4788	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4789	}
4790
4791	/**
4792	* @brief Enable capture/compare 4 DMA request (CC4DE).
4793	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4794	* @param TIMx Timer instance
4795	* @retval None
4796	*/
4797	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4798	{
4799	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4800	}
4801
4802	/**
4803	* @brief Disable capture/compare 4 DMA request (CC4DE).
4804	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4805	* @param TIMx Timer instance
4806	* @retval None
4807	*/
4808	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4809	{
4810	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4811	}
4812
4813	/**
4814	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4815	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4816	* @param TIMx Timer instance
4817	* @retval State of bit (1 or 0).
4818	*/
4819	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4820	{
4821	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4822	}
4823
4824	/**
4825	* @brief Enable commutation DMA request (COMDE).
4826	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4827	* @param TIMx Timer instance
4828	* @retval None
4829	*/
4830	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4831	{
4832	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4833	}
4834
4835	/**
4836	* @brief Disable commutation DMA request (COMDE).
4837	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4838	* @param TIMx Timer instance
4839	* @retval None
4840	*/
4841	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4842	{
4843	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4844	}
4845
4846	/**
4847	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4848	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4849	* @param TIMx Timer instance
4850	* @retval State of bit (1 or 0).
4851	*/
4852	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4853	{
4854	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4855	}
4856
4857	/**
4858	* @brief Enable trigger interrupt (TDE).
4859	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4860	* @param TIMx Timer instance
4861	* @retval None
4862	*/
4863	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4864	{
4865	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4866	}
4867
4868	/**
4869	* @brief Disable trigger interrupt (TDE).
4870	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4871	* @param TIMx Timer instance
4872	* @retval None
4873	*/
4874	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4875	{
4876	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4877	}
4878
4879	/**
4880	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
4881	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4882	* @param TIMx Timer instance
4883	* @retval State of bit (1 or 0).
4884	*/
4885	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4886	{
4887	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4888	}
4889
4890	/**
4891	* @}
4892	*/
4893
4894	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4895	* @{
4896	*/
4897	/**
4898	* @brief Generate an update event.
4899	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4900	* @param TIMx Timer instance
4901	* @retval None
4902	*/
4903	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4904	{
4905	SET_BIT(TIMx->EGR, TIM_EGR_UG);
4906	}
4907
4908	/**
4909	* @brief Generate Capture/Compare 1 event.
4910	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4911	* @param TIMx Timer instance
4912	* @retval None
4913	*/
4914	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4915	{
4916	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4917	}
4918
4919	/**
4920	* @brief Generate Capture/Compare 2 event.
4921	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4922	* @param TIMx Timer instance
4923	* @retval None
4924	*/
4925	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4926	{
4927	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4928	}
4929
4930	/**
4931	* @brief Generate Capture/Compare 3 event.
4932	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4933	* @param TIMx Timer instance
4934	* @retval None
4935	*/
4936	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4937	{
4938	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4939	}
4940
4941	/**
4942	* @brief Generate Capture/Compare 4 event.
4943	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4944	* @param TIMx Timer instance
4945	* @retval None
4946	*/
4947	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4948	{
4949	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4950	}
4951
4952	/**
4953	* @brief Generate commutation event.
4954	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4955	* @param TIMx Timer instance
4956	* @retval None
4957	*/
4958	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4959	{
4960	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4961	}
4962
4963	/**
4964	* @brief Generate trigger event.
4965	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4966	* @param TIMx Timer instance
4967	* @retval None
4968	*/
4969	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4970	{
4971	SET_BIT(TIMx->EGR, TIM_EGR_TG);
4972	}
4973
4974	/**
4975	* @brief Generate break event.
4976	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4977	* @param TIMx Timer instance
4978	* @retval None
4979	*/
4980	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4981	{
4982	SET_BIT(TIMx->EGR, TIM_EGR_BG);
4983	}
4984
4985	/**
4986	* @brief Generate break 2 event.
4987	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4988	* @param TIMx Timer instance
4989	* @retval None
4990	*/
4991	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4992	{
4993	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4994	}
4995
4996	/**
4997	* @}
4998	*/
4999
5000	#if defined(USE_FULL_LL_DRIVER)
5001	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5002	* @{
5003	*/
5004
5005	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
5006	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5007	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
5008	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5009	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
5010	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5011	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
5012	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5013	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
5014	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5015	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
5016	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5017	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
5018	/**
5019	* @}
5020	*/
5021	#endif /* USE_FULL_LL_DRIVER */
5022
5023	/**
5024	* @}
5025	*/
5026
5027	/**
5028	* @}
5029	*/
5030
5031	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
5032
5033	/**
5034	* @}
5035	*/
5036
5037	#ifdef __cplusplus
5038	}
5039	#endif
5040
5041	#endif /* __STM32G0xx_LL_TIM_H */
5042	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h

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