source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lpuart.h

Last change on this file was 6, checked in by f.jahn, 8 months ago
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1/**
2 ******************************************************************************
3 * @file stm32g0xx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32G0xx_LL_LPUART_H
22#define STM32G0xx_LL_LPUART_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32g0xx.h"
30
31/** @addtogroup STM32G0xx_LL_Driver
32 * @{
33 */
34
35#if defined (LPUART1)
36
37/** @defgroup LPUART_LL LPUART
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
44 * @{
45 */
46/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
47static const uint16_t LPUART_PRESCALER_TAB[] =
48{
49 (uint16_t)1,
50 (uint16_t)2,
51 (uint16_t)4,
52 (uint16_t)6,
53 (uint16_t)8,
54 (uint16_t)10,
55 (uint16_t)12,
56 (uint16_t)16,
57 (uint16_t)32,
58 (uint16_t)64,
59 (uint16_t)128,
60 (uint16_t)256
61};
62/**
63 * @}
64 */
65
66/* Private constants ---------------------------------------------------------*/
67/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
68 * @{
69 */
70/* Defines used in Baud Rate related macros and corresponding register setting computation */
71#define LPUART_LPUARTDIV_FREQ_MUL 256U
72#define LPUART_BRR_MASK 0x000FFFFFU
73#define LPUART_BRR_MIN_VALUE 0x00000300U
74/**
75 * @}
76 */
77
78
79/* Private macros ------------------------------------------------------------*/
80#if defined(USE_FULL_LL_DRIVER)
81/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
82 * @{
83 */
84/**
85 * @}
86 */
87#endif /*USE_FULL_LL_DRIVER*/
88
89/* Exported types ------------------------------------------------------------*/
90#if defined(USE_FULL_LL_DRIVER)
91/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
92 * @{
93 */
94
95/**
96 * @brief LL LPUART Init Structure definition
97 */
98typedef struct
99{
100 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
101 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
102
103 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
104
105 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
106
107 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
108
109 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
110 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
111
112 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
113
114 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
115 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
116
117 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
118
119 uint32_t Parity; /*!< Specifies the parity mode.
120 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
121
122 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
123
124 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
125 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
126
127 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
128
129 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
130 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
131
132 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
133
134} LL_LPUART_InitTypeDef;
135
136/**
137 * @}
138 */
139#endif /* USE_FULL_LL_DRIVER */
140
141/* Exported constants --------------------------------------------------------*/
142/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
143 * @{
144 */
145
146/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
147 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
148 * @{
149 */
150#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
151#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
152#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */
153#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
154#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
155#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
156#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
157#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
158#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
159#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
160/**
161 * @}
162 */
163
164/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
165 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
166 * @{
167 */
168#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
169#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
170#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
171#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
172#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
173#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
174#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
175#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
176#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
177#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
178#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
179#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
180#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
181#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
182#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
183#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
184#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
185#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
186#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
187#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
188#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
189/**
190 * @}
191 */
192
193/** @defgroup LPUART_LL_EC_IT IT Defines
194 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
195 * @{
196 */
197#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
198#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
199#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
200#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
201#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
202#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
203#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
204#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
205#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
206#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
207#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
208#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
209#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
210/**
211 * @}
212 */
213
214/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
215 * @{
216 */
217#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
218#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
219#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
220#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
221#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
222#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
223/**
224 * @}
225 */
226
227/** @defgroup LPUART_LL_EC_DIRECTION Direction
228 * @{
229 */
230#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
231#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
232#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
233#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
234/**
235 * @}
236 */
237
238/** @defgroup LPUART_LL_EC_PARITY Parity Control
239 * @{
240 */
241#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
242#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
243#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
244/**
245 * @}
246 */
247
248/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
249 * @{
250 */
251#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
252#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
253/**
254 * @}
255 */
256
257/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
258 * @{
259 */
260#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
261#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
262#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
263/**
264 * @}
265 */
266
267/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
268 * @{
269 */
270#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
271#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
272#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
273#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
274#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
275#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
276#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
277#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
278#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
279#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
280#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
281#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
282/**
283 * @}
284 */
285
286/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
287 * @{
288 */
289#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
290#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
291/**
292 * @}
293 */
294
295/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
296 * @{
297 */
298#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
299#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
300/**
301 * @}
302 */
303
304/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
305 * @{
306 */
307#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
308#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
309/**
310 * @}
311 */
312
313/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
314 * @{
315 */
316#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
317#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
318/**
319 * @}
320 */
321
322/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
323 * @{
324 */
325#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
326#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
327/**
328 * @}
329 */
330
331/** @defgroup LPUART_LL_EC_BITORDER Bit Order
332 * @{
333 */
334#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
335#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
336/**
337 * @}
338 */
339
340/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
341 * @{
342 */
343#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
344#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
345/**
346 * @}
347 */
348
349/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
350 * @{
351 */
352#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
353#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
354#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
355#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
356/**
357 * @}
358 */
359
360/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
361 * @{
362 */
363#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
364#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
365#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
366/**
367 * @}
368 */
369
370/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
371 * @{
372 */
373#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
374#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
375/**
376 * @}
377 */
378
379/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
380 * @{
381 */
382#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
383#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
384/**
385 * @}
386 */
387
388/**
389 * @}
390 */
391
392/* Exported macro ------------------------------------------------------------*/
393/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
394 * @{
395 */
396
397/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
398 * @{
399 */
400
401/**
402 * @brief Write a value in LPUART register
403 * @param __INSTANCE__ LPUART Instance
404 * @param __REG__ Register to be written
405 * @param __VALUE__ Value to be written in the register
406 * @retval None
407 */
408#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
409
410/**
411 * @brief Read a value in LPUART register
412 * @param __INSTANCE__ LPUART Instance
413 * @param __REG__ Register to be read
414 * @retval Register value
415 */
416#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
417/**
418 * @}
419 */
420
421/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
422 * @{
423 */
424
425/**
426 * @brief Compute LPUARTDIV value according to Peripheral Clock and
427 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
428 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
429 * @param __PRESCALER__ This parameter can be one of the following values:
430 * @arg @ref LL_LPUART_PRESCALER_DIV1
431 * @arg @ref LL_LPUART_PRESCALER_DIV2
432 * @arg @ref LL_LPUART_PRESCALER_DIV4
433 * @arg @ref LL_LPUART_PRESCALER_DIV6
434 * @arg @ref LL_LPUART_PRESCALER_DIV8
435 * @arg @ref LL_LPUART_PRESCALER_DIV10
436 * @arg @ref LL_LPUART_PRESCALER_DIV12
437 * @arg @ref LL_LPUART_PRESCALER_DIV16
438 * @arg @ref LL_LPUART_PRESCALER_DIV32
439 * @arg @ref LL_LPUART_PRESCALER_DIV64
440 * @arg @ref LL_LPUART_PRESCALER_DIV128
441 * @arg @ref LL_LPUART_PRESCALER_DIV256
442 * @param __BAUDRATE__ Baud Rate value to achieve
443 * @retval LPUARTDIV value to be used for BRR register filling
444 */
445#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
446
447/**
448 * @}
449 */
450
451/**
452 * @}
453 */
454
455/* Exported functions --------------------------------------------------------*/
456/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
457 * @{
458 */
459
460/** @defgroup LPUART_LL_EF_Configuration Configuration functions
461 * @{
462 */
463
464/**
465 * @brief LPUART Enable
466 * @rmtoll CR1 UE LL_LPUART_Enable
467 * @param LPUARTx LPUART Instance
468 * @retval None
469 */
470__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
471{
472 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
473}
474
475/**
476 * @brief LPUART Disable
477 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
478 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
479 * flags, in the LPUARTx_ISR are set to their default values.
480 * @note In order to go into low-power mode without generating errors on the line,
481 * the TE bit must be reset before and the software must wait
482 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
483 * The DMA requests are also reset when UE = 0 so the DMA channel must
484 * be disabled before resetting the UE bit.
485 * @rmtoll CR1 UE LL_LPUART_Disable
486 * @param LPUARTx LPUART Instance
487 * @retval None
488 */
489__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
490{
491 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
492}
493
494/**
495 * @brief Indicate if LPUART is enabled
496 * @rmtoll CR1 UE LL_LPUART_IsEnabled
497 * @param LPUARTx LPUART Instance
498 * @retval State of bit (1 or 0).
499 */
500__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
501{
502 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
503}
504
505/**
506 * @brief FIFO Mode Enable
507 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
508 * @param LPUARTx LPUART Instance
509 * @retval None
510 */
511__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
512{
513 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
514}
515
516/**
517 * @brief FIFO Mode Disable
518 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
519 * @param LPUARTx LPUART Instance
520 * @retval None
521 */
522__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
523{
524 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
525}
526
527/**
528 * @brief Indicate if FIFO Mode is enabled
529 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
530 * @param LPUARTx LPUART Instance
531 * @retval State of bit (1 or 0).
532 */
533__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
534{
535 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
536}
537
538/**
539 * @brief Configure TX FIFO Threshold
540 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
541 * @param LPUARTx LPUART Instance
542 * @param Threshold This parameter can be one of the following values:
543 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
544 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
545 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
546 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
547 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
548 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
549 * @retval None
550 */
551__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
552{
553 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
554}
555
556/**
557 * @brief Return TX FIFO Threshold Configuration
558 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
559 * @param LPUARTx LPUART Instance
560 * @retval Returned value can be one of the following values:
561 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
562 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
563 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
564 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
565 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
566 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
567 */
568__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
569{
570 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
571}
572
573/**
574 * @brief Configure RX FIFO Threshold
575 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
576 * @param LPUARTx LPUART Instance
577 * @param Threshold This parameter can be one of the following values:
578 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
579 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
580 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
581 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
582 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
583 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
584 * @retval None
585 */
586__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
587{
588 MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
589}
590
591/**
592 * @brief Return RX FIFO Threshold Configuration
593 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
594 * @param LPUARTx LPUART Instance
595 * @retval Returned value can be one of the following values:
596 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
597 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
598 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
599 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
600 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
601 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
602 */
603__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
604{
605 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
606}
607
608/**
609 * @brief Configure TX and RX FIFOs Threshold
610 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
611 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
612 * @param LPUARTx LPUART Instance
613 * @param TXThreshold This parameter can be one of the following values:
614 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
615 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
616 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
617 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
618 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
619 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
620 * @param RXThreshold This parameter can be one of the following values:
621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
623 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
625 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
626 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
627 * @retval None
628 */
629__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
630{
631 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
632}
633
634/**
635 * @brief LPUART enabled in STOP Mode
636 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
637 * LPUART clock selection is HSI or LSE in RCC.
638 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
639 * @param LPUARTx LPUART Instance
640 * @retval None
641 */
642__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
643{
644 SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
645}
646
647/**
648 * @brief LPUART disabled in STOP Mode
649 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
650 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
651 * @param LPUARTx LPUART Instance
652 * @retval None
653 */
654__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
655{
656 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
657}
658
659/**
660 * @brief Indicate if LPUART is enabled in STOP Mode
661 * (able to wake up MCU from Stop mode or not)
662 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
663 * @param LPUARTx LPUART Instance
664 * @retval State of bit (1 or 0).
665 */
666__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
667{
668 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
669}
670
671/**
672 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
673 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
674 * @param LPUARTx LPUART Instance
675 * @retval None
676 */
677__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
678{
679 SET_BIT(LPUARTx->CR1, USART_CR1_RE);
680}
681
682/**
683 * @brief Receiver Disable
684 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
685 * @param LPUARTx LPUART Instance
686 * @retval None
687 */
688__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
689{
690 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
691}
692
693/**
694 * @brief Transmitter Enable
695 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
696 * @param LPUARTx LPUART Instance
697 * @retval None
698 */
699__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
700{
701 SET_BIT(LPUARTx->CR1, USART_CR1_TE);
702}
703
704/**
705 * @brief Transmitter Disable
706 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
707 * @param LPUARTx LPUART Instance
708 * @retval None
709 */
710__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
711{
712 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
713}
714
715/**
716 * @brief Configure simultaneously enabled/disabled states
717 * of Transmitter and Receiver
718 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
719 * CR1 TE LL_LPUART_SetTransferDirection
720 * @param LPUARTx LPUART Instance
721 * @param TransferDirection This parameter can be one of the following values:
722 * @arg @ref LL_LPUART_DIRECTION_NONE
723 * @arg @ref LL_LPUART_DIRECTION_RX
724 * @arg @ref LL_LPUART_DIRECTION_TX
725 * @arg @ref LL_LPUART_DIRECTION_TX_RX
726 * @retval None
727 */
728__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
729{
730 MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
731}
732
733/**
734 * @brief Return enabled/disabled states of Transmitter and Receiver
735 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
736 * CR1 TE LL_LPUART_GetTransferDirection
737 * @param LPUARTx LPUART Instance
738 * @retval Returned value can be one of the following values:
739 * @arg @ref LL_LPUART_DIRECTION_NONE
740 * @arg @ref LL_LPUART_DIRECTION_RX
741 * @arg @ref LL_LPUART_DIRECTION_TX
742 * @arg @ref LL_LPUART_DIRECTION_TX_RX
743 */
744__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
745{
746 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
747}
748
749/**
750 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
751 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
752 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
753 * (depending on data width) and parity is checked on the received data.
754 * @rmtoll CR1 PS LL_LPUART_SetParity\n
755 * CR1 PCE LL_LPUART_SetParity
756 * @param LPUARTx LPUART Instance
757 * @param Parity This parameter can be one of the following values:
758 * @arg @ref LL_LPUART_PARITY_NONE
759 * @arg @ref LL_LPUART_PARITY_EVEN
760 * @arg @ref LL_LPUART_PARITY_ODD
761 * @retval None
762 */
763__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
764{
765 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
766}
767
768/**
769 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
770 * @rmtoll CR1 PS LL_LPUART_GetParity\n
771 * CR1 PCE LL_LPUART_GetParity
772 * @param LPUARTx LPUART Instance
773 * @retval Returned value can be one of the following values:
774 * @arg @ref LL_LPUART_PARITY_NONE
775 * @arg @ref LL_LPUART_PARITY_EVEN
776 * @arg @ref LL_LPUART_PARITY_ODD
777 */
778__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
779{
780 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
781}
782
783/**
784 * @brief Set Receiver Wake Up method from Mute mode.
785 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
786 * @param LPUARTx LPUART Instance
787 * @param Method This parameter can be one of the following values:
788 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
789 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
790 * @retval None
791 */
792__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
793{
794 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
795}
796
797/**
798 * @brief Return Receiver Wake Up method from Mute mode
799 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
800 * @param LPUARTx LPUART Instance
801 * @retval Returned value can be one of the following values:
802 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
803 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
804 */
805__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
806{
807 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
808}
809
810/**
811 * @brief Set Word length (nb of data bits, excluding start and stop bits)
812 * @rmtoll CR1 M LL_LPUART_SetDataWidth
813 * @param LPUARTx LPUART Instance
814 * @param DataWidth This parameter can be one of the following values:
815 * @arg @ref LL_LPUART_DATAWIDTH_7B
816 * @arg @ref LL_LPUART_DATAWIDTH_8B
817 * @arg @ref LL_LPUART_DATAWIDTH_9B
818 * @retval None
819 */
820__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
821{
822 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
823}
824
825/**
826 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
827 * @rmtoll CR1 M LL_LPUART_GetDataWidth
828 * @param LPUARTx LPUART Instance
829 * @retval Returned value can be one of the following values:
830 * @arg @ref LL_LPUART_DATAWIDTH_7B
831 * @arg @ref LL_LPUART_DATAWIDTH_8B
832 * @arg @ref LL_LPUART_DATAWIDTH_9B
833 */
834__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
835{
836 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
837}
838
839/**
840 * @brief Allow switch between Mute Mode and Active mode
841 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
842 * @param LPUARTx LPUART Instance
843 * @retval None
844 */
845__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
846{
847 SET_BIT(LPUARTx->CR1, USART_CR1_MME);
848}
849
850/**
851 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
852 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
853 * @param LPUARTx LPUART Instance
854 * @retval None
855 */
856__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
857{
858 CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
859}
860
861/**
862 * @brief Indicate if switch between Mute Mode and Active mode is allowed
863 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
864 * @param LPUARTx LPUART Instance
865 * @retval State of bit (1 or 0).
866 */
867__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
868{
869 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
870}
871
872/**
873 * @brief Configure Clock source prescaler for baudrate generator and oversampling
874 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
875 * @param LPUARTx LPUART Instance
876 * @param PrescalerValue This parameter can be one of the following values:
877 * @arg @ref LL_LPUART_PRESCALER_DIV1
878 * @arg @ref LL_LPUART_PRESCALER_DIV2
879 * @arg @ref LL_LPUART_PRESCALER_DIV4
880 * @arg @ref LL_LPUART_PRESCALER_DIV6
881 * @arg @ref LL_LPUART_PRESCALER_DIV8
882 * @arg @ref LL_LPUART_PRESCALER_DIV10
883 * @arg @ref LL_LPUART_PRESCALER_DIV12
884 * @arg @ref LL_LPUART_PRESCALER_DIV16
885 * @arg @ref LL_LPUART_PRESCALER_DIV32
886 * @arg @ref LL_LPUART_PRESCALER_DIV64
887 * @arg @ref LL_LPUART_PRESCALER_DIV128
888 * @arg @ref LL_LPUART_PRESCALER_DIV256
889 * @retval None
890 */
891__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
892{
893 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
894}
895
896/**
897 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
898 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
899 * @param LPUARTx LPUART Instance
900 * @retval Returned value can be one of the following values:
901 * @arg @ref LL_LPUART_PRESCALER_DIV1
902 * @arg @ref LL_LPUART_PRESCALER_DIV2
903 * @arg @ref LL_LPUART_PRESCALER_DIV4
904 * @arg @ref LL_LPUART_PRESCALER_DIV6
905 * @arg @ref LL_LPUART_PRESCALER_DIV8
906 * @arg @ref LL_LPUART_PRESCALER_DIV10
907 * @arg @ref LL_LPUART_PRESCALER_DIV12
908 * @arg @ref LL_LPUART_PRESCALER_DIV16
909 * @arg @ref LL_LPUART_PRESCALER_DIV32
910 * @arg @ref LL_LPUART_PRESCALER_DIV64
911 * @arg @ref LL_LPUART_PRESCALER_DIV128
912 * @arg @ref LL_LPUART_PRESCALER_DIV256
913 */
914__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
915{
916 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
917}
918
919/**
920 * @brief Set the length of the stop bits
921 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
922 * @param LPUARTx LPUART Instance
923 * @param StopBits This parameter can be one of the following values:
924 * @arg @ref LL_LPUART_STOPBITS_1
925 * @arg @ref LL_LPUART_STOPBITS_2
926 * @retval None
927 */
928__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
929{
930 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
931}
932
933/**
934 * @brief Retrieve the length of the stop bits
935 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
936 * @param LPUARTx LPUART Instance
937 * @retval Returned value can be one of the following values:
938 * @arg @ref LL_LPUART_STOPBITS_1
939 * @arg @ref LL_LPUART_STOPBITS_2
940 */
941__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
942{
943 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
944}
945
946/**
947 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
948 * @note Call of this function is equivalent to following function call sequence :
949 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
950 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
951 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
952 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
953 * CR1 PCE LL_LPUART_ConfigCharacter\n
954 * CR1 M LL_LPUART_ConfigCharacter\n
955 * CR2 STOP LL_LPUART_ConfigCharacter
956 * @param LPUARTx LPUART Instance
957 * @param DataWidth This parameter can be one of the following values:
958 * @arg @ref LL_LPUART_DATAWIDTH_7B
959 * @arg @ref LL_LPUART_DATAWIDTH_8B
960 * @arg @ref LL_LPUART_DATAWIDTH_9B
961 * @param Parity This parameter can be one of the following values:
962 * @arg @ref LL_LPUART_PARITY_NONE
963 * @arg @ref LL_LPUART_PARITY_EVEN
964 * @arg @ref LL_LPUART_PARITY_ODD
965 * @param StopBits This parameter can be one of the following values:
966 * @arg @ref LL_LPUART_STOPBITS_1
967 * @arg @ref LL_LPUART_STOPBITS_2
968 * @retval None
969 */
970__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
971 uint32_t StopBits)
972{
973 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
974 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
975}
976
977/**
978 * @brief Configure TX/RX pins swapping setting.
979 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
980 * @param LPUARTx LPUART Instance
981 * @param SwapConfig This parameter can be one of the following values:
982 * @arg @ref LL_LPUART_TXRX_STANDARD
983 * @arg @ref LL_LPUART_TXRX_SWAPPED
984 * @retval None
985 */
986__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
987{
988 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
989}
990
991/**
992 * @brief Retrieve TX/RX pins swapping configuration.
993 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
994 * @param LPUARTx LPUART Instance
995 * @retval Returned value can be one of the following values:
996 * @arg @ref LL_LPUART_TXRX_STANDARD
997 * @arg @ref LL_LPUART_TXRX_SWAPPED
998 */
999__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
1000{
1001 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1002}
1003
1004/**
1005 * @brief Configure RX pin active level logic
1006 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1007 * @param LPUARTx LPUART Instance
1008 * @param PinInvMethod This parameter can be one of the following values:
1009 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1010 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1011 * @retval None
1012 */
1013__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1014{
1015 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1016}
1017
1018/**
1019 * @brief Retrieve RX pin active level logic configuration
1020 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1021 * @param LPUARTx LPUART Instance
1022 * @retval Returned value can be one of the following values:
1023 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1024 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1025 */
1026__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
1027{
1028 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1029}
1030
1031/**
1032 * @brief Configure TX pin active level logic
1033 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1034 * @param LPUARTx LPUART Instance
1035 * @param PinInvMethod This parameter can be one of the following values:
1036 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1037 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1038 * @retval None
1039 */
1040__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1041{
1042 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1043}
1044
1045/**
1046 * @brief Retrieve TX pin active level logic configuration
1047 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1048 * @param LPUARTx LPUART Instance
1049 * @retval Returned value can be one of the following values:
1050 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1051 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1052 */
1053__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
1054{
1055 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1056}
1057
1058/**
1059 * @brief Configure Binary data logic.
1060 *
1061 * @note Allow to define how Logical data from the data register are send/received :
1062 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1063 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1064 * @param LPUARTx LPUART Instance
1065 * @param DataLogic This parameter can be one of the following values:
1066 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1067 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1068 * @retval None
1069 */
1070__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1071{
1072 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1073}
1074
1075/**
1076 * @brief Retrieve Binary data configuration
1077 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1078 * @param LPUARTx LPUART Instance
1079 * @retval Returned value can be one of the following values:
1080 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1081 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1082 */
1083__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
1084{
1085 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1086}
1087
1088/**
1089 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1090 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1091 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1092 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1093 * @param LPUARTx LPUART Instance
1094 * @param BitOrder This parameter can be one of the following values:
1095 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1096 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1097 * @retval None
1098 */
1099__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1100{
1101 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1102}
1103
1104/**
1105 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1106 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1107 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1108 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1109 * @param LPUARTx LPUART Instance
1110 * @retval Returned value can be one of the following values:
1111 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1112 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1113 */
1114__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
1115{
1116 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1117}
1118
1119/**
1120 * @brief Set Address of the LPUART node.
1121 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1122 * for wake up with address mark detection.
1123 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1124 * (b7-b4 should be set to 0)
1125 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1126 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1127 * for wake up with 7-bit address mark detection.
1128 * The MSB of the character sent by the transmitter should be equal to 1.
1129 * It may also be used for character detection during normal reception,
1130 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1131 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1132 * value and CMF flag is set on match)
1133 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1134 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1135 * @param LPUARTx LPUART Instance
1136 * @param AddressLen This parameter can be one of the following values:
1137 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1138 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1139 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1140 * @retval None
1141 */
1142__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1143{
1144 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1145 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1146}
1147
1148/**
1149 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1150 * @note If 4-bit Address Detection is selected in ADDM7,
1151 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1152 * If 7-bit Address Detection is selected in ADDM7,
1153 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1154 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1155 * @param LPUARTx LPUART Instance
1156 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1157 */
1158__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
1159{
1160 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1161}
1162
1163/**
1164 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1165 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1166 * @param LPUARTx LPUART Instance
1167 * @retval Returned value can be one of the following values:
1168 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1169 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1170 */
1171__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
1172{
1173 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1174}
1175
1176/**
1177 * @brief Enable RTS HW Flow Control
1178 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1179 * @param LPUARTx LPUART Instance
1180 * @retval None
1181 */
1182__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1183{
1184 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1185}
1186
1187/**
1188 * @brief Disable RTS HW Flow Control
1189 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1190 * @param LPUARTx LPUART Instance
1191 * @retval None
1192 */
1193__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1194{
1195 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1196}
1197
1198/**
1199 * @brief Enable CTS HW Flow Control
1200 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1201 * @param LPUARTx LPUART Instance
1202 * @retval None
1203 */
1204__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1205{
1206 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1207}
1208
1209/**
1210 * @brief Disable CTS HW Flow Control
1211 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1212 * @param LPUARTx LPUART Instance
1213 * @retval None
1214 */
1215__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1216{
1217 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1218}
1219
1220/**
1221 * @brief Configure HW Flow Control mode (both CTS and RTS)
1222 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1223 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1224 * @param LPUARTx LPUART Instance
1225 * @param HardwareFlowControl This parameter can be one of the following values:
1226 * @arg @ref LL_LPUART_HWCONTROL_NONE
1227 * @arg @ref LL_LPUART_HWCONTROL_RTS
1228 * @arg @ref LL_LPUART_HWCONTROL_CTS
1229 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1230 * @retval None
1231 */
1232__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1233{
1234 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1235}
1236
1237/**
1238 * @brief Return HW Flow Control configuration (both CTS and RTS)
1239 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1240 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1241 * @param LPUARTx LPUART Instance
1242 * @retval Returned value can be one of the following values:
1243 * @arg @ref LL_LPUART_HWCONTROL_NONE
1244 * @arg @ref LL_LPUART_HWCONTROL_RTS
1245 * @arg @ref LL_LPUART_HWCONTROL_CTS
1246 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1247 */
1248__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
1249{
1250 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1251}
1252
1253/**
1254 * @brief Enable Overrun detection
1255 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1256 * @param LPUARTx LPUART Instance
1257 * @retval None
1258 */
1259__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1260{
1261 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1262}
1263
1264/**
1265 * @brief Disable Overrun detection
1266 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1267 * @param LPUARTx LPUART Instance
1268 * @retval None
1269 */
1270__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1271{
1272 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1273}
1274
1275/**
1276 * @brief Indicate if Overrun detection is enabled
1277 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1278 * @param LPUARTx LPUART Instance
1279 * @retval State of bit (1 or 0).
1280 */
1281__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
1282{
1283 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1284}
1285
1286/**
1287 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1288 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1289 * @param LPUARTx LPUART Instance
1290 * @param Type This parameter can be one of the following values:
1291 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1292 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1293 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1294 * @retval None
1295 */
1296__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1297{
1298 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1299}
1300
1301/**
1302 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1303 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1304 * @param LPUARTx LPUART Instance
1305 * @retval Returned value can be one of the following values:
1306 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1307 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1308 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1309 */
1310__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
1311{
1312 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1313}
1314
1315/**
1316 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1317 *
1318 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1319 * according to used Peripheral Clock and expected Baud Rate values
1320 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1321 * (Baud rate value != 0).
1322 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1323 * a care should be taken when generating high baud rates using high PeriphClk
1324 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1325 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1326 * @param LPUARTx LPUART Instance
1327 * @param PeriphClk Peripheral Clock
1328 * @param PrescalerValue This parameter can be one of the following values:
1329 * @arg @ref LL_LPUART_PRESCALER_DIV1
1330 * @arg @ref LL_LPUART_PRESCALER_DIV2
1331 * @arg @ref LL_LPUART_PRESCALER_DIV4
1332 * @arg @ref LL_LPUART_PRESCALER_DIV6
1333 * @arg @ref LL_LPUART_PRESCALER_DIV8
1334 * @arg @ref LL_LPUART_PRESCALER_DIV10
1335 * @arg @ref LL_LPUART_PRESCALER_DIV12
1336 * @arg @ref LL_LPUART_PRESCALER_DIV16
1337 * @arg @ref LL_LPUART_PRESCALER_DIV32
1338 * @arg @ref LL_LPUART_PRESCALER_DIV64
1339 * @arg @ref LL_LPUART_PRESCALER_DIV128
1340 * @arg @ref LL_LPUART_PRESCALER_DIV256
1341 * @param BaudRate Baud Rate
1342 * @retval None
1343 */
1344__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
1345{
1346 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1347}
1348
1349/**
1350 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1351 * (full BRR content), and to used Peripheral Clock values
1352 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1353 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1354 * @param LPUARTx LPUART Instance
1355 * @param PeriphClk Peripheral Clock
1356 * @param PrescalerValue This parameter can be one of the following values:
1357 * @arg @ref LL_LPUART_PRESCALER_DIV1
1358 * @arg @ref LL_LPUART_PRESCALER_DIV2
1359 * @arg @ref LL_LPUART_PRESCALER_DIV4
1360 * @arg @ref LL_LPUART_PRESCALER_DIV6
1361 * @arg @ref LL_LPUART_PRESCALER_DIV8
1362 * @arg @ref LL_LPUART_PRESCALER_DIV10
1363 * @arg @ref LL_LPUART_PRESCALER_DIV12
1364 * @arg @ref LL_LPUART_PRESCALER_DIV16
1365 * @arg @ref LL_LPUART_PRESCALER_DIV32
1366 * @arg @ref LL_LPUART_PRESCALER_DIV64
1367 * @arg @ref LL_LPUART_PRESCALER_DIV128
1368 * @arg @ref LL_LPUART_PRESCALER_DIV256
1369 * @retval Baud Rate
1370 */
1371__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
1372{
1373 register uint32_t lpuartdiv;
1374 register uint32_t brrresult;
1375 register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1376
1377 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1378
1379 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1380 {
1381 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1382 }
1383 else
1384 {
1385 brrresult = 0x0UL;
1386 }
1387
1388 return (brrresult);
1389}
1390
1391/**
1392 * @}
1393 */
1394
1395/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1396 * @{
1397 */
1398
1399/**
1400 * @brief Enable Single Wire Half-Duplex mode
1401 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1402 * @param LPUARTx LPUART Instance
1403 * @retval None
1404 */
1405__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1406{
1407 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1408}
1409
1410/**
1411 * @brief Disable Single Wire Half-Duplex mode
1412 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1413 * @param LPUARTx LPUART Instance
1414 * @retval None
1415 */
1416__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1417{
1418 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1419}
1420
1421/**
1422 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1423 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1424 * @param LPUARTx LPUART Instance
1425 * @retval State of bit (1 or 0).
1426 */
1427__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
1428{
1429 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1430}
1431
1432/**
1433 * @}
1434 */
1435
1436/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1437 * @{
1438 */
1439
1440/**
1441 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1442 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1443 * @param LPUARTx LPUART Instance
1444 * @param Time Value between Min_Data=0 and Max_Data=31
1445 * @retval None
1446 */
1447__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1448{
1449 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1450}
1451
1452/**
1453 * @brief Return DEDT (Driver Enable De-Assertion Time)
1454 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1455 * @param LPUARTx LPUART Instance
1456 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1457 */
1458__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
1459{
1460 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1461}
1462
1463/**
1464 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1465 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1466 * @param LPUARTx LPUART Instance
1467 * @param Time Value between Min_Data=0 and Max_Data=31
1468 * @retval None
1469 */
1470__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1471{
1472 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1473}
1474
1475/**
1476 * @brief Return DEAT (Driver Enable Assertion Time)
1477 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1478 * @param LPUARTx LPUART Instance
1479 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1480 */
1481__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
1482{
1483 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1484}
1485
1486/**
1487 * @brief Enable Driver Enable (DE) Mode
1488 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1489 * @param LPUARTx LPUART Instance
1490 * @retval None
1491 */
1492__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1493{
1494 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1495}
1496
1497/**
1498 * @brief Disable Driver Enable (DE) Mode
1499 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1500 * @param LPUARTx LPUART Instance
1501 * @retval None
1502 */
1503__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1504{
1505 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1506}
1507
1508/**
1509 * @brief Indicate if Driver Enable (DE) Mode is enabled
1510 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1511 * @param LPUARTx LPUART Instance
1512 * @retval State of bit (1 or 0).
1513 */
1514__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
1515{
1516 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1517}
1518
1519/**
1520 * @brief Select Driver Enable Polarity
1521 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1522 * @param LPUARTx LPUART Instance
1523 * @param Polarity This parameter can be one of the following values:
1524 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1525 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1526 * @retval None
1527 */
1528__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1529{
1530 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1531}
1532
1533/**
1534 * @brief Return Driver Enable Polarity
1535 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1536 * @param LPUARTx LPUART Instance
1537 * @retval Returned value can be one of the following values:
1538 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1539 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1540 */
1541__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
1542{
1543 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1544}
1545
1546/**
1547 * @}
1548 */
1549
1550/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1551 * @{
1552 */
1553
1554/**
1555 * @brief Check if the LPUART Parity Error Flag is set or not
1556 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1557 * @param LPUARTx LPUART Instance
1558 * @retval State of bit (1 or 0).
1559 */
1560__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
1561{
1562 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1563}
1564
1565/**
1566 * @brief Check if the LPUART Framing Error Flag is set or not
1567 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1568 * @param LPUARTx LPUART Instance
1569 * @retval State of bit (1 or 0).
1570 */
1571__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
1572{
1573 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1574}
1575
1576/**
1577 * @brief Check if the LPUART Noise error detected Flag is set or not
1578 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1579 * @param LPUARTx LPUART Instance
1580 * @retval State of bit (1 or 0).
1581 */
1582__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
1583{
1584 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1585}
1586
1587/**
1588 * @brief Check if the LPUART OverRun Error Flag is set or not
1589 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1590 * @param LPUARTx LPUART Instance
1591 * @retval State of bit (1 or 0).
1592 */
1593__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
1594{
1595 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1596}
1597
1598/**
1599 * @brief Check if the LPUART IDLE line detected Flag is set or not
1600 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1601 * @param LPUARTx LPUART Instance
1602 * @retval State of bit (1 or 0).
1603 */
1604__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
1605{
1606 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1607}
1608
1609/* Legacy define */
1610#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1611
1612/**
1613 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1614 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1615 * @param LPUARTx LPUART Instance
1616 * @retval State of bit (1 or 0).
1617 */
1618__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1619{
1620 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1621}
1622
1623/**
1624 * @brief Check if the LPUART Transmission Complete Flag is set or not
1625 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1626 * @param LPUARTx LPUART Instance
1627 * @retval State of bit (1 or 0).
1628 */
1629__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
1630{
1631 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1632}
1633
1634/* Legacy define */
1635#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
1636
1637/**
1638 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1639 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1640 * @param LPUARTx LPUART Instance
1641 * @retval State of bit (1 or 0).
1642 */
1643__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
1644{
1645 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1646}
1647
1648/**
1649 * @brief Check if the LPUART CTS interrupt Flag is set or not
1650 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1651 * @param LPUARTx LPUART Instance
1652 * @retval State of bit (1 or 0).
1653 */
1654__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
1655{
1656 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1657}
1658
1659/**
1660 * @brief Check if the LPUART CTS Flag is set or not
1661 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1662 * @param LPUARTx LPUART Instance
1663 * @retval State of bit (1 or 0).
1664 */
1665__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
1666{
1667 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1668}
1669
1670/**
1671 * @brief Check if the LPUART Busy Flag is set or not
1672 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1673 * @param LPUARTx LPUART Instance
1674 * @retval State of bit (1 or 0).
1675 */
1676__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
1677{
1678 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1679}
1680
1681/**
1682 * @brief Check if the LPUART Character Match Flag is set or not
1683 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1684 * @param LPUARTx LPUART Instance
1685 * @retval State of bit (1 or 0).
1686 */
1687__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
1688{
1689 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1690}
1691
1692/**
1693 * @brief Check if the LPUART Send Break Flag is set or not
1694 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1695 * @param LPUARTx LPUART Instance
1696 * @retval State of bit (1 or 0).
1697 */
1698__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
1699{
1700 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1701}
1702
1703/**
1704 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1705 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1706 * @param LPUARTx LPUART Instance
1707 * @retval State of bit (1 or 0).
1708 */
1709__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
1710{
1711 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1712}
1713
1714/**
1715 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1716 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1717 * @param LPUARTx LPUART Instance
1718 * @retval State of bit (1 or 0).
1719 */
1720__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
1721{
1722 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1723}
1724
1725/**
1726 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1727 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1728 * @param LPUARTx LPUART Instance
1729 * @retval State of bit (1 or 0).
1730 */
1731__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
1732{
1733 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1734}
1735
1736/**
1737 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1738 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1739 * @param LPUARTx LPUART Instance
1740 * @retval State of bit (1 or 0).
1741 */
1742__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
1743{
1744 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1745}
1746
1747/**
1748 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1749 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1750 * @param LPUARTx LPUART Instance
1751 * @retval State of bit (1 or 0).
1752 */
1753__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
1754{
1755 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1756}
1757
1758/**
1759 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1760 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1761 * @param LPUARTx LPUART Instance
1762 * @retval State of bit (1 or 0).
1763 */
1764__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
1765{
1766 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1767}
1768
1769/**
1770 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1771 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1772 * @param LPUARTx LPUART Instance
1773 * @retval State of bit (1 or 0).
1774 */
1775__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
1776{
1777 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1778}
1779
1780/**
1781 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1782 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1783 * @param LPUARTx LPUART Instance
1784 * @retval State of bit (1 or 0).
1785 */
1786__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
1787{
1788 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1789}
1790
1791/**
1792 * @brief Clear Parity Error Flag
1793 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1794 * @param LPUARTx LPUART Instance
1795 * @retval None
1796 */
1797__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1798{
1799 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1800}
1801
1802/**
1803 * @brief Clear Framing Error Flag
1804 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1805 * @param LPUARTx LPUART Instance
1806 * @retval None
1807 */
1808__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1809{
1810 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1811}
1812
1813/**
1814 * @brief Clear Noise detected Flag
1815 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1816 * @param LPUARTx LPUART Instance
1817 * @retval None
1818 */
1819__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1820{
1821 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1822}
1823
1824/**
1825 * @brief Clear OverRun Error Flag
1826 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1827 * @param LPUARTx LPUART Instance
1828 * @retval None
1829 */
1830__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1831{
1832 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1833}
1834
1835/**
1836 * @brief Clear IDLE line detected Flag
1837 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1838 * @param LPUARTx LPUART Instance
1839 * @retval None
1840 */
1841__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1842{
1843 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1844}
1845
1846/**
1847 * @brief Clear TX FIFO Empty Flag
1848 * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
1849 * @param LPUARTx LPUART Instance
1850 * @retval None
1851 */
1852__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
1853{
1854 WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
1855}
1856
1857/**
1858 * @brief Clear Transmission Complete Flag
1859 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1860 * @param LPUARTx LPUART Instance
1861 * @retval None
1862 */
1863__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1864{
1865 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1866}
1867
1868/**
1869 * @brief Clear CTS Interrupt Flag
1870 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1871 * @param LPUARTx LPUART Instance
1872 * @retval None
1873 */
1874__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1875{
1876 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1877}
1878
1879/**
1880 * @brief Clear Character Match Flag
1881 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1882 * @param LPUARTx LPUART Instance
1883 * @retval None
1884 */
1885__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1886{
1887 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1888}
1889
1890/**
1891 * @brief Clear Wake Up from stop mode Flag
1892 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
1893 * @param LPUARTx LPUART Instance
1894 * @retval None
1895 */
1896__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1897{
1898 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1899}
1900
1901/**
1902 * @}
1903 */
1904
1905/** @defgroup LPUART_LL_EF_IT_Management IT_Management
1906 * @{
1907 */
1908
1909/**
1910 * @brief Enable IDLE Interrupt
1911 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1912 * @param LPUARTx LPUART Instance
1913 * @retval None
1914 */
1915__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1916{
1917 SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1918}
1919
1920/* Legacy define */
1921#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
1922
1923/**
1924 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1925 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1926 * @param LPUARTx LPUART Instance
1927 * @retval None
1928 */
1929__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1930{
1931 SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1932}
1933
1934/**
1935 * @brief Enable Transmission Complete Interrupt
1936 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1937 * @param LPUARTx LPUART Instance
1938 * @retval None
1939 */
1940__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1941{
1942 SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1943}
1944
1945/* Legacy define */
1946#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
1947
1948/**
1949 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1950 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1951 * @param LPUARTx LPUART Instance
1952 * @retval None
1953 */
1954__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1955{
1956 SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1957}
1958
1959/**
1960 * @brief Enable Parity Error Interrupt
1961 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1962 * @param LPUARTx LPUART Instance
1963 * @retval None
1964 */
1965__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1966{
1967 SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1968}
1969
1970/**
1971 * @brief Enable Character Match Interrupt
1972 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1973 * @param LPUARTx LPUART Instance
1974 * @retval None
1975 */
1976__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1977{
1978 SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1979}
1980
1981/**
1982 * @brief Enable TX FIFO Empty Interrupt
1983 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
1984 * @param LPUARTx LPUART Instance
1985 * @retval None
1986 */
1987__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
1988{
1989 SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
1990}
1991
1992/**
1993 * @brief Enable RX FIFO Full Interrupt
1994 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
1995 * @param LPUARTx LPUART Instance
1996 * @retval None
1997 */
1998__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
1999{
2000 SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2001}
2002
2003/**
2004 * @brief Enable Error Interrupt
2005 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2006 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2007 * - 0: Interrupt is inhibited
2008 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2009 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2010 * @param LPUARTx LPUART Instance
2011 * @retval None
2012 */
2013__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2014{
2015 SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2016}
2017
2018/**
2019 * @brief Enable CTS Interrupt
2020 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2021 * @param LPUARTx LPUART Instance
2022 * @retval None
2023 */
2024__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2025{
2026 SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2027}
2028
2029/**
2030 * @brief Enable Wake Up from Stop Mode Interrupt
2031 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2032 * @param LPUARTx LPUART Instance
2033 * @retval None
2034 */
2035__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2036{
2037 SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2038}
2039
2040/**
2041 * @brief Enable TX FIFO Threshold Interrupt
2042 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2043 * @param LPUARTx LPUART Instance
2044 * @retval None
2045 */
2046__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2047{
2048 SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2049}
2050
2051/**
2052 * @brief Enable RX FIFO Threshold Interrupt
2053 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2054 * @param LPUARTx LPUART Instance
2055 * @retval None
2056 */
2057__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2058{
2059 SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2060}
2061
2062/**
2063 * @brief Disable IDLE Interrupt
2064 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2065 * @param LPUARTx LPUART Instance
2066 * @retval None
2067 */
2068__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2069{
2070 CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2071}
2072
2073/* Legacy define */
2074#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
2075
2076/**
2077 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2078 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2079 * @param LPUARTx LPUART Instance
2080 * @retval None
2081 */
2082__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2083{
2084 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2085}
2086
2087/**
2088 * @brief Disable Transmission Complete Interrupt
2089 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2090 * @param LPUARTx LPUART Instance
2091 * @retval None
2092 */
2093__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2094{
2095 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2096}
2097
2098/* Legacy define */
2099#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
2100
2101/**
2102 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2103 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2104 * @param LPUARTx LPUART Instance
2105 * @retval None
2106 */
2107__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2108{
2109 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2110}
2111
2112/**
2113 * @brief Disable Parity Error Interrupt
2114 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2115 * @param LPUARTx LPUART Instance
2116 * @retval None
2117 */
2118__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2119{
2120 CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2121}
2122
2123/**
2124 * @brief Disable Character Match Interrupt
2125 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2126 * @param LPUARTx LPUART Instance
2127 * @retval None
2128 */
2129__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2130{
2131 CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2132}
2133
2134/**
2135 * @brief Disable TX FIFO Empty Interrupt
2136 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2137 * @param LPUARTx LPUART Instance
2138 * @retval None
2139 */
2140__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2141{
2142 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2143}
2144
2145/**
2146 * @brief Disable RX FIFO Full Interrupt
2147 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2148 * @param LPUARTx LPUART Instance
2149 * @retval None
2150 */
2151__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2152{
2153 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2154}
2155
2156/**
2157 * @brief Disable Error Interrupt
2158 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2159 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2160 * - 0: Interrupt is inhibited
2161 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2162 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2163 * @param LPUARTx LPUART Instance
2164 * @retval None
2165 */
2166__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2167{
2168 CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2169}
2170
2171/**
2172 * @brief Disable CTS Interrupt
2173 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2174 * @param LPUARTx LPUART Instance
2175 * @retval None
2176 */
2177__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2178{
2179 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2180}
2181
2182/**
2183 * @brief Disable Wake Up from Stop Mode Interrupt
2184 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2185 * @param LPUARTx LPUART Instance
2186 * @retval None
2187 */
2188__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2189{
2190 CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2191}
2192
2193/**
2194 * @brief Disable TX FIFO Threshold Interrupt
2195 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2196 * @param LPUARTx LPUART Instance
2197 * @retval None
2198 */
2199__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2200{
2201 CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2202}
2203
2204/**
2205 * @brief Disable RX FIFO Threshold Interrupt
2206 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2207 * @param LPUARTx LPUART Instance
2208 * @retval None
2209 */
2210__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2211{
2212 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2213}
2214
2215/**
2216 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2217 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2218 * @param LPUARTx LPUART Instance
2219 * @retval State of bit (1 or 0).
2220 */
2221__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
2222{
2223 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2224}
2225
2226/* Legacy define */
2227#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2228
2229/**
2230 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2231 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2232 * @param LPUARTx LPUART Instance
2233 * @retval State of bit (1 or 0).
2234 */
2235__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2236{
2237 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2238}
2239
2240/**
2241 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2242 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2243 * @param LPUARTx LPUART Instance
2244 * @retval State of bit (1 or 0).
2245 */
2246__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
2247{
2248 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2249}
2250
2251/* Legacy define */
2252#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
2253
2254/**
2255 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2256 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2257 * @param LPUARTx LPUART Instance
2258 * @retval State of bit (1 or 0).
2259 */
2260__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2261{
2262 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2263}
2264
2265/**
2266 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2267 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2268 * @param LPUARTx LPUART Instance
2269 * @retval State of bit (1 or 0).
2270 */
2271__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
2272{
2273 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2274}
2275
2276/**
2277 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2278 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2279 * @param LPUARTx LPUART Instance
2280 * @retval State of bit (1 or 0).
2281 */
2282__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
2283{
2284 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2285}
2286
2287/**
2288 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2289 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2290 * @param LPUARTx LPUART Instance
2291 * @retval State of bit (1 or 0).
2292 */
2293__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
2294{
2295 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2296}
2297
2298/**
2299 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2300 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2301 * @param LPUARTx LPUART Instance
2302 * @retval State of bit (1 or 0).
2303 */
2304__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
2305{
2306 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2307}
2308
2309/**
2310 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2311 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2312 * @param LPUARTx LPUART Instance
2313 * @retval State of bit (1 or 0).
2314 */
2315__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
2316{
2317 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2318}
2319
2320/**
2321 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2322 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2323 * @param LPUARTx LPUART Instance
2324 * @retval State of bit (1 or 0).
2325 */
2326__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
2327{
2328 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2329}
2330
2331/**
2332 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2333 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2334 * @param LPUARTx LPUART Instance
2335 * @retval State of bit (1 or 0).
2336 */
2337__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
2338{
2339 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2340}
2341
2342/**
2343 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2344 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2345 * @param LPUARTx LPUART Instance
2346 * @retval State of bit (1 or 0).
2347 */
2348__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
2349{
2350 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2351}
2352
2353/**
2354 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2355 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2356 * @param LPUARTx LPUART Instance
2357 * @retval State of bit (1 or 0).
2358 */
2359__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
2360{
2361 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2362}
2363
2364/**
2365 * @}
2366 */
2367
2368/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2369 * @{
2370 */
2371
2372/**
2373 * @brief Enable DMA Mode for reception
2374 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2375 * @param LPUARTx LPUART Instance
2376 * @retval None
2377 */
2378__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2379{
2380 SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2381}
2382
2383/**
2384 * @brief Disable DMA Mode for reception
2385 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2386 * @param LPUARTx LPUART Instance
2387 * @retval None
2388 */
2389__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2390{
2391 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2392}
2393
2394/**
2395 * @brief Check if DMA Mode is enabled for reception
2396 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2397 * @param LPUARTx LPUART Instance
2398 * @retval State of bit (1 or 0).
2399 */
2400__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
2401{
2402 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2403}
2404
2405/**
2406 * @brief Enable DMA Mode for transmission
2407 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2408 * @param LPUARTx LPUART Instance
2409 * @retval None
2410 */
2411__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2412{
2413 SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2414}
2415
2416/**
2417 * @brief Disable DMA Mode for transmission
2418 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2419 * @param LPUARTx LPUART Instance
2420 * @retval None
2421 */
2422__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2423{
2424 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2425}
2426
2427/**
2428 * @brief Check if DMA Mode is enabled for transmission
2429 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2430 * @param LPUARTx LPUART Instance
2431 * @retval State of bit (1 or 0).
2432 */
2433__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
2434{
2435 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2436}
2437
2438/**
2439 * @brief Enable DMA Disabling on Reception Error
2440 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2441 * @param LPUARTx LPUART Instance
2442 * @retval None
2443 */
2444__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2445{
2446 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2447}
2448
2449/**
2450 * @brief Disable DMA Disabling on Reception Error
2451 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2452 * @param LPUARTx LPUART Instance
2453 * @retval None
2454 */
2455__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2456{
2457 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2458}
2459
2460/**
2461 * @brief Indicate if DMA Disabling on Reception Error is disabled
2462 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2463 * @param LPUARTx LPUART Instance
2464 * @retval State of bit (1 or 0).
2465 */
2466__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2467{
2468 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2469}
2470
2471/**
2472 * @brief Get the LPUART data register address used for DMA transfer
2473 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2474 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2475 * @param LPUARTx LPUART Instance
2476 * @param Direction This parameter can be one of the following values:
2477 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2478 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2479 * @retval Address of data register
2480 */
2481__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
2482{
2483 register uint32_t data_reg_addr;
2484
2485 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2486 {
2487 /* return address of TDR register */
2488 data_reg_addr = (uint32_t) & (LPUARTx->TDR);
2489 }
2490 else
2491 {
2492 /* return address of RDR register */
2493 data_reg_addr = (uint32_t) & (LPUARTx->RDR);
2494 }
2495
2496 return data_reg_addr;
2497}
2498
2499/**
2500 * @}
2501 */
2502
2503/** @defgroup LPUART_LL_EF_Data_Management Data_Management
2504 * @{
2505 */
2506
2507/**
2508 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2509 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2510 * @param LPUARTx LPUART Instance
2511 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2512 */
2513__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
2514{
2515 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2516}
2517
2518/**
2519 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2520 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2521 * @param LPUARTx LPUART Instance
2522 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2523 */
2524__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
2525{
2526 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2527}
2528
2529/**
2530 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2531 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2532 * @param LPUARTx LPUART Instance
2533 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2534 * @retval None
2535 */
2536__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2537{
2538 LPUARTx->TDR = Value;
2539}
2540
2541/**
2542 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2543 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2544 * @param LPUARTx LPUART Instance
2545 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2546 * @retval None
2547 */
2548__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2549{
2550 LPUARTx->TDR = Value & 0x1FFUL;
2551}
2552
2553/**
2554 * @}
2555 */
2556
2557/** @defgroup LPUART_LL_EF_Execution Execution
2558 * @{
2559 */
2560
2561/**
2562 * @brief Request Break sending
2563 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2564 * @param LPUARTx LPUART Instance
2565 * @retval None
2566 */
2567__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2568{
2569 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2570}
2571
2572/**
2573 * @brief Put LPUART in mute mode and set the RWU flag
2574 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2575 * @param LPUARTx LPUART Instance
2576 * @retval None
2577 */
2578__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2579{
2580 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2581}
2582
2583/**
2584 * @brief Request a Receive Data and FIFO flush
2585 * @note Allows to discard the received data without reading them, and avoid an overrun
2586 * condition.
2587 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2588 * @param LPUARTx LPUART Instance
2589 * @retval None
2590 */
2591__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2592{
2593 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2594}
2595
2596/**
2597 * @}
2598 */
2599
2600#if defined(USE_FULL_LL_DRIVER)
2601/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2602 * @{
2603 */
2604ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
2605ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
2606void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2607/**
2608 * @}
2609 */
2610#endif /* USE_FULL_LL_DRIVER */
2611
2612/**
2613 * @}
2614 */
2615
2616/**
2617 * @}
2618 */
2619
2620#endif /* LPUART1 */
2621
2622/**
2623 * @}
2624 */
2625
2626#ifdef __cplusplus
2627}
2628#endif
2629
2630#endif /* STM32G0xx_LL_LPUART_H */
2631
2632/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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