source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_lptim.h

Last change on this file was 6, checked in by f.jahn, 8 months ago
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1/**
2 ******************************************************************************
3 * @file stm32g0xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32G0xx_LL_LPTIM_H
22#define STM32G0xx_LL_LPTIM_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32g0xx.h"
30
31/** @addtogroup STM32G0xx_LL_Driver
32 * @{
33 */
34
35#if defined (LPTIM1) || defined (LPTIM2)
36
37/** @defgroup LPTIM_LL LPTIM
38 * @{
39 */
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
45
46/* Private macros ------------------------------------------------------------*/
47#if defined(USE_FULL_LL_DRIVER)
48/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
49 * @{
50 */
51/**
52 * @}
53 */
54#endif /*USE_FULL_LL_DRIVER*/
55
56/* Exported types ------------------------------------------------------------*/
57#if defined(USE_FULL_LL_DRIVER)
58/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
59 * @{
60 */
61
62/**
63 * @brief LPTIM Init structure definition
64 */
65typedef struct
66{
67 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
68 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
69
70 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
76
77 uint32_t Waveform; /*!< Specifies the waveform shape.
78 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
79
80 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
81
82 uint32_t Polarity; /*!< Specifies waveform polarity.
83 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
84
85 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
86} LL_LPTIM_InitTypeDef;
87
88/**
89 * @}
90 */
91#endif /* USE_FULL_LL_DRIVER */
92
93/* Exported constants --------------------------------------------------------*/
94/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
95 * @{
96 */
97
98/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
99 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
100 * @{
101 */
102#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
103#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
104#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
105#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
106#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
107#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
108#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
109/**
110 * @}
111 */
112
113/** @defgroup LPTIM_LL_EC_IT IT Defines
114 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
115 * @{
116 */
117#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
118#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
119#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
120#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
121#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
122#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
123#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
124/**
125 * @}
126 */
127
128/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
129 * @{
130 */
131#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
132#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
133/**
134 * @}
135 */
136
137/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
138 * @{
139 */
140#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
141#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
142/**
143 * @}
144 */
145
146/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
147 * @{
148 */
149#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
150#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
151/**
152 * @}
153 */
154
155/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
156 * @{
157 */
158#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
159#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
160/**
161 * @}
162 */
163
164/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
165 * @{
166 */
167#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
168#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
169/**
170 * @}
171 */
172
173/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
174 * @{
175 */
176#define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
177#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
178#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
179#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
180#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
181#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
182#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
183#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
184/**
185 * @}
186 */
187
188/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
189 * @{
190 */
191#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
192#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
193#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
194#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
195#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
196#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
197#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
198/**
199 * @}
200 */
201
202/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
203 * @{
204 */
205#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
206#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
207#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
208#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
209/**
210 * @}
211 */
212
213/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
214 * @{
215 */
216#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
217#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
218#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
219/**
220 * @}
221 */
222
223/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
224 * @{
225 */
226#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
227#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
228/**
229 * @}
230 */
231
232/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
233 * @{
234 */
235#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
236#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
237#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
238#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
239/**
240 * @}
241 */
242
243/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
244 * @{
245 */
246#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
247#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
248#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
249/**
250 * @}
251 */
252
253/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
254 * @{
255 */
256#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
257#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
258#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
259/**
260 * @}
261 */
262
263/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
264 * @{
265 */
266#define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
267#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
268#define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM2 */
269#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
270/**
271 * @}
272 */
273
274/** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
275 * @{
276 */
277#define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */
278#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 */
279/**
280 * @}
281 */
282
283
284/**
285 * @}
286 */
287
288/* Exported macro ------------------------------------------------------------*/
289/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
290 * @{
291 */
292
293/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
294 * @{
295 */
296
297/**
298 * @brief Write a value in LPTIM register
299 * @param __INSTANCE__ LPTIM Instance
300 * @param __REG__ Register to be written
301 * @param __VALUE__ Value to be written in the register
302 * @retval None
303 */
304#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
305
306/**
307 * @brief Read a value in LPTIM register
308 * @param __INSTANCE__ LPTIM Instance
309 * @param __REG__ Register to be read
310 * @retval Register value
311 */
312#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
313/**
314 * @}
315 */
316
317/**
318 * @}
319 */
320
321
322/* Exported functions --------------------------------------------------------*/
323/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
324 * @{
325 */
326
327/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
328 * @{
329 */
330
331/**
332 * @brief Enable the LPTIM instance
333 * @note After setting the ENABLE bit, a delay of two counter clock is needed
334 * before the LPTIM instance is actually enabled.
335 * @rmtoll CR ENABLE LL_LPTIM_Enable
336 * @param LPTIMx Low-Power Timer instance
337 * @retval None
338 */
339__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
340{
341 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
342}
343
344/**
345 * @brief Disable the LPTIM instance
346 * @rmtoll CR ENABLE LL_LPTIM_Disable
347 * @param LPTIMx Low-Power Timer instance
348 * @retval None
349 */
350__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
351{
352 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
353}
354
355/**
356 * @brief Indicates whether the LPTIM instance is enabled.
357 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
358 * @param LPTIMx Low-Power Timer instance
359 * @retval State of bit (1 or 0).
360 */
361__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
362{
363 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
364}
365
366/**
367 * @brief Starts the LPTIM counter in the desired mode.
368 * @note LPTIM instance must be enabled before starting the counter.
369 * @note It is possible to change on the fly from One Shot mode to
370 * Continuous mode.
371 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
372 * CR SNGSTRT LL_LPTIM_StartCounter
373 * @param LPTIMx Low-Power Timer instance
374 * @param OperatingMode This parameter can be one of the following values:
375 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
376 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
377 * @retval None
378 */
379__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
380{
381 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
382}
383
384/**
385 * @brief Enable reset after read.
386 * @note After calling this function any read access to LPTIM_CNT
387 * register will asynchronously reset the LPTIM_CNT register content.
388 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
389 * @param LPTIMx Low-Power Timer instance
390 * @retval None
391 */
392__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
393{
394 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
395}
396
397/**
398 * @brief Disable reset after read.
399 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
400 * @param LPTIMx Low-Power Timer instance
401 * @retval None
402 */
403__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
404{
405 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
406}
407
408/**
409 * @brief Indicate whether the reset after read feature is enabled.
410 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
411 * @param LPTIMx Low-Power Timer instance
412 * @retval State of bit (1 or 0).
413 */
414__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
415{
416 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
417}
418
419/**
420 * @brief Reset of the LPTIM_CNT counter register (synchronous).
421 * @note Due to the synchronous nature of this reset, it only takes
422 * place after a synchronization delay of 3 LPTIM core clock cycles
423 * (LPTIM core clock may be different from APB clock).
424 * @note COUNTRST is automatically cleared by hardware
425 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
426 * @param LPTIMx Low-Power Timer instance
427 * @retval None
428 */
429__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
430{
431 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
432}
433
434/**
435 * @brief Set the LPTIM registers update mode (enable/disable register preload)
436 * @note This function must be called when the LPTIM instance is disabled.
437 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
438 * @param LPTIMx Low-Power Timer instance
439 * @param UpdateMode This parameter can be one of the following values:
440 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
441 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
442 * @retval None
443 */
444__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
445{
446 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
447}
448
449/**
450 * @brief Get the LPTIM registers update mode
451 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
452 * @param LPTIMx Low-Power Timer instance
453 * @retval Returned value can be one of the following values:
454 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
455 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
456 */
457__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
458{
459 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
460}
461
462/**
463 * @brief Set the auto reload value
464 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
465 * @note After a write to the LPTIMx_ARR register a new write operation to the
466 * same register can only be performed when the previous write operation
467 * is completed. Any successive write before the ARROK flag be set, will
468 * lead to unpredictable results.
469 * @note autoreload value be strictly greater than the compare value.
470 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
471 * @param LPTIMx Low-Power Timer instance
472 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
473 * @retval None
474 */
475__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
476{
477 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
478}
479
480/**
481 * @brief Get actual auto reload value
482 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
483 * @param LPTIMx Low-Power Timer instance
484 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
485 */
486__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
487{
488 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
489}
490
491/**
492 * @brief Set the compare value
493 * @note After a write to the LPTIMx_CMP register a new write operation to the
494 * same register can only be performed when the previous write operation
495 * is completed. Any successive write before the CMPOK flag be set, will
496 * lead to unpredictable results.
497 * @rmtoll CMP CMP LL_LPTIM_SetCompare
498 * @param LPTIMx Low-Power Timer instance
499 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
500 * @retval None
501 */
502__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
503{
504 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
505}
506
507/**
508 * @brief Get actual compare value
509 * @rmtoll CMP CMP LL_LPTIM_GetCompare
510 * @param LPTIMx Low-Power Timer instance
511 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
512 */
513__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
514{
515 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
516}
517
518/**
519 * @brief Get actual counter value
520 * @note When the LPTIM instance is running with an asynchronous clock, reading
521 * the LPTIMx_CNT register may return unreliable values. So in this case
522 * it is necessary to perform two consecutive read accesses and verify
523 * that the two returned values are identical.
524 * @rmtoll CNT CNT LL_LPTIM_GetCounter
525 * @param LPTIMx Low-Power Timer instance
526 * @retval Counter value
527 */
528__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
529{
530 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
531}
532
533/**
534 * @brief Set the counter mode (selection of the LPTIM counter clock source).
535 * @note The counter mode can be set only when the LPTIM instance is disabled.
536 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
537 * @param LPTIMx Low-Power Timer instance
538 * @param CounterMode This parameter can be one of the following values:
539 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
540 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
541 * @retval None
542 */
543__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
544{
545 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
546}
547
548/**
549 * @brief Get the counter mode
550 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
551 * @param LPTIMx Low-Power Timer instance
552 * @retval Returned value can be one of the following values:
553 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
554 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
555 */
556__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
557{
558 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
559}
560
561/**
562 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
563 * @note This function must be called when the LPTIM instance is disabled.
564 * @note Regarding the LPTIM output polarity the change takes effect
565 * immediately, so the output default value will change immediately after
566 * the polarity is re-configured, even before the timer is enabled.
567 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
568 * CFGR WAVPOL LL_LPTIM_ConfigOutput
569 * @param LPTIMx Low-Power Timer instance
570 * @param Waveform This parameter can be one of the following values:
571 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
572 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
573 * @param Polarity This parameter can be one of the following values:
574 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
575 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
576 * @retval None
577 */
578__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
579{
580 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
581}
582
583/**
584 * @brief Set waveform shape
585 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
586 * @param LPTIMx Low-Power Timer instance
587 * @param Waveform This parameter can be one of the following values:
588 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
589 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
590 * @retval None
591 */
592__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
593{
594 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
595}
596
597/**
598 * @brief Get actual waveform shape
599 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
600 * @param LPTIMx Low-Power Timer instance
601 * @retval Returned value can be one of the following values:
602 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
603 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
604 */
605__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
606{
607 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
608}
609
610/**
611 * @brief Set output polarity
612 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
613 * @param LPTIMx Low-Power Timer instance
614 * @param Polarity This parameter can be one of the following values:
615 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
616 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
617 * @retval None
618 */
619__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
620{
621 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
622}
623
624/**
625 * @brief Get actual output polarity
626 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
627 * @param LPTIMx Low-Power Timer instance
628 * @retval Returned value can be one of the following values:
629 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
630 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
631 */
632__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
633{
634 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
635}
636
637/**
638 * @brief Set actual prescaler division ratio.
639 * @note This function must be called when the LPTIM instance is disabled.
640 * @note When the LPTIM is configured to be clocked by an internal clock source
641 * and the LPTIM counter is configured to be updated by active edges
642 * detected on the LPTIM external Input1, the internal clock provided to
643 * the LPTIM must be not be prescaled.
644 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
645 * @param LPTIMx Low-Power Timer instance
646 * @param Prescaler This parameter can be one of the following values:
647 * @arg @ref LL_LPTIM_PRESCALER_DIV1
648 * @arg @ref LL_LPTIM_PRESCALER_DIV2
649 * @arg @ref LL_LPTIM_PRESCALER_DIV4
650 * @arg @ref LL_LPTIM_PRESCALER_DIV8
651 * @arg @ref LL_LPTIM_PRESCALER_DIV16
652 * @arg @ref LL_LPTIM_PRESCALER_DIV32
653 * @arg @ref LL_LPTIM_PRESCALER_DIV64
654 * @arg @ref LL_LPTIM_PRESCALER_DIV128
655 * @retval None
656 */
657__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
658{
659 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
660}
661
662/**
663 * @brief Get actual prescaler division ratio.
664 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
665 * @param LPTIMx Low-Power Timer instance
666 * @retval Returned value can be one of the following values:
667 * @arg @ref LL_LPTIM_PRESCALER_DIV1
668 * @arg @ref LL_LPTIM_PRESCALER_DIV2
669 * @arg @ref LL_LPTIM_PRESCALER_DIV4
670 * @arg @ref LL_LPTIM_PRESCALER_DIV8
671 * @arg @ref LL_LPTIM_PRESCALER_DIV16
672 * @arg @ref LL_LPTIM_PRESCALER_DIV32
673 * @arg @ref LL_LPTIM_PRESCALER_DIV64
674 * @arg @ref LL_LPTIM_PRESCALER_DIV128
675 */
676__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
677{
678 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
679}
680
681/**
682 * @brief Set LPTIM input 1 source (default GPIO).
683 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
684 * @param LPTIMx Low-Power Timer instance
685 * @param Src This parameter can be one of the following values:
686 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
687 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
688 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
689 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
690 * @retval None
691 */
692__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
693{
694 WRITE_REG(LPTIMx->CFGR2, Src);
695}
696
697/**
698 * @brief Set LPTIM input 2 source (default GPIO).
699 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
700 * @param LPTIMx Low-Power Timer instance
701 * @param Src This parameter can be one of the following values:
702 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
703 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
704 * @retval None
705 */
706__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
707{
708 WRITE_REG(LPTIMx->CFGR2, Src);
709}
710
711/**
712 * @}
713 */
714
715/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
716 * @{
717 */
718
719/**
720 * @brief Enable the timeout function
721 * @note This function must be called when the LPTIM instance is disabled.
722 * @note The first trigger event will start the timer, any successive trigger
723 * event will reset the counter and the timer will restart.
724 * @note The timeout value corresponds to the compare value; if no trigger
725 * occurs within the expected time frame, the MCU is waked-up by the
726 * compare match event.
727 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
728 * @param LPTIMx Low-Power Timer instance
729 * @retval None
730 */
731__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
732{
733 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
734}
735
736/**
737 * @brief Disable the timeout function
738 * @note This function must be called when the LPTIM instance is disabled.
739 * @note A trigger event arriving when the timer is already started will be
740 * ignored.
741 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
742 * @param LPTIMx Low-Power Timer instance
743 * @retval None
744 */
745__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
746{
747 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
748}
749
750/**
751 * @brief Indicate whether the timeout function is enabled.
752 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
753 * @param LPTIMx Low-Power Timer instance
754 * @retval State of bit (1 or 0).
755 */
756__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
757{
758 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
759}
760
761/**
762 * @brief Start the LPTIM counter
763 * @note This function must be called when the LPTIM instance is disabled.
764 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
765 * @param LPTIMx Low-Power Timer instance
766 * @retval None
767 */
768__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
769{
770 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
771}
772
773/**
774 * @brief Configure the external trigger used as a trigger event for the LPTIM.
775 * @note This function must be called when the LPTIM instance is disabled.
776 * @note An internal clock source must be present when a digital filter is
777 * required for the trigger.
778 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
779 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
780 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
781 * @param LPTIMx Low-Power Timer instance
782 * @param Source This parameter can be one of the following values:
783 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
784 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
785 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
786 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
787 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
788 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
789 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
790 * @param Filter This parameter can be one of the following values:
791 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
792 * @arg @ref LL_LPTIM_TRIG_FILTER_2
793 * @arg @ref LL_LPTIM_TRIG_FILTER_4
794 * @arg @ref LL_LPTIM_TRIG_FILTER_8
795 * @param Polarity This parameter can be one of the following values:
796 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
797 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
798 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
799 * @retval None
800 */
801__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
802{
803 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
804}
805
806/**
807 * @brief Get actual external trigger source.
808 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
809 * @param LPTIMx Low-Power Timer instance
810 * @retval Returned value can be one of the following values:
811 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
812 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
813 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
814 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
815 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
816 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
817 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
818 */
819__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
820{
821 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
822}
823
824/**
825 * @brief Get actual external trigger filter.
826 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
827 * @param LPTIMx Low-Power Timer instance
828 * @retval Returned value can be one of the following values:
829 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
830 * @arg @ref LL_LPTIM_TRIG_FILTER_2
831 * @arg @ref LL_LPTIM_TRIG_FILTER_4
832 * @arg @ref LL_LPTIM_TRIG_FILTER_8
833 */
834__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
835{
836 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
837}
838
839/**
840 * @brief Get actual external trigger polarity.
841 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
842 * @param LPTIMx Low-Power Timer instance
843 * @retval Returned value can be one of the following values:
844 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
845 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
846 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
847 */
848__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
849{
850 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
851}
852
853/**
854 * @}
855 */
856
857/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
858 * @{
859 */
860
861/**
862 * @brief Set the source of the clock used by the LPTIM instance.
863 * @note This function must be called when the LPTIM instance is disabled.
864 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
865 * @param LPTIMx Low-Power Timer instance
866 * @param ClockSource This parameter can be one of the following values:
867 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
868 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
869 * @retval None
870 */
871__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
872{
873 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
874}
875
876/**
877 * @brief Get actual LPTIM instance clock source.
878 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
879 * @param LPTIMx Low-Power Timer instance
880 * @retval Returned value can be one of the following values:
881 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
882 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
883 */
884__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
885{
886 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
887}
888
889/**
890 * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
891 * @note This function must be called when the LPTIM instance is disabled.
892 * @note When both external clock signal edges are considered active ones,
893 * the LPTIM must also be clocked by an internal clock source with a
894 * frequency equal to at least four times the external clock frequency.
895 * @note An internal clock source must be present when a digital filter is
896 * required for external clock.
897 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
898 * CFGR CKPOL LL_LPTIM_ConfigClock
899 * @param LPTIMx Low-Power Timer instance
900 * @param ClockFilter This parameter can be one of the following values:
901 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
902 * @arg @ref LL_LPTIM_CLK_FILTER_2
903 * @arg @ref LL_LPTIM_CLK_FILTER_4
904 * @arg @ref LL_LPTIM_CLK_FILTER_8
905 * @param ClockPolarity This parameter can be one of the following values:
906 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
907 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
908 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
909 * @retval None
910 */
911__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
912{
913 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
914}
915
916/**
917 * @brief Get actual clock polarity
918 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
919 * @param LPTIMx Low-Power Timer instance
920 * @retval Returned value can be one of the following values:
921 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
922 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
923 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
924 */
925__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
926{
927 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
928}
929
930/**
931 * @brief Get actual clock digital filter
932 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
933 * @param LPTIMx Low-Power Timer instance
934 * @retval Returned value can be one of the following values:
935 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
936 * @arg @ref LL_LPTIM_CLK_FILTER_2
937 * @arg @ref LL_LPTIM_CLK_FILTER_4
938 * @arg @ref LL_LPTIM_CLK_FILTER_8
939 */
940__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
941{
942 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
943}
944
945/**
946 * @}
947 */
948
949/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
950 * @{
951 */
952
953/**
954 * @brief Configure the encoder mode.
955 * @note This function must be called when the LPTIM instance is disabled.
956 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
957 * @param LPTIMx Low-Power Timer instance
958 * @param EncoderMode This parameter can be one of the following values:
959 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
960 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
961 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
962 * @retval None
963 */
964__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
965{
966 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
967}
968
969/**
970 * @brief Get actual encoder mode.
971 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
972 * @param LPTIMx Low-Power Timer instance
973 * @retval Returned value can be one of the following values:
974 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
975 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
976 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
977 */
978__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
979{
980 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
981}
982
983/**
984 * @brief Enable the encoder mode
985 * @note This function must be called when the LPTIM instance is disabled.
986 * @note In this mode the LPTIM instance must be clocked by an internal clock
987 * source. Also, the prescaler division ratio must be equal to 1.
988 * @note LPTIM instance must be configured in continuous mode prior enabling
989 * the encoder mode.
990 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
991 * @param LPTIMx Low-Power Timer instance
992 * @retval None
993 */
994__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
995{
996 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
997}
998
999/**
1000 * @brief Disable the encoder mode
1001 * @note This function must be called when the LPTIM instance is disabled.
1002 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1003 * @param LPTIMx Low-Power Timer instance
1004 * @retval None
1005 */
1006__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1007{
1008 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1009}
1010
1011/**
1012 * @brief Indicates whether the LPTIM operates in encoder mode.
1013 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1014 * @param LPTIMx Low-Power Timer instance
1015 * @retval State of bit (1 or 0).
1016 */
1017__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
1018{
1019 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
1020}
1021
1022/**
1023 * @}
1024 */
1025
1026/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1027 * @{
1028 */
1029
1030/**
1031 * @brief Clear the compare match flag (CMPMCF)
1032 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
1033 * @param LPTIMx Low-Power Timer instance
1034 * @retval None
1035 */
1036__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
1037{
1038 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1039}
1040
1041/**
1042 * @brief Inform application whether a compare match interrupt has occurred.
1043 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1044 * @param LPTIMx Low-Power Timer instance
1045 * @retval State of bit (1 or 0).
1046 */
1047__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1048{
1049 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
1050}
1051
1052/**
1053 * @brief Clear the autoreload match flag (ARRMCF)
1054 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
1055 * @param LPTIMx Low-Power Timer instance
1056 * @retval None
1057 */
1058__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
1059{
1060 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1061}
1062
1063/**
1064 * @brief Inform application whether a autoreload match interrupt has occurred.
1065 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1066 * @param LPTIMx Low-Power Timer instance
1067 * @retval State of bit (1 or 0).
1068 */
1069__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1070{
1071 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
1072}
1073
1074/**
1075 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1076 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1077 * @param LPTIMx Low-Power Timer instance
1078 * @retval None
1079 */
1080__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1081{
1082 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1083}
1084
1085/**
1086 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1087 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1088 * @param LPTIMx Low-Power Timer instance
1089 * @retval State of bit (1 or 0).
1090 */
1091__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1092{
1093 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
1094}
1095
1096/**
1097 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1098 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1099 * @param LPTIMx Low-Power Timer instance
1100 * @retval None
1101 */
1102__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1103{
1104 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1105}
1106
1107/**
1108 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
1109 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1110 * @param LPTIMx Low-Power Timer instance
1111 * @retval State of bit (1 or 0).
1112 */
1113__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1114{
1115 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
1116}
1117
1118/**
1119 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1120 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1121 * @param LPTIMx Low-Power Timer instance
1122 * @retval None
1123 */
1124__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1125{
1126 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1127}
1128
1129/**
1130 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
1131 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1132 * @param LPTIMx Low-Power Timer instance
1133 * @retval State of bit (1 or 0).
1134 */
1135__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1136{
1137 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
1138}
1139
1140/**
1141 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1142 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1143 * @param LPTIMx Low-Power Timer instance
1144 * @retval None
1145 */
1146__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1147{
1148 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1149}
1150
1151/**
1152 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
1153 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1154 * @param LPTIMx Low-Power Timer instance
1155 * @retval State of bit (1 or 0).
1156 */
1157__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1158{
1159 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
1160}
1161
1162/**
1163 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1164 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1165 * @param LPTIMx Low-Power Timer instance
1166 * @retval None
1167 */
1168__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1169{
1170 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1171}
1172
1173/**
1174 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
1175 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1176 * @param LPTIMx Low-Power Timer instance
1177 * @retval State of bit (1 or 0).
1178 */
1179__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1180{
1181 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
1182}
1183
1184/**
1185 * @}
1186 */
1187
1188/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1189 * @{
1190 */
1191
1192/**
1193 * @brief Enable compare match interrupt (CMPMIE).
1194 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1195 * @param LPTIMx Low-Power Timer instance
1196 * @retval None
1197 */
1198__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1199{
1200 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1201}
1202
1203/**
1204 * @brief Disable compare match interrupt (CMPMIE).
1205 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1206 * @param LPTIMx Low-Power Timer instance
1207 * @retval None
1208 */
1209__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1210{
1211 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1212}
1213
1214/**
1215 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1216 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1217 * @param LPTIMx Low-Power Timer instance
1218 * @retval State of bit (1 or 0).
1219 */
1220__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1221{
1222 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
1223}
1224
1225/**
1226 * @brief Enable autoreload match interrupt (ARRMIE).
1227 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1228 * @param LPTIMx Low-Power Timer instance
1229 * @retval None
1230 */
1231__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1232{
1233 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1234}
1235
1236/**
1237 * @brief Disable autoreload match interrupt (ARRMIE).
1238 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1239 * @param LPTIMx Low-Power Timer instance
1240 * @retval None
1241 */
1242__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1243{
1244 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1245}
1246
1247/**
1248 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1249 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1250 * @param LPTIMx Low-Power Timer instance
1251 * @retval State of bit (1 or 0).
1252 */
1253__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1254{
1255 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
1256}
1257
1258/**
1259 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1260 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1261 * @param LPTIMx Low-Power Timer instance
1262 * @retval None
1263 */
1264__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1265{
1266 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1267}
1268
1269/**
1270 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1271 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1272 * @param LPTIMx Low-Power Timer instance
1273 * @retval None
1274 */
1275__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1276{
1277 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1278}
1279
1280/**
1281 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1282 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1283 * @param LPTIMx Low-Power Timer instance
1284 * @retval State of bit (1 or 0).
1285 */
1286__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1287{
1288 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
1289}
1290
1291/**
1292 * @brief Enable compare register write completed interrupt (CMPOKIE).
1293 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1294 * @param LPTIMx Low-Power Timer instance
1295 * @retval None
1296 */
1297__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1298{
1299 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1300}
1301
1302/**
1303 * @brief Disable compare register write completed interrupt (CMPOKIE).
1304 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1305 * @param LPTIMx Low-Power Timer instance
1306 * @retval None
1307 */
1308__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1309{
1310 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1311}
1312
1313/**
1314 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1315 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1316 * @param LPTIMx Low-Power Timer instance
1317 * @retval State of bit (1 or 0).
1318 */
1319__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1320{
1321 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
1322}
1323
1324/**
1325 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1326 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1327 * @param LPTIMx Low-Power Timer instance
1328 * @retval None
1329 */
1330__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1331{
1332 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1333}
1334
1335/**
1336 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1337 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1338 * @param LPTIMx Low-Power Timer instance
1339 * @retval None
1340 */
1341__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1342{
1343 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1344}
1345
1346/**
1347 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1348 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1349 * @param LPTIMx Low-Power Timer instance
1350 * @retval State of bit (1 or 0).
1351 */
1352__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1353{
1354 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
1355}
1356
1357/**
1358 * @brief Enable direction change to up interrupt (UPIE).
1359 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1360 * @param LPTIMx Low-Power Timer instance
1361 * @retval None
1362 */
1363__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1364{
1365 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1366}
1367
1368/**
1369 * @brief Disable direction change to up interrupt (UPIE).
1370 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1371 * @param LPTIMx Low-Power Timer instance
1372 * @retval None
1373 */
1374__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1375{
1376 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1377}
1378
1379/**
1380 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1381 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1382 * @param LPTIMx Low-Power Timer instance
1383 * @retval State of bit (1 or 0).
1384 */
1385__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1386{
1387 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
1388}
1389
1390/**
1391 * @brief Enable direction change to down interrupt (DOWNIE).
1392 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1393 * @param LPTIMx Low-Power Timer instance
1394 * @retval None
1395 */
1396__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1397{
1398 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1399}
1400
1401/**
1402 * @brief Disable direction change to down interrupt (DOWNIE).
1403 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1404 * @param LPTIMx Low-Power Timer instance
1405 * @retval None
1406 */
1407__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1408{
1409 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1410}
1411
1412/**
1413 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1414 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1415 * @param LPTIMx Low-Power Timer instance
1416 * @retval State of bit (1 or 0).
1417 */
1418__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1419{
1420 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL));
1421}
1422
1423/**
1424 * @}
1425 */
1426
1427#if defined(USE_FULL_LL_DRIVER)
1428/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
1429 * @{
1430 */
1431
1432ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
1433void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
1434ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
1435/**
1436 * @}
1437 */
1438#endif /* USE_FULL_LL_DRIVER */
1439
1440/**
1441 * @}
1442 */
1443
1444/**
1445 * @}
1446 */
1447
1448#endif /* LPTIM1 || LPTIM2 */
1449
1450/**
1451 * @}
1452 */
1453
1454#ifdef __cplusplus
1455}
1456#endif
1457
1458#endif /* STM32G0xx_LL_LPTIM_H */
1459
1460/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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