source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h

Last change on this file was 6, checked in by f.jahn, 8 months ago
File size: 87.6 KB
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1/**
2 ******************************************************************************
3 * @file stm32g0xx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32G0xx_LL_DMAMUX_H
21#define STM32G0xx_LL_DMAMUX_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32g0xx.h"
29
30/** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34#if defined (DMAMUX1)
35
36/** @defgroup DMAMUX_LL DMAMUX
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private constants ---------------------------------------------------------*/
43/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
44 * @{
45 */
46/* Define used to get DMAMUX CCR register size */
47#define DMAMUX_CCR_SIZE 0x00000004UL
48
49/* Define used to get DMAMUX RGCR register size */
50#define DMAMUX_RGCR_SIZE 0x00000004UL
51/**
52 * @}
53 */
54
55/* Private macros ------------------------------------------------------------*/
56/* Exported types ------------------------------------------------------------*/
57/* Exported constants --------------------------------------------------------*/
58/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
59 * @{
60 */
61/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
62 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
63 * @{
64 */
65#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
66#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
67#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
68#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
69#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
70#if defined(DMAMUX1_Channel5)
71#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
72#endif /* DMAMUX1_Channel5 */
73#if defined(DMAMUX1_Channel6)
74#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
75#endif /* DMAMUX1_Channel6 */
76#if defined(DMA2)
77#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
78#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
79#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
80#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
81#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
82#endif /* DMA2 */
83#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
84#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
85#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
86#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
87/**
88 * @}
89 */
90
91/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
92 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
93 * @{
94 */
95#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
96#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
97#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
98#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
99#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
100#if defined(DMAMUX1_Channel5)
101#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
102#endif /* DMAMUX1_Channel5 */
103#if defined(DMAMUX1_Channel6)
104#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
105#endif /* DMAMUX1_Channel6 */
106#if defined(DMA2)
107#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
108#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
109#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
110#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
111#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
112#endif /* DMA2 */
113#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
114#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
115#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
116#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
117/**
118 * @}
119 */
120
121/** @defgroup DMAMUX_LL_EC_IT IT Defines
122 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
123 * @{
124 */
125#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
126#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
127/**
128 * @}
129 */
130
131/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
132 * @{
133 */
134#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */
135#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */
136#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */
137#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */
138#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */
139#define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */
140#if defined(AES)
141#define LL_DMAMUX_REQ_AES_IN 0x00000006U /*!< DMAMUX AES_IN request */
142#define LL_DMAMUX_REQ_AES_OUT 0x00000007U /*!< DMAMUX AES_OUT request */
143#endif /* AES */
144#if defined(DAC1)
145#define LL_DMAMUX_REQ_DAC1_CH1 0x00000008U /*!< DMAMUX DAC_CH1 request */
146#define LL_DMAMUX_REQ_DAC1_CH2 0x00000009U /*!< DMAMUX DAC_CH2 request */
147#endif /* DAC1 */
148#define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */
149#define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */
150#define LL_DMAMUX_REQ_I2C2_RX 0x0000000CU /*!< DMAMUX I2C2 RX request */
151#define LL_DMAMUX_REQ_I2C2_TX 0x0000000DU /*!< DMAMUX I2C2 TX request */
152#if defined(LPUART1)
153#define LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU /*!< DMAMUX LPUART1 RX request */
154#define LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU /*!< DMAMUX LPUART1 TX request */
155#endif /* LPUART1 */
156#define LL_DMAMUX_REQ_SPI1_RX 0x00000010U /*!< DMAMUX SPI1 RX request */
157#define LL_DMAMUX_REQ_SPI1_TX 0x00000011U /*!< DMAMUX SPI1 TX request */
158#define LL_DMAMUX_REQ_SPI2_RX 0x00000012U /*!< DMAMUX SPI2 RX request */
159#define LL_DMAMUX_REQ_SPI2_TX 0x00000013U /*!< DMAMUX SPI2 TX request */
160#define LL_DMAMUX_REQ_TIM1_CH1 0x00000014U /*!< DMAMUX TIM1 CH1 request */
161#define LL_DMAMUX_REQ_TIM1_CH2 0x00000015U /*!< DMAMUX TIM1 CH2 request */
162#define LL_DMAMUX_REQ_TIM1_CH3 0x00000016U /*!< DMAMUX TIM1 CH3 request */
163#define LL_DMAMUX_REQ_TIM1_CH4 0x00000017U /*!< DMAMUX TIM1 CH4 request */
164#define LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U /*!< DMAMUX TIM1 TRIG COM request */
165#define LL_DMAMUX_REQ_TIM1_UP 0x00000019U /*!< DMAMUX TIM1 UP request */
166#if defined(TIM2)
167#define LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU /*!< DMAMUX TIM2 CH1 request */
168#define LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU /*!< DMAMUX TIM2 CH2 request */
169#define LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU /*!< DMAMUX TIM2 CH3 request */
170#define LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU /*!< DMAMUX TIM2 CH4 request */
171#define LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU /*!< DMAMUX TIM2 TRIG request */
172#define LL_DMAMUX_REQ_TIM2_UP 0x0000001FU /*!< DMAMUX TIM2 UP request */
173#endif /* TIM2 */
174#define LL_DMAMUX_REQ_TIM3_CH1 0x00000020U /*!< DMAMUX TIM3 CH1 request */
175#define LL_DMAMUX_REQ_TIM3_CH2 0x00000021U /*!< DMAMUX TIM3 CH2 request */
176#define LL_DMAMUX_REQ_TIM3_CH3 0x00000022U /*!< DMAMUX TIM3 CH3 request */
177#define LL_DMAMUX_REQ_TIM3_CH4 0x00000023U /*!< DMAMUX TIM3 CH4 request */
178#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U /*!< DMAMUX TIM3 TRIG request */
179#define LL_DMAMUX_REQ_TIM3_UP 0x00000025U /*!< DMAMUX TIM3 UP request */
180#if defined(TIM6)
181#define LL_DMAMUX_REQ_TIM6_UP 0x00000026U /*!< DMAMUX TIM6 UP request */
182#endif /* TIM6 */
183#if defined(TIM7)
184#define LL_DMAMUX_REQ_TIM7_UP 0x00000027U /*!< DMAMUX TIM7 UP request */
185#endif /* TIM7 */
186#if defined(TIM15)
187#define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U /*!< DMAMUX TIM15 CH1 request */
188#define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U /*!< DMAMUX TIM15 CH2 request */
189#define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU /*!< DMAMUX TIM15 TRIG COM request */
190#define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU /*!< DMAMUX TIM15 UP request */
191#endif /* TIM15 */
192#define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU /*!< DMAMUX TIM16 CH1 request */
193#define LL_DMAMUX_REQ_TIM16_COM 0x0000002DU /*!< DMAMUX TIM16 COM request */
194#define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU /*!< DMAMUX TIM16 UP request */
195#define LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU /*!< DMAMUX TIM17 CH1 request */
196#define LL_DMAMUX_REQ_TIM17_COM 0x00000030U /*!< DMAMUX TIM17 COM request */
197#define LL_DMAMUX_REQ_TIM17_UP 0x00000031U /*!< DMAMUX TIM17 UP request */
198#define LL_DMAMUX_REQ_USART1_RX 0x00000032U /*!< DMAMUX USART1 RX request */
199#define LL_DMAMUX_REQ_USART1_TX 0x00000033U /*!< DMAMUX USART1 TX request */
200#define LL_DMAMUX_REQ_USART2_RX 0x00000034U /*!< DMAMUX USART2 RX request */
201#define LL_DMAMUX_REQ_USART2_TX 0x00000035U /*!< DMAMUX USART2 TX request */
202#if defined(USART3)
203#define LL_DMAMUX_REQ_USART3_RX 0x00000036U /*!< DMAMUX USART3 RX request */
204#define LL_DMAMUX_REQ_USART3_TX 0x00000037U /*!< DMAMUX USART3 TX request */
205#endif /* USART3 */
206#if defined(USART4)
207#define LL_DMAMUX_REQ_USART4_RX 0x00000038U /*!< DMAMUX USART4 RX request */
208#define LL_DMAMUX_REQ_USART4_TX 0x00000039U /*!< DMAMUX USART4 TX request */
209#endif /* USART4 */
210#if defined(UCPD1)
211#define LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU /*!< DMAMUX UCPD1 RX request */
212#define LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU /*!< DMAMUX UCPD1 TX request */
213#endif /* UCPD1 */
214#if defined(UCPD2)
215#define LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU /*!< DMAMUX UCPD2 RX request */
216#define LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU /*!< DMAMUX UCPD2 TX request */
217#endif /* UCPD2 */
218
219#if defined(I2C3)
220#define LL_DMAMUX_REQ_I2C3_RX 0x0000003EU /*!< DMAMUX I2C3 RX request */
221#define LL_DMAMUX_REQ_I2C3_TX 0x0000003FU /*!< DMAMUX I2C3 TX request */
222#endif /* I2C3 */
223
224#if defined(LPUART2)
225#define LL_DMAMUX_REQ_LPUART2_RX 0x00000040U /*!< DMAMUX LPUART2 RX request */
226#define LL_DMAMUX_REQ_LPUART2_TX 0x00000041U /*!< DMAMUX LPUART2 TX request */
227#endif /* LPUART2 */
228
229#if defined(SPI3)
230#define LL_DMAMUX_REQ_SPI3_RX 0x00000042U /*!< DMAMUX SPI3 RX request */
231#define LL_DMAMUX_REQ_SPI3_TX 0x00000043U /*!< DMAMUX SPI3 TX request */
232#endif /* SPI3 */
233
234#if defined(TIM4)
235#define LL_DMAMUX_REQ_TIM4_CH1 0x00000044U /*!< DMAMUX TIM4 CH1 request */
236#define LL_DMAMUX_REQ_TIM4_CH2 0x00000045U /*!< DMAMUX TIM4 CH2 request */
237#define LL_DMAMUX_REQ_TIM4_CH3 0x00000046U /*!< DMAMUX TIM4 CH3 request */
238#define LL_DMAMUX_REQ_TIM4_CH4 0x00000047U /*!< DMAMUX TIM4 CH4 request */
239#define LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U /*!< DMAMUX TIM4 TRIG request */
240#define LL_DMAMUX_REQ_TIM4_UP 0x00000049U /*!< DMAMUX TIM4 UP request */
241#endif /* TIM4 */
242
243#if defined(USART5)
244#define LL_DMAMUX_REQ_USART5_RX 0x0000004AU /*!< DMAMUX USART5 RX request */
245#define LL_DMAMUX_REQ_USART5_TX 0x0000004BU /*!< DMAMUX USART5 TX request */
246#endif /* USART5 */
247
248#if defined(USART6)
249#define LL_DMAMUX_REQ_USART6_RX 0x0000004CU /*!< DMAMUX USART6 RX request */
250#define LL_DMAMUX_REQ_USART6_TX 0x0000004DU /*!< DMAMUX USART6 TX request */
251#endif /* USART6 */
252
253#if defined(STM32G0C1xx)||defined(STM32G0B1xx)
254#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX
255#elif defined(STM32G0B0xx)
256#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX
257#elif defined(STM32G081xx)||defined(STM32G071xx)
258#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_UCPD2_TX
259#elif defined(STM32G070xx)
260#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX
261#else
262#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART2_TX
263#endif /* STM32G0C1xx || STM32G0B1xx */
264/**
265 * @}
266 */
267
268/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
269 * @{
270 */
271#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
272#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
273#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
274#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
275#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
276#if defined(DMAMUX1_Channel5)
277#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
278#endif /* DMAMUX1_Channel5 */
279#if defined(DMAMUX1_Channel6)
280#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
281#endif /* DMAMUX1_Channel6 */
282#if defined(DMA2)
283#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */
284#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */
285#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */
286#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
287#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
288#endif /* DMA2 */
289/**
290 * @}
291 */
292
293/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
294 * @{
295 */
296#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
297#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
298#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
299#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
300/**
301 * @}
302 */
303
304/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
305 * @{
306 */
307#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */
308#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
309#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
310#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
311#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
312#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
313#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
314#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
315#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
316#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
317#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
318#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
319#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
320#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 3 */
321#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line1 4 */
322#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */
323#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */
324#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
325#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */
326#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */
327#if defined(LPTIM1)
328#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
329#endif /* LPTIM1 */
330#if defined(LPTIM2)
331#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */
332#endif /* LPTIM2 */
333#define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from TIM14 OC */
334/**
335 * @}
336 */
337
338/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
339 * @{
340 */
341#define LL_DMAMUX_REQ_GEN_0 0x00000000U
342#define LL_DMAMUX_REQ_GEN_1 0x00000001U
343#define LL_DMAMUX_REQ_GEN_2 0x00000002U
344#define LL_DMAMUX_REQ_GEN_3 0x00000003U
345/**
346 * @}
347 */
348
349/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
350 * @{
351 */
352#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
353#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
354#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
355#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
356/**
357 * @}
358 */
359
360/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
361 * @{
362 */
363#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */
364#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
365#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
366#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
367#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
368#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
369#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
370#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
371#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
372#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
373#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
374#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
375#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
376#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
377#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
378#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
379#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */
380#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
381#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */
382#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */
383#if defined(LPTIM1)
384#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
385#endif /* LPTIM1 */
386#if defined(LPTIM2)
387#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */
388#endif /* LPTIM2 */
389#define LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from TIM14 OC */
390/**
391 * @}
392 */
393
394/**
395 * @}
396 */
397
398/* Exported macro ------------------------------------------------------------*/
399/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
400 * @{
401 */
402
403/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
404 * @{
405 */
406/**
407 * @brief Write a value in DMAMUX register
408 * @param __INSTANCE__ DMAMUX Instance
409 * @param __REG__ Register to be written
410 * @param __VALUE__ Value to be written in the register
411 * @retval None
412 */
413#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
414
415/**
416 * @brief Read a value in DMAMUX register
417 * @param __INSTANCE__ DMAMUX Instance
418 * @param __REG__ Register to be read
419 * @retval Register value
420 */
421#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
422/**
423 * @}
424 */
425
426/**
427 * @}
428 */
429
430/* Exported functions --------------------------------------------------------*/
431/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
432 * @{
433 */
434
435/** @defgroup DMAMUX_LL_EF_Configuration Configuration
436 * @{
437 */
438/**
439 * @brief Set DMAMUX request ID for DMAMUX Channel x.
440 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
441 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
442 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
443 * @param DMAMUXx DMAMUXx Instance
444 * @param Channel This parameter can be one of the following values:
445 * @arg @ref LL_DMAMUX_CHANNEL_0
446 * @arg @ref LL_DMAMUX_CHANNEL_1
447 * @arg @ref LL_DMAMUX_CHANNEL_2
448 * @arg @ref LL_DMAMUX_CHANNEL_3
449 * @arg @ref LL_DMAMUX_CHANNEL_4
450 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
451 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
452 *
453 * @arg All the next values are only available on chip which support DMA2:
454 * @arg @ref LL_DMAMUX_CHANNEL_7
455 * @arg @ref LL_DMAMUX_CHANNEL_8
456 * @arg @ref LL_DMAMUX_CHANNEL_9
457 * @arg @ref LL_DMAMUX_CHANNEL_10
458 * @arg @ref LL_DMAMUX_CHANNEL_11
459 * @param Request This parameter can be one of the following values:
460 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
461 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
462 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
463 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
464 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
465 * @arg @ref LL_DMAMUX_REQ_ADC1
466 * @arg @ref LL_DMAMUX_REQ_AES_IN
467 * @arg @ref LL_DMAMUX_REQ_AES_OUT
468 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
469 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
470 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
471 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
472 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
473 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
474 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
475 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
476 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
477 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
478 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
479 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
480 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
481 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
482 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
483 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
484 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
485 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
486 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
487 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
488 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
489 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
490 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
491 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
492 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
493 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
494 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
495 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
496 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
497 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
498 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
499 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
500 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
501 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
502 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
503 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
504 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
505 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
506 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
507 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
508 * @arg @ref LL_DMAMUX_REQ_TIM17_COM
509 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
510 * @arg @ref LL_DMAMUX_REQ_USART1_RX
511 * @arg @ref LL_DMAMUX_REQ_USART1_TX
512 * @arg @ref LL_DMAMUX_REQ_USART2_RX
513 * @arg @ref LL_DMAMUX_REQ_USART2_TX
514 * @arg @ref LL_DMAMUX_REQ_USART3_RX
515 * @arg @ref LL_DMAMUX_REQ_USART3_TX
516 * @arg @ref LL_DMAMUX_REQ_USART4_RX
517 * @arg @ref LL_DMAMUX_REQ_USART4_TX
518 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
519 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
520 * @arg @ref LL_DMAMUX_REQ_UCPD2_RX
521 * @arg @ref LL_DMAMUX_REQ_UCPD2_TX
522 * @retval None
523 */
524__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
525{
526 (void)(DMAMUXx);
527 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
528}
529
530/**
531 * @brief Get DMAMUX request ID for DMAMUX Channel x.
532 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
533 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
534 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
535 * @param DMAMUXx DMAMUXx Instance
536 * @param Channel This parameter can be one of the following values:
537 * @arg @ref LL_DMAMUX_CHANNEL_0
538 * @arg @ref LL_DMAMUX_CHANNEL_1
539 * @arg @ref LL_DMAMUX_CHANNEL_2
540 * @arg @ref LL_DMAMUX_CHANNEL_3
541 * @arg @ref LL_DMAMUX_CHANNEL_4
542 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
543 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
544 *
545 * @arg All the next values are only available on chip which support DMA2:
546 * @arg @ref LL_DMAMUX_CHANNEL_7
547 * @arg @ref LL_DMAMUX_CHANNEL_8
548 * @arg @ref LL_DMAMUX_CHANNEL_9
549 * @arg @ref LL_DMAMUX_CHANNEL_10
550 * @arg @ref LL_DMAMUX_CHANNEL_11
551 * @retval Returned value can be one of the following values:
552 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
553 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
554 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
555 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
556 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
557 * @arg @ref LL_DMAMUX_REQ_ADC1
558 * @arg @ref LL_DMAMUX_REQ_AES_IN
559 * @arg @ref LL_DMAMUX_REQ_AES_OUT
560 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
561 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
562 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
563 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
564 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
565 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
566 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
567 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
568 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
569 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
570 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
571 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
572 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
573 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
574 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
575 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
576 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
577 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
578 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
579 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
580 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
581 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
582 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
583 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
584 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
585 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
586 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
587 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
588 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
589 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
590 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
591 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
592 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
593 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
594 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
595 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
596 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
597 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
598 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
599 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
600 * @arg @ref LL_DMAMUX_REQ_TIM17_COM
601 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
602 * @arg @ref LL_DMAMUX_REQ_USART1_RX
603 * @arg @ref LL_DMAMUX_REQ_USART1_TX
604 * @arg @ref LL_DMAMUX_REQ_USART2_RX
605 * @arg @ref LL_DMAMUX_REQ_USART2_TX
606 * @arg @ref LL_DMAMUX_REQ_USART3_RX
607 * @arg @ref LL_DMAMUX_REQ_USART3_TX
608 * @arg @ref LL_DMAMUX_REQ_USART4_RX
609 * @arg @ref LL_DMAMUX_REQ_USART4_TX
610 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
611 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
612 * @arg @ref LL_DMAMUX_REQ_UCPD2_RX
613 * @arg @ref LL_DMAMUX_REQ_UCPD2_TX
614 */
615__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
616{
617 (void)(DMAMUXx);
618 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
619}
620
621/**
622 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
623 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
624 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
625 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
626 * @param DMAMUXx DMAMUXx Instance
627 * @param Channel This parameter can be one of the following values:
628 * @arg @ref LL_DMAMUX_CHANNEL_0
629 * @arg @ref LL_DMAMUX_CHANNEL_1
630 * @arg @ref LL_DMAMUX_CHANNEL_2
631 * @arg @ref LL_DMAMUX_CHANNEL_3
632 * @arg @ref LL_DMAMUX_CHANNEL_4
633 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
634 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
635 *
636 * @arg All the next values are only available on chip which support DMA2:
637 * @arg @ref LL_DMAMUX_CHANNEL_7
638 * @arg @ref LL_DMAMUX_CHANNEL_8
639 * @arg @ref LL_DMAMUX_CHANNEL_9
640 * @arg @ref LL_DMAMUX_CHANNEL_10
641 * @arg @ref LL_DMAMUX_CHANNEL_11
642 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
643 * @retval None
644 */
645__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
646{
647 (void)(DMAMUXx);
648 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
649}
650
651/**
652 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
653 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
654 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
655 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
656 * @param DMAMUXx DMAMUXx Instance
657 * @param Channel This parameter can be one of the following values:
658 * @arg @ref LL_DMAMUX_CHANNEL_0
659 * @arg @ref LL_DMAMUX_CHANNEL_1
660 * @arg @ref LL_DMAMUX_CHANNEL_2
661 * @arg @ref LL_DMAMUX_CHANNEL_3
662 * @arg @ref LL_DMAMUX_CHANNEL_4
663 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
664 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
665 *
666 * @arg All the next values are only available on chip which support DMA2:
667 * @arg @ref LL_DMAMUX_CHANNEL_7
668 * @arg @ref LL_DMAMUX_CHANNEL_8
669 * @arg @ref LL_DMAMUX_CHANNEL_9
670 * @arg @ref LL_DMAMUX_CHANNEL_10
671 * @arg @ref LL_DMAMUX_CHANNEL_11
672 * @retval Between Min_Data = 1 and Max_Data = 32
673 */
674__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
675{
676 (void)(DMAMUXx);
677 return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
678}
679
680/**
681 * @brief Set the polarity of the signal on which the DMA request is synchronized.
682 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
683 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
684 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
685 * @param DMAMUXx DMAMUXx Instance
686 * @param Channel This parameter can be one of the following values:
687 * @arg @ref LL_DMAMUX_CHANNEL_0
688 * @arg @ref LL_DMAMUX_CHANNEL_1
689 * @arg @ref LL_DMAMUX_CHANNEL_2
690 * @arg @ref LL_DMAMUX_CHANNEL_3
691 * @arg @ref LL_DMAMUX_CHANNEL_4
692 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
693 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
694 *
695 * @arg All the next values are only available on chip which support DMA2:
696 * @arg @ref LL_DMAMUX_CHANNEL_7
697 * @arg @ref LL_DMAMUX_CHANNEL_8
698 * @arg @ref LL_DMAMUX_CHANNEL_9
699 * @arg @ref LL_DMAMUX_CHANNEL_10
700 * @arg @ref LL_DMAMUX_CHANNEL_11
701 * @param Polarity This parameter can be one of the following values:
702 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
703 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
704 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
705 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
706 * @retval None
707 */
708__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
709{
710 (void)(DMAMUXx);
711 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
712}
713
714/**
715 * @brief Get the polarity of the signal on which the DMA request is synchronized.
716 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
717 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
718 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
719 * @param DMAMUXx DMAMUXx Instance
720 * @param Channel This parameter can be one of the following values:
721 * @arg @ref LL_DMAMUX_CHANNEL_0
722 * @arg @ref LL_DMAMUX_CHANNEL_1
723 * @arg @ref LL_DMAMUX_CHANNEL_2
724 * @arg @ref LL_DMAMUX_CHANNEL_3
725 * @arg @ref LL_DMAMUX_CHANNEL_4
726 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
727 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
728 *
729 * @arg All the next values are only available on chip which support DMA2:
730 * @arg @ref LL_DMAMUX_CHANNEL_7
731 * @arg @ref LL_DMAMUX_CHANNEL_8
732 * @arg @ref LL_DMAMUX_CHANNEL_9
733 * @arg @ref LL_DMAMUX_CHANNEL_10
734 * @arg @ref LL_DMAMUX_CHANNEL_11
735 * @retval Returned value can be one of the following values:
736 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
737 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
738 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
739 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
740 */
741__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
742{
743 (void)(DMAMUXx);
744 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
745}
746
747/**
748 * @brief Enable the Event Generation on DMAMUX channel x.
749 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
750 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
751 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
752 * @param DMAMUXx DMAMUXx Instance
753 * @param Channel This parameter can be one of the following values:
754 * @arg @ref LL_DMAMUX_CHANNEL_0
755 * @arg @ref LL_DMAMUX_CHANNEL_1
756 * @arg @ref LL_DMAMUX_CHANNEL_2
757 * @arg @ref LL_DMAMUX_CHANNEL_3
758 * @arg @ref LL_DMAMUX_CHANNEL_4
759 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
760 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
761 *
762 * @arg All the next values are only available on chip which support DMA2:
763 * @arg @ref LL_DMAMUX_CHANNEL_7
764 * @arg @ref LL_DMAMUX_CHANNEL_8
765 * @arg @ref LL_DMAMUX_CHANNEL_9
766 * @arg @ref LL_DMAMUX_CHANNEL_10
767 * @arg @ref LL_DMAMUX_CHANNEL_11
768 * @retval None
769 */
770__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
771{
772 (void)(DMAMUXx);
773 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
774}
775
776/**
777 * @brief Disable the Event Generation on DMAMUX channel x.
778 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
779 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
780 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
781 * @param DMAMUXx DMAMUXx Instance
782 * @param Channel This parameter can be one of the following values:
783 * @arg @ref LL_DMAMUX_CHANNEL_0
784 * @arg @ref LL_DMAMUX_CHANNEL_1
785 * @arg @ref LL_DMAMUX_CHANNEL_2
786 * @arg @ref LL_DMAMUX_CHANNEL_3
787 * @arg @ref LL_DMAMUX_CHANNEL_4
788 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
789 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
790 *
791 * @arg All the next values are only available on chip which support DMA2:
792 * @arg @ref LL_DMAMUX_CHANNEL_7
793 * @arg @ref LL_DMAMUX_CHANNEL_8
794 * @arg @ref LL_DMAMUX_CHANNEL_9
795 * @arg @ref LL_DMAMUX_CHANNEL_10
796 * @arg @ref LL_DMAMUX_CHANNEL_11
797 * @retval None
798 */
799__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
800{
801 (void)(DMAMUXx);
802 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
803}
804
805/**
806 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
807 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
808 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
809 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
810 * @param DMAMUXx DMAMUXx Instance
811 * @param Channel This parameter can be one of the following values:
812 * @arg @ref LL_DMAMUX_CHANNEL_0
813 * @arg @ref LL_DMAMUX_CHANNEL_1
814 * @arg @ref LL_DMAMUX_CHANNEL_2
815 * @arg @ref LL_DMAMUX_CHANNEL_3
816 * @arg @ref LL_DMAMUX_CHANNEL_4
817 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
818 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
819 *
820 * @arg All the next values are only available on chip which support DMA2:
821 * @arg @ref LL_DMAMUX_CHANNEL_7
822 * @arg @ref LL_DMAMUX_CHANNEL_8
823 * @arg @ref LL_DMAMUX_CHANNEL_9
824 * @arg @ref LL_DMAMUX_CHANNEL_10
825 * @arg @ref LL_DMAMUX_CHANNEL_11
826 * @retval State of bit (1 or 0).
827 */
828__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
829{
830 (void)(DMAMUXx);
831 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
832}
833
834/**
835 * @brief Enable the synchronization mode.
836 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
837 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
838 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
839 * @param DMAMUXx DMAMUXx Instance
840 * @param Channel This parameter can be one of the following values:
841 * @arg @ref LL_DMAMUX_CHANNEL_0
842 * @arg @ref LL_DMAMUX_CHANNEL_1
843 * @arg @ref LL_DMAMUX_CHANNEL_2
844 * @arg @ref LL_DMAMUX_CHANNEL_3
845 * @arg @ref LL_DMAMUX_CHANNEL_4
846 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
847 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
848 *
849 * @arg All the next values are only available on chip which support DMA2:
850 * @arg @ref LL_DMAMUX_CHANNEL_7
851 * @arg @ref LL_DMAMUX_CHANNEL_8
852 * @arg @ref LL_DMAMUX_CHANNEL_9
853 * @arg @ref LL_DMAMUX_CHANNEL_10
854 * @arg @ref LL_DMAMUX_CHANNEL_11
855 * @retval None
856 */
857__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
858{
859 (void)(DMAMUXx);
860 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
861}
862
863/**
864 * @brief Disable the synchronization mode.
865 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
866 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
867 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
868 * @param DMAMUXx DMAMUXx Instance
869 * @param Channel This parameter can be one of the following values:
870 * @arg @ref LL_DMAMUX_CHANNEL_0
871 * @arg @ref LL_DMAMUX_CHANNEL_1
872 * @arg @ref LL_DMAMUX_CHANNEL_2
873 * @arg @ref LL_DMAMUX_CHANNEL_3
874 * @arg @ref LL_DMAMUX_CHANNEL_4
875 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
876 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
877 *
878 * @arg All the next values are only available on chip which support DMA2:
879 * @arg @ref LL_DMAMUX_CHANNEL_7
880 * @arg @ref LL_DMAMUX_CHANNEL_8
881 * @arg @ref LL_DMAMUX_CHANNEL_9
882 * @arg @ref LL_DMAMUX_CHANNEL_10
883 * @arg @ref LL_DMAMUX_CHANNEL_11
884 * @retval None
885 */
886__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
887{
888 (void)(DMAMUXx);
889 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
890}
891
892/**
893 * @brief Check if the synchronization mode is enabled or disabled.
894 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
895 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
896 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
897 * @param DMAMUXx DMAMUXx Instance
898 * @param Channel This parameter can be one of the following values:
899 * @arg @ref LL_DMAMUX_CHANNEL_0
900 * @arg @ref LL_DMAMUX_CHANNEL_1
901 * @arg @ref LL_DMAMUX_CHANNEL_2
902 * @arg @ref LL_DMAMUX_CHANNEL_3
903 * @arg @ref LL_DMAMUX_CHANNEL_4
904 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
905 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
906 *
907 * @arg All the next values are only available on chip which support DMA2:
908 * @arg @ref LL_DMAMUX_CHANNEL_7
909 * @arg @ref LL_DMAMUX_CHANNEL_8
910 * @arg @ref LL_DMAMUX_CHANNEL_9
911 * @arg @ref LL_DMAMUX_CHANNEL_10
912 * @arg @ref LL_DMAMUX_CHANNEL_11
913 * @retval State of bit (1 or 0).
914 */
915__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
916{
917 (void)(DMAMUXx);
918 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
919}
920
921/**
922 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
923 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
924 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
925 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
926 * @param DMAMUXx DMAMUXx Instance
927 * @param Channel This parameter can be one of the following values:
928 * @arg @ref LL_DMAMUX_CHANNEL_0
929 * @arg @ref LL_DMAMUX_CHANNEL_1
930 * @arg @ref LL_DMAMUX_CHANNEL_2
931 * @arg @ref LL_DMAMUX_CHANNEL_3
932 * @arg @ref LL_DMAMUX_CHANNEL_4
933 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
934 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
935 *
936 * @arg All the next values are only available on chip which support DMA2:
937 * @arg @ref LL_DMAMUX_CHANNEL_7
938 * @arg @ref LL_DMAMUX_CHANNEL_8
939 * @arg @ref LL_DMAMUX_CHANNEL_9
940 * @arg @ref LL_DMAMUX_CHANNEL_10
941 * @arg @ref LL_DMAMUX_CHANNEL_11
942 * @param SyncID This parameter can be one of the following values:
943 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
944 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
945 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
946 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
947 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
948 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
949 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
950 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
951 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
952 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
953 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
954 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
955 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
956 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
957 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
958 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
959 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
960 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
961 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
962 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
963 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
964 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
965 * @arg @ref LL_DMAMUX_SYNC_TIM14_OC
966 * @retval None
967 */
968__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
969{
970 (void)(DMAMUXx);
971 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
972}
973
974/**
975 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
976 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
977 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
978 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
979 * @param DMAMUXx DMAMUXx Instance
980 * @param Channel This parameter can be one of the following values:
981 * @arg @ref LL_DMAMUX_CHANNEL_0
982 * @arg @ref LL_DMAMUX_CHANNEL_1
983 * @arg @ref LL_DMAMUX_CHANNEL_2
984 * @arg @ref LL_DMAMUX_CHANNEL_3
985 * @arg @ref LL_DMAMUX_CHANNEL_4
986 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
987 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
988 *
989 * @arg All the next values are only available on chip which support DMA2:
990 * @arg @ref LL_DMAMUX_CHANNEL_7
991 * @arg @ref LL_DMAMUX_CHANNEL_8
992 * @arg @ref LL_DMAMUX_CHANNEL_9
993 * @arg @ref LL_DMAMUX_CHANNEL_10
994 * @arg @ref LL_DMAMUX_CHANNEL_11
995 * @retval Returned value can be one of the following values:
996 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
997 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
998 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
999 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
1000 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
1001 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
1002 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
1003 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
1004 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
1005 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
1006 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
1007 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
1008 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
1009 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
1010 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
1011 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
1012 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
1013 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
1014 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
1015 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
1016 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
1017 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
1018 * @arg @ref LL_DMAMUX_SYNC_TIM14_OC
1019 */
1020__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1021{
1022 (void)(DMAMUXx);
1023 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
1024}
1025
1026/**
1027 * @brief Enable the Request Generator.
1028 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1029 * @param DMAMUXx DMAMUXx Instance
1030 * @param RequestGenChannel This parameter can be one of the following values:
1031 * @arg @ref LL_DMAMUX_REQ_GEN_0
1032 * @arg @ref LL_DMAMUX_REQ_GEN_1
1033 * @arg @ref LL_DMAMUX_REQ_GEN_2
1034 * @arg @ref LL_DMAMUX_REQ_GEN_3
1035 * @retval None
1036 */
1037__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1038{
1039 (void)(DMAMUXx);
1040 SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1041 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
1042}
1043
1044/**
1045 * @brief Disable the Request Generator.
1046 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1047 * @param DMAMUXx DMAMUXx Instance
1048 * @param RequestGenChannel This parameter can be one of the following values:
1049 * @arg @ref LL_DMAMUX_REQ_GEN_0
1050 * @arg @ref LL_DMAMUX_REQ_GEN_1
1051 * @arg @ref LL_DMAMUX_REQ_GEN_2
1052 * @arg @ref LL_DMAMUX_REQ_GEN_3
1053 * @retval None
1054 */
1055__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1056{
1057 (void)(DMAMUXx);
1058 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1059 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
1060}
1061
1062/**
1063 * @brief Check if the Request Generator is enabled or disabled.
1064 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1065 * @param DMAMUXx DMAMUXx Instance
1066 * @param RequestGenChannel This parameter can be one of the following values:
1067 * @arg @ref LL_DMAMUX_REQ_GEN_0
1068 * @arg @ref LL_DMAMUX_REQ_GEN_1
1069 * @arg @ref LL_DMAMUX_REQ_GEN_2
1070 * @arg @ref LL_DMAMUX_REQ_GEN_3
1071 * @retval State of bit (1 or 0).
1072 */
1073__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1074{
1075 (void)(DMAMUXx);
1076 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1077 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1078}
1079
1080/**
1081 * @brief Set the polarity of the signal on which the DMA request is generated.
1082 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1083 * @param DMAMUXx DMAMUXx Instance
1084 * @param RequestGenChannel This parameter can be one of the following values:
1085 * @arg @ref LL_DMAMUX_REQ_GEN_0
1086 * @arg @ref LL_DMAMUX_REQ_GEN_1
1087 * @arg @ref LL_DMAMUX_REQ_GEN_2
1088 * @arg @ref LL_DMAMUX_REQ_GEN_3
1089 * @param Polarity This parameter can be one of the following values:
1090 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1091 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1092 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1093 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1094 * @retval None
1095 */
1096__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1097 uint32_t Polarity)
1098{
1099 (void)(DMAMUXx);
1100 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1101 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1102}
1103
1104/**
1105 * @brief Get the polarity of the signal on which the DMA request is generated.
1106 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1107 * @param DMAMUXx DMAMUXx Instance
1108 * @param RequestGenChannel This parameter can be one of the following values:
1109 * @arg @ref LL_DMAMUX_REQ_GEN_0
1110 * @arg @ref LL_DMAMUX_REQ_GEN_1
1111 * @arg @ref LL_DMAMUX_REQ_GEN_2
1112 * @arg @ref LL_DMAMUX_REQ_GEN_3
1113 * @retval Returned value can be one of the following values:
1114 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1115 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1116 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1117 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1118 */
1119__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1120{
1121 (void)(DMAMUXx);
1122 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
1123 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
1124}
1125
1126/**
1127 * @brief Set the number of DMA request that will be autorized after a generation event.
1128 * @note This field can only be written when Generator is disabled.
1129 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1130 * @param DMAMUXx DMAMUXx Instance
1131 * @param RequestGenChannel This parameter can be one of the following values:
1132 * @arg @ref LL_DMAMUX_REQ_GEN_0
1133 * @arg @ref LL_DMAMUX_REQ_GEN_1
1134 * @arg @ref LL_DMAMUX_REQ_GEN_2
1135 * @arg @ref LL_DMAMUX_REQ_GEN_3
1136 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1137 * @retval None
1138 */
1139__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1140 uint32_t RequestNb)
1141{
1142 (void)(DMAMUXx);
1143 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1144 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1145}
1146
1147/**
1148 * @brief Get the number of DMA request that will be autorized after a generation event.
1149 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1150 * @param DMAMUXx DMAMUXx Instance
1151 * @param RequestGenChannel This parameter can be one of the following values:
1152 * @arg @ref LL_DMAMUX_REQ_GEN_0
1153 * @arg @ref LL_DMAMUX_REQ_GEN_1
1154 * @arg @ref LL_DMAMUX_REQ_GEN_2
1155 * @arg @ref LL_DMAMUX_REQ_GEN_3
1156 * @retval Between Min_Data = 1 and Max_Data = 32
1157 */
1158__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1159{
1160 (void)(DMAMUXx);
1161 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
1162 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1163}
1164
1165/**
1166 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1167 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1168 * @param DMAMUXx DMAMUXx Instance
1169 * @param RequestGenChannel This parameter can be one of the following values:
1170 * @arg @ref LL_DMAMUX_REQ_GEN_0
1171 * @arg @ref LL_DMAMUX_REQ_GEN_1
1172 * @arg @ref LL_DMAMUX_REQ_GEN_2
1173 * @arg @ref LL_DMAMUX_REQ_GEN_3
1174 * @param RequestSignalID This parameter can be one of the following values:
1175 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1176 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1177 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1178 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1179 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1180 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1181 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1182 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1183 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1184 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1185 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1186 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1187 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1188 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1189 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1190 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1191 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1192 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1193 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
1194 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
1195 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1196 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1197 * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
1198 * @retval None
1199 */
1200__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
1201 uint32_t RequestSignalID)
1202{
1203 (void)(DMAMUXx);
1204 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
1205 (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1206}
1207
1208/**
1209 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1210 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1211 * @param DMAMUXx DMAMUXx Instance
1212 * @param RequestGenChannel This parameter can be one of the following values:
1213 * @arg @ref LL_DMAMUX_REQ_GEN_0
1214 * @arg @ref LL_DMAMUX_REQ_GEN_1
1215 * @arg @ref LL_DMAMUX_REQ_GEN_2
1216 * @arg @ref LL_DMAMUX_REQ_GEN_3
1217 * @retval Returned value can be one of the following values:
1218 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1219 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1220 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1221 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1222 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1223 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1224 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1225 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1226 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1227 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1228 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1229 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1230 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1231 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1232 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1233 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1234 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1235 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1236 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
1237 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
1238 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1239 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1240 * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
1241 */
1242__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1243{
1244 (void)(DMAMUXx);
1245 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 +
1246 (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
1247}
1248
1249/**
1250 * @}
1251 */
1252
1253/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1254 * @{
1255 */
1256
1257/**
1258 * @brief Get Synchronization Event Overrun Flag Channel 0.
1259 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1260 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1261 * @retval State of bit (1 or 0).
1262 */
1263__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1264{
1265 (void)(DMAMUXx);
1266 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1267}
1268
1269/**
1270 * @brief Get Synchronization Event Overrun Flag Channel 1.
1271 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1272 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1273 * @retval State of bit (1 or 0).
1274 */
1275__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1276{
1277 (void)(DMAMUXx);
1278 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1279}
1280
1281/**
1282 * @brief Get Synchronization Event Overrun Flag Channel 2.
1283 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1284 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1285 * @retval State of bit (1 or 0).
1286 */
1287__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1288{
1289 (void)(DMAMUXx);
1290 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1291}
1292
1293/**
1294 * @brief Get Synchronization Event Overrun Flag Channel 3.
1295 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1296 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1297 * @retval State of bit (1 or 0).
1298 */
1299__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1300{
1301 (void)(DMAMUXx);
1302 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1303}
1304
1305/**
1306 * @brief Get Synchronization Event Overrun Flag Channel 4.
1307 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1308 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1309 * @retval State of bit (1 or 0).
1310 */
1311__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
1312{
1313 (void)(DMAMUXx);
1314 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1315}
1316
1317#if defined(DMAMUX1_Channel5)
1318/**
1319 * @brief Get Synchronization Event Overrun Flag Channel 5.
1320 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1321 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1322 * @retval State of bit (1 or 0).
1323 */
1324__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
1325{
1326 (void)(DMAMUXx);
1327 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1328}
1329
1330#endif /* DMAMUX1_Channel5 */
1331#if defined(DMAMUX1_Channel6)
1332/**
1333 * @brief Get Synchronization Event Overrun Flag Channel 6.
1334 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1335 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1336 * @retval State of bit (1 or 0).
1337 */
1338__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
1339{
1340 (void)(DMAMUXx);
1341 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1342}
1343
1344#endif /* DMAMUX1_Channel6 */
1345#if defined(DMAMUX1_Channel7)
1346/**
1347 * @brief Get Synchronization Event Overrun Flag Channel 7.
1348 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1349 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1350 * @retval State of bit (1 or 0).
1351 */
1352__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
1353{
1354 (void)(DMAMUXx);
1355 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1356}
1357
1358#endif /* DMAMUX1_Channel7 */
1359#if defined(DMAMUX1_Channel8)
1360/**
1361 * @brief Get Synchronization Event Overrun Flag Channel 8.
1362 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1363 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1364 * @retval State of bit (1 or 0).
1365 */
1366__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
1367{
1368 (void)(DMAMUXx);
1369 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1370}
1371
1372#endif /* DMAMUX1_Channel8 */
1373#if defined(DMAMUX1_Channel9)
1374/**
1375 * @brief Get Synchronization Event Overrun Flag Channel 9.
1376 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1377 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1378 * @retval State of bit (1 or 0).
1379 */
1380__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
1381{
1382 (void)(DMAMUXx);
1383 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1384}
1385
1386#endif /* DMAMUX1_Channel9 */
1387#if defined(DMAMUX1_Channel10)
1388/**
1389 * @brief Get Synchronization Event Overrun Flag Channel 10.
1390 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1391 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1392 * @retval State of bit (1 or 0).
1393 */
1394__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
1395{
1396 (void)(DMAMUXx);
1397 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1398}
1399
1400#endif /* DMAMUX1_Channel10 */
1401#if defined(DMAMUX1_Channel11)
1402/**
1403 * @brief Get Synchronization Event Overrun Flag Channel 11.
1404 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1405 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1406 * @retval State of bit (1 or 0).
1407 */
1408__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
1409{
1410 (void)(DMAMUXx);
1411 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1412}
1413
1414#endif /* DMAMUX1_Channel11 */
1415/**
1416 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1417 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1418 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1419 * @retval State of bit (1 or 0).
1420 */
1421__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1422{
1423 (void)(DMAMUXx);
1424 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1425}
1426
1427/**
1428 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1429 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1430 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1431 * @retval State of bit (1 or 0).
1432 */
1433__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1434{
1435 (void)(DMAMUXx);
1436 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1437}
1438
1439/**
1440 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1441 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1442 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1443 * @retval State of bit (1 or 0).
1444 */
1445__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1446{
1447 (void)(DMAMUXx);
1448 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1449}
1450
1451/**
1452 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1453 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1454 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1455 * @retval State of bit (1 or 0).
1456 */
1457__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1458{
1459 (void)(DMAMUXx);
1460 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1461}
1462
1463/**
1464 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1465 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1466 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1467 * @retval None
1468 */
1469__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1470{
1471 (void)(DMAMUXx);
1472 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
1473}
1474
1475/**
1476 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1477 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1478 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1479 * @retval None
1480 */
1481__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1482{
1483 (void)(DMAMUXx);
1484 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
1485}
1486
1487/**
1488 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1489 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1490 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1491 * @retval None
1492 */
1493__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1494{
1495 (void)(DMAMUXx);
1496 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
1497}
1498
1499/**
1500 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1501 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1502 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1503 * @retval None
1504 */
1505__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1506{
1507 (void)(DMAMUXx);
1508 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
1509}
1510
1511/**
1512 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1513 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1514 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1515 * @retval None
1516 */
1517__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx)
1518{
1519 (void)(DMAMUXx);
1520 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
1521}
1522
1523#if defined(DMAMUX1_Channel5)
1524/**
1525 * @brief Clear Synchronization Event Overrun Flag Channel 5.
1526 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
1527 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1528 * @retval None
1529 */
1530__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx)
1531{
1532 (void)(DMAMUXx);
1533 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
1534}
1535
1536#endif /* DMAMUX1_Channel5 */
1537#if defined(DMAMUX1_Channel6)
1538/**
1539 * @brief Clear Synchronization Event Overrun Flag Channel 6.
1540 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
1541 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1542 * @retval None
1543 */
1544__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx)
1545{
1546 (void)(DMAMUXx);
1547 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
1548}
1549
1550#endif /* DMAMUX1_Channel6 */
1551#if defined(DMAMUX1_Channel7)
1552/**
1553 * @brief Clear Synchronization Event Overrun Flag Channel 7.
1554 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
1555 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1556 * @retval None
1557 */
1558__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx)
1559{
1560 (void)(DMAMUXx);
1561 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
1562}
1563
1564#endif /* DMAMUX1_Channel7 */
1565#if defined(DMAMUX1_Channel8)
1566/**
1567 * @brief Clear Synchronization Event Overrun Flag Channel 8.
1568 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
1569 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1570 * @retval None
1571 */
1572__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx)
1573{
1574 (void)(DMAMUXx);
1575 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
1576}
1577
1578#endif /* DMAMUX1_Channel8 */
1579#if defined(DMAMUX1_Channel9)
1580/**
1581 * @brief Clear Synchronization Event Overrun Flag Channel 9.
1582 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
1583 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1584 * @retval None
1585 */
1586__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx)
1587{
1588 (void)(DMAMUXx);
1589 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
1590}
1591
1592#endif /* DMAMUX1_Channel9 */
1593#if defined(DMAMUX1_Channel10)
1594/**
1595 * @brief Clear Synchronization Event Overrun Flag Channel 10.
1596 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
1597 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1598 * @retval None
1599 */
1600__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx)
1601{
1602 (void)(DMAMUXx);
1603 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
1604}
1605
1606#endif /* DMAMUX1_Channel10 */
1607#if defined(DMAMUX1_Channel11)
1608/**
1609 * @brief Clear Synchronization Event Overrun Flag Channel 11.
1610 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
1611 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1612 * @retval None
1613 */
1614__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx)
1615{
1616 (void)(DMAMUXx);
1617 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
1618}
1619
1620#endif /* DMAMUX1_Channel11 */
1621/**
1622 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
1623 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
1624 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1625 * @retval None
1626 */
1627__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx)
1628{
1629 (void)(DMAMUXx);
1630 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
1631}
1632
1633/**
1634 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
1635 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
1636 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1637 * @retval None
1638 */
1639__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx)
1640{
1641 (void)(DMAMUXx);
1642 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
1643}
1644
1645/**
1646 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
1647 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
1648 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1649 * @retval None
1650 */
1651__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx)
1652{
1653 (void)(DMAMUXx);
1654 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
1655}
1656
1657/**
1658 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
1659 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
1660 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1661 * @retval None
1662 */
1663__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx)
1664{
1665 (void)(DMAMUXx);
1666 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
1667}
1668
1669/**
1670 * @}
1671 */
1672
1673/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
1674 * @{
1675 */
1676
1677/**
1678 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1679 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1680 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1681 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
1682 * @param DMAMUXx DMAMUXx Instance
1683 * @param Channel This parameter can be one of the following values:
1684 * @arg @ref LL_DMAMUX_CHANNEL_0
1685 * @arg @ref LL_DMAMUX_CHANNEL_1
1686 * @arg @ref LL_DMAMUX_CHANNEL_2
1687 * @arg @ref LL_DMAMUX_CHANNEL_3
1688 * @arg @ref LL_DMAMUX_CHANNEL_4
1689 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
1690 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
1691 *
1692 * @arg All the next values are only available on chip which support DMA2:
1693 * @arg @ref LL_DMAMUX_CHANNEL_7
1694 * @arg @ref LL_DMAMUX_CHANNEL_8
1695 * @arg @ref LL_DMAMUX_CHANNEL_9
1696 * @arg @ref LL_DMAMUX_CHANNEL_10
1697 * @arg @ref LL_DMAMUX_CHANNEL_11
1698 * @retval None
1699 */
1700__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1701{
1702 (void)(DMAMUXx);
1703 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1704}
1705
1706/**
1707 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1708 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1709 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1710 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
1711 * @param DMAMUXx DMAMUXx Instance
1712 * @param Channel This parameter can be one of the following values:
1713 * @arg @ref LL_DMAMUX_CHANNEL_0
1714 * @arg @ref LL_DMAMUX_CHANNEL_1
1715 * @arg @ref LL_DMAMUX_CHANNEL_2
1716 * @arg @ref LL_DMAMUX_CHANNEL_3
1717 * @arg @ref LL_DMAMUX_CHANNEL_4
1718 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
1719 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
1720 *
1721 * @arg All the next values are only available on chip which support DMA2:
1722 * @arg @ref LL_DMAMUX_CHANNEL_7
1723 * @arg @ref LL_DMAMUX_CHANNEL_8
1724 * @arg @ref LL_DMAMUX_CHANNEL_9
1725 * @arg @ref LL_DMAMUX_CHANNEL_10
1726 * @arg @ref LL_DMAMUX_CHANNEL_11
1727 * @retval None
1728 */
1729__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1730{
1731 (void)(DMAMUXx);
1732 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1733}
1734
1735/**
1736 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1737 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1738 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1739 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
1740 * @param DMAMUXx DMAMUXx Instance
1741 * @param Channel This parameter can be one of the following values:
1742 * @arg @ref LL_DMAMUX_CHANNEL_0
1743 * @arg @ref LL_DMAMUX_CHANNEL_1
1744 * @arg @ref LL_DMAMUX_CHANNEL_2
1745 * @arg @ref LL_DMAMUX_CHANNEL_3
1746 * @arg @ref LL_DMAMUX_CHANNEL_4
1747 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
1748 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
1749 *
1750 * @arg All the next values are only available on chip which support DMA2:
1751 * @arg @ref LL_DMAMUX_CHANNEL_7
1752 * @arg @ref LL_DMAMUX_CHANNEL_8
1753 * @arg @ref LL_DMAMUX_CHANNEL_9
1754 * @arg @ref LL_DMAMUX_CHANNEL_10
1755 * @arg @ref LL_DMAMUX_CHANNEL_11
1756 * @retval State of bit (1 or 0).
1757 */
1758__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1759{
1760 (void)(DMAMUXx);
1761 return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
1762}
1763
1764/**
1765 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1766 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
1767 * @param DMAMUXx DMAMUXx Instance
1768 * @param RequestGenChannel This parameter can be one of the following values:
1769 * @arg @ref LL_DMAMUX_REQ_GEN_0
1770 * @arg @ref LL_DMAMUX_REQ_GEN_1
1771 * @arg @ref LL_DMAMUX_REQ_GEN_2
1772 * @arg @ref LL_DMAMUX_REQ_GEN_3
1773 * @retval None
1774 */
1775__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1776{
1777 (void)(DMAMUXx);
1778 SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1779}
1780
1781/**
1782 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1783 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
1784 * @param DMAMUXx DMAMUXx Instance
1785 * @param RequestGenChannel This parameter can be one of the following values:
1786 * @arg @ref LL_DMAMUX_REQ_GEN_0
1787 * @arg @ref LL_DMAMUX_REQ_GEN_1
1788 * @arg @ref LL_DMAMUX_REQ_GEN_2
1789 * @arg @ref LL_DMAMUX_REQ_GEN_3
1790 * @retval None
1791 */
1792__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1793{
1794 (void)(DMAMUXx);
1795 CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1796}
1797
1798/**
1799 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1800 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
1801 * @param DMAMUXx DMAMUXx Instance
1802 * @param RequestGenChannel This parameter can be one of the following values:
1803 * @arg @ref LL_DMAMUX_REQ_GEN_0
1804 * @arg @ref LL_DMAMUX_REQ_GEN_1
1805 * @arg @ref LL_DMAMUX_REQ_GEN_2
1806 * @arg @ref LL_DMAMUX_REQ_GEN_3
1807 * @retval State of bit (1 or 0).
1808 */
1809__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1810{
1811 (void)(DMAMUXx);
1812 return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
1813}
1814
1815/**
1816 * @}
1817 */
1818
1819/**
1820 * @}
1821 */
1822
1823/**
1824 * @}
1825 */
1826
1827#endif /* DMAMUX1 */
1828
1829/**
1830 * @}
1831 */
1832
1833#ifdef __cplusplus
1834}
1835#endif
1836
1837#endif /* STM32G0xx_LL_DMAMUX_H */
1838
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