Context Navigation

stm32g0xx_hal_spi.h

Last change on this file was 6, checked in by f.jahn, 8 months ago

File size: 37.8 KB

Line
1	/**
2	******************************************************************************
3	* @file stm32g0xx_hal_spi.h
4	* @author MCD Application Team
5	* @brief Header file of SPI HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.
11	*
12	* This software is licensed under terms that can be found in the LICENSE file
13	* in the root directory of this software component.
14	* If no LICENSE file comes with this software, it is provided AS-IS.
15	*
16	******************************************************************************
17	*/
18
19	/* Define to prevent recursive inclusion -------------------------------------*/
20	#ifndef STM32G0xx_HAL_SPI_H
21	#define STM32G0xx_HAL_SPI_H
22
23	#ifdef __cplusplus
24	extern "C" {
25	#endif
26
27	/* Includes ------------------------------------------------------------------*/
28	#include "stm32g0xx_hal_def.h"
29
30	/** @addtogroup STM32G0xx_HAL_Driver
31	* @{
32	*/
33
34	/** @addtogroup SPI
35	* @{
36	*/
37
38	/* Exported types ------------------------------------------------------------*/
39	/** @defgroup SPI_Exported_Types SPI Exported Types
40	* @{
41	*/
42
43	/**
44	* @brief SPI Configuration Structure definition
45	*/
46	typedef struct
47	{
48	uint32_t Mode; /*!< Specifies the SPI operating mode.
49	This parameter can be a value of @ref SPI_Mode */
50
51	uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
52	This parameter can be a value of @ref SPI_Direction */
53
54	uint32_t DataSize; /*!< Specifies the SPI data size.
55	This parameter can be a value of @ref SPI_Data_Size */
56
57	uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
58	This parameter can be a value of @ref SPI_Clock_Polarity */
59
60	uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
61	This parameter can be a value of @ref SPI_Clock_Phase */
62
63	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
64	hardware (NSS pin) or by software using the SSI bit.
65	This parameter can be a value of @ref SPI_Slave_Select_management */
66
67	uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
68	used to configure the transmit and receive SCK clock.
69	This parameter can be a value of @ref SPI_BaudRate_Prescaler
70	@note The communication clock is derived from the master
71	clock. The slave clock does not need to be set. */
72
73	uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
74	This parameter can be a value of @ref SPI_MSB_LSB_transmission */
75
76	uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
77	This parameter can be a value of @ref SPI_TI_mode */
78
79	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
80	This parameter can be a value of @ref SPI_CRC_Calculation */
81
82	uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
83	This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
84
85	uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
86	CRC Length is only used with Data8 and Data16, not other data size
87	This parameter can be a value of @ref SPI_CRC_length */
88
89	uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
90	This parameter can be a value of @ref SPI_NSSP_Mode
91	This mode is activated by the NSSP bit in the SPIx_CR2 register and
92	it takes effect only if the SPI interface is configured as Motorola SPI
93	master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
94	CPOL setting is ignored).. */
95	} SPI_InitTypeDef;
96
97	/**
98	* @brief HAL SPI State structure definition
99	*/
100	typedef enum
101	{
102	HAL_SPI_STATE_RESET = 0x00U, /!< Peripheral not Initialized /
103	HAL_SPI_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
104	HAL_SPI_STATE_BUSY = 0x02U, /!< an internal process is ongoing /
105	HAL_SPI_STATE_BUSY_TX = 0x03U, /!< Data Transmission process is ongoing /
106	HAL_SPI_STATE_BUSY_RX = 0x04U, /!< Data Reception process is ongoing /
107	HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /!< Data Transmission and Reception process is ongoing /
108	HAL_SPI_STATE_ERROR = 0x06U, /!< SPI error state /
109	HAL_SPI_STATE_ABORT = 0x07U /!< SPI abort is ongoing /
110	} HAL_SPI_StateTypeDef;
111
112	/**
113	* @brief SPI handle Structure definition
114	*/
115	typedef struct __SPI_HandleTypeDef
116	{
117	SPI_TypeDef Instance; /!< SPI registers base address */
118
119	SPI_InitTypeDef Init; /!< SPI communication parameters /
120
121	uint8_t pTxBuffPtr; /!< Pointer to SPI Tx transfer Buffer */
122
123	uint16_t TxXferSize; /!< SPI Tx Transfer size /
124
125	__IO uint16_t TxXferCount; /!< SPI Tx Transfer Counter /
126
127	uint8_t pRxBuffPtr; /!< Pointer to SPI Rx transfer Buffer */
128
129	uint16_t RxXferSize; /!< SPI Rx Transfer size /
130
131	__IO uint16_t RxXferCount; /!< SPI Rx Transfer Counter /
132
133	uint32_t CRCSize; /!< SPI CRC size used for the transfer /
134
135	void (RxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Rx ISR /
136
137	void (TxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Tx ISR /
138
139	DMA_HandleTypeDef hdmatx; /!< SPI Tx DMA Handle parameters */
140
141	DMA_HandleTypeDef hdmarx; /!< SPI Rx DMA Handle parameters */
142
143	HAL_LockTypeDef Lock; /!< Locking object /
144
145	__IO HAL_SPI_StateTypeDef State; /!< SPI communication state /
146
147	__IO uint32_t ErrorCode; /!< SPI Error code /
148
149	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
150	void (* TxCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Tx Completed callback */
151	void (* RxCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Rx Completed callback */
152	void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI TxRx Completed callback */
153	void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Tx Half Completed callback */
154	void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Rx Half Completed callback */
155	void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI TxRx Half Completed callback */
156	void (* ErrorCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Error callback */
157	void (* AbortCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Abort callback */
158	void (* MspInitCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Msp Init callback */
159	void (* MspDeInitCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Msp DeInit callback */
160
161	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
162	} SPI_HandleTypeDef;
163
164	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
165	/**
166	* @brief HAL SPI Callback ID enumeration definition
167	*/
168	typedef enum
169	{
170	HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /!< SPI Tx Completed callback ID /
171	HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /!< SPI Rx Completed callback ID /
172	HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /!< SPI TxRx Completed callback ID /
173	HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /!< SPI Tx Half Completed callback ID /
174	HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /!< SPI Rx Half Completed callback ID /
175	HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /!< SPI TxRx Half Completed callback ID /
176	HAL_SPI_ERROR_CB_ID = 0x06U, /!< SPI Error callback ID /
177	HAL_SPI_ABORT_CB_ID = 0x07U, /!< SPI Abort callback ID /
178	HAL_SPI_MSPINIT_CB_ID = 0x08U, /!< SPI Msp Init callback ID /
179	HAL_SPI_MSPDEINIT_CB_ID = 0x09U /!< SPI Msp DeInit callback ID /
180
181	} HAL_SPI_CallbackIDTypeDef;
182
183	/**
184	* @brief HAL SPI Callback pointer definition
185	*/
186	typedef void (pSPI_CallbackTypeDef)(SPI_HandleTypeDef hspi); /!< pointer to an SPI callback function /
187
188	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
189	/**
190	* @}
191	*/
192
193	/* Exported constants --------------------------------------------------------*/
194	/** @defgroup SPI_Exported_Constants SPI Exported Constants
195	* @{
196	*/
197
198	/** @defgroup SPI_Error_Code SPI Error Code
199	* @{
200	*/
201	#define HAL_SPI_ERROR_NONE (0x00000000U) /!< No error /
202	#define HAL_SPI_ERROR_MODF (0x00000001U) /!< MODF error /
203	#define HAL_SPI_ERROR_CRC (0x00000002U) /!< CRC error /
204	#define HAL_SPI_ERROR_OVR (0x00000004U) /!< OVR error /
205	#define HAL_SPI_ERROR_FRE (0x00000008U) /!< FRE error /
206	#define HAL_SPI_ERROR_DMA (0x00000010U) /!< DMA transfer error /
207	#define HAL_SPI_ERROR_FLAG (0x00000020U) /!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag /
208	#define HAL_SPI_ERROR_ABORT (0x00000040U) /!< Error during SPI Abort procedure /
209	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
210	#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /!< Invalid Callback error /
211	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
212	/**
213	* @}
214	*/
215
216	/** @defgroup SPI_Mode SPI Mode
217	* @{
218	*/
219	#define SPI_MODE_SLAVE (0x00000000U)
220	#define SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI)
221	/**
222	* @}
223	*/
224
225	/** @defgroup SPI_Direction SPI Direction Mode
226	* @{
227	*/
228	#define SPI_DIRECTION_2LINES (0x00000000U)
229	#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
230	#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
231	/**
232	* @}
233	*/
234
235	/** @defgroup SPI_Data_Size SPI Data Size
236	* @{
237	*/
238	#define SPI_DATASIZE_4BIT (0x00000300U)
239	#define SPI_DATASIZE_5BIT (0x00000400U)
240	#define SPI_DATASIZE_6BIT (0x00000500U)
241	#define SPI_DATASIZE_7BIT (0x00000600U)
242	#define SPI_DATASIZE_8BIT (0x00000700U)
243	#define SPI_DATASIZE_9BIT (0x00000800U)
244	#define SPI_DATASIZE_10BIT (0x00000900U)
245	#define SPI_DATASIZE_11BIT (0x00000A00U)
246	#define SPI_DATASIZE_12BIT (0x00000B00U)
247	#define SPI_DATASIZE_13BIT (0x00000C00U)
248	#define SPI_DATASIZE_14BIT (0x00000D00U)
249	#define SPI_DATASIZE_15BIT (0x00000E00U)
250	#define SPI_DATASIZE_16BIT (0x00000F00U)
251	/**
252	* @}
253	*/
254
255	/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
256	* @{
257	*/
258	#define SPI_POLARITY_LOW (0x00000000U)
259	#define SPI_POLARITY_HIGH SPI_CR1_CPOL
260	/**
261	* @}
262	*/
263
264	/** @defgroup SPI_Clock_Phase SPI Clock Phase
265	* @{
266	*/
267	#define SPI_PHASE_1EDGE (0x00000000U)
268	#define SPI_PHASE_2EDGE SPI_CR1_CPHA
269	/**
270	* @}
271	*/
272
273	/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
274	* @{
275	*/
276	#define SPI_NSS_SOFT SPI_CR1_SSM
277	#define SPI_NSS_HARD_INPUT (0x00000000U)
278	#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
279	/**
280	* @}
281	*/
282
283	/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
284	* @{
285	*/
286	#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
287	#define SPI_NSS_PULSE_DISABLE (0x00000000U)
288	/**
289	* @}
290	*/
291
292	/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
293	* @{
294	*/
295	#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
296	#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
297	#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
298	#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0)
299	#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
300	#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0)
301	#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1)
302	#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0)
303	/**
304	* @}
305	*/
306
307	/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
308	* @{
309	*/
310	#define SPI_FIRSTBIT_MSB (0x00000000U)
311	#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
312	/**
313	* @}
314	*/
315
316	/** @defgroup SPI_TI_mode SPI TI Mode
317	* @{
318	*/
319	#define SPI_TIMODE_DISABLE (0x00000000U)
320	#define SPI_TIMODE_ENABLE SPI_CR2_FRF
321	/**
322	* @}
323	*/
324
325	/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
326	* @{
327	*/
328	#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
329	#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
330	/**
331	* @}
332	*/
333
334	/** @defgroup SPI_CRC_length SPI CRC Length
335	* @{
336	* This parameter can be one of the following values:
337	* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
338	* SPI_CRC_LENGTH_8BIT : CRC 8bit
339	* SPI_CRC_LENGTH_16BIT : CRC 16bit
340	*/
341	#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
342	#define SPI_CRC_LENGTH_8BIT (0x00000001U)
343	#define SPI_CRC_LENGTH_16BIT (0x00000002U)
344	/**
345	* @}
346	*/
347
348	/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
349	* @{
350	* This parameter can be one of the following values:
351	* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
352	* RXNE event is generated if the FIFO
353	* level is greater or equal to 1/4(8-bits).
354	* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
355	* level is greater or equal to 1/2(16 bits). */
356	#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
357	#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
358	#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
359	/**
360	* @}
361	*/
362
363	/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
364	* @{
365	*/
366	#define SPI_IT_TXE SPI_CR2_TXEIE
367	#define SPI_IT_RXNE SPI_CR2_RXNEIE
368	#define SPI_IT_ERR SPI_CR2_ERRIE
369	/**
370	* @}
371	*/
372
373	/** @defgroup SPI_Flags_definition SPI Flags Definition
374	* @{
375	*/
376	#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
377	#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
378	#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
379	#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
380	#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
381	#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
382	#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
383	#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
384	#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
385	#define SPI_FLAG_MASK (SPI_SR_RXNE \| SPI_SR_TXE \| SPI_SR_BSY \| SPI_SR_CRCERR\
386	\| SPI_SR_MODF \| SPI_SR_OVR \| SPI_SR_FRE \| SPI_SR_FTLVL \| SPI_SR_FRLVL)
387	/**
388	* @}
389	*/
390
391	/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
392	* @{
393	*/
394	#define SPI_FTLVL_EMPTY (0x00000000U)
395	#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
396	#define SPI_FTLVL_HALF_FULL (0x00001000U)
397	#define SPI_FTLVL_FULL (0x00001800U)
398
399	/**
400	* @}
401	*/
402
403	/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
404	* @{
405	*/
406	#define SPI_FRLVL_EMPTY (0x00000000U)
407	#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
408	#define SPI_FRLVL_HALF_FULL (0x00000400U)
409	#define SPI_FRLVL_FULL (0x00000600U)
410	/**
411	* @}
412	*/
413
414	/**
415	* @}
416	*/
417
418	/* Exported macros -----------------------------------------------------------*/
419	/** @defgroup SPI_Exported_Macros SPI Exported Macros
420	* @{
421	*/
422
423	/** @brief Reset SPI handle state.
424	* @param __HANDLE__ specifies the SPI Handle.
425	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
426	* @retval None
427	*/
428	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
429	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
430	(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
431	(__HANDLE__)->MspInitCallback = NULL; \
432	(__HANDLE__)->MspDeInitCallback = NULL; \
433	} while(0)
434	#else
435	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
436	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
437
438	/** @brief Enable the specified SPI interrupts.
439	* @param __HANDLE__ specifies the SPI Handle.
440	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
441	* @param __INTERRUPT__ specifies the interrupt source to enable.
442	* This parameter can be one of the following values:
443	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
444	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
445	* @arg SPI_IT_ERR: Error interrupt enable
446	* @retval None
447	*/
448	#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
449
450	/** @brief Disable the specified SPI interrupts.
451	* @param __HANDLE__ specifies the SPI handle.
452	* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
453	* @param __INTERRUPT__ specifies the interrupt source to disable.
454	* This parameter can be one of the following values:
455	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
456	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
457	* @arg SPI_IT_ERR: Error interrupt enable
458	* @retval None
459	*/
460	#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
461
462	/** @brief Check whether the specified SPI interrupt source is enabled or not.
463	* @param __HANDLE__ specifies the SPI Handle.
464	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
465	* @param __INTERRUPT__ specifies the SPI interrupt source to check.
466	* This parameter can be one of the following values:
467	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
468	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
469	* @arg SPI_IT_ERR: Error interrupt enable
470	* @retval The new state of __IT__ (TRUE or FALSE).
471	*/
472	#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
473	& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
474
475	/** @brief Check whether the specified SPI flag is set or not.
476	* @param __HANDLE__ specifies the SPI Handle.
477	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
478	* @param __FLAG__ specifies the flag to check.
479	* This parameter can be one of the following values:
480	* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
481	* @arg SPI_FLAG_TXE: Transmit buffer empty flag
482	* @arg SPI_FLAG_CRCERR: CRC error flag
483	* @arg SPI_FLAG_MODF: Mode fault flag
484	* @arg SPI_FLAG_OVR: Overrun flag
485	* @arg SPI_FLAG_BSY: Busy flag
486	* @arg SPI_FLAG_FRE: Frame format error flag
487	* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
488	* @arg SPI_FLAG_FRLVL: SPI fifo reception level
489	* @retval The new state of __FLAG__ (TRUE or FALSE).
490	*/
491	#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
492
493	/** @brief Clear the SPI CRCERR pending flag.
494	* @param __HANDLE__ specifies the SPI Handle.
495	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
496	* @retval None
497	*/
498	#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
499
500	/** @brief Clear the SPI MODF pending flag.
501	* @param __HANDLE__ specifies the SPI Handle.
502	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
503	* @retval None
504	*/
505	#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
506	do{ \
507	__IO uint32_t tmpreg_modf = 0x00U; \
508	tmpreg_modf = (__HANDLE__)->Instance->SR; \
509	CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
510	UNUSED(tmpreg_modf); \
511	} while(0U)
512
513	/** @brief Clear the SPI OVR pending flag.
514	* @param __HANDLE__ specifies the SPI Handle.
515	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
516	* @retval None
517	*/
518	#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
519	do{ \
520	__IO uint32_t tmpreg_ovr = 0x00U; \
521	tmpreg_ovr = (__HANDLE__)->Instance->DR; \
522	tmpreg_ovr = (__HANDLE__)->Instance->SR; \
523	UNUSED(tmpreg_ovr); \
524	} while(0U)
525
526	/** @brief Clear the SPI FRE pending flag.
527	* @param __HANDLE__ specifies the SPI Handle.
528	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
529	* @retval None
530	*/
531	#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
532	do{ \
533	__IO uint32_t tmpreg_fre = 0x00U; \
534	tmpreg_fre = (__HANDLE__)->Instance->SR; \
535	UNUSED(tmpreg_fre); \
536	}while(0U)
537
538	/** @brief Enable the SPI peripheral.
539	* @param __HANDLE__ specifies the SPI Handle.
540	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
541	* @retval None
542	*/
543	#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
544
545	/** @brief Disable the SPI peripheral.
546	* @param __HANDLE__ specifies the SPI Handle.
547	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
548	* @retval None
549	*/
550	#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
551
552	/**
553	* @}
554	*/
555
556	/* Private macros ------------------------------------------------------------*/
557	/** @defgroup SPI_Private_Macros SPI Private Macros
558	* @{
559	*/
560
561	/** @brief Set the SPI transmit-only mode.
562	* @param __HANDLE__ specifies the SPI Handle.
563	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
564	* @retval None
565	*/
566	#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
567
568	/** @brief Set the SPI receive-only mode.
569	* @param __HANDLE__ specifies the SPI Handle.
570	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
571	* @retval None
572	*/
573	#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
574
575	/** @brief Reset the CRC calculation of the SPI.
576	* @param __HANDLE__ specifies the SPI Handle.
577	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
578	* @retval None
579	*/
580	#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
581	SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
582
583	/** @brief Check whether the specified SPI flag is set or not.
584	* @param __SR__ copy of SPI SR register.
585	* @param __FLAG__ specifies the flag to check.
586	* This parameter can be one of the following values:
587	* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
588	* @arg SPI_FLAG_TXE: Transmit buffer empty flag
589	* @arg SPI_FLAG_CRCERR: CRC error flag
590	* @arg SPI_FLAG_MODF: Mode fault flag
591	* @arg SPI_FLAG_OVR: Overrun flag
592	* @arg SPI_FLAG_BSY: Busy flag
593	* @arg SPI_FLAG_FRE: Frame format error flag
594	* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
595	* @arg SPI_FLAG_FRLVL: SPI fifo reception level
596	* @retval SET or RESET.
597	*/
598	#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
599	((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
600
601	/** @brief Check whether the specified SPI Interrupt is set or not.
602	* @param __CR2__ copy of SPI CR2 register.
603	* @param __INTERRUPT__ specifies the SPI interrupt source to check.
604	* This parameter can be one of the following values:
605	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
606	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
607	* @arg SPI_IT_ERR: Error interrupt enable
608	* @retval SET or RESET.
609	*/
610	#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
611	(__INTERRUPT__)) ? SET : RESET)
612
613	/** @brief Checks if SPI Mode parameter is in allowed range.
614	* @param __MODE__ specifies the SPI Mode.
615	* This parameter can be a value of @ref SPI_Mode
616	* @retval None
617	*/
618	#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) \|\| \
619	((__MODE__) == SPI_MODE_MASTER))
620
621	/** @brief Checks if SPI Direction Mode parameter is in allowed range.
622	* @param __MODE__ specifies the SPI Direction Mode.
623	* This parameter can be a value of @ref SPI_Direction
624	* @retval None
625	*/
626	#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) \|\| \
627	((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) \|\| \
628	((__MODE__) == SPI_DIRECTION_1LINE))
629
630	/** @brief Checks if SPI Direction Mode parameter is 2 lines.
631	* @param __MODE__ specifies the SPI Direction Mode.
632	* @retval None
633	*/
634	#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
635
636	/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
637	* @param __MODE__ specifies the SPI Direction Mode.
638	* @retval None
639	*/
640	#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) \|\| \
641	((__MODE__) == SPI_DIRECTION_1LINE))
642
643	/** @brief Checks if SPI Data Size parameter is in allowed range.
644	* @param __DATASIZE__ specifies the SPI Data Size.
645	* This parameter can be a value of @ref SPI_Data_Size
646	* @retval None
647	*/
648	#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) \|\| \
649	((__DATASIZE__) == SPI_DATASIZE_15BIT) \|\| \
650	((__DATASIZE__) == SPI_DATASIZE_14BIT) \|\| \
651	((__DATASIZE__) == SPI_DATASIZE_13BIT) \|\| \
652	((__DATASIZE__) == SPI_DATASIZE_12BIT) \|\| \
653	((__DATASIZE__) == SPI_DATASIZE_11BIT) \|\| \
654	((__DATASIZE__) == SPI_DATASIZE_10BIT) \|\| \
655	((__DATASIZE__) == SPI_DATASIZE_9BIT) \|\| \
656	((__DATASIZE__) == SPI_DATASIZE_8BIT) \|\| \
657	((__DATASIZE__) == SPI_DATASIZE_7BIT) \|\| \
658	((__DATASIZE__) == SPI_DATASIZE_6BIT) \|\| \
659	((__DATASIZE__) == SPI_DATASIZE_5BIT) \|\| \
660	((__DATASIZE__) == SPI_DATASIZE_4BIT))
661
662	/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
663	* @param __CPOL__ specifies the SPI serial clock steady state.
664	* This parameter can be a value of @ref SPI_Clock_Polarity
665	* @retval None
666	*/
667	#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) \|\| \
668	((__CPOL__) == SPI_POLARITY_HIGH))
669
670	/** @brief Checks if SPI Clock Phase parameter is in allowed range.
671	* @param __CPHA__ specifies the SPI Clock Phase.
672	* This parameter can be a value of @ref SPI_Clock_Phase
673	* @retval None
674	*/
675	#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) \|\| \
676	((__CPHA__) == SPI_PHASE_2EDGE))
677
678	/** @brief Checks if SPI Slave Select parameter is in allowed range.
679	* @param __NSS__ specifies the SPI Slave Select management parameter.
680	* This parameter can be a value of @ref SPI_Slave_Select_management
681	* @retval None
682	*/
683	#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) \|\| \
684	((__NSS__) == SPI_NSS_HARD_INPUT) \|\| \
685	((__NSS__) == SPI_NSS_HARD_OUTPUT))
686
687	/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
688	* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
689	* This parameter can be a value of @ref SPI_NSSP_Mode
690	* @retval None
691	*/
692	#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) \|\| \
693	((__NSSP__) == SPI_NSS_PULSE_DISABLE))
694
695	/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
696	* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
697	* This parameter can be a value of @ref SPI_BaudRate_Prescaler
698	* @retval None
699	*/
700	#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) \|\| \
701	((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) \|\| \
702	((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) \|\| \
703	((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) \|\| \
704	((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) \|\| \
705	((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) \|\| \
706	((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) \|\| \
707	((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
708
709	/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
710	* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
711	* This parameter can be a value of @ref SPI_MSB_LSB_transmission
712	* @retval None
713	*/
714	#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) \|\| \
715	((__BIT__) == SPI_FIRSTBIT_LSB))
716
717	/** @brief Checks if SPI TI mode parameter is in allowed range.
718	* @param __MODE__ specifies the SPI TI mode.
719	* This parameter can be a value of @ref SPI_TI_mode
720	* @retval None
721	*/
722	#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) \|\| \
723	((__MODE__) == SPI_TIMODE_ENABLE))
724
725	/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
726	* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
727	* This parameter can be a value of @ref SPI_CRC_Calculation
728	* @retval None
729	*/
730	#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) \|\| \
731	((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
732
733	/** @brief Checks if SPI CRC length is in allowed range.
734	* @param __LENGTH__ specifies the SPI CRC length.
735	* This parameter can be a value of @ref SPI_CRC_length
736	* @retval None
737	*/
738	#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) \|\| \
739	((__LENGTH__) == SPI_CRC_LENGTH_8BIT) \|\| \
740	((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
741
742	/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
743	* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
744	* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
745	* @retval None
746	*/
747	#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
748	((__POLYNOMIAL__) <= 0xFFFFU) && \
749	(((__POLYNOMIAL__)&0x1U) != 0U))
750
751	/** @brief Checks if DMA handle is valid.
752	* @param __HANDLE__ specifies a DMA Handle.
753	* @retval None
754	*/
755	#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
756
757	/**
758	* @}
759	*/
760
761	/* Include SPI HAL Extended module */
762	#include "stm32g0xx_hal_spi_ex.h"
763
764	/* Exported functions --------------------------------------------------------*/
765	/** @addtogroup SPI_Exported_Functions
766	* @{
767	*/
768
769	/** @addtogroup SPI_Exported_Functions_Group1
770	* @{
771	*/
772	/* Initialization/de-initialization functions ********************************/
773	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
774	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
775	void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
776	void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
777
778	/* Callbacks Register/UnRegister functions ***********************************/
779	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
780	HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
781	pSPI_CallbackTypeDef pCallback);
782	HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
783	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
784	/**
785	* @}
786	*/
787
788	/** @addtogroup SPI_Exported_Functions_Group2
789	* @{
790	*/
791	/* I/O operation functions ***************************************************/
792	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
793	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
794	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
795	uint32_t Timeout);
796	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
797	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
798	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
799	uint16_t Size);
800	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
801	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
802	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
803	uint16_t Size);
804	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
805	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
806	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
807	/* Transfer Abort functions */
808	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
809	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
810
811	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
812	void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
813	void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
814	void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
815	void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
816	void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
817	void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
818	void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
819	void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
820	/**
821	* @}
822	*/
823
824	/** @addtogroup SPI_Exported_Functions_Group3
825	* @{
826	*/
827	/* Peripheral State and Error functions ***************************************/
828	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
829	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
830	/**
831	* @}
832	*/
833
834	/**
835	* @}
836	*/
837
838	/**
839	* @}
840	*/
841
842	/**
843	* @}
844	*/
845
846	#ifdef __cplusplus
847	}
848	#endif
849
850	#endif /* STM32G0xx_HAL_SPI_H */
851

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h

Download in other formats: