source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h

Last change on this file was 6, checked in by f.jahn, 8 months ago
File size: 177.4 KB
Line 
1/**
2 ******************************************************************************
3 * @file stm32g0xx_hal_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef STM32G0xx_HAL_RCC_H
20#define STM32G0xx_HAL_RCC_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32g0xx_hal_def.h"
28#include "stm32g0xx_ll_rcc.h"
29
30/** @addtogroup STM32G0xx_HAL_Driver
31 * @{
32 */
33
34/** @addtogroup RCC
35 * @{
36 */
37
38/* Private constants ---------------------------------------------------------*/
39/** @addtogroup RCC_Private_Constants
40 * @{
41 */
42/* Defines used for Flags */
43#define CR_REG_INDEX 1U
44#define BDCR_REG_INDEX 2U
45#define CSR_REG_INDEX 3U
46#if defined(RCC_HSI48_SUPPORT)
47#define CRRCR_REG_INDEX 4U
48#endif /* RCC_HSI48_SUPPORT */
49
50#define RCC_FLAG_MASK 0x1FU
51
52/* Define used for IS_RCC_CLOCKTYPE() */
53#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */
54/**
55 * @}
56 */
57
58/* Private macros ------------------------------------------------------------*/
59/** @addtogroup RCC_Private_Macros
60 * @{
61 */
62
63#if defined(RCC_HSI48_SUPPORT)
64#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \
65 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
66 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
67 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
68 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
69 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
70 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
71#else
72#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \
73 (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
74 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
75 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
76 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
77 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
78#endif /* RCC_HSI48_SUPPORT */
79
80#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
81 ((__HSE__) == RCC_HSE_BYPASS))
82
83#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
84 ((__LSE__) == RCC_LSE_BYPASS))
85
86#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
87
88#if defined(RCC_HSI48_SUPPORT)
89#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
90#endif /* RCC_HSI48_SUPPORT */
91
92#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
93
94#define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \
95 ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \
96 ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \
97 ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128))
98
99#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
100
101#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
102 ((__PLL__) == RCC_PLL_ON))
103
104#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
105 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
106 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
107
108#define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \
109 ((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \
110 ((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \
111 ((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8))
112
113#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
114
115#define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
116
117#if defined(RCC_PLLQ_SUPPORT)
118#define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
119#endif /* RCC_PLLQ_SUPPORT */
120
121#define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
122
123#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\
124 & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
125
126#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
127 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
128 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \
129 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \
130 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
131
132#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
133 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
134 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
135 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
136 ((__HCLK__) == RCC_SYSCLK_DIV512))
137
138#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
139 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
140 ((__PCLK__) == RCC_HCLK_DIV16))
141
142#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
143 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
144 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
145 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
146
147#if defined(RCC_MCO2_SUPPORT)
148#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO_PA8) || \
149 ((__MCOX__) == RCC_MCO_PA9) || \
150 ((__MCOX__) == RCC_MCO_PD10) || \
151 ((__MCOX__) == RCC_MCO_PF2) || \
152 ((__MCOX__) == RCC_MCO_PA10) || \
153 ((__MCOX__) == RCC_MCO_PA15) || \
154 ((__MCOX__) == RCC_MCO_PB2) || \
155 ((__MCOX__) == RCC_MCO_PD7))
156#else
157#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO_PA8) || \
158 ((__MCOX__) == RCC_MCO_PA9) || \
159 ((__MCOX__) == RCC_MCO_PD10) || \
160 ((__MCOX__) == RCC_MCO_PF2))
161#endif /* RCC_MCO2_SUPPORT */
162
163#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
164#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
165 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
166 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
167 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \
168 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
169 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
170 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
171 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
172 ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \
173 ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \
174 ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \
175 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP))
176#elif defined(STM32G0B0xx)
177#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
178 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
179 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
180 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
181 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
182 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
183 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
184 ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \
185 ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \
186 ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \
187 ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP))
188#else
189#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
190 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
191 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
192 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
193 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
194 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
195 ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
196#endif /* STM32G0C1xx || STM32G0B1xx */
197
198#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
199#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
200 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
201 ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \
202 ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128) || \
203 ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \
204 ((__DIV__) == RCC_MCODIV_1024))
205#else
206#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
207 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
208 ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \
209 ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128))
210#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
211
212#if defined(RCC_MCO2_SUPPORT)
213#if defined(RCC_HSI48_SUPPORT)
214#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \
215 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \
216 ((__SOURCE__) == RCC_MCO2SOURCE_HSI48) || \
217 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \
218 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \
219 ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \
220 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \
221 ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \
222 ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \
223 ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \
224 ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \
225 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP))
226#else
227#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \
228 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \
229 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \
230 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \
231 ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \
232 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \
233 ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \
234 ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \
235 ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \
236 ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \
237 ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP))
238#endif /* RCC_HSI48_SUPPORT */
239#define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \
240 ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \
241 ((__DIV__) == RCC_MCO2DIV_16) || ((__DIV__) == RCC_MCO2DIV_32) || \
242 ((__DIV__) == RCC_MCO2DIV_64) || ((__DIV__) == RCC_MCO2DIV_128)|| \
243 ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512)|| \
244 ((__DIV__) == RCC_MCO2DIV_1024))
245
246#endif /* RCC_MCO2_SUPPORT */
247
248#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
249 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
250 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
251 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
252
253/**
254 * @}
255 */
256
257/* Exported types ------------------------------------------------------------*/
258/** @defgroup RCC_Exported_Types RCC Exported Types
259 * @{
260 */
261
262/**
263 * @brief RCC PLL configuration structure definition
264 */
265typedef struct
266{
267 uint32_t PLLState; /*!< The new state of the PLL.
268 This parameter can be a value of @ref RCC_PLL_Config */
269
270 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
271 This parameter must be a value of @ref RCC_PLL_Clock_Source */
272
273 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
274 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */
275
276 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
277 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
278
279 uint32_t PLLP; /*!< PLLP: PLL Division factor.
280 User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ.
281 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
282
283#if defined(RCC_PLLQ_SUPPORT)
284 uint32_t PLLQ; /*!< PLLQ: PLL Division factor.
285 User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ.
286 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
287#endif /* RCC_PLLQ_SUPPORT */
288
289 uint32_t PLLR; /*!< PLLR: PLL Division for the main system clock.
290 User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ.
291 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
292
293} RCC_PLLInitTypeDef;
294
295/**
296 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
297 */
298typedef struct
299{
300 uint32_t OscillatorType; /*!< The oscillators to be configured.
301 This parameter can be a value of @ref RCC_Oscillator_Type */
302
303 uint32_t HSEState; /*!< The new state of the HSE.
304 This parameter can be a value of @ref RCC_HSE_Config */
305
306 uint32_t LSEState; /*!< The new state of the LSE.
307 This parameter can be a value of @ref RCC_LSE_Config */
308
309 uint32_t HSIState; /*!< The new state of the HSI.
310 This parameter can be a value of @ref RCC_HSI_Config */
311
312 uint32_t HSIDiv; /*!< The division factor of the HSI16.
313 This parameter can be a value of @ref RCC_HSI_Div */
314
315 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
316 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
317
318 uint32_t LSIState; /*!< The new state of the LSI.
319 This parameter can be a value of @ref RCC_LSI_Config */
320
321#if defined(RCC_HSI48_SUPPORT)
322 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices).
323 This parameter can be a value of @ref RCC_HSI48_Config */
324
325#endif /* RCC_HSI48_SUPPORT */
326
327 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
328
329} RCC_OscInitTypeDef;
330
331/**
332 * @brief RCC System, AHB and APB buses clock configuration structure definition
333 */
334typedef struct
335{
336 uint32_t ClockType; /*!< The clock to be configured.
337 This parameter can be a combination of @ref RCC_System_Clock_Type */
338
339 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
340 This parameter can be a value of @ref RCC_System_Clock_Source */
341
342 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
343 This parameter can be a value of @ref RCC_AHB_Clock_Source */
344
345 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
346 This parameter can be a value of @ref RCC_APB1_Clock_Source */
347
348
349} RCC_ClkInitTypeDef;
350
351/**
352 * @}
353 */
354
355/* Exported constants --------------------------------------------------------*/
356/** @defgroup RCC_Exported_Constants RCC Exported Constants
357 * @{
358 */
359
360/** @defgroup RCC_Timeout_Value Timeout Values
361 * @{
362 */
363#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
364#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */
365/**
366 * @}
367 */
368
369/** @defgroup RCC_Oscillator_Type Oscillator Type
370 * @{
371 */
372#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
373#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
374#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
375#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
376#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
377#if defined(RCC_HSI48_SUPPORT)
378#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
379#endif /* RCC_HSI48_SUPPORT */
380
381/**
382 * @}
383 */
384
385/** @defgroup RCC_HSE_Config HSE Config
386 * @{
387 */
388#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
389#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
390#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
391/**
392 * @}
393 */
394
395/** @defgroup RCC_LSE_Config LSE Config
396 * @{
397 */
398#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
399#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
400#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
401/**
402 * @}
403 */
404
405/** @defgroup RCC_HSI_Config HSI Config
406 * @{
407 */
408#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
409#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
410
411#define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */
412/**
413 * @}
414 */
415
416/** @defgroup RCC_HSI_Div HSI Div
417 * @{
418 */
419#define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */
420#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */
421#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */
422#define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */
423#define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */
424#define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */
425#define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */
426#define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */
427/**
428 * @}
429 */
430
431/** @defgroup RCC_LSI_Config LSI Config
432 * @{
433 */
434#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
435#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
436/**
437 * @}
438 */
439
440#if defined(RCC_HSI48_SUPPORT)
441/** @defgroup RCC_HSI48_Config HSI48 Config
442 * @{
443 */
444#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
445#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */
446/**
447 * @}
448 */
449#endif /* RCC_HSI48_SUPPORT */
450
451/** @defgroup RCC_PLL_Config PLL Config
452 * @{
453 */
454#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
455#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
456#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
457/**
458 * @}
459 */
460
461/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
462 * @{
463 */
464#define RCC_PLLM_DIV1 0x00000000U /*!< PLLM division factor = 8 */
465#define RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0 /*!< PLLM division factor = 2 */
466#define RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1 /*!< PLLM division factor = 3 */
467#define RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 4 */
468#define RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2 /*!< PLLM division factor = 5 */
469#define RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 6 */
470#define RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLLM division factor = 7 */
471#define RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 8 */
472/**
473 * @}
474 */
475
476/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
477 * @{
478 */
479#define RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0 /*!< PLLP division factor = 2 */
480#define RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1 /*!< PLLP division factor = 3 */
481#define RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 4 */
482#define RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2 /*!< PLLP division factor = 5 */
483#define RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 6 */
484#define RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 7 */
485#define RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 8 */
486#define RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3 /*!< PLLP division factor = 9 */
487#define RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 10 */
488#define RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 11 */
489#define RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 12 */
490#define RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 13 */
491#define RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 14 */
492#define RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 15 */
493#define RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 16 */
494#define RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4 /*!< PLLP division factor = 17 */
495#define RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 18 */
496#define RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 19 */
497#define RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 20 */
498#define RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 21 */
499#define RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 22 */
500#define RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 23 */
501#define RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 24 */
502#define RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3) /*!< PLLP division factor = 25 */
503#define RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 26 */
504#define RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 27 */
505#define RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 28 */
506#define RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 29 */
507#define RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 30 */
508#define RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 31 */
509#define RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 32 */
510/**
511 * @}
512 */
513
514#if defined(RCC_PLLQ_SUPPORT)
515/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
516 * @{
517 */
518#define RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0 /*!< PLLQ division factor = 2 */
519#define RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1 /*!< PLLQ division factor = 3 */
520#define RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 4 */
521#define RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2 /*!< PLLQ division factor = 5 */
522#define RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 6 */
523#define RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1) /*!< PLLQ division factor = 7 */
524#define RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 8 */
525/** * @}
526 */
527#endif /* RCC_PLLQ_SUPPORT */
528
529/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
530 * @{
531 */
532#define RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0 /*!< PLLR division factor = 2 */
533#define RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1 /*!< PLLR division factor = 3 */
534#define RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 4 */
535#define RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2 /*!< PLLR division factor = 5 */
536#define RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 6 */
537#define RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1) /*!< PLLR division factor = 7 */
538#define RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 8 */
539/** * @}
540 */
541
542/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
543 * @{
544 */
545#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */
546#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
547#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
548/**
549 * @}
550 */
551
552/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
553 * @{
554 */
555#define RCC_PLLPCLK RCC_PLLCFGR_PLLPEN /*!< PLLPCLK selection from main PLL */
556#if defined(RCC_PLLQ_SUPPORT)
557#define RCC_PLLQCLK RCC_PLLCFGR_PLLQEN /*!< PLLQCLK selection from main PLL */
558#endif /* RCC_PLLQ_SUPPORT */
559#define RCC_PLLRCLK RCC_PLLCFGR_PLLREN /*!< PLLRCLK selection from main PLL */
560
561/**
562 * @}
563 */
564
565/** @defgroup RCC_System_Clock_Type System Clock Type
566 * @{
567 */
568#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
569#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
570#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
571/**
572 * @}
573 */
574
575/** @defgroup RCC_System_Clock_Source System Clock Source
576 * @{
577 */
578#define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */
579#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */
580#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_1 /*!< PLL selection as system clock */
581#define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */
582#define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */
583/**
584 * @}
585 */
586
587/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
588 * @{
589 */
590#define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */
591#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */
592#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1 /*!< PLL used as system clock */
593#define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */
594#define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */
595/**
596 * @}
597 */
598
599/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
600 * @{
601 */
602#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */
603#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
604#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
605#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
606#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
607#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
608#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
609#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
610#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
611/**
612 * @}
613 */
614
615/** @defgroup RCC_APB1_Clock_Source APB Clock Source
616 * @{
617 */
618#define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */
619#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */
620#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */
621#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */
622#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
623/**
624 * @}
625 */
626
627/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
628 * @{
629 */
630#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock configured for RTC */
631#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
632#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
633#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
634/**
635 * @}
636 */
637
638/** @defgroup RCC_MCO_Index MCO Index
639 * @{
640 */
641
642/* 32 28 20 16 0
643 --------------------------------
644 | MCO | GPIO | GPIO | GPIO |
645 | Index | AF | Port | Pin |
646 -------------------------------*/
647
648#define RCC_MCO_GPIOPORT_POS 16U
649#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)
650#define RCC_MCO_GPIOAF_POS 20U
651#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)
652#define RCC_MCO_INDEX_POS 28U
653#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)
654#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */
655#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
656#define RCC_MCO_PA9 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9)
657#define RCC_MCO_PD10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOD) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) /* Not defined for all stm32g0xx family lines */
658#define RCC_MCO_PF2 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) /* Not defined for all stm32g0xx family lines */
659#define RCC_MCO1 RCC_MCO_PA8
660
661#if defined(RCC_MCO2_SUPPORT)
662#define RCC_MCO2_INDEX (0x1u << RCC_MCO_INDEX_POS) /*!< MCO2 index */
663#define RCC_MCO_PA10 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
664#define RCC_MCO_PA15 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_15)
665#define RCC_MCO_PB2 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOB) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2)
666#define RCC_MCO_PD7 (RCC_MCO2_INDEX | (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOD) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_7)
667#define RCC_MCO2 RCC_MCO_PA10
668#endif /* RCC_MCO2_SUPPORT */
669
670#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
671/**
672 * @}
673 */
674
675/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
676 * @{
677 */
678#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
679#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
680#if defined(RCC_HSI48_SUPPORT)
681#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */
682#endif /* RCC_HSI48_SUPPORT */
683#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
684#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
685#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
686#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
687#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
688#if defined(RCC_CFGR_MCOSEL_3)
689#define RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */
690#define RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */
691#define RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */
692#define RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */
693#endif /* RCC_CFGR_MCOSEL_3 */
694/**
695 * @}
696 */
697
698/** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler
699 * @{
700 */
701#define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */
702#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
703#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
704#define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
705#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
706#define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */
707#define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */
708#define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */
709#if defined(RCC_CFGR_MCOPRE_3)
710#define RCC_MCODIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */
711#define RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */
712#define RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */
713#endif /* RCC_CFGR_MCOSEL_3 */
714/**
715 * @}
716 */
717
718#if defined(RCC_MCO2_SUPPORT)
719/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
720 * @{
721 */
722#define RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */
723#define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */
724#if defined(RCC_HSI48_SUPPORT)
725#define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */
726#endif /* RCC_HSI48_SUPPORT */
727#define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0) /*!< HSI selection as MCO2 source */
728#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */
729#define RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0) /*!< PLLCLK selection as MCO2 source */
730#define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */
731#define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */
732#define RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLLPCLK selection as MCO2 source */
733#define RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0) /*!< PLLQCLK selection as MCO2 source */
734#define RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1) /*!< RTCCLK selection as MCO2 source */
735#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */
736/**
737 * @}
738 */
739
740/** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler
741 * @{
742 */
743#define RCC_MCO2DIV_1 0x00000000U /*!< MCO2 not divided */
744#define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */
745#define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */
746#define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */
747#define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */
748#define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */
749#define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */
750#define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
751#define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */
752#define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */
753#define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */
754/**
755 * @}
756 */
757#endif /* RCC_MCO2_SUPPORT */
758
759/** @defgroup RCC_Interrupt Interrupts
760 * @{
761 */
762#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
763#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
764#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
765#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
766#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
767#define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */
768#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
769#if defined(RCC_HSI48_SUPPORT)
770#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
771#endif /* RCC_HSI48_SUPPORT */
772/**
773 * @}
774 */
775
776/** @defgroup RCC_Flag Flags
777 * Elements values convention: XXXYYYYYb
778 * - YYYYY : Flag position in the register
779 * - XXX : Register index
780 * - 001: CR register
781 * - 010: BDCR register
782 * - 011: CSR register
783 * @{
784 */
785/* Flags in the CR register */
786#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
787#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
788#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
789
790#if defined(RCC_HSI48_SUPPORT)
791/* Flags in the CR register */
792#define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
793#endif /* RCC_HSI48_SUPPORT */
794
795/* Flags in the BDCR register */
796#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
797#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
798
799/* Flags in the CSR register */
800#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
801#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
802#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
803#define RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */
804#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
805#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
806#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
807#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
808
809/**
810 * @}
811 */
812
813/** @defgroup RCC_LSEDrive_Config LSE Drive Configuration
814 * @{
815 */
816#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
817#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
818#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
819#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
820/**
821 * @}
822 */
823
824/** @defgroup RCC_Reset_Flag Reset Flag
825 * @{
826 */
827#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */
828#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */
829#define RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */
830#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */
831#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
832#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
833#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */
834#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
835 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
836 RCC_RESET_FLAG_LPWR)
837/**
838 * @}
839 */
840
841/**
842 * @}
843 */
844
845/* Exported macros -----------------------------------------------------------*/
846
847/** @defgroup RCC_Exported_Macros RCC Exported Macros
848 * @{
849 */
850
851/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
852 * @brief Enable or disable the AHB peripheral clock.
853 * @note After reset, the peripheral clock (used for registers read/write access)
854 * is disabled and the application software has to enable this clock before
855 * using it.
856 * @{
857 */
858
859#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
860 __IO uint32_t tmpreg; \
861 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
862 /* Delay after an RCC peripheral clock enabling */ \
863 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
864 UNUSED(tmpreg); \
865 } while(0U)
866
867#if defined(DMA2)
868#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
869 __IO uint32_t tmpreg; \
870 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
871 /* Delay after an RCC peripheral clock enabling */ \
872 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
873 UNUSED(tmpreg); \
874 } while(0U)
875
876#endif /* DMA2 */
877
878
879#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
880 __IO uint32_t tmpreg; \
881 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
882 /* Delay after an RCC peripheral clock enabling */ \
883 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
884 UNUSED(tmpreg); \
885 } while(0U)
886
887#define __HAL_RCC_CRC_CLK_ENABLE() do { \
888 __IO uint32_t tmpreg; \
889 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
890 /* Delay after an RCC peripheral clock enabling */ \
891 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
892 UNUSED(tmpreg); \
893 } while(0U)
894
895#if defined(RNG)
896#define __HAL_RCC_RNG_CLK_ENABLE() do { \
897 __IO uint32_t tmpreg; \
898 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
899 /* Delay after an RCC peripheral clock enabling */ \
900 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
901 UNUSED(tmpreg); \
902 } while(0U)
903#endif /* RNG */
904
905#if defined(AES)
906#define __HAL_RCC_AES_CLK_ENABLE() do { \
907 __IO uint32_t tmpreg; \
908 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
909 /* Delay after an RCC peripheral clock enabling */ \
910 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
911 UNUSED(tmpreg); \
912 } while(0U)
913#endif /* AES */
914
915#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
916#if defined(DMA2)
917#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)
918#endif /* DMA2 */
919#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN)
920#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
921#if defined(RNG)
922#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN)
923#endif /* RNG */
924#if defined(AES)
925#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN)
926#endif /* AES */
927/**
928 * @}
929 */
930
931/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable
932 * @brief Enable or disable the IO Ports clock.
933 * @note After reset, the IO ports clock (used for registers read/write access)
934 * is disabled and the application software has to enable this clock before
935 * using it.
936 * @{
937 */
938
939#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
940 __IO uint32_t tmpreg; \
941 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
942 /* Delay after an RCC peripheral clock enabling */ \
943 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
944 UNUSED(tmpreg); \
945 } while(0U)
946
947#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
948 __IO uint32_t tmpreg; \
949 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
950 /* Delay after an RCC peripheral clock enabling */ \
951 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
952 UNUSED(tmpreg); \
953 } while(0U)
954
955#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
956 __IO uint32_t tmpreg; \
957 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
958 /* Delay after an RCC peripheral clock enabling */ \
959 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
960 UNUSED(tmpreg); \
961 } while(0U)
962
963#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
964 __IO uint32_t tmpreg; \
965 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
966 /* Delay after an RCC peripheral clock enabling */ \
967 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
968 UNUSED(tmpreg); \
969 } while(0U)
970
971#if defined(GPIOE)
972#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
973 __IO uint32_t tmpreg; \
974 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
975 /* Delay after an RCC peripheral clock enabling */ \
976 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
977 UNUSED(tmpreg); \
978 } while(0U)
979#endif /* GPIOE */
980
981#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
982 __IO uint32_t tmpreg; \
983 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
984 /* Delay after an RCC peripheral clock enabling */ \
985 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
986 UNUSED(tmpreg); \
987 } while(0U)
988
989#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
990#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
991#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
992#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN)
993#if defined(GPIOE)
994#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN)
995#endif /* GPIOE */
996#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN)
997
998/**
999 * @}
1000 */
1001
1002/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
1003 * @brief Enable or disable the APB1 peripheral clock.
1004 * @note After reset, the peripheral clock (used for registers read/write access)
1005 * is disabled and the application software has to enable this clock before
1006 * using it.
1007 * @{
1008 */
1009#if defined(TIM2)
1010#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
1011 __IO uint32_t tmpreg; \
1012 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
1013 /* Delay after an RCC peripheral clock enabling */ \
1014 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
1015 UNUSED(tmpreg); \
1016 } while(0U)
1017#endif /* TIM2 */
1018
1019#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
1020 __IO uint32_t tmpreg; \
1021 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
1022 /* Delay after an RCC peripheral clock enabling */ \
1023 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
1024 UNUSED(tmpreg); \
1025 } while(0U)
1026
1027#if defined(TIM4)
1028#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
1029 __IO uint32_t tmpreg; \
1030 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
1031 /* Delay after an RCC peripheral clock enabling */ \
1032 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
1033 UNUSED(tmpreg); \
1034 } while(0U)
1035#endif /* TIM4 */
1036
1037#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
1038 __IO uint32_t tmpreg; \
1039 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
1040 /* Delay after an RCC peripheral clock enabling */ \
1041 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
1042 UNUSED(tmpreg); \
1043 } while(0U)
1044
1045#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
1046 __IO uint32_t tmpreg; \
1047 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
1048 /* Delay after an RCC peripheral clock enabling */ \
1049 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
1050 UNUSED(tmpreg); \
1051 } while(0U)
1052
1053#if defined(CRS)
1054#define __HAL_RCC_CRS_CLK_ENABLE() do { \
1055 __IO uint32_t tmpreg; \
1056 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
1057 /* Delay after an RCC peripheral clock enabling */ \
1058 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
1059 UNUSED(tmpreg); \
1060 } while(0)
1061#endif /* CRS */
1062
1063#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
1064 __IO uint32_t tmpreg; \
1065 SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
1066 /* Delay after an RCC peripheral clock enabling */ \
1067 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
1068 UNUSED(tmpreg); \
1069 } while(0U)
1070
1071#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
1072 __IO uint32_t tmpreg; \
1073 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
1074 /* Delay after an RCC peripheral clock enabling */ \
1075 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
1076 UNUSED(tmpreg); \
1077 } while(0U)
1078
1079#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
1080 __IO uint32_t tmpreg; \
1081 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
1082 /* Delay after an RCC peripheral clock enabling */ \
1083 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
1084 UNUSED(tmpreg); \
1085 } while(0U)
1086#if defined(SPI3)
1087#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1088 __IO uint32_t tmpreg; \
1089 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
1090 /* Delay after an RCC peripheral clock enabling */ \
1091 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
1092 UNUSED(tmpreg); \
1093 } while(0U)
1094#endif /* SPI3 */
1095
1096#define __HAL_RCC_USART2_CLK_ENABLE() do { \
1097 __IO uint32_t tmpreg; \
1098 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
1099 /* Delay after an RCC peripheral clock enabling */ \
1100 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
1101 UNUSED(tmpreg); \
1102 } while(0U)
1103
1104#define __HAL_RCC_USART3_CLK_ENABLE() do { \
1105 __IO uint32_t tmpreg; \
1106 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
1107 /* Delay after an RCC peripheral clock enabling */ \
1108 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
1109 UNUSED(tmpreg); \
1110 } while(0U)
1111
1112#define __HAL_RCC_USART4_CLK_ENABLE() do { \
1113 __IO uint32_t tmpreg; \
1114 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
1115 /* Delay after an RCC peripheral clock enabling */ \
1116 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
1117 UNUSED(tmpreg); \
1118 } while(0U)
1119
1120#if defined(USART5)
1121#define __HAL_RCC_USART5_CLK_ENABLE() do { \
1122 __IO uint32_t tmpreg; \
1123 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
1124 /* Delay after an RCC peripheral clock enabling */ \
1125 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
1126 UNUSED(tmpreg); \
1127 } while(0U)
1128#endif /* USART5 */
1129
1130#if defined(USART6)
1131#define __HAL_RCC_USART6_CLK_ENABLE() do { \
1132 __IO uint32_t tmpreg; \
1133 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
1134 /* Delay after an RCC peripheral clock enabling */ \
1135 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
1136 UNUSED(tmpreg); \
1137 } while(0U)
1138#endif /* USART6 */
1139
1140#if defined(LPUART1)
1141#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
1142 __IO uint32_t tmpreg; \
1143 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
1144 /* Delay after an RCC peripheral clock enabling */ \
1145 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
1146 UNUSED(tmpreg); \
1147 } while(0U)
1148#endif /* LPUART1 */
1149
1150#if defined(LPUART2)
1151#define __HAL_RCC_LPUART2_CLK_ENABLE() do { \
1152 __IO uint32_t tmpreg; \
1153 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
1154 /* Delay after an RCC peripheral clock enabling */ \
1155 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
1156 UNUSED(tmpreg); \
1157 } while(0U)
1158#endif /* LPUART2 */
1159
1160#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
1161 __IO uint32_t tmpreg; \
1162 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
1163 /* Delay after an RCC peripheral clock enabling */ \
1164 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
1165 UNUSED(tmpreg); \
1166 } while(0U)
1167
1168#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
1169 __IO uint32_t tmpreg; \
1170 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
1171 /* Delay after an RCC peripheral clock enabling */ \
1172 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
1173 UNUSED(tmpreg); \
1174 } while(0U)
1175
1176#if defined(I2C3)
1177#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1178 __IO uint32_t tmpreg; \
1179 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
1180 /* Delay after an RCC peripheral clock enabling */ \
1181 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
1182 UNUSED(tmpreg); \
1183 } while(0U)
1184#endif /* I2C3 */
1185
1186#if defined(CEC)
1187#define __HAL_RCC_CEC_CLK_ENABLE() do { \
1188 __IO uint32_t tmpreg; \
1189 SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
1190 /* Delay after an RCC peripheral clock enabling */ \
1191 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
1192 UNUSED(tmpreg); \
1193 } while(0U)
1194#endif /* CEC */
1195
1196#if defined(UCPD1)
1197#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \
1198 __IO uint32_t tmpreg; \
1199 SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
1200 /* Delay after an RCC peripheral clock enabling */ \
1201 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
1202 UNUSED(tmpreg); \
1203 } while(0U)
1204#endif /* UCPD1 */
1205
1206#if defined(UCPD2)
1207#define __HAL_RCC_UCPD2_CLK_ENABLE() do { \
1208 __IO uint32_t tmpreg; \
1209 SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
1210 /* Delay after an RCC peripheral clock enabling */ \
1211 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
1212 UNUSED(tmpreg); \
1213 } while(0U)
1214#endif /* UCPD2 */
1215
1216#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
1217#define __HAL_RCC_USB_CLK_ENABLE() do { \
1218 __IO uint32_t tmpreg; \
1219 SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
1220 /* Delay after an RCC peripheral clock enabling */ \
1221 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
1222 UNUSED(tmpreg); \
1223 } while(0U)
1224#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
1225
1226#if defined(FDCAN1) || defined(FDCAN2)
1227#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
1228 __IO uint32_t tmpreg; \
1229 SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
1230 /* Delay after an RCC peripheral clock enabling */ \
1231 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
1232 UNUSED(tmpreg); \
1233 } while(0)
1234#endif /* FDCAN1 || FDCAN2 */
1235
1236#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
1237 __IO uint32_t tmpreg; \
1238 SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
1239 /* Delay after an RCC peripheral clock enabling */ \
1240 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
1241 UNUSED(tmpreg); \
1242 } while(0U)
1243
1244#define __HAL_RCC_PWR_CLK_ENABLE() do { \
1245 __IO uint32_t tmpreg; \
1246 SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
1247 /* Delay after an RCC peripheral clock enabling */ \
1248 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
1249 UNUSED(tmpreg); \
1250 } while(0U)
1251
1252#if defined(DAC1)
1253#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
1254 __IO uint32_t tmpreg; \
1255 SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
1256 /* Delay after an RCC peripheral clock enabling */ \
1257 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
1258 UNUSED(tmpreg); \
1259 } while(0U)
1260#endif /* DAC1 */
1261
1262#if defined(LPTIM2)
1263#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
1264 __IO uint32_t tmpreg; \
1265 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
1266 /* Delay after an RCC peripheral clock enabling */ \
1267 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
1268 UNUSED(tmpreg); \
1269 } while(0U)
1270#endif /* LPTIM2 */
1271
1272#if defined(LPTIM1)
1273#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
1274 __IO uint32_t tmpreg; \
1275 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
1276 /* Delay after an RCC peripheral clock enabling */ \
1277 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
1278 UNUSED(tmpreg); \
1279 } while(0U)
1280#endif /* LPTIM1 */
1281
1282/**
1283 * @}
1284 */
1285
1286/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
1287 * @brief Enable or disable the APB2 peripheral clock.
1288 * @note After reset, the peripheral clock (used for registers read/write access)
1289 * is disabled and the application software has to enable this clock before
1290 * using it.
1291 * @{
1292 */
1293
1294#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
1295 __IO uint32_t tmpreg; \
1296 SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
1297 /* Delay after an RCC peripheral clock enabling */ \
1298 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
1299 UNUSED(tmpreg); \
1300 } while(0U)
1301
1302#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
1303 __IO uint32_t tmpreg; \
1304 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
1305 /* Delay after an RCC peripheral clock enabling */ \
1306 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
1307 UNUSED(tmpreg); \
1308 } while(0U)
1309
1310#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
1311 __IO uint32_t tmpreg; \
1312 SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
1313 /* Delay after an RCC peripheral clock enabling */ \
1314 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
1315 UNUSED(tmpreg); \
1316 } while(0U)
1317
1318#define __HAL_RCC_USART1_CLK_ENABLE() do { \
1319 __IO uint32_t tmpreg; \
1320 SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
1321 /* Delay after an RCC peripheral clock enabling */ \
1322 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
1323 UNUSED(tmpreg); \
1324 } while(0U)
1325
1326#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1327 __IO uint32_t tmpreg; \
1328 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
1329 /* Delay after an RCC peripheral clock enabling */ \
1330 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
1331 UNUSED(tmpreg); \
1332 } while(0U)
1333
1334#if defined(TIM15)
1335#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
1336 __IO uint32_t tmpreg; \
1337 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
1338 /* Delay after an RCC peripheral clock enabling */ \
1339 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
1340 UNUSED(tmpreg); \
1341 } while(0U)
1342#endif /* TIM15 */
1343
1344#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
1345 __IO uint32_t tmpreg; \
1346 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
1347 /* Delay after an RCC peripheral clock enabling */ \
1348 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
1349 UNUSED(tmpreg); \
1350 } while(0U)
1351
1352#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
1353 __IO uint32_t tmpreg; \
1354 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
1355 /* Delay after an RCC peripheral clock enabling */ \
1356 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
1357 UNUSED(tmpreg); \
1358 } while(0U)
1359
1360#define __HAL_RCC_ADC_CLK_ENABLE() do { \
1361 __IO uint32_t tmpreg; \
1362 SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
1363 /* Delay after an RCC peripheral clock enabling */ \
1364 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
1365 UNUSED(tmpreg); \
1366 } while(0U)
1367
1368#if defined(TIM2)
1369#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
1370#endif /* TIM2 */
1371#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
1372#if defined(TIM4)
1373#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)
1374#endif /* TIM4 */
1375#if defined(TIM6)
1376#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)
1377#endif /* TIM6 */
1378#if defined(TIM7)
1379#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)
1380#endif /* TIM7 */
1381#if defined(CRS)
1382#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN);
1383#endif /* CRS */
1384#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN)
1385#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)
1386#if defined(SPI3)
1387#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)
1388#endif /* SPI3 */
1389#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN)
1390#if defined(USART3)
1391#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN)
1392#endif /* USART3 */
1393#if defined(USART4)
1394#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN)
1395#endif /* USART4 */
1396#if defined(USART5)
1397#define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN)
1398#endif /* USART5 */
1399#if defined(USART6)
1400#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN)
1401#endif /* USART6 */
1402#if defined(LPUART1)
1403#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)
1404#endif /* LPUART1 */
1405#if defined(LPUART2)
1406#define __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)
1407#endif /* LPUART2 */
1408#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)
1409#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)
1410#if defined(I2C3)
1411#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)
1412#endif /* I2C3 */
1413#if defined(CEC)
1414#define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)
1415#endif /* CEC */
1416#if defined(UCPD1)
1417#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)
1418#endif /* UCPD1 */
1419#if defined(UCPD2)
1420#define __HAL_RCC_UCPD2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)
1421#endif /* UCPD2 */
1422#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
1423#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)
1424#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
1425#if defined(FDCAN1) || defined(FDCAN2)
1426#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)
1427#endif /* FDCAN1 || FDCAN2 */
1428#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)
1429#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)
1430#if defined(DAC1)
1431#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)
1432#endif /* DAC1 */
1433#if defined(LPTIM1)
1434#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN)
1435#endif /* LPTIM1 */
1436#if defined(LPTIM2)
1437#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN)
1438#endif /* LPTIM2 */
1439#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN)
1440#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
1441#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)
1442#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN)
1443#define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)
1444#if defined(TIM15)
1445#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN)
1446#endif /* TIM15 */
1447#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN)
1448#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN)
1449#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)
1450
1451/**
1452 * @}
1453 */
1454
1455/** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status
1456 * @brief Check whether the AHB peripheral clock is enabled or not.
1457 * @note After reset, the peripheral clock (used for registers read/write access)
1458 * is disabled and the application software has to enable this clock before
1459 * using it.
1460 * @{
1461 */
1462
1463#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
1464#if defined(DMA2)
1465#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET)
1466#endif /* DMA2 */
1467#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET)
1468#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
1469#if defined(RNG)
1470#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET)
1471#endif /* RNG */
1472#if defined(AES)
1473#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != RESET)
1474#endif /* AES */
1475
1476#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET)
1477#if defined(DMA2)
1478#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET)
1479#endif /* DMA2 */
1480#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET)
1481#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)
1482#if defined(RNG)
1483#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET)
1484#endif /* RNG */
1485#if defined(AES)
1486#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == RESET)
1487#endif /* AES */
1488/**
1489 * @}
1490 */
1491
1492/** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status
1493 * @brief Check whether the IO Port clock is enabled or not.
1494 * @note After reset, the peripheral clock (used for registers read/write access)
1495 * is disabled and the application software has to enable this clock before
1496 * using it.
1497 * @{
1498 */
1499#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
1500#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
1501#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
1502#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET)
1503#if defined(GPIOE)
1504#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET)
1505#endif /* GPIOE */
1506#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET)
1507
1508
1509#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)
1510#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)
1511#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)
1512#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET)
1513#if defined(GPIOE)
1514#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET)
1515#endif /* GPIOE */
1516#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET)
1517
1518/**
1519 * @}
1520 */
1521
1522/** @defgroup RCC_APB1_Clock_Enabled_Disabled_Status APB1 Peripheral Clock Enabled or Disabled Status
1523 * @brief Check whether the APB1 peripheral clock is enabled or not.
1524 * @note After reset, the peripheral clock (used for registers read/write access)
1525 * is disabled and the application software has to enable this clock before
1526 * using it.
1527 * @{
1528 */
1529
1530#if defined(TIM2)
1531#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U)
1532#endif /* TIM2 */
1533#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U)
1534#if defined(TIM4)
1535#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U)
1536#endif /* TIM4 */
1537#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U)
1538#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U)
1539#if defined(CRS)
1540#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)
1541#endif /* CRS */
1542#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U)
1543#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U)
1544#if defined(FDCAN1) || defined(FDCAN2)
1545#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U)
1546#endif /* FDCAN1 || FDCAN2 */
1547#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
1548#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U)
1549#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
1550#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U)
1551#if defined(SPI3)
1552#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U)
1553#endif /* SPI3 */
1554#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U)
1555#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U)
1556#define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U)
1557#if defined(USART5)
1558#define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U)
1559#endif /* USART5 */
1560#if defined(USART6)
1561#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U)
1562#endif /* USART6 */
1563#if defined(LPUART1)
1564#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U)
1565#endif /* LPUART1 */
1566#if defined(LPUART2)
1567#define __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U)
1568#endif /* LPUART2 */
1569#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U)
1570#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U)
1571#if defined(I2C3)
1572#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U)
1573#endif /* I2C3 */
1574#if defined(CEC)
1575#define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U)
1576#endif /* CEC */
1577#if defined(UCPD1)
1578#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U)
1579#endif /* UCPD1 */
1580#if defined(UCPD2)
1581#define __HAL_RCC_UCPD2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U)
1582#endif /* UCPD2 */
1583#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U)
1584#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U)
1585#if defined(DAC1)
1586#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U)
1587#endif /* DAC1 */
1588#if defined(LPTIM2)
1589#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U)
1590#endif /* LPTIM2 */
1591#if defined(LPTIM1)
1592#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U)
1593#endif /* LPTIM1 */
1594#if defined(TIM2)
1595#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U)
1596#endif /* TIM2 */
1597#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U)
1598#if defined(TIM4)
1599#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U)
1600#endif /* TIM4 */
1601#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U)
1602#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U)
1603#if defined(CRS)
1604#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)
1605#endif /* CRS */
1606#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U)
1607#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U)
1608#if defined(FDCAN1) || defined(FDCAN2)
1609#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U)
1610#endif /* FDCAN1 || FDCAN2 */
1611#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
1612#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U)
1613#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
1614#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U)
1615#if defined(SPI3)
1616#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U)
1617#endif /* SPI3 */
1618#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U)
1619#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U)
1620#define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U)
1621#if defined(USART5)
1622#define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U)
1623#endif /* USART5 */
1624#if defined(USART6)
1625#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U)
1626#endif /* USART6 */
1627#if defined(LPUART1)
1628#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U)
1629#endif /* LPUART1 */
1630#if defined(LPUART2)
1631#define __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U)
1632#endif /* LPUART2 */
1633#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U)
1634#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U)
1635#if defined(I2C3)
1636#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U)
1637#endif /* I2C3 */
1638#if defined(CEC)
1639#define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U)
1640#endif /* CEC */
1641#if defined(UCPD1)
1642#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U)
1643#endif /* UCPD1 */
1644#if defined(UCPD2)
1645#define __HAL_RCC_UCPD2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U)
1646#endif /* UCPD2 */
1647#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U)
1648#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U)
1649#if defined(DAC1)
1650#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U)
1651#endif /* DAC1 */
1652#if defined(LPTIM2)
1653#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U)
1654#endif /* LPTIM2 */
1655#if defined(LPTIM1)
1656#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U)
1657#endif /* LPTIM1 */
1658
1659/**
1660 * @}
1661 */
1662
1663/** @defgroup RCC_APB2_Clock_Enabled_Disabled_Status APB2 Peripheral Clock Enabled or Disabled Status
1664 * @brief Check whether the APB2 peripheral clock is enabled or not.
1665 * @note After reset, the peripheral clock (used for registers read/write access)
1666 * is disabled and the application software has to enable this clock before
1667 * using it.
1668 * @{
1669 */
1670
1671#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U)
1672#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)
1673#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U)
1674#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U)
1675#define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U)
1676#if defined(TIM15)
1677#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U)
1678#endif /* TIM15 */
1679#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U)
1680#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U)
1681#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U)
1682
1683#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U)
1684#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)
1685#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U)
1686#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U)
1687#define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U)
1688#if defined(TIM15)
1689#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U)
1690#endif /* TIM15 */
1691#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U)
1692#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U)
1693#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U)
1694
1695/**
1696 * @}
1697 */
1698
1699/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
1700 * @brief Force or release AHB1 peripheral reset.
1701 * @{
1702 */
1703#define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU)
1704#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
1705#if defined(DMA2)
1706#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
1707#endif /* DMA2 */
1708#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
1709#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
1710#if defined(RNG)
1711#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
1712#endif /* RNG */
1713#if defined(AES)
1714#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)
1715#endif /* AES */
1716
1717#define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U)
1718#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST)
1719#if defined(DMA2)
1720#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST)
1721#endif /* DMA2 */
1722#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
1723#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
1724#if defined(RNG)
1725#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST)
1726#endif /* RNG */
1727#if defined(AES)
1728#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST)
1729#endif /* AES */
1730/**
1731 * @}
1732 */
1733
1734/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset
1735 * @brief Force or release IO Port reset.
1736 * @{
1737 */
1738#define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU)
1739#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
1740#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
1741#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
1742#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
1743#if defined(GPIOE)
1744#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
1745#endif /* GPIOE */
1746#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)
1747
1748#define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U)
1749#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
1750#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
1751#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
1752#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST)
1753#if defined(GPIOE)
1754#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST)
1755#endif /* GPIOE */
1756#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST)
1757
1758/**
1759 * @}
1760 */
1761
1762/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
1763 * @brief Force or release APB1 peripheral reset.
1764 * @{
1765 */
1766#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU)
1767
1768#if defined(TIM2)
1769#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
1770#endif /* TIM2 */
1771#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
1772#if defined(TIM4)
1773#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
1774#endif /* TIM4 */
1775#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
1776#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
1777#if defined(CRS)
1778#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
1779#endif /* CRS */
1780#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
1781#if defined(SPI3)
1782#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
1783#endif /* SPI3 */
1784#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
1785#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
1786#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
1787#if defined(USART5)
1788#define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
1789#endif /* USART5 */
1790#if defined(USART6)
1791#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
1792#endif /* USART6 */
1793#if defined(LPUART1)
1794#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
1795#endif /* LPUART1 */
1796#if defined(LPUART2)
1797#define __HAL_RCC_LPUART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
1798#endif /* LPUART2 */
1799#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
1800#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
1801#if defined(I2C3)
1802#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
1803#endif /* I2C3 */
1804#if defined(CEC)
1805#define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
1806#endif /* CEC */
1807#if defined(UCPD1)
1808#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
1809#endif /* UCPD1 */
1810#if defined(UCPD2)
1811#define __HAL_RCC_UCPD2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
1812#endif /* UCPD2 */
1813#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
1814#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
1815#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
1816#if defined(FDCAN1) || defined(FDCAN2)
1817#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
1818#endif /* FDCAN1 || FDCAN2 */
1819#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
1820#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
1821#if defined(DAC1)
1822#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
1823#endif /* DAC1 */
1824#if defined(LPTIM2)
1825#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
1826#endif /* LPTIM2 */
1827#if defined(LPTIM1)
1828#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)
1829#endif /* LPTIM1 */
1830#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U)
1831#if defined(TIM2)
1832#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST)
1833#endif /* TIM2 */
1834#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST)
1835#if defined(TIM4)
1836#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST)
1837#endif /* TIM4 */
1838#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST)
1839#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST)
1840#if defined(CRS)
1841#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST)
1842#endif /* CRS */
1843#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST)
1844#if defined(SPI3)
1845#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST)
1846#endif /* SPI3 */
1847#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST)
1848#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST)
1849#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST)
1850#if defined(USART5)
1851#define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST)
1852#endif /* USART5 */
1853#if defined(USART6)
1854#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST)
1855#endif /* USART6 */
1856#if defined(LPUART1)
1857#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST)
1858#endif /* LPUART1 */
1859#if defined(LPUART2)
1860#define __HAL_RCC_LPUART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST)
1861#endif /* LPUART2 */
1862#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST)
1863#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST)
1864#if defined(I2C3)
1865#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST)
1866#endif /* I2C3 */
1867#if defined(CEC)
1868#define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST)
1869#endif /* CEC */
1870#if defined(UCPD1)
1871#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST)
1872#endif /* UCPD1 */
1873#if defined(UCPD2)
1874#define __HAL_RCC_UCPD2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST)
1875#endif /* UCPD2 */
1876#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
1877#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST)
1878#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
1879#if defined(FDCAN1) || defined(FDCAN2)
1880#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST)
1881#endif /* FDCAN1 || FDCAN2 */
1882#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
1883#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
1884#if defined(DAC1)
1885#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST)
1886#endif /* DAC1 */
1887#if defined(LPTIM2)
1888#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST)
1889#endif /* LPTIM2 */
1890#if defined(LPTIM1)
1891#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST)
1892#endif /* LPTIM1 */
1893/**
1894 * @}
1895 */
1896
1897/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
1898 * @brief Force or release APB2 peripheral reset.
1899 * @{
1900 */
1901#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU)
1902#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
1903#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
1904#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
1905#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
1906#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
1907#if defined(TIM15)
1908#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
1909#endif /* TIM15 */
1910#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
1911#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
1912#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
1913
1914#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00U)
1915#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
1916#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
1917#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
1918#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
1919#define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
1920#if defined(TIM15)
1921#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST)
1922#endif /* TIM15 */
1923#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST)
1924#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST)
1925#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
1926
1927/**
1928 * @}
1929 */
1930
1931/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable
1932 * @brief Enable or disable the AHB peripherals clock during Low Power (Sleep) mode.
1933 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1934 * power consumption.
1935 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1936 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1937 * @{
1938 */
1939
1940#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1941#if defined(DMA2)
1942#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
1943#endif /* DMA2 */
1944#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
1945#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
1946#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
1947#if defined(RNG)
1948#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
1949#endif /* RNG */
1950#if defined(AES)
1951#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
1952#endif /* AES */
1953#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1954#if defined(DMA2)
1955#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
1956#endif /* DMA2 */
1957#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
1958#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
1959#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
1960#if defined(RNG)
1961#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
1962#endif /* RNG */
1963#if defined(AES)
1964#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
1965#endif /* AES */
1966
1967/**
1968 * @}
1969 */
1970
1971/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable
1972 * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode.
1973 * @note IOPORT clock gating in SLEEP mode can be used to further reduce
1974 * power consumption.
1975 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1976 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1977 * @{
1978 */
1979
1980#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
1981#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
1982#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
1983#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
1984#if defined(GPIOE)
1985#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
1986#endif /* GPIOE */
1987#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)
1988
1989#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)
1990#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)
1991#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)
1992#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)
1993#if defined(GPIOE)
1994#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)
1995#endif /* GPIOE */
1996#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)
1997/**
1998 * @}
1999 */
2000
2001/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
2002 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
2003 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2004 * power consumption.
2005 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2006 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2007 * @{
2008 */
2009#if defined(TIM2)
2010#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
2011#endif /* TIM2 */
2012#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
2013#if defined(TIM4)
2014#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
2015#endif /* TIM4 */
2016#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
2017#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
2018#if defined(CRS)
2019#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
2020#endif /* CRS */
2021#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
2022#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
2023#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
2024#if defined(SPI3)
2025#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
2026#endif /* SPI3 */
2027#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
2028#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
2029#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
2030#if defined(USART5)
2031#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
2032#endif /* USART5 */
2033#if defined(USART6)
2034#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
2035#endif /* USART6 */
2036#if defined(LPUART1)
2037#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
2038#endif /* LPUART1 */
2039#if defined(LPUART2)
2040#define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
2041#endif /* LPUART2 */
2042#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
2043#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
2044#if defined(I2C3)
2045#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
2046#endif /* I2C3 */
2047#if defined(CEC)
2048#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
2049#endif /* CEC */
2050#if defined(UCPD1)
2051#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
2052#endif /* UCPD1 */
2053#if defined(UCPD2)
2054#define __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
2055#endif /* UCPD2 */
2056#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
2057#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
2058#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
2059#if defined(FDCAN1) || defined(FDCAN2)
2060#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
2061#endif /* FDCAN1 || FDCAN2 */
2062#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
2063#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
2064#if defined(DAC1)
2065#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
2066#endif /* DAC1 */
2067#if defined(LPTIM2)
2068#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
2069#endif /* LPTIM2 */
2070#if defined(LPTIM1)
2071#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)
2072#endif /* LPTIM1 */
2073#if defined(TIM2)
2074#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN)
2075#endif /* TIM2 */
2076#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN)
2077#if defined(TIM4)
2078#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN)
2079#endif /* TIM4 */
2080#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN)
2081#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN)
2082#if defined(CRS)
2083#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN)
2084#endif /* CRS */
2085#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN)
2086#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN)
2087#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN)
2088#if defined(SPI3)
2089#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN)
2090#endif /* TIM2 */
2091#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN)
2092#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN)
2093#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN)
2094#if defined(USART5)
2095#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN)
2096#endif /* USART5 */
2097#if defined(USART6)
2098#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN)
2099#endif /* USART6 */
2100#if defined(LPUART1)
2101#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)
2102#endif /* LPUART1 */
2103#if defined(LPUART2)
2104#define __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)
2105#endif /* LPUART2 */
2106#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN)
2107#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN)
2108#if defined(I2C3)
2109#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN)
2110#endif /* I2C3 */
2111#if defined(CEC)
2112#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN)
2113#endif /* CEC */
2114#if defined(UCPD1)
2115#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN)
2116#endif /* UCPD1 */
2117#if defined(UCPD2)
2118#define __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN)
2119#endif /* UCPD2 */
2120#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
2121#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN)
2122#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
2123#if defined(FDCAN1) || defined(FDCAN2)
2124#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN)
2125#endif /* FDCAN1) || FDCAN2 */
2126#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN)
2127#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN)
2128#if defined(DAC1)
2129#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN)
2130#endif /* DAC1 */
2131#if defined(LPTIM2)
2132#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN)
2133#endif /* LPTIM2 */
2134#if defined(LPTIM1)
2135#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN)
2136#endif /* LPTIM1 */
2137/**
2138 * @}
2139 */
2140
2141/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
2142 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
2143 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2144 * power consumption.
2145 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2146 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2147 * @{
2148 */
2149
2150#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
2151#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
2152#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
2153#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
2154#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
2155#if defined(TIM15)
2156#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
2157#endif /* TIM15 */
2158#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
2159#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
2160#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)
2161
2162#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN)
2163#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN)
2164#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN)
2165#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN)
2166#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN)
2167#if defined(TIM15)
2168#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN)
2169#endif /* TIM15 */
2170#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN)
2171#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN)
2172#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN)
2173
2174/**
2175 * @}
2176 */
2177
2178/** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
2179 * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
2180 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2181 * power consumption.
2182 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2183 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2184 * @{
2185 */
2186
2187#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
2188#if defined(DMA2)
2189#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET)
2190#endif /* DMA2 */
2191#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET)
2192#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
2193#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
2194#if defined(RNG)
2195#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET)
2196#endif /* RNG */
2197#if defined(AES)
2198#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) != RESET)
2199#endif /* AES */
2200#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET)
2201#if defined(DMA2)
2202#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) == RESET)
2203#endif /* DMA2 */
2204#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET)
2205#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET)
2206#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET)
2207#if defined(RNG)
2208#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET)
2209#endif /* RNG */
2210#if defined(AES)
2211#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) == RESET)
2212#endif /* AES */
2213
2214/**
2215 * @}
2216 */
2217
2218/** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status
2219 * @brief Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not.
2220 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2221 * power consumption.
2222 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2223 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2224 * @{
2225 */
2226
2227
2228#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET)
2229#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET)
2230#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET)
2231#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET)
2232#if defined(GPIOE)
2233#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET)
2234#endif /* GPIOE */
2235#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET)
2236
2237
2238
2239#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET)
2240#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET)
2241#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET)
2242#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET)
2243#if defined(GPIOE)
2244#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET)
2245#endif /* GPIOE */
2246#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET)
2247
2248/**
2249 * @}
2250 */
2251
2252/** @defgroup RCC_APB1_Clock_Sleep_Enabled_Disabled_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
2253 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
2254 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2255 * power consumption.
2256 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2257 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2258 * @{
2259 */
2260#if defined(TIM2)
2261#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET)
2262#endif /* TIM2 */
2263#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET)
2264#if defined(TIM4)
2265#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) != RESET)
2266#endif /* TIM4 */
2267#if defined(TIM6)
2268#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) != RESET)
2269#endif /* TIM6 */
2270#if defined(TIM7)
2271#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) != RESET)
2272#endif /* TIM7 */
2273#if defined(CRS)
2274#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET)
2275#endif /* CRS */
2276#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET)
2277#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET)
2278#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET)
2279#if defined(SPI3)
2280#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) != RESET)
2281#endif /* SPI3 */
2282#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET)
2283#if defined(USART3)
2284#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET)
2285#endif /* USART3 */
2286#if defined(USART4)
2287#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET)
2288#endif /* USART4 */
2289#if defined(USART5)
2290#define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET)
2291#endif /* USART5 */
2292#if defined(USART6)
2293#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET)
2294#endif /* USART6 */
2295#if defined(LPUART1)
2296#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET)
2297#endif /* LPUART1 */
2298#if defined(LPUART2)
2299#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET)
2300#endif /* LPUART2 */
2301#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET)
2302#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET)
2303#if defined(I2C3)
2304#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) != RESET)
2305#endif /* I2C3 */
2306#if defined(CEC)
2307#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) != RESET)
2308#endif /* CEC */
2309#if defined(UCPD1)
2310#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) != RESET)
2311#endif /* UCPD1 */
2312#if defined(UCPD2)
2313#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) != RESET)
2314#endif /* UCPD2 */
2315#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
2316#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET)
2317#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
2318#if defined(FDCAN1) || defined(FDCAN2)
2319#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) != RESET)
2320#endif /* FDCAN1 || FDCAN2 */
2321#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET)
2322#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET)
2323#if defined(DAC1)
2324#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) != RESET)
2325#endif /* DAC1 */
2326#if defined(LPTIM2)
2327#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET)
2328#endif /* LPTIM2 */
2329#if defined(LPTIM1)
2330#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET)
2331#endif /* LPTIM1 */
2332#if defined(TIM2)
2333#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET)
2334#endif /* TIM2 */
2335#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET)
2336#if defined(TIM4)
2337#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) == RESET)
2338#endif /* TIM4 */
2339#if defined(TIM6)
2340#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) == RESET)
2341#endif /* TIM6 */
2342#if defined(TIM7)
2343#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) == RESET)
2344#endif /* TIM7 */
2345#if defined(CRS)
2346#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET)
2347#endif /* CRS */
2348#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET)
2349#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET)
2350#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET)
2351#if defined(SPI3)
2352#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) == RESET)
2353#endif /* SPI3 */
2354#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET)
2355#if defined(USART3)
2356#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET)
2357#endif /* USART3 */
2358#if defined(USART4)
2359#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET)
2360#endif /* USART4 */
2361#if defined(USART5)
2362#define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET)
2363#endif /* USART5 */
2364#if defined(USART6)
2365#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET)
2366#endif /* USART6 */
2367#if defined(LPUART1)
2368#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET)
2369#endif /* LPUART1 */
2370#if defined(LPUART2)
2371#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET)
2372#endif /* LPUART2 */
2373#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET)
2374#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET)
2375#if defined(I2C3)
2376#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) == RESET)
2377#endif /* I2C3 */
2378#if defined(CEC)
2379#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) == RESET)
2380#endif /* CEC */
2381#if defined(UCPD1)
2382#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) == RESET)
2383#endif /* UCPD1 */
2384#if defined(UCPD2)
2385#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) == RESET)
2386#endif /* UCPD2 */
2387#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
2388#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET)
2389#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
2390#if defined(FDCAN1) || defined(FDCAN2)
2391#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) == RESET)
2392#endif /* FDCAN1 || FDCAN2 */
2393#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET)
2394#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET)
2395#if defined(DAC1)
2396#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) == RESET)
2397#endif /* DAC1 */
2398#if defined(LPTIM2)
2399#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET)
2400#endif /* LPTIM2 */
2401#if defined(LPTIM1)
2402#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET)
2403#endif /* LPTIM1 */
2404
2405/**
2406 * @}
2407 */
2408
2409/** @defgroup RCC_APB2_Clock_Sleep_Enabled_Disabled_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
2410 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
2411 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2412 * power consumption.
2413 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2414 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2415 * @{
2416 */
2417
2418#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET)
2419#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET)
2420#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET)
2421#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET)
2422#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET)
2423#if defined(TIM15)
2424#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET)
2425#endif /* TIM15 */
2426#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET)
2427#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET)
2428#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET)
2429
2430
2431#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET)
2432#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET)
2433#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET)
2434#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET)
2435#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET)
2436#if defined(TIM15)
2437#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET)
2438#endif /* TIM15 */
2439#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET)
2440#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET)
2441#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET)
2442
2443
2444/**
2445 * @}
2446 */
2447
2448/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
2449 * @{
2450 */
2451
2452/** @brief Macros to force or release the Backup domain reset.
2453 * @note This function resets the RTC peripheral (including the backup registers)
2454 * and the RTC clock source selection in RCC_CSR register.
2455 * @note The BKPSRAM is not affected by this reset.
2456 * @retval None
2457 */
2458#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
2459
2460#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
2461
2462/**
2463 * @}
2464 */
2465
2466/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
2467 * @{
2468 */
2469
2470/** @brief Macros to enable or disable the RTC clock.
2471 * @note As the RTC is in the Backup domain and write access is denied to
2472 * this domain after reset, you have to enable write access using
2473 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
2474 * (to be done once after reset).
2475 * @note These macros must be used after the RTC clock source was selected.
2476 * @retval None
2477 */
2478#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
2479
2480#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
2481
2482/**
2483 * @}
2484 */
2485
2486/** @defgroup RCC_Clock_Configuration RCC Clock Configuration
2487 * @{
2488 */
2489
2490/** @brief Macros to enable the Internal High Speed oscillator (HSI).
2491 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
2492 * It is used (enabled by hardware) as system clock source after startup
2493 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
2494 * of the HSE used directly or indirectly as system clock (if the Clock
2495 * Security System CSS is enabled).
2496 * @note After enabling the HSI, the application software should wait on HSIRDY
2497 * flag to be set indicating that HSI clock is stable and can be used as
2498 * system clock source.
2499 * This parameter can be: ENABLE or DISABLE.
2500 * @retval None
2501 */
2502#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
2503
2504/** @brief Macros to disable the Internal High Speed oscillator (HSI).
2505 * @note HSI can not be stopped if it is used as system clock source. In this case,
2506 * you have to select another source of the system clock then stop the HSI.
2507 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
2508 * clock cycles.
2509 * @retval None
2510 */
2511#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
2512
2513/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
2514 * @note The calibration is used to compensate for the variations in voltage
2515 * and temperature that influence the frequency of the internal HSI RC.
2516 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
2517 * (default is RCC_HSICALIBRATION_DEFAULT).
2518 * This parameter must be a number between 0 and 127.
2519 * @retval None
2520 */
2521#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
2522 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
2523
2524/**
2525 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
2526 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
2527 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
2528 * speed because of the HSI startup time.
2529 * @note The enable of this function has not effect on the HSION bit.
2530 * This parameter can be: ENABLE or DISABLE.
2531 * @retval None
2532 */
2533#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
2534
2535#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
2536
2537/** @brief Macro to configure the HSISYS clock.
2538 * @param __HSIDIV__ specifies the HSI16 division factor.
2539 * This parameter can be one of the following values:
2540 * @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1
2541 * @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2
2542 * @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4
2543 * @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8
2544 * @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16
2545 * @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32
2546 * @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64
2547 * @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128
2548 */
2549#define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \
2550 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__))
2551
2552/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
2553 * @note After enabling the LSI, the application software should wait on
2554 * LSIRDY flag to be set indicating that LSI clock is stable and can
2555 * be used to clock the IWDG and/or the RTC.
2556 * @note LSI can not be disabled if the IWDG is running.
2557 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
2558 * clock cycles.
2559 * @retval None
2560 */
2561#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
2562
2563#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
2564
2565/**
2566 * @brief Macro to configure the External High Speed oscillator (HSE).
2567 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
2568 * supported by this macro. User should request a transition to HSE Off
2569 * first and then HSE On or HSE Bypass.
2570 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
2571 * software should wait on HSERDY flag to be set indicating that HSE clock
2572 * is stable and can be used to clock the PLL and/or system clock.
2573 * @note HSE state can not be changed if it is used directly or through the
2574 * PLL as system clock. In this case, you have to select another source
2575 * of the system clock then change the HSE state (ex. disable it).
2576 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
2577 * @note This function reset the CSSON bit, so if the clock security system(CSS)
2578 * was previously enabled you have to enable it again after calling this
2579 * function.
2580 * @param __STATE__ specifies the new state of the HSE.
2581 * This parameter can be one of the following values:
2582 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
2583 * 6 HSE oscillator clock cycles.
2584 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
2585 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
2586 * @retval None
2587 */
2588#define __HAL_RCC_HSE_CONFIG(__STATE__) do { \
2589 if((__STATE__) == RCC_HSE_ON) \
2590 { \
2591 SET_BIT(RCC->CR, RCC_CR_HSEON); \
2592 } \
2593 else if((__STATE__) == RCC_HSE_BYPASS) \
2594 { \
2595 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
2596 SET_BIT(RCC->CR, RCC_CR_HSEON); \
2597 } \
2598 else \
2599 { \
2600 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
2601 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
2602 } \
2603 } while(0U)
2604
2605/**
2606 * @brief Macro to configure the External Low Speed oscillator (LSE).
2607 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
2608 * supported by this macro. User should request a transition to LSE Off
2609 * first and then LSE On or LSE Bypass.
2610 * @note As the LSE is in the Backup domain and write access is denied to
2611 * this domain after reset, you have to enable write access using
2612 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
2613 * (to be done once after reset).
2614 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
2615 * software should wait on LSERDY flag to be set indicating that LSE clock
2616 * is stable and can be used to clock the RTC.
2617 * @param __STATE__ specifies the new state of the LSE.
2618 * This parameter can be one of the following values:
2619 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
2620 * 6 LSE oscillator clock cycles.
2621 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
2622 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
2623 * @retval None
2624 */
2625#define __HAL_RCC_LSE_CONFIG(__STATE__) do { \
2626 if((__STATE__) == RCC_LSE_ON) \
2627 { \
2628 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
2629 } \
2630 else if((__STATE__) == RCC_LSE_BYPASS) \
2631 { \
2632 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
2633 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
2634 } \
2635 else \
2636 { \
2637 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
2638 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
2639 } \
2640 } while(0U)
2641
2642#if defined(RCC_HSI48_SUPPORT)
2643/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
2644 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
2645 * @note After enabling the HSI48, the application software should wait on HSI48RDY
2646 * flag to be set indicating that HSI48 clock is stable.
2647 * This parameter can be: ENABLE or DISABLE.
2648 * @retval None
2649 */
2650#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON)
2651
2652#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON)
2653
2654#endif /* RCC_HSI48_SUPPORT */
2655
2656/**
2657 * @}
2658 */
2659
2660/** @addtogroup RCC_RTC_Clock_Configuration
2661 * @{
2662 */
2663
2664/** @brief Macros to configure the RTC clock (RTCCLK).
2665 * @note As the RTC clock configuration bits are in the Backup domain and write
2666 * access is denied to this domain after reset, you have to enable write
2667 * access using the Power Backup Access macro before to configure
2668 * the RTC clock source (to be done once after reset).
2669 * @note Once the RTC clock is configured it cannot be changed unless the
2670 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
2671 * a Power On Reset (POR).
2672 *
2673 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
2674 * This parameter can be one of the following values:
2675 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
2676 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
2677 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
2678 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
2679 *
2680 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
2681 * work in STOP and STANDBY modes, and can be used as wakeup source.
2682 * However, when the HSE clock is used as RTC clock source, the RTC
2683 * cannot be used in STOP and STANDBY modes.
2684 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
2685 * RTC clock source).
2686 * @retval None
2687 */
2688#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
2689 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
2690
2691
2692/** @brief Macro to get the RTC clock source.
2693 * @retval The returned value can be one of the following:
2694 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
2695 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
2696 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
2697 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
2698 */
2699#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
2700
2701/** @brief Macros to enable or disable the main PLL.
2702 * @note After enabling the main PLL, the application software should wait on
2703 * PLLRDY flag to be set indicating that PLL clock is stable and can
2704 * be used as system clock source.
2705 * @note The main PLL can not be disabled if it is used as system clock source
2706 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
2707 * @retval None
2708 */
2709
2710/**
2711 * @}
2712 */
2713
2714/** @addtogroup RCC_Clock_Configuration
2715 * @{
2716 */
2717
2718#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
2719
2720#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
2721
2722/** @brief Macro to configure the PLL clock source.
2723 * @note This function must be used only when the main PLL is disabled.
2724 * @param __PLLSOURCE__ specifies the PLL entry clock source.
2725 * This parameter can be one of the following values:
2726 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
2727 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
2728 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
2729 * @retval None
2730 *
2731 */
2732#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
2733 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
2734
2735/** @brief Macro to configure the PLL multiplication factor.
2736 * @note This function must be used only when the main PLL is disabled.
2737 * @param __PLLM__ specifies the division factor for PLL VCO input clock
2738 * This parameter must be a value of RCC_PLLM_Clock_Divider.
2739 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
2740 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
2741 * of 16 MHz to limit PLL jitter.
2742 * @retval None
2743 *
2744 */
2745#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
2746 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
2747
2748/**
2749 * @brief Macro to configure the main PLL clock source, multiplication and division factors.
2750 * @note This function must be used only when the main PLL is disabled.
2751 *
2752 * @param __PLLSOURCE__ specifies the PLL entry clock source.
2753 * This parameter can be one of the following values:
2754 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
2755 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
2756 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
2757 *
2758 * @param __PLLM__ specifies the division factor for PLL VCO input clock.
2759 * This parameter must be a value of RCC_PLLM_Clock_Divider.
2760 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
2761 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
2762 * of 16 MHz to limit PLL jitter.
2763 *
2764 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
2765 * This parameter must be a number between 8 and 86.
2766 * @note You have to set the PLLN parameter correctly to ensure that the VCO
2767 * output frequency is between 64 and 344 MHz.
2768 *
2769 * @param __PLLP__ specifies the division factor for ADC clock.
2770 * This parameter must be a value of @ref RCC_PLLP_Clock_Divider.
2771 *
2772 * @param __PLLQ__ specifies the division factor for RBG & HS Timers clocks.(1)
2773 * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider
2774 * @note (1)__PLLQ__ parameter availability depends on devices
2775 * @note If the USB FS is used in your application, you have to set the
2776 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
2777 * the RNG needs a frequency lower than or equal to 48 MHz to work
2778 * correctly.
2779 *
2780 * @param __PLLR__ specifies the division factor for the main system clock.
2781 * This parameter must be a value of RCC_PLLR_Clock_Divider
2782 * @note You have to set the PLL parameters correctly to not exceed 64MHZ.
2783 * @retval None
2784 */
2785#if defined(RCC_PLLQ_SUPPORT)
2786#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
2787 MODIFY_REG(RCC->PLLCFGR, \
2788 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
2789 RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \
2790 ((uint32_t) (__PLLSOURCE__) | \
2791 (uint32_t) (__PLLM__) | \
2792 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
2793 (uint32_t) (__PLLP__) | \
2794 (uint32_t) (__PLLQ__) | \
2795 (uint32_t) (__PLLR__)))
2796#else
2797#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \
2798 MODIFY_REG(RCC->PLLCFGR, \
2799 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
2800 RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLR), \
2801 ((uint32_t) (__PLLSOURCE__) | \
2802 (uint32_t) (__PLLM__) | \
2803 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
2804 (uint32_t) (__PLLP__) | \
2805 (uint32_t) (__PLLR__)))
2806#endif /* RCC_PLLQ_SUPPORT */
2807/** @brief Macro to get the oscillator used as PLL clock source.
2808 * @retval The oscillator used as PLL clock source. The returned value can be one
2809 * of the following:
2810 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source.
2811 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source.
2812 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source.
2813 */
2814#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
2815
2816/**
2817 * @brief Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
2818 * @note Enabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime
2819 * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot
2820 * be stopped if used as System Clock.
2821 * @note (*) RCC_PLLQCLK availability depends on devices
2822 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
2823 * This parameter can be one or a combination of the following values:
2824 * @arg @ref RCC_PLLPCLK This clock is used to generate the clock for the ADC.
2825 * @if defined(STM32G081xx)
2826 * @arg @ref RCC_PLLQCLK This Clock is used to generate the clock for the High Speed Timers,
2827 * and the random analog generator (<=48 MHz).
2828 * @endif
2829 * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz)
2830 * @retval None
2831 */
2832#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
2833
2834/**
2835 * @brief Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
2836 * @note Disabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime
2837 * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot
2838 * be stopped if used as System Clock.
2839 * @note (*) RCC_PLLQCLK availability depends on devices
2840 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
2841 * This parameter can be one or a combination of the following values:
2842 * @arg @ref RCC_PLLPCLK This clock may be used to generate the clock for the ADC, I2S1.
2843 * @if defined(STM32G081xx)
2844 * @arg @ref RCC_PLLQCLK This Clock may be used to generate the clock for the High Speed Timers,
2845 * and RNG (<=48 MHz).
2846 * @endif
2847 * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz)
2848 * @retval None
2849 */
2850#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
2851
2852/**
2853 * @brief Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK)
2854 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
2855 * This parameter can be one of the following values:
2856 * @arg RCC_PLLPCLK This clock may be used to generate the clock for ADC, I2S1.
2857 * @if defined(STM32G081xx)
2858 * @arg RCC_PLLQCLK This Clock may be used to generate the clock for the HS Timers,
2859 * the RNG (<=48 MHz).
2860 * @endif
2861 * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz)
2862 * @retval SET / RESET
2863 * @note (*) RCC_PLLQCLK availability depends on devices
2864 */
2865#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
2866
2867/**
2868 * @brief Macro to configure the system clock source.
2869 * @param __SYSCLKSOURCE__ specifies the system clock source.
2870 * This parameter can be one of the following values:
2871 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
2872 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
2873 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
2874 * @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source.
2875 * @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source.
2876 * @retval None
2877 */
2878#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
2879 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
2880
2881/** @brief Macro to get the clock source used as system clock.
2882 * @retval The clock source used as system clock. The returned value can be one
2883 * of the following:
2884 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock.
2885 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
2886 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock.
2887 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source.
2888 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source.
2889 */
2890#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
2891
2892/**
2893 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
2894 * @note As the LSE is in the Backup domain and write access is denied to
2895 * this domain after reset, you have to enable write access using
2896 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
2897 * (to be done once after reset).
2898 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
2899 * This parameter can be one of the following values:
2900 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
2901 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
2902 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
2903 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
2904 * @retval None
2905 */
2906#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
2907 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
2908
2909/** @brief Macro to configure the Microcontroller output clock.
2910 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
2911 * This parameter can be one of the following values:
2912 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
2913 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
2914 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
2915 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
2916 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
2917 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
2918 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
2919 * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source
2920 * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source
2921 * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source
2922 * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source
2923 @if STM32G0C1xx
2924 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
2925 @endif
2926 * @param __MCODIV__ specifies the MCO clock prescaler.
2927 * This parameter can be one of the following values:
2928 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
2929 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
2930 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
2931 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
2932 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
2933 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
2934 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
2935 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
2936 @if STM32G0C1xx
2937 * @arg @ref RCC_MCODIV_256 MCO clock source is divided by 256
2938 * @arg @ref RCC_MCODIV_512 MCO clock source is divided by 512
2939 * @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024
2940 @endif
2941 */
2942#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
2943 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
2944
2945#if defined(RCC_MCO2_SUPPORT)
2946/** @brief Macro to configure the Microcontroller output clock 2.
2947 * @param __MCOCLKSOURCE__ specifies the MCO2 clock source.
2948 * This parameter can be one of the following values:
2949 * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled
2950 * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source
2951 * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source
2952 * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source
2953 * @arg @ref RCC_MCO2SOURCE_PLLCLK Main PLL clock selected as MCO2 source
2954 * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source
2955 * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source
2956 * @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP output clock selected as MCO2 source
2957 * @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ output clock selected as MCO2 source
2958 * @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source
2959 * @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO2 source
2960 @if STM32G0C1xx
2961 * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48
2962 @endif
2963 * @param __MCODIV__ specifies the MCO clock prescaler.
2964 * This parameter can be one of the following values:
2965 * @arg @ref RCC_MCO2DIV_1 MCO2 clock source is divided by 1
2966 * @arg @ref RCC_MCO2DIV_2 MCO2 clock source is divided by 2
2967 * @arg @ref RCC_MCO2DIV_4 MCO2 clock source is divided by 4
2968 * @arg @ref RCC_MCO2DIV_8 MCO2 clock source is divided by 8
2969 * @arg @ref RCC_MCO2DIV_16 MCO2 clock source is divided by 16
2970 * @arg @ref RCC_MCO2DIV_32 MCO2 clock source is divided by 32
2971 * @arg @ref RCC_MCO2DIV_64 MCO2 clock source is divided by 64
2972 * @arg @ref RCC_MCO2DIV_128 MCO2 clock source is divided by 128
2973 * @arg @ref RCC_MCO2DIV_256 MCO2 clock source is divided by 256
2974 * @arg @ref RCC_MCO2DIV_512 MCO2 clock source is divided by 512
2975 * @arg @ref RCC_MCO2DIV_1024 MCO2 clock source is divided by 1024
2976 */
2977#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
2978 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
2979#endif /* RCC_MCO2_SUPPORT */
2980
2981/**
2982 * @}
2983 */
2984
2985/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
2986 * @brief macros to manage the specified RCC Flags and interrupts.
2987 * @{
2988 */
2989
2990/** @brief Enable RCC interrupt.
2991 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
2992 * This parameter can be any combination of the following values:
2993 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
2994 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
2995 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
2996 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
2997 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
2998 @if STM32G0C1xx
2999 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3000 @endif
3001 * @retval None
3002 */
3003#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
3004
3005/** @brief Disable RCC interrupt.
3006 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
3007 * This parameter can be any combination of the following values:
3008 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
3009 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
3010 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
3011 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
3012 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
3013 @if STM32G0C1xx
3014 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3015 @endif
3016 * @retval None
3017 */
3018#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
3019
3020/** @brief Clear RCC interrupt pending bits.
3021 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
3022 * This parameter can be any combination of the following values:
3023 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
3024 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
3025 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
3026 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
3027 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
3028 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
3029 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
3030 @if STM32G0C1xx
3031 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3032 @endif
3033 * @retval None
3034 */
3035#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
3036
3037/** @brief Check whether the RCC interrupt has occurred or not.
3038 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
3039 * This parameter can be one of the following values:
3040 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
3041 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
3042 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
3043 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
3044 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
3045 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
3046 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
3047 @if STM32G0C1xx
3048 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3049 @endif
3050 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
3051 */
3052#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
3053
3054/** @brief Set RMVF bit to clear the reset flags.
3055 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST,
3056 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
3057 * @retval None
3058 */
3059#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
3060
3061/** @brief Check whether the selected RCC flag is set or not.
3062 * @param __FLAG__ specifies the flag to check.
3063 * This parameter can be one of the following values:
3064 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
3065 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
3066 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
3067 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
3068 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
3069 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
3070 @if STM32G0C1xx
3071 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3072 @endif
3073 * @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset
3074 * @arg @ref RCC_FLAG_OBLRST OBLRST reset
3075 * @arg @ref RCC_FLAG_PINRST Pin reset
3076 * @arg @ref RCC_FLAG_SFTRST Software reset
3077 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
3078 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
3079 * @arg @ref RCC_FLAG_LPWRRST Low Power reset
3080 * @retval The new state of __FLAG__ (TRUE or FALSE).
3081 */
3082#if defined(RCC_HSI48_SUPPORT)
3083#define __HAL_RCC_GET_FLAG(__FLAG__) \
3084 (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
3085 ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \
3086 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
3087 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \
3088 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
3089#else
3090#define __HAL_RCC_GET_FLAG(__FLAG__) \
3091 (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
3092 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
3093 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \
3094 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
3095#endif /* RCC_HSI48_SUPPORT */
3096
3097/**
3098 * @}
3099 */
3100
3101/**
3102 * @}
3103 */
3104
3105/* Include RCC HAL Extended module */
3106#include "stm32g0xx_hal_rcc_ex.h"
3107
3108/* Exported functions --------------------------------------------------------*/
3109/** @addtogroup RCC_Exported_Functions
3110 * @{
3111 */
3112
3113
3114/** @addtogroup RCC_Exported_Functions_Group1
3115 * @{
3116 */
3117
3118/* Initialization and de-initialization functions ******************************/
3119HAL_StatusTypeDef HAL_RCC_DeInit(void);
3120HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
3121HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
3122
3123/**
3124 * @}
3125 */
3126
3127/** @addtogroup RCC_Exported_Functions_Group2
3128 * @{
3129 */
3130
3131/* Peripheral Control functions ************************************************/
3132void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
3133void HAL_RCC_EnableCSS(void);
3134void HAL_RCC_EnableLSECSS(void);
3135void HAL_RCC_DisableLSECSS(void);
3136uint32_t HAL_RCC_GetSysClockFreq(void);
3137uint32_t HAL_RCC_GetHCLKFreq(void);
3138uint32_t HAL_RCC_GetPCLK1Freq(void);
3139void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
3140void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
3141uint32_t HAL_RCC_GetResetSource(void);
3142/* LSE & HSE CSS NMI IRQ handler */
3143void HAL_RCC_NMI_IRQHandler(void);
3144/* User Callbacks in non blocking mode (IT mode) */
3145void HAL_RCC_CSSCallback(void);
3146void HAL_RCC_LSECSSCallback(void);
3147
3148/**
3149 * @}
3150 */
3151
3152/**
3153 * @}
3154 */
3155
3156/**
3157 * @}
3158 */
3159
3160/**
3161 * @}
3162 */
3163
3164#ifdef __cplusplus
3165}
3166#endif
3167
3168#endif /* STM32G0xx_HAL_RCC_H */
3169
Note: See TracBrowser for help on using the repository browser.