source: trunk/firmware/Drivers/CMSIS/Include/core_sc300.h

Last change on this file was 6, checked in by f.jahn, 8 months ago
File size: 107.7 KB
Line 
1/**************************************************************************//**
2 * @file core_sc300.h
3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
4 * @version V5.0.8
5 * @date 31. May 2019
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_SC300_H_GENERIC
32#define __CORE_SC300_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup SC3000
60 @{
61 */
62
63#include "cmsis_version.h"
64
65/* CMSIS SC300 definitions */
66#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
69 __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71#define __CORTEX_SC (300U) /*!< Cortex secure core */
72
73/** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75*/
76#define __FPU_USED 0U
77
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113#endif
114
115#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118#ifdef __cplusplus
119}
120#endif
121
122#endif /* __CORE_SC300_H_GENERIC */
123
124#ifndef __CMSIS_GENERIC
125
126#ifndef __CORE_SC300_H_DEPENDANT
127#define __CORE_SC300_H_DEPENDANT
128
129#ifdef __cplusplus
130 extern "C" {
131#endif
132
133/* check device defines and use defaults */
134#if defined __CHECK_DEVICE_DEFINES
135 #ifndef __SC300_REV
136 #define __SC300_REV 0x0000U
137 #warning "__SC300_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __NVIC_PRIO_BITS
146 #define __NVIC_PRIO_BITS 3U
147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
148 #endif
149
150 #ifndef __Vendor_SysTickConfig
151 #define __Vendor_SysTickConfig 0U
152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
153 #endif
154#endif
155
156/* IO definitions (access restrictions to peripheral registers) */
157/**
158 \defgroup CMSIS_glob_defs CMSIS Global Defines
159
160 <strong>IO Type Qualifiers</strong> are used
161 \li to specify the access to peripheral variables.
162 \li for automatic generation of peripheral register debug information.
163*/
164#ifdef __cplusplus
165 #define __I volatile /*!< Defines 'read only' permissions */
166#else
167 #define __I volatile const /*!< Defines 'read only' permissions */
168#endif
169#define __O volatile /*!< Defines 'write only' permissions */
170#define __IO volatile /*!< Defines 'read / write' permissions */
171
172/* following defines should be used for structure members */
173#define __IM volatile const /*! Defines 'read only' structure member permissions */
174#define __OM volatile /*! Defines 'write only' structure member permissions */
175#define __IOM volatile /*! Defines 'read / write' structure member permissions */
176
177/*@} end of group SC300 */
178
179
180
181/*******************************************************************************
182 * Register Abstraction
183 Core Register contain:
184 - Core Register
185 - Core NVIC Register
186 - Core SCB Register
187 - Core SysTick Register
188 - Core Debug Register
189 - Core MPU Register
190 ******************************************************************************/
191/**
192 \defgroup CMSIS_core_register Defines and Type Definitions
193 \brief Type definitions and defines for Cortex-M processor based devices.
194*/
195
196/**
197 \ingroup CMSIS_core_register
198 \defgroup CMSIS_CORE Status and Control Registers
199 \brief Core Register type definitions.
200 @{
201 */
202
203/**
204 \brief Union type to access the Application Program Status Register (APSR).
205 */
206typedef union
207{
208 struct
209 {
210 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
211 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
212 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
213 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
214 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
215 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
216 } b; /*!< Structure used for bit access */
217 uint32_t w; /*!< Type used for word access */
218} APSR_Type;
219
220/* APSR Register Definitions */
221#define APSR_N_Pos 31U /*!< APSR: N Position */
222#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
223
224#define APSR_Z_Pos 30U /*!< APSR: Z Position */
225#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
226
227#define APSR_C_Pos 29U /*!< APSR: C Position */
228#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
229
230#define APSR_V_Pos 28U /*!< APSR: V Position */
231#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
232
233#define APSR_Q_Pos 27U /*!< APSR: Q Position */
234#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
235
236
237/**
238 \brief Union type to access the Interrupt Program Status Register (IPSR).
239 */
240typedef union
241{
242 struct
243 {
244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
246 } b; /*!< Structure used for bit access */
247 uint32_t w; /*!< Type used for word access */
248} IPSR_Type;
249
250/* IPSR Register Definitions */
251#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
252#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
253
254
255/**
256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
257 */
258typedef union
259{
260 struct
261 {
262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
264 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
265 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
266 uint32_t T:1; /*!< bit: 24 Thumb bit */
267 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
268 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
269 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
270 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
271 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
272 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
273 } b; /*!< Structure used for bit access */
274 uint32_t w; /*!< Type used for word access */
275} xPSR_Type;
276
277/* xPSR Register Definitions */
278#define xPSR_N_Pos 31U /*!< xPSR: N Position */
279#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
280
281#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
282#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
283
284#define xPSR_C_Pos 29U /*!< xPSR: C Position */
285#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
286
287#define xPSR_V_Pos 28U /*!< xPSR: V Position */
288#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
289
290#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
291#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
292
293#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
294#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
295
296#define xPSR_T_Pos 24U /*!< xPSR: T Position */
297#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
298
299#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
300#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
301
302#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
303#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
304
305
306/**
307 \brief Union type to access the Control Registers (CONTROL).
308 */
309typedef union
310{
311 struct
312 {
313 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
314 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
315 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
316 } b; /*!< Structure used for bit access */
317 uint32_t w; /*!< Type used for word access */
318} CONTROL_Type;
319
320/* CONTROL Register Definitions */
321#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
322#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
323
324#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
325#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
326
327/*@} end of group CMSIS_CORE */
328
329
330/**
331 \ingroup CMSIS_core_register
332 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
333 \brief Type definitions for the NVIC Registers
334 @{
335 */
336
337/**
338 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
339 */
340typedef struct
341{
342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
343 uint32_t RESERVED0[24U];
344 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
345 uint32_t RESERVED1[24U];
346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
347 uint32_t RESERVED2[24U];
348 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
349 uint32_t RESERVED3[24U];
350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
351 uint32_t RESERVED4[56U];
352 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
353 uint32_t RESERVED5[644U];
354 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
355} NVIC_Type;
356
357/* Software Triggered Interrupt Register Definitions */
358#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
359#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
360
361/*@} end of group CMSIS_NVIC */
362
363
364/**
365 \ingroup CMSIS_core_register
366 \defgroup CMSIS_SCB System Control Block (SCB)
367 \brief Type definitions for the System Control Block Registers
368 @{
369 */
370
371/**
372 \brief Structure type to access the System Control Block (SCB).
373 */
374typedef struct
375{
376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
377 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
379 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
380 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
381 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
382 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
383 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
384 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
385 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
386 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
387 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
388 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
389 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
394 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
395 uint32_t RESERVED0[5U];
396 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
397 uint32_t RESERVED1[129U];
398 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
399} SCB_Type;
400
401/* SCB CPUID Register Definitions */
402#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
403#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
404
405#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
406#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
407
408#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
409#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
410
411#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
412#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
413
414#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
415#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
416
417/* SCB Interrupt Control State Register Definitions */
418#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
419#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
420
421#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
422#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
423
424#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
425#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
426
427#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
428#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
429
430#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
431#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
432
433#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
434#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
435
436#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
437#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
438
439#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
440#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
441
442#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
443#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
444
445#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
446#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
447
448/* SCB Vector Table Offset Register Definitions */
449#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
450#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
451
452#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
453#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
454
455/* SCB Application Interrupt and Reset Control Register Definitions */
456#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
457#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
458
459#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
460#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
461
462#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
463#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
464
465#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
466#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
467
468#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
469#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
470
471#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
472#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
473
474#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
475#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
476
477/* SCB System Control Register Definitions */
478#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
479#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
480
481#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
482#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
483
484#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
485#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
486
487/* SCB Configuration Control Register Definitions */
488#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
489#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
490
491#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
492#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
493
494#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
495#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
496
497#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
498#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
499
500#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
501#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
502
503#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
504#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
505
506/* SCB System Handler Control and State Register Definitions */
507#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
508#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
509
510#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
511#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
512
513#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
514#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
515
516#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
517#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
518
519#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
520#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
521
522#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
523#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
524
525#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
526#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
527
528#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
529#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
530
531#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
532#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
533
534#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
535#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
536
537#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
538#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
539
540#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
541#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
542
543#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
544#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
545
546#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
547#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
548
549/* SCB Configurable Fault Status Register Definitions */
550#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
551#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
552
553#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
554#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
555
556#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
557#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
558
559/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
560#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
561#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
562
563#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
564#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
565
566#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
567#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
568
569#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
570#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
571
572#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
573#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
574
575/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
576#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
577#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
578
579#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
580#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
581
582#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
583#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
584
585#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
586#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
587
588#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
589#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
590
591#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
592#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
593
594/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
595#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
596#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
597
598#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
599#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
600
601#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
602#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
603
604#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
605#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
606
607#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
608#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
609
610#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
611#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
612
613/* SCB Hard Fault Status Register Definitions */
614#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
615#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
616
617#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
618#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
619
620#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
621#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
622
623/* SCB Debug Fault Status Register Definitions */
624#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
625#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
626
627#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
628#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
629
630#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
631#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
632
633#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
634#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
635
636#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
637#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
638
639/*@} end of group CMSIS_SCB */
640
641
642/**
643 \ingroup CMSIS_core_register
644 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
645 \brief Type definitions for the System Control and ID Register not in the SCB
646 @{
647 */
648
649/**
650 \brief Structure type to access the System Control and ID Register not in the SCB.
651 */
652typedef struct
653{
654 uint32_t RESERVED0[1U];
655 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
656 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
657} SCnSCB_Type;
658
659/* Interrupt Controller Type Register Definitions */
660#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
661#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
662
663/* Auxiliary Control Register Definitions */
664#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
665#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
666
667#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
668#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
669
670#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
671#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
672
673/*@} end of group CMSIS_SCnotSCB */
674
675
676/**
677 \ingroup CMSIS_core_register
678 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
679 \brief Type definitions for the System Timer Registers.
680 @{
681 */
682
683/**
684 \brief Structure type to access the System Timer (SysTick).
685 */
686typedef struct
687{
688 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
689 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
690 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
691 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
692} SysTick_Type;
693
694/* SysTick Control / Status Register Definitions */
695#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
696#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
697
698#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
699#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
700
701#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
702#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
703
704#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
705#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
706
707/* SysTick Reload Register Definitions */
708#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
709#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
710
711/* SysTick Current Register Definitions */
712#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
713#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
714
715/* SysTick Calibration Register Definitions */
716#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
717#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
718
719#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
720#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
721
722#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
723#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
724
725/*@} end of group CMSIS_SysTick */
726
727
728/**
729 \ingroup CMSIS_core_register
730 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
731 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
732 @{
733 */
734
735/**
736 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
737 */
738typedef struct
739{
740 __OM union
741 {
742 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
743 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
744 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
745 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
746 uint32_t RESERVED0[864U];
747 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
748 uint32_t RESERVED1[15U];
749 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
750 uint32_t RESERVED2[15U];
751 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
752 uint32_t RESERVED3[32U];
753 uint32_t RESERVED4[43U];
754 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
755 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
756 uint32_t RESERVED5[6U];
757 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
758 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
759 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
760 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
761 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
762 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
763 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
764 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
765 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
766 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
767 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
768 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
769} ITM_Type;
770
771/* ITM Trace Privilege Register Definitions */
772#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
773#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
774
775/* ITM Trace Control Register Definitions */
776#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
777#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
778
779#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
780#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
781
782#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
783#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
784
785#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
786#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
787
788#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
789#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
790
791#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
792#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
793
794#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
795#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
796
797#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
798#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
799
800#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
801#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
802
803/* ITM Lock Status Register Definitions */
804#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
805#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
806
807#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
808#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
809
810#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
811#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
812
813/*@}*/ /* end of group CMSIS_ITM */
814
815
816/**
817 \ingroup CMSIS_core_register
818 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
819 \brief Type definitions for the Data Watchpoint and Trace (DWT)
820 @{
821 */
822
823/**
824 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
825 */
826typedef struct
827{
828 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
829 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
830 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
831 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
832 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
833 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
834 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
835 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
836 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
837 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
838 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
839 uint32_t RESERVED0[1U];
840 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
841 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
842 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
843 uint32_t RESERVED1[1U];
844 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
845 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
846 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
847 uint32_t RESERVED2[1U];
848 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
849 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
850 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
851} DWT_Type;
852
853/* DWT Control Register Definitions */
854#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
855#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
856
857#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
858#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
859
860#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
861#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
862
863#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
864#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
865
866#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
867#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
868
869#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
870#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
871
872#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
873#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
874
875#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
876#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
877
878#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
879#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
880
881#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
882#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
883
884#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
885#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
886
887#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
888#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
889
890#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
891#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
892
893#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
894#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
895
896#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
897#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
898
899#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
900#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
901
902#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
903#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
904
905#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
906#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
907
908/* DWT CPI Count Register Definitions */
909#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
910#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
911
912/* DWT Exception Overhead Count Register Definitions */
913#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
914#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
915
916/* DWT Sleep Count Register Definitions */
917#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
918#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
919
920/* DWT LSU Count Register Definitions */
921#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
922#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
923
924/* DWT Folded-instruction Count Register Definitions */
925#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
926#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
927
928/* DWT Comparator Mask Register Definitions */
929#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
930#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
931
932/* DWT Comparator Function Register Definitions */
933#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
934#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
935
936#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
937#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
938
939#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
940#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
941
942#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
943#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
944
945#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
946#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
947
948#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
949#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
950
951#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
952#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
953
954#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
955#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
956
957#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
958#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
959
960/*@}*/ /* end of group CMSIS_DWT */
961
962
963/**
964 \ingroup CMSIS_core_register
965 \defgroup CMSIS_TPI Trace Port Interface (TPI)
966 \brief Type definitions for the Trace Port Interface (TPI)
967 @{
968 */
969
970/**
971 \brief Structure type to access the Trace Port Interface Register (TPI).
972 */
973typedef struct
974{
975 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
976 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
977 uint32_t RESERVED0[2U];
978 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
979 uint32_t RESERVED1[55U];
980 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
981 uint32_t RESERVED2[131U];
982 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
983 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
984 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
985 uint32_t RESERVED3[759U];
986 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
987 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
988 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
989 uint32_t RESERVED4[1U];
990 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
991 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
992 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
993 uint32_t RESERVED5[39U];
994 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
995 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
996 uint32_t RESERVED7[8U];
997 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
998 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
999} TPI_Type;
1000
1001/* TPI Asynchronous Clock Prescaler Register Definitions */
1002#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1003#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1004
1005/* TPI Selected Pin Protocol Register Definitions */
1006#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1007#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1008
1009/* TPI Formatter and Flush Status Register Definitions */
1010#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1011#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1012
1013#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1014#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1015
1016#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1017#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1018
1019#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1020#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1021
1022/* TPI Formatter and Flush Control Register Definitions */
1023#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1024#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1025
1026#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1027#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1028
1029/* TPI TRIGGER Register Definitions */
1030#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1031#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1032
1033/* TPI Integration ETM Data Register Definitions (FIFO0) */
1034#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1035#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1036
1037#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1038#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1039
1040#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1041#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1042
1043#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1044#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1045
1046#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1047#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1048
1049#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1050#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1051
1052#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1053#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1054
1055/* TPI ITATBCTR2 Register Definitions */
1056#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
1057#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
1058
1059#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
1060#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
1061
1062/* TPI Integration ITM Data Register Definitions (FIFO1) */
1063#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1064#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1065
1066#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1067#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1068
1069#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1070#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1071
1072#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1073#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1074
1075#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1076#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1077
1078#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1079#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1080
1081#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1082#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1083
1084/* TPI ITATBCTR0 Register Definitions */
1085#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
1086#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
1087
1088#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
1089#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
1090
1091/* TPI Integration Mode Control Register Definitions */
1092#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1093#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1094
1095/* TPI DEVID Register Definitions */
1096#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1097#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1098
1099#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1100#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1101
1102#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1103#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1104
1105#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1106#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1107
1108#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1109#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1110
1111#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1112#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1113
1114/* TPI DEVTYPE Register Definitions */
1115#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1116#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1117
1118#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1119#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1120
1121/*@}*/ /* end of group CMSIS_TPI */
1122
1123
1124#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1125/**
1126 \ingroup CMSIS_core_register
1127 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1128 \brief Type definitions for the Memory Protection Unit (MPU)
1129 @{
1130 */
1131
1132/**
1133 \brief Structure type to access the Memory Protection Unit (MPU).
1134 */
1135typedef struct
1136{
1137 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1138 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1139 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1140 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1141 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1142 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1143 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1144 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1145 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1146 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1147 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1148} MPU_Type;
1149
1150/* MPU Type Register Definitions */
1151#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1152#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1153
1154#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1155#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1156
1157#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1158#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1159
1160/* MPU Control Register Definitions */
1161#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1162#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1163
1164#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1165#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1166
1167#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1168#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1169
1170/* MPU Region Number Register Definitions */
1171#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1172#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1173
1174/* MPU Region Base Address Register Definitions */
1175#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1176#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1177
1178#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1179#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1180
1181#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1182#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1183
1184/* MPU Region Attribute and Size Register Definitions */
1185#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1186#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1187
1188#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1189#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1190
1191#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1192#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1193
1194#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1195#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1196
1197#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1198#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1199
1200#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1201#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1202
1203#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1204#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1205
1206#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1207#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1208
1209#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1210#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1211
1212#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1213#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1214
1215/*@} end of group CMSIS_MPU */
1216#endif
1217
1218
1219/**
1220 \ingroup CMSIS_core_register
1221 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1222 \brief Type definitions for the Core Debug Registers
1223 @{
1224 */
1225
1226/**
1227 \brief Structure type to access the Core Debug Register (CoreDebug).
1228 */
1229typedef struct
1230{
1231 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1232 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1233 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1234 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1235} CoreDebug_Type;
1236
1237/* Debug Halting Control and Status Register Definitions */
1238#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1239#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1240
1241#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1242#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1243
1244#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1245#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1246
1247#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1248#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1249
1250#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1251#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1252
1253#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1254#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1255
1256#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1257#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1258
1259#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1260#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1261
1262#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1263#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1264
1265#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1266#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1267
1268#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1269#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1270
1271#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1272#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1273
1274/* Debug Core Register Selector Register Definitions */
1275#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1276#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1277
1278#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1279#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1280
1281/* Debug Exception and Monitor Control Register Definitions */
1282#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1283#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1284
1285#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1286#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1287
1288#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1289#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1290
1291#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1292#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1293
1294#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1295#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1296
1297#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1298#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1299
1300#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1301#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1302
1303#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1304#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1305
1306#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1307#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1308
1309#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1310#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1311
1312#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1313#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1314
1315#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1316#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1317
1318#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1319#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1320
1321/*@} end of group CMSIS_CoreDebug */
1322
1323
1324/**
1325 \ingroup CMSIS_core_register
1326 \defgroup CMSIS_core_bitfield Core register bit field macros
1327 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1328 @{
1329 */
1330
1331/**
1332 \brief Mask and shift a bit field value for use in a register bit range.
1333 \param[in] field Name of the register bit field.
1334 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1335 \return Masked and shifted value.
1336*/
1337#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1338
1339/**
1340 \brief Mask and shift a register value to extract a bit filed value.
1341 \param[in] field Name of the register bit field.
1342 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1343 \return Masked and shifted bit field value.
1344*/
1345#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1346
1347/*@} end of group CMSIS_core_bitfield */
1348
1349
1350/**
1351 \ingroup CMSIS_core_register
1352 \defgroup CMSIS_core_base Core Definitions
1353 \brief Definitions for base addresses, unions, and structures.
1354 @{
1355 */
1356
1357/* Memory mapping of Core Hardware */
1358#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1359#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1360#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1361#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1362#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1363#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1364#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1365#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1366
1367#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1368#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1369#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1370#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1371#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1372#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1373#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1374#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1375
1376#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1377 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1378 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1379#endif
1380
1381/*@} */
1382
1383
1384
1385/*******************************************************************************
1386 * Hardware Abstraction Layer
1387 Core Function Interface contains:
1388 - Core NVIC Functions
1389 - Core SysTick Functions
1390 - Core Debug Functions
1391 - Core Register Access Functions
1392 ******************************************************************************/
1393/**
1394 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1395*/
1396
1397
1398
1399/* ########################## NVIC functions #################################### */
1400/**
1401 \ingroup CMSIS_Core_FunctionInterface
1402 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1403 \brief Functions that manage interrupts and exceptions via the NVIC.
1404 @{
1405 */
1406
1407#ifdef CMSIS_NVIC_VIRTUAL
1408 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1409 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1410 #endif
1411 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1412#else
1413 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1414 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1415 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1416 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1417 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1418 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1419 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1420 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1421 #define NVIC_GetActive __NVIC_GetActive
1422 #define NVIC_SetPriority __NVIC_SetPriority
1423 #define NVIC_GetPriority __NVIC_GetPriority
1424 #define NVIC_SystemReset __NVIC_SystemReset
1425#endif /* CMSIS_NVIC_VIRTUAL */
1426
1427#ifdef CMSIS_VECTAB_VIRTUAL
1428 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1429 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1430 #endif
1431 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1432#else
1433 #define NVIC_SetVector __NVIC_SetVector
1434 #define NVIC_GetVector __NVIC_GetVector
1435#endif /* (CMSIS_VECTAB_VIRTUAL) */
1436
1437#define NVIC_USER_IRQ_OFFSET 16
1438
1439
1440/* The following EXC_RETURN values are saved the LR on exception entry */
1441#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1442#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1443#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1444
1445
1446/**
1447 \brief Set Priority Grouping
1448 \details Sets the priority grouping field using the required unlock sequence.
1449 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1450 Only values from 0..7 are used.
1451 In case of a conflict between priority grouping and available
1452 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1453 \param [in] PriorityGroup Priority grouping field.
1454 */
1455__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1456{
1457 uint32_t reg_value;
1458 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1459
1460 reg_value = SCB->AIRCR; /* read old register configuration */
1461 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1462 reg_value = (reg_value |
1463 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1464 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1465 SCB->AIRCR = reg_value;
1466}
1467
1468
1469/**
1470 \brief Get Priority Grouping
1471 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1472 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1473 */
1474__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1475{
1476 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1477}
1478
1479
1480/**
1481 \brief Enable Interrupt
1482 \details Enables a device specific interrupt in the NVIC interrupt controller.
1483 \param [in] IRQn Device specific interrupt number.
1484 \note IRQn must not be negative.
1485 */
1486__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1487{
1488 if ((int32_t)(IRQn) >= 0)
1489 {
1490 __COMPILER_BARRIER();
1491 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1492 __COMPILER_BARRIER();
1493 }
1494}
1495
1496
1497/**
1498 \brief Get Interrupt Enable status
1499 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1500 \param [in] IRQn Device specific interrupt number.
1501 \return 0 Interrupt is not enabled.
1502 \return 1 Interrupt is enabled.
1503 \note IRQn must not be negative.
1504 */
1505__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1506{
1507 if ((int32_t)(IRQn) >= 0)
1508 {
1509 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1510 }
1511 else
1512 {
1513 return(0U);
1514 }
1515}
1516
1517
1518/**
1519 \brief Disable Interrupt
1520 \details Disables a device specific interrupt in the NVIC interrupt controller.
1521 \param [in] IRQn Device specific interrupt number.
1522 \note IRQn must not be negative.
1523 */
1524__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1525{
1526 if ((int32_t)(IRQn) >= 0)
1527 {
1528 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1529 __DSB();
1530 __ISB();
1531 }
1532}
1533
1534
1535/**
1536 \brief Get Pending Interrupt
1537 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1538 \param [in] IRQn Device specific interrupt number.
1539 \return 0 Interrupt status is not pending.
1540 \return 1 Interrupt status is pending.
1541 \note IRQn must not be negative.
1542 */
1543__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1544{
1545 if ((int32_t)(IRQn) >= 0)
1546 {
1547 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1548 }
1549 else
1550 {
1551 return(0U);
1552 }
1553}
1554
1555
1556/**
1557 \brief Set Pending Interrupt
1558 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1559 \param [in] IRQn Device specific interrupt number.
1560 \note IRQn must not be negative.
1561 */
1562__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1563{
1564 if ((int32_t)(IRQn) >= 0)
1565 {
1566 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1567 }
1568}
1569
1570
1571/**
1572 \brief Clear Pending Interrupt
1573 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1574 \param [in] IRQn Device specific interrupt number.
1575 \note IRQn must not be negative.
1576 */
1577__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1578{
1579 if ((int32_t)(IRQn) >= 0)
1580 {
1581 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1582 }
1583}
1584
1585
1586/**
1587 \brief Get Active Interrupt
1588 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1589 \param [in] IRQn Device specific interrupt number.
1590 \return 0 Interrupt status is not active.
1591 \return 1 Interrupt status is active.
1592 \note IRQn must not be negative.
1593 */
1594__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1595{
1596 if ((int32_t)(IRQn) >= 0)
1597 {
1598 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1599 }
1600 else
1601 {
1602 return(0U);
1603 }
1604}
1605
1606
1607/**
1608 \brief Set Interrupt Priority
1609 \details Sets the priority of a device specific interrupt or a processor exception.
1610 The interrupt number can be positive to specify a device specific interrupt,
1611 or negative to specify a processor exception.
1612 \param [in] IRQn Interrupt number.
1613 \param [in] priority Priority to set.
1614 \note The priority cannot be set for every processor exception.
1615 */
1616__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1617{
1618 if ((int32_t)(IRQn) >= 0)
1619 {
1620 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1621 }
1622 else
1623 {
1624 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1625 }
1626}
1627
1628
1629/**
1630 \brief Get Interrupt Priority
1631 \details Reads the priority of a device specific interrupt or a processor exception.
1632 The interrupt number can be positive to specify a device specific interrupt,
1633 or negative to specify a processor exception.
1634 \param [in] IRQn Interrupt number.
1635 \return Interrupt Priority.
1636 Value is aligned automatically to the implemented priority bits of the microcontroller.
1637 */
1638__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1639{
1640
1641 if ((int32_t)(IRQn) >= 0)
1642 {
1643 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1644 }
1645 else
1646 {
1647 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1648 }
1649}
1650
1651
1652/**
1653 \brief Encode Priority
1654 \details Encodes the priority for an interrupt with the given priority group,
1655 preemptive priority value, and subpriority value.
1656 In case of a conflict between priority grouping and available
1657 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1658 \param [in] PriorityGroup Used priority group.
1659 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1660 \param [in] SubPriority Subpriority value (starting from 0).
1661 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1662 */
1663__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1664{
1665 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1666 uint32_t PreemptPriorityBits;
1667 uint32_t SubPriorityBits;
1668
1669 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1670 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1671
1672 return (
1673 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1674 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1675 );
1676}
1677
1678
1679/**
1680 \brief Decode Priority
1681 \details Decodes an interrupt priority value with a given priority group to
1682 preemptive priority value and subpriority value.
1683 In case of a conflict between priority grouping and available
1684 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1685 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1686 \param [in] PriorityGroup Used priority group.
1687 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1688 \param [out] pSubPriority Subpriority value (starting from 0).
1689 */
1690__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1691{
1692 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1693 uint32_t PreemptPriorityBits;
1694 uint32_t SubPriorityBits;
1695
1696 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1697 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1698
1699 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1700 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1701}
1702
1703
1704/**
1705 \brief Set Interrupt Vector
1706 \details Sets an interrupt vector in SRAM based interrupt vector table.
1707 The interrupt number can be positive to specify a device specific interrupt,
1708 or negative to specify a processor exception.
1709 VTOR must been relocated to SRAM before.
1710 \param [in] IRQn Interrupt number
1711 \param [in] vector Address of interrupt handler function
1712 */
1713__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1714{
1715 uint32_t vectors = (uint32_t )SCB->VTOR;
1716 (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
1717 /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
1718}
1719
1720
1721/**
1722 \brief Get Interrupt Vector
1723 \details Reads an interrupt vector from interrupt vector table.
1724 The interrupt number can be positive to specify a device specific interrupt,
1725 or negative to specify a processor exception.
1726 \param [in] IRQn Interrupt number.
1727 \return Address of interrupt handler function
1728 */
1729__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1730{
1731 uint32_t vectors = (uint32_t )SCB->VTOR;
1732 return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
1733}
1734
1735
1736/**
1737 \brief System Reset
1738 \details Initiates a system reset request to reset the MCU.
1739 */
1740__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1741{
1742 __DSB(); /* Ensure all outstanding memory accesses included
1743 buffered write are completed before reset */
1744 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1745 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1746 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1747 __DSB(); /* Ensure completion of memory access */
1748
1749 for(;;) /* wait until reset */
1750 {
1751 __NOP();
1752 }
1753}
1754
1755/*@} end of CMSIS_Core_NVICFunctions */
1756
1757
1758/* ########################## FPU functions #################################### */
1759/**
1760 \ingroup CMSIS_Core_FunctionInterface
1761 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1762 \brief Function that provides FPU type.
1763 @{
1764 */
1765
1766/**
1767 \brief get FPU type
1768 \details returns the FPU type
1769 \returns
1770 - \b 0: No FPU
1771 - \b 1: Single precision FPU
1772 - \b 2: Double + Single precision FPU
1773 */
1774__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1775{
1776 return 0U; /* No FPU */
1777}
1778
1779
1780/*@} end of CMSIS_Core_FpuFunctions */
1781
1782
1783
1784/* ################################## SysTick function ############################################ */
1785/**
1786 \ingroup CMSIS_Core_FunctionInterface
1787 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1788 \brief Functions that configure the System.
1789 @{
1790 */
1791
1792#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1793
1794/**
1795 \brief System Tick Configuration
1796 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1797 Counter is in free running mode to generate periodic interrupts.
1798 \param [in] ticks Number of ticks between two interrupts.
1799 \return 0 Function succeeded.
1800 \return 1 Function failed.
1801 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1802 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1803 must contain a vendor-specific implementation of this function.
1804 */
1805__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1806{
1807 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1808 {
1809 return (1UL); /* Reload value impossible */
1810 }
1811
1812 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1813 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1814 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1815 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1816 SysTick_CTRL_TICKINT_Msk |
1817 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1818 return (0UL); /* Function successful */
1819}
1820
1821#endif
1822
1823/*@} end of CMSIS_Core_SysTickFunctions */
1824
1825
1826
1827/* ##################################### Debug In/Output function ########################################### */
1828/**
1829 \ingroup CMSIS_Core_FunctionInterface
1830 \defgroup CMSIS_core_DebugFunctions ITM Functions
1831 \brief Functions that access the ITM debug interface.
1832 @{
1833 */
1834
1835extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1836#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1837
1838
1839/**
1840 \brief ITM Send Character
1841 \details Transmits a character via the ITM channel 0, and
1842 \li Just returns when no debugger is connected that has booked the output.
1843 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1844 \param [in] ch Character to transmit.
1845 \returns Character to transmit.
1846 */
1847__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1848{
1849 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1850 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1851 {
1852 while (ITM->PORT[0U].u32 == 0UL)
1853 {
1854 __NOP();
1855 }
1856 ITM->PORT[0U].u8 = (uint8_t)ch;
1857 }
1858 return (ch);
1859}
1860
1861
1862/**
1863 \brief ITM Receive Character
1864 \details Inputs a character via the external variable \ref ITM_RxBuffer.
1865 \return Received character.
1866 \return -1 No character pending.
1867 */
1868__STATIC_INLINE int32_t ITM_ReceiveChar (void)
1869{
1870 int32_t ch = -1; /* no character available */
1871
1872 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1873 {
1874 ch = ITM_RxBuffer;
1875 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1876 }
1877
1878 return (ch);
1879}
1880
1881
1882/**
1883 \brief ITM Check Character
1884 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1885 \return 0 No character available.
1886 \return 1 Character available.
1887 */
1888__STATIC_INLINE int32_t ITM_CheckChar (void)
1889{
1890
1891 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1892 {
1893 return (0); /* no character available */
1894 }
1895 else
1896 {
1897 return (1); /* character available */
1898 }
1899}
1900
1901/*@} end of CMSIS_core_DebugFunctions */
1902
1903
1904
1905
1906#ifdef __cplusplus
1907}
1908#endif
1909
1910#endif /* __CORE_SC300_H_DEPENDANT */
1911
1912#endif /* __CMSIS_GENERIC */
Note: See TracBrowser for help on using the repository browser.