<!DOCTYPE Register_Definition_File>
<Processor name="STM32C031" description="STM32C031">
  <RegisterGroup name="ADC" description="Analog to Digital Converter" start="0x40012400">
    <Register name="ADC_ISR" description="ADC interrupt and status register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ADRDY" description="ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
      </BitField>
      <BitField name="EOSMP" description="End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to ‘1’." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
      </BitField>
      <BitField name="EOC" description="End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="Channel conversion complete" start="0x1" />
      </BitField>
      <BitField name="EOS" description="End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="Conversion sequence complete" start="0x1" />
      </BitField>
      <BitField name="OVR" description="ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
      </BitField>
      <BitField name="AWD1" description="Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog event occurred" start="0x1" />
      </BitField>
      <BitField name="AWD2" description="Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog event occurred" start="0x1" />
      </BitField>
      <BitField name="AWD3" description="Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog event occurred" start="0x1" />
      </BitField>
      <BitField name="EOCAL" description="End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Calibration is not complete" start="0x0" />
        <Enum name="B_0x1" description="Calibration is complete" start="0x1" />
      </BitField>
      <BitField name="CCRDY" description="Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Channel configuration update not applied. " start="0x0" />
        <Enum name="B_0x1" description="Channel configuration update is applied." start="0x1" />
      </BitField>
    </Register>
    <Register name="ADC_IER" description="ADC interrupt enable register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ADRDYIE" description="ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADRDY interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
      </BitField>
      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
      </BitField>
      <BitField name="EOCIE" description="End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="EOC interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
      </BitField>
      <BitField name="EOSIE" description="End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
      </BitField>
      <BitField name="OVRIE" description="Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
      </BitField>
      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Analog watchdog interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Analog watchdog interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Analog watchdog interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="EOCALIE" description="End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="End of calibration interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="End of calibration interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CCRDYIE" description="Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Channel configuration ready interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Channel configuration ready interrupt enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="ADC_CR" description="ADC control register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ADEN" description="ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
      </BitField>
      <BitField name="ADDIS" description="ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to ‘1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No ADDIS command ongoing" start="0x0" />
        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. " start="0x1" />
      </BitField>
      <BitField name="ADSTART" description="ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No ADC conversion is ongoing." start="0x0" />
        <Enum name="B_0x1" description="Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting." start="0x1" />
      </BitField>
      <BitField name="ADSTP" description="ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to ‘1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)" start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No ADC stop conversion command ongoing" start="0x0" />
        <Enum name="B_0x1" description="Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress." start="0x1" />
      </BitField>
      <BitField name="ADVREGEN" description="ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC voltage regulator disabled" start="0x0" />
        <Enum name="B_0x1" description="ADC voltage regulator enabled" start="0x1" />
      </BitField>
      <BitField name="ADCAL" description="ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing)." start="31" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Calibration complete" start="0x0" />
        <Enum name="B_0x1" description="Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress." start="0x1" />
      </BitField>
    </Register>
    <Register name="ADC_CFGR1" description="ADC configuration register 1 " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMAEN" description="Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
      </BitField>
      <BitField name="DMACFG" description="Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 355 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA one shot mode selected" start="0x0" />
        <Enum name="B_0x1" description="DMA circular mode selected" start="0x1" />
      </BitField>
      <BitField name="SCANDIR" description="Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Upward scan (from CHSEL0 to CHSEL22)" start="0x0" />
        <Enum name="B_0x1" description="Backward scan (from CHSEL22 to CHSEL0)" start="0x1" />
      </BitField>
      <BitField name="RES" description="Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN = 0." start="3" size="2" access="Read/Write">
        <Enum name="B_0x0" description="12 bits" start="0x0" />
        <Enum name="B_0x1" description="10 bits" start="0x1" />
        <Enum name="B_0x2" description="8 bits" start="0x2" />
        <Enum name="B_0x3" description="6 bits" start="0x3" />
      </BitField>
      <BitField name="ALIGN" description="Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 353 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Right alignment" start="0x0" />
        <Enum name="B_0x1" description="Left alignment" start="0x1" />
      </BitField>
      <BitField name="EXTSEL" description="External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="6" size="3" access="Read/Write">
        <Enum name="B_0x0" description="TRG0" start="0x0" />
        <Enum name="B_0x1" description="TRG1" start="0x1" />
        <Enum name="B_0x2" description="TRG2" start="0x2" />
        <Enum name="B_0x3" description="TRG3" start="0x3" />
        <Enum name="B_0x4" description="TRG4" start="0x4" />
        <Enum name="B_0x5" description="TRG5" start="0x5" />
        <Enum name="B_0x6" description="TRG6" start="0x6" />
        <Enum name="B_0x7" description="TRG7" start="0x7" />
      </BitField>
      <BitField name="EXTEN" description="External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be started by software)" start="0x0" />
        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="OVRMOD" description="Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected. " start="0x0" />
        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
      </BitField>
      <BitField name="CONT" description="Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
      </BitField>
      <BitField name="WAIT" description="Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Wait conversion mode off" start="0x0" />
        <Enum name="B_0x1" description="Wait conversion mode on" start="0x1" />
      </BitField>
      <BitField name="AUTOFF" description="Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Auto-off mode disabled" start="0x0" />
        <Enum name="B_0x1" description="Auto-off mode enabled" start="0x1" />
      </BitField>
      <BitField name="DISCEN" description="Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Discontinuous mode disabled" start="0x0" />
        <Enum name="B_0x1" description="Discontinuous mode enabled" start="0x1" />
      </BitField>
      <BitField name="CHSELRMOD" description="Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Each bit of the ADC_CHSELR register enables an input " start="0x0" />
        <Enum name="B_0x1" description="ADC_CHSELR register is able to sequence up to 8 channels" start="0x1" />
      </BitField>
      <BitField name="AWD1SGL" description="Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
      </BitField>
      <BitField name="AWD1EN" description="Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Analog watchdog 1 disabled" start="0x0" />
        <Enum name="B_0x1" description="Analog watchdog 1 enabled" start="0x1" />
      </BitField>
      <BitField name="AWD1CH" description="Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog input Channel 0 monitored by AWD" start="0x0" />
        <Enum name="B_0x1" description="ADC analog input Channel 1 monitored by AWD" start="0x1" />
        <Enum name="B_0x16" description="ADC analog input Channel 22 monitored by AWD " start="0x16" />
      </BitField>
    </Register>
    <Register name="ADC_CFGR2" description="ADC configuration register 2 " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OVSE" description="Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Oversampler disabled" start="0x0" />
        <Enum name="B_0x1" description="Oversampler enabled" start="0x1" />
      </BitField>
      <BitField name="OVSR" description="Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="2" size="3" access="Read/Write">
        <Enum name="B_0x0" description="2x" start="0x0" />
        <Enum name="B_0x1" description="4x" start="0x1" />
        <Enum name="B_0x2" description="8x" start="0x2" />
        <Enum name="B_0x3" description="16x" start="0x3" />
        <Enum name="B_0x4" description="32x" start="0x4" />
        <Enum name="B_0x5" description="64x" start="0x5" />
        <Enum name="B_0x6" description="128x" start="0x6" />
        <Enum name="B_0x7" description="256x" start="0x7" />
      </BitField>
      <BitField name="OVSS" description="Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="5" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No shift" start="0x0" />
        <Enum name="B_0x1" description="Shift 1-bit" start="0x1" />
        <Enum name="B_0x2" description="Shift 2-bits" start="0x2" />
        <Enum name="B_0x3" description="Shift 3-bits" start="0x3" />
        <Enum name="B_0x4" description="Shift 4-bits" start="0x4" />
        <Enum name="B_0x5" description="Shift 5-bits" start="0x5" />
        <Enum name="B_0x6" description="Shift 6-bits" start="0x6" />
        <Enum name="B_0x7" description="Shift 7-bits" start="0x7" />
        <Enum name="B_0x8" description="Shift 8-bits" start="0x8" />
      </BitField>
      <BitField name="TOVS" description="Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively after a trigger" start="0x0" />
        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a trigger" start="0x1" />
      </BitField>
      <BitField name="LFTRIG" description="Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)." start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Low Frequency Trigger Mode disabled" start="0x0" />
        <Enum name="B_0x1" description="Low Frequency Trigger Mode enabled" start="0x1" />
      </BitField>
      <BitField name="CKMODE" description="ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)" start="0x0" />
        <Enum name="B_0x1" description="PCLK/2 (Synchronous clock mode)" start="0x1" />
        <Enum name="B_0x2" description="PCLK/4 (Synchronous clock mode)" start="0x2" />
        <Enum name="B_0x3" description="PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)" start="0x3" />
      </BitField>
    </Register>
    <Register name="ADC_SMPR" description="ADC sampling time register " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SMP1" description="Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="3" access="Read/Write">
        <Enum name="B_0x0" description="1.5 ADC clock cycles " start="0x0" />
        <Enum name="B_0x1" description="3.5 ADC clock cycles " start="0x1" />
        <Enum name="B_0x2" description="7.5 ADC clock cycles " start="0x2" />
        <Enum name="B_0x3" description="12.5 ADC clock cycles " start="0x3" />
        <Enum name="B_0x4" description="19.5 ADC clock cycles " start="0x4" />
        <Enum name="B_0x5" description="39.5 ADC clock cycles " start="0x5" />
        <Enum name="B_0x6" description="79.5 ADC clock cycles " start="0x6" />
        <Enum name="B_0x7" description="160.5 ADC clock cycles " start="0x7" />
      </BitField>
      <BitField name="SMP2" description="Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="1.5 ADC clock cycles " start="0x0" />
        <Enum name="B_0x1" description="3.5 ADC clock cycles " start="0x1" />
        <Enum name="B_0x2" description="7.5 ADC clock cycles " start="0x2" />
        <Enum name="B_0x3" description="12.5 ADC clock cycles " start="0x3" />
        <Enum name="B_0x4" description="19.5 ADC clock cycles " start="0x4" />
        <Enum name="B_0x5" description="39.5 ADC clock cycles " start="0x5" />
        <Enum name="B_0x6" description="79.5 ADC clock cycles " start="0x6" />
        <Enum name="B_0x7" description="160.5 ADC clock cycles " start="0x7" />
      </BitField>
      <BitField name="SMPSEL0" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL1" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL2" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL3" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL4" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL5" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL6" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL7" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL8" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL9" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL10" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL11" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL12" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL13" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL14" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL15" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL16" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="24" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL17" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="25" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL18" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL19" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL20" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL21" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
      <BitField name="SMPSEL22" description="Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels." start="30" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Sampling time of CHANNELx use the setting of SMP1[2:0] register. " start="0x0" />
        <Enum name="B_0x1" description="Sampling time of CHANNELx use the setting of SMP2[2:0] register. " start="0x1" />
      </BitField>
    </Register>
    <Register name="ADC_AWD1TR" description="ADC watchdog threshold register " start="+0x20" size="4" reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
      <BitField name="LT1" description="Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359." start="0" size="12" access="Read/Write" />
      <BitField name="HT1" description="Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359." start="16" size="12" access="Read/Write" />
    </Register>
    <Register name="ADC_AWD2TR" description="ADC watchdog threshold register " start="+0x24" size="4" reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
      <BitField name="LT2" description="Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359." start="0" size="12" access="Read/Write" />
      <BitField name="HT2" description="Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359." start="16" size="12" access="Read/Write" />
    </Register>
    <Register name="ADC_CHSELR_MOD0" description="ADC channel selection register [alternate] " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CHSEL0" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL1" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL2" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL3" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL4" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL5" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL6" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL7" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL8" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL9" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL10" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL11" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL12" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL13" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL14" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL15" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL16" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL17" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL18" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL19" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL20" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL21" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
      <BitField name="CHSEL22" description="Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Input Channel-x is not selected for conversion" start="0x0" />
        <Enum name="B_0x1" description="Input Channel-x is selected for conversion" start="0x1" />
      </BitField>
    </Register>
    <Register name="ADC_CHSELR_MOD1" description="ADC channel selection register [alternate] " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SQ1" description="1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="4" access="Read/Write" />
      <BitField name="SQ2" description="2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="4" size="4" access="Read/Write" />
      <BitField name="SQ3" description="3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="8" size="4" access="Read/Write" />
      <BitField name="SQ4" description="4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="12" size="4" access="Read/Write" />
      <BitField name="SQ5" description="5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="16" size="4" access="Read/Write" />
      <BitField name="SQ6" description="6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="20" size="4" access="Read/Write" />
      <BitField name="SQ7" description="7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="24" size="4" access="Read/Write" />
      <BitField name="SQ8" description="8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="28" size="4" access="Read/Write">
        <Enum name="B_0x0" description="CH0 " start="0x0" />
        <Enum name="B_0x1" description="CH1" start="0x1" />
        <Enum name="B_0xC" description="CH12" start="0xC" />
        <Enum name="B_0xD" description="CH13" start="0xD" />
        <Enum name="B_0xE" description="CH14" start="0xE" />
        <Enum name="B_0xF" description="No channel selected (End of sequence)" start="0xF" />
      </BitField>
    </Register>
    <Register name="ADC_AWD3TR" description="ADC watchdog threshold register " start="+0x2c" size="4" reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
      <BitField name="LT3" description="Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359." start="0" size="12" access="Read/Write" />
      <BitField name="HT3" description="Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359." start="16" size="12" access="Read/Write" />
    </Register>
    <Register name="ADC_DR" description="ADC data register " start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DATA" description="Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 353. Just after a calibration is complete, DATA[6:0] contains the calibration factor." start="0" size="16" access="ReadOnly" />
    </Register>
    <Register name="ADC_AWD2CR" description="ADC Analog Watchdog 2 Configuration register " start="+0xa0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AWD2CH0" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH1" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH2" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH3" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH4" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH5" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH6" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH7" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH8" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH9" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH10" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH11" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH12" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH13" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH14" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH15" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH16" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH17" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH18" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH19" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH20" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH21" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
      <BitField name="AWD2CH22" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD2 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD2 " start="0x1" />
      </BitField>
    </Register>
    <Register name="ADC_AWD3CR" description="ADC Analog Watchdog 3 Configuration register " start="+0xa4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AWD3CH0" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH1" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH2" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH3" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH4" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH5" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH6" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH7" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH8" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH9" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH10" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH11" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH12" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH13" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH14" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH15" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH16" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH17" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH18" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH19" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH20" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH21" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
      <BitField name="AWD3CH22" description="Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ADC analog channel-x is not monitored by AWD3 " start="0x0" />
        <Enum name="B_0x1" description="ADC analog channel-x is monitored by AWD3 " start="0x1" />
      </BitField>
    </Register>
    <Register name="ADC_CALFACT" description="ADC Calibration factor " start="+0xb4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CALFACT" description="Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection." start="0" size="7" access="Read/Write" />
    </Register>
    <Register name="ADC_CCR" description="ADC common configuration register " start="+0x308" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PRESC" description="ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="18" size="4" access="Read/Write">
        <Enum name="B_0x0" description="input ADC clock not divided" start="0x0" />
        <Enum name="B_0x1" description="input ADC clock divided by 2" start="0x1" />
        <Enum name="B_0x2" description="input ADC clock divided by 4" start="0x2" />
        <Enum name="B_0x3" description="input ADC clock divided by 6" start="0x3" />
        <Enum name="B_0x4" description="input ADC clock divided by 8" start="0x4" />
        <Enum name="B_0x5" description="input ADC clock divided by 10" start="0x5" />
        <Enum name="B_0x6" description="input ADC clock divided by 12" start="0x6" />
        <Enum name="B_0x7" description="input ADC clock divided by 16" start="0x7" />
        <Enum name="B_0x8" description="input ADC clock divided by 32" start="0x8" />
        <Enum name="B_0x9" description="input ADC clock divided by 64" start="0x9" />
        <Enum name="B_0xA" description="input ADC clock divided by 128" start="0xA" />
        <Enum name="B_0xB" description="input ADC clock divided by 256" start="0xB" />
      </BitField>
      <BitField name="VREFEN" description="VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="VREFINT disabled" start="0x0" />
        <Enum name="B_0x1" description="VREFINT enabled" start="0x1" />
      </BitField>
      <BitField name="TSEN" description="Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Temperature sensor disabled" start="0x0" />
        <Enum name="B_0x1" description="Temperature sensor enabled" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="CRC" description="Cyclic redundancy check calculation unit" start="0x40023000">
    <Register name="CRC_DR" description="CRC data register " start="+0x0" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="DR" description="Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="CRC_IDR" description="CRC independent data register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="GPDR" description="General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register" start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="CRC_CR" description="CRC control register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RESET" description="RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware" start="0" size="1" access="Read/Write" />
      <BitField name="POLYSIZE" description="Polynomial size These bits control the size of the polynomial." start="3" size="2" access="Read/Write">
        <Enum name="B_0x0" description="32 bit polynomial" start="0x0" />
        <Enum name="B_0x1" description="16 bit polynomial" start="0x1" />
        <Enum name="B_0x2" description="8 bit polynomial" start="0x2" />
        <Enum name="B_0x3" description="7 bit polynomial" start="0x3" />
      </BitField>
      <BitField name="REV_IN" description="Reverse input data These bits control the reversal of the bit order of the input data" start="5" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Bit order not affected" start="0x0" />
        <Enum name="B_0x1" description="Bit reversal done by byte" start="0x1" />
        <Enum name="B_0x2" description="Bit reversal done by half-word" start="0x2" />
        <Enum name="B_0x3" description="Bit reversal done by word" start="0x3" />
      </BitField>
      <BitField name="REV_OUT" description="Reverse output data This bit controls the reversal of the bit order of the output data." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Bit order not affected" start="0x0" />
        <Enum name="B_0x1" description="Bit-reversed output format" start="0x1" />
      </BitField>
    </Register>
    <Register name="CRC_INIT" description="CRC initial value " start="+0x10" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="CRC_INIT" description="Programmable initial CRC value This register is used to write the CRC initial value." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="CRC_POL" description="CRC polynomial " start="+0x14" size="4" reset_value="0x04C11DB7" reset_mask="0xFFFFFFFF">
      <BitField name="POL" description="Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value." start="0" size="32" access="Read/Write" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="DBG" description="DBG register block" start="0x40015800">
    <Register name="DBG_IDCODE" description="DBG device ID code register " start="+0x0" size="4" reset_value="0x10000453" reset_mask="0xFFFFFFFF">
      <BitField name="DEV_ID" description="Device identifier This bitfield indicates the device ID." start="0" size="12" access="ReadOnly" />
      <BitField name="REV_ID" description="Revision identifier This bitfield indicates the revision of the device." start="16" size="16" access="ReadOnly" />
    </Register>
    <Register name="DBG_CR" description="DBG configuration register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DBG_STOP" description="Debug Stop mode" start="1" size="1" access="Read/Write" />
      <BitField name="DBG_STANDBY" description="Debug Standby and Shutdown modes" start="2" size="1" access="Read/Write" />
    </Register>
    <Register name="DBG_APB_FZ1" description="DBG APB freeze register 1 " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DBG_TIM3_STOP" description="Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
      <BitField name="DBG_RTC_STOP" description="Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:" start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
      <BitField name="DBG_WWDG_STOP" description="Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
      <BitField name="DBG_IWDG_STOP" description="Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:" start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
      <BitField name="DBG_I2C1_SMBUS_TIMEOUT" description="SMBUS timeout when core is halted" start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Same behavior as in normal mode" start="0x0" />
        <Enum name="B_0x1" description="The SMBUS timeout is frozen" start="0x1" />
      </BitField>
    </Register>
    <Register name="DBG_APB_FZ2" description="DBG APB freeze register 2 " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DBG_TIM1_STOP" description="Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
      <BitField name="DBG_TIM14_STOP" description="Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
      <BitField name="DBG_TIM16_STOP" description="Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:" start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
      <BitField name="DBG_TIM17_STOP" description="Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:" start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Enable" start="0x0" />
        <Enum name="B_0x1" description="Disable" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="DMA" description="DMA controller" start="0x40020000">
    <Register name="DMA_ISR" description="DMA interrupt status register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="GIF1" description="global interrupt flag for channel 1" start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TE, HT or TC event" start="0x0" />
        <Enum name="B_0x1" description="a TE, HT or TC event occurred" start="0x1" />
      </BitField>
      <BitField name="TCIF1" description="transfer complete (TC) flag for channel 1" start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TC event" start="0x0" />
        <Enum name="B_0x1" description="a TC event occurred" start="0x1" />
      </BitField>
      <BitField name="HTIF1" description="half transfer (HT) flag for channel 1" start="2" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no HT event " start="0x0" />
        <Enum name="B_0x1" description="a HT event occurred" start="0x1" />
      </BitField>
      <BitField name="TEIF1" description="transfer error (TE) flag for channel 1" start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TE event" start="0x0" />
        <Enum name="B_0x1" description="a TE event occurred" start="0x1" />
      </BitField>
      <BitField name="GIF2" description="global interrupt flag for channel 2" start="4" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TE, HT or TC event" start="0x0" />
        <Enum name="B_0x1" description="a TE, HT or TC event occurred" start="0x1" />
      </BitField>
      <BitField name="TCIF2" description="transfer complete (TC) flag for channel 2" start="5" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TC event" start="0x0" />
        <Enum name="B_0x1" description="a TC event occurred" start="0x1" />
      </BitField>
      <BitField name="HTIF2" description="half transfer (HT) flag for channel 2" start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no HT event " start="0x0" />
        <Enum name="B_0x1" description="a HT event occurred" start="0x1" />
      </BitField>
      <BitField name="TEIF2" description="transfer error (TE) flag for channel 2" start="7" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TE event" start="0x0" />
        <Enum name="B_0x1" description="a TE event occurred" start="0x1" />
      </BitField>
      <BitField name="GIF3" description="global interrupt flag for channel 3" start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TE, HT or TC event" start="0x0" />
        <Enum name="B_0x1" description="a TE, HT or TC event occurred" start="0x1" />
      </BitField>
      <BitField name="TCIF3" description="transfer complete (TC) flag for channel 3" start="9" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TC event" start="0x0" />
        <Enum name="B_0x1" description="a TC event occurred" start="0x1" />
      </BitField>
      <BitField name="HTIF3" description="half transfer (HT) flag for channel 3" start="10" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no HT event " start="0x0" />
        <Enum name="B_0x1" description="a HT event occurred" start="0x1" />
      </BitField>
      <BitField name="TEIF3" description="transfer error (TE) flag for channel 3" start="11" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="no TE event" start="0x0" />
        <Enum name="B_0x1" description="a TE event occurred" start="0x1" />
      </BitField>
    </Register>
    <Register name="DMA_IFCR" description="DMA interrupt flag clear register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CGIF1" description="global interrupt flag clear for channel 1" start="0" size="1" access="WriteOnly" />
      <BitField name="CTCIF1" description="transfer complete flag clear for channel 1" start="1" size="1" access="WriteOnly" />
      <BitField name="CHTIF1" description="half transfer flag clear for channel 1" start="2" size="1" access="WriteOnly" />
      <BitField name="CTEIF1" description="transfer error flag clear for channel 1" start="3" size="1" access="WriteOnly" />
      <BitField name="CGIF2" description="global interrupt flag clear for channel 2" start="4" size="1" access="WriteOnly" />
      <BitField name="CTCIF2" description="transfer complete flag clear for channel 2" start="5" size="1" access="WriteOnly" />
      <BitField name="CHTIF2" description="half transfer flag clear for channel 2" start="6" size="1" access="WriteOnly" />
      <BitField name="CTEIF2" description="transfer error flag clear for channel 2" start="7" size="1" access="WriteOnly" />
      <BitField name="CGIF3" description="global interrupt flag clear for channel 3" start="8" size="1" access="WriteOnly" />
      <BitField name="CTCIF3" description="transfer complete flag clear for channel 3" start="9" size="1" access="WriteOnly" />
      <BitField name="CHTIF3" description="half transfer flag clear for channel 3" start="10" size="1" access="WriteOnly" />
      <BitField name="CTEIF3" description="transfer error flag clear for channel 3" start="11" size="1" access="WriteOnly" />
    </Register>
    <Register name="DMA_CCR1" description="DMA channel 1 configuration register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EN" description="channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="HTIE" description="half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="TEIE" description="transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="DIR" description="data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="read from peripheral" start="0x0" />
        <Enum name="B_0x1" description="read from memory" start="0x1" />
      </BitField>
      <BitField name="CIRC" description="circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="PINC" description="peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="MINC" description="memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="PSIZE" description="peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="8 bits" start="0x0" />
        <Enum name="B_0x1" description="16 bits" start="0x1" />
        <Enum name="B_0x2" description="32 bits" start="0x2" />
      </BitField>
      <BitField name="MSIZE" description="memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="8 bits" start="0x0" />
        <Enum name="B_0x1" description="16 bits" start="0x1" />
        <Enum name="B_0x2" description="32 bits" start="0x2" />
      </BitField>
      <BitField name="PL" description="priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="low" start="0x0" />
        <Enum name="B_0x1" description="medium" start="0x1" />
        <Enum name="B_0x2" description="high" start="0x2" />
        <Enum name="B_0x3" description="very high" start="0x3" />
      </BitField>
      <BitField name="MEM2MEM" description="memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="DMA_CNDTR1" description="DMA channel 1 number of data to transfer register" start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="NDT" description="number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="DMA_CPAR1" description="DMA channel 1 peripheral address register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PA" description="peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="DMA_CMAR1" description="DMA channel 1 memory address register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="MA" description="peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="DMA_CCR2" description="DMA channel 2 configuration register" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EN" description="channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="HTIE" description="half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="TEIE" description="transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="DIR" description="data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="read from peripheral" start="0x0" />
        <Enum name="B_0x1" description="read from memory" start="0x1" />
      </BitField>
      <BitField name="CIRC" description="circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="PINC" description="peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="MINC" description="memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="PSIZE" description="peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="8 bits" start="0x0" />
        <Enum name="B_0x1" description="16 bits" start="0x1" />
        <Enum name="B_0x2" description="32 bits" start="0x2" />
      </BitField>
      <BitField name="MSIZE" description="memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="8 bits" start="0x0" />
        <Enum name="B_0x1" description="16 bits" start="0x1" />
        <Enum name="B_0x2" description="32 bits" start="0x2" />
      </BitField>
      <BitField name="PL" description="priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="low" start="0x0" />
        <Enum name="B_0x1" description="medium" start="0x1" />
        <Enum name="B_0x2" description="high" start="0x2" />
        <Enum name="B_0x3" description="very high" start="0x3" />
      </BitField>
      <BitField name="MEM2MEM" description="memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="DMA_CNDTR2" description="DMA channel 2 number of data to transfer register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="NDT" description="number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="DMA_CPAR2" description="DMA channel 2 peripheral address register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PA" description="peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="DMA_CMAR2" description="DMA channel 2 memory address register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="MA" description="peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="DMA_CCR3" description="DMA channel 3 configuration register" start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EN" description="channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="HTIE" description="half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="TEIE" description="transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="DIR" description="data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="read from peripheral" start="0x0" />
        <Enum name="B_0x1" description="read from memory" start="0x1" />
      </BitField>
      <BitField name="CIRC" description="circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="PINC" description="peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="MINC" description="memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
      <BitField name="PSIZE" description="peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="8 bits" start="0x0" />
        <Enum name="B_0x1" description="16 bits" start="0x1" />
        <Enum name="B_0x2" description="32 bits" start="0x2" />
      </BitField>
      <BitField name="MSIZE" description="memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="8 bits" start="0x0" />
        <Enum name="B_0x1" description="16 bits" start="0x1" />
        <Enum name="B_0x2" description="32 bits" start="0x2" />
      </BitField>
      <BitField name="PL" description="priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="low" start="0x0" />
        <Enum name="B_0x1" description="medium" start="0x1" />
        <Enum name="B_0x2" description="high" start="0x2" />
        <Enum name="B_0x3" description="very high" start="0x3" />
      </BitField>
      <BitField name="MEM2MEM" description="memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="disabled" start="0x0" />
        <Enum name="B_0x1" description="enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="DMA_CNDTR3" description="DMA channel 3 number of data to transfer register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="NDT" description="number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="DMA_CPAR3" description="DMA channel 3 peripheral address register" start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PA" description="peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="DMA_CMAR3" description="DMA channel 3 memory address register" start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="MA" description="peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)." start="0" size="32" access="Read/Write" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="DMAMUX" description="DMAMUX register block" start="0x40020800">
    <Register name="DMAMUX_C0CR" description="DMAMUX request line multiplexer channel 0 configuration register" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMAREQ_ID" description="DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources." start="0" size="6" access="Read/Write" />
      <BitField name="SOIE" description="Synchronization overrun interrupt enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="EGE" description="Event generation enable" start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Event generation disabled" start="0x0" />
        <Enum name="B_0x1" description="Event generation enabled" start="0x1" />
      </BitField>
      <BitField name="SE" description="Synchronization enable" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Synchronization disabled" start="0x0" />
        <Enum name="B_0x1" description="Synchronization enabled" start="0x1" />
      </BitField>
      <BitField name="SPOL" description="Synchronization polarity Defines the edge polarity of the selected synchronization input:" start="17" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No event, i.e. no synchronization nor detection." start="0x0" />
        <Enum name="B_0x1" description="Rising edge" start="0x1" />
        <Enum name="B_0x2" description="Falling edge" start="0x2" />
        <Enum name="B_0x3" description="Rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="NBREQ" description="Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low." start="19" size="5" access="Read/Write" />
      <BitField name="SYNC_ID" description="Synchronization identification Selects the synchronization input (see inputs to resources)." start="24" size="5" access="Read/Write" />
    </Register>
    <Register name="DMAMUX_C1CR" description="DMAMUX request line multiplexer channel 1 configuration register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMAREQ_ID" description="DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources." start="0" size="6" access="Read/Write" />
      <BitField name="SOIE" description="Synchronization overrun interrupt enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="EGE" description="Event generation enable" start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Event generation disabled" start="0x0" />
        <Enum name="B_0x1" description="Event generation enabled" start="0x1" />
      </BitField>
      <BitField name="SE" description="Synchronization enable" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Synchronization disabled" start="0x0" />
        <Enum name="B_0x1" description="Synchronization enabled" start="0x1" />
      </BitField>
      <BitField name="SPOL" description="Synchronization polarity Defines the edge polarity of the selected synchronization input:" start="17" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No event, i.e. no synchronization nor detection." start="0x0" />
        <Enum name="B_0x1" description="Rising edge" start="0x1" />
        <Enum name="B_0x2" description="Falling edge" start="0x2" />
        <Enum name="B_0x3" description="Rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="NBREQ" description="Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low." start="19" size="5" access="Read/Write" />
      <BitField name="SYNC_ID" description="Synchronization identification Selects the synchronization input (see inputs to resources)." start="24" size="5" access="Read/Write" />
    </Register>
    <Register name="DMAMUX_C2CR" description="DMAMUX request line multiplexer channel 2 configuration register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMAREQ_ID" description="DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources." start="0" size="6" access="Read/Write" />
      <BitField name="SOIE" description="Synchronization overrun interrupt enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="EGE" description="Event generation enable" start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Event generation disabled" start="0x0" />
        <Enum name="B_0x1" description="Event generation enabled" start="0x1" />
      </BitField>
      <BitField name="SE" description="Synchronization enable" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Synchronization disabled" start="0x0" />
        <Enum name="B_0x1" description="Synchronization enabled" start="0x1" />
      </BitField>
      <BitField name="SPOL" description="Synchronization polarity Defines the edge polarity of the selected synchronization input:" start="17" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No event, i.e. no synchronization nor detection." start="0x0" />
        <Enum name="B_0x1" description="Rising edge" start="0x1" />
        <Enum name="B_0x2" description="Falling edge" start="0x2" />
        <Enum name="B_0x3" description="Rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="NBREQ" description="Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low." start="19" size="5" access="Read/Write" />
      <BitField name="SYNC_ID" description="Synchronization identification Selects the synchronization input (see inputs to resources)." start="24" size="5" access="Read/Write" />
    </Register>
    <Register name="DMAMUX_CSR" description="DMAMUX request line multiplexer interrupt channel status register&#09;" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SOF0" description="Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register." start="0" size="1" access="ReadOnly" />
      <BitField name="SOF1" description="Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register." start="1" size="1" access="ReadOnly" />
      <BitField name="SOF2" description="Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register." start="2" size="1" access="ReadOnly" />
    </Register>
    <Register name="DMAMUX_CFR" description="DMAMUX request line multiplexer interrupt clear flag register&#09;" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CSOF0" description="Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register." start="0" size="1" access="WriteOnly" />
      <BitField name="CSOF1" description="Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register." start="1" size="1" access="WriteOnly" />
      <BitField name="CSOF2" description="Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register." start="2" size="1" access="WriteOnly" />
    </Register>
    <Register name="DMAMUX_RG0CR" description="DMAMUX request generator channel 0 configuration register" start="+0x100" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SIG_ID" description="Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator" start="0" size="5" access="Read/Write" />
      <BitField name="OIE" description="Trigger overrun interrupt enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt on a trigger overrun event occurrence is disabled" start="0x0" />
        <Enum name="B_0x1" description="Interrupt on a trigger overrun event occurrence is enabled" start="0x1" />
      </BitField>
      <BitField name="GE" description="DMA request generator channel x enable" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA request generator channel x disabled" start="0x0" />
        <Enum name="B_0x1" description="DMA request generator channel x enabled" start="0x1" />
      </BitField>
      <BitField name="GPOL" description="DMA request generator trigger polarity Defines the edge polarity of the selected trigger input" start="17" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No event, i.e. no trigger detection nor generation." start="0x0" />
        <Enum name="B_0x1" description="Rising edge" start="0x1" />
        <Enum name="B_0x2" description="Falling edge" start="0x2" />
        <Enum name="B_0x3" description="Rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="GNBREQ" description="Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled." start="19" size="5" access="Read/Write" />
    </Register>
    <Register name="DMAMUX_RG1CR" description="DMAMUX request generator channel 1 configuration register" start="+0x104" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SIG_ID" description="Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator" start="0" size="5" access="Read/Write" />
      <BitField name="OIE" description="Trigger overrun interrupt enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt on a trigger overrun event occurrence is disabled" start="0x0" />
        <Enum name="B_0x1" description="Interrupt on a trigger overrun event occurrence is enabled" start="0x1" />
      </BitField>
      <BitField name="GE" description="DMA request generator channel x enable" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA request generator channel x disabled" start="0x0" />
        <Enum name="B_0x1" description="DMA request generator channel x enabled" start="0x1" />
      </BitField>
      <BitField name="GPOL" description="DMA request generator trigger polarity Defines the edge polarity of the selected trigger input" start="17" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No event, i.e. no trigger detection nor generation." start="0x0" />
        <Enum name="B_0x1" description="Rising edge" start="0x1" />
        <Enum name="B_0x2" description="Falling edge" start="0x2" />
        <Enum name="B_0x3" description="Rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="GNBREQ" description="Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled." start="19" size="5" access="Read/Write" />
    </Register>
    <Register name="DMAMUX_RG2CR" description="DMAMUX request generator channel 2 configuration register" start="+0x108" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SIG_ID" description="Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator" start="0" size="5" access="Read/Write" />
      <BitField name="OIE" description="Trigger overrun interrupt enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt on a trigger overrun event occurrence is disabled" start="0x0" />
        <Enum name="B_0x1" description="Interrupt on a trigger overrun event occurrence is enabled" start="0x1" />
      </BitField>
      <BitField name="GE" description="DMA request generator channel x enable" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA request generator channel x disabled" start="0x0" />
        <Enum name="B_0x1" description="DMA request generator channel x enabled" start="0x1" />
      </BitField>
      <BitField name="GPOL" description="DMA request generator trigger polarity Defines the edge polarity of the selected trigger input" start="17" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No event, i.e. no trigger detection nor generation." start="0x0" />
        <Enum name="B_0x1" description="Rising edge" start="0x1" />
        <Enum name="B_0x2" description="Falling edge" start="0x2" />
        <Enum name="B_0x3" description="Rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="GNBREQ" description="Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled." start="19" size="5" access="Read/Write" />
    </Register>
    <Register name="DMAMUX_RG3CR" description="DMAMUX request generator channel 3 configuration register" start="+0x10c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SIG_ID" description="Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator" start="0" size="5" access="Read/Write" />
      <BitField name="OIE" description="Trigger overrun interrupt enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt on a trigger overrun event occurrence is disabled" start="0x0" />
        <Enum name="B_0x1" description="Interrupt on a trigger overrun event occurrence is enabled" start="0x1" />
      </BitField>
      <BitField name="GE" description="DMA request generator channel x enable" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA request generator channel x disabled" start="0x0" />
        <Enum name="B_0x1" description="DMA request generator channel x enabled" start="0x1" />
      </BitField>
      <BitField name="GPOL" description="DMA request generator trigger polarity Defines the edge polarity of the selected trigger input" start="17" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No event, i.e. no trigger detection nor generation." start="0x0" />
        <Enum name="B_0x1" description="Rising edge" start="0x1" />
        <Enum name="B_0x2" description="Falling edge" start="0x2" />
        <Enum name="B_0x3" description="Rising and falling edges" start="0x3" />
      </BitField>
      <BitField name="GNBREQ" description="Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled." start="19" size="5" access="Read/Write" />
    </Register>
    <Register name="DMAMUX_RGSR" description="DMAMUX request generator interrupt status register&#09;" start="+0x140" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OF0" description="Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register." start="0" size="1" access="ReadOnly" />
      <BitField name="OF1" description="Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register." start="1" size="1" access="ReadOnly" />
      <BitField name="OF2" description="Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register." start="2" size="1" access="ReadOnly" />
      <BitField name="OF3" description="Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register." start="3" size="1" access="ReadOnly" />
    </Register>
    <Register name="DMAMUX_RGCFR" description="DMAMUX request generator interrupt clear flag register&#09;" start="+0x144" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="COF0" description="Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register." start="0" size="1" access="WriteOnly" />
      <BitField name="COF1" description="Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register." start="1" size="1" access="WriteOnly" />
      <BitField name="COF2" description="Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register." start="2" size="1" access="WriteOnly" />
      <BitField name="COF3" description="Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register." start="3" size="1" access="WriteOnly" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="EXTI" description="EXTI address block description" start="0x40021800">
    <Register name="EXTI_RTSR1" description="EXTI rising trigger selection register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RT0" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT1" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT2" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT3" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT4" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT5" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT6" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT7" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT8" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT9" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT10" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT11" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT12" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT13" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT14" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RT15" description="Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="EXTI_FTSR1" description="EXTI falling trigger selection register 1 " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="FT0" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT1" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT2" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT3" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT4" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT5" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT6" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT7" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT8" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT9" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT10" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT11" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT12" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT13" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT14" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FT15" description="Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="EXTI_SWIER1" description="EXTI software interrupt event register 1 " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SWI0" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI1" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI2" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI3" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI4" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI5" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI6" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI7" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI8" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI9" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI10" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI11" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI12" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI13" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI14" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
      <BitField name="SWI15" description="Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Rising edge event generated on the corresponding line, followed by an interrupt" start="0x1" />
      </BitField>
    </Register>
    <Register name="EXTI_RPR1" description="EXTI rising edge pending register 1 " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RPIF0" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF1" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF2" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF3" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF4" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF5" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF6" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF7" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF8" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF9" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF10" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF11" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF12" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF13" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF14" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="RPIF15" description="Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No rising edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Rising edge trigger request occurred" start="0x1" />
      </BitField>
    </Register>
    <Register name="EXTI_FPR1" description="EXTI falling edge pending register 1 " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="FPIF0" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF1" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF2" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF3" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF4" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF5" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF6" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF7" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF8" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF9" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF10" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF11" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF12" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF13" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF14" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
      <BitField name="FPIF15" description="Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No falling edge trigger request occurred" start="0x0" />
        <Enum name="B_0x1" description="Falling edge trigger request occurred" start="0x1" />
      </BitField>
    </Register>
    <Register name="EXTI_EXTICR1" description="EXTI external interrupt selection register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EXTI0" description="EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved" start="0" size="8" access="Read/Write">
        <Enum name="B_0x0" description="PA[m] pin" start="0x0" />
        <Enum name="B_0x1" description="PB[m] pin" start="0x1" />
        <Enum name="B_0x2" description="PC[m] pin" start="0x2" />
        <Enum name="B_0x3" description="PD[m] pin" start="0x3" />
        <Enum name="B_0x5" description="PF[m] pin" start="0x5" />
      </BitField>
      <BitField name="EXTI1" start="8" size="8" access="Read/Write" />
      <BitField name="EXTI2" start="16" size="8" access="Read/Write" />
      <BitField name="EXTI3" start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="EXTI_EXTICR2" description="EXTI external interrupt selection register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EXTI0" description="EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved" start="0" size="8" access="Read/Write">
        <Enum name="B_0x0" description="PA[m] pin" start="0x0" />
        <Enum name="B_0x1" description="PB[m] pin" start="0x1" />
        <Enum name="B_0x2" description="PC[m] pin" start="0x2" />
        <Enum name="B_0x3" description="PD[m] pin" start="0x3" />
        <Enum name="B_0x5" description="PF[m] pin" start="0x5" />
      </BitField>
      <BitField name="EXTI1" start="8" size="8" access="Read/Write" />
      <BitField name="EXTI2" start="16" size="8" access="Read/Write" />
      <BitField name="EXTI3" start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="EXTI_EXTICR3" description="EXTI external interrupt selection register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EXTI0" description="EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved" start="0" size="8" access="Read/Write">
        <Enum name="B_0x0" description="PA[m] pin" start="0x0" />
        <Enum name="B_0x1" description="PB[m] pin" start="0x1" />
        <Enum name="B_0x2" description="PC[m] pin" start="0x2" />
        <Enum name="B_0x3" description="PD[m] pin" start="0x3" />
        <Enum name="B_0x5" description="PF[m] pin" start="0x5" />
      </BitField>
      <BitField name="EXTI1" start="8" size="8" access="Read/Write" />
      <BitField name="EXTI2" start="16" size="8" access="Read/Write" />
      <BitField name="EXTI3" start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="EXTI_EXTICR4" description="EXTI external interrupt selection register" start="+0x6c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EXTI0" description="EXTIm GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm external interrupt. Other: reserved" start="0" size="8" access="Read/Write">
        <Enum name="B_0x0" description="PA[m] pin" start="0x0" />
        <Enum name="B_0x1" description="PB[m] pin" start="0x1" />
        <Enum name="B_0x2" description="PC[m] pin" start="0x2" />
        <Enum name="B_0x3" description="PD[m] pin" start="0x3" />
        <Enum name="B_0x5" description="PF[m] pin" start="0x5" />
      </BitField>
      <BitField name="EXTI1" start="8" size="8" access="Read/Write" />
      <BitField name="EXTI2" start="16" size="8" access="Read/Write" />
      <BitField name="EXTI3" start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="EXTI_IMR1" description="EXTI CPU wakeup with interrupt mask register " start="+0x80" size="4" reset_value="0xFFF80000" reset_mask="0xFFFFFFFF">
      <BitField name="IM" description="CPU wakeup with interrupt mask" start="0" size="16" access="Read/Write" />
      <BitField name="IM19" description="IM19" start="19" size="1" access="Read/Write" />
      <BitField name="IM23" description="IM23" start="23" size="1" access="Read/Write" />
      <BitField name="IM25" description="IM25" start="25" size="1" access="Read/Write" />
      <BitField name="IM31" description="IM31" start="31" size="1" access="Read/Write" />
    </Register>
    <Register name="EXTI_EMR1" description="EXTI CPU wakeup with event mask register " start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EM" description="CPU wakeup with event generation mask" start="0" size="16" access="Read/Write" />
      <BitField name="EM19" description="EM19" start="19" size="1" access="Read/Write" />
      <BitField name="EM23" description="EM23" start="23" size="1" access="Read/Write" />
      <BitField name="EM25" description="EM25" start="25" size="1" access="Read/Write" />
      <BitField name="EM31" description="EM31" start="31" size="1" access="Read/Write" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="GPIOA" description="GPIOA address block description" start="0x50000000">
    <Register name="GPIOA_MODER" description="GPIO port mode register" start="+0x0" size="4" reset_value="0xEBFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="MODE0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOA_OTYPER" description="GPIO port output type register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OT0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOA_OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
      <BitField name="OSPEED0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOA_PUPDR" description="GPIO port pull-up/pull-down register" start="+0xc" size="4" reset_value="0x24000000" reset_mask="0xFFFFFFFF">
      <BitField name="PUPD0" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD1" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD2" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD3" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD4" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD5" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD6" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD7" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD8" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD9" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD10" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD11" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD12" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD13" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD14" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD15" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
    </Register>
    <Register name="GPIOA_IDR" description="GPIO port input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
      <BitField name="ID0" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" access="ReadOnly" />
      <BitField name="ID1" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" access="ReadOnly" />
      <BitField name="ID2" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" access="ReadOnly" />
      <BitField name="ID3" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" access="ReadOnly" />
      <BitField name="ID4" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" access="ReadOnly" />
      <BitField name="ID5" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" access="ReadOnly" />
      <BitField name="ID6" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" access="ReadOnly" />
      <BitField name="ID7" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" access="ReadOnly" />
      <BitField name="ID8" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" access="ReadOnly" />
      <BitField name="ID9" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" access="ReadOnly" />
      <BitField name="ID10" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" access="ReadOnly" />
      <BitField name="ID11" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" access="ReadOnly" />
      <BitField name="ID12" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" access="ReadOnly" />
      <BitField name="ID13" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" access="ReadOnly" />
      <BitField name="ID14" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" access="ReadOnly" />
      <BitField name="ID15" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" access="ReadOnly" />
    </Register>
    <Register name="GPIOA_ODR" description="GPIO port output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OD0" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="0" size="1" access="Read/Write" />
      <BitField name="OD1" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="1" size="1" access="Read/Write" />
      <BitField name="OD2" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="2" size="1" access="Read/Write" />
      <BitField name="OD3" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="3" size="1" access="Read/Write" />
      <BitField name="OD4" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="4" size="1" access="Read/Write" />
      <BitField name="OD5" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="5" size="1" access="Read/Write" />
      <BitField name="OD6" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="6" size="1" access="Read/Write" />
      <BitField name="OD7" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="7" size="1" access="Read/Write" />
      <BitField name="OD8" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="8" size="1" access="Read/Write" />
      <BitField name="OD9" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="9" size="1" access="Read/Write" />
      <BitField name="OD10" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="10" size="1" access="Read/Write" />
      <BitField name="OD11" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="11" size="1" access="Read/Write" />
      <BitField name="OD12" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="12" size="1" access="Read/Write" />
      <BitField name="OD13" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="13" size="1" access="Read/Write" />
      <BitField name="OD14" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="14" size="1" access="Read/Write" />
      <BitField name="OD15" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="GPIOA_BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BS0" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS1" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS2" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS3" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS4" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS5" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS6" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS7" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS8" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS9" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS10" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS11" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS12" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS13" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS14" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS15" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOA_LCKR" description="GPIO port configuration lock register" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LCK0" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK1" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK2" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK3" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK4" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK5" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK6" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK7" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK8" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK9" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK10" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK11" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK12" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK13" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK14" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK15" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns ‘1’ until the next MCU reset or peripheral reset." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOA_AFRL" description="GPIO alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL0" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL1" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL2" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL3" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL4" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL5" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL6" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL7" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOA_AFRH" description="GPIO alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL8" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL9" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL10" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL11" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL12" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL13" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL14" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL15" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOA_BRR" description="GPIO port bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="GPIOB" description="GPIOB address block description" start="0x50000400">
    <Register name="GPIOB_MODER" description="GPIO port mode register" start="+0x0" size="4" reset_value="0xEBFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="MODE0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOB_OTYPER" description="GPIO port output type register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OT0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOB_OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
      <BitField name="OSPEED0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOB_PUPDR" description="GPIO port pull-up/pull-down register" start="+0xc" size="4" reset_value="0x24000000" reset_mask="0xFFFFFFFF">
      <BitField name="PUPD0" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD1" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD2" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD3" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD4" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD5" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD6" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD7" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD8" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD9" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD10" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD11" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD12" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD13" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD14" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD15" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
    </Register>
    <Register name="GPIOB_IDR" description="GPIO port input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
      <BitField name="ID0" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" access="ReadOnly" />
      <BitField name="ID1" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" access="ReadOnly" />
      <BitField name="ID2" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" access="ReadOnly" />
      <BitField name="ID3" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" access="ReadOnly" />
      <BitField name="ID4" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" access="ReadOnly" />
      <BitField name="ID5" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" access="ReadOnly" />
      <BitField name="ID6" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" access="ReadOnly" />
      <BitField name="ID7" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" access="ReadOnly" />
      <BitField name="ID8" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" access="ReadOnly" />
      <BitField name="ID9" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" access="ReadOnly" />
      <BitField name="ID10" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" access="ReadOnly" />
      <BitField name="ID11" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" access="ReadOnly" />
      <BitField name="ID12" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" access="ReadOnly" />
      <BitField name="ID13" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" access="ReadOnly" />
      <BitField name="ID14" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" access="ReadOnly" />
      <BitField name="ID15" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" access="ReadOnly" />
    </Register>
    <Register name="GPIOB_ODR" description="GPIO port output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OD0" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="0" size="1" access="Read/Write" />
      <BitField name="OD1" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="1" size="1" access="Read/Write" />
      <BitField name="OD2" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="2" size="1" access="Read/Write" />
      <BitField name="OD3" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="3" size="1" access="Read/Write" />
      <BitField name="OD4" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="4" size="1" access="Read/Write" />
      <BitField name="OD5" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="5" size="1" access="Read/Write" />
      <BitField name="OD6" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="6" size="1" access="Read/Write" />
      <BitField name="OD7" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="7" size="1" access="Read/Write" />
      <BitField name="OD8" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="8" size="1" access="Read/Write" />
      <BitField name="OD9" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="9" size="1" access="Read/Write" />
      <BitField name="OD10" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="10" size="1" access="Read/Write" />
      <BitField name="OD11" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="11" size="1" access="Read/Write" />
      <BitField name="OD12" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="12" size="1" access="Read/Write" />
      <BitField name="OD13" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="13" size="1" access="Read/Write" />
      <BitField name="OD14" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="14" size="1" access="Read/Write" />
      <BitField name="OD15" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="GPIOB_BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BS0" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS1" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS2" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS3" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS4" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS5" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS6" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS7" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS8" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS9" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS10" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS11" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS12" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS13" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS14" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS15" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOB_LCKR" description="GPIO port configuration lock register" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LCK0" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK1" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK2" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK3" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK4" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK5" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK6" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK7" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK8" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK9" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK10" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK11" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK12" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK13" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK14" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK15" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns ‘1’ until the next MCU reset or peripheral reset." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOB_AFRL" description="GPIO alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL0" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL1" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL2" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL3" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL4" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL5" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL6" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL7" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOB_AFRH" description="GPIO alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL8" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL9" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL10" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL11" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL12" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL13" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL14" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL15" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOB_BRR" description="GPIO port bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="GPIOC" description="GPIOC address block description" start="0x50000800">
    <Register name="GPIOC_MODER" description="GPIO port mode register" start="+0x0" size="4" reset_value="0xEBFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="MODE0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOC_OTYPER" description="GPIO port output type register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OT0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOC_OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
      <BitField name="OSPEED0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOC_PUPDR" description="GPIO port pull-up/pull-down register" start="+0xc" size="4" reset_value="0x24000000" reset_mask="0xFFFFFFFF">
      <BitField name="PUPD0" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD1" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD2" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD3" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD4" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD5" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD6" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD7" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD8" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD9" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD10" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD11" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD12" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD13" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD14" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD15" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
    </Register>
    <Register name="GPIOC_IDR" description="GPIO port input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
      <BitField name="ID0" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" access="ReadOnly" />
      <BitField name="ID1" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" access="ReadOnly" />
      <BitField name="ID2" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" access="ReadOnly" />
      <BitField name="ID3" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" access="ReadOnly" />
      <BitField name="ID4" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" access="ReadOnly" />
      <BitField name="ID5" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" access="ReadOnly" />
      <BitField name="ID6" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" access="ReadOnly" />
      <BitField name="ID7" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" access="ReadOnly" />
      <BitField name="ID8" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" access="ReadOnly" />
      <BitField name="ID9" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" access="ReadOnly" />
      <BitField name="ID10" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" access="ReadOnly" />
      <BitField name="ID11" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" access="ReadOnly" />
      <BitField name="ID12" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" access="ReadOnly" />
      <BitField name="ID13" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" access="ReadOnly" />
      <BitField name="ID14" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" access="ReadOnly" />
      <BitField name="ID15" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" access="ReadOnly" />
    </Register>
    <Register name="GPIOC_ODR" description="GPIO port output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OD0" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="0" size="1" access="Read/Write" />
      <BitField name="OD1" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="1" size="1" access="Read/Write" />
      <BitField name="OD2" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="2" size="1" access="Read/Write" />
      <BitField name="OD3" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="3" size="1" access="Read/Write" />
      <BitField name="OD4" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="4" size="1" access="Read/Write" />
      <BitField name="OD5" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="5" size="1" access="Read/Write" />
      <BitField name="OD6" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="6" size="1" access="Read/Write" />
      <BitField name="OD7" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="7" size="1" access="Read/Write" />
      <BitField name="OD8" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="8" size="1" access="Read/Write" />
      <BitField name="OD9" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="9" size="1" access="Read/Write" />
      <BitField name="OD10" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="10" size="1" access="Read/Write" />
      <BitField name="OD11" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="11" size="1" access="Read/Write" />
      <BitField name="OD12" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="12" size="1" access="Read/Write" />
      <BitField name="OD13" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="13" size="1" access="Read/Write" />
      <BitField name="OD14" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="14" size="1" access="Read/Write" />
      <BitField name="OD15" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="GPIOC_BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BS0" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS1" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS2" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS3" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS4" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS5" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS6" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS7" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS8" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS9" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS10" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS11" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS12" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS13" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS14" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS15" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOC_LCKR" description="GPIO port configuration lock register" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LCK0" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK1" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK2" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK3" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK4" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK5" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK6" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK7" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK8" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK9" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK10" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK11" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK12" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK13" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK14" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK15" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns ‘1’ until the next MCU reset or peripheral reset." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOC_AFRL" description="GPIO alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL0" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL1" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL2" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL3" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL4" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL5" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL6" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL7" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOC_AFRH" description="GPIO alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL8" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL9" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL10" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL11" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL12" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL13" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL14" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL15" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOC_BRR" description="GPIO port bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="GPIOD" description="GPIOD address block description" start="0x50000C00">
    <Register name="GPIOD_MODER" description="GPIO port mode register" start="+0x0" size="4" reset_value="0xEBFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="MODE0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOD_OTYPER" description="GPIO port output type register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OT0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOD_OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
      <BitField name="OSPEED0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOD_PUPDR" description="GPIO port pull-up/pull-down register" start="+0xc" size="4" reset_value="0x24000000" reset_mask="0xFFFFFFFF">
      <BitField name="PUPD0" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD1" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD2" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD3" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD4" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD5" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD6" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD7" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD8" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD9" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD10" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD11" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD12" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD13" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD14" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD15" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
    </Register>
    <Register name="GPIOD_IDR" description="GPIO port input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
      <BitField name="ID0" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" access="ReadOnly" />
      <BitField name="ID1" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" access="ReadOnly" />
      <BitField name="ID2" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" access="ReadOnly" />
      <BitField name="ID3" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" access="ReadOnly" />
      <BitField name="ID4" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" access="ReadOnly" />
      <BitField name="ID5" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" access="ReadOnly" />
      <BitField name="ID6" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" access="ReadOnly" />
      <BitField name="ID7" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" access="ReadOnly" />
      <BitField name="ID8" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" access="ReadOnly" />
      <BitField name="ID9" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" access="ReadOnly" />
      <BitField name="ID10" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" access="ReadOnly" />
      <BitField name="ID11" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" access="ReadOnly" />
      <BitField name="ID12" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" access="ReadOnly" />
      <BitField name="ID13" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" access="ReadOnly" />
      <BitField name="ID14" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" access="ReadOnly" />
      <BitField name="ID15" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" access="ReadOnly" />
    </Register>
    <Register name="GPIOD_ODR" description="GPIO port output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OD0" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="0" size="1" access="Read/Write" />
      <BitField name="OD1" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="1" size="1" access="Read/Write" />
      <BitField name="OD2" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="2" size="1" access="Read/Write" />
      <BitField name="OD3" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="3" size="1" access="Read/Write" />
      <BitField name="OD4" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="4" size="1" access="Read/Write" />
      <BitField name="OD5" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="5" size="1" access="Read/Write" />
      <BitField name="OD6" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="6" size="1" access="Read/Write" />
      <BitField name="OD7" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="7" size="1" access="Read/Write" />
      <BitField name="OD8" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="8" size="1" access="Read/Write" />
      <BitField name="OD9" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="9" size="1" access="Read/Write" />
      <BitField name="OD10" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="10" size="1" access="Read/Write" />
      <BitField name="OD11" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="11" size="1" access="Read/Write" />
      <BitField name="OD12" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="12" size="1" access="Read/Write" />
      <BitField name="OD13" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="13" size="1" access="Read/Write" />
      <BitField name="OD14" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="14" size="1" access="Read/Write" />
      <BitField name="OD15" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="GPIOD_BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BS0" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS1" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS2" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS3" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS4" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS5" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS6" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS7" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS8" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS9" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS10" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS11" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS12" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS13" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS14" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS15" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOD_LCKR" description="GPIO port configuration lock register" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LCK0" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK1" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK2" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK3" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK4" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK5" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK6" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK7" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK8" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK9" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK10" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK11" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK12" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK13" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK14" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK15" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns ‘1’ until the next MCU reset or peripheral reset." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOD_AFRL" description="GPIO alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL0" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL1" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL2" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL3" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL4" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL5" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL6" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL7" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOD_AFRH" description="GPIO alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL8" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL9" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL10" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL11" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL12" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL13" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL14" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL15" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOD_BRR" description="GPIO port bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="GPIOF" description="GPIOF address block description" start="0x50001400">
    <Register name="GPIOF_MODER" description="GPIO port mode register" start="+0x0" size="4" reset_value="0xEBFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="MODE0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
      <BitField name="MODE15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Input" start="0x0" />
        <Enum name="B_0x1" description="Output" start="0x1" />
        <Enum name="B_0x2" description="Alternate function" start="0x2" />
        <Enum name="B_0x3" description="Analog" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOF_OTYPER" description="GPIO port output type register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OT0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
      <BitField name="OT15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output push-pull (reset state)" start="0x0" />
        <Enum name="B_0x1" description="Output open-drain" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOF_OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
      <BitField name="OSPEED0" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED1" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED2" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED3" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED4" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED5" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED6" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED7" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED8" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED9" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED10" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED11" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED12" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED13" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED14" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
      <BitField name="OSPEED15" description="Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed." start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Very low speed" start="0x0" />
        <Enum name="B_0x1" description="Low speed" start="0x1" />
        <Enum name="B_0x2" description="High speed" start="0x2" />
        <Enum name="B_0x3" description="Very high speed" start="0x3" />
      </BitField>
    </Register>
    <Register name="GPIOF_PUPDR" description="GPIO port pull-up/pull-down register" start="+0xc" size="4" reset_value="0x24000000" reset_mask="0xFFFFFFFF">
      <BitField name="PUPD0" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD1" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD2" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD3" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD4" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD5" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD6" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD7" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD8" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD9" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD10" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD11" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD12" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD13" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD14" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
      <BitField name="PUPD15" description="Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up, pull-down" start="0x0" />
        <Enum name="B_0x1" description="Pull-up" start="0x1" />
        <Enum name="B_0x2" description="Pull-down" start="0x2" />
      </BitField>
    </Register>
    <Register name="GPIOF_IDR" description="GPIO port input data register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFF0000">
      <BitField name="ID0" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" access="ReadOnly" />
      <BitField name="ID1" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" access="ReadOnly" />
      <BitField name="ID2" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" access="ReadOnly" />
      <BitField name="ID3" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" access="ReadOnly" />
      <BitField name="ID4" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" access="ReadOnly" />
      <BitField name="ID5" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" access="ReadOnly" />
      <BitField name="ID6" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" access="ReadOnly" />
      <BitField name="ID7" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" access="ReadOnly" />
      <BitField name="ID8" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" access="ReadOnly" />
      <BitField name="ID9" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" access="ReadOnly" />
      <BitField name="ID10" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" access="ReadOnly" />
      <BitField name="ID11" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" access="ReadOnly" />
      <BitField name="ID12" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" access="ReadOnly" />
      <BitField name="ID13" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" access="ReadOnly" />
      <BitField name="ID14" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" access="ReadOnly" />
      <BitField name="ID15" description="Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" access="ReadOnly" />
    </Register>
    <Register name="GPIOF_ODR" description="GPIO port output data register" start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OD0" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="0" size="1" access="Read/Write" />
      <BitField name="OD1" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="1" size="1" access="Read/Write" />
      <BitField name="OD2" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="2" size="1" access="Read/Write" />
      <BitField name="OD3" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="3" size="1" access="Read/Write" />
      <BitField name="OD4" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="4" size="1" access="Read/Write" />
      <BitField name="OD5" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="5" size="1" access="Read/Write" />
      <BitField name="OD6" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="6" size="1" access="Read/Write" />
      <BitField name="OD7" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="7" size="1" access="Read/Write" />
      <BitField name="OD8" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="8" size="1" access="Read/Write" />
      <BitField name="OD9" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="9" size="1" access="Read/Write" />
      <BitField name="OD10" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="10" size="1" access="Read/Write" />
      <BitField name="OD11" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="11" size="1" access="Read/Write" />
      <BitField name="OD12" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="12" size="1" access="Read/Write" />
      <BitField name="OD13" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="13" size="1" access="Read/Write" />
      <BitField name="OD14" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="14" size="1" access="Read/Write" />
      <BitField name="OD15" description="Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="GPIOF_BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BS0" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS1" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS2" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS3" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS4" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS5" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS6" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS7" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS8" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS9" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS10" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS11" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS12" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS13" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS14" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BS15" description="Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Sets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODRx bit" start="0x0" />
        <Enum name="B_0x1" description="Resets the corresponding ODRx bit" start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOF_LCKR" description="GPIO port configuration lock register" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LCK0" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK1" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK2" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK3" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK4" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK5" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK6" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK7" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK8" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK9" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK10" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK11" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK12" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK13" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK14" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCK15" description="Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration not locked" start="0x0" />
        <Enum name="B_0x1" description="Port configuration locked" start="0x1" />
      </BitField>
      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns ‘1’ until the next MCU reset or peripheral reset." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Port configuration lock key not active" start="0x0" />
        <Enum name="B_0x1" description="Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset." start="0x1" />
      </BitField>
    </Register>
    <Register name="GPIOF_AFRL" description="GPIO alternate function low register" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL0" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL1" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL2" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL3" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL4" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL5" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL6" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL7" description="Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOF_AFRH" description="GPIO alternate function high register" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="AFSEL8" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="0" size="4" access="Read/Write" />
      <BitField name="AFSEL9" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="4" size="4" access="Read/Write" />
      <BitField name="AFSEL10" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="8" size="4" access="Read/Write" />
      <BitField name="AFSEL11" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="12" size="4" access="Read/Write" />
      <BitField name="AFSEL12" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="16" size="4" access="Read/Write" />
      <BitField name="AFSEL13" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="20" size="4" access="Read/Write" />
      <BitField name="AFSEL14" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="24" size="4" access="Read/Write" />
      <BitField name="AFSEL15" description="Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="GPIOF_BRR" description="GPIO port bit reset register" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BR0" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR1" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR2" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="2" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR3" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR4" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR5" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR6" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR7" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR8" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR9" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR10" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="10" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR11" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="11" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR12" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="12" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR13" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="13" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR14" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="14" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
      <BitField name="BR15" description="Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000." start="15" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action on the corresponding ODx bit" start="0x0" />
        <Enum name="B_0x1" description="Reset the corresponding ODx bit" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="I2C" description="I2C register block" start="0x40005400">
    <Register name="I2C_CR1" description="I2C control register 1 " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PE" description="Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Peripheral disable" start="0x0" />
        <Enum name="B_0x1" description="Peripheral enable" start="0x1" />
      </BitField>
      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Transmit (TXIS) interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Transmit (TXIS) interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receive (RXNE) interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Receive (RXNE) interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Address match (ADDR) interrupts disabled" start="0x0" />
        <Enum name="B_0x1" description="Address match (ADDR) interrupts enabled" start="0x1" />
      </BitField>
      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Not acknowledge (NACKF) received interrupts disabled" start="0x0" />
        <Enum name="B_0x1" description="Not acknowledge (NACKF) received interrupts enabled" start="0x1" />
      </BitField>
      <BitField name="STOPIE" description="Stop detection Interrupt enable" start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Stop detection (STOPF) interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Stop detection (STOPF) interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)" start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Transfer Complete interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Transfer Complete interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="ERRIE" description="Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Error detection interrupts disabled" start="0x0" />
        <Enum name="B_0x1" description="Error detection interrupts enabled" start="0x1" />
      </BitField>
      <BitField name="DNF" description="Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)." start="8" size="4" access="Read/Write">
        <Enum name="B_0x0" description="Digital filter disabled " start="0x0" />
        <Enum name="B_0x1" description="Digital filter enabled and filtering capability up to 1 tI2CCLK" start="0x1" />
        <Enum name="B_0xF" description="digital filter enabled and filtering capability up to15 tI2CCLK" start="0xF" />
      </BitField>
      <BitField name="ANFOFF" description="Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Analog noise filter enabled" start="0x0" />
        <Enum name="B_0x1" description="Analog noise filter disabled" start="0x1" />
      </BitField>
      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA mode disabled for transmission" start="0x0" />
        <Enum name="B_0x1" description="DMA mode enabled for transmission" start="0x1" />
      </BitField>
      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA mode disabled for reception" start="0x0" />
        <Enum name="B_0x1" description="DMA mode enabled for reception" start="0x1" />
      </BitField>
      <BitField name="SBC" description="Slave byte control This bit is used to enable hardware byte control in slave mode." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Slave byte control disabled" start="0x0" />
        <Enum name="B_0x1" description="Slave byte control enabled" start="0x1" />
      </BitField>
      <BitField name="NOSTRETCH" description="Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Clock stretching enabled" start="0x0" />
        <Enum name="B_0x1" description="Clock stretching disabled" start="0x1" />
      </BitField>
      <BitField name="WUPEN" description="Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . Note: WUPEN can be set only when DNF = ‘0000’" start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Wakeup from Stop mode disable." start="0x0" />
        <Enum name="B_0x1" description="Wakeup from Stop mode enable." start="0x1" />
      </BitField>
      <BitField name="GCEN" description="General call enable" start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="General call disabled. Address 0b00000000 is NACKed." start="0x0" />
        <Enum name="B_0x1" description="General call enabled. Address 0b00000000 is ACKed." start="0x1" />
      </BitField>
      <BitField name="SMBHEN" description="SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Host address disabled. Address 0b0001000x is NACKed." start="0x0" />
        <Enum name="B_0x1" description="Host address enabled. Address 0b0001000x is ACKed." start="0x1" />
      </BitField>
      <BitField name="SMBDEN" description="SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Device default address disabled. Address 0b1100001x is NACKed." start="0x0" />
        <Enum name="B_0x1" description="Device default address enabled. Address 0b1100001x is ACKed." start="0x1" />
      </BitField>
      <BitField name="ALERTEN" description="SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). " start="0x0" />
        <Enum name="B_0x1" description="The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK)." start="0x1" />
      </BitField>
      <BitField name="PECEN" description="PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="PEC calculation disabled" start="0x0" />
        <Enum name="B_0x1" description="PEC calculation enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="I2C_CR2" description="I2C control register 2 " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SADD" description="Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="0" size="10" access="Read/Write" />
      <BitField name="RD_WRN" description="Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Master requests a write transfer." start="0x0" />
        <Enum name="B_0x1" description="Master requests a read transfer." start="0x1" />
      </BitField>
      <BitField name="ADD10" description="10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The master operates in 7-bit addressing mode," start="0x0" />
        <Enum name="B_0x1" description="The master operates in 10-bit addressing mode" start="0x1" />
      </BitField>
      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction." start="0x0" />
        <Enum name="B_0x1" description="The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction." start="0x1" />
      </BitField>
      <BitField name="START" description="Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing ‘0’ to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No Start generation." start="0x0" />
        <Enum name="B_0x1" description="Restart/Start generation:" start="0x1" />
      </BitField>
      <BitField name="STOP" description="Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing ‘0’ to this bit has no effect." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No Stop generation." start="0x0" />
        <Enum name="B_0x1" description="Stop generation after current byte transfer." start="0x1" />
      </BitField>
      <BitField name="NACK" description="NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing ‘0’ to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="an ACK is sent after current received byte." start="0x0" />
        <Enum name="B_0x1" description="a NACK is sent after current received byte." start="0x1" />
      </BitField>
      <BitField name="NBYTES" description="Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed." start="16" size="8" access="Read/Write" />
      <BitField name="RELOAD" description="NBYTES reload mode This bit is set and cleared by software." start="24" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The transfer is completed after the NBYTES data transfer (STOP or RESTART follows)." start="0x0" />
        <Enum name="B_0x1" description="The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low." start="0x1" />
      </BitField>
      <BitField name="AUTOEND" description="Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set." start="25" size="1" access="Read/Write">
        <Enum name="B_0x0" description="software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low." start="0x0" />
        <Enum name="B_0x1" description="Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred." start="0x1" />
      </BitField>
      <BitField name="PECBYTE" description="Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing ‘0’ to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No PEC transfer." start="0x0" />
        <Enum name="B_0x1" description="PEC transmission/reception is requested" start="0x1" />
      </BitField>
    </Register>
    <Register name="I2C_OAR1" description="I2C own address 1 register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OA1" description="Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0." start="0" size="10" access="Read/Write" />
      <BitField name="OA1MODE" description="Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Own address 1 is a 7-bit address." start="0x0" />
        <Enum name="B_0x1" description="Own address 1 is a 10-bit address." start="0x1" />
      </BitField>
      <BitField name="OA1EN" description="Own Address 1 enable" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Own address 1 disabled. The received slave address OA1 is NACKed." start="0x0" />
        <Enum name="B_0x1" description="Own address 1 enabled. The received slave address OA1 is ACKed." start="0x1" />
      </BitField>
    </Register>
    <Register name="I2C_OAR2" description="I2C own address 2 register " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OA2" description="Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0." start="1" size="7" access="Read/Write" />
      <BitField name="OA2MSK" description="Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches." start="8" size="3" access="Read/Write">
        <Enum name="B_0x0" description="No mask" start="0x0" />
        <Enum name="B_0x1" description="OA2[1] is masked and don’t care. Only OA2[7:2] are compared." start="0x1" />
        <Enum name="B_0x2" description="OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared." start="0x2" />
        <Enum name="B_0x3" description="OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared." start="0x3" />
        <Enum name="B_0x4" description="OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared." start="0x4" />
        <Enum name="B_0x5" description="OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared." start="0x5" />
        <Enum name="B_0x6" description="OA2[6:1] are masked and don’t care. Only OA2[7] is compared." start="0x6" />
        <Enum name="B_0x7" description="OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged." start="0x7" />
      </BitField>
      <BitField name="OA2EN" description="Own Address 2 enable" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Own address 2 disabled. The received slave address OA2 is NACKed." start="0x0" />
        <Enum name="B_0x1" description="Own address 2 enabled. The received slave address OA2 is ACKed." start="0x1" />
      </BitField>
    </Register>
    <Register name="I2C_TIMINGR" description="I2C timing register " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SCLL" description="SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings." start="0" size="8" access="Read/Write" />
      <BitField name="SCLH" description="SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing." start="8" size="8" access="Read/Write" />
      <BitField name="SDADEL" description="Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing." start="16" size="4" access="Read/Write" />
      <BitField name="SCLDEL" description="Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing." start="20" size="4" access="Read/Write" />
      <BitField name="PRESC" description="Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to ) and for SCL high and low level counters (refer to ). tPRESC = (PRESC+1) x tI2CCLK" start="28" size="4" access="Read/Write" />
    </Register>
    <Register name="I2C_TIMEOUTR" description="I2C timeout register " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIMEOUTA" description="Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0." start="0" size="12" access="Read/Write" />
      <BitField name="TIDLE" description="Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TIMEOUTA is used to detect SCL low timeout" start="0x0" />
        <Enum name="B_0x1" description="TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)" start="0x1" />
      </BitField>
      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="SCL timeout detection is disabled" start="0x0" />
        <Enum name="B_0x1" description="SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1)." start="0x1" />
      </BitField>
      <BitField name="TIMEOUTB" description="Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0." start="16" size="12" access="Read/Write" />
      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Extended clock timeout detection is disabled" start="0x0" />
        <Enum name="B_0x1" description="Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1)." start="0x1" />
      </BitField>
    </Register>
    <Register name="I2C_ISR" description="I2C interrupt and status register " start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
      <BitField name="TXE" description="Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to ‘1’ by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0." start="0" size="1" access="Read/Write" />
      <BitField name="TXIS" description="Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0." start="1" size="1" access="Read/Write" />
      <BitField name="RXNE" description="Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0." start="2" size="1" access="ReadOnly" />
      <BitField name="ADDR" description="Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0." start="3" size="1" access="ReadOnly" />
      <BitField name="NACKF" description="Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0." start="4" size="1" access="ReadOnly" />
      <BitField name="STOPF" description="Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0." start="5" size="1" access="ReadOnly" />
      <BitField name="TC" description="Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0." start="6" size="1" access="ReadOnly" />
      <BitField name="TCR" description="Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set." start="7" size="1" access="ReadOnly" />
      <BitField name="BERR" description="Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0." start="8" size="1" access="ReadOnly" />
      <BitField name="ARLO" description="Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0." start="9" size="1" access="ReadOnly" />
      <BitField name="OVR" description="Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0." start="10" size="1" access="ReadOnly" />
      <BitField name="PECERR" description="PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="11" size="1" access="ReadOnly" />
      <BitField name="TIMEOUT" description="Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="12" size="1" access="ReadOnly" />
      <BitField name="ALERT" description="SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="13" size="1" access="ReadOnly" />
      <BitField name="BUSY" description="Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE=0." start="15" size="1" access="ReadOnly" />
      <BitField name="DIR" description="Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)." start="16" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Write transfer, slave enters receiver mode." start="0x0" />
        <Enum name="B_0x1" description="Read transfer, slave enters transmitter mode." start="0x1" />
      </BitField>
      <BitField name="ADDCODE" description="Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address." start="17" size="7" access="ReadOnly" />
    </Register>
    <Register name="I2C_ICR" description="I2C interrupt clear register " start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ADDRCF" description="Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register." start="3" size="1" access="WriteOnly" />
      <BitField name="NACKCF" description="Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register." start="4" size="1" access="WriteOnly" />
      <BitField name="STOPCF" description="STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register." start="5" size="1" access="WriteOnly" />
      <BitField name="BERRCF" description="Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register." start="8" size="1" access="WriteOnly" />
      <BitField name="ARLOCF" description="Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register." start="9" size="1" access="WriteOnly" />
      <BitField name="OVRCF" description="Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register." start="10" size="1" access="WriteOnly" />
      <BitField name="PECCF" description="PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="11" size="1" access="WriteOnly" />
      <BitField name="TIMOUTCF" description="Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="12" size="1" access="WriteOnly" />
      <BitField name="ALERTCF" description="Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to ." start="13" size="1" access="WriteOnly" />
    </Register>
    <Register name="I2C_PECR" description="I2C PEC register " start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PEC" description="Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0." start="0" size="8" access="ReadOnly" />
    </Register>
    <Register name="I2C_RXDR" description="I2C receive data register " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RXDATA" description="8-bit receive data Data byte received from the I2C bus" start="0" size="8" access="ReadOnly" />
    </Register>
    <Register name="I2C_TXDR" description="I2C transmit data register " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TXDATA" description="8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE=1." start="0" size="8" access="Read/Write" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="IWDG" description="IWDG register block" start="0x40003000">
    <Register name="IWDG_KR" description="IWDG key register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="KEY" description="Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see ) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected)" start="0" size="16" access="WriteOnly" />
    </Register>
    <Register name="IWDG_PR" description="IWDG prescaler register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PR" description="Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset." start="0" size="3" access="Read/Write">
        <Enum name="B_0x0" description="divider /4" start="0x0" />
        <Enum name="B_0x1" description="divider /8" start="0x1" />
        <Enum name="B_0x2" description="divider /16" start="0x2" />
        <Enum name="B_0x3" description="divider /32" start="0x3" />
        <Enum name="B_0x4" description="divider /64" start="0x4" />
        <Enum name="B_0x5" description="divider /128" start="0x5" />
        <Enum name="B_0x6" description="divider /256" start="0x6" />
        <Enum name="B_0x7" description="divider /256" start="0x7" />
      </BitField>
    </Register>
    <Register name="IWDG_RLR" description="IWDG reload register " start="+0x8" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
      <BitField name="RL" description="Watchdog counter reload value These bits are write access protected see . They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the . The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the status register (IWDG_SR) is reset." start="0" size="12" access="Read/Write" />
    </Register>
    <Register name="IWDG_SR" description="IWDG status register " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PVU" description="Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset." start="0" size="1" access="ReadOnly" />
      <BitField name="RVU" description="Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset." start="1" size="1" access="ReadOnly" />
      <BitField name="WVU" description="Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset." start="2" size="1" access="ReadOnly" />
    </Register>
    <Register name="IWDG_WINR" description="IWDG window register " start="+0x10" size="4" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
      <BitField name="WIN" description="Watchdog counter window value These bits are write access protected, see , they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the (IWDG_SR) is reset." start="0" size="12" access="Read/Write" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="PWR" description="PWR address block description" start="0x40007000">
    <Register name="PWR_CR1" description="PWR control register 1 " start="+0x0" size="4" reset_value="0x00000208" reset_mask="0xFFFFFFFF">
      <BitField name="LPMS" description="Low-power mode selection These bits select the low-power mode entered when CPU enters deepsleep mode. 1XX: Shutdown mode" start="0" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Stop mode" start="0x0" />
        <Enum name="B_0x3" description="Standby mode" start="0x3" />
      </BitField>
      <BitField name="FPD_STOP" description="Flash memory powered down during Stop mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Flash memory idle" start="0x0" />
        <Enum name="B_0x1" description="Flash memory powered down" start="0x1" />
      </BitField>
      <BitField name="FPD_SLP" description="Flash memory powered down during Sleep mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Flash memory idle" start="0x0" />
        <Enum name="B_0x1" description="Flash memory powered down" start="0x1" />
      </BitField>
    </Register>
    <Register name="PWR_CR3" description="PWR control register 3 " start="+0x8" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
      <BitField name="EWUP1" description="Enable WKUP1 wakeup pin When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit of the PWR_CR4 register." start="0" size="1" access="Read/Write" />
      <BitField name="EWUP2" description="Enable WKUP2 wakeup pin When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit of the PWR_CR4 register." start="1" size="1" access="Read/Write" />
      <BitField name="EWUP3" description="Enable WKUP3 wakeup pin When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit of the PWR_CR4 register." start="2" size="1" access="Read/Write" />
      <BitField name="EWUP4" description="Enable WKUP4 wakeup pin When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register." start="3" size="1" access="Read/Write" />
      <BitField name="EWUP6" description="Enable WKUP6 wakeup pin When this bit is set, the WKUP6 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured through WP6 bit in the PWR_CR4 register." start="5" size="1" access="Read/Write" />
      <BitField name="APC" description="Apply pull-up and pull-down configuration This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Not applied" start="0x0" />
        <Enum name="B_0x1" description="Applied" start="0x1" />
      </BitField>
      <BitField name="EIWUL" description="Enable internal wakeup line When set, a rising edge on the internal wakeup line triggers a wakeup event." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="PWR_CR4" description="PWR control register 4 " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="WP1" description="WKUP1 wakeup pin polarity WKUP1 external wakeup signal polarity (level or edge) to generate wakeup condition:" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="High level or rising edge" start="0x0" />
        <Enum name="B_0x1" description="Low level or falling edge" start="0x1" />
      </BitField>
      <BitField name="WP2" description="WKUP2 wakeup pin polarity WKUP2 external wakeup signal polarity (level or edge) to generate wakeup condition:" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="High level or rising edge" start="0x0" />
        <Enum name="B_0x1" description="Low level or falling edge" start="0x1" />
      </BitField>
      <BitField name="WP3" description="WKUP3 wakeup pin polarity WKUP3 external wakeup signal polarity (level or edge) to generate wakeup condition:" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="High level or rising edge" start="0x0" />
        <Enum name="B_0x1" description="Low level or falling edge" start="0x1" />
      </BitField>
      <BitField name="WP4" description="WKUP4 wakeup pin polarity WKUP4 external wakeup signal polarity (level or edge) to generate wakeup condition:" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="High level or rising edge" start="0x0" />
        <Enum name="B_0x1" description="Low level or falling edge" start="0x1" />
      </BitField>
      <BitField name="WP6" description="WKUP6 wakeup pin polarity WKUP6 external wakeup signal polarity (level or edge) to generate wakeup condition:" start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="High level or rising edge" start="0x0" />
        <Enum name="B_0x1" description="Low level or falling edge" start="0x1" />
      </BitField>
    </Register>
    <Register name="PWR_SR1" description="PWR status register 1 " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="WUF1" description="Wakeup flag 1 This bit is set when a wakeup condition is detected on WKUP1 wakeup pin. It is cleared by setting the CWUF1 bit of the PWR_SCR register." start="0" size="1" access="ReadOnly" />
      <BitField name="WUF2" description="Wakeup flag 2 This bit is set when a wakeup condition is detected on WKUP2 wakeup pin. It is cleared by setting the CWUF2 bit of the PWR_SCR register." start="1" size="1" access="ReadOnly" />
      <BitField name="WUF3" description="Wakeup flag 3 This bit is set when a wakeup condition is detected on WKUP3 wakeup pin. It is cleared by setting the CWUF3 bit of the PWR_SCR register." start="2" size="1" access="ReadOnly" />
      <BitField name="WUF4" description="Wakeup flag 4 This bit is set when a wakeup condition is detected on WKUP4 wakeup pin. It is cleared by setting the CWUF4 bit of the PWR_SCR register." start="3" size="1" access="ReadOnly" />
      <BitField name="WUF6" description="Wakeup flag 6 This bit is set when a wakeup condition is detected on WKUP6 wakeup pin. It is cleared by setting the CWUF6 bit of the PWR_SCR register." start="5" size="1" access="ReadOnly" />
      <BitField name="SBF" description="Standby/Shutdown flag This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset." start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="The device did not enter Standby or Shutdown mode" start="0x0" />
        <Enum name="B_0x1" description="The device entered Standby or Shutdown mode " start="0x1" />
      </BitField>
      <BitField name="WUFI" description="Wakeup flag internal This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared." start="15" size="1" access="ReadOnly" />
    </Register>
    <Register name="PWR_SR2" description="PWR status register 2 " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="FLASH_RDY" description="Flash ready flag This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory." start="7" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Flash memory in power-down" start="0x0" />
        <Enum name="B_0x1" description="Flash memory ready to be accessed" start="0x1" />
      </BitField>
    </Register>
    <Register name="PWR_SCR" description="PWR status clear register " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CWUF1" description="Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register." start="0" size="1" access="WriteOnly" />
      <BitField name="CWUF2" description="Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register." start="1" size="1" access="WriteOnly" />
      <BitField name="CWUF3" description="Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register." start="2" size="1" access="WriteOnly" />
      <BitField name="CWUF4" description="Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register." start="3" size="1" access="WriteOnly" />
      <BitField name="CWUF6" description="Clear wakeup flag 6 Setting this bit clears the WUF6 flag in the PWR_SR1 register." start="5" size="1" access="WriteOnly" />
      <BitField name="CSBF" description="Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register." start="8" size="1" access="WriteOnly" />
    </Register>
    <Register name="PWR_PUCRA" description="PWR Port A pull-up control register " start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PU0" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="0" size="1" access="Read/Write" />
      <BitField name="PU1" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="1" size="1" access="Read/Write" />
      <BitField name="PU2" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="2" size="1" access="Read/Write" />
      <BitField name="PU3" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="3" size="1" access="Read/Write" />
      <BitField name="PU4" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="4" size="1" access="Read/Write" />
      <BitField name="PU5" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="5" size="1" access="Read/Write" />
      <BitField name="PU6" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="6" size="1" access="Read/Write" />
      <BitField name="PU7" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="7" size="1" access="Read/Write" />
      <BitField name="PU8" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="8" size="1" access="Read/Write" />
      <BitField name="PU9" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="9" size="1" access="Read/Write" />
      <BitField name="PU10" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="10" size="1" access="Read/Write" />
      <BitField name="PU11" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="11" size="1" access="Read/Write" />
      <BitField name="PU12" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="12" size="1" access="Read/Write" />
      <BitField name="PU13" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="13" size="1" access="Read/Write" />
      <BitField name="PU14" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="14" size="1" access="Read/Write" />
      <BitField name="PU15" description="Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PDCRA" description="PWR Port A pull-down control register " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PD0" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="0" size="1" access="Read/Write" />
      <BitField name="PD1" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="1" size="1" access="Read/Write" />
      <BitField name="PD2" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="2" size="1" access="Read/Write" />
      <BitField name="PD3" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="3" size="1" access="Read/Write" />
      <BitField name="PD4" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="4" size="1" access="Read/Write" />
      <BitField name="PD5" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="5" size="1" access="Read/Write" />
      <BitField name="PD6" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="6" size="1" access="Read/Write" />
      <BitField name="PD7" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="7" size="1" access="Read/Write" />
      <BitField name="PD8" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="8" size="1" access="Read/Write" />
      <BitField name="PD9" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="9" size="1" access="Read/Write" />
      <BitField name="PD10" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="10" size="1" access="Read/Write" />
      <BitField name="PD11" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="11" size="1" access="Read/Write" />
      <BitField name="PD12" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="12" size="1" access="Read/Write" />
      <BitField name="PD13" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="13" size="1" access="Read/Write" />
      <BitField name="PD14" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="14" size="1" access="Read/Write" />
      <BitField name="PD15" description="Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PUCRB" description="PWR Port B pull-up control register " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PU0" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="0" size="1" access="Read/Write" />
      <BitField name="PU1" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="1" size="1" access="Read/Write" />
      <BitField name="PU2" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="2" size="1" access="Read/Write" />
      <BitField name="PU3" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="3" size="1" access="Read/Write" />
      <BitField name="PU4" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="4" size="1" access="Read/Write" />
      <BitField name="PU5" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="5" size="1" access="Read/Write" />
      <BitField name="PU6" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="6" size="1" access="Read/Write" />
      <BitField name="PU7" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="7" size="1" access="Read/Write" />
      <BitField name="PU8" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="8" size="1" access="Read/Write" />
      <BitField name="PU9" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="9" size="1" access="Read/Write" />
      <BitField name="PU10" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="10" size="1" access="Read/Write" />
      <BitField name="PU11" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="11" size="1" access="Read/Write" />
      <BitField name="PU12" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="12" size="1" access="Read/Write" />
      <BitField name="PU13" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="13" size="1" access="Read/Write" />
      <BitField name="PU14" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="14" size="1" access="Read/Write" />
      <BitField name="PU15" description="Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available" start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PDCRB" description="PWR Port B pull-down control register " start="+0x2c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PD0" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="0" size="1" access="Read/Write" />
      <BitField name="PD1" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="1" size="1" access="Read/Write" />
      <BitField name="PD2" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="2" size="1" access="Read/Write" />
      <BitField name="PD3" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="3" size="1" access="Read/Write" />
      <BitField name="PD4" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="4" size="1" access="Read/Write" />
      <BitField name="PD5" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="5" size="1" access="Read/Write" />
      <BitField name="PD6" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="6" size="1" access="Read/Write" />
      <BitField name="PD7" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="7" size="1" access="Read/Write" />
      <BitField name="PD8" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="8" size="1" access="Read/Write" />
      <BitField name="PD9" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="9" size="1" access="Read/Write" />
      <BitField name="PD10" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="10" size="1" access="Read/Write" />
      <BitField name="PD11" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="11" size="1" access="Read/Write" />
      <BitField name="PD12" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="12" size="1" access="Read/Write" />
      <BitField name="PD13" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="13" size="1" access="Read/Write" />
      <BitField name="PD14" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="14" size="1" access="Read/Write" />
      <BitField name="PD15" description="Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available" start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PUCRC" description="PWR Port C pull-up control register " start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PU6" description="Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available" start="6" size="1" access="Read/Write" />
      <BitField name="PU7" description="Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available" start="7" size="1" access="Read/Write" />
      <BitField name="PU13" description="Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available" start="13" size="1" access="Read/Write" />
      <BitField name="PU14" description="Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available" start="14" size="1" access="Read/Write" />
      <BitField name="PU15" description="Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available" start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PDCRC" description="PWR Port C pull-down control register " start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PD6" description="Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available." start="6" size="1" access="Read/Write" />
      <BitField name="PD7" description="Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available." start="7" size="1" access="Read/Write" />
      <BitField name="PD13" description="Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available." start="13" size="1" access="Read/Write" />
      <BitField name="PD14" description="Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available." start="14" size="1" access="Read/Write" />
      <BitField name="PD15" description="Port C pull-down bit i (i = 15, 14, 13, 7, 6) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[i] I/O. On STM32C011xx, only PD15 and PD14 are available." start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PUCRD" description="PWR Port D pull-up control register " start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PU0" description="Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O." start="0" size="1" access="Read/Write" />
      <BitField name="PU1" description="Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O." start="1" size="1" access="Read/Write" />
      <BitField name="PU2" description="Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O." start="2" size="1" access="Read/Write" />
      <BitField name="PU3" description="Port D pull-up bit i (i = 3 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[i] I/O." start="3" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PDCRD" description="PWR Port D pull-down control register " start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PD0" description="Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O." start="0" size="1" access="Read/Write" />
      <BitField name="PD1" description="Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O." start="1" size="1" access="Read/Write" />
      <BitField name="PD2" description="Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O." start="2" size="1" access="Read/Write" />
      <BitField name="PD3" description="Port D pull-down bit i (i = 3 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[i] I/O." start="3" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PUCRF" description="PWR Port F pull-up control register " start="+0x48" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PU0" description="Port F pull-up bit i (i = 2 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. On STM32C011xx, only PU2 is available." start="0" size="1" access="Read/Write" />
      <BitField name="PU1" description="Port F pull-up bit i (i = 2 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. On STM32C011xx, only PU2 is available." start="1" size="1" access="Read/Write" />
      <BitField name="PU2" description="Port F pull-up bit i (i = 2 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[i] I/O. On STM32C011xx, only PU2 is available." start="2" size="1" access="Read/Write" />
    </Register>
    <Register name="PWR_PDCRF" description="PWR Port F pull-down control register " start="+0x4c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PD0" description="Port F pull-down bit i (i = 2 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. On STM32C011xx, only PD2 is available." start="0" size="1" access="Read/Write" />
      <BitField name="PD1" description="Port F pull-down bit i (i = 2 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. On STM32C011xx, only PD2 is available." start="1" size="1" access="Read/Write" />
      <BitField name="PD2" description="Port F pull-down bit i (i = 2 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[i] I/O. On STM32C011xx, only PD2 is available." start="2" size="1" access="Read/Write" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="RCC" description="RCC address block description" start="0x40021000">
    <Register name="RCC_CR" description="RCC clock control register " start="+0x0" size="4" reset_value="0x00000500" reset_mask="0xFFFFFFFF">
      <BitField name="SYSDIV" description="System clock division factor This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:" start="2" size="3" access="Read/Write">
        <Enum name="B_0x0" description="1" start="0x0" />
        <Enum name="B_0x1" description="2" start="0x1" />
        <Enum name="B_0x2" description="3 (reset value)" start="0x2" />
        <Enum name="B_0x3" description="4" start="0x3" />
        <Enum name="B_0x4" description="5" start="0x4" />
        <Enum name="B_0x5" description="6" start="0x5" />
        <Enum name="B_0x6" description="7" start="0x6" />
        <Enum name="B_0x7" description="8" start="0x7" />
      </BitField>
      <BitField name="HSIKERDIV" description="HSI48 kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:" start="5" size="3" access="Read/Write">
        <Enum name="B_0x0" description="1" start="0x0" />
        <Enum name="B_0x1" description="2" start="0x1" />
        <Enum name="B_0x2" description="3 (reset value)" start="0x2" />
        <Enum name="B_0x3" description="4" start="0x3" />
        <Enum name="B_0x4" description="5" start="0x4" />
        <Enum name="B_0x5" description="6" start="0x5" />
        <Enum name="B_0x6" description="7" start="0x6" />
        <Enum name="B_0x7" description="8" start="0x7" />
      </BitField>
      <BitField name="HSION" description="HSI48 clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="HSIKERON" description="HSI48 always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock. Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="HSI48 oscillator enable depends on the HSION bit" start="0x0" />
        <Enum name="B_0x1" description="HSI48 oscillator is active in Run and Stop modes" start="0x1" />
      </BitField>
      <BitField name="HSIRDY" description="HSI48 clock ready flag Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles." start="10" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Not ready" start="0x0" />
        <Enum name="B_0x1" description="Ready" start="0x1" />
      </BitField>
      <BitField name="HSIDIV" description="HSI48 clock division factor This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock:" start="11" size="3" access="Read/Write">
        <Enum name="B_0x0" description="1" start="0x0" />
        <Enum name="B_0x1" description="2" start="0x1" />
        <Enum name="B_0x2" description="4 (reset value)" start="0x2" />
        <Enum name="B_0x3" description="8" start="0x3" />
        <Enum name="B_0x4" description="16" start="0x4" />
        <Enum name="B_0x5" description="32" start="0x5" />
        <Enum name="B_0x6" description="64" start="0x6" />
        <Enum name="B_0x7" description="128" start="0x7" />
      </BitField>
      <BitField name="HSEON" description="HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="HSERDY" description="HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles." start="17" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Not ready" start="0x0" />
        <Enum name="B_0x1" description="Ready " start="0x1" />
      </BitField>
      <BitField name="HSEBYP" description="HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No bypass" start="0x0" />
        <Enum name="B_0x1" description="Bypass" start="0x1" />
      </BitField>
      <BitField name="CSSON" description="Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_ICSCR" description="RCC internal clock source calibration register " start="+0x4" size="4" reset_value="0x00004000" reset_mask="0xFFFFFF00">
      <BitField name="HSICAL" description="HSI48 clock calibration This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64." start="0" size="8" access="ReadOnly" />
      <BitField name="HSITRIM" description="HSI48 clock trimming The value of this bitfield contributes to the HSICAL[7:0] bitfield value. It allows HSI48 clock frequency user trimming. The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value." start="8" size="7" access="Read/Write" />
    </Register>
    <Register name="RCC_CFGR" description="RCC clock configuration register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SW" description="System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected." start="0" size="3" access="Read/Write">
        <Enum name="B_0x0" description="HSISYS" start="0x0" />
        <Enum name="B_0x1" description="HSE" start="0x1" />
        <Enum name="B_0x3" description="LSI" start="0x3" />
        <Enum name="B_0x4" description="LSE" start="0x4" />
      </BitField>
      <BitField name="SWS" description="System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved" start="3" size="3" access="ReadOnly">
        <Enum name="B_0x0" description="HSISYS" start="0x0" />
        <Enum name="B_0x1" description="HSE" start="0x1" />
        <Enum name="B_0x3" description="LSI" start="0x3" />
        <Enum name="B_0x4" description="LSE" start="0x4" />
      </BitField>
      <BitField name="HPRE" description="AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1" start="8" size="4" access="Read/Write">
        <Enum name="B_0x8" description="2" start="0x8" />
        <Enum name="B_0x9" description="4" start="0x9" />
        <Enum name="B_0xA" description="8" start="0xA" />
        <Enum name="B_0xB" description="16" start="0xB" />
        <Enum name="B_0xC" description="64" start="0xC" />
        <Enum name="B_0xD" description="128" start="0xD" />
        <Enum name="B_0xE" description="256" start="0xE" />
        <Enum name="B_0xF" description="512" start="0xF" />
      </BitField>
      <BitField name="PPRE" description="APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1" start="12" size="3" access="Read/Write">
        <Enum name="B_0x4" description="2" start="0x4" />
        <Enum name="B_0x5" description="4" start="0x5" />
        <Enum name="B_0x6" description="8" start="0x6" />
        <Enum name="B_0x7" description="16" start="0x7" />
      </BitField>
      <BitField name="MCO2SEL" description="Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching." start="16" size="4" access="Read/Write">
        <Enum name="B_0x0" description="no clock, MCO output disabled" start="0x0" />
        <Enum name="B_0x1" description="SYSCLK" start="0x1" />
        <Enum name="B_0x3" description="HSI48" start="0x3" />
        <Enum name="B_0x4" description="HSE" start="0x4" />
        <Enum name="B_0x6" description="LSI" start="0x6" />
        <Enum name="B_0x7" description="LSE" start="0x7" />
      </BitField>
      <BitField name="MCO2PRE" description="Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled." start="20" size="4" access="Read/Write">
        <Enum name="B_0x0" description="1" start="0x0" />
        <Enum name="B_0x1" description="2" start="0x1" />
        <Enum name="B_0x2" description="4" start="0x2" />
        <Enum name="B_0xF" description="128" start="0xF" />
      </BitField>
      <BitField name="MCOSEL" description="Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO." start="24" size="4" access="Read/Write">
        <Enum name="B_0x0" description="no clock, MCO output disabled" start="0x0" />
        <Enum name="B_0x1" description="SYSCLK" start="0x1" />
        <Enum name="B_0x3" description="HSI48" start="0x3" />
        <Enum name="B_0x4" description="HSE" start="0x4" />
        <Enum name="B_0x6" description="LSI" start="0x6" />
        <Enum name="B_0x7" description="LSE" start="0x7" />
      </BitField>
      <BitField name="MCOPRE" description="Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled." start="28" size="4" access="Read/Write">
        <Enum name="B_0x0" description="1" start="0x0" />
        <Enum name="B_0x1" description="2" start="0x1" />
        <Enum name="B_0x2" description="4" start="0x2" />
        <Enum name="B_0xF" description="128" start="0xF" />
      </BitField>
    </Register>
    <Register name="RCC_CIER" description="RCC clock interrupt enable register " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LSIRDYIE" description="LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="LSERDYIE" description="LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="HSIRDYIE" description="HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="HSERDYIE" description="HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:" start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_CIFR" description="RCC clock interrupt flag register " start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LSIRDYF" description="LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit." start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Interrupt not pending" start="0x0" />
        <Enum name="B_0x1" description="Interrupt pending" start="0x1" />
      </BitField>
      <BitField name="LSERDYF" description="LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit." start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Interrupt not pending" start="0x0" />
        <Enum name="B_0x1" description="Interrupt pending" start="0x1" />
      </BitField>
      <BitField name="HSIRDYF" description="HSI16 ready interrupt flag This flag indicates a pending interrupt upon HSI16 clock getting ready. Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit." start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Interrupt not pending" start="0x0" />
        <Enum name="B_0x1" description="Interrupt pending" start="0x1" />
      </BitField>
      <BitField name="HSERDYF" description="HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit." start="4" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Iterrupt not pending" start="0x0" />
        <Enum name="B_0x1" description="Interrupt pending" start="0x1" />
      </BitField>
      <BitField name="CSSF" description="HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit." start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Interrupt not pending" start="0x0" />
        <Enum name="B_0x1" description="Interrupt pending" start="0x1" />
      </BitField>
      <BitField name="LSECSSF" description="LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit." start="9" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Interrupt not pending" start="0x0" />
        <Enum name="B_0x1" description="Interrupt pending" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_CICR" description="RCC clock interrupt clear register " start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LSIRDYC" description="LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Clear LSIRDYF flag" start="0x1" />
      </BitField>
      <BitField name="LSERDYC" description="LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Clear LSERDYF flag" start="0x1" />
      </BitField>
      <BitField name="HSIRDYC" description="HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag." start="3" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Clear HSIRDYF flag" start="0x1" />
      </BitField>
      <BitField name="HSERDYC" description="HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag." start="4" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Clear HSERDYF flag" start="0x1" />
      </BitField>
      <BitField name="CSSC" description="Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Clear CSSF flag" start="0x1" />
      </BitField>
      <BitField name="LSECSSC" description="LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag." start="9" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Clear LSECSSF flag" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_IOPRSTR" description="RCC I/O port reset register " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="GPIOARST" description="I/O port A reset This bit is set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="no effect " start="0x0" />
        <Enum name="B_0x1" description="Reset I/O port A" start="0x1" />
      </BitField>
      <BitField name="GPIOBRST" description="I/O port B reset This bit is set and cleared by software." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="no effect " start="0x0" />
        <Enum name="B_0x1" description="Reset I/O port B" start="0x1" />
      </BitField>
      <BitField name="GPIOCRST" description="I/O port C reset This bit is set and cleared by software." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="no effect " start="0x0" />
        <Enum name="B_0x1" description="Reset I/O port C" start="0x1" />
      </BitField>
      <BitField name="GPIODRST" description="I/O port D reset This bit is set and cleared by software." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="no effect " start="0x0" />
        <Enum name="B_0x1" description="Reset I/O port D" start="0x1" />
      </BitField>
      <BitField name="GPIOFRST" description="I/O port F reset This bit is set and cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="no effect " start="0x0" />
        <Enum name="B_0x1" description="Reset I/O port F" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_AHBRSTR" description="RCC AHB peripheral reset register " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMA1RST" description="DMA1 and DMAMUX reset Set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset DMA1 and DMAMUX" start="0x1" />
      </BitField>
      <BitField name="FLASHRST" description="Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset Flash memory interface" start="0x1" />
      </BitField>
      <BitField name="CRCRST" description="CRC reset Set and cleared by software." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset CRC" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_APBRSTR1" description="RCC APB peripheral reset register 1 " start="+0x2c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM3RST" description="TIM3 timer reset Set and cleared by software." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset TIM3" start="0x1" />
      </BitField>
      <BitField name="USART2RST" description="USART2 reset Set and cleared by software." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset USART2" start="0x1" />
      </BitField>
      <BitField name="I2C1RST" description="I2C1 reset Set and cleared by software." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset I2C1" start="0x1" />
      </BitField>
      <BitField name="DBGRST" description="Debug support reset Set and cleared by software." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset DBG" start="0x1" />
      </BitField>
      <BitField name="PWRRST" description="Power interface reset Set and cleared by software." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset PWR" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_APBRSTR2" description="RCC APB peripheral reset register 2 " start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SYSCFGRST" description="SYSCFG reset Set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset SYSCFG" start="0x1" />
      </BitField>
      <BitField name="TIM1RST" description="TIM1 timer reset Set and cleared by software." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset TIM1 timer" start="0x1" />
      </BitField>
      <BitField name="SPI1RST" description="SPI1 reset Set and cleared by software." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset SPI1" start="0x1" />
      </BitField>
      <BitField name="USART1RST" description="USART1 reset Set and cleared by software." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset USART1" start="0x1" />
      </BitField>
      <BitField name="TIM14RST" description="TIM14 timer reset Set and cleared by software." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset TIM14 timer" start="0x1" />
      </BitField>
      <BitField name="TIM16RST" description="TIM16 timer reset Set and cleared by software." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset TIM16 timer" start="0x1" />
      </BitField>
      <BitField name="TIM17RST" description="TIM16 timer reset Set and cleared by software." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset TIM17 timer" start="0x1" />
      </BitField>
      <BitField name="ADCRST" description="ADC reset Set and cleared by software." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset ADC" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_IOPENR" description="RCC I/O port clock enable register " start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="GPIOAEN" description="I/O port A clock enable This bit is set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIOBEN" description="I/O port B clock enable This bit is set and cleared by software." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIOCEN" description="I/O port C clock enable This bit is set and cleared by software." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIODEN" description="I/O port D clock enable This bit is set and cleared by software." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIOFEN" description="I/O port F clock enable This bit is set and cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_AHBENR" description="RCC AHB peripheral clock enable register " start="+0x38" size="4" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
      <BitField name="DMA1EN" description="DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FLASHEN" description="Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="CRCEN" description="CRC clock enable Set and cleared by software." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_APBENR1" description="RCC APB peripheral clock enable register 1 " start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM3EN" description="TIM3 timer clock enable Set and cleared by software." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RTCAPBEN" description="RTC APB clock enable Set and cleared by software." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="WWDGEN" description="WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="USART2EN" description="USART2 clock enable Set and cleared by software." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C1EN" description="I2C1 clock enable Set and cleared by software." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="DBGEN" description="Debug support clock enable Set and cleared by software." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="PWREN" description="Power interface clock enable Set and cleared by software." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_APBENR2" description="RCC APB peripheral clock enable register 2" start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SYSCFGEN" description="SYSCFG clock enable Set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM1EN" description="TIM1 timer clock enable Set and cleared by software." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="SPI1EN" description="SPI1 clock enable Set and cleared by software." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="USART1EN" description="USART1 clock enable Set and cleared by software." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM14EN" description="TIM14 timer clock enable Set and cleared by software." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM16EN" description="TIM16 timer clock enable Set and cleared by software." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM17EN" description="TIM16 timer clock enable Set and cleared by software." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="ADCEN" description="ADC clock enable Set and cleared by software." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_IOPSMENR" description="RCC I/O port in Sleep mode clock enable register " start="+0x44" size="4" reset_value="0x0000003F" reset_mask="0xFFFFFFFF">
      <BitField name="GPIOASMEN" description="I/O port A clock enable during Sleep mode Set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIOBSMEN" description="I/O port B clock enable during Sleep mode Set and cleared by software." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIOCSMEN" description="I/O port C clock enable during Sleep mode Set and cleared by software." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIODSMEN" description="I/O port D clock enable during Sleep mode Set and cleared by software." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="GPIOFSMEN" description="I/O port F clock enable during Sleep mode Set and cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_AHBSMENR" description="RCC AHB peripheral clock enable in Sleep/Stop mode register&#09;" start="+0x48" size="4" reset_value="0x00051303" reset_mask="0xFFFFFFFF">
      <BitField name="DMA1SMEN" description="DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="FLASHSMEN" description="Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="SRAMSMEN" description="SRAM clock enable during Sleep mode Set and cleared by software." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="CRCSMEN" description="CRC clock enable during Sleep mode Set and cleared by software." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_APBSMENR1" description="RCC APB peripheral clock enable in Sleep/Stop mode register 1&#09;" start="+0x4c" size="4" reset_value="0x18EF7F36" reset_mask="0xFFFFFFFF">
      <BitField name="TIM3SMEN" description="TIM3 timer clock enable during Sleep mode Set and cleared by software." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RTCAPBSMEN" description="RTC APB clock enable during Sleep mode Set and cleared by software." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="WWDGSMEN" description="WWDG clock enable during Sleep and Stop modes Set and cleared by software." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="USART2SMEN" description="USART2 clock enable during Sleep and Stop modes Set and cleared by software." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C1SMEN" description="I2C1 clock enable during Sleep and Stop modes Set and cleared by software." start="21" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="DBGSMEN" description="Debug support clock enable during Sleep mode Set and cleared by software." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="PWRSMEN" description="Power interface clock enable during Sleep mode Set and cleared by software." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_APBSMENR2" description="RCC APB peripheral clock enable in Sleep/Stop mode register 2&#09;" start="+0x50" size="4" reset_value="0x0017D801" reset_mask="0xFFFFFFFF">
      <BitField name="SYSCFGSMEN" description="SYSCFG clock enable during Sleep and Stop modes Set and cleared by software." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM1SMEN" description="TIM1 timer clock enable during Sleep mode Set and cleared by software." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="SPI1SMEN" description="SPI1 clock enable during Sleep mode Set and cleared by software." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="USART1SMEN" description="USART1 clock enable during Sleep and Stop modes Set and cleared by software." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM14SMEN" description="TIM14 timer clock enable during Sleep mode Set and cleared by software." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM16SMEN" description="TIM16 timer clock enable during Sleep mode Set and cleared by software." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="TIM17SMEN" description="TIM16 timer clock enable during Sleep mode Set and cleared by software." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="ADCSMEN" description="ADC clock enable during Sleep mode Set and cleared by software." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_CCIPR" description="RCC peripherals independent clock configuration register " start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="USART1SEL" description="USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:" start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="PCLK" start="0x0" />
        <Enum name="B_0x1" description="SYSCLK" start="0x1" />
        <Enum name="B_0x2" description="HSIKER" start="0x2" />
        <Enum name="B_0x3" description="LSE" start="0x3" />
      </BitField>
      <BitField name="I2C1SEL" description="I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:" start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="PCLK " start="0x0" />
        <Enum name="B_0x1" description="SYSCLK" start="0x1" />
        <Enum name="B_0x2" description="HSIKER" start="0x2" />
      </BitField>
      <BitField name="I2S1SEL" description="I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows:" start="14" size="2" access="Read/Write">
        <Enum name="B_0x0" description="SYSCLK" start="0x0" />
        <Enum name="B_0x2" description="HSIKER" start="0x2" />
        <Enum name="B_0x3" description="I2S_CKIN" start="0x3" />
      </BitField>
      <BitField name="ADCSEL" description="ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:" start="30" size="2" access="Read/Write">
        <Enum name="B_0x0" description="System clock" start="0x0" />
        <Enum name="B_0x2" description="HSIKER" start="0x2" />
      </BitField>
    </Register>
    <Register name="RCC_CSR1" description="RCC control/status register 1 " start="+0x5c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LSEON" description="LSE oscillator enable Set and cleared by software to enable LSE oscillator:" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="LSERDY" description="LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles." start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Not ready" start="0x0" />
        <Enum name="B_0x1" description="Ready" start="0x1" />
      </BitField>
      <BitField name="LSEBYP" description="LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Not bypassed" start="0x0" />
        <Enum name="B_0x1" description="Bypassed" start="0x1" />
      </BitField>
      <BitField name="LSEDRV" description="LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode." start="3" size="2" access="Read/Write">
        <Enum name="B_0x0" description="low driving capability" start="0x0" />
        <Enum name="B_0x1" description="medium-low driving capability" start="0x1" />
        <Enum name="B_0x2" description="medium-high driving capability" start="0x2" />
        <Enum name="B_0x3" description="high driving capability " start="0x3" />
      </BitField>
      <BitField name="LSECSSON" description="CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="LSECSSD" description="CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE):" start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No failure detected" start="0x0" />
        <Enum name="B_0x1" description="Failure detected" start="0x1" />
      </BitField>
      <BitField name="RTCSEL" description="RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="No clock" start="0x0" />
        <Enum name="B_0x1" description="LSE" start="0x1" />
        <Enum name="B_0x2" description="LSI" start="0x2" />
        <Enum name="B_0x3" description="HSE divided by 32" start="0x3" />
      </BitField>
      <BitField name="RTCEN" description="RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="RTCRST" description="RTC domain software reset Set and cleared by software to reset the RTC domain:" start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Reset" start="0x1" />
      </BitField>
      <BitField name="LSCOEN" description="Low-speed clock output (LSCO) enable Set and cleared by software." start="24" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="LSCOSEL" description="Low-speed clock output selection Set and cleared by software to select the low-speed output clock:" start="25" size="1" access="Read/Write">
        <Enum name="B_0x0" description="LSI" start="0x0" />
        <Enum name="B_0x1" description="LSE" start="0x1" />
      </BitField>
    </Register>
    <Register name="RCC_CSR2" description="RCC control/status register 2 " start="+0x60" size="4" reset_value="0x00000000" reset_mask="0x00FFFFFF">
      <BitField name="LSION" description="LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="LSIRDY" description="LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC." start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Not ready" start="0x0" />
        <Enum name="B_0x1" description="Ready" start="0x1" />
      </BitField>
      <BitField name="RMVF" description="Remove reset flags Set by software to clear the reset flags." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Clear reset flags" start="0x1" />
      </BitField>
      <BitField name="OBLRSTF" description="Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit." start="25" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No reset from Option byte loading occurred" start="0x0" />
        <Enum name="B_0x1" description="Reset from Option byte loading occurred" start="0x1" />
      </BitField>
      <BitField name="PINRSTF" description="Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit." start="26" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No reset from NRST pin occurred" start="0x0" />
        <Enum name="B_0x1" description="Reset from NRST pin occurred" start="0x1" />
      </BitField>
      <BitField name="PWRRSTF" description="BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit." start="27" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No BOR or POR occurred" start="0x0" />
        <Enum name="B_0x1" description="BOR or POR occurred" start="0x1" />
      </BitField>
      <BitField name="SFTRSTF" description="Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit." start="28" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No software reset occurred" start="0x0" />
        <Enum name="B_0x1" description="Software reset occurred" start="0x1" />
      </BitField>
      <BitField name="IWDGRSTF" description="Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit." start="29" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No independent watchdog reset occurred" start="0x0" />
        <Enum name="B_0x1" description="Independent watchdog reset occurred" start="0x1" />
      </BitField>
      <BitField name="WWDGRSTF" description="Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit." start="30" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No window watchdog reset occurred" start="0x0" />
        <Enum name="B_0x1" description="Window watchdog reset occurred" start="0x1" />
      </BitField>
      <BitField name="LPWRRSTF" description="Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared." start="31" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No illegal mode reset occurred" start="0x0" />
        <Enum name="B_0x1" description="Illegal mode reset occurred" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="RTC" description="RTC register block" start="0x40002800">
    <Register name="RTC_TR" description="RTC time register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SU" description="Second units in BCD format" start="0" size="4" access="Read/Write" />
      <BitField name="ST" description="Second tens in BCD format" start="4" size="3" access="Read/Write" />
      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
        <Enum name="B_0x1" description="PM" start="0x1" />
      </BitField>
    </Register>
    <Register name="RTC_DR" description="RTC date register " start="+0x4" size="4" reset_value="0x00002101" reset_mask="0xFFFFFFFF">
      <BitField name="DU" description="Date units in BCD format" start="0" size="4" access="Read/Write" />
      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" access="Read/Write" />
      <BitField name="MU" description="Month units in BCD format" start="8" size="4" access="Read/Write" />
      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" access="Read/Write" />
      <BitField name="WDU" description="Week day units ..." start="13" size="3" access="Read/Write">
        <Enum name="B_0x0" description="forbidden" start="0x0" />
        <Enum name="B_0x1" description="Monday" start="0x1" />
        <Enum name="B_0x7" description="Sunday" start="0x7" />
      </BitField>
      <BitField name="YU" description="Year units in BCD format" start="16" size="4" access="Read/Write" />
      <BitField name="YT" description="Year tens in BCD format" start="20" size="4" access="Read/Write" />
    </Register>
    <Register name="RTC_SSR" description="RTC sub second register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SS" description="Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR." start="0" size="16" access="ReadOnly" />
    </Register>
    <Register name="RTC_ICSR" description="RTC initialization control and status register " start="+0xc" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
      <BitField name="ALRAWF" description="Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode." start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Alarm A update not allowed" start="0x0" />
        <Enum name="B_0x1" description="Alarm A update allowed" start="0x1" />
      </BitField>
      <BitField name="SHPF" description="Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect." start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No shift operation is pending" start="0x0" />
        <Enum name="B_0x1" description="A shift operation is pending" start="0x1" />
      </BitField>
      <BitField name="INITS" description="Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Power-on reset state)." start="4" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Calendar has not been initialized" start="0x0" />
        <Enum name="B_0x1" description="Calendar has been initialized" start="0x1" />
      </BitField>
      <BitField name="RSF" description="Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Calendar shadow registers not yet synchronized" start="0x0" />
        <Enum name="B_0x1" description="Calendar shadow registers synchronized" start="0x1" />
      </BitField>
      <BitField name="INITF" description="Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated." start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Calendar registers update is not allowed" start="0x0" />
        <Enum name="B_0x1" description="Calendar registers update is allowed" start="0x1" />
      </BitField>
      <BitField name="INIT" description="Initialization mode" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Free running mode" start="0x0" />
        <Enum name="B_0x1" description="Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." start="0x1" />
      </BitField>
      <BitField name="RECALPF" description="Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to ." start="16" size="1" access="ReadOnly" />
    </Register>
    <Register name="RTC_PRER" description="RTC prescaler register " start="+0x10" size="4" reset_value="0x007F00FF" reset_mask="0xFFFFFFFF">
      <BitField name="PREDIV_S" description="Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)" start="0" size="15" access="Read/Write" />
      <BitField name="PREDIV_A" description="Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)" start="16" size="7" access="Read/Write" />
    </Register>
    <Register name="RTC_CR" description="RTC control register " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TSEDGE" description="Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RTC_TS input rising edge generates a timestamp event" start="0x0" />
        <Enum name="B_0x1" description="RTC_TS input falling edge generates a timestamp event" start="0x1" />
      </BitField>
      <BitField name="REFCKON" description="RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: PREDIV_S must be 0x00FF." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RTC_REFIN detection disabled" start="0x0" />
        <Enum name="B_0x1" description="RTC_REFIN detection enabled" start="0x1" />
      </BitField>
      <BitField name="BYPSHAD" description="Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles." start="0x0" />
        <Enum name="B_0x1" description="Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters." start="0x1" />
      </BitField>
      <BitField name="FMT" description="Hour format" start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="24 hour/day format" start="0x0" />
        <Enum name="B_0x1" description="AM/PM hour format" start="0x1" />
      </BitField>
      <BitField name="ALRAE" description="Alarm A enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Alarm A disabled" start="0x0" />
        <Enum name="B_0x1" description="Alarm A enabled" start="0x1" />
      </BitField>
      <BitField name="TSE" description="timestamp enable" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="timestamp disable" start="0x0" />
        <Enum name="B_0x1" description="timestamp enable" start="0x1" />
      </BitField>
      <BitField name="ALRAIE" description="Alarm A interrupt enable" start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Alarm A interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Alarm A interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="TSIE" description="Timestamp interrupt enable" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Timestamp interrupt disable" start="0x0" />
        <Enum name="B_0x1" description="Timestamp interrupt enable" start="0x1" />
      </BitField>
      <BitField name="ADD1H" description="Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0." start="16" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Adds 1 hour to the current time. This can be used for summer time change" start="0x1" />
      </BitField>
      <BitField name="SUB1H" description="Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0." start="17" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Subtracts 1 hour to the current time. This can be used for winter time change." start="0x1" />
      </BitField>
      <BitField name="BKP" description="Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not." start="18" size="1" access="Read/Write" />
      <BitField name="COSEL" description="Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to ." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Calibration output is 512 Hz" start="0x0" />
        <Enum name="B_0x1" description="Calibration output is 1 Hz" start="0x1" />
      </BitField>
      <BitField name="POL" description="Output polarity This bit is used to configure the polarity of TAMPALRM output." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The pin is high when ALRAF is asserted (depending on OSEL[1:0])." start="0x0" />
        <Enum name="B_0x1" description="The pin is low when ALRAF is asserted (depending on OSEL[1:0])." start="0x1" />
      </BitField>
      <BitField name="OSEL" description="Output selection These bits are used to select the flag to be routed to TAMPALRM output." start="21" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Output disabled" start="0x0" />
        <Enum name="B_0x1" description="Alarm A output enabled" start="0x1" />
      </BitField>
      <BitField name="COE" description="Calibration output enable This bit enables the CALIB output" start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Calibration output disabled" start="0x0" />
        <Enum name="B_0x1" description="Calibration output enabled" start="0x1" />
      </BitField>
      <BitField name="TAMPALRM_PU" description="TAMPALRM pull-up enable" start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No pull-up is applied on TAMPALRM output" start="0x0" />
        <Enum name="B_0x1" description="A pull-up is applied on TAMPALRM output" start="0x1" />
      </BitField>
      <BitField name="TAMPALRM_TYPE" description="TAMPALRM output type" start="30" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TAMPALRM is push-pull output" start="0x0" />
        <Enum name="B_0x1" description="TAMPALRM is open-drain output" start="0x1" />
      </BitField>
      <BitField name="OUT2EN" description="RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL ≠ 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1." start="31" size="1" access="Read/Write" />
    </Register>
    <Register name="RTC_WPR" description="RTC write protection register " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="KEY" description="Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection." start="0" size="8" access="WriteOnly" />
    </Register>
    <Register name="RTC_CALR" description="RTC calibration register " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CALM" description="Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See ." start="0" size="9" access="Read/Write" />
      <BitField name="CALW16" description="Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration." start="13" size="1" access="Read/Write" />
      <BitField name="CALW8" description="Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration." start="14" size="1" access="Read/Write" />
      <BitField name="CALP" description="Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 � CALP) - CALM. Refer to ." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No RTCCLK pulses are added." start="0x0" />
        <Enum name="B_0x1" description="One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5 ppm)." start="0x1" />
      </BitField>
    </Register>
    <Register name="RTC_SHIFTR" description="RTC shift control register " start="+0x2c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SUBFS" description="Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time." start="0" size="15" access="WriteOnly" />
      <BitField name="ADD1S" description="Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation." start="31" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No effect" start="0x0" />
        <Enum name="B_0x1" description="Add one second to the clock/calendar" start="0x1" />
      </BitField>
    </Register>
    <Register name="RTC_TSTR" description="RTC timestamp time register " start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SU" description="Second units in BCD format." start="0" size="4" access="ReadOnly" />
      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" access="ReadOnly" />
      <BitField name="MNU" description="Minute units in BCD format." start="8" size="4" access="ReadOnly" />
      <BitField name="MNT" description="Minute tens in BCD format." start="12" size="3" access="ReadOnly" />
      <BitField name="HU" description="Hour units in BCD format." start="16" size="4" access="ReadOnly" />
      <BitField name="HT" description="Hour tens in BCD format." start="20" size="2" access="ReadOnly" />
      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
        <Enum name="B_0x1" description="PM" start="0x1" />
      </BitField>
    </Register>
    <Register name="RTC_TSDR" description="RTC timestamp date register " start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DU" description="Date units in BCD format" start="0" size="4" access="ReadOnly" />
      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" access="ReadOnly" />
      <BitField name="MU" description="Month units in BCD format" start="8" size="4" access="ReadOnly" />
      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" access="ReadOnly" />
      <BitField name="WDU" description="Week day units" start="13" size="3" access="ReadOnly" />
    </Register>
    <Register name="RTC_TSSSR" description="RTC timestamp sub second register " start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SS" description="Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred." start="0" size="16" access="ReadOnly" />
    </Register>
    <Register name="RTC_ALRMAR" description="RTC alarm A register " start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SU" description="Second units in BCD format." start="0" size="4" access="Read/Write" />
      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" access="Read/Write" />
      <BitField name="MSK1" description="Alarm A seconds mask" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Alarm A set if the seconds match" start="0x0" />
        <Enum name="B_0x1" description="Seconds don’t care in alarm A comparison" start="0x1" />
      </BitField>
      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" access="Read/Write" />
      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" access="Read/Write" />
      <BitField name="MSK2" description="Alarm A minutes mask" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Alarm A set if the minutes match" start="0x0" />
        <Enum name="B_0x1" description="Minutes don’t care in alarm A comparison" start="0x1" />
      </BitField>
      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" access="Read/Write" />
      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" access="Read/Write" />
      <BitField name="PM" description="AM/PM notation" start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="AM or 24-hour format" start="0x0" />
        <Enum name="B_0x1" description="PM" start="0x1" />
      </BitField>
      <BitField name="MSK3" description="Alarm A hours mask" start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Alarm A set if the hours match" start="0x0" />
        <Enum name="B_0x1" description="Hours don’t care in alarm A comparison" start="0x1" />
      </BitField>
      <BitField name="DU" description="Date units or day in BCD format" start="24" size="4" access="Read/Write" />
      <BitField name="DT" description="Date tens in BCD format" start="28" size="2" access="Read/Write" />
      <BitField name="WDSEL" description="Week day selection" start="30" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DU[3:0] represents the date units" start="0x0" />
        <Enum name="B_0x1" description="DU[3:0] represents the week day. DT[1:0] is don’t care." start="0x1" />
      </BitField>
      <BitField name="MSK4" description="Alarm A date mask" start="31" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Alarm A set if the date/day match" start="0x0" />
        <Enum name="B_0x1" description="Date/day don’t care in alarm A comparison" start="0x1" />
      </BitField>
    </Register>
    <Register name="RTC_ALRMASSR" description="RTC alarm A sub second register " start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SS" description="Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared." start="0" size="15" access="Read/Write" />
      <BitField name="MASKSS" description="Mask the most-significant bits starting at this bit 2:&#09;SS[14:2] are don’t care in alarm A comparison. Only SS[1:0] are compared. 3:&#09;SS[14:3] are don’t care in alarm A comparison. Only SS[2:0] are compared. ... 12:&#09;SS[14:12] are don’t care in alarm A comparison. SS[11:0] are compared. 13:&#09;SS[14:13] are don’t care in alarm A comparison. SS[12:0] are compared. 14:&#09;SS[14] is don’t care in alarm A comparison. SS[13:0] are compared. 15:&#09;All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation." start="24" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match)." start="0x0" />
        <Enum name="B_0x1" description="SS[14:1] are don’t care in alarm A comparison. Only SS[0] is compared." start="0x1" />
      </BitField>
    </Register>
    <Register name="RTC_SR" description="RTC status register " start="+0x50" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ALRAF" description="Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR)." start="0" size="1" access="ReadOnly" />
      <BitField name="TSF" description="Timestamp flag This flag is set by hardware when a timestamp event occurs." start="3" size="1" access="ReadOnly" />
      <BitField name="TSOVF" description="Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared." start="4" size="1" access="ReadOnly" />
    </Register>
    <Register name="RTC_MISR" description="RTC masked interrupt status register " start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ALRAMF" description="Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs." start="0" size="1" access="ReadOnly" />
      <BitField name="TSMF" description="Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs." start="3" size="1" access="ReadOnly" />
      <BitField name="TSOVMF" description="Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared." start="4" size="1" access="ReadOnly" />
    </Register>
    <Register name="RTC_SCR" description="RTC status clear register " start="+0x5c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CALRAF" description="Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register." start="0" size="1" access="WriteOnly" />
      <BitField name="CTSF" description="Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register." start="3" size="1" access="WriteOnly" />
      <BitField name="CTSOVF" description="Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared." start="4" size="1" access="WriteOnly" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="SPI" description="Serial peripheral interface" start="0x40013000">
    <Register name="SPI_CR1" description="SPI control register 1 " start="+0x0" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CPHA" description="Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
      </BitField>
      <BitField name="CPOL" description="Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CK to 0 when idle" start="0x0" />
        <Enum name="B_0x1" description="CK to 1 when idle" start="0x1" />
      </BitField>
      <BitField name="MSTR" description="Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Slave configuration" start="0x0" />
        <Enum name="B_0x1" description="Master configuration" start="0x1" />
      </BitField>
      <BitField name="BR" description="Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode." start="3" size="3" access="Read/Write">
        <Enum name="B_0x0" description="fPCLK/2" start="0x0" />
        <Enum name="B_0x1" description="fPCLK/4" start="0x1" />
        <Enum name="B_0x2" description="fPCLK/8" start="0x2" />
        <Enum name="B_0x3" description="fPCLK/16" start="0x3" />
        <Enum name="B_0x4" description="fPCLK/32" start="0x4" />
        <Enum name="B_0x5" description="fPCLK/64" start="0x5" />
        <Enum name="B_0x6" description="fPCLK/128" start="0x6" />
        <Enum name="B_0x7" description="fPCLK/256" start="0x7" />
      </BitField>
      <BitField name="SPE" description="SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page 1349. This bit is not used in I2S mode." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Peripheral disabled" start="0x0" />
        <Enum name="B_0x1" description="Peripheral enabled" start="0x1" />
      </BitField>
      <BitField name="LSBFIRST" description="Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="data is transmitted / received with the MSB first" start="0x0" />
        <Enum name="B_0x1" description="data is transmitted / received with the LSB first" start="0x1" />
      </BitField>
      <BitField name="SSI" description="Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode." start="8" size="1" access="Read/Write" />
      <BitField name="SSM" description="Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Software slave management disabled" start="0x0" />
        <Enum name="B_0x1" description="Software slave management enabled" start="0x1" />
      </BitField>
      <BitField name="RXONLY" description="Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Full-duplex (Transmit and receive)" start="0x0" />
        <Enum name="B_0x1" description="Output disabled (Receive-only mode)" start="0x1" />
      </BitField>
      <BitField name="CRCL" description="CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="8-bit CRC length" start="0x0" />
        <Enum name="B_0x1" description="16-bit CRC length" start="0x1" />
      </BitField>
      <BitField name="CRCNEXT" description="Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Next transmit value is from Tx buffer." start="0x0" />
        <Enum name="B_0x1" description="Next transmit value is from Tx CRC register." start="0x1" />
      </BitField>
      <BitField name="CRCEN" description="Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CRC calculation disabled" start="0x0" />
        <Enum name="B_0x1" description="CRC calculation enabled" start="0x1" />
      </BitField>
      <BitField name="BIDIOE" description="Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output disabled (receive-only mode) " start="0x0" />
        <Enum name="B_0x1" description="Output enabled (transmit-only mode)" start="0x1" />
      </BitField>
      <BitField name="BIDIMODE" description="Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="2-line unidirectional data mode selected" start="0x0" />
        <Enum name="B_0x1" description="1-line bidirectional data mode selected" start="0x1" />
      </BitField>
    </Register>
    <Register name="SPI_CR2" description="SPI control register 2 " start="+0x4" size="2" reset_value="0x00000700" reset_mask="0x0000FFFF">
      <BitField name="RXDMAEN" description="Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Rx buffer DMA disabled" start="0x0" />
        <Enum name="B_0x1" description="Rx buffer DMA enabled" start="0x1" />
      </BitField>
      <BitField name="TXDMAEN" description="Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Tx buffer DMA disabled" start="0x0" />
        <Enum name="B_0x1" description="Tx buffer DMA enabled" start="0x1" />
      </BitField>
      <BitField name="SSOE" description="SS output enable Note: This bit is not used in I2S mode and SPI TI mode." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="SS output is disabled in master mode and the SPI interface can work in multimaster configuration" start="0x0" />
        <Enum name="B_0x1" description="SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment." start="0x1" />
      </BitField>
      <BitField name="NSSP" description="NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No NSS pulse" start="0x0" />
        <Enum name="B_0x1" description="NSS pulse generated" start="0x1" />
      </BitField>
      <BitField name="FRF" description="Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="SPI Motorola mode" start="0x0" />
      </BitField>
      <BitField name="ERRIE" description="Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode)." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Error interrupt is masked" start="0x0" />
        <Enum name="B_0x1" description="Error interrupt is enabled" start="0x1" />
      </BitField>
      <BitField name="RXNEIE" description="RX buffer not empty interrupt enable" start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RXNE interrupt masked " start="0x0" />
        <Enum name="B_0x1" description="RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set." start="0x1" />
      </BitField>
      <BitField name="TXEIE" description="Tx buffer empty interrupt enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TXE interrupt masked " start="0x0" />
        <Enum name="B_0x1" description="TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set." start="0x1" />
      </BitField>
      <BitField name="DS" description="Data size These bits configure the data length for SPI transfers. If software attempts to write one of the “Not used” values, they are forced to the value “0111” (8-bit) Note: These bits are not used in I2S mode." start="8" size="4" access="Read/Write">
        <Enum name="B_0x0" description="Not used" start="0x0" />
        <Enum name="B_0x1" description="Not used" start="0x1" />
        <Enum name="B_0x2" description="Not used" start="0x2" />
        <Enum name="B_0x3" description="4-bit" start="0x3" />
        <Enum name="B_0x4" description="5-bit" start="0x4" />
        <Enum name="B_0x5" description="6-bit" start="0x5" />
        <Enum name="B_0x6" description="7-bit" start="0x6" />
        <Enum name="B_0x7" description="8-bit" start="0x7" />
        <Enum name="B_0x8" description="9-bit" start="0x8" />
        <Enum name="B_0x9" description="10-bit" start="0x9" />
        <Enum name="B_0xA" description="11-bit" start="0xA" />
        <Enum name="B_0xB" description="12-bit" start="0xB" />
        <Enum name="B_0xC" description="13-bit" start="0xC" />
        <Enum name="B_0xD" description="14-bit" start="0xD" />
        <Enum name="B_0xE" description="15-bit" start="0xE" />
        <Enum name="B_0xF" description="16-bit" start="0xF" />
      </BitField>
      <BitField name="FRXTH" description="FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)" start="0x0" />
        <Enum name="B_0x1" description="RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)" start="0x1" />
      </BitField>
      <BitField name="LDMA_RX" description="Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =&lt; 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I�S mode." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Number of data to transfer is even" start="0x0" />
        <Enum name="B_0x1" description="Number of data to transfer is odd" start="0x1" />
      </BitField>
      <BitField name="LDMA_TX" description="Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =&lt; 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I�S mode." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Number of data to transfer is even" start="0x0" />
        <Enum name="B_0x1" description="Number of data to transfer is odd" start="0x1" />
      </BitField>
    </Register>
    <Register name="SPI_SR" description="SPI status register " start="+0x8" size="2" reset_value="0x00000002" reset_mask="0x0000FFFF">
      <BitField name="RXNE" description="Receive buffer not empty" start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Rx buffer empty" start="0x0" />
        <Enum name="B_0x1" description="Rx buffer not empty" start="0x1" />
      </BitField>
      <BitField name="TXE" description="Transmit buffer empty" start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Tx buffer not empty" start="0x0" />
        <Enum name="B_0x1" description="Tx buffer empty" start="0x1" />
      </BitField>
      <BitField name="CHSIDE" description="Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode." start="2" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Channel Left has to be transmitted or has been received" start="0x0" />
        <Enum name="B_0x1" description="Channel Right has to be transmitted or has been received" start="0x1" />
      </BitField>
      <BitField name="UDR" description="Underrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence. Note: This bit is not used in SPI mode." start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No underrun occurred" start="0x0" />
        <Enum name="B_0x1" description="Underrun occurred" start="0x1" />
      </BitField>
      <BitField name="CRCERR" description="CRC error flag Note: This flag is set by hardware and cleared by software writing 0. This bit is not used in I2S mode." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CRC value received matches the SPI_RXCRCR value" start="0x0" />
        <Enum name="B_0x1" description="CRC value received does not match the SPI_RXCRCR value" start="0x1" />
      </BitField>
      <BitField name="MODF" description="Mode fault This flag is set by hardware and reset by a software sequence. Refer to (MODF) on page 1359 for the software sequence. Note: This bit is not used in I2S mode." start="5" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No mode fault occurred" start="0x0" />
        <Enum name="B_0x1" description="Mode fault occurred" start="0x1" />
      </BitField>
      <BitField name="OVR" description="Overrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence." start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No overrun occurred" start="0x0" />
        <Enum name="B_0x1" description="Overrun occurred" start="0x1" />
      </BitField>
      <BitField name="BSY" description="Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to and ." start="7" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="SPI (or I2S) not busy" start="0x0" />
        <Enum name="B_0x1" description="SPI (or I2S) is busy in communication or Tx buffer is not empty" start="0x1" />
      </BitField>
      <BitField name="FRE" description="Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to error flags and . This flag is set by hardware and reset when SPI_SR is read by software." start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No frame format error" start="0x0" />
        <Enum name="B_0x1" description="A frame format error occurred" start="0x1" />
      </BitField>
      <BitField name="FRLVL" description="FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in I�S mode and in SPI receive-only mode while CRC calculation is enabled." start="9" size="2" access="ReadOnly">
        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
        <Enum name="B_0x1" description="1/4 FIFO" start="0x1" />
        <Enum name="B_0x2" description="1/2 FIFO" start="0x2" />
        <Enum name="B_0x3" description="FIFO full" start="0x3" />
      </BitField>
      <BitField name="FTLVL" description="FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode." start="11" size="2" access="ReadOnly">
        <Enum name="B_0x0" description="FIFO empty" start="0x0" />
        <Enum name="B_0x1" description="1/4 FIFO" start="0x1" />
        <Enum name="B_0x2" description="1/2 FIFO" start="0x2" />
        <Enum name="B_0x3" description="FIFO full (considered as FULL when the FIFO threshold is greater than 1/2)" start="0x3" />
      </BitField>
    </Register>
    <Register name="SPI_DR" description="SPI data register " start="+0xc" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DR" description="Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="SPI_CRCPR" description="SPI CRC polynomial register " start="+0x10" size="2" reset_value="0x00000007" reset_mask="0x0000FFFF">
      <BitField name="CRCPOLY" description="CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="SPI_RXCRCR" description="SPI Rx CRC register " start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="RXCRC" description="Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode." start="0" size="16" access="ReadOnly" />
    </Register>
    <Register name="SPI_TXCRCR" description="SPI Tx CRC register " start="+0x18" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="TXCRC" description="Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode." start="0" size="16" access="ReadOnly" />
    </Register>
    <Register name="SPI_I2SCFGR" description="SPI_I2S configuration register " start="+0x1c" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CHLEN" description="Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="16-bit wide" start="0x0" />
        <Enum name="B_0x1" description="32-bit wide" start="0x1" />
      </BitField>
      <BitField name="DATLEN" description="Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode." start="1" size="2" access="Read/Write">
        <Enum name="B_0x0" description="16-bit data length" start="0x0" />
        <Enum name="B_0x1" description="24-bit data length" start="0x1" />
        <Enum name="B_0x2" description="32-bit data length" start="0x2" />
        <Enum name="B_0x3" description="Not allowed" start="0x3" />
      </BitField>
      <BitField name="CKPOL" description="Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="I2S clock inactive state is low level" start="0x0" />
        <Enum name="B_0x1" description="I2S clock inactive state is high level" start="0x1" />
      </BitField>
      <BitField name="I2SSTD" description="I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode." start="4" size="2" access="Read/Write">
        <Enum name="B_0x0" description="I2S Philips standard" start="0x0" />
        <Enum name="B_0x1" description="MSB justified standard (left justified)" start="0x1" />
        <Enum name="B_0x2" description="LSB justified standard (right justified)" start="0x2" />
        <Enum name="B_0x3" description="PCM standard" start="0x3" />
      </BitField>
      <BitField name="PCMSYNC" description="PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Short frame synchronization" start="0x0" />
        <Enum name="B_0x1" description="Long frame synchronization" start="0x1" />
      </BitField>
      <BitField name="I2SCFG" description="I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Slave - transmit" start="0x0" />
        <Enum name="B_0x1" description="Slave - receive" start="0x1" />
        <Enum name="B_0x2" description="Master - transmit" start="0x2" />
        <Enum name="B_0x3" description="Master - receive" start="0x3" />
      </BitField>
      <BitField name="I2SE" description="I2S enable Note: This bit is not used in SPI mode." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="I2S peripheral is disabled" start="0x0" />
        <Enum name="B_0x1" description="I2S peripheral is enabled" start="0x1" />
      </BitField>
      <BitField name="I2SMOD" description="I2S mode selection Note: This bit should be configured when the SPI is disabled." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="SPI mode is selected" start="0x0" />
        <Enum name="B_0x1" description="I2S mode is selected" start="0x1" />
      </BitField>
      <BitField name="ASTRTEN" description="Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The Asynchronous start is disabled. " start="0x0" />
        <Enum name="B_0x1" description="The Asynchronous start is enabled. " start="0x1" />
      </BitField>
    </Register>
    <Register name="SPI_I2SPR" description="SPI_I2S prescaler register " start="+0x20" size="2" reset_value="0x00000002" reset_mask="0x0000FFFF">
      <BitField name="I2SDIV" description="I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to . Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. They are not used in SPI mode." start="0" size="8" access="Read/Write" />
      <BitField name="ODD" description="Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Real divider value is = I2SDIV *2" start="0x0" />
        <Enum name="B_0x1" description="Real divider value is = (I2SDIV * 2) + 1" start="0x1" />
      </BitField>
      <BitField name="MCKOE" description="Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Master clock output is disabled" start="0x0" />
        <Enum name="B_0x1" description="Master clock output is enabled" start="0x1" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="SYSCFG" description="SYSCFG register block" start="0x40010000">
    <Register name="SYSCFG_CFGR1" description="SYSCFG configuration register 1 " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFF0">
      <BitField name="MEM_MODE" description="Memory mapping selection bits This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to for more details. x0: Main Flash memory" start="0" size="2" access="Read/Write">
        <Enum name="B_0x1" description="System Flash memory" start="0x1" />
        <Enum name="B_0x3" description="Embedded SRAM" start="0x3" />
      </BitField>
      <BitField name="PA11_RMP" description="PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No remap (PA11)" start="0x0" />
        <Enum name="B_0x1" description="Remap (PA9)" start="0x1" />
      </BitField>
      <BitField name="PA12_RMP" description="PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No remap (PA12)" start="0x0" />
        <Enum name="B_0x1" description="Remap (PA10)" start="0x1" />
      </BitField>
      <BitField name="IR_POL" description="IR output polarity selection" start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Output of IRTIM (IR_OUT) is not inverted" start="0x0" />
        <Enum name="B_0x1" description="Output of IRTIM (IR_OUT) is inverted" start="0x1" />
      </BitField>
      <BitField name="IR_MOD" description="IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:" start="6" size="2" access="Read/Write">
        <Enum name="B_0x0" description="TIM16" start="0x0" />
        <Enum name="B_0x1" description="USART1" start="0x1" />
        <Enum name="B_0x2" description="USART2" start="0x2" />
      </BitField>
      <BitField name="I2C_PB6_FMP" description="Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C_PB7_FMP" description="Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C_PB8_FMP" description="Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C_PB9_FMP" description="Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C1_FMP" description="Fast Mode Plus (FM+) enable for I2C1 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C_PA9_FMP" description="Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C_PA10_FMP" description="Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
      <BitField name="I2C_PC14_FMP" description="Fast Mode Plus (FM+) enable for PC14 This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored." start="24" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="SYSCFG_CFGR2" description="SYSCFG configuration register 2 " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="LOCKUP_LOCK" description="Cortex&lt;Superscript&gt;�&lt;Default � Font&gt;-M0+ LOCKUP enable This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex&lt;Superscript&gt;�&lt;Default � Font&gt;-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Disable" start="0x0" />
        <Enum name="B_0x1" description="Enable" start="0x1" />
      </BitField>
    </Register>
    <Register name="SYSCFG_CFGR3" description="SYSCFG configuration register 3 " start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PINMUX0" description="Pin GPIO multiplexer 0 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Pin F2 of WLCSP14 package GPIO assignment 1x: Reserved" start="0" size="2" access="Read/Write">
        <Enum name="B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1" description="PB7" start="0x0" />
        <Enum name="B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1" description="PC14" start="0x1" />
        <Enum name="B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2" description="PA1" start="0x0" />
        <Enum name="B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2" description="PA2" start="0x1" />
      </BitField>
      <BitField name="PINMUX1" description="Pin GPIO multiplexer 1 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved" start="2" size="2" access="Read/Write">
        <Enum name="B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4" description="PF2" start="0x0" />
        <Enum name="B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4" description="PA0" start="0x1" />
        <Enum name="B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4" description="PA1" start="0x2" />
        <Enum name="B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4" description="PA2" start="0x3" />
        <Enum name="B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3" description="PF2" start="0x0" />
        <Enum name="B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3" description="PA0" start="0x1" />
      </BitField>
      <BitField name="PINMUX2" description="Pin GPIO multiplexer 2 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved" start="4" size="2" access="Read/Write">
        <Enum name="B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5" description="PA8" start="0x0" />
        <Enum name="B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5" description="PA11" start="0x1" />
        <Enum name="B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1" description="PA8" start="0x0" />
        <Enum name="B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1" description="PA11" start="0x1" />
      </BitField>
      <BitField name="PINMUX3" description="Pin GPIO multiplexer 3 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved" start="6" size="2" access="Read/Write">
        <Enum name="B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8" description="PA14" start="0x0" />
        <Enum name="B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8" description="PB6" start="0x1" />
        <Enum name="B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8" description="PC15" start="0x2" />
        <Enum name="B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2" description="PA5" start="0x0" />
        <Enum name="B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2" description="PA6" start="0x1" />
      </BitField>
      <BitField name="PINMUX4" description="Pin GPIO multiplexer 4 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved" start="8" size="2" access="Read/Write">
        <Enum name="B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2" description="PA7" start="0x0" />
        <Enum name="B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2" description="PA12" start="0x1" />
        <Enum name="B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1" description="PA7" start="0x0" />
        <Enum name="B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1" description="PA12" start="0x1" />
      </BitField>
      <BitField name="PINMUX5" description="Pin GPIO multiplexer 5 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved" start="10" size="2" access="Read/Write">
        <Enum name="B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1" description="PA3" start="0x0" />
        <Enum name="B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1" description="PA4" start="0x1" />
        <Enum name="B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1" description="PA5" start="0x2" />
        <Enum name="B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1" description="PA6" start="0x3" />
        <Enum name="B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3" description="PA3" start="0x0" />
        <Enum name="B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3" description="PA4" start="0x1" />
      </BitField>
    </Register>
    <Register name="SYSCFG_ITLINE0" description="SYSCFG interrupt line 0 status register " start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="WWDG" description="Window watchdog interrupt pending flag" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE2" description="SYSCFG interrupt line 2 status register " start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RTC" description="RTC interrupt request pending (EXTI line 19)" start="1" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE3" description="SYSCFG interrupt line 3 status register " start="+0x8c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="FLASH_ITF" description="Flash interface interrupt request pending" start="1" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE4" description="SYSCFG interrupt line 4 status register " start="+0x90" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RCC" description="Reset and clock control interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE5" description="SYSCFG interrupt line 5 status register " start="+0x94" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EXTI0" description="EXTI line 0 interrupt request pending" start="0" size="1" access="ReadOnly" />
      <BitField name="EXTI1" description="EXTI line 1 interrupt request pending" start="1" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE6" description="SYSCFG interrupt line 6 status register " start="+0x98" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EXTI2" description="EXTI line 2 interrupt request pending" start="0" size="1" access="ReadOnly" />
      <BitField name="EXTI3" description="EXTI line 3 interrupt request pending" start="1" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE7" description="SYSCFG interrupt line 7 status register " start="+0x9c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EXTI4" description="EXTI line 4 interrupt request pending" start="0" size="1" access="ReadOnly" />
      <BitField name="EXTI5" description="EXTI line 5 interrupt request pending" start="1" size="1" access="ReadOnly" />
      <BitField name="EXTI6" description="EXTI line 6 interrupt request pending" start="2" size="1" access="ReadOnly" />
      <BitField name="EXTI7" description="EXTI line 7 interrupt request pending" start="3" size="1" access="ReadOnly" />
      <BitField name="EXTI8" description="EXTI line 8 interrupt request pending" start="4" size="1" access="ReadOnly" />
      <BitField name="EXTI9" description="EXTI line 9 interrupt request pending" start="5" size="1" access="ReadOnly" />
      <BitField name="EXTI10" description="EXTI line 10 interrupt request pending" start="6" size="1" access="ReadOnly" />
      <BitField name="EXTI11" description="EXTI line 11 interrupt request pending" start="7" size="1" access="ReadOnly" />
      <BitField name="EXTI12" description="EXTI line 12 interrupt request pending" start="8" size="1" access="ReadOnly" />
      <BitField name="EXTI13" description="EXTI line 13 interrupt request pending" start="9" size="1" access="ReadOnly" />
      <BitField name="EXTI14" description="EXTI line 14 interrupt request pending" start="10" size="1" access="ReadOnly" />
      <BitField name="EXTI15" description="EXTI line 15 interrupt request pending" start="11" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE9" description="SYSCFG interrupt line 9 status register " start="+0xa4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMA1_CH1" description="DMA1 channel 1interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE10" description="SYSCFG interrupt line 10 status register " start="+0xa8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMA1_CH2" description="DMA1 channel 2 interrupt request pending" start="0" size="1" access="ReadOnly" />
      <BitField name="DMA1_CH3" description="DMA1 channel 3 interrupt request pending" start="1" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE11" description="SYSCFG interrupt line 11 status register " start="+0xac" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMAMUX" description="DMAMUX interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE12" description="SYSCFG interrupt line 12 status register " start="+0xb0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ADC" description="ADC interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE13" description="SYSCFG interrupt line 13 status register " start="+0xb4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM1_CCU" description="Timer 1 commutation interrupt request pending" start="0" size="1" access="ReadOnly" />
      <BitField name="TIM1_TRG" description="Timer 1 trigger interrupt request pending" start="1" size="1" access="ReadOnly" />
      <BitField name="TIM1_UPD" description="Timer 1 update interrupt request pending" start="2" size="1" access="ReadOnly" />
      <BitField name="TIM1_BRK" description="Timer 1 break interrupt request pending" start="3" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE14" description="SYSCFG interrupt line 14 status register " start="+0xb8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM1_CC" description="Timer 1 capture compare interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE16" description="SYSCFG interrupt line 16 status register " start="+0xc0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM3" description="Timer 3 interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE19" description="SYSCFG interrupt line 19 status register " start="+0xcc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM14" description="Timer 14 interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE21" description="SYSCFG interrupt line 21 status register " start="+0xd4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM16" description="Timer 16 interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE22" description="SYSCFG interrupt line 22 status register " start="+0xd8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TIM17" description="Timer 17 interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE23" description="SYSCFG interrupt line 23 status register " start="+0xdc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="I2C1" description="I2C1 interrupt request pending, combined with EXTI line 23" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE25" description="SYSCFG interrupt line 25 status register " start="+0xe4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SPI1" description="SPI1 interrupt request pending" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE27" description="SYSCFG interrupt line 27 status register " start="+0xec" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="USART1" description="USART1 interrupt request pending, combined with EXTI line 25" start="0" size="1" access="ReadOnly" />
    </Register>
    <Register name="SYSCFG_ITLINE28" description="SYSCFG interrupt line 28 status register " start="+0xf0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="USART2" description="USART2 interrupt request pending (EXTI line 26)" start="0" size="1" access="ReadOnly" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="TIM1" description="Advanced-control timer" start="0x40012C00">
    <Register name="TIM1_CR1" description="TIM1 control register 1 " start="+0x0" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CEN" description="Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
      </BitField>
      <BitField name="UDIS" description="Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
      </BitField>
      <BitField name="URS" description="Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be: " start="0x0" />
        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
      </BitField>
      <BitField name="OPM" description="One pulse mode" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
      </BitField>
      <BitField name="DIR" description="Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
      </BitField>
      <BitField name="CMS" description="Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed" start="5" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
      </BitField>
      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
      </BitField>
      <BitField name="CKD" description="Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="tDTS=tCK_INT" start="0x0" />
        <Enum name="B_0x1" description="tDTS=2*tCK_INT" start="0x1" />
        <Enum name="B_0x2" description="tDTS=4*tCK_INT" start="0x2" />
        <Enum name="B_0x3" description="Reserved, do not program this value" start="0x3" />
      </BitField>
      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM1_CR2" description="TIM1 control register 2 " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CCPC" description="Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit)." start="0x1" />
      </BitField>
      <BitField name="CCUS" description="Capture/compare control update selection Note: This bit acts only on channels that have a complementary output." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only" start="0x0" />
        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI" start="0x1" />
      </BitField>
      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
      </BitField>
      <BitField name="MMS" description="Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset." start="0x0" />
        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)." start="0x3" />
        <Enum name="B_0x4" description="Compare - OC1REFC signal is used as trigger output (TRGO)" start="0x4" />
        <Enum name="B_0x5" description="Compare - OC2REFC signal is used as trigger output (TRGO)" start="0x5" />
        <Enum name="B_0x6" description="Compare - OC3REFC signal is used as trigger output (TRGO)" start="0x6" />
        <Enum name="B_0x7" description="Compare - OC4REFC signal is used as trigger output (TRGO)" start="0x7" />
      </BitField>
      <BitField name="TI1S" description="TI1 selection" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The TIMx_CH1 pin is connected to TI1 input" start="0x0" />
        <Enum name="B_0x1" description="The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)" start="0x1" />
      </BitField>
      <BitField name="OIS1" description="Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1=0 (after a dead-time if OC1N is implemented) when MOE=0" start="0x0" />
        <Enum name="B_0x1" description="OC1=1 (after a dead-time if OC1N is implemented) when MOE=0" start="0x1" />
      </BitField>
      <BitField name="OIS1N" description="Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1N=0 after a dead-time when MOE=0" start="0x0" />
        <Enum name="B_0x1" description="OC1N=1 after a dead-time when MOE=0" start="0x1" />
      </BitField>
      <BitField name="OIS2" description="Output Idle state 2 (OC2 output) Refer to OIS1 bit" start="10" size="1" access="Read/Write" />
      <BitField name="OIS2N" description="Output Idle state 2 (OC2N output) Refer to OIS1N bit" start="11" size="1" access="Read/Write" />
      <BitField name="OIS3" description="Output Idle state 3 (OC3 output) Refer to OIS1 bit" start="12" size="1" access="Read/Write" />
      <BitField name="OIS3N" description="Output Idle state 3 (OC3N output) Refer to OIS1N bit" start="13" size="1" access="Read/Write" />
      <BitField name="OIS4" description="Output Idle state 4 (OC4 output) Refer to OIS1 bit" start="14" size="1" access="Read/Write" />
      <BitField name="OIS5" description="Output Idle state 5 (OC5 output) Refer to OIS1 bit" start="16" size="1" access="Read/Write" />
      <BitField name="OIS6" description="Output Idle state 6 (OC6 output) Refer to OIS1 bit" start="18" size="1" access="Read/Write" />
      <BitField name="MMS2" description="Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer." start="20" size="4" access="Read/Write">
        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset." start="0x0" />
        <Enum name="B_0x1" description="Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)." start="0x1" />
        <Enum name="B_0x2" description="Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer." start="0x2" />
        <Enum name="B_0x3" description="Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2)." start="0x3" />
        <Enum name="B_0x4" description="Compare - OC1REFC signal is used as trigger output (TRGO2)" start="0x4" />
        <Enum name="B_0x5" description="Compare - OC2REFC signal is used as trigger output (TRGO2)" start="0x5" />
        <Enum name="B_0x6" description="Compare - OC3REFC signal is used as trigger output (TRGO2)" start="0x6" />
        <Enum name="B_0x7" description="Compare - OC4REFC signal is used as trigger output (TRGO2)" start="0x7" />
        <Enum name="B_0x8" description="Compare - OC5REFC signal is used as trigger output (TRGO2)" start="0x8" />
        <Enum name="B_0x9" description="Compare - OC6REFC signal is used as trigger output (TRGO2)" start="0x9" />
        <Enum name="B_0xA" description="Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2" start="0xA" />
        <Enum name="B_0xB" description="Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2" start="0xB" />
        <Enum name="B_0xC" description="Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2" start="0xC" />
        <Enum name="B_0xD" description="Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2" start="0xD" />
        <Enum name="B_0xE" description="Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2" start="0xE" />
        <Enum name="B_0xF" description="Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2" start="0xF" />
      </BitField>
    </Register>
    <Register name="TIM1_SMCR" description="TIM1 slave mode control register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SMS1" description="Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer." start="0" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock." start="0x0" />
        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level." start="0x1" />
        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level." start="0x2" />
        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input." start="0x3" />
        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers." start="0x4" />
        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled." start="0x6" />
        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter." start="0x7" />
        <Enum name="B_0x8" description="Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.Codes above 1000: Reserved." start="0x8" />
      </BitField>
      <BitField name="OCCS" description="OCREF clear selection This bit is used to select the OCREF clear source." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OCREF_CLR_INT is not connected (reserved configuration)" start="0x0" />
        <Enum name="B_0x1" description="OCREF_CLR_INT is connected to ETRF" start="0x1" />
      </BitField>
      <BitField name="TS1" description="Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Internal Trigger 0 (ITR0) " start="0x0" />
        <Enum name="B_0x1" description="Internal Trigger 1 (ITR1)" start="0x1" />
        <Enum name="B_0x2" description="Internal Trigger 2 (ITR2)" start="0x2" />
        <Enum name="B_0x3" description="Internal Trigger 3 (ITR3)" start="0x3" />
        <Enum name="B_0x4" description="TI1 Edge Detector (TI1F_ED)" start="0x4" />
        <Enum name="B_0x5" description="Filtered Timer Input 1 (TI1FP1)" start="0x5" />
        <Enum name="B_0x6" description="Filtered Timer Input 2 (TI2FP2)" start="0x6" />
        <Enum name="B_0x7" description="External Trigger input (ETRF)" start="0x7" />
      </BitField>
      <BitField name="MSM" description="Master/slave mode" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
      </BitField>
      <BitField name="ETF" description="External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:" start="8" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, sampling is done at fDTS" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="ETPS" description="External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
        <Enum name="B_0x1" description="ETRP frequency divided by 2" start="0x1" />
        <Enum name="B_0x2" description="ETRP frequency divided by 4" start="0x2" />
        <Enum name="B_0x3" description="ETRP frequency divided by 8" start="0x3" />
      </BitField>
      <BitField name="ECE" description="External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal." start="0x1" />
      </BitField>
      <BitField name="ETP" description="External trigger polarity This bit selects whether ETR or ETR is used for trigger operations" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ETR is non-inverted, active at high level or rising edge." start="0x0" />
        <Enum name="B_0x1" description="ETR is inverted, active at low level or falling edge." start="0x1" />
      </BitField>
      <BitField name="SMS2" description="Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock." start="0x0" />
        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level." start="0x1" />
        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level." start="0x2" />
        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input." start="0x3" />
        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers." start="0x4" />
        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled." start="0x6" />
        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter." start="0x7" />
        <Enum name="B_0x8" description="Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.Codes above 1000: Reserved." start="0x8" />
      </BitField>
      <BitField name="TS2" description="Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Internal Trigger 0 (ITR0) " start="0x0" />
        <Enum name="B_0x1" description="Internal Trigger 1 (ITR1)" start="0x1" />
        <Enum name="B_0x2" description="Internal Trigger 2 (ITR2)" start="0x2" />
        <Enum name="B_0x3" description="Internal Trigger 3 (ITR3)" start="0x3" />
        <Enum name="B_0x4" description="TI1 Edge Detector (TI1F_ED)" start="0x4" />
        <Enum name="B_0x5" description="Filtered Timer Input 1 (TI1FP1)" start="0x5" />
        <Enum name="B_0x6" description="Filtered Timer Input 2 (TI2FP2)" start="0x6" />
        <Enum name="B_0x7" description="External Trigger input (ETRF)" start="0x7" />
      </BitField>
    </Register>
    <Register name="TIM1_DIER" description="TIM1 DMA/interrupt enable register " start="+0xc" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC2 interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="CC2 interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC3 interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="CC3 interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC4 interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="CC4 interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Trigger interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Trigger interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC2 DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="CC2 DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC3 DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="CC3 DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC4 DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="CC4 DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="COM DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="COM DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Trigger DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="Trigger DMA request enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM1_SR" description="TIM1 status register " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="UIF" description="Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No update occurred." start="0x0" />
        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
      </BitField>
      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
      </BitField>
      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag Refer to CC1IF description" start="2" size="1" access="Read/Write" />
      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag Refer to CC1IF description" start="3" size="1" access="Read/Write" />
      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag Refer to CC1IF description" start="4" size="1" access="Read/Write" />
      <BitField name="COMIF" description="COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No COM event occurred." start="0x0" />
        <Enum name="B_0x1" description="COM interrupt pending." start="0x1" />
      </BitField>
      <BitField name="TIF" description="Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
      </BitField>
      <BitField name="BIF" description="Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
        <Enum name="B_0x1" description="An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
      </BitField>
      <BitField name="B2IF" description="Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
        <Enum name="B_0x1" description="An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
      </BitField>
      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
      </BitField>
      <BitField name="CC2OF" description="Capture/Compare 2 overcapture flag Refer to CC1OF description" start="10" size="1" access="Read/Write" />
      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag Refer to CC1OF description" start="11" size="1" access="Read/Write" />
      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag Refer to CC1OF description" start="12" size="1" access="Read/Write" />
      <BitField name="SBIF" description="System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No break event occurred." start="0x0" />
        <Enum name="B_0x1" description="An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register." start="0x1" />
      </BitField>
      <BitField name="CC5IF" description="Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)" start="16" size="1" access="Read/Write" />
      <BitField name="CC6IF" description="Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)" start="17" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM1_EGR" description="TIM1 event generation register " start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UG" description="Update generation This bit can be set by software, it is automatically cleared by hardware." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
      </BitField>
      <BitField name="CC1G" description="Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
      </BitField>
      <BitField name="CC2G" description="Capture/Compare 2 generation Refer to CC1G description" start="2" size="1" access="WriteOnly" />
      <BitField name="CC3G" description="Capture/Compare 3 generation Refer to CC1G description" start="3" size="1" access="WriteOnly" />
      <BitField name="CC4G" description="Capture/Compare 4 generation Refer to CC1G description" start="4" size="1" access="WriteOnly" />
      <BitField name="COMG" description="Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated." start="0x1" />
      </BitField>
      <BitField name="TG" description="Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
      </BitField>
      <BitField name="BG" description="Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
      </BitField>
      <BitField name="B2G" description="Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware." start="8" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM1_CCMR1_input" description="TIM1 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
        <Enum name="B_0x2" description="CC1 channel is configured as input, IC1 is mapped on TI2" start="0x2" />
        <Enum name="B_0x3" description="CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC1PSC" description="Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
      </BitField>
      <BitField name="IC1F" description="Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:" start="4" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, sampling is done at fDTS" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="CC2S" description="Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on TI2" start="0x1" />
        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on TI1" start="0x2" />
        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC2PSC" description="Input capture 2 prescaler Refer to IC1PSC[1:0] description." start="10" size="2" access="Read/Write" />
      <BitField name="IC2F" description="Input capture 2 filter Refer to IC1F[3:0] description." start="12" size="4" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCMR1_output" description="TIM1 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
        <Enum name="B_0x2" description="CC1 channel is configured as input, IC1 is mapped on TI2" start="0x2" />
        <Enum name="B_0x3" description="CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC1FE" description="Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
      </BitField>
      <BitField name="OC1PE" description="Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
      </BitField>
      <BitField name="OC1M1" description="Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT&gt;TIMx_CCR1 else active (OC1REF=’1’)." start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
        <Enum name="B_0x8" description="Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update." start="0x8" />
        <Enum name="B_0x9" description="Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update." start="0x9" />
        <Enum name="B_0xC" description="Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF." start="0xC" />
        <Enum name="B_0xD" description="Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF." start="0xD" />
        <Enum name="B_0xE" description="Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xE" />
        <Enum name="B_0xF" description="Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xF" />
      </BitField>
      <BitField name="OC1CE" description="Output Compare 1 clear enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1Ref is not affected by the ocref_clr_int signal" start="0x0" />
        <Enum name="B_0x1" description="OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal (OCREF_CLR input or ETRF input)" start="0x1" />
      </BitField>
      <BitField name="CC2S" description="Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on TI2" start="0x1" />
        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on TI1" start="0x2" />
        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC2FE" description="Output Compare 2 fast enable Refer to OC1FE description." start="10" size="1" access="Read/Write" />
      <BitField name="OC2PE" description="Output Compare 2 preload enable Refer to OC1PE description." start="11" size="1" access="Read/Write" />
      <BitField name="OC2M1" description="Output Compare 2 mode Refer to OC1M[3:0] description." start="12" size="3" access="Read/Write" />
      <BitField name="OC2CE" description="Output Compare 2 clear enable Refer to OC1CE description." start="15" size="1" access="Read/Write" />
      <BitField name="OC1M2" description="Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT&gt;TIMx_CCR1 else active (OC1REF=’1’)." start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
        <Enum name="B_0x8" description="Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update." start="0x8" />
        <Enum name="B_0x9" description="Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update." start="0x9" />
        <Enum name="B_0xC" description="Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF." start="0xC" />
        <Enum name="B_0xD" description="Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF." start="0xD" />
        <Enum name="B_0xE" description="Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xE" />
        <Enum name="B_0xF" description="Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xF" />
      </BitField>
      <BitField name="OC2M2" description="Output Compare 2 mode Refer to OC1M[3:0] description." start="24" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCMR2_input" description="TIM1 capture/compare mode register 2 [alternate]" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC3S" description="Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC3 channel is configured as input, IC3 is mapped on TI3" start="0x1" />
        <Enum name="B_0x2" description="CC3 channel is configured as input, IC3 is mapped on TI4" start="0x2" />
        <Enum name="B_0x3" description="CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC3PSC" description="Input capture 3 prescaler Refer to IC1PSC[1:0] description." start="2" size="2" access="Read/Write" />
      <BitField name="IC3F" description="Input capture 3 filter Refer to IC1F[3:0] description." start="4" size="4" access="Read/Write" />
      <BitField name="CC4S" description="Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC4 channel is configured as input, IC4 is mapped on TI4" start="0x1" />
        <Enum name="B_0x2" description="CC4 channel is configured as input, IC4 is mapped on TI3" start="0x2" />
        <Enum name="B_0x3" description="CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC4PSC" description="Input capture 4 prescaler Refer to IC1PSC[1:0] description." start="10" size="2" access="Read/Write" />
      <BitField name="IC4F" description="Input capture 4 filter Refer to IC1F[3:0] description." start="12" size="4" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCMR2_output" description="TIM1 capture/compare mode register 2 [alternate]" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC3S" description="Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC3 channel is configured as input, IC3 is mapped on TI3" start="0x1" />
        <Enum name="B_0x2" description="CC3 channel is configured as input, IC3 is mapped on TI4" start="0x2" />
        <Enum name="B_0x3" description="CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC3FE" description="Output compare 3 fast enable Refer to OC1FE description." start="2" size="1" access="Read/Write" />
      <BitField name="OC3PE" description="Output compare 3 preload enable Refer to OC1PE description." start="3" size="1" access="Read/Write" />
      <BitField name="OC3M1" description="Output compare 3 mode Refer to OC1M[3:0] description." start="4" size="3" access="Read/Write" />
      <BitField name="OC3CE" description="Output compare 3 clear enable Refer to OC1CE description." start="7" size="1" access="Read/Write" />
      <BitField name="CC4S" description="Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC4 channel is configured as input, IC4 is mapped on TI4" start="0x1" />
        <Enum name="B_0x2" description="CC4 channel is configured as input, IC4 is mapped on TI3" start="0x2" />
        <Enum name="B_0x3" description="CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC4FE" description="Output compare 4 fast enable Refer to OC1FE description." start="10" size="1" access="Read/Write" />
      <BitField name="OC4PE" description="Output compare 4 preload enable Refer to OC1PE description." start="11" size="1" access="Read/Write" />
      <BitField name="OC4M1" description="Output compare 4 mode Refer to OC3M[3:0] description." start="12" size="3" access="Read/Write" />
      <BitField name="OC4CE" description="Output compare 4 clear enable Refer to OC1CE description." start="15" size="1" access="Read/Write" />
      <BitField name="OC3M2" description="Output compare 3 mode Refer to OC1M[3:0] description." start="16" size="1" access="Read/Write" />
      <BitField name="OC4M2" description="Output compare 4 mode Refer to OC3M[3:0] description." start="24" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCER" description="TIM1 capture/compare enable register&#09;" start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1E" description="Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
      </BitField>
      <BitField name="CC1P" description="Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0:&#09;non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1:&#09;inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1:&#09;non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0:&#09;The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
      </BitField>
      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
        <Enum name="B_0x1" description="On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
      </BitField>
      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1N active high." start="0x0" />
        <Enum name="B_0x1" description="OC1N active low." start="0x1" />
      </BitField>
      <BitField name="CC2E" description="Capture/Compare 2 output enable Refer to CC1E description" start="4" size="1" access="Read/Write" />
      <BitField name="CC2P" description="Capture/Compare 2 output polarity Refer to CC1P description" start="5" size="1" access="Read/Write" />
      <BitField name="CC2NE" description="Capture/Compare 2 complementary output enable Refer to CC1NE description" start="6" size="1" access="Read/Write" />
      <BitField name="CC2NP" description="Capture/Compare 2 complementary output polarity Refer to CC1NP description" start="7" size="1" access="Read/Write" />
      <BitField name="CC3E" description="Capture/Compare 3 output enable Refer to CC1E description" start="8" size="1" access="Read/Write" />
      <BitField name="CC3P" description="Capture/Compare 3 output polarity Refer to CC1P description" start="9" size="1" access="Read/Write" />
      <BitField name="CC3NE" description="Capture/Compare 3 complementary output enable Refer to CC1NE description" start="10" size="1" access="Read/Write" />
      <BitField name="CC3NP" description="Capture/Compare 3 complementary output polarity Refer to CC1NP description" start="11" size="1" access="Read/Write" />
      <BitField name="CC4E" description="Capture/Compare 4 output enable Refer to CC1E description" start="12" size="1" access="Read/Write" />
      <BitField name="CC4P" description="Capture/Compare 4 output polarity Refer to CC1P description" start="13" size="1" access="Read/Write" />
      <BitField name="CC4NP" description="Capture/Compare 4 complementary output polarity Refer to CC1NP description" start="15" size="1" access="Read/Write" />
      <BitField name="CC5E" description="Capture/Compare 5 output enable Refer to CC1E description" start="16" size="1" access="Read/Write" />
      <BitField name="CC5P" description="Capture/Compare 5 output polarity Refer to CC1P description" start="17" size="1" access="Read/Write" />
      <BitField name="CC6E" description="Capture/Compare 6 output enable Refer to CC1E description" start="20" size="1" access="Read/Write" />
      <BitField name="CC6P" description="Capture/Compare 6 output polarity Refer to CC1P description" start="21" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM1_CNT" description="TIM1 counter " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
      <BitField name="UIFCPY" description="UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0." start="31" size="1" access="ReadOnly" />
    </Register>
    <Register name="TIM1_PSC" description="TIM1 prescaler " start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="PSC" description="Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_ARR" description="TIM1 auto-reload register " start="+0x2c" size="2" reset_value="0x0000FFFF" reset_mask="0x0000FFFF">
      <BitField name="ARR" description="Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_RCR" description="TIM1 repetition counter register " start="+0x30" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="REP" description="Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCR1" description="TIM1 capture/compare register 1 " start="+0x34" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR1" description="Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCR2" description="TIM1 capture/compare register 2 " start="+0x38" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR2" description="Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCR3" description="TIM1 capture/compare register 3 " start="+0x3c" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR3" description="Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCR4" description="TIM1 capture/compare register 4 " start="+0x40" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR4" description="Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_BDTR" description="TIM1 break and dead-time register&#09;" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DTG" description="Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5] = 0xx =&gt; DT = DTG[7:0] x tDTG with tDTG = tDTS. DTG[7:5] = 10x =&gt; DT = (64 + DTG[5:0]) x tDTG with tDTG = 2 x tDTS. DTG[7:5] = 110 =&gt; DT = (32 + DTG[4:0]) x tDTG with tDTG = 8 x tDTS. DTG[7:5] = 111 =&gt; DT = (32 + DTG[4:0]) x tDTG with tDTG = 16 x tDTS. Example if tDTS = 125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="0" size="8" access="Read/Write" />
      <BitField name="LOCK" description="Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected." start="0x0" />
        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written." start="0x1" />
        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
      </BitField>
      <BitField name="OSSI" description="Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state)." start="0x0" />
        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output." start="0x1" />
      </BitField>
      <BitField name="OSSR" description="Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state)." start="0x0" />
        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
      </BitField>
      <BitField name="BKE" description="Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break function disabled" start="0x0" />
        <Enum name="B_0x1" description="Break function enabled" start="0x1" />
      </BitField>
      <BitField name="BKP" description="Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK is active low" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK is active high" start="0x1" />
      </BitField>
      <BitField name="AOE" description="Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)" start="0x1" />
      </BitField>
      <BitField name="MOE" description="Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="In response to a break 2 event. OC and OCN outputs are disabled" start="0x0" />
        <Enum name="B_0x1" description="OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)." start="0x1" />
      </BitField>
      <BitField name="BKF" description="Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="16" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, BRK acts asynchronously" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="BK2F" description="Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="20" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, BRK2 acts asynchronously" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="BK2E" description="Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="24" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK2 disabled" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK2 enabled" start="0x1" />
      </BitField>
      <BitField name="BK2P" description="Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="25" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK2 is active low" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK2 is active high" start="0x1" />
      </BitField>
      <BitField name="BKDSRM" description="Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK is armed" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK is disarmed" start="0x1" />
      </BitField>
      <BitField name="BK2DSRM" description="Break2 Disarm Refer to BKDSRM description" start="27" size="1" access="Read/Write" />
      <BitField name="BKBID" description="Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK in input mode" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK in bidirectional mode" start="0x1" />
      </BitField>
      <BitField name="BK2BID" description="Break2 bidirectional Refer to BKBID description" start="29" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM1_DCR" description="TIM1 DMA control register " start="+0x48" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DBA" description="DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ..." start="0" size="5" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
      </BitField>
      <BitField name="DBL" description="DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes &amp; DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA." start="8" size="5" access="Read/Write">
        <Enum name="B_0x0" description="1 transfer" start="0x0" />
        <Enum name="B_0x1" description="2 transfers" start="0x1" />
        <Enum name="B_0x2" description="3 transfers" start="0x2" />
        <Enum name="B_0x11" description="18 transfers" start="0x11" />
      </BitField>
    </Register>
    <Register name="TIM1_DMAR" description="TIM1 DMA address for full transfer&#09;" start="+0x4c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DMAB" description="DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)." start="0" size="32" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCMR3" description="TIM1 capture/compare mode register 3&#09;" start="+0x54" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="OC5FE" description="Output compare 5 fast enable Refer to OC1FE description." start="2" size="1" access="Read/Write" />
      <BitField name="OC5PE" description="Output compare 5 preload enable Refer to OC1PE description." start="3" size="1" access="Read/Write" />
      <BitField name="OC5M1" description="Output compare 5 mode Refer to OC1M description." start="4" size="3" access="Read/Write" />
      <BitField name="OC5CE" description="Output compare 5 clear enable Refer to OC1CE description." start="7" size="1" access="Read/Write" />
      <BitField name="OC6FE" description="Output compare 6 fast enable Refer to OC1FE description." start="10" size="1" access="Read/Write" />
      <BitField name="OC6PE" description="Output compare 6 preload enable Refer to OC1PE description." start="11" size="1" access="Read/Write" />
      <BitField name="OC6M1" description="Output compare 6 mode Refer to OC1M description." start="12" size="3" access="Read/Write" />
      <BitField name="OC6CE" description="Output compare 6 clear enable Refer to OC1CE description." start="15" size="1" access="Read/Write" />
      <BitField name="OC5M2" description="Output compare 5 mode Refer to OC1M description." start="16" size="1" access="Read/Write" />
      <BitField name="OC6M2" description="Output compare 6 mode Refer to OC1M description." start="24" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM1_CCR5" description="TIM1 capture/compare register 5 " start="+0x58" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CCR5" description="Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output." start="0" size="16" access="Read/Write" />
      <BitField name="GC5C1" description="Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals." start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect of OC5REF on OC1REFC5" start="0x0" />
        <Enum name="B_0x1" description="OC1REFC is the logical AND of OC1REFC and OC5REF" start="0x1" />
      </BitField>
      <BitField name="GC5C2" description="Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals." start="30" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect of OC5REF on OC2REFC" start="0x0" />
        <Enum name="B_0x1" description="OC2REFC is the logical AND of OC2REFC and OC5REF" start="0x1" />
      </BitField>
      <BitField name="GC5C3" description="Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals." start="31" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No effect of OC5REF on OC3REFC" start="0x0" />
        <Enum name="B_0x1" description="OC3REFC is the logical AND of OC3REFC and OC5REF" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM1_CCR6" description="TIM1 capture/compare register 6 " start="+0x5c" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR6" description="Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM1_AF1" description="TIM1 alternate function option register 1 " start="+0x60" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
      <BitField name="BKINE" description="BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN input disabled" start="0x0" />
        <Enum name="B_0x1" description="BKIN input enabled" start="0x1" />
      </BitField>
      <BitField name="BKINP" description="BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1)" start="0x0" />
        <Enum name="B_0x1" description="BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1)" start="0x1" />
      </BitField>
      <BitField name="ETRSEL" description="ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="14" size="4" access="Read/Write">
        <Enum name="B_0x0" description="ETR legacy mode" start="0x0" />
        <Enum name="B_0x3" description="ADC1 AWD1" start="0x3" />
        <Enum name="B_0x4" description="ADC1 AWD2" start="0x4" />
        <Enum name="B_0x5" description="ADC1 AWD3" start="0x5" />
      </BitField>
    </Register>
    <Register name="TIM1_AF2" description="TIM1 Alternate function register 2 " start="+0x64" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
      <BitField name="BK2INE" description="BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN2 input disabled" start="0x0" />
        <Enum name="B_0x1" description="BKIN2 input enabled" start="0x1" />
      </BitField>
      <BitField name="BK2INP" description="BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)" start="0x0" />
        <Enum name="B_0x1" description="BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM1_TISEL" description="TIM1 timer input selection register " start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input Others: Reserved" start="0" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM1_CH1 input" start="0x0" />
      </BitField>
      <BitField name="TI2SEL" description="selects TI2[0] to TI2[15] input Others: Reserved" start="8" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM1_CH2 input" start="0x0" />
      </BitField>
      <BitField name="TI3SEL" description="selects TI3[0] to TI3[15] input Others: Reserved" start="16" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM1_CH3 input" start="0x0" />
      </BitField>
      <BitField name="TI4SEL" description="selects TI4[0] to TI4[15] input Others: Reserved" start="24" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM1_CH4 input" start="0x0" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="TIM3" description="General-purpose timer" start="0x40000400">
    <Register name="TIM3_CR1" description="TIM3 control register 1 " start="+0x0" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CEN" description="Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
      </BitField>
      <BitField name="UDIS" description="Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
      </BitField>
      <BitField name="URS" description="Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be: " start="0x0" />
        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
      </BitField>
      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
      </BitField>
      <BitField name="DIR" description="Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter used as upcounter" start="0x0" />
        <Enum name="B_0x1" description="Counter used as downcounter" start="0x1" />
      </BitField>
      <BitField name="CMS" description="Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)" start="5" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR)." start="0x0" />
        <Enum name="B_0x1" description="Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down." start="0x1" />
        <Enum name="B_0x2" description="Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up." start="0x2" />
        <Enum name="B_0x3" description="Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down." start="0x3" />
      </BitField>
      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
      </BitField>
      <BitField name="CKD" description="Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx)," start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="tDTS = tCK_INT" start="0x0" />
        <Enum name="B_0x1" description="tDTS = 2 � tCK_INT" start="0x1" />
        <Enum name="B_0x2" description="tDTS = 4 � tCK_INT" start="0x2" />
      </BitField>
      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM3_CR2" description="TIM3 control register 2 " start="+0x4" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
      </BitField>
      <BitField name="MMS" description="Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset." start="0x0" />
        <Enum name="B_0x1" description="Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. " start="0x1" />
        <Enum name="B_0x2" description="Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer." start="0x2" />
        <Enum name="B_0x3" description="Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)" start="0x3" />
        <Enum name="B_0x4" description="Compare - OC1REFC signal is used as trigger output (TRGO)" start="0x4" />
        <Enum name="B_0x5" description="Compare - OC2REFC signal is used as trigger output (TRGO)" start="0x5" />
        <Enum name="B_0x6" description="Compare - OC3REFC signal is used as trigger output (TRGO)" start="0x6" />
        <Enum name="B_0x7" description="Compare - OC4REFC signal is used as trigger output (TRGO)" start="0x7" />
      </BitField>
      <BitField name="TI1S" description="TI1 selection" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The TIMx_CH1 pin is connected to TI1 input" start="0x0" />
        <Enum name="B_0x1" description="The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also " start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM3_SMCR" description="TIM3 slave mode control register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SMS1" description="Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer." start="0" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock." start="0x0" />
        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level." start="0x1" />
        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level." start="0x2" />
        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input." start="0x3" />
        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers." start="0x4" />
        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled." start="0x6" />
        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter." start="0x7" />
        <Enum name="B_0x8" description="Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)" start="0x8" />
      </BitField>
      <BitField name="OCCS" description="OCREF clear selection This bit is used to select the OCREF clear source" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OCREF_CLR_INT is unconnected." start="0x0" />
        <Enum name="B_0x1" description="OCREF_CLR_INT is connected to ETRF" start="0x1" />
      </BitField>
      <BitField name="TS1" description="Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Internal Trigger 0 (ITR0)" start="0x0" />
        <Enum name="B_0x1" description="Internal Trigger 1 (ITR1)" start="0x1" />
        <Enum name="B_0x2" description="Internal Trigger 2 (ITR2)" start="0x2" />
        <Enum name="B_0x3" description="Internal Trigger 3 (ITR3)" start="0x3" />
        <Enum name="B_0x4" description="TI1 Edge Detector (TI1F_ED)" start="0x4" />
        <Enum name="B_0x5" description="Filtered Timer Input 1 (TI1FP1)" start="0x5" />
        <Enum name="B_0x6" description="Filtered Timer Input 2 (TI2FP2)" start="0x6" />
        <Enum name="B_0x7" description="External Trigger input (ETRF)" start="0x7" />
        <Enum name="B_0x8" description="Internal Trigger 4 (ITR4)" start="0x8" />
        <Enum name="B_0x9" description="Internal Trigger 5 (ITR5)" start="0x9" />
        <Enum name="B_0xA" description="Internal Trigger 6 (ITR6)" start="0xA" />
        <Enum name="B_0xB" description="Internal Trigger 7 (ITR7)" start="0xB" />
        <Enum name="B_0xC" description="Internal Trigger 8 (ITR8)" start="0xC" />
      </BitField>
      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event." start="0x1" />
      </BitField>
      <BitField name="ETF" description="External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:" start="8" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, sampling is done at fDTS" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="ETPS" description="External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Prescaler OFF" start="0x0" />
        <Enum name="B_0x1" description="ETRP frequency divided by 2" start="0x1" />
        <Enum name="B_0x2" description="ETRP frequency divided by 4" start="0x2" />
        <Enum name="B_0x3" description="ETRP frequency divided by 8" start="0x3" />
      </BitField>
      <BitField name="ECE" description="External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="External clock mode 2 disabled" start="0x0" />
        <Enum name="B_0x1" description="External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal." start="0x1" />
      </BitField>
      <BitField name="ETP" description="External trigger polarity This bit selects whether ETR or ETR is used for trigger operations" start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="ETR is non-inverted, active at high level or rising edge" start="0x0" />
        <Enum name="B_0x1" description="ETR is inverted, active at low level or falling edge" start="0x1" />
      </BitField>
      <BitField name="SMS2" description="Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock." start="0x0" />
        <Enum name="B_0x1" description="Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level." start="0x1" />
        <Enum name="B_0x2" description="Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level." start="0x2" />
        <Enum name="B_0x3" description="Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input." start="0x3" />
        <Enum name="B_0x4" description="Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers." start="0x4" />
        <Enum name="B_0x5" description="Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled." start="0x5" />
        <Enum name="B_0x6" description="Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled." start="0x6" />
        <Enum name="B_0x7" description="External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter." start="0x7" />
        <Enum name="B_0x8" description="Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)" start="0x8" />
      </BitField>
      <BitField name="TS2" description="Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Internal Trigger 0 (ITR0)" start="0x0" />
        <Enum name="B_0x1" description="Internal Trigger 1 (ITR1)" start="0x1" />
        <Enum name="B_0x2" description="Internal Trigger 2 (ITR2)" start="0x2" />
        <Enum name="B_0x3" description="Internal Trigger 3 (ITR3)" start="0x3" />
        <Enum name="B_0x4" description="TI1 Edge Detector (TI1F_ED)" start="0x4" />
        <Enum name="B_0x5" description="Filtered Timer Input 1 (TI1FP1)" start="0x5" />
        <Enum name="B_0x6" description="Filtered Timer Input 2 (TI2FP2)" start="0x6" />
        <Enum name="B_0x7" description="External Trigger input (ETRF)" start="0x7" />
        <Enum name="B_0x8" description="Internal Trigger 4 (ITR4)" start="0x8" />
        <Enum name="B_0x9" description="Internal Trigger 5 (ITR5)" start="0x9" />
        <Enum name="B_0xA" description="Internal Trigger 6 (ITR6)" start="0xA" />
        <Enum name="B_0xB" description="Internal Trigger 7 (ITR7)" start="0xB" />
        <Enum name="B_0xC" description="Internal Trigger 8 (ITR8)" start="0xC" />
      </BitField>
    </Register>
    <Register name="TIM3_DIER" description="TIM3 DMA/Interrupt enable register " start="+0xc" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="Update interrupt enabled." start="0x1" />
      </BitField>
      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="CC1 interrupt enabled." start="0x1" />
      </BitField>
      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC2 interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="CC2 interrupt enabled." start="0x1" />
      </BitField>
      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC3 interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="CC3 interrupt enabled." start="0x1" />
      </BitField>
      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC4 interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="CC4 interrupt enabled." start="0x1" />
      </BitField>
      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Trigger interrupt disabled." start="0x0" />
        <Enum name="B_0x1" description="Trigger interrupt enabled." start="0x1" />
      </BitField>
      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update DMA request disabled." start="0x0" />
        <Enum name="B_0x1" description="Update DMA request enabled." start="0x1" />
      </BitField>
      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 DMA request disabled." start="0x0" />
        <Enum name="B_0x1" description="CC1 DMA request enabled." start="0x1" />
      </BitField>
      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC2 DMA request disabled." start="0x0" />
        <Enum name="B_0x1" description="CC2 DMA request enabled." start="0x1" />
      </BitField>
      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC3 DMA request disabled." start="0x0" />
        <Enum name="B_0x1" description="CC3 DMA request enabled." start="0x1" />
      </BitField>
      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC4 DMA request disabled." start="0x0" />
        <Enum name="B_0x1" description="CC4 DMA request enabled." start="0x1" />
      </BitField>
      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Trigger DMA request disabled." start="0x0" />
        <Enum name="B_0x1" description="Trigger DMA request enabled." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM3_SR" description="TIM3 status register " start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIF" description="Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No update occurred" start="0x0" />
        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
      </BitField>
      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
      </BitField>
      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag Refer to CC1IF description" start="2" size="1" access="Read/Write" />
      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag Refer to CC1IF description" start="3" size="1" access="Read/Write" />
      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag Refer to CC1IF description" start="4" size="1" access="Read/Write" />
      <BitField name="TIF" description="Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No trigger event occurred." start="0x0" />
        <Enum name="B_0x1" description="Trigger interrupt pending." start="0x1" />
      </BitField>
      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
      </BitField>
      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag refer to CC1OF description" start="10" size="1" access="Read/Write" />
      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag refer to CC1OF description" start="11" size="1" access="Read/Write" />
      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag refer to CC1OF description" start="12" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM3_EGR" description="TIM3 event generation register " start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UG" description="Update generation This bit can be set by software, it is automatically cleared by hardware." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting)." start="0x1" />
      </BitField>
      <BitField name="CC1G" description="Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
      </BitField>
      <BitField name="CC2G" description="Capture/compare 2 generation Refer to CC1G description" start="2" size="1" access="WriteOnly" />
      <BitField name="CC3G" description="Capture/compare 3 generation Refer to CC1G description" start="3" size="1" access="WriteOnly" />
      <BitField name="CC4G" description="Capture/compare 4 generation Refer to CC1G description" start="4" size="1" access="WriteOnly" />
      <BitField name="TG" description="Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware." start="6" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM3_CCMR1_input" description="TIM3 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
        <Enum name="B_0x2" description="CC1 channel is configured as input, IC1 is mapped on TI2" start="0x2" />
        <Enum name="B_0x3" description="CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC1PSC" description="Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register)." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
      </BitField>
      <BitField name="IC1F" description="Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:" start="4" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, sampling is done at fDTS" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="CC2S" description="Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC2 channel is configured as output." start="0x0" />
        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on TI2." start="0x1" />
        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on TI1." start="0x2" />
        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" access="Read/Write" />
      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCMR1_output" description="TIM3 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1." start="0x1" />
        <Enum name="B_0x2" description="CC1 channel is configured as input, IC1 is mapped on TI2." start="0x2" />
        <Enum name="B_0x3" description="CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC1FE" description="Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
      </BitField>
      <BitField name="OC1PE" description="Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
      </BitField>
      <BitField name="OC1M1" description="Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (OC1REF=1)." start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
        <Enum name="B_0x8" description="Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update." start="0x8" />
        <Enum name="B_0x9" description="Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update." start="0x9" />
        <Enum name="B_0xC" description="Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF." start="0xC" />
        <Enum name="B_0xD" description="Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF." start="0xD" />
        <Enum name="B_0xE" description="Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xE" />
        <Enum name="B_0xF" description="Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xF" />
      </BitField>
      <BitField name="OC1CE" description="Output compare 1 clear enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1Ref is not affected by the ETRF input" start="0x0" />
        <Enum name="B_0x1" description="OC1Ref is cleared as soon as a High level is detected on ETRF input" start="0x1" />
      </BitField>
      <BitField name="CC2S" description="Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC2 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC2 channel is configured as input, IC2 is mapped on TI2" start="0x1" />
        <Enum name="B_0x2" description="CC2 channel is configured as input, IC2 is mapped on TI1" start="0x2" />
        <Enum name="B_0x3" description="CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC2FE" description="Output compare 2 fast enable" start="10" size="1" access="Read/Write" />
      <BitField name="OC2PE" description="Output compare 2 preload enable" start="11" size="1" access="Read/Write" />
      <BitField name="OC2M1" description="Output compare 2 mode refer to OC1M description on bits 6:4" start="12" size="3" access="Read/Write" />
      <BitField name="OC2CE" description="Output compare 2 clear enable" start="15" size="1" access="Read/Write" />
      <BitField name="OC1M2" description="Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base)." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT&gt;TIMx_CCR1 else active (OC1REF=1)." start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT&gt;TIMx_CCR1 else inactive." start="0x7" />
        <Enum name="B_0x8" description="Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update." start="0x8" />
        <Enum name="B_0x9" description="Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update." start="0x9" />
        <Enum name="B_0xC" description="Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF." start="0xC" />
        <Enum name="B_0xD" description="Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF." start="0xD" />
        <Enum name="B_0xE" description="Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xE" />
        <Enum name="B_0xF" description="Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down." start="0xF" />
      </BitField>
      <BitField name="OC2M2" description="Output compare 2 mode refer to OC1M description on bits 6:4" start="24" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCMR2_input" description="TIM3 capture/compare mode register 2 [alternate]" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC3S" description="Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC3 channel is configured as input, IC3 is mapped on TI3" start="0x1" />
        <Enum name="B_0x2" description="CC3 channel is configured as input, IC3 is mapped on TI4" start="0x2" />
        <Enum name="B_0x3" description="CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" access="Read/Write" />
      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" access="Read/Write" />
      <BitField name="CC4S" description="Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC4 channel is configured as input, IC4 is mapped on TI4" start="0x1" />
        <Enum name="B_0x2" description="CC4 channel is configured as input, IC4 is mapped on TI3" start="0x2" />
        <Enum name="B_0x3" description="CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" access="Read/Write" />
      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCMR2_output" description="TIM3 capture/compare mode register 2 [alternate]" start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC3S" description="Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC3 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC3 channel is configured as input, IC3 is mapped on TI3" start="0x1" />
        <Enum name="B_0x2" description="CC3 channel is configured as input, IC3 is mapped on TI4" start="0x2" />
        <Enum name="B_0x3" description="CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" access="Read/Write" />
      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" access="Read/Write" />
      <BitField name="OC3M1" description="Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)" start="4" size="3" access="Read/Write" />
      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" access="Read/Write" />
      <BitField name="CC4S" description="Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC4 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC4 channel is configured as input, IC4 is mapped on TI4" start="0x1" />
        <Enum name="B_0x2" description="CC4 channel is configured as input, IC4 is mapped on TI3" start="0x2" />
        <Enum name="B_0x3" description="CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)" start="0x3" />
      </BitField>
      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" access="Read/Write" />
      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" access="Read/Write" />
      <BitField name="OC4M1" description="Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)" start="12" size="3" access="Read/Write" />
      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" access="Read/Write" />
      <BitField name="OC3M2" description="Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)" start="16" size="1" access="Read/Write" />
      <BitField name="OC4M2" description="Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)" start="24" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCER" description="TIM3 capture/compare enable register&#09;" start="+0x20" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
      </BitField>
      <BitField name="CC1P" description="Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0:&#09;non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1:&#09;inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1:&#09;non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0:&#09;This configuration is reserved, it must not be used." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
      </BitField>
      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description." start="3" size="1" access="Read/Write" />
      <BitField name="CC2E" description="Capture/Compare 2 output enable. Refer to CC1E description" start="4" size="1" access="Read/Write" />
      <BitField name="CC2P" description="Capture/Compare 2 output Polarity. refer to CC1P description" start="5" size="1" access="Read/Write" />
      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity. Refer to CC1NP description" start="7" size="1" access="Read/Write" />
      <BitField name="CC3E" description="Capture/Compare 3 output enable. Refer to CC1E description" start="8" size="1" access="Read/Write" />
      <BitField name="CC3P" description="Capture/Compare 3 output Polarity. Refer to CC1P description" start="9" size="1" access="Read/Write" />
      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity. Refer to CC1NP description" start="11" size="1" access="Read/Write" />
      <BitField name="CC4E" description="Capture/Compare 4 output enable. refer to CC1E description" start="12" size="1" access="Read/Write" />
      <BitField name="CC4P" description="Capture/Compare 4 output Polarity. Refer to CC1P description" start="13" size="1" access="Read/Write" />
      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity. Refer to CC1NP description" start="15" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM3_CNT" description="TIM3 counter [alternate] " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CNT" description="counter value" start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_CNT_alternate" description="TIM3 counter [alternate] " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CNT" description="counter value" start="0" size="16" access="Read/Write" />
      <BitField name="UIFCPY" description="UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register" start="31" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM3_PSC" description="TIM3 prescaler " start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="PSC" description="Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_ARR" description="TIM3 auto-reload register " start="+0x2c" size="4" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
      <BitField name="ARR" description="Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCR1" description="TIM3 capture/compare register 1 " start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CCR1" description="Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCR2" description="TIM3 capture/compare register 2 " start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CCR2" description="Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCR3" description="TIM3 capture/compare register 3 " start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CCR3" description="Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_CCR4" description="TIM3 capture/compare register 4 " start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CCR4" description="Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_DCR" description="TIM3 DMA control register " start="+0x48" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DBA" description="DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers &amp; DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address." start="0" size="5" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_CR1" start="0x0" />
        <Enum name="B_0x1" description="TIMx_CR2" start="0x1" />
        <Enum name="B_0x2" description="TIMx_SMCR" start="0x2" />
      </BitField>
      <BitField name="DBL" description="DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ..." start="8" size="5" access="Read/Write">
        <Enum name="B_0x0" description="1 transfer," start="0x0" />
        <Enum name="B_0x1" description="2 transfers," start="0x1" />
        <Enum name="B_0x2" description="3 transfers," start="0x2" />
        <Enum name="B_0x11" description="18 transfers." start="0x11" />
      </BitField>
    </Register>
    <Register name="TIM3_DMAR" description="TIM3 DMA address for full transfer " start="+0x4c" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DMAB" description="DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM3_AF1" description="TIM3 alternate function option register 1 " start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ETRSEL" description="ETR source selection These bits select the ETR input source. Others: Reserved" start="14" size="4" access="Read/Write">
        <Enum name="B_0x0" description="ETR legacy mode" start="0x0" />
      </BitField>
    </Register>
    <Register name="TIM3_TISEL" description="TIM3 timer input selection register " start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved" start="0" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM3_CH1 input" start="0x0" />
      </BitField>
      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved" start="8" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM3_CH2 input" start="0x0" />
      </BitField>
      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved" start="16" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM3_CH3 input" start="0x0" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="TIM14" description="General-purpose timers" start="0x40002000">
    <Register name="TIM14_CR1" description="TIM14 control register 1 " start="+0x0" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CEN" description="Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
      </BitField>
      <BitField name="UDIS" description="Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="UEV enabled. An UEV is generated by one of the following events:" start="0x0" />
        <Enum name="B_0x1" description="UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set." start="0x1" />
      </BitField>
      <BitField name="URS" description="Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Any of the following events generate an UEV if enabled: " start="0x0" />
        <Enum name="B_0x1" description="Only counter overflow generates an UEV if enabled." start="0x1" />
      </BitField>
      <BitField name="OPM" description="One-pulse mode" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter is not stopped on the update event" start="0x0" />
        <Enum name="B_0x1" description="Counter stops counting on the next update event (clearing the CEN bit)." start="0x1" />
      </BitField>
      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
      </BitField>
      <BitField name="CKD" description="Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx)," start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="tDTS = tCK_INT" start="0x0" />
        <Enum name="B_0x1" description="tDTS = 2 � tCK_INT" start="0x1" />
        <Enum name="B_0x2" description="tDTS = 4 � tCK_INT" start="0x2" />
      </BitField>
      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM14_DIER" description="TIM14 Interrupt enable register " start="+0xc" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM14_SR" description="TIM14 status register " start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIF" description="Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=’0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No update occurred." start="0x0" />
        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
      </BitField>
      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
        <Enum name="B_0x1" description="A compare match or an input capture occurred." start="0x1" />
      </BitField>
      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No overcapture has been detected." start="0x0" />
        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM14_EGR" description="TIM14 event generation register " start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UG" description="Update generation This bit can be set by software, it is automatically cleared by hardware." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. " start="0x1" />
      </BitField>
      <BitField name="CC1G" description="Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM14_CCMR1_input" description="TIM14 capture/compare mode register 1 [alternate] " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
      </BitField>
      <BitField name="IC1PSC" description="Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input" start="0x0" />
        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
      </BitField>
      <BitField name="IC1F" description="Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:" start="4" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, sampling is done at fDTS" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
    </Register>
    <Register name="TIM14_CCMR1_output" description="TIM14 capture/compare mode register 1 [alternate] " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output." start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1." start="0x1" />
      </BitField>
      <BitField name="OC1FE" description="Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
      </BitField>
      <BitField name="OC1PE" description="Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. " start="0x0" />
        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
      </BitField>
      <BitField name="OC1M1" description="Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. " start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). " start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). " start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. " start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low. " start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT &lt; TIMx_CCR1 else inactive." start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT &lt; TIMx_CCR1 else active" start="0x7" />
      </BitField>
      <BitField name="OC1M2" description="Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. " start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). " start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). " start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. " start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low. " start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT &lt; TIMx_CCR1 else inactive." start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT &lt; TIMx_CCR1 else active" start="0x7" />
      </BitField>
    </Register>
    <Register name="TIM14_CCER" description="TIM14 capture/compare enable register " start="+0x20" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CC1E" description="Capture/Compare 1 output enable." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active" start="0x0" />
        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
      </BitField>
      <BitField name="CC1P" description="Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0:&#09;non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1:&#09;inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1:&#09;non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0:&#09;This configuration is reserved, it must not be used." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
      </BitField>
      <BitField name="CC1NP" description="Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description)." start="3" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM14_CNT" description="TIM14 counter " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
      <BitField name="UIFCPY" description="UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register." start="31" size="1" access="Read/Write" />
    </Register>
    <Register name="TIM14_PSC" description="TIM14 prescaler " start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="PSC" description="Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM14_ARR" description="TIM14 auto-reload register " start="+0x2c" size="2" reset_value="0x0000FFFF" reset_mask="0x0000FFFF">
      <BitField name="ARR" description="Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM14_CCR1" description="TIM14 capture/compare register 1 " start="+0x34" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR1" description="Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM14_TISEL" description="TIM14 timer input selection register " start="+0x68" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input Others: Reserved" start="0" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM14_CH1 input" start="0x0" />
        <Enum name="B_0x1" description="RTC CLK" start="0x1" />
        <Enum name="B_0x2" description="HSE/32" start="0x2" />
        <Enum name="B_0x3" description="MCO" start="0x3" />
        <Enum name="B_0x4" description="MCO2" start="0x4" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="TIM16" description="General-purpose timers" start="0x40014400">
    <Register name="TIM16_CR1" description="TIM16 control register 1" start="+0x0" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CEN" description="Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
      </BitField>
      <BitField name="UDIS" description="Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
      </BitField>
      <BitField name="URS" description="Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be: " start="0x0" />
        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
      </BitField>
      <BitField name="OPM" description="One pulse mode" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
      </BitField>
      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
      </BitField>
      <BitField name="CKD" description="Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx)," start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="tDTS = tCK_INT" start="0x0" />
        <Enum name="B_0x1" description="tDTS = 2 * tCK_INT" start="0x1" />
        <Enum name="B_0x2" description="tDTS = 4 * tCK_INT" start="0x2" />
        <Enum name="B_0x3" description="Reserved, do not program this value" start="0x3" />
      </BitField>
      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_CR2" description="TIM16 control register 2" start="+0x4" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCPC" description="Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set." start="0x1" />
      </BitField>
      <BitField name="CCUS" description="Capture/compare control update selection Note: This bit acts only on channels that have a complementary output." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI." start="0x1" />
      </BitField>
      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
      </BitField>
      <BitField name="OIS1" description="Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1=0 (after a dead-time if OC1N is implemented) when MOE=0" start="0x0" />
        <Enum name="B_0x1" description="OC1=1 (after a dead-time if OC1N is implemented) when MOE=0" start="0x1" />
      </BitField>
      <BitField name="OIS1N" description="Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1N=0 after a dead-time when MOE=0" start="0x0" />
        <Enum name="B_0x1" description="OC1N=1 after a dead-time when MOE=0" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_DIER" description="TIM16 DMA/interrupt enable register" start="+0xc" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_SR" description="TIM16 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIF" description="Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No update occurred." start="0x0" />
        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
      </BitField>
      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
      </BitField>
      <BitField name="COMIF" description="COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
      </BitField>
      <BitField name="BIF" description="Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
      </BitField>
      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_EGR" description="TIM16 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UG" description="Update generation This bit can be set by software, it is automatically cleared by hardware." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action." start="0x0" />
        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). " start="0x1" />
      </BitField>
      <BitField name="CC1G" description="Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action." start="0x0" />
        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
      </BitField>
      <BitField name="COMG" description="Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
      </BitField>
      <BitField name="BG" description="Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action." start="0x0" />
        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_CCMR1_input" description="TIM16 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
      </BitField>
      <BitField name="IC1PSC" description="Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input." start="0x0" />
        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
      </BitField>
      <BitField name="IC1F" description="Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:" start="4" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, sampling is done at fDTS" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
    </Register>
    <Register name="TIM16_CCMR1_output" description="TIM16 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
      </BitField>
      <BitField name="OC1FE" description="Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
      </BitField>
      <BitField name="OC1PE" description="Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
      </BitField>
      <BitField name="OC1M1" description="Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. " start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. " start="0x7" />
      </BitField>
      <BitField name="OC1M2" description="Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. " start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. " start="0x7" />
      </BitField>
    </Register>
    <Register name="TIM16_CCER" description="TIM16 capture/compare enable register" start="+0x20" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CC1E" description="Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
      </BitField>
      <BitField name="CC1P" description="Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0:&#09;non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1:&#09;inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1:&#09;non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0:&#09;this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
      </BitField>
      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
        <Enum name="B_0x1" description="On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
      </BitField>
      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1N active high" start="0x0" />
        <Enum name="B_0x1" description="OC1N active low" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_CNT" description="TIM16 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
      <BitField name="UIFCPY" description="UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0." start="31" size="1" access="ReadOnly" />
    </Register>
    <Register name="TIM16_PSC" description="TIM16 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="PSC" description="Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM16_ARR" description="TIM16 auto-reload register" start="+0x2c" size="2" reset_value="0x0000FFFF" reset_mask="0x0000FFFF">
      <BitField name="ARR" description="Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM16_RCR" description="TIM16 repetition counter register" start="+0x30" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="REP" description="Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode." start="0" size="8" access="Read/Write" />
    </Register>
    <Register name="TIM16_CCR1" description="TIM16 capture/compare register 1" start="+0x34" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR1" description="Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM16_BDTR" description="TIM16 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DTG" description="Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5] = 0xx =&gt; DT = DTG[7:0] x tdtg with tdtg = tDTS DTG[7:5] = 10x =&gt; DT = (64 + DTG[5:0]) x tdtg with tdtg = 2 x tDTS DTG[7:5] = 110 =&gt; DT = (32 + DTG[4:0]) x tdtg with tdtg = 8 x tDTS DTG[7:5] = 111 =&gt; DT = (32 + DTG[4:0]) x tdtg with tdtg = 16 x tDTS Example if tDTS = 125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 �s to 31750 ns by 250 ns steps, 32 �s to 63 �s by 1 �s steps, 64 �s to 126 �s by 2 �s steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="0" size="8" access="Read/Write" />
      <BitField name="LOCK" description="Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
      </BitField>
      <BitField name="OSSI" description="Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)" start="0x0" />
        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)" start="0x1" />
      </BitField>
      <BitField name="OSSR" description="Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
      </BitField>
      <BitField name="BKE" description="Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break inputs (BRK and CCS clock failure event) disabled" start="0x0" />
      </BitField>
      <BitField name="BKP" description="Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK is active low" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK is active high" start="0x1" />
      </BitField>
      <BitField name="AOE" description="Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the break input is not be active)" start="0x1" />
      </BitField>
      <BitField name="MOE" description="Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
        <Enum name="B_0x1" description="OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (" start="0x1" />
      </BitField>
      <BitField name="BKF" description="Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="16" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, BRK acts asynchronously" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="BKDSRM" description="Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK is armed" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK is disarmed" start="0x1" />
      </BitField>
      <BitField name="BKBID" description="Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK in input mode" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK in bidirectional mode" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_DCR" description="TIM16 DMA control register" start="+0x48" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DBA" description="DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address." start="0" size="5" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
      </BitField>
      <BitField name="DBL" description="DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ..." start="8" size="5" access="Read/Write">
        <Enum name="B_0x0" description="1 transfer," start="0x0" />
        <Enum name="B_0x1" description="2 transfers," start="0x1" />
        <Enum name="B_0x2" description="3 transfers," start="0x2" />
        <Enum name="B_0x11" description="18 transfers." start="0x11" />
      </BitField>
    </Register>
    <Register name="TIM16_DMAR" description="TIM16 DMA address for full transfer" start="+0x4c" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DMAB" description="DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM16_AF1" description="TIM16 alternate function register 1 " start="+0x60" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
      <BitField name="BKINE" description="BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN input disabled" start="0x0" />
        <Enum name="B_0x1" description="BKIN input enabled" start="0x1" />
      </BitField>
      <BitField name="BKINP" description="BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN input is active low" start="0x0" />
        <Enum name="B_0x1" description="BKIN input is active high" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM16_TISEL" description="TIM16 input selection register " start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input Others: Reserved" start="0" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM16_CH1 input" start="0x0" />
        <Enum name="B_0x1" description="LSI" start="0x1" />
        <Enum name="B_0x2" description="LSE" start="0x2" />
        <Enum name="B_0x4" description="MCO2" start="0x4" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="TIM17" description="General-purpose timers" start="0x40014800">
    <Register name="TIM17_CR1" description="TIM17 control register 1" start="+0x0" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CEN" description="Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter disabled" start="0x0" />
        <Enum name="B_0x1" description="Counter enabled" start="0x1" />
      </BitField>
      <BitField name="UDIS" description="Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="UEV enabled. The Update (UEV) event is generated by one of the following events:" start="0x0" />
        <Enum name="B_0x1" description="UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller." start="0x1" />
      </BitField>
      <BitField name="URS" description="Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Any of the following events generate an update interrupt or DMA request if enabled. These events can be: " start="0x0" />
        <Enum name="B_0x1" description="Only counter overflow/underflow generates an update interrupt or DMA request if enabled." start="0x1" />
      </BitField>
      <BitField name="OPM" description="One pulse mode" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Counter is not stopped at update event" start="0x0" />
        <Enum name="B_0x1" description="Counter stops counting at the next update event (clearing the bit CEN)" start="0x1" />
      </BitField>
      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_ARR register is not buffered" start="0x0" />
        <Enum name="B_0x1" description="TIMx_ARR register is buffered" start="0x1" />
      </BitField>
      <BitField name="CKD" description="Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx)," start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="tDTS = tCK_INT" start="0x0" />
        <Enum name="B_0x1" description="tDTS = 2 * tCK_INT" start="0x1" />
        <Enum name="B_0x2" description="tDTS = 4 * tCK_INT" start="0x2" />
        <Enum name="B_0x3" description="Reserved, do not program this value" start="0x3" />
      </BitField>
      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No remapping. UIF status bit is not copied to TIMx_CNT register bit 31." start="0x0" />
        <Enum name="B_0x1" description="Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_CR2" description="TIM17 control register 2" start="+0x4" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCPC" description="Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CCxE, CCxNE and OCxM bits are not preloaded" start="0x0" />
        <Enum name="B_0x1" description="CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set." start="0x1" />
      </BitField>
      <BitField name="CCUS" description="Capture/compare control update selection Note: This bit acts only on channels that have a complementary output." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only." start="0x0" />
        <Enum name="B_0x1" description="When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI." start="0x1" />
      </BitField>
      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CCx DMA request sent when CCx event occurs" start="0x0" />
        <Enum name="B_0x1" description="CCx DMA requests sent when update event occurs" start="0x1" />
      </BitField>
      <BitField name="OIS1" description="Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1=0 (after a dead-time if OC1N is implemented) when MOE=0" start="0x0" />
        <Enum name="B_0x1" description="OC1=1 (after a dead-time if OC1N is implemented) when MOE=0" start="0x1" />
      </BitField>
      <BitField name="OIS1N" description="Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1N=0 after a dead-time when MOE=0" start="0x0" />
        <Enum name="B_0x1" description="OC1N=1 after a dead-time when MOE=0" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_DIER" description="TIM17 DMA/interrupt enable register" start="+0xc" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Update interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="CC1 interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="COM interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="COM interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break interrupt disabled" start="0x0" />
        <Enum name="B_0x1" description="Break interrupt enabled" start="0x1" />
      </BitField>
      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Update DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="Update DMA request enabled" start="0x1" />
      </BitField>
      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 DMA request disabled" start="0x0" />
        <Enum name="B_0x1" description="CC1 DMA request enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_SR" description="TIM17 status register" start="+0x10" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UIF" description="Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No update occurred." start="0x0" />
        <Enum name="B_0x1" description="Update interrupt pending. This bit is set by hardware when the registers are updated:" start="0x1" />
      </BitField>
      <BitField name="CC1IF" description="Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No compare match / No input capture occurred" start="0x0" />
        <Enum name="B_0x1" description="A compare match or an input capture occurred" start="0x1" />
      </BitField>
      <BitField name="COMIF" description="COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No COM event occurred" start="0x0" />
        <Enum name="B_0x1" description="COM interrupt pending" start="0x1" />
      </BitField>
      <BitField name="BIF" description="Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No break event occurred" start="0x0" />
        <Enum name="B_0x1" description="An active level has been detected on the break input" start="0x1" />
      </BitField>
      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="No overcapture has been detected" start="0x0" />
        <Enum name="B_0x1" description="The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_EGR" description="TIM17 event generation register" start="+0x14" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="UG" description="Update generation This bit can be set by software, it is automatically cleared by hardware." start="0" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action." start="0x0" />
        <Enum name="B_0x1" description="Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). " start="0x1" />
      </BitField>
      <BitField name="CC1G" description="Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high." start="1" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action." start="0x0" />
        <Enum name="B_0x1" description="A capture/compare event is generated on channel 1:" start="0x1" />
      </BitField>
      <BitField name="COMG" description="Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output." start="5" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action" start="0x0" />
        <Enum name="B_0x1" description="When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits" start="0x1" />
      </BitField>
      <BitField name="BG" description="Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware." start="7" size="1" access="WriteOnly">
        <Enum name="B_0x0" description="No action." start="0x0" />
        <Enum name="B_0x1" description="A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled." start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_CCMR1_input" description="TIM17 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
      </BitField>
      <BitField name="IC1PSC" description="Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register)." start="2" size="2" access="Read/Write">
        <Enum name="B_0x0" description="no prescaler, capture is done each time an edge is detected on the capture input." start="0x0" />
        <Enum name="B_0x1" description="capture is done once every 2 events" start="0x1" />
        <Enum name="B_0x2" description="capture is done once every 4 events" start="0x2" />
        <Enum name="B_0x3" description="capture is done once every 8 events" start="0x3" />
      </BitField>
      <BitField name="IC1F" description="Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:" start="4" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, sampling is done at fDTS" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
    </Register>
    <Register name="TIM17_CCMR1_output" description="TIM17 capture/compare mode register 1 [alternate]" start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CC1S" description="Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER)." start="0" size="2" access="Read/Write">
        <Enum name="B_0x0" description="CC1 channel is configured as output" start="0x0" />
        <Enum name="B_0x1" description="CC1 channel is configured as input, IC1 is mapped on TI1" start="0x1" />
      </BitField>
      <BitField name="OC1FE" description="Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles." start="0x0" />
        <Enum name="B_0x1" description="An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode." start="0x1" />
      </BitField>
      <BitField name="OC1PE" description="Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately." start="0x0" />
        <Enum name="B_0x1" description="Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event." start="0x1" />
      </BitField>
      <BitField name="OC1M1" description="Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16." start="4" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. " start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. " start="0x7" />
      </BitField>
      <BitField name="OC1M2" description="Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs." start="0x0" />
        <Enum name="B_0x1" description="Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x1" />
        <Enum name="B_0x2" description="Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1)." start="0x2" />
        <Enum name="B_0x3" description="Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1." start="0x3" />
        <Enum name="B_0x4" description="Force inactive level - OC1REF is forced low." start="0x4" />
        <Enum name="B_0x5" description="Force active level - OC1REF is forced high." start="0x5" />
        <Enum name="B_0x6" description="PWM mode 1 - Channel 1 is active as long as TIMx_CNT&lt;TIMx_CCR1 else inactive. " start="0x6" />
        <Enum name="B_0x7" description="PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT&lt;TIMx_CCR1 else active. " start="0x7" />
      </BitField>
    </Register>
    <Register name="TIM17_CCER" description="TIM17 capture/compare enable register" start="+0x20" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CC1E" description="Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Capture mode disabled / OC1 is not active (see below)" start="0x0" />
        <Enum name="B_0x1" description="Capture mode enabled / OC1 signal is output on the corresponding output pin" start="0x1" />
      </BitField>
      <BitField name="CC1P" description="Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0:&#09;non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1:&#09;inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1:&#09;non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0:&#09;this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)" start="0x0" />
        <Enum name="B_0x1" description="OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)" start="0x1" />
      </BitField>
      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x0" />
        <Enum name="B_0x1" description="On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits." start="0x1" />
      </BitField>
      <BitField name="CC1NP" description="Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC1N active high" start="0x0" />
        <Enum name="B_0x1" description="OC1N active low" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_CNT" description="TIM17 counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="CNT" description="Counter value" start="0" size="16" access="Read/Write" />
      <BitField name="UIFCPY" description="UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0." start="31" size="1" access="ReadOnly" />
    </Register>
    <Register name="TIM17_PSC" description="TIM17 prescaler" start="+0x28" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="PSC" description="Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM17_ARR" description="TIM17 auto-reload register" start="+0x2c" size="2" reset_value="0x0000FFFF" reset_mask="0x0000FFFF">
      <BitField name="ARR" description="Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM17_RCR" description="TIM17 repetition counter register" start="+0x30" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="REP" description="Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode." start="0" size="8" access="Read/Write" />
    </Register>
    <Register name="TIM17_CCR1" description="TIM17 capture/compare register 1" start="+0x34" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="CCR1" description="Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM17_BDTR" description="TIM17 break and dead-time register" start="+0x44" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="DTG" description="Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5] = 0xx =&gt; DT = DTG[7:0] x tdtg with tdtg = tDTS DTG[7:5] = 10x =&gt; DT = (64 + DTG[5:0]) x tdtg with tdtg = 2 x tDTS DTG[7:5] = 110 =&gt; DT = (32 + DTG[4:0]) x tdtg with tdtg = 8 x tDTS DTG[7:5] = 111 =&gt; DT = (32 + DTG[4:0]) x tdtg with tdtg = 16 x tDTS Example if tDTS = 125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 �s to 31750 ns by 250 ns steps, 32 �s to 63 �s by 1 �s steps, 64 �s to 126 �s by 2 �s steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)." start="0" size="8" access="Read/Write" />
      <BitField name="LOCK" description="Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset." start="8" size="2" access="Read/Write">
        <Enum name="B_0x0" description="LOCK OFF - No bit is write protected" start="0x0" />
        <Enum name="B_0x1" description="LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written." start="0x1" />
        <Enum name="B_0x2" description="LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written." start="0x2" />
        <Enum name="B_0x3" description="LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written." start="0x3" />
      </BitField>
      <BitField name="OSSI" description="Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)" start="0x0" />
        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)" start="0x1" />
      </BitField>
      <BitField name="OSSR" description="Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)" start="0x0" />
        <Enum name="B_0x1" description="When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer)." start="0x1" />
      </BitField>
      <BitField name="BKE" description="Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break inputs (BRK and CCS clock failure event) disabled" start="0x0" />
      </BitField>
      <BitField name="BKP" description="Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK is active low" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK is active high" start="0x1" />
      </BitField>
      <BitField name="AOE" description="Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="MOE can be set only by software" start="0x0" />
        <Enum name="B_0x1" description="MOE can be set by software or automatically at the next update event (if the break input is not be active)" start="0x1" />
      </BitField>
      <BitField name="MOE" description="Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit." start="0x0" />
        <Enum name="B_0x1" description="OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (" start="0x1" />
      </BitField>
      <BitField name="BKF" description="Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="16" size="4" access="Read/Write">
        <Enum name="B_0x0" description="No filter, BRK acts asynchronously" start="0x0" />
        <Enum name="B_0x1" description="fSAMPLING=fCK_INT, N=2" start="0x1" />
        <Enum name="B_0x2" description="fSAMPLING=fCK_INT, N=4" start="0x2" />
        <Enum name="B_0x3" description="fSAMPLING=fCK_INT, N=8" start="0x3" />
        <Enum name="B_0x4" description="fSAMPLING=fDTS/2, N=6" start="0x4" />
        <Enum name="B_0x5" description="fSAMPLING=fDTS/2, N=8" start="0x5" />
        <Enum name="B_0x6" description="fSAMPLING=fDTS/4, N=6" start="0x6" />
        <Enum name="B_0x7" description="fSAMPLING=fDTS/4, N=8" start="0x7" />
        <Enum name="B_0x8" description="fSAMPLING=fDTS/8, N=6" start="0x8" />
        <Enum name="B_0x9" description="fSAMPLING=fDTS/8, N=8" start="0x9" />
        <Enum name="B_0xA" description="fSAMPLING=fDTS/16, N=5" start="0xA" />
        <Enum name="B_0xB" description="fSAMPLING=fDTS/16, N=6" start="0xB" />
        <Enum name="B_0xC" description="fSAMPLING=fDTS/16, N=8" start="0xC" />
        <Enum name="B_0xD" description="fSAMPLING=fDTS/32, N=5" start="0xD" />
        <Enum name="B_0xE" description="fSAMPLING=fDTS/32, N=6" start="0xE" />
        <Enum name="B_0xF" description="fSAMPLING=fDTS/32, N=8" start="0xF" />
      </BitField>
      <BitField name="BKDSRM" description="Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK is armed" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK is disarmed" start="0x1" />
      </BitField>
      <BitField name="BKBID" description="Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Break input BRK in input mode" start="0x0" />
        <Enum name="B_0x1" description="Break input BRK in bidirectional mode" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_DCR" description="TIM17 DMA control register" start="+0x48" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DBA" description="DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address." start="0" size="5" access="Read/Write">
        <Enum name="B_0x0" description="TIMx_CR1," start="0x0" />
        <Enum name="B_0x1" description="TIMx_CR2," start="0x1" />
        <Enum name="B_0x2" description="TIMx_SMCR," start="0x2" />
      </BitField>
      <BitField name="DBL" description="DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ..." start="8" size="5" access="Read/Write">
        <Enum name="B_0x0" description="1 transfer," start="0x0" />
        <Enum name="B_0x1" description="2 transfers," start="0x1" />
        <Enum name="B_0x2" description="3 transfers," start="0x2" />
        <Enum name="B_0x11" description="18 transfers." start="0x11" />
      </BitField>
    </Register>
    <Register name="TIM17_DMAR" description="TIM17 DMA address for full transfer" start="+0x4c" size="2" reset_value="0x00000000" reset_mask="0x0000FFFF">
      <BitField name="DMAB" description="DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="TIM17_AF1" description="TIM17 alternate function register 1 " start="+0x60" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
      <BitField name="BKINE" description="BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN input disabled" start="0x0" />
        <Enum name="B_0x1" description="BKIN input enabled" start="0x1" />
      </BitField>
      <BitField name="BKINP" description="BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="BKIN input is active low" start="0x0" />
        <Enum name="B_0x1" description="BKIN input is active high" start="0x1" />
      </BitField>
    </Register>
    <Register name="TIM17_TISEL" description="TIM17 input selection register " start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input Others: Reserved" start="0" size="4" access="Read/Write">
        <Enum name="B_0x0" description="TIM17_CH1 input" start="0x0" />
        <Enum name="B_0x2" description="HSE/32" start="0x2" />
        <Enum name="B_0x3" description="MCO" start="0x3" />
        <Enum name="B_0x4" description="MCO2" start="0x4" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="USART1" description="USART register block" start="0x40013800">
    <Register name="USART_CR1_enabled" description="USART control register 1 [alternate] " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="UE" description="USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
        <Enum name="B_0x1" description="USART enabled" start="0x1" />
      </BitField>
      <BitField name="UESM" description="USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode. " start="0x1" />
      </BitField>
      <BitField name="RE" description="Receiver enable This bit enables the receiver. It is set and cleared by software." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
      </BitField>
      <BitField name="TE" description="Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to ‘1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
      </BitField>
      <BitField name="IDLEIE" description="IDLE interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="Transmission complete interrupt enable This bit is set and cleared by software." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TC = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable This bit is set and cleared by software." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PEIE" description="PE interrupt enable This bit is set and cleared by software." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever PE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PS" description="Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Even parity" start="0x0" />
        <Enum name="B_0x1" description="Odd parity" start="0x1" />
      </BitField>
      <BitField name="PCE" description="Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
      </BitField>
      <BitField name="WAKE" description="Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Idle line" start="0x0" />
        <Enum name="B_0x1" description="Address mark" start="0x1" />
      </BitField>
      <BitField name="M0" description="Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)." start="12" size="1" access="Read/Write" />
      <BitField name="MME" description="Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver in active mode permanently" start="0x0" />
        <Enum name="B_0x1" description="Receiver can switch between Mute mode and active mode. " start="0x1" />
      </BitField>
      <BitField name="CMIE" description="Character match interrupt enable This bit is set and cleared by software." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="OVER8" description="Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
      </BitField>
      <BitField name="DEDT" description="Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="16" size="5" access="Read/Write" />
      <BitField name="DEAT" description="Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="21" size="5" access="Read/Write" />
      <BitField name="RTOIE" description="Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="EOBIE" description="End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="M1" description="Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported." start="28" size="1" access="Read/Write" />
      <BitField name="FIFOEN" description="FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes." start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
      </BitField>
      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable This bit is set and cleared by software." start="30" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when TXFE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable This bit is set and cleared by software." start="31" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when RXFF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_CR1_disabled" description="USART control register 1 [alternate] " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="UE" description="USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
        <Enum name="B_0x1" description="USART enabled" start="0x1" />
      </BitField>
      <BitField name="UESM" description="USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode. " start="0x1" />
      </BitField>
      <BitField name="RE" description="Receiver enable This bit enables the receiver. It is set and cleared by software." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
      </BitField>
      <BitField name="TE" description="Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to ‘1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
      </BitField>
      <BitField name="IDLEIE" description="IDLE interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXNEIE" description="Receive data register not empty This bit is set and cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="Transmission complete interrupt enable This bit is set and cleared by software." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TC = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TXEIE" description="Transmit data register empty This bit is set and cleared by software." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PEIE" description="PE interrupt enable This bit is set and cleared by software." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever PE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PS" description="Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Even parity" start="0x0" />
        <Enum name="B_0x1" description="Odd parity" start="0x1" />
      </BitField>
      <BitField name="PCE" description="Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
      </BitField>
      <BitField name="WAKE" description="Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Idle line" start="0x0" />
        <Enum name="B_0x1" description="Address mark" start="0x1" />
      </BitField>
      <BitField name="M0" description="Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)." start="12" size="1" access="Read/Write" />
      <BitField name="MME" description="Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver in active mode permanently" start="0x0" />
        <Enum name="B_0x1" description="Receiver can switch between Mute mode and active mode. " start="0x1" />
      </BitField>
      <BitField name="CMIE" description="Character match interrupt enable This bit is set and cleared by software." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="OVER8" description="Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
      </BitField>
      <BitField name="DEDT" description="Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="16" size="5" access="Read/Write" />
      <BitField name="DEAT" description="Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="21" size="5" access="Read/Write" />
      <BitField name="RTOIE" description="Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="EOBIE" description="End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="M1" description="Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported." start="28" size="1" access="Read/Write" />
      <BitField name="FIFOEN" description="FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes." start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_CR2" description="USART control register 2 " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SLVEN" description="Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
      </BitField>
      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
      </BitField>
      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
      </BitField>
      <BitField name="LBDL" description="LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
      </BitField>
      <BitField name="LBDIE" description="LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="LBCL" description="Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
      </BitField>
      <BitField name="CPHA" description="Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
      </BitField>
      <BitField name="CPOL" description="Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
      </BitField>
      <BitField name="CLKEN" description="Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
      </BitField>
      <BitField name="STOP" description="stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
      </BitField>
      <BitField name="LINEN" description="LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
      </BitField>
      <BitField name="SWAP" description="Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. " start="0x1" />
      </BitField>
      <BitField name="RXINV" description="RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark) " start="0x0" />
        <Enum name="B_0x1" description="RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle). " start="0x1" />
      </BitField>
      <BitField name="TXINV" description="TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark) " start="0x0" />
        <Enum name="B_0x1" description="TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle). " start="0x1" />
      </BitField>
      <BitField name="DATAINV" description="Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L) " start="0x0" />
        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted." start="0x1" />
      </BitField>
      <BitField name="MSBFIRST" description="Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit. " start="0x0" />
        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit. " start="0x1" />
      </BitField>
      <BitField name="ABREN" description="Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Auto baud rate detection is disabled. " start="0x0" />
        <Enum name="B_0x1" description="Auto baud rate detection is enabled. " start="0x1" />
      </BitField>
      <BitField name="ABRMOD" description="Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ." start="21" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate. " start="0x0" />
        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)" start="0x1" />
        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
      </BitField>
      <BitField name="RTOEN" description="Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver timeout feature disabled. " start="0x0" />
        <Enum name="B_0x1" description="Receiver timeout feature enabled. " start="0x1" />
      </BitField>
      <BitField name="ADD" description="Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)." start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="USART_CR3" description="USART control register 3 " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EIE" description="Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="IREN" description="IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
      </BitField>
      <BitField name="IRLP" description="IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Normal mode" start="0x0" />
        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
      </BitField>
      <BitField name="HDSEL" description="Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Half duplex mode is not selected" start="0x0" />
        <Enum name="B_0x1" description="Half duplex mode is selected " start="0x1" />
      </BitField>
      <BitField name="NACK" description="Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
      </BitField>
      <BitField name="SCEN" description="Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Smartcard Mode disabled" start="0x0" />
        <Enum name="B_0x1" description="Smartcard Mode enabled" start="0x1" />
      </BitField>
      <BitField name="DMAR" description="DMA enable receiver This bit is set/reset by software" start="6" size="1" access="Read/Write">
        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
      </BitField>
      <BitField name="DMAT" description="DMA enable transmitter This bit is set/reset by software" start="7" size="1" access="Read/Write">
        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
      </BitField>
      <BitField name="RTSE" description="RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received." start="0x1" />
      </BitField>
      <BitField name="CTSE" description="CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted." start="0x1" />
      </BitField>
      <BitField name="CTSIE" description="CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="ONEBIT" description="One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
      </BitField>
      <BitField name="OVRDIS" description="Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data" start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data. " start="0x0" />
        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
      </BitField>
      <BitField name="DDRE" description="DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode)." start="0x0" />
        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
      </BitField>
      <BitField name="DEM" description="Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DE function is disabled. " start="0x0" />
        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
      </BitField>
      <BitField name="DEP" description="Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DE signal is active high. " start="0x0" />
        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
      </BitField>
      <BitField name="SCARCNT" description="Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="17" size="3" access="Read/Write">
        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in transmit mode. " start="0x0" />
        <Enum name="B_0x1" description="number of automatic retransmission attempts (before signaling error)" start="0x1" />
        <Enum name="B_0x2" description="number of automatic retransmission attempts (before signaling error)" start="0x2" />
        <Enum name="B_0x3" description="number of automatic retransmission attempts (before signaling error)" start="0x3" />
        <Enum name="B_0x4" description="number of automatic retransmission attempts (before signaling error)" start="0x4" />
        <Enum name="B_0x5" description="number of automatic retransmission attempts (before signaling error)" start="0x5" />
        <Enum name="B_0x6" description="number of automatic retransmission attempts (before signaling error)" start="0x6" />
        <Enum name="B_0x7" description="number of automatic retransmission attempts (before signaling error)" start="0x7" />
      </BitField>
      <BitField name="WUS" description="Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
        <Enum name="B_0x2" description="WUF active on start bit detection" start="0x2" />
        <Enum name="B_0x3" description="WUF active on RXNE/RXFNE. " start="0x3" />
      </BitField>
      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever WUF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable This bit is set and cleared by software." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
      </BitField>
      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="24" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration Remaining combinations: Reserved" start="25" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
      </BitField>
      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable This bit is set and cleared by software." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
      </BitField>
      <BitField name="TXFTCFG" description="TXFIFO threshold configuration Remaining combinations: Reserved" start="29" size="3" access="Read/Write">
        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
      </BitField>
    </Register>
    <Register name="USART_BRR" description="USART baud rate register " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BRR" description="USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="USART_GTPR" description="USART guard time and prescaler register " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PSC" description="Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to ‘0’ when the Smartcard and IrDA modes are not supported. Refer to ." start="0" size="8" access="Read/Write">
        <Enum name="B_0x0" description="Reserved - do not program this value" start="0x0" />
        <Enum name="B_0x1" description="Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)" start="0x1" />
        <Enum name="B_0x2" description="Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)" start="0x2" />
        <Enum name="B_0x3" description="Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)" start="0x3" />
        <Enum name="B_0x1F" description="Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)" start="0x1F" />
        <Enum name="B_0x20" description="Divides the source clock by 32 (IrDA mode)" start="0x20" />
        <Enum name="B_0xFF" description="Divides the source clock by 255 (IrDA mode)" start="0xFF" />
      </BitField>
      <BitField name="GT" description="Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="8" access="Read/Write" />
    </Register>
    <Register name="USART_RTOR" description="USART receiver timeout register " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RTO" description="Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character." start="0" size="24" access="Read/Write" />
      <BitField name="BLEN" description="Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block." start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="USART_RQR" description="USART request register " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ABRRQ" description="Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ." start="0" size="1" access="WriteOnly" />
      <BitField name="SBKRQ" description="Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit." start="1" size="1" access="WriteOnly" />
      <BitField name="MMRQ" description="Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag." start="2" size="1" access="WriteOnly" />
      <BitField name="RXFRQ" description="Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition." start="3" size="1" access="WriteOnly" />
      <BitField name="TXFRQ" description="Transmit data flush request When FIFO mode is disabled, writing ‘1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register." start="4" size="1" access="WriteOnly" />
    </Register>
    <Register name="USART_ISR_enabled" description="USART interrupt and status register [alternate] " start="+0x1c" size="4" reset_value="0x008000C0" reset_mask="0xF0FFFFFF">
      <BitField name="PE" description="Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR." start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No parity error" start="0x0" />
        <Enum name="B_0x1" description="Parity error" start="0x1" />
      </BitField>
      <BitField name="FE" description="Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR." start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
      </BitField>
      <BitField name="NE" description="Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR." start="2" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
      </BitField>
      <BitField name="ORE" description="Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register." start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No overrun error" start="0x0" />
        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
      </BitField>
      <BitField name="IDLE" description="Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set." start="4" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
      </BitField>
      <BitField name="RXFNE" description="RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register." start="5" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Data is not received" start="0x0" />
        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
      </BitField>
      <BitField name="TC" description="Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set." start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete" start="0x1" />
      </BitField>
      <BitField name="TXFNF" description="TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission." start="7" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
      </BitField>
      <BitField name="LBDF" description="LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ." start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
      </BitField>
      <BitField name="CTSIF" description="CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="9" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No change occurred on the nCTS status line" start="0x0" />
        <Enum name="B_0x1" description="A change occurred on the nCTS status line" start="0x1" />
      </BitField>
      <BitField name="CTS" description="CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="10" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="nCTS line set" start="0x0" />
        <Enum name="B_0x1" description="nCTS line reset" start="0x1" />
      </BitField>
      <BitField name="RTOF" description="Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value." start="11" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
      </BitField>
      <BitField name="EOBF" description="End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ." start="12" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
      </BitField>
      <BitField name="UDR" description="SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ." start="13" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No underrun error" start="0x0" />
        <Enum name="B_0x1" description="underrun error" start="0x1" />
      </BitField>
      <BitField name="ABRE" description="Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="14" size="1" access="ReadOnly" />
      <BitField name="ABRF" description="Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="15" size="1" access="ReadOnly" />
      <BitField name="BUSY" description="Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)." start="16" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
        <Enum name="B_0x1" description="Reception on going" start="0x1" />
      </BitField>
      <BitField name="CMF" description="Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register." start="17" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
        <Enum name="B_0x1" description="Character Match detected" start="0x1" />
      </BitField>
      <BitField name="SBKF" description="Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission." start="18" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Break character transmitted" start="0x0" />
        <Enum name="B_0x1" description="Break character requested by setting SBKRQ bit in USART_RQR register" start="0x1" />
      </BitField>
      <BitField name="RWU" description="Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="19" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Receiver in active mode" start="0x0" />
        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
      </BitField>
      <BitField name="WUF" description="Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="20" size="1" access="ReadOnly" />
      <BitField name="TEACK" description="Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period." start="21" size="1" access="ReadOnly" />
      <BitField name="REACK" description="Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="22" size="1" access="ReadOnly" />
      <BitField name="TXFE" description="TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register." start="23" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
      </BitField>
      <BitField name="RXFF" description="RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register." start="24" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
      </BitField>
      <BitField name="TCBGT" description="Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is ‘1’. Refer to on page 1985." start="25" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
      </BitField>
      <BitField name="RXFT" description="RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to ‘101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data." start="26" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
      </BitField>
      <BitField name="TXFT" description="TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register." start="27" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_ISR_disabled" description="USART interrupt and status register [alternate] " start="+0x1c" size="4" reset_value="0x008000C0" reset_mask="0xF0FFFFFF">
      <BitField name="PE" description="Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register." start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No parity error" start="0x0" />
        <Enum name="B_0x1" description="Parity error" start="0x1" />
      </BitField>
      <BitField name="FE" description="Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register." start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
      </BitField>
      <BitField name="NE" description="Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012)." start="2" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
      </BitField>
      <BitField name="ORE" description="Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register." start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No overrun error" start="0x0" />
        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
      </BitField>
      <BitField name="IDLE" description="Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set." start="4" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
      </BitField>
      <BitField name="RXNE" description="Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register." start="5" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Data is not received" start="0x0" />
        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
      </BitField>
      <BitField name="TC" description="Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately." start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete" start="0x1" />
      </BitField>
      <BitField name="TXE" description="Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit = 1 in the USART_CR1 register." start="7" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Data register full" start="0x0" />
        <Enum name="B_0x1" description="Data register not full" start="0x1" />
      </BitField>
      <BitField name="LBDF" description="LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ." start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
      </BitField>
      <BitField name="CTSIF" description="CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="9" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No change occurred on the nCTS status line" start="0x0" />
        <Enum name="B_0x1" description="A change occurred on the nCTS status line" start="0x1" />
      </BitField>
      <BitField name="CTS" description="CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="10" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="nCTS line set" start="0x0" />
        <Enum name="B_0x1" description="nCTS line reset" start="0x1" />
      </BitField>
      <BitField name="RTOF" description="Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value." start="11" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
      </BitField>
      <BitField name="EOBF" description="End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ." start="12" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
      </BitField>
      <BitField name="UDR" description="SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ." start="13" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No underrun error" start="0x0" />
        <Enum name="B_0x1" description="underrun error" start="0x1" />
      </BitField>
      <BitField name="ABRE" description="Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="14" size="1" access="ReadOnly" />
      <BitField name="ABRF" description="Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="15" size="1" access="ReadOnly" />
      <BitField name="BUSY" description="Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)." start="16" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
        <Enum name="B_0x1" description="Reception on going" start="0x1" />
      </BitField>
      <BitField name="CMF" description="Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register." start="17" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
        <Enum name="B_0x1" description="Character Match detected" start="0x1" />
      </BitField>
      <BitField name="SBKF" description="Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission." start="18" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Break character transmitted" start="0x0" />
        <Enum name="B_0x1" description="Break character requested by setting SBKRQ bit in USART_RQR register" start="0x1" />
      </BitField>
      <BitField name="RWU" description="Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="19" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Receiver in active mode" start="0x0" />
        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
      </BitField>
      <BitField name="WUF" description="Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="20" size="1" access="ReadOnly" />
      <BitField name="TEACK" description="Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period." start="21" size="1" access="ReadOnly" />
      <BitField name="REACK" description="Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="22" size="1" access="ReadOnly" />
      <BitField name="TCBGT" description="Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is ‘1’. Refer to on page 1985." start="25" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_ICR" description="USART interrupt flag clear register " start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PECF" description="Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register." start="0" size="1" access="WriteOnly" />
      <BitField name="FECF" description="Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register." start="1" size="1" access="WriteOnly" />
      <BitField name="NECF" description="Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register." start="2" size="1" access="WriteOnly" />
      <BitField name="ORECF" description="Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register." start="3" size="1" access="WriteOnly" />
      <BitField name="IDLECF" description="Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register." start="4" size="1" access="WriteOnly" />
      <BitField name="TXFECF" description="TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register." start="5" size="1" access="WriteOnly" />
      <BitField name="TCCF" description="Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register." start="6" size="1" access="WriteOnly" />
      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register." start="7" size="1" access="WriteOnly" />
      <BitField name="LBDCF" description="LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="1" access="WriteOnly" />
      <BitField name="CTSCF" description="CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="9" size="1" access="WriteOnly" />
      <BitField name="RTOCF" description="Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="11" size="1" access="WriteOnly" />
      <BitField name="EOBCF" description="End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="12" size="1" access="WriteOnly" />
      <BitField name="UDRCF" description="SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to" start="13" size="1" access="WriteOnly" />
      <BitField name="CMCF" description="Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register." start="17" size="1" access="WriteOnly" />
      <BitField name="WUCF" description="Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="20" size="1" access="WriteOnly" />
    </Register>
    <Register name="USART_RDR" description="USART receive data register " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RDR" description="Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit." start="0" size="9" access="ReadOnly" />
    </Register>
    <Register name="USART_TDR" description="USART transmit data register " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TDR" description="Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1." start="0" size="9" access="Read/Write" />
    </Register>
    <Register name="USART_PRESC" description="USART prescaler register " start="+0x2c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PRESCALER" description="Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256." start="0" size="4" access="Read/Write">
        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="USART2" description="USART register block" start="0x40004400">
    <Register name="USART_CR1_enabled" description="USART control register 1 [alternate] " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="UE" description="USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
        <Enum name="B_0x1" description="USART enabled" start="0x1" />
      </BitField>
      <BitField name="UESM" description="USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode. " start="0x1" />
      </BitField>
      <BitField name="RE" description="Receiver enable This bit enables the receiver. It is set and cleared by software." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
      </BitField>
      <BitField name="TE" description="Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to ‘1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
      </BitField>
      <BitField name="IDLEIE" description="IDLE interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXFNEIE" description="RXFIFO not empty interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever ORE = 1 or RXFNE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="Transmission complete interrupt enable This bit is set and cleared by software." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TC = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TXFNFIE" description="TXFIFO not full interrupt enable This bit is set and cleared by software." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TXFNF =1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PEIE" description="PE interrupt enable This bit is set and cleared by software." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever PE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PS" description="Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Even parity" start="0x0" />
        <Enum name="B_0x1" description="Odd parity" start="0x1" />
      </BitField>
      <BitField name="PCE" description="Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
      </BitField>
      <BitField name="WAKE" description="Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Idle line" start="0x0" />
        <Enum name="B_0x1" description="Address mark" start="0x1" />
      </BitField>
      <BitField name="M0" description="Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)." start="12" size="1" access="Read/Write" />
      <BitField name="MME" description="Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver in active mode permanently" start="0x0" />
        <Enum name="B_0x1" description="Receiver can switch between Mute mode and active mode. " start="0x1" />
      </BitField>
      <BitField name="CMIE" description="Character match interrupt enable This bit is set and cleared by software." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="OVER8" description="Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
      </BitField>
      <BitField name="DEDT" description="Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="16" size="5" access="Read/Write" />
      <BitField name="DEAT" description="Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="21" size="5" access="Read/Write" />
      <BitField name="RTOIE" description="Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="EOBIE" description="End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="M1" description="Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported." start="28" size="1" access="Read/Write" />
      <BitField name="FIFOEN" description="FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes." start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
      </BitField>
      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable This bit is set and cleared by software." start="30" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when TXFE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable This bit is set and cleared by software." start="31" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when RXFF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_CR1_disabled" description="USART control register 1 [alternate] " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="UE" description="USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART prescaler and outputs disabled, low-power mode" start="0x0" />
        <Enum name="B_0x1" description="USART enabled" start="0x1" />
      </BitField>
      <BitField name="UESM" description="USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="USART not able to wake up the MCU from low-power mode." start="0x0" />
        <Enum name="B_0x1" description="USART able to wake up the MCU from low-power mode. " start="0x1" />
      </BitField>
      <BitField name="RE" description="Receiver enable This bit enables the receiver. It is set and cleared by software." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver is disabled" start="0x0" />
        <Enum name="B_0x1" description="Receiver is enabled and begins searching for a start bit" start="0x1" />
      </BitField>
      <BitField name="TE" description="Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to ‘1’. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Transmitter is disabled" start="0x0" />
        <Enum name="B_0x1" description="Transmitter is enabled" start="0x1" />
      </BitField>
      <BitField name="IDLEIE" description="IDLE interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever IDLE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXNEIE" description="Receive data register not empty This bit is set and cleared by software." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever ORE = 1 or RXNE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TCIE" description="Transmission complete interrupt enable This bit is set and cleared by software." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TC = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TXEIE" description="Transmit data register empty This bit is set and cleared by software." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TXE =1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PEIE" description="PE interrupt enable This bit is set and cleared by software." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever PE = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="PS" description="Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Even parity" start="0x0" />
        <Enum name="B_0x1" description="Odd parity" start="0x1" />
      </BitField>
      <BitField name="PCE" description="Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Parity control disabled" start="0x0" />
        <Enum name="B_0x1" description="Parity control enabled" start="0x1" />
      </BitField>
      <BitField name="WAKE" description="Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Idle line" start="0x0" />
        <Enum name="B_0x1" description="Address mark" start="0x1" />
      </BitField>
      <BitField name="M0" description="Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)." start="12" size="1" access="Read/Write" />
      <BitField name="MME" description="Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver in active mode permanently" start="0x0" />
        <Enum name="B_0x1" description="Receiver can switch between Mute mode and active mode. " start="0x1" />
      </BitField>
      <BitField name="CMIE" description="Character match interrupt enable This bit is set and cleared by software." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the CMF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="OVER8" description="Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Oversampling by 16" start="0x0" />
        <Enum name="B_0x1" description="Oversampling by 8" start="0x1" />
      </BitField>
      <BitField name="DEDT" description="Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="16" size="5" access="Read/Write" />
      <BitField name="DEAT" description="Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="21" size="5" access="Read/Write" />
      <BitField name="RTOIE" description="Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ." start="26" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the RTOF bit is set in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="EOBIE" description="End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="27" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when the EOBF flag is set in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="M1" description="Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = ‘00’: 1 start bit, 8 Data bits, n Stop bit M[1:0] = ‘01’: 1 start bit, 9 Data bits, n Stop bit M[1:0] = ‘10’: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported." start="28" size="1" access="Read/Write" />
      <BitField name="FIFOEN" description="FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes." start="29" size="1" access="Read/Write">
        <Enum name="B_0x0" description="FIFO mode is disabled." start="0x0" />
        <Enum name="B_0x1" description="FIFO mode is enabled." start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_CR2" description="USART control register 2 " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="SLVEN" description="Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Slave mode disabled." start="0x0" />
        <Enum name="B_0x1" description="Slave mode enabled." start="0x1" />
      </BitField>
      <BitField name="DIS_NSS" description="When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="SPI slave selection depends on NSS input pin." start="0x0" />
        <Enum name="B_0x1" description="SPI slave is always selected and NSS input pin is ignored." start="0x1" />
      </BitField>
      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="4-bit address detection" start="0x0" />
        <Enum name="B_0x1" description="7-bit address detection (in 8-bit data mode)" start="0x1" />
      </BitField>
      <BitField name="LBDL" description="LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="10-bit break detection" start="0x0" />
        <Enum name="B_0x1" description="11-bit break detection" start="0x1" />
      </BitField>
      <BitField name="LBDIE" description="LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="6" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
        <Enum name="B_0x1" description="An interrupt is generated whenever LBDF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="LBCL" description="Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The clock pulse of the last data bit is not output to the CK pin" start="0x0" />
        <Enum name="B_0x1" description="The clock pulse of the last data bit is output to the CK pin" start="0x1" />
      </BitField>
      <BitField name="CPHA" description="Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="The first clock transition is the first data capture edge" start="0x0" />
        <Enum name="B_0x1" description="The second clock transition is the first data capture edge" start="0x1" />
      </BitField>
      <BitField name="CPOL" description="Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Steady low value on CK pin outside transmission window" start="0x0" />
        <Enum name="B_0x1" description="Steady high value on CK pin outside transmission window" start="0x1" />
      </BitField>
      <BitField name="CLKEN" description="Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1" start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CK pin disabled" start="0x0" />
        <Enum name="B_0x1" description="CK pin enabled" start="0x1" />
      </BitField>
      <BitField name="STOP" description="stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)." start="12" size="2" access="Read/Write">
        <Enum name="B_0x0" description="1 stop bit" start="0x0" />
        <Enum name="B_0x1" description="0.5 stop bit." start="0x1" />
        <Enum name="B_0x2" description="2 stop bits" start="0x2" />
        <Enum name="B_0x3" description="1.5 stop bits" start="0x3" />
      </BitField>
      <BitField name="LINEN" description="LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="LIN mode disabled" start="0x0" />
        <Enum name="B_0x1" description="LIN mode enabled" start="0x1" />
      </BitField>
      <BitField name="SWAP" description="Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TX/RX pins are used as defined in standard pinout" start="0x0" />
        <Enum name="B_0x1" description="The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. " start="0x1" />
      </BitField>
      <BitField name="RXINV" description="RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)." start="16" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark) " start="0x0" />
        <Enum name="B_0x1" description="RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle). " start="0x1" />
      </BitField>
      <BitField name="TXINV" description="TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)." start="17" size="1" access="Read/Write">
        <Enum name="B_0x0" description="TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark) " start="0x0" />
        <Enum name="B_0x1" description="TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle). " start="0x1" />
      </BitField>
      <BitField name="DATAINV" description="Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="18" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L) " start="0x0" />
        <Enum name="B_0x1" description="Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted." start="0x1" />
      </BitField>
      <BitField name="MSBFIRST" description="Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)." start="19" size="1" access="Read/Write">
        <Enum name="B_0x0" description="data is transmitted/received with data bit 0 first, following the start bit. " start="0x0" />
        <Enum name="B_0x1" description="data is transmitted/received with the MSB (bit 7/8) first, following the start bit. " start="0x1" />
      </BitField>
      <BitField name="ABREN" description="Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ." start="20" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Auto baud rate detection is disabled. " start="0x0" />
        <Enum name="B_0x1" description="Auto baud rate detection is enabled. " start="0x1" />
      </BitField>
      <BitField name="ABRMOD" description="Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ." start="21" size="2" access="Read/Write">
        <Enum name="B_0x0" description="Measurement of the start bit is used to detect the baud rate. " start="0x0" />
        <Enum name="B_0x1" description="Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)" start="0x1" />
        <Enum name="B_0x2" description="0x7F frame detection." start="0x2" />
        <Enum name="B_0x3" description="0x55 frame detection" start="0x3" />
      </BitField>
      <BitField name="RTOEN" description="Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Receiver timeout feature disabled. " start="0x0" />
        <Enum name="B_0x1" description="Receiver timeout feature enabled. " start="0x1" />
      </BitField>
      <BitField name="ADD" description="Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)." start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="USART_CR3" description="USART control register 3 " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EIE" description="Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)." start="0" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register." start="0x1" />
      </BitField>
      <BitField name="IREN" description="IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="1" size="1" access="Read/Write">
        <Enum name="B_0x0" description="IrDA disabled" start="0x0" />
        <Enum name="B_0x1" description="IrDA enabled" start="0x1" />
      </BitField>
      <BitField name="IRLP" description="IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="2" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Normal mode" start="0x0" />
        <Enum name="B_0x1" description="Low-power mode" start="0x1" />
      </BitField>
      <BitField name="HDSEL" description="Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)." start="3" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Half duplex mode is not selected" start="0x0" />
        <Enum name="B_0x1" description="Half duplex mode is selected " start="0x1" />
      </BitField>
      <BitField name="NACK" description="Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="4" size="1" access="Read/Write">
        <Enum name="B_0x0" description="NACK transmission in case of parity error is disabled" start="0x0" />
        <Enum name="B_0x1" description="NACK transmission during parity error is enabled" start="0x1" />
      </BitField>
      <BitField name="SCEN" description="Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="5" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Smartcard Mode disabled" start="0x0" />
        <Enum name="B_0x1" description="Smartcard Mode enabled" start="0x1" />
      </BitField>
      <BitField name="DMAR" description="DMA enable receiver This bit is set/reset by software" start="6" size="1" access="Read/Write">
        <Enum name="B_0x1" description="DMA mode is enabled for reception" start="0x1" />
        <Enum name="B_0x0" description="DMA mode is disabled for reception" start="0x0" />
      </BitField>
      <BitField name="DMAT" description="DMA enable transmitter This bit is set/reset by software" start="7" size="1" access="Read/Write">
        <Enum name="B_0x1" description="DMA mode is enabled for transmission" start="0x1" />
        <Enum name="B_0x0" description="DMA mode is disabled for transmission" start="0x0" />
      </BitField>
      <BitField name="RTSE" description="RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="1" access="Read/Write">
        <Enum name="B_0x0" description="RTS hardware flow control disabled" start="0x0" />
        <Enum name="B_0x1" description="RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received." start="0x1" />
      </BitField>
      <BitField name="CTSE" description="CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="9" size="1" access="Read/Write">
        <Enum name="B_0x0" description="CTS hardware flow control disabled" start="0x0" />
        <Enum name="B_0x1" description="CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted." start="0x1" />
      </BitField>
      <BitField name="CTSIE" description="CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="10" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt is inhibited" start="0x0" />
        <Enum name="B_0x1" description="An interrupt is generated whenever CTSIF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="ONEBIT" description="One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)." start="11" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Three sample bit method" start="0x0" />
        <Enum name="B_0x1" description="One sample bit method" start="0x1" />
      </BitField>
      <BitField name="OVRDIS" description="Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data" start="12" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Overrun Error Flag, ORE, is set when received data is not read before receiving new data. " start="0x0" />
        <Enum name="B_0x1" description="Overrun functionality is disabled. If new data is received while the RXNE flag is still set" start="0x1" />
      </BitField>
      <BitField name="DDRE" description="DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error." start="13" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode)." start="0x0" />
        <Enum name="B_0x1" description="DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag." start="0x1" />
      </BitField>
      <BitField name="DEM" description="Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ." start="14" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DE function is disabled. " start="0x0" />
        <Enum name="B_0x1" description="DE function is enabled. The DE signal is output on the RTS pin." start="0x1" />
      </BitField>
      <BitField name="DEP" description="Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="15" size="1" access="Read/Write">
        <Enum name="B_0x0" description="DE signal is active high. " start="0x0" />
        <Enum name="B_0x1" description="DE signal is active low." start="0x1" />
      </BitField>
      <BitField name="SCARCNT" description="Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="17" size="3" access="Read/Write">
        <Enum name="B_0x0" description="retransmission disabled - No automatic retransmission in transmit mode. " start="0x0" />
        <Enum name="B_0x1" description="number of automatic retransmission attempts (before signaling error)" start="0x1" />
        <Enum name="B_0x2" description="number of automatic retransmission attempts (before signaling error)" start="0x2" />
        <Enum name="B_0x3" description="number of automatic retransmission attempts (before signaling error)" start="0x3" />
        <Enum name="B_0x4" description="number of automatic retransmission attempts (before signaling error)" start="0x4" />
        <Enum name="B_0x5" description="number of automatic retransmission attempts (before signaling error)" start="0x5" />
        <Enum name="B_0x6" description="number of automatic retransmission attempts (before signaling error)" start="0x6" />
        <Enum name="B_0x7" description="number of automatic retransmission attempts (before signaling error)" start="0x7" />
      </BitField>
      <BitField name="WUS" description="Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="20" size="2" access="Read/Write">
        <Enum name="B_0x0" description="WUF active on address match (as defined by ADD[7:0] and ADDM7)" start="0x0" />
        <Enum name="B_0x2" description="WUF active on start bit detection" start="0x2" />
        <Enum name="B_0x3" description="WUF active on RXNE/RXFNE. " start="0x3" />
      </BitField>
      <BitField name="WUFIE" description="Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="22" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever WUF = 1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable This bit is set and cleared by software." start="23" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG." start="0x1" />
      </BitField>
      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="24" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated whenever TCBGT=1 in the USART_ISR register" start="0x1" />
      </BitField>
      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration Remaining combinations: Reserved" start="25" size="3" access="Read/Write">
        <Enum name="B_0x0" description="Receive FIFO reaches 1/8 of its depth" start="0x0" />
        <Enum name="B_0x1" description="Receive FIFO reaches 1/4 of its depth" start="0x1" />
        <Enum name="B_0x2" description="Receive FIFO reaches 1/2 of its depth" start="0x2" />
        <Enum name="B_0x3" description="Receive FIFO reaches 3/4 of its depth" start="0x3" />
        <Enum name="B_0x4" description="Receive FIFO reaches 7/8 of its depth" start="0x4" />
        <Enum name="B_0x5" description="Receive FIFO becomes full" start="0x5" />
      </BitField>
      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable This bit is set and cleared by software." start="28" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Interrupt inhibited" start="0x0" />
        <Enum name="B_0x1" description="USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG." start="0x1" />
      </BitField>
      <BitField name="TXFTCFG" description="TXFIFO threshold configuration Remaining combinations: Reserved" start="29" size="3" access="Read/Write">
        <Enum name="B_0x0" description="TXFIFO reaches 1/8 of its depth" start="0x0" />
        <Enum name="B_0x1" description="TXFIFO reaches 1/4 of its depth" start="0x1" />
        <Enum name="B_0x2" description="TXFIFO reaches 1/2 of its depth" start="0x2" />
        <Enum name="B_0x3" description="TXFIFO reaches 3/4 of its depth" start="0x3" />
        <Enum name="B_0x4" description="TXFIFO reaches 7/8 of its depth" start="0x4" />
        <Enum name="B_0x5" description="TXFIFO becomes empty" start="0x5" />
      </BitField>
    </Register>
    <Register name="USART_BRR" description="USART baud rate register " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="BRR" description="USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared." start="0" size="16" access="Read/Write" />
    </Register>
    <Register name="USART_GTPR" description="USART guard time and prescaler register " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PSC" description="Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to ‘0’ when the Smartcard and IrDA modes are not supported. Refer to ." start="0" size="8" access="Read/Write">
        <Enum name="B_0x0" description="Reserved - do not program this value" start="0x0" />
        <Enum name="B_0x1" description="Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)" start="0x1" />
        <Enum name="B_0x2" description="Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)" start="0x2" />
        <Enum name="B_0x3" description="Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)" start="0x3" />
        <Enum name="B_0x1F" description="Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)" start="0x1F" />
        <Enum name="B_0x20" description="Divides the source clock by 32 (IrDA mode)" start="0x20" />
        <Enum name="B_0xFF" description="Divides the source clock by 255 (IrDA mode)" start="0xFF" />
      </BitField>
      <BitField name="GT" description="Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="8" access="Read/Write" />
    </Register>
    <Register name="USART_RTOR" description="USART receiver timeout register " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RTO" description="Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character." start="0" size="24" access="Read/Write" />
      <BitField name="BLEN" description="Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block." start="24" size="8" access="Read/Write" />
    </Register>
    <Register name="USART_RQR" description="USART request register " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="ABRRQ" description="Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ." start="0" size="1" access="WriteOnly" />
      <BitField name="SBKRQ" description="Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit." start="1" size="1" access="WriteOnly" />
      <BitField name="MMRQ" description="Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag." start="2" size="1" access="WriteOnly" />
      <BitField name="RXFRQ" description="Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition." start="3" size="1" access="WriteOnly" />
      <BitField name="TXFRQ" description="Transmit data flush request When FIFO mode is disabled, writing ‘1’ to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register." start="4" size="1" access="WriteOnly" />
    </Register>
    <Register name="USART_ISR_enabled" description="USART interrupt and status register [alternate] " start="+0x1c" size="4" reset_value="0x008000C0" reset_mask="0xF0FFFFFF">
      <BitField name="PE" description="Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR." start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No parity error" start="0x0" />
        <Enum name="B_0x1" description="Parity error" start="0x1" />
      </BitField>
      <BitField name="FE" description="Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR." start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
      </BitField>
      <BitField name="NE" description="Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR." start="2" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
      </BitField>
      <BitField name="ORE" description="Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register." start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No overrun error" start="0x0" />
        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
      </BitField>
      <BitField name="IDLE" description="Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set." start="4" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
      </BitField>
      <BitField name="RXFNE" description="RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register." start="5" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Data is not received" start="0x0" />
        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
      </BitField>
      <BitField name="TC" description="Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set." start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete" start="0x1" />
      </BitField>
      <BitField name="TXFNF" description="TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission." start="7" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmit FIFO is full" start="0x0" />
        <Enum name="B_0x1" description="Transmit FIFO is not full" start="0x1" />
      </BitField>
      <BitField name="LBDF" description="LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ." start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
      </BitField>
      <BitField name="CTSIF" description="CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="9" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No change occurred on the nCTS status line" start="0x0" />
        <Enum name="B_0x1" description="A change occurred on the nCTS status line" start="0x1" />
      </BitField>
      <BitField name="CTS" description="CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="10" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="nCTS line set" start="0x0" />
        <Enum name="B_0x1" description="nCTS line reset" start="0x1" />
      </BitField>
      <BitField name="RTOF" description="Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value." start="11" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
      </BitField>
      <BitField name="EOBF" description="End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ." start="12" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
      </BitField>
      <BitField name="UDR" description="SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ." start="13" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No underrun error" start="0x0" />
        <Enum name="B_0x1" description="underrun error" start="0x1" />
      </BitField>
      <BitField name="ABRE" description="Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="14" size="1" access="ReadOnly" />
      <BitField name="ABRF" description="Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="15" size="1" access="ReadOnly" />
      <BitField name="BUSY" description="Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)." start="16" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
        <Enum name="B_0x1" description="Reception on going" start="0x1" />
      </BitField>
      <BitField name="CMF" description="Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register." start="17" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
        <Enum name="B_0x1" description="Character Match detected" start="0x1" />
      </BitField>
      <BitField name="SBKF" description="Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission." start="18" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Break character transmitted" start="0x0" />
        <Enum name="B_0x1" description="Break character requested by setting SBKRQ bit in USART_RQR register" start="0x1" />
      </BitField>
      <BitField name="RWU" description="Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="19" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Receiver in active mode" start="0x0" />
        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
      </BitField>
      <BitField name="WUF" description="Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="20" size="1" access="ReadOnly" />
      <BitField name="TEACK" description="Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period." start="21" size="1" access="ReadOnly" />
      <BitField name="REACK" description="Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="22" size="1" access="ReadOnly" />
      <BitField name="TXFE" description="TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register." start="23" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="TXFIFO not empty." start="0x0" />
        <Enum name="B_0x1" description="TXFIFO empty." start="0x1" />
      </BitField>
      <BitField name="RXFF" description="RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register." start="24" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="RXFIFO not full." start="0x0" />
        <Enum name="B_0x1" description="RXFIFO Full." start="0x1" />
      </BitField>
      <BitField name="TCBGT" description="Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is ‘1’. Refer to on page 1985." start="25" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
      </BitField>
      <BitField name="RXFT" description="RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to ‘101’, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data." start="26" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Receive FIFO does not reach the programmed threshold." start="0x0" />
        <Enum name="B_0x1" description="Receive FIFO reached the programmed threshold." start="0x1" />
      </BitField>
      <BitField name="TXFT" description="TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register." start="27" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="TXFIFO does not reach the programmed threshold." start="0x0" />
        <Enum name="B_0x1" description="TXFIFO reached the programmed threshold." start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_ISR_disabled" description="USART interrupt and status register [alternate] " start="+0x1c" size="4" reset_value="0x008000C0" reset_mask="0xF0FFFFFF">
      <BitField name="PE" description="Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register." start="0" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No parity error" start="0x0" />
        <Enum name="B_0x1" description="Parity error" start="0x1" />
      </BitField>
      <BitField name="FE" description="Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register." start="1" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Framing error is detected" start="0x0" />
        <Enum name="B_0x1" description="Framing error or break character is detected" start="0x1" />
      </BitField>
      <BitField name="NE" description="Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012)." start="2" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No noise is detected" start="0x0" />
        <Enum name="B_0x1" description="Noise is detected" start="0x1" />
      </BitField>
      <BitField name="ORE" description="Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register." start="3" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No overrun error" start="0x0" />
        <Enum name="B_0x1" description="Overrun error is detected" start="0x1" />
      </BitField>
      <BitField name="IDLE" description="Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set." start="4" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Idle line is detected" start="0x0" />
        <Enum name="B_0x1" description="Idle line is detected" start="0x1" />
      </BitField>
      <BitField name="RXNE" description="Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register." start="5" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Data is not received" start="0x0" />
        <Enum name="B_0x1" description="Received data is ready to be read." start="0x1" />
      </BitField>
      <BitField name="TC" description="Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately." start="6" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete" start="0x1" />
      </BitField>
      <BitField name="TXE" description="Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit = 1 in the USART_CR1 register." start="7" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Data register full" start="0x0" />
        <Enum name="B_0x1" description="Data register not full" start="0x1" />
      </BitField>
      <BitField name="LBDF" description="LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ." start="8" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="LIN Break not detected" start="0x0" />
        <Enum name="B_0x1" description="LIN break detected" start="0x1" />
      </BitField>
      <BitField name="CTSIF" description="CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="9" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No change occurred on the nCTS status line" start="0x0" />
        <Enum name="B_0x1" description="A change occurred on the nCTS status line" start="0x1" />
      </BitField>
      <BitField name="CTS" description="CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value." start="10" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="nCTS line set" start="0x0" />
        <Enum name="B_0x1" description="nCTS line reset" start="0x1" />
      </BitField>
      <BitField name="RTOF" description="Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value." start="11" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Timeout value not reached" start="0x0" />
        <Enum name="B_0x1" description="Timeout value reached without any data reception" start="0x1" />
      </BitField>
      <BitField name="EOBF" description="End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ." start="12" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="End of Block not reached" start="0x0" />
        <Enum name="B_0x1" description="End of Block (number of characters) reached" start="0x1" />
      </BitField>
      <BitField name="UDR" description="SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ." start="13" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No underrun error" start="0x0" />
        <Enum name="B_0x1" description="underrun error" start="0x1" />
      </BitField>
      <BitField name="ABRE" description="Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="14" size="1" access="ReadOnly" />
      <BitField name="ABRF" description="Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value." start="15" size="1" access="ReadOnly" />
      <BitField name="BUSY" description="Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)." start="16" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="USART is idle (no reception)" start="0x0" />
        <Enum name="B_0x1" description="Reception on going" start="0x1" />
      </BitField>
      <BitField name="CMF" description="Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register." start="17" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="No Character match detected" start="0x0" />
        <Enum name="B_0x1" description="Character Match detected" start="0x1" />
      </BitField>
      <BitField name="SBKF" description="Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission." start="18" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Break character transmitted" start="0x0" />
        <Enum name="B_0x1" description="Break character requested by setting SBKRQ bit in USART_RQR register" start="0x1" />
      </BitField>
      <BitField name="RWU" description="Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="19" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Receiver in active mode" start="0x0" />
        <Enum name="B_0x1" description="Receiver in Mute mode" start="0x1" />
      </BitField>
      <BitField name="WUF" description="Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="20" size="1" access="ReadOnly" />
      <BitField name="TEACK" description="Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period." start="21" size="1" access="ReadOnly" />
      <BitField name="REACK" description="Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ." start="22" size="1" access="ReadOnly" />
      <BitField name="TCBGT" description="Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is ‘1’. Refer to on page 1985." start="25" size="1" access="ReadOnly">
        <Enum name="B_0x0" description="Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)" start="0x0" />
        <Enum name="B_0x1" description="Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)." start="0x1" />
      </BitField>
    </Register>
    <Register name="USART_ICR" description="USART interrupt flag clear register " start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PECF" description="Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register." start="0" size="1" access="WriteOnly" />
      <BitField name="FECF" description="Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register." start="1" size="1" access="WriteOnly" />
      <BitField name="NECF" description="Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register." start="2" size="1" access="WriteOnly" />
      <BitField name="ORECF" description="Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register." start="3" size="1" access="WriteOnly" />
      <BitField name="IDLECF" description="Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register." start="4" size="1" access="WriteOnly" />
      <BitField name="TXFECF" description="TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register." start="5" size="1" access="WriteOnly" />
      <BitField name="TCCF" description="Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register." start="6" size="1" access="WriteOnly" />
      <BitField name="TCBGTCF" description="Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register." start="7" size="1" access="WriteOnly" />
      <BitField name="LBDCF" description="LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="8" size="1" access="WriteOnly" />
      <BitField name="CTSCF" description="CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ." start="9" size="1" access="WriteOnly" />
      <BitField name="RTOCF" description="Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="11" size="1" access="WriteOnly" />
      <BitField name="EOBCF" description="End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ." start="12" size="1" access="WriteOnly" />
      <BitField name="UDRCF" description="SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to" start="13" size="1" access="WriteOnly" />
      <BitField name="CMCF" description="Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register." start="17" size="1" access="WriteOnly" />
      <BitField name="WUCF" description="Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985." start="20" size="1" access="WriteOnly" />
    </Register>
    <Register name="USART_RDR" description="USART receive data register " start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="RDR" description="Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit." start="0" size="9" access="ReadOnly" />
    </Register>
    <Register name="USART_TDR" description="USART transmit data register " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="TDR" description="Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1." start="0" size="9" access="Read/Write" />
    </Register>
    <Register name="USART_PRESC" description="USART prescaler register " start="+0x2c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="PRESCALER" description="Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256." start="0" size="4" access="Read/Write">
        <Enum name="B_0x0" description="input clock not divided" start="0x0" />
        <Enum name="B_0x1" description="input clock divided by 2" start="0x1" />
        <Enum name="B_0x2" description="input clock divided by 4" start="0x2" />
        <Enum name="B_0x3" description="input clock divided by 6" start="0x3" />
        <Enum name="B_0x4" description="input clock divided by 8" start="0x4" />
        <Enum name="B_0x5" description="input clock divided by 10" start="0x5" />
        <Enum name="B_0x6" description="input clock divided by 12" start="0x6" />
        <Enum name="B_0x7" description="input clock divided by 16" start="0x7" />
        <Enum name="B_0x8" description="input clock divided by 32" start="0x8" />
        <Enum name="B_0x9" description="input clock divided by 64" start="0x9" />
        <Enum name="B_0xA" description="input clock divided by 128" start="0xA" />
        <Enum name="B_0xB" description="input clock divided by 256" start="0xB" />
      </BitField>
    </Register>
  </RegisterGroup>
  <RegisterGroup name="WWDG" description="WWDG register block" start="0x40002C00">
    <Register name="WWDG_CR" description="WWDG control register " start="+0x0" size="4" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
      <BitField name="T" description="7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)." start="0" size="7" access="Read/Write" />
      <BitField name="WDGA" description="Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset." start="7" size="1" access="Read/Write">
        <Enum name="B_0x0" description="Watchdog disabled" start="0x0" />
        <Enum name="B_0x1" description="Watchdog enabled" start="0x1" />
      </BitField>
    </Register>
    <Register name="WWDG_CFR" description="WWDG configuration register " start="+0x4" size="4" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
      <BitField name="W" description="7-bit window value These bits contain the window value to be compared with the down-counter." start="0" size="7" access="Read/Write" />
      <BitField name="EWI" description="Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset." start="9" size="1" access="Read/Write" />
      <BitField name="WDGTB" description="Timer base The timebase of the prescaler can be modified as follows:" start="11" size="3" access="Read/Write">
        <Enum name="B_0x0" description="CK counter clock (PCLK div 4096) div 1" start="0x0" />
        <Enum name="B_0x1" description="CK counter clock (PCLK div 4096) div 2" start="0x1" />
        <Enum name="B_0x2" description="CK counter clock (PCLK div 4096) div 4" start="0x2" />
        <Enum name="B_0x3" description="CK counter clock (PCLK div 4096) div 8" start="0x3" />
        <Enum name="B_0x4" description="CK counter clock (PCLK div 4096) div 16" start="0x4" />
        <Enum name="B_0x5" description="CK counter clock (PCLK div 4096) div 32" start="0x5" />
        <Enum name="B_0x6" description="CK counter clock (PCLK div 4096) div 64" start="0x6" />
        <Enum name="B_0x7" description="CK counter clock (PCLK div 4096) div 128" start="0x7" />
      </BitField>
    </Register>
    <Register name="WWDG_SR" description="WWDG status register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField name="EWIF" description="Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’. Writing ‘1’ has no effect. This bit is also set if the interrupt is not enabled." start="0" size="1" access="Read/Write" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="NVIC" start="0xE000E000" description="Nested Vectored Interrupt Controller">
    <Register start="+0x100" size="0" name="ISER0" access="Read/Write" description="Interrupt Set-Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="0" size="1" name="WWDG" />
      <BitField start="2" size="1" name="RTC" />
      <BitField start="3" size="1" name="FLASH" />
      <BitField start="4" size="1" name="RCC" />
      <BitField start="5" size="1" name="EXTI0_1" />
      <BitField start="6" size="1" name="EXTI2_3" />
      <BitField start="7" size="1" name="EXTI4_15" />
      <BitField start="9" size="1" name="DMA1_Channel1" />
      <BitField start="10" size="1" name="DMA1_Channel2_3" />
      <BitField start="11" size="1" name="DMAMUX1" />
      <BitField start="12" size="1" name="ADC1" />
      <BitField start="13" size="1" name="TIM1_BRK_UP_TRG_COM" />
      <BitField start="14" size="1" name="TIM1_CC" />
      <BitField start="16" size="1" name="TIM3" />
      <BitField start="19" size="1" name="TIM14" />
      <BitField start="21" size="1" name="TIM16" />
      <BitField start="22" size="1" name="TIM17" />
      <BitField start="23" size="1" name="I2C1" />
      <BitField start="25" size="1" name="SPI1" />
      <BitField start="27" size="1" name="USART1" />
      <BitField start="28" size="1" name="USART2" />
    </Register>
    <Register start="+0x180" size="0" name="ICER0" access="Read/Write" description="Interrupt Clear-Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="0" size="1" name="WWDG" />
      <BitField start="2" size="1" name="RTC" />
      <BitField start="3" size="1" name="FLASH" />
      <BitField start="4" size="1" name="RCC" />
      <BitField start="5" size="1" name="EXTI0_1" />
      <BitField start="6" size="1" name="EXTI2_3" />
      <BitField start="7" size="1" name="EXTI4_15" />
      <BitField start="9" size="1" name="DMA1_Channel1" />
      <BitField start="10" size="1" name="DMA1_Channel2_3" />
      <BitField start="11" size="1" name="DMAMUX1" />
      <BitField start="12" size="1" name="ADC1" />
      <BitField start="13" size="1" name="TIM1_BRK_UP_TRG_COM" />
      <BitField start="14" size="1" name="TIM1_CC" />
      <BitField start="16" size="1" name="TIM3" />
      <BitField start="19" size="1" name="TIM14" />
      <BitField start="21" size="1" name="TIM16" />
      <BitField start="22" size="1" name="TIM17" />
      <BitField start="23" size="1" name="I2C1" />
      <BitField start="25" size="1" name="SPI1" />
      <BitField start="27" size="1" name="USART1" />
      <BitField start="28" size="1" name="USART2" />
    </Register>
    <Register start="+0x200" size="0" name="ISPR0" access="Read/Write" description="Interrupt Set-Pending Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="0" size="1" name="WWDG" />
      <BitField start="2" size="1" name="RTC" />
      <BitField start="3" size="1" name="FLASH" />
      <BitField start="4" size="1" name="RCC" />
      <BitField start="5" size="1" name="EXTI0_1" />
      <BitField start="6" size="1" name="EXTI2_3" />
      <BitField start="7" size="1" name="EXTI4_15" />
      <BitField start="9" size="1" name="DMA1_Channel1" />
      <BitField start="10" size="1" name="DMA1_Channel2_3" />
      <BitField start="11" size="1" name="DMAMUX1" />
      <BitField start="12" size="1" name="ADC1" />
      <BitField start="13" size="1" name="TIM1_BRK_UP_TRG_COM" />
      <BitField start="14" size="1" name="TIM1_CC" />
      <BitField start="16" size="1" name="TIM3" />
      <BitField start="19" size="1" name="TIM14" />
      <BitField start="21" size="1" name="TIM16" />
      <BitField start="22" size="1" name="TIM17" />
      <BitField start="23" size="1" name="I2C1" />
      <BitField start="25" size="1" name="SPI1" />
      <BitField start="27" size="1" name="USART1" />
      <BitField start="28" size="1" name="USART2" />
    </Register>
    <Register start="+0x280" size="0" name="ICPR0" access="Read/Write" description="Interrupt Clear-Pending Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="0" size="1" name="WWDG" />
      <BitField start="2" size="1" name="RTC" />
      <BitField start="3" size="1" name="FLASH" />
      <BitField start="4" size="1" name="RCC" />
      <BitField start="5" size="1" name="EXTI0_1" />
      <BitField start="6" size="1" name="EXTI2_3" />
      <BitField start="7" size="1" name="EXTI4_15" />
      <BitField start="9" size="1" name="DMA1_Channel1" />
      <BitField start="10" size="1" name="DMA1_Channel2_3" />
      <BitField start="11" size="1" name="DMAMUX1" />
      <BitField start="12" size="1" name="ADC1" />
      <BitField start="13" size="1" name="TIM1_BRK_UP_TRG_COM" />
      <BitField start="14" size="1" name="TIM1_CC" />
      <BitField start="16" size="1" name="TIM3" />
      <BitField start="19" size="1" name="TIM14" />
      <BitField start="21" size="1" name="TIM16" />
      <BitField start="22" size="1" name="TIM17" />
      <BitField start="23" size="1" name="I2C1" />
      <BitField start="25" size="1" name="SPI1" />
      <BitField start="27" size="1" name="USART1" />
      <BitField start="28" size="1" name="USART2" />
    </Register>
    <Register start="+0x300" size="0" name="IABR0" access="ReadOnly" description="Interrupt Active Bit Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="0" size="1" name="WWDG" />
      <BitField start="2" size="1" name="RTC" />
      <BitField start="3" size="1" name="FLASH" />
      <BitField start="4" size="1" name="RCC" />
      <BitField start="5" size="1" name="EXTI0_1" />
      <BitField start="6" size="1" name="EXTI2_3" />
      <BitField start="7" size="1" name="EXTI4_15" />
      <BitField start="9" size="1" name="DMA1_Channel1" />
      <BitField start="10" size="1" name="DMA1_Channel2_3" />
      <BitField start="11" size="1" name="DMAMUX1" />
      <BitField start="12" size="1" name="ADC1" />
      <BitField start="13" size="1" name="TIM1_BRK_UP_TRG_COM" />
      <BitField start="14" size="1" name="TIM1_CC" />
      <BitField start="16" size="1" name="TIM3" />
      <BitField start="19" size="1" name="TIM14" />
      <BitField start="21" size="1" name="TIM16" />
      <BitField start="22" size="1" name="TIM17" />
      <BitField start="23" size="1" name="I2C1" />
      <BitField start="25" size="1" name="SPI1" />
      <BitField start="27" size="1" name="USART1" />
      <BitField start="28" size="1" name="USART2" />
    </Register>
    <Register start="+0x400" size="0" name="IPR0" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="4" size="4" name="WWDG" />
      <BitField start="20" size="4" name="RTC" />
      <BitField start="28" size="4" name="FLASH" />
    </Register>
    <Register start="+0x404" size="0" name="IPR1" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="4" size="4" name="RCC" />
      <BitField start="12" size="4" name="EXTI0_1" />
      <BitField start="20" size="4" name="EXTI2_3" />
      <BitField start="28" size="4" name="EXTI4_15" />
    </Register>
    <Register start="+0x408" size="0" name="IPR2" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="12" size="4" name="DMA1_Channel1" />
      <BitField start="20" size="4" name="DMA1_Channel2_3" />
      <BitField start="28" size="4" name="DMAMUX1" />
    </Register>
    <Register start="+0x40c" size="0" name="IPR3" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="4" size="4" name="ADC1" />
      <BitField start="12" size="4" name="TIM1_BRK_UP_TRG_COM" />
      <BitField start="20" size="4" name="TIM1_CC" />
    </Register>
    <Register start="+0x410" size="0" name="IPR4" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="4" size="4" name="TIM3" />
      <BitField start="28" size="4" name="TIM14" />
    </Register>
    <Register start="+0x414" size="0" name="IPR5" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="12" size="4" name="TIM16" />
      <BitField start="20" size="4" name="TIM17" />
      <BitField start="28" size="4" name="I2C1" />
    </Register>
    <Register start="+0x418" size="0" name="IPR6" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="12" size="4" name="SPI1" />
      <BitField start="28" size="4" name="USART1" />
    </Register>
    <Register start="+0x41c" size="0" name="IPR7" access="Read/Write" description="Interrupt Priority Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
      <BitField start="4" size="4" name="USART2" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
      <BitField start="0" size="1" name="ENABLE" description="Enable SysTick Timer" />
      <BitField start="1" size="1" name="TICKINT" description="Tick Interrupt Enable" />
      <BitField start="2" size="1" name="CLKSOURCE" description="Timer Clock Source" />
      <BitField start="16" size="1" name="COUNTFLAG" description="Counter Flag" />
    </Register>
    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
      <BitField start="0" size="24" name="RELOAD" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
    </Register>
    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
      <BitField start="0" size="24" name="CURRENT" description="The current value of the SysTick counter" />
    </Register>
    <Register name="SYST_CALIB" start="0xE000E01C" description="SysTick Calibration Value Register" access="ReadOnly">
      <BitField start="0" size="24" name="TENMS" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
      <BitField start="30" size="1" name="SKEW" description="Indicates whether the TENMS value is exact" />
      <BitField start="31" size="1" name="NOREF" description="Indicates whether the device provides a reference clock to the processor" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="SCB" start="0xE000E000" description="System Control Block">
    <Register name="CPUID" start="0xE000ED00" description="CPUID Register" access="ReadOnly">
      <BitField start="0" size="4" name="REVISION" description="Revision Number" />
      <BitField start="4" size="12" name="PARTNO" description="Part Number" />
      <BitField start="20" size="4" name="VARIANT" description="Variant Number" />
      <BitField start="24" size="8" name="IMPLEMENTER" description="Implementer Code" />
    </Register>
    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
      <BitField start="0" size="9" name="VECTACTIVE" description="Contains the active exception number" />
      <BitField start="12" size="9" name="VECTPENDING" description="Indicates the exception number of the highest priority pending enabled exception" />
      <BitField start="22" size="1" name="ISRPENDING" description="Interrupt pending flag" />
      <BitField start="23" size="1" name="ISRPREEMPT" />
      <BitField start="25" size="1" name="PENDSTCLR" description="SysTick exception clear-pending bit" />
      <BitField start="26" size="1" name="PENDSTSET" description="SysTick exception set-pending bit" />
      <BitField start="27" size="1" name="PENDSVCLR" description="PendSV clear-pending bit" />
      <BitField start="28" size="1" name="PENDSVSET" description="PendSV set-pending bit" />
      <BitField start="31" size="1" name="NMIPENDSET" description="NMI set-pending bit" />
    </Register>
    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
      <BitField start="7" size="25" name="TBLOFF" description="Vector table base offset field" />
    </Register>
    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
      <BitField start="1" size="1" name="VECTCLRACTIVE" />
      <BitField start="2" size="1" name="SYSRESETREQ" description="System reset request bit" />
      <BitField start="15" size="1" name="ENDIANESS" description="Data endianness bit" />
      <BitField start="16" size="16" name="VECTKEY" description="Register key" />
    </Register>
    <Register name="SCR" start="0xE000ED10" description="System Control Register">
      <BitField start="1" size="1" name="SLEEPONEXIT" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
      <BitField start="2" size="1" name="SLEEPDEEP" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
      <BitField start="4" size="1" name="SEVONPEND" description="Send event on pending bit" />
    </Register>
    <Register name="CCR" start="0xE000ED14" description="Configuration and Control Register">
      <BitField start="3" size="1" name="UNALIGN_TRP" description="Enables unaligned access traps" />
      <BitField start="9" size="1" name="STKALIGN" description="Indicates stack alignment on exception entry" />
    </Register>
    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
      <BitField start="28" size="4" name="PRI_11(SVCall)" description="Priority of system handler 11 (SVCall)" />
    </Register>
    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
      <BitField start="20" size="4" name="PRI_14(PendSV)" description="Priority of system handler 14 (PendSV)" />
      <BitField start="28" size="4" name="PRI_15(SysTick)" description="Priority of system handler 15 (SysTick)" />
    </Register>
    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
      <BitField start="15" size="1" name="SVCALLPENDED" description="SVCall Pending Bit" />
    </Register>
    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
      <BitField start="0" size="1" name="HALTED" />
      <BitField start="1" size="1" name="BKPT" />
      <BitField start="2" size="1" name="DWTTRAP" />
      <BitField start="3" size="1" name="VCATCH" />
      <BitField start="4" size="1" name="EXTERNAL" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="FPU" start="0xE000EF34" description="Floating Point Unit">
    <Register name="FPCCR" start="0xE000EF34" description="Floating-point Context Control Register">
      <BitField start="0" size="1" name="LSPACT" description="Lazy state preservation active" />
      <BitField start="1" size="1" name="USER" description="User privilege" />
      <BitField start="3" size="1" name="THREAD" description="Thread Mode" />
      <BitField start="4" size="1" name="HFRDY" description="HardFault ready" />
      <BitField start="5" size="1" name="MMRDY" description="MemManage ready" />
      <BitField start="6" size="1" name="BFRDY" description="BusFault ready" />
      <BitField start="8" size="1" name="MONRDY" description="DebugMonitor ready" />
      <BitField start="30" size="1" name="LSPEN" description="Lazy state preservation enable" />
      <BitField start="31" size="1" name="ASPEN" description="Automatic state preservation enable" />
    </Register>
    <Register name="FPCAR" start="0xE000EF38" description="Floating-point Context Address Register">
      <BitField start="3" size="29" name="ADDRESS" description="The location of the unpopulated floating-point register space allocated on an exception stack frame" />
    </Register>
    <Register name="FPDSCR" start="0xE000EF3C" description="Floating-point Default Status Control Register">
      <BitField start="22" size="2" name="RMode" description="Rounding Mode control field" />
      <BitField start="24" size="1" name="FZ" description="Flush-to-zero mode control bit" />
      <BitField start="25" size="1" name="DN" description="Default NaN mode control bit" />
      <BitField start="26" size="1" name="AHP" description="Alternative half-precision control bit" />
    </Register>
  </RegisterGroup>
  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
    <Register name="MPU_TYPE" start="0xE000ED90" description="MPU Type Register" access="ReadOnly">
      <BitField start="0" size="1" name="SEPARATE" description="Support for unified or separate instruction and date memory maps" />
      <BitField start="8" size="8" name="DREGION" description="Number of supported MPU data regions" />
      <BitField start="16" size="8" name="IREGION" description="Number of supported MPU instruction regions" />
    </Register>
    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
      <BitField start="0" size="1" name="ENABLE" description="Enable MPU" />
      <BitField start="1" size="1" name="HFNMIENA" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
      <BitField start="2" size="1" name="PRIVDEFENA" description="Enables privileged software access to the default memory map" />
    </Register>
    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
      <BitField start="0" size="8" name="REGION" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
    </Register>
    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
      <BitField start="0" size="4" name="REGION" description="MPU region field" />
      <BitField start="4" size="1" name="VALID" description="MPU Region Number valid bit" />
      <BitField start="5" size="27" name="ADDR" description="Region base address field" />
    </Register>
    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
      <BitField start="0" size="1" name="ENABLE" description="Region enable bit" />
      <BitField start="1" size="5" name="SIZE" description="MPU protection region size" />
      <BitField start="8" size="8" name="SRD" description="Subregion disable bits" />
      <BitField start="16" size="1" name="B" description="Memory access attribute" />
      <BitField start="17" size="1" name="C" description="Memory access attribute" />
      <BitField start="18" size="1" name="S" description="Shareable bit" />
      <BitField start="19" size="3" name="TEX" description="Memory access attribute" />
      <BitField start="24" size="3" name="AP" description="Access permission field" />
      <BitField start="28" size="1" name="XN" description="Instruction access disable bit" />
    </Register>
  </RegisterGroup>
</Processor>
