source: trunk/firmware_v2/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal.h

Last change on this file was 17, checked in by f.jahn, 4 months ago
File size: 46.7 KB
Line 
1/**
2 ******************************************************************************
3 * @file stm32c0xx_hal.h
4 * @author MCD Application Team
5 * @brief This file contains all the functions prototypes for the HAL
6 * module driver.
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2022 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32C0xx_HAL_H
22#define STM32C0xx_HAL_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32c0xx_ll_system.h"
30#include "stm32c0xx_hal_conf.h"
31
32/** @addtogroup STM32C0xx_HAL_Driver
33 * @{
34 */
35
36/** @defgroup HAL HAL
37 * @{
38 */
39
40/* Exported types ------------------------------------------------------------*/
41/* Exported constants --------------------------------------------------------*/
42
43/** @defgroup HAL_Exported_Constants HAL Exported Constants
44 * @{
45 */
46
47/** @defgroup HAL_TICK_FREQ Tick Frequency
48 * @{
49 */
50
51typedef enum
52{
53 HAL_TICK_FREQ_10HZ = 100U,
54 HAL_TICK_FREQ_100HZ = 10U,
55 HAL_TICK_FREQ_1KHZ = 1U,
56 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
57} HAL_TickFreqTypeDef;
58
59/**
60 * @}
61 */
62
63/** @defgroup HAL_BIND_CFG Bind Pin config
64 * @{
65 */
66
67#if (DEV_ID == 0x443UL)
68#define HAL_BIND_SO8_PIN1_PB7 LL_PINMUX_SO8_PIN1_PB7 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */
69#define HAL_BIND_SO8_PIN1_PC14 LL_PINMUX_SO8_PIN1_PC14 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */
70#define HAL_BIND_SO8_PIN4_PF2 LL_PINMUX_SO8_PIN4_PF2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */
71#define HAL_BIND_SO8_PIN4_PA0 LL_PINMUX_SO8_PIN4_PA0 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */
72#define HAL_BIND_SO8_PIN4_PA1 LL_PINMUX_SO8_PIN4_PA1 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */
73#define HAL_BIND_SO8_PIN4_PA2 LL_PINMUX_SO8_PIN4_PA2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */
74#define HAL_BIND_SO8_PIN5_PA8 LL_PINMUX_SO8_PIN5_PA8 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8*/
75#define HAL_BIND_SO8_PIN5_PA11 LL_PINMUX_SO8_PIN5_PA11 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */
76#define HAL_BIND_SO8_PIN8_PA14 LL_PINMUX_SO8_PIN8_PA14 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */
77#define HAL_BIND_SO8_PIN8_PB6 LL_PINMUX_SO8_PIN8_PB6 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */
78#define HAL_BIND_SO8_PIN8_PC15 LL_PINMUX_SO8_PIN8_PC15 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */
79#define HAL_BIND_WLCSP12_PINE2_PA7 LL_PINMUX_WLCSP12_PINE2_PA7 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */
80#define HAL_BIND_WLCSP12_PINE2_PA12 LL_PINMUX_WLCSP12_PINE2_PA12 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12*/
81#define HAL_BIND_WLCSP12_PINF1_PA3 LL_PINMUX_WLCSP12_PINF1_PA3 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3 */
82#define HAL_BIND_WLCSP12_PINF1_PA4 LL_PINMUX_WLCSP12_PINF1_PA4 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */
83#define HAL_BIND_WLCSP12_PINF1_PA5 LL_PINMUX_WLCSP12_PINF1_PA5 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */
84#define HAL_BIND_WLCSP12_PINF1_PA6 LL_PINMUX_WLCSP12_PINF1_PA6 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */
85#elif (DEV_ID == 0x453UL)
86#define HAL_BIND_WLCSP14_PINF2_PA1 LL_PINMUX_WLCSP14_PINF2_PA1 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */
87#define HAL_BIND_WLCSP14_PINF2_PA2 LL_PINMUX_WLCSP14_PINF2_PA2 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */
88#define HAL_BIND_WLCSP14_PING3_PF2 LL_PINMUX_WLCSP14_PING3_PF2 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */
89#define HAL_BIND_WLCSP14_PING3_PA0 LL_PINMUX_WLCSP14_PING3_PA0 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */
90#define HAL_BIND_WLCSP14_PINJ1_PA8 LL_PINMUX_WLCSP14_PINJ1_PA8 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */
91#define HAL_BIND_WLCSP14_PINJ1_PA11 LL_PINMUX_WLCSP14_PINJ1_PA11 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */
92#define HAL_BIND_WLCSP14_PINH2_PA5 LL_PINMUX_WLCSP14_PINH2_PA5 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */
93#define HAL_BIND_WLCSP14_PINH2_PA6 LL_PINMUX_WLCSP14_PINH2_PA6 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */
94#define HAL_BIND_WLCSP14_PING1_PA7 LL_PINMUX_WLCSP14_PING1_PA7 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */
95#define HAL_BIND_WLCSP14_PING1_PA12 LL_PINMUX_WLCSP14_PING1_PA12 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */
96#define HAL_BIND_WLCSP14_PINJ3_PA3 LL_PINMUX_WLCSP14_PINJ3_PA3 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */
97#define HAL_BIND_WLCSP14_PINJ3_PA4 LL_PINMUX_WLCSP14_PINJ3_PA4 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */
98#elif (DEV_ID == 0x493UL)
99#define HAL_BIND_WLCSP19_PINH3_PF2 LL_PINMUX_WLCSP19_PINH3_PF2 /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PF2 */
100#define HAL_BIND_WLCSP19_PINH3_PA0 LL_PINMUX_WLCSP19_PINH3_PA0 /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PA0 */
101#define HAL_BIND_WLCSP19_PINB1_PA14 LL_PINMUX_WLCSP19_PINB1_PA14 /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA14 */
102#define HAL_BIND_WLCSP19_PINB1_PA15 LL_PINMUX_WLCSP19_PINB1_PA15 /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA15 */
103#define HAL_BIND_TSSOP20_PIN19_PA14 LL_PINMUX_TSSOP20_PIN19_PA14
104#define HAL_BIND_TSSOP20_PIN19_PA15 LL_PINMUX_TSSOP20_PIN19_PA15
105#define HAL_BIND_TSSOP20_PIN20_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB6 */
106#define HAL_BIND_TSSOP20_PIN20_PB3 LL_PINMUX_TSSOP20_PIN20_PB3 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB3 */
107#define HAL_BIND_TSSOP20_PIN20_PB4 LL_PINMUX_TSSOP20_PIN20_PB4 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB4 */
108#define HAL_BIND_TSSOP20_PIN20_PB5 LL_PINMUX_TSSOP20_PIN20_PB5 /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB5 */
109#define HAL_BIND_WLCSP19_PINB3_PB LL_PINMUX_WLCSP19_PINB3_PB7 /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB7 */
110#define HAL_BIND_WLCSP19_PINB3_PB8 LL_PINMUX_WLCSP19_PINB3_PB8 /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB8 */
111#define HAL_BIND_TSSOP20_PIN1_PB7 LL_PINMUX_TSSOP20_PIN1_PB7 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB7 */
112#define HAL_BIND_TSSOP20_PIN1_PB8 LL_PINMUX_TSSOP20_PIN1_PB8 /*!< STM32C071 TSSOP20 package, Pin1 assigned to GPIO PB8 */
113#elif (DEV_ID == 0x44CUL)
114#define HAL_BIND_WLCSP15_PINH3_PF2 LL_PINMUX_WLCSP15_PINH3_PF2 /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PF2 */
115#define HAL_BIND_WLCSP15_PINH3_PA0 LL_PINMUX_WLCSP15_PINH3_PA0 /*!< STM32C051 WLCSP15 package, PinH3 assigned to GPIO PA0 */
116#define HAL_BIND_WLCSP15_PING2_PA1 LL_PINMUX_WLCSP15_PING2_PA1 /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA1 */
117#define HAL_BIND_WLCSP15_PING2_PA2 LL_PINMUX_WLCSP15_PING2_PA2 /*!< STM32C051 WLCSP15 package, PinG2 assigned to GPIO PA2 */
118#define HAL_BIND_WLCSP15_PINK3_PA3 LL_PINMUX_WLCSP15_PINK3_PA3 /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA3 */
119#define HAL_BIND_WLCSP15_PINK3_PA4 LL_PINMUX_WLCSP15_PINK3_PA4 /*!< STM32C051 WLCSP15 package, PinK3 assigned to GPIO PA4 */
120#define HAL_BIND_WLCSP15_PINJ2_PA5 LL_PINMUX_WLCSP15_PINJ2_PA5 /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA5 */
121#define HAL_BIND_WLCSP15_PINJ2_PA6 LL_PINMUX_WLCSP15_PINJ2_PA6 /*!< STM32C051 WLCSP15 package, PinJ2 assigned to GPIO PA6 */
122#define HAL_BIND_WLCSP15_PINH1_PA7 LL_PINMUX_WLCSP15_PINH1_PA7 /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA7 */
123#define HAL_BIND_WLCSP15_PINH1_PA12 LL_PINMUX_WLCSP15_PINH1_PA12 /*!< STM32C051 WLCSP15 package, PinH1 assigned to GPIO PA12 */
124#define HAL_BIND_WLCSP15_PINE2_PA14 LL_PINMUX_WLCSP15_PINE2_PA14 /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA14 */
125#define HAL_BIND_WLCSP15_PINE2_PA15 LL_PINMUX_WLCSP15_PINE2_PA15 /*!< STM32C051 WLCSP15 package, PinE2 assigned to GPIO PA15 */
126#define HAL_BIND_WLCSP15_PINB1_PA3 LL_PINMUX_WLCSP15_PINB1_PA3 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA3 */
127#define HAL_BIND_WLCSP15_PINB1_PA4 LL_PINMUX_WLCSP15_PINB1_PA4 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA4 */
128#define HAL_BIND_WLCSP15_PINB1_PA5 LL_PINMUX_WLCSP15_PINB1_PA5 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA5 */
129#define HAL_BIND_WLCSP15_PINB1_PA6 LL_PINMUX_WLCSP15_PINB1_PA6 /*!< STM32C051 WLCSP15 package, PinB1 assigned to GPIO PA6 */
130#define HAL_BIND_WLCSP15_PINA2_PB7 LL_PINMUX_WLCSP15_PINA2_PB7 /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB7 */
131#define HAL_BIND_WLCSP15_PINA2_PB8 LL_PINMUX_WLCSP15_PINA2_PB8 /*!< STM32C051 WLCSP15 package, PinA2 assigned to GPIO PB8 */
132#elif (DEV_ID == 0x44DUL)
133#define HAL_BIND_TSSOP20_PIN19_PA14 LL_PINMUX_TSSOP20_PIN19_PA14 /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA14 */
134#define HAL_BIND_TSSOP20_PIN19_PA15 LL_PINMUX_TSSOP20_PIN19_PA15 /*!< STM32C091/92 TSSOP20 package, Pin19 assigned to GPIO PA15 */
135#define HAL_BIND_TSSOP20_PIN15_PA8 LL_PINMUX_TSSOP20_PIN15_PA8 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PA8 */
136#define HAL_BIND_TSSOP20_PIN15_PB0 LL_PINMUX_TSSOP20_PIN15_PB0 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB0 */
137#define HAL_BIND_TSSOP20_PIN15_PB1 LL_PINMUX_TSSOP20_PIN15_PB1 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB1 */
138#define HAL_BIND_TSSOP20_PIN15_PB2 LL_PINMUX_TSSOP20_PIN15_PB2 /*!< STM32C091/92 TSSOP20 package, Pin15 assigned to GPIO PB2 */
139#define HAL_BIND_TSSOP20_PIN20_PB6 LL_PINMUX_TSSOP20_PIN20_PB6 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB6 */
140#define HAL_BIND_TSSOP20_PIN20_PB3 LL_PINMUX_TSSOP20_PIN20_PB3 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB3 */
141#define HAL_BIND_TSSOP20_PIN20_PB4 LL_PINMUX_TSSOP20_PIN20_PB4 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB4 */
142#define HAL_BIND_TSSOP20_PIN20_PB5 LL_PINMUX_TSSOP20_PIN20_PB5 /*!< STM32C091/92 TSSOP20 package, Pin20 assigned to GPIO PB5 */
143#define HAL_BIND_WLCSP24_PINA3_PB5 LL_PINMUX_WLCSP24_PINA3_PB5 /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB5 */
144#define HAL_BIND_WLCSP24_PINA3_PB3 LL_PINMUX_WLCSP24_PINA3_PB3 /*!< STM32C091/92 WLCSP24 package, PinA3 assigned to GPIO PB3 */
145#define HAL_BIND_WLCSP24_PINB4_PB7 LL_PINMUX_WLCSP24_PINB4_PB7 /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB7 */
146#define HAL_BIND_WLCSP24_PINB4_PB8 LL_PINMUX_WLCSP24_PINB4_PB8 /*!< STM32C091/92 WLCSP24 package, PinB4 assigned to GPIO PB8 */
147#endif /* DEV_ID == 0x443UL */
148
149/**
150 * @}
151 */
152
153/** @defgroup HAL_BIND_SCOURCE Bind Pin Source
154 * @{
155 */
156#if (DEV_ID == 0x443UL)
157#define HAL_BIND_SO8_PIN1 LL_PINMUX_SO8_PIN1 /*!< STM32C011 SO8 package, GPIO Pin1 multiplexer */
158#define HAL_BIND_SO8_PIN4 LL_PINMUX_SO8_PIN4 /*!< STM32C011 SO8 package, GPIO Pin4 multiplexer */
159#define HAL_BIND_SO8_PIN5 LL_PINMUX_SO8_PIN5 /*!< STM32C011 SO8 package, GPIO Pin5 multiplexer */
160#define HAL_BIND_SO8_PIN8 LL_PINMUX_SO8_PIN8 /*!< STM32C011 SO8 package, GPIO Pin8 multiplexer */
161#define HAL_BIND_WLCSP12_PINE2 LL_PINMUX_WLCSP12_PINE2 /*!< STM32C011 WLCSP12 package, GPIO PinE2 multiplexer */
162#define HAL_BIND_WLCSP12_PINF1 LL_PINMUX_WLCSP12_PINF1 /*!< STM32C011 WLCSP12 package, GPIO PinF1 multiplexer */
163#elif (DEV_ID == 0x453UL)
164#define HAL_BIND_WLCSP14_PINF2 LL_PINMUX_WLCSP14_PINF2 /*!< STM32C031 WLCSP14 package, GPIO PinF2 multiplexer */
165#define HAL_BIND_WLCSP14_PING3 LL_PINMUX_WLCSP14_PING3 /*!< STM32C031 WLCSP14 package, GPIO PinG3 multiplexer */
166#define HAL_BIND_WLCSP14_PINJ1 LL_PINMUX_WLCSP14_PINJ1 /*!< STM32C031 WLCSP14 package, GPIO PinJ1 multiplexer */
167#define HAL_BIND_WLCSP14_PINH2 LL_PINMUX_WLCSP14_PINH2 /*!< STM32C031 WLCSP14 package, GPIO PinH2 multiplexer */
168#define HAL_BIND_WLCSP14_PING1 LL_PINMUX_WLCSP14_PING1 /*!< STM32C031 WLCSP14 package, GPIO PinG1 multiplexer */
169#define HAL_BIND_WLCSP14_PINJ3 LL_PINMUX_WLCSP14_PINJ3 /*!< STM32C031 WLCSP14 package, GPIO PinJ3 multiplexer */
170#elif (DEV_ID == 0x493UL)
171#define HAL_BIND_WLCSP19_PINH3 LL_PINMUX_WLCSP19_PINH3 /*!< STM32C071 WLCSP19 package, GPIO PinH3 multiplexer */
172#define HAL_BIND_WLCSP19_PINB1 LL_PINMUX_WLCSP19_PINB1 /*!< STM32C071 WLCSP19 package, GPIO PinB1 multiplexer */
173#define HAL_BIND_TSSOP20_PIN19 LL_PINMUX_TSSOP20_PIN19 /*!< STM32C071 TSSOP20 package, GPIO Pin19 multiplexer */
174#define HAL_BIND_TSSOP20_PIN20 LL_PINMUX_TSSOP20_PIN20 /*!< STM32C071 TSSOP20 package, GPIO Pin20 multiplexer */
175#define HAL_BIND_WLCSP19_PINB3 LL_PINMUX_WLCSP19_PINB3 /*!< STM32C071 WLCSP19 package, GPIO PinB3 multiplexer */
176#define HAL_BIND_TSSOP20_PIN1 LL_PINMUX_TSSOP20_PIN1 /*!< STM32C071 TSSOP20 package, GPIO Pin1 multiplexer */
177#elif (DEV_ID == 0x44CUL)
178#define HAL_BIND_WLCSP15_PINH3 LL_PINMUX_WLCSP15_PINH3 /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */
179#define HAL_BIND_WLCSP15_PING2 LL_PINMUX_WLCSP15_PING2 /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */
180#define HAL_BIND_WLCSP15_PINK3 LL_PINMUX_WLCSP15_PINK3 /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */
181#define HAL_BIND_WLCSP15_PINJ2 LL_PINMUX_WLCSP15_PINJ2 /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */
182#define HAL_BIND_WLCSP15_PINH1 LL_PINMUX_WLCSP15_PINH1 /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */
183#define HAL_BIND_WLCSP15_PINE2 LL_PINMUX_WLCSP15_PINE2 /*!< STM32C051 WLCSP15 package, GPIO PinE2 multiplexer */
184#define HAL_BIND_WLCSP15_PINB1 LL_PINMUX_WLCSP15_PINB1 /*!< STM32C051 WLCSP15 package, GPIO PinB1 multiplexer */
185#define HAL_BIND_WLCSP15_PINA2 LL_PINMUX_WLCSP15_PINA2 /*!< STM32C051 WLCSP15 package, GPIO PinA2 multiplexer */
186#elif (DEV_ID == 0x44DUL)
187#define HAL_BIND_TSSOP20_PIN19 LL_PINMUX_TSSOP20_PIN19 /*!< STM32C051 WLCSP15 package, GPIO PinH3 multiplexer */
188#define HAL_BIND_TSSOP20_PIN15 LL_PINMUX_TSSOP20_PIN15 /*!< STM32C051 WLCSP15 package, GPIO PinG2 multiplexer */
189#define HAL_BIND_TSSOP20_PIN20 LL_PINMUX_TSSOP20_PIN20 /*!< STM32C051 WLCSP15 package, GPIO PinK3 multiplexer */
190#define HAL_BIND_WLCSP24_PINA3 LL_PINMUX_WLCSP24_PINA3 /*!< STM32C051 WLCSP15 package, GPIO PinJ2 multiplexer */
191#define HAL_BIND_WLCSP24_PINB4 LL_PINMUX_WLCSP24_PINB4 /*!< STM32C051 WLCSP15 package, GPIO PinH1 multiplexer */
192#endif /* DEV_ID == 0x443UL */
193/**
194 * @}
195 */
196
197/**
198 * @}
199 */
200
201/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
202 * @{
203 */
204
205/** @defgroup SYSCFG_BootMode Boot Mode
206 * @{
207 */
208#define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */
209#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */
210#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */
211
212/**
213 * @}
214 */
215
216/** @defgroup SYSCFG_Break Break
217 * @{
218 */
219#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/16/17 */
220/**
221 * @}
222 */
223
224/** @defgroup HAL_Pin_remapping Pin remapping
225 * @{
226 */
227#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */
228#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */
229/**
230 * @}
231 */
232
233/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection
234 * @{
235 */
236#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */
237#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */
238#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */
239
240/**
241 * @}
242 */
243
244/** @defgroup HAL_IR_POL_SEL IR output polarity selection
245 * @{
246 */
247#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */
248#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */
249
250/**
251 * @}
252 */
253/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO
254 * @{
255 */
256
257/** @brief Fast mode Plus driving capability on a specific GPIO
258 */
259#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */
260#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */
261#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */
262#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */
263#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */
264#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */
265#define SYSCFG_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast mode Plus on PC14 */
266/**
267 * @}
268 */
269
270/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx
271 * @{
272 */
273
274/** @brief Fast mode Plus driving capability on a specific GPIO
275 */
276#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */
277#if defined(I2C2)
278#define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */
279#endif /* I2C2 */
280/**
281 * @}
282 */
283
284/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
285 * @brief ISR Wrapper
286 * @{
287 */
288#define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */
289#define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */
290#define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */
291#define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */
292#define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */
293#define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */
294#define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */
295#if defined(USB_DRD_FS)
296#define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */
297#endif /* USB */
298#define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */
299#define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */
300#define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */
301#define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */
302#define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */
303#define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */
304#if defined(TIM2)
305#define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */
306#endif /* TIM2 */
307#define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */
308#define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */
309#if defined(TIM15)
310#define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */
311#endif /* TIM15 */
312#define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */
313#define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */
314#define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */
315#if defined(I2C2)
316#define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */
317#endif /* I2C2 */
318#define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */
319#if defined(SPI2)
320#define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */
321#endif /* SPI2 */
322#define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */
323#define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */
324#if defined(USART3)
325#define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */
326#endif /* USART3 */
327#if defined(FDCAN1)
328#define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */
329#define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */
330#endif /* FDCAN1 */
331
332#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_WWDG) /*!< WWDG Interrupt */
333#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC Interrupt */
334#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */
335#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */
336#if defined(CRS)
337#define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */
338#endif /* CRS */
339#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */
340#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */
341#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */
342#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */
343#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */
344#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */
345#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */
346#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */
347#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */
348#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */
349#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */
350#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */
351#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */
352#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */
353#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */
354#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */
355#if defined(USB_DRD_FS)
356#define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */
357#endif /* USB */
358#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */
359#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */
360#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */
361#define HAL_ITLINE_DMAMUX ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX) /*!< DMAMUX Interrupt */
362#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
363#define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */
364#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
365#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
366#define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */
367#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
368#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
369#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */
370#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
371#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
372#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */
373#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
374#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */
375#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */
376#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */
377#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */
378#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */
379#define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */
380#if defined(TIM2)
381#define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2) /*!< TIM2 Interrupt */
382#endif /* TIM2 */
383#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */
384#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */
385#if defined(TIM15)
386#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */
387#endif /* TIM15 */
388#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */
389#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */
390#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt */
391#if defined(I2C2)
392#define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C1 Interrupt */
393#endif /* I2C2 */
394#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */
395#if defined(SPI2)
396#define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE25_SR_SPI2) /*!< SPI1 Interrupt */
397#endif /* SPI2 */
398#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt */
399#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt */
400#if defined(USART3)
401#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 GLB Interrupt */
402#endif /* USART3 */
403#if defined(USART4)
404#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 GLB Interrupt */
405#endif /* USART4 */
406#if defined(FDCAN1)
407#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_FDCAN1_IT0_GLB) /*!< FDCAN1_IT0 GLB Interrupt */
408#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_FDCAN1_IT1_GLB) /*!< FDCAN1_IT1 GLB Interrupt */
409#endif /* FDCAN1 */
410
411/**
412 * @}
413 */
414
415/**
416 * @}
417 */
418
419/* Exported macros -----------------------------------------------------------*/
420/** @defgroup HAL_Exported_Macros HAL Exported Macros
421 * @{
422 */
423
424/** @defgroup DBG_Exported_Macros DBG Exported Macros
425 * @{
426 */
427
428/** @brief Freeze and Unfreeze Peripherals in Debug mode
429 */
430
431#if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
432#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
433#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
434#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */
435
436#if defined(DBG_APB_FZ1_DBG_TIM3_STOP)
437#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
438#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
439#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */
440
441#if defined(DBG_APB_FZ1_DBG_RTC_STOP)
442#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
443#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
444#endif /* DBG_APB_FZ1_DBG_RTC_STOP */
445
446#if defined(DBG_APB_FZ1_DBG_WWDG_STOP)
447#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
448#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
449#endif /* DBG_APB_FZ1_DBG_RTC_STOP */
450
451#if defined(DBG_APB_FZ1_DBG_IWDG_STOP)
452#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
453#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
454#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */
455
456#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
457#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
458#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
459#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */
460
461#if defined(DBG_APB_FZ2_DBG_TIM1_STOP)
462#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
463#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
464#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */
465
466#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
467#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
468#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
469#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
470
471#if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
472#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
473#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
474#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */
475
476#if defined(DBG_APB_FZ2_DBG_TIM16_STOP)
477#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
478#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
479#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */
480
481#if defined(DBG_APB_FZ2_DBG_TIM17_STOP)
482#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
483#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
484#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */
485
486/**
487 * @}
488 */
489
490/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
491 * @{
492 */
493
494/**
495 * @brief ISR wrapper check
496 * @note Allow to determine interrupt source per line.
497 */
498#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
499
500/** @brief Main Flash memory mapped at 0x00000000
501 */
502#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
503
504/** @brief System Flash memory mapped at 0x00000000
505 */
506#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
507
508/** @brief Embedded SRAM mapped at 0x00000000
509 */
510#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
511 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0))
512
513/**
514 * @brief Return the boot mode as configured by user.
515 * @retval The boot mode as configured by user. The returned value can be one
516 * of the following values @ref SYSCFG_BootMode
517 */
518#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
519
520/** @brief SYSCFG Break Cortex-M0+ Lockup lock.
521 * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/16/17 Break input
522 * @note The selected configuration is locked and can be unlocked only by system reset.
523 */
524#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
525
526/** @brief Fast-mode Plus driving capability enable/disable macros
527 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
528 */
529#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \
530 do { \
531 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
532 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
533 }while(0U)
534
535#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \
536 do { \
537 assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
538 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
539 }while(0U)
540
541
542/** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
543 * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL
544 */
545#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
546 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
547 SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
548 }while(0U)
549
550#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U)
551
552/** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register
553 * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL
554 */
555#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
556 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
557 SET_BIT(SYSCFG->CFGR1,(__SEL__));\
558 }while(0U)
559
560/**
561 * @brief Return the IROut Polarity mode as configured by user.
562 * @retval The IROut polarity as configured by user. The returned value can be one
563 * of @ref HAL_IR_POL_SEL
564 */
565#define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
566
567/** @brief Break input to TIM1/16/17 capability enable/disable macros
568 * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break
569 */
570#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
571 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
572 }while(0U)
573
574#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
575 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
576 }while(0U)
577/**
578 * @}
579 */
580
581/* Private macros ------------------------------------------------------------*/
582/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
583 * @{
584 */
585
586#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)
587
588#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
589 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
590 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
591
592#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \
593 ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
594
595
596#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PC14) == SYSCFG_FASTMODEPLUS_PC14) || \
597 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
598 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
599 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
600 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
601 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
602 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
603
604#define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \
605 ((RMP) == SYSCFG_REMAP_PA12) || \
606 ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))
607#if (DEV_ID == 0x443UL)
608#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_SO8_PIN1_PB7) || \
609 ((PIN) == HAL_BIND_SO8_PIN1_PC14) || \
610 ((PIN) == HAL_BIND_SO8_PIN4_PF2) || \
611 ((PIN) == HAL_BIND_SO8_PIN4_PA0) || \
612 ((PIN) == HAL_BIND_SO8_PIN4_PA1) || \
613 ((PIN) == HAL_BIND_SO8_PIN4_PA2) || \
614 ((PIN) == HAL_BIND_SO8_PIN5_PA8) || \
615 ((PIN) == HAL_BIND_SO8_PIN5_PA11) || \
616 ((PIN) == HAL_BIND_SO8_PIN8_PA14) || \
617 ((PIN) == HAL_BIND_SO8_PIN8_PB6) || \
618 ((PIN) == HAL_BIND_SO8_PIN8_PC15) || \
619 ((PIN) == HAL_BIND_WLCSP12_PINE2_PA7) || \
620 ((PIN) == HAL_BIND_WLCSP12_PINE2_PA12) || \
621 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA3) || \
622 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA4) || \
623 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA5) || \
624 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA6))
625#elif (DEV_ID == 0x453UL)
626#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_WLCSP14_PINF2_PA1) || \
627 ((PIN) == HAL_BIND_WLCSP14_PINF2_PA2) || \
628 ((PIN) == HAL_BIND_WLCSP14_PING3_PF2) || \
629 ((PIN) == HAL_BIND_WLCSP14_PING3_PA0) || \
630 ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA8) || \
631 ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA11) || \
632 ((PIN) == HAL_BIND_WLCSP14_PINH2_PA5) || \
633 ((PIN) == HAL_BIND_WLCSP14_PINH2_PA6) || \
634 ((PIN) == HAL_BIND_WLCSP14_PING1_PA7) || \
635 ((PIN) == HAL_BIND_WLCSP14_PING1_PA12)|| \
636 ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA3) || \
637 ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA4))
638#elif (DEV_ID == 0x493UL)
639#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_WLCSP19_PINH3_PF2) || \
640 ((PIN) == LL_PINMUX_WLCSP19_PINH3_PA0) || \
641 ((PIN) == LL_PINMUX_WLCSP19_PINB1_PA14) || \
642 ((PIN) == LL_PINMUX_WLCSP19_PINB1_PA15) || \
643 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB6) || \
644 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB3) || \
645 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB4) || \
646 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB5) || \
647 ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB7) || \
648 ((PIN) == LL_PINMUX_WLCSP19_PINB3_PB8))
649#elif (DEV_ID == 0x44CUL)
650#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_WLCSP15_PINH3_PF2) || \
651 ((PIN) == LL_PINMUX_WLCSP15_PINH3_PA0) || \
652 ((PIN) == LL_PINMUX_WLCSP15_PING2_PA1) || \
653 ((PIN) == LL_PINMUX_WLCSP15_PING2_PA2) || \
654 ((PIN) == LL_PINMUX_WLCSP15_PINK3_PA3) || \
655 ((PIN) == LL_PINMUX_WLCSP15_PINK3_PA4) || \
656 ((PIN) == LL_PINMUX_WLCSP15_PINJ2_PA5) || \
657 ((PIN) == LL_PINMUX_WLCSP15_PINJ2_PA6) || \
658 ((PIN) == LL_PINMUX_WLCSP15_PINH1_PA7) || \
659 ((PIN) == LL_PINMUX_WLCSP15_PINH1_PA12) || \
660 ((PIN) == LL_PINMUX_WLCSP15_PINE2_PA14) || \
661 ((PIN) == LL_PINMUX_WLCSP15_PINE2_PA15) || \
662 ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA3) || \
663 ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA4) || \
664 ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA5) || \
665 ((PIN) == LL_PINMUX_WLCSP15_PINB1_PA6) || \
666 ((PIN) == LL_PINMUX_WLCSP15_PINA2_PB7) || \
667 ((PIN) == LL_PINMUX_WLCSP15_PINA2_PB8))
668#elif (DEV_ID == 0x44DUL)
669#define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == LL_PINMUX_TSSOP20_PIN19_PA14) || \
670 ((PIN) == LL_PINMUX_TSSOP20_PIN19_PA15) || \
671 ((PIN) == LL_PINMUX_TSSOP20_PIN15_PA8) || \
672 ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB0) || \
673 ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB1) || \
674 ((PIN) == LL_PINMUX_TSSOP20_PIN15_PB2) || \
675 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB6) || \
676 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB3) || \
677 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB4) || \
678 ((PIN) == LL_PINMUX_TSSOP20_PIN20_PB5) || \
679 ((PIN) == LL_PINMUX_WLCSP24_PINA3_PB5) || \
680 ((PIN) == LL_PINMUX_WLCSP24_PINA3_PB3) || \
681 ((PIN) == LL_PINMUX_WLCSP24_PINB4_PB7) || \
682 ((PIN) == LL_PINMUX_WLCSP24_PINB4_PB8))
683#endif /* DEV_ID == 0x443UL | DEV_ID == 0x453UL | DEV_ID == 0x493UL | DEV_ID == 0x44CUL | DEV_ID == 0x44DUL */
684/**
685 * @}
686 */
687
688/** @defgroup HAL_Private_Macros HAL Private Macros
689 * @{
690 */
691#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
692 ((FREQ) == HAL_TICK_FREQ_100HZ) || \
693 ((FREQ) == HAL_TICK_FREQ_1KHZ))
694/**
695 * @}
696 */
697/* Exported functions --------------------------------------------------------*/
698
699/** @defgroup HAL_Exported_Functions HAL Exported Functions
700 * @{
701 */
702
703/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
704 * @{
705 */
706
707/* Initialization and Configuration functions ******************************/
708HAL_StatusTypeDef HAL_Init(void);
709HAL_StatusTypeDef HAL_DeInit(void);
710void HAL_MspInit(void);
711void HAL_MspDeInit(void);
712HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
713
714/**
715 * @}
716 */
717
718/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
719 * @{
720 */
721
722/* Peripheral Control functions ************************************************/
723void HAL_IncTick(void);
724void HAL_Delay(uint32_t Delay);
725uint32_t HAL_GetTick(void);
726uint32_t HAL_GetTickPrio(void);
727HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
728HAL_TickFreqTypeDef HAL_GetTickFreq(void);
729void HAL_SuspendTick(void);
730void HAL_ResumeTick(void);
731uint32_t HAL_GetHalVersion(void);
732uint32_t HAL_GetREVID(void);
733uint32_t HAL_GetDEVID(void);
734uint32_t HAL_GetUIDw0(void);
735uint32_t HAL_GetUIDw1(void);
736uint32_t HAL_GetUIDw2(void);
737
738/**
739 * @}
740 */
741
742/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions
743 * @{
744 */
745
746/* DBGMCU Peripheral Control functions *****************************************/
747void HAL_DBGMCU_EnableDBGStopMode(void);
748void HAL_DBGMCU_DisableDBGStopMode(void);
749void HAL_DBGMCU_EnableDBGStandbyMode(void);
750void HAL_DBGMCU_DisableDBGStandbyMode(void);
751
752/**
753 * @}
754 */
755
756/* Exported variables ---------------------------------------------------------*/
757/** @addtogroup HAL_Exported_Variables
758 * @{
759 */
760extern __IO uint32_t uwTick;
761extern uint32_t uwTickPrio;
762extern HAL_TickFreqTypeDef uwTickFreq;
763/**
764 * @}
765 */
766
767/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions
768 * @{
769 */
770
771/* SYSCFG Control functions ****************************************************/
772void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
773void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
774void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding);
775uint32_t HAL_SYSCFG_GetPinBinding(uint32_t pin_binding_source);
776/**
777 * @}
778 */
779
780/**
781 * @}
782 */
783
784/**
785 * @}
786 */
787
788/**
789 * @}
790 */
791
792/**
793 * @}
794 */
795#ifdef __cplusplus
796}
797#endif
798
799#endif /* STM32C0xx_HAL_H */
Note: See TracBrowser for help on using the repository browser.