.ALIASES
V_V1            V1(+=N16302 -=0 ) CN @T2.SCHEMATIC1(sch_1):INS14649@SOURCE.VDC.Normal(chips)
X_M1            M1(d=N16585 g=N16298 s=N16302 ) CN @T2.SCHEMATIC1(sch_1):INS14702@BREAKOUT.POWER_NMOS_P.Normal(chips)
C_C1            C1(1=N16660 2=N16585 ) CN @T2.SCHEMATIC1(sch_1):INS14782@ANALOG.C.Normal(chips)
R_R1            R1(1=0 2=N15213 ) CN @T2.SCHEMATIC1(sch_1):INS15169@ANALOG.R.Normal(chips)
R_R2            R2(1=N15213 2=N15205 ) CN @T2.SCHEMATIC1(sch_1):INS15185@ANALOG.R.Normal(chips)
X_U1            U1(A=N16302 C=N16585 CAP=N16660 DGATE=N16298 EN_UVLO=N16703 GND=0 HGATE=N17461 OUT=0 OV=0 PAD=PAD SW=N15205
+VS=N16585 VSNS=N16302 ) CN @T2.SCHEMATIC1(sch_1):INS15735@T2.LM74810-Q1_TRANS_9.Normal(chips)
V_V2            V2(+=N16703 -=0 ) CN @T2.SCHEMATIC1(sch_1):INS16687@SOURCE.VDC.Normal(chips)
R_R3            R3(1=0 2=N16585 ) CN @T2.SCHEMATIC1(sch_1):INS16763@ANALOG.R.Normal(chips)
R_R5            R5(1=0 2=N17461 ) CN @T2.SCHEMATIC1(sch_1):INS17419@ANALOG.R.Normal(chips)
_    _(GND_0=0)
.ENDALIASES