*$ * LM74800-Q1 ***************************************************************************** * (C) Copyright 2020 Texas Instruments Incorporated. All rights reserved. ***************************************************************************** ** This model is designed as an aid for customers of Texas Instruments. ** TI and its licensors and suppliers make no warranties, either expressed ** or implied, with respect to this model, including the warranties of ** merchantability or fitness for a particular purpose. The model is ** provided solely on an "as is" basis. The entire risk as to its quality ** and performance is with the customer ***************************************************************************** * * This model is subject to change without notice. Texas Instruments * Incorporated is not responsible for updating this model. * ***************************************************************************** * ** Released by: Texas Instruments Inc. * Part: LM74800-Q1 * Date: 28APR2020 * Model Type: TRANSIENT * Simulator: PSPICE * Simulator Version: 17.2-2016 S064 * EVM Order Number: LM74700EVM, LM74800EVM-CS * EVM Users Guide: PSIL106, PSIL107 * Datasheet: SNOSD95 –FEBRUARY 2020 * * Model Version:1.00 * * TI Confidential – NDA Restrictions per NDA with ECS ***************************************************************************** * * Updates: * * Final 1.00 * Release to Web. * ***************************************************************************** * * Model Usage Notes: * 1. The following features have been modeled * a. Switched output(in Common Drain) and Load Dump Protection(in commom source) * b. Charge pump behaviour as function of ANODE and DGATE * c. VS POR, EN_UVLO thresholds, Charge pump shutdown, charge pump POR, Anode POR * d. Reverse input protection * e. Over voltage potection * 2. Temperature effects are not modeled. * ***************************************************************************** .SUBCKT LM74800-Q1_TRANS A C CAP DGATE EN_UVLO GND HGATE OUT OV PAD SW VS VSNS V_U4_V14 U4_N166036923 0 150m X_U4_U868 N13182 U4_N71968 U4_N71906 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 X_U4_U864 U4_N16600867 U4_N16623166 ASYMMETRIC_DELAY PARAMS: + RISING_EDGE_DELAY=0.6u VTHRESH=0.5 FALLING_EDGE_DELAY=100n VDD=1 VSS=0 X_U4_U869 N10103 N51846 U4_N16602359 NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 X_U4_U852 U4_N71906 EN_DGATEDRV U4_N16605337 AND2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=500E-3 X_U4_U853 U4_N16602359 EN_DGATEDRV N13056 AND2_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=500E-3 E_U4_ABM2 N13182 0 VALUE { V(ANODE_INT) + -V(CATHOD_INT) } X_U4_U863 U4_REVERSE U4_N16600773 U4_N16600867 AND2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=500E-3 V_U4_V13 U4_N16600773 0 1 X_U4_U871 U4_N16605337 N51846 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 DELAY=100n V_U4_V10 U4_N71968 0 150m X_U4_U870 U4_N72162 N13182 U4_N166036923 U4_REVERSE COMPHYS_BASIC_GEN + PARAMS: VDD=1 VSS=0 VTHRESH=0.5 V_U4_V12 U4_N72162 0 -4.5m X_U4_U873 EN_DGATEDRV U4_N16623102 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 X_U4_U874 U4_N16623166 U4_N16623102 N10103 OR2_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=500E-3 V_U6_V1 U6_N42514 0 1.233 E_U6_E6 U6_OV_INT 0 OV GND 1 V_U6_V2 U6_N42500 0 110m X_U6_U842 U6_OV_INT U6_N42514 U6_N42500 OVP COMPHYS_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 X_U6_S1 EN_OK 0 VSNS SW OVP_VSNS_U6_S1 V_U5_V4 U5_N16549192 0 -1m E_U5_E1 U5_OUT_INT 0 OUT GND 1 X_U5_U5 HGATE CAP d_lm74700 X_U5_U2 EN_DRV U5_OVP_B U5_N16551783 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 X_U5_S9 U5_N16562144 0 OUT 0 HGATE_DRIVER_U5_S9 X_U5_U11 OVP U5_N16543509 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 DELAY=1u G_U5_G1 CAP HGATE U5_HGATE_EN 0 53u X_U5_U843 OUT U5_N16549192 U5_N16549172 U5_N16577297 COMPHYS_BASIC_GEN + PARAMS: VDD=1 VSS=0 VTHRESH=0.5 X_U5_U6 OUT HGATE d_lm74700 X_U5_U10 U5_HGATE_EN U5_N16552507 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 X_U5_U3 U5_N16551783 U5_OUT_SHORT U5_HGATE_EN AND2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=500E-3 V_U5_V3 U5_N16549172 0 0.1m X_U5_U8 U5_N16543509 U5_OVP_B asymmetric_delay PARAMS: + RISING_EDGE_DELAY=5u VTHRESH=0.5 FALLING_EDGE_DELAY=2u VDD=1 VSS=0 X_U5_U12 U5_OUT_SHORT U5_N16562144 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 R_U5_R5 U5_N16566538 U5_OUT_SHORT 1 C_U5_C5 0 U5_OUT_SHORT 1n X_U5_U844 HGATE U5_N16571579 d_lm74700 G_U5_G2 HGATE OUT U5_N16552507 0 260m X_U5_U845 U5_N16577297 U5_N16566538 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=0.5 DELAY=500n V_U5_V5 U5_N16571579 U5_N16573039 11 R_U5_R2 U5_N16573039 U5_OUT_INT 1 C_U5_C1 0 U5_N16573039 1n V_U1_V20 U1_N38512 0 2.38 V_U1_V2 U1_N38424 0 109m E_U1_E8 CATHOD_INT 0 C GND 1 X_U1_U842 U1_EN_INT U1_V2V U1_N38424 EN_OK COMPHYS_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 X_U1_U851 EN_SYS EN_SYSB INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 E_U1_E7 U1_VCAP_INT 0 CAP GND 1 V_U1_V5 U1_N16793140 0 0.736 X_U1_U859 U1_ANODE_REV U1_ANODE_POS INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 V_U1_V7 U1_N379060 0 1.2 G_U1_ABM3I1 VS GND VALUE { IF(V(U1_CP_OK)>0.5, + if(V(U1_ANODE_REV)>0.5,110u,V(U1_IQCP)),3u) } V_U1_V6 U1_N16793130 0 66m X_U1_U830 U1_EN_DGATE_DLY U1_POR U1_CP_POR U1_N38418 AND3_BASIC_GEN + PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 E_U1_E5 U1_VS_INT 0 VS GND 1 V_U1_V4 U1_N37784 0 2.72 X_U1_U846 U1_EN_INT U1_N16793140 U1_N16793130 U1_CP_OK + COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 X_U1_U856 U1_N50226 ANODE_INT U1_ANODE_REV COMP_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=0.5 X_U1_U835 VCP U1_N38620 U1_N379060 U1_CP_POR COMPHYS_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 X_U1_U854 ANODE_INT U1_N38512 U1_N38492 U1_VA_POR COMPHYS_BASIC_GEN + PARAMS: VDD=1 VSS=0 VTHRESH=0.5 X_U1_U843 U1_VS_INT U1_N37784 U1_N37764 U1_POR COMPHYS_BASIC_GEN + PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_U1_E6 U1_EN_INT 0 EN_UVLO GND 1 V_U1_V3 U1_N37764 0 640m V_U1_V15 U1_N38492 0 380m V_U1_V1 U1_V2V 0 1.237 X_U1_U858 U1_N38418 U1_VA_POR EN_DGATEDRV AND2_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=500E-3 V_U1_V9 U1_N38620 0 6.7 G_U1_G1 C 0 U1_ANODE_REV 0 15u E_U1_E9 ANODE_INT 0 A GND 1 R_U1_R1 U1_CP_OK U1_N16836740 1 X_U1_U861 U1_N16836740 U1_N16836190 asymmetric_delay PARAMS: + RISING_EDGE_DELAY=185u VTHRESH=0.5 FALLING_EDGE_DELAY=5.8u VDD=1 VSS=0 V_U1_V21 U1_N50226 0 -1m R_U1_R4 U1_N16836190 U1_EN_DGATE_DLY 1 C_U1_C4 0 U1_EN_DGATE_DLY 1n X_U1_U864 U1_CP_OK U1_POR EN_SYS AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 C_U1_C1 0 U1_N16836740 1n C_U1_C6 0 U1_N16855278 1n G_U1_G2 VS 0 U1_N16848208 0 2.5m C_U1_C7 0 U1_N16855391 1n C_U1_C8 GND VS 1p IC=0 V_U1_V22 U1_N16851556 0 5 E_U1_ABM2 U1_N16854741 0 VALUE { if(V(U1_VS_INT)>2.72,428u,110u) } X_U1_U866 CP_SAMPLE_HOLD U1_N16848195 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 R_U1_R8 U1_N16854741 U1_IQCP 1 X_U1_U869 U1_VS_INT U1_N16851724 U1_N16851727 U1_VS_POR_CS + COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 X_U1_U868 VCP U1_N16851556 CP_SAMPLE_HOLD COMP_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=0.5 X_U1_U870 U1_N16855278 U1_N16855287 asymmetric_delay PARAMS: + RISING_EDGE_DELAY=100n VTHRESH=0.5 FALLING_EDGE_DELAY=5.6u VDD=1 VSS=0 X_U1_U865 U1_N16855391 U1_CP_POR U1_POR EN_DRV AND3_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=500E-3 V_U1_V23 U1_N16851724 0 2.72 X_U1_U867 U1_N16848195 U1_VS_POR_CS U1_N16848208 AND2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=500E-3 R_U1_R9 EN_OK U1_N16855278 1 C_U1_C5 0 U1_IQCP 1n R_U1_R10 U1_N16855287 U1_N16855391 1 V_U1_V24 U1_N16851727 0 200m V_U2_V8 U2_N16606029 0 1 X_U2_U851 U2_VS_CP_ON U2_VS_CP_OFF INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 X_U2_U848 EN_SYS U2_DISCHG U2_EN_DISCHG AND2_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=500E-3 X_U2_U847 U2_DISCHG U2_CHG INV_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 E_U2_ABM1 VCP 0 VALUE { V(CAP) + -V(VS) } V_U2_V15 U2_N16606813 0 13.257 G_U2_G1 CAP GND U2_EN_DISCHG 0 33u X_U2_U846 EN_SYS U2_CHG U2_N16606091 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 V_U2_V9 U2_N16606767 0 1 X_U2_U850 U2_N16606029 U2_N16606091 U2_EN_CHG AND2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=500E-3 X_U2_U852 0 EN_SYSB U2_N16606391 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 V_U2_V7 U2_N16607087 0 4 E_U2_ABM4 U2_ICP_HIGH 0 VALUE { + LIMIT((-5u*V(ANODE_INT)-98.77u*V(DGATE)+1570u),V(U2_ICP_MIN),1350u) } G_U2_ABMII5 VS CAP VALUE { if( + V(U2_EN_CHG)<0.5,0u,if(V(ANODE_INT)>5.9,V(U2_ICP_HIGH),120u)) } V_U2_V16 U2_N16606887 0 1.041 X_U2_U849 VS U2_N16607087 U2_VS_CP_ON COMP_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=0.5 X_U2_U836 VCP U2_N16606813 U2_N16606887 U2_DISCHG COMPHYS_BASIC_GEN + PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_U2_TABLE1 U2_ICP_MIN 0 TABLE {V(ANODE_INT)} 3V 57uV + 6V 548uV + 12V 525uV + 24V 466uV + 65V 262uV X_U2_S8 U2_N16606391 0 CAP GND Charge_pump_U2_S8 X_U3_U5 U3_N16859196 CAP d_lm74700 V_U3_V19 U3_N16846596 0 8.9m X_U3_U6 A DGATE d_lm74700 G_U3_ABM2I8 DGATE A VALUE { IF(V(N13056)<0.5, 0, + LIMIT((V(U3_N16846596)-V(N13182))*1.432m, -10u,20m)) } G_U3_ABMII6 DGATE A VALUE { IF(V(N10103)>0.5, 1500m,0) } X_U3_U844 U3_N16859196 U3_N16863874 d_lm74700 G_U3_ABMII5 CAP U3_N16859196 VALUE { IF(V(N51846)>0.5, 20m,0) } R_U3_R1 DGATE U3_N16859196 100n R_U3_R2 U3_N16865832 ANODE_INT 1 C_U3_C1 0 U3_N16865832 1n V_U3_V20 U3_N16863874 U3_N16865832 11Vdc .ENDS LM74800-Q1_TRANS *$ .subckt OVP_VSNS_U6_S1 1 2 3 4 S_U6_S1 3 4 1 2 _U6_S1 RS_U6_S1 1 2 1G .MODEL _U6_S1 VSWITCH Roff=1e6 Ron=24 Voff=0.2V Von=0.8V .ends OVP_VSNS_U6_S1 *$ .subckt HGATE_DRIVER_U5_S9 1 2 3 4 S_U5_S9 3 4 1 2 _U5_S9 RS_U5_S9 1 2 1G .MODEL _U5_S9 VSWITCH Roff=1e9 Ron=350k Voff=0.2 Von=0.8 .ends HGATE_DRIVER_U5_S9 *$ .subckt Charge_pump_U2_S8 1 2 3 4 S_U2_S8 3 4 1 2 _U2_S8 RS_U2_S8 1 2 1G .MODEL _U2_S8 VSWITCH Roff=1e12 Ron=1e9 Voff=0.2 Von=0.8 .ends Charge_pump_U2_S8 *$ .subckt asymmetric_delay inp out params: rising_edge_delay=1 vthresh=0.5 + falling_edge_delay=1 vdd=1 vss=0 e_abm3 inp1 0 value { if(v(inp) > {vthresh}, {vdd} , {vss}) } e_abm1 yin4 0 value { if(v(yin3) > {vthresh}, {vdd} , {vss}) } e_abm2 yin2 0 value { if(v(yin1) > {vthresh}, {vdd} , {vss}) } r_rint inp1 yin1 1 c_cint yin1 0 {1.443*rising_edge_delay} d_d10 yin1 inp1 d_d1 r_r1 yin4 out 1 r_rout yin2 yin3 1 c_cout yin3 0 {1.443*falling_edge_delay} c_c1 0 out 1n d_d11 yin2 yin3 d_d1 *$ .model d_d1 d + is=1e-015 + tt=1e-011 + rs=0.005 + n=0.1 *$ .ends asymmetric_delay *$ .SUBCKT CESR IN OUT + PARAMS: C=100u ESR=0.01 X=1 IC=0 C IN 1 {C*X} IC={IC} RESR 1 OUT {ESR/X} .ENDS CESR *$ .SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABM Yint 0 VALUE {IF (V(INP) > + V(INM), {VDD},{VSS})} R1 Yint Y 1 C1 Y 0 1n .ENDS COMP_BASIC_GEN *$ .SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NOR2_BASIC_GEN *$ .SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS AND2_BASIC_GEN *$ .SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}} RINT YINT1 YINT2 1 CINT YINT2 0 {DELAY*1.3} E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , + {VDD},{VSS})}} RINT2 YINT3 Y 1 CINT2 Y 0 1n .ENDS BUF_DELAY_BASIC_GEN *$ .SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5 EIN INP1 INM1 INP INM 1 EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) } EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) } R1 OUT 1 1 C1 1 0 5n RINP1 INP1 0 1K .ENDS COMPHYS_BASIC_GEN *$ .SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}} RINT YINT1 YINT2 1 CINT YINT2 0 {DELAY*1.3} E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , + {VSS},{VDD})}} RINT2 YINT3 Y 1 CINT2 Y 0 1n .ENDS INV_DELAY_BASIC_GEN *$ .SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , + {VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS INV_BASIC_GEN *$ .SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} & + V(C) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS AND3_BASIC_GEN *$ .SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS OR2_BASIC_GEN *$ .subckt D_LM74700 1 2 d1 1 2 dd .model dd d + is=1e-012 + n=0.0001 + tt=1e-011 + bv=100 .ends D_LM74700 *$ .SUBCKT BUK7Y4R8_60E D G S C_Cgs S G 3832p TC=0,0 C_Cds S D 191p TC=0,0 M_M1 D G S S Q1 C_Cgd G D 308p TC=0,0 D_D1 S D BD_Q1 .ENDS BUK7Y4R8_60E *$ .model BD_Q1 d + is=1e-015 + tt=1e-011 + rs=0.05 + n=1 *$ .model Q1 nmos + vto=3 + kp=50 *$ .SUBCKT 1SMB5944BT3G 1 2 D1 1 2 DF DZ 3 1 DR VZ 2 3 62 .MODEL DF D ( IS=3.68p RS=28.1 N=1.10 + CJO=11.6p VJ=1.00 M=0.330 TT=50.1n ) .MODEL DR D ( IS=7.36e-016 RS=115 N=3.00 ) .ENDS *$ .SUBCKT DI_BZT52C51 1 2 D1 1 2 DF DZ 3 1 DR VZ 2 3 48.3 .MODEL DF D ( IS=3.31p RS=1.45 N=1.10 + CJO=24.1p VJ=1.00 M=0.330 TT=50.1n ) .MODEL DR D ( IS=6.62e-016 RS=84.5 N=3.00 ) .ENDS *$ .SUBCKT IPB320N20N3_L0 drain gate source Lg gate g1 4n Ld drain d1 1n Ls source s1 2n Rs s1 s2 1.05m Rg g1 g2 2.4 M1 d2 g2 s2 s2 DMOS L=1u W=1u .MODEL DMOS NMOS ( KP= 109.7 VTO=3.9 THETA=0 VMAX=1.5e5 ETA=0.004 LEVEL=3) Rd d1a d2 17m TC=17m .MODEL MVDR NMOS (KP=126.56 VTO=-1 LAMBDA=0.25) Mr d1 d2a d1a d1a MVDR W=1u L=1u Rx d2a d1a 1m Dbd s2 d2 Dbt .MODEL Dbt D(BV=217 M=0.45 CJO=0.89n VJ=0.9V) Rsp s2 s3 0.7 Dbd1 s3 d2 Dbt1 .MODEL Dbt1 D(BV=1000 M=0.45 CJO=1.77n VJ=0.9V) Dbody s2 21 DBODY .MODEL DBODY D(IS=16.8p N=1.12 RS=0.06u EG=1.12 TT=120n) Rdiode d1 21 3.39m TC=3m .MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) Maux g2 c a a sw Maux2 b d g2 g2 sw Eaux c a d2 g2 1 Eaux2 d g2 d2 g2 -1 Cox b d2 0.27n .MODEL DGD D(M=0.8 CJO=0.27n VJ=0.5) Rpar b d2 1Meg Dgd a d2 DGD Rpar2 d2 a 10Meg Cgs g2 s2 1.77n .ENDS IPB320N20N3_L0 *$ .MODEL 1N4148WS D ( IS=10.4n RS=51.5m BV=75.0 IBV=1.00u + CJO=2.00p M=0.333 N=2.07 TT=5.76n ) *$ .model SMBJ33A D(IS=.1u RS=0.3 CJO=80000p M=1.3 VJ=0.4 ISR=.008u N=1.05 + IKF=1m BV=34.3 NBV=20 IBV=10u TT=4n EG=.84 TRS1=.1m) *$