source: trunk/simulation/tsv99x.txt@ 9

Last change on this file since 9 was 1, checked in by f.jahn, 3 years ago
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[1]1* WARNING : please consider following remarks before usage
2*
3* 1) All models are a tradeoff between accuracy and complexity (ie. simulation
4* time).
5* 2) Macromodels are not a substitute to breadboarding, they rather confirm the
6* validity of a design approach and help to select surrounding component values.
7*
8* 3) A macromodel emulates the NOMINAL performance of a TYPICAL device within
9* SPECIFIED OPERATING CONDITIONS (ie. temperature, supply voltage, etc.).
10* Thus the macromodel is often not as exhaustive as the datasheet, its goal
11* is to illustrate the main parameters of the product.
12*
13* 4) Data issued from macromodels used outside of its specified conditions
14* (Vcc, Temperature, etc) or even worse: outside of the device operating
15* conditions (Vcc, Vicm, etc) are not reliable in any way.
16*
17****************************************************************************
18****
19**** TSV99X Spice macromodel subckt
20****
21**** Revision Date: 10/06/08
22****
23*********** CONNECTIONS:
24**** INVERTING INPUT
25**** | NON-INVERTING INPUT
26**** | | OUTPUT
27**** | | | POSITIVE POWER SUPPLY
28**** | | | | NEGATIVE POWER SUPPLY
29**** | | | | |
30**** | | | | |
31.SUBCKT TSV99X VM VP VS VCCP VCCN
32 HILIM_ICCN NET0477 0 V_OUTVLIM_LOW 235
33 HILIM_ICCP NET0437 0 V_OUTVLIM_HIGH -235
34 M_NMOS2 VO_DIFF_MINUS VM VEE_N VCCN_ENHANCED MOS_N L={L} W={W}
35 M_NMOS1 VO_DIFF_PLUS NET0158 VEE_N VCCN_ENHANCED MOS_N L={L} W={W}
36 IEE_N VEE_N VCCN_ENHANCED DC {IEE}
37 V_OUTVLIM_LOW NET0372 NET0373 DC -770m
38 VVLIM_LOW_VB NET0109 NET0110 DC -770m
39 VREADIO NET0481 VS DC 0
40 VOS NET0158 VP DC 0
41 VPROT_IN_P_VCCP NET0123 NET0134 DC {V_DPROT}
42 V_ENHANCE_VCCN VCCN_ENHANCED VCCN DC -360m
43 VVLIM_HIGH_VB NET0180 NET0153 DC -770m
44 V_ENHANCE_VCCP VCCP_ENHANCED VCCP DC -500m
45 VPROT_IN_M_VCCN NET0116 NET0192 DC {V_DPROT}
46 VPROT_IN_P_VCCN NET0115 NET096 DC {V_DPROT}
47 VPROT_IN_M_VCCP NET0190 NET0135 DC {V_DPROT}
48 V_OUTVLIM_HIGH NET0397 NET0375 DC -770m
49 DILIM_ICCN NET0402 VB_3 DIODE_ILIM
50 DVLIM_HIGH_VB VB NET0180 DIODE_VLIM
51 DPROT_IN_M_VCCP VM NET0135 DIODE_VLIM
52 DILIM_SOURCE VB_3 VB_3_SOURCE DIODE_ILIM
53 D_OUTVLIM_LOW NET0373 VB_3 DIODE_VLIM
54 DVLIM_LOW_VB NET0110 VB DIODE_VLIM
55 DILIM_SINK VB_3_SINK VB_3 DIODE_ILIM
56 D_OUTVLIM_HIGH VB_3 NET0397 DIODE_VLIM
57 DILIM_ICCP VB_3 NET0395 DIODE_ILIM
58 DPROT_IN_M_VCCN NET0116 VM DIODE_VLIM
59 DPROT_IN_P_VCCP NET0158 NET0134 DIODE_VLIM
60 DPROT_IN_P_VCCN NET0115 NET0158 DIODE_VLIM
61 CGATE_VM_PARASITIC VM VREF 7p
62 CGATE_VP_PARASITIC VP VREF 7p
63 CCOMP VB VB_2 {Ccomp}
64 CBD2_PARASITIC VO_DIFF_MINUS VCCN_ENHANCED 7p
65 CGD2_PARASITIC VO_DIFF_MINUS VM 200.0f
66 CBD1_PARASITIC VO_DIFF_PLUS VCCN_ENHANCED 7p
67 CDIFF_PARASITIC VO_DIFF_PLUS VO_DIFF_MINUS 200.0f
68 CGD1_PARASITIC VO_DIFF_PLUS NET0158 200.0f
69 E_ICCSAT_LOW ICC_OUT_LOW 0 POLY(1) VCCP VCCN 0.0023261764705882347
70+-5.5705882352941006E-5 5.294117647058802E-6
71 EMEAS_VOUT_DIFF VOUT_DIFF 0 VO_DIFF_PLUS VO_DIFF_MINUS 1.0
72 EVLIM_HIGH_VB NET0153 0 VCCP 0 1.0
73 E_VDEP_SOURCE_1 VAL_VDEP_SOURCE 0 VALUE={ 174.5 -5000*I(VreadIo)}
74 EVLIM_LOW_VB NET0109 0 VCCN 0 1.0
75
76 *Eldo:
77 *E_RO1_VOL RO1_VOL 0 PWL(1) VCCP VCCN ( 2.5 , 14 ) ( 3.3 , 11 ) ( 5.0 , 7.5 )
78 *PSpice:
79 E_RO1_VOL RO1_VOL 0 VALUE={TABLE(V(VCCP,VCCN), 2.5 , 14 , 3.3 , 11 , 5.0 , 7.5 )}
80
81 E2_REF NET0238 0 VCCN 0 1.0
82 E_VDEP_SINK_1 VAL_VDEP_SINK 0 VALUE={ -159.5 -5000*I(VreadIo)}
83
84 *Eldo:
85 *E_VDEP_SINK_2 VAL_VDEP_SINK_FILTERED 0
86 *+VALUE={VALIF(V(val_vdep_sink)<=0 , 0 , V(val_vdep_sink))}
87 *PSpice:
88 E_VDEP_SINK_2 VAL_VDEP_SINK_FILTERED 0
89 +VALUE={IF(V(val_vdep_sink)<=0 , 0 , V(val_vdep_sink))}
90
91 E_ICCSAT_HIGH ICC_OUT_HIGH 0 POLY(1) VCCP VCCN 0.0023261764705882347
92+-5.5705882352941006E-5 5.294117647058802E-6
93 E_VREF VREF 0 NET0250 0 1.0
94
95 *Eldo:
96 *E_RO1_VOH RO1_VOH 0 PWL(1) VCCP VCCN ( 2.5 , 14 ) ( 3.3 , 11 ) ( 5.0 , 7.5 )
97 *PSpice:
98 E_RO1_VOH RO1_VOH 0 VALUE={TABLE(V(VCCP,VCCN), 2.5 , 14 , 3.3 , 11 , 5.0 , 7.5 )}
99
100 *Eldo:
101 *E_VDEP_SOURCE_3 VDEP_SOURCE 0 VALUE={VALIF( abs(I(VreadIo))<1m , 0 ,
102 *+V(val_vdep_source_filtered))}
103 *PSpice:
104 E_VDEP_SOURCE_3 VDEP_SOURCE 0 VALUE={IF( abs(I(VreadIo))<1m , 0 ,
105 +V(val_vdep_source_filtered))}
106
107 EILIM_ICCP NET0395 NET0437 VB_3 0 1.0
108 EILIM_SINK VB_3_SINK VDEP_SINK VB_3 0 1.0
109 EILIM_ICCN NET0402 NET0477 VB_3 0 1.0
110 EILIM_SOURCE VB_3_SOURCE VDEP_SOURCE VB_3 0 1.0
111
112 *Eldo:
113 *E_RO1 VB_3 NET0481 VALUE={VALIF(I(VreadIo)>0,
114 *+V(Ro1_Voh)*I(VreadIo),V(Ro1_Vol)*I(VreadIo))}
115 *E_VDEP_SINK_3 VDEP_SINK 0 VALUE={VALIF( abs(I(VreadIo))<1m , 0 ,
116 *+V(val_vdep_sink_filtered))}
117 *PSpice:
118 E_RO1 VB_3 NET0481 VALUE={IF(I(VreadIo)>0,
119 +V(Ro1_Voh)*I(VreadIo),V(Ro1_Vol)*I(VreadIo))}
120 E_VDEP_SINK_3 VDEP_SINK 0 VALUE={IF( abs(I(VreadIo))<1m , 0 ,
121 +V(val_vdep_sink_filtered))}
122
123 E1_REF NET0210 0 VCCP 0 1.0
124 EVLIM_LOW_VOUT NET0372 0 VCCN 0 1.0
125
126 *Eldo:
127 *E_VDEP_SOURCE_2 VAL_VDEP_SOURCE_FILTERED 0
128 *+VALUE={VALIF(V(val_vdep_source)>=0, 0, V(val_vdep_source))}
129 *PSpice:
130 E_VDEP_SOURCE_2 VAL_VDEP_SOURCE_FILTERED 0
131 +VALUE={IF(V(val_vdep_source)>=0, 0, V(val_vdep_source))}
132
133 EVLIM_HIGH_VOUT NET0375 0 VCCP 0 1.0
134 R_ICCSAT_HIGH ICC_OUT_HIGH 0 1K
135 R_ICCSAT_LOW ICC_OUT_LOW 0 1K
136 RPROT_IN_P_VCCP NET0123 VCCP 15K
137 RPROT_IN_M_VCCP VCCP NET0190 15K
138 RD1 VCCP_ENHANCED VO_DIFF_PLUS {RD}
139 RD2 VCCP_ENHANCED VO_DIFF_MINUS {RD}
140 RO2_1 VREF VB_2 {Ro2_1}
141 R1_REF NET0210 NET0250 1Meg
142 RO2_2 VB_3 VB_2 {Ro2_2}
143 R1 VB VREF {R1}
144 RPROT_IN_M_VCCN VCCN NET0192 15K
145 R2_REF NET0250 NET0238 1Meg
146 RPROT_IN_P_VCCN NET096 VCCN 15K
147
148 *Eldo:
149 *G_IOUT_SOUCED VCCP 0 VALUE={VALIF(I(VreadIo)>0, I(VreadIo),0)}
150 *G_ICCSAT_OUTLOW VCCP VCCN VALUE={VALIF(I(V_OUTVLIM_LOW)>1u ,
151 *+V(Icc_out_low) , 0)}
152 *G_ICCSAT_OUTHIGH VCCP VCCN VALUE={VALIF(I(V_OUTVLIM_HIGH)>1u ,
153 *+V(Icc_out_high), 0)}
154 *G_IOUT_SINKED VCCN 0 VALUE={VALIF(I(VreadIo)>0, 0, I(VreadIo))}
155 *PSpice:
156 G_IOUT_SOUCED VCCP 0 VALUE={IF(I(VreadIo)>0, I(VreadIo),0)}
157 G_ICCSAT_OUTLOW VCCP VCCN VALUE={IF(I(V_OUTVLIM_LOW)>1u ,
158 +V(Icc_out_low) , 0)}
159 G_ICCSAT_OUTHIGH VCCP VCCN VALUE={IF(I(V_OUTVLIM_HIGH)>1u ,
160 +V(Icc_out_high), 0)}
161 G_IOUT_SINKED VCCN 0 VALUE={IF(I(VreadIo)>0, 0, I(VreadIo))}
162
163 G_I_VB VB_2 VREF POLY(1) VB VREF 7.773528173127232E-19
164 +0.010310813241023556 0 0.1401392933601382
165 GM1 VREF VB VOUT_DIFF 0 {1/RD}
166 G_ICC VCCP VCCN POLY(1) VCCP VCCN 6.380235294117639E-4
167+5.570588235294159E-5 -5.294117647058884E-6
168.ENDS
169*** End of subcircuit definition.
170
171.PARAM RD=1k
172.PARAM Ccomp=3.4p
173.PARAM IEE=35.8u
174.PARAM W=25u
175.PARAM L=2u
176.PARAM gm_mos=0.0004733346976081021
177.PARAM A0=97.93103448E3
178.PARAM Ro=17587.2
179.PARAM GB=11m
180.PARAM Ro1=11
181.PARAM Ro2_2=1e-3
182.PARAM Ro2_1={Ro - Ro2_2 - Ro1}
183.PARAM R1={A0/(gm_mos*GB*Ro2_1)}
184.PARAM V_DPROT=0.6
185
186*Eldo:
187*.MODEL MOS_N NMOS LEVEL=1 MODTYPE=ELDO VTO=+0.65 KP=500E-6
188*.MODEL DIODE_VLIM D LEVEL=1 MODTYPE=ELDO IS=0.8E-15
189*.MODEL DIODE_ILIM D LEVEL=1 MODTYPE=ELDO IS=0.8E-15
190*.MODEL DX D LEVEL=1 MODTYPE=ELDO IS=1E-14
191*PSpice:
192.MODEL MOS_N NMOS LEVEL=1 VTO=+0.65 KP=500E-6
193.MODEL DIODE_VLIM D LEVEL=1 IS=0.8E-15
194.MODEL DIODE_ILIM D LEVEL=1 IS=0.8E-15
195.MODEL DX D LEVEL=1 IS=1E-14
196***********************************************************************************
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