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TRANSIENT.out.1@ 2

Last change on this file since 2 was 1, checked in by f.jahn, 3 years ago

File size: 13.4 KB

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1
2
3	** 01/23/20 16:28:32 * PSpice 16.6.0 (October 2012) * ID# 0 ******
4
5	** Profile: "SCHEMATIC1-TRANSIENT" [ C:\Users\a0282827\Downloads\PSpice Library\^INA302\INA302_PSpice\INA302 Test Circuit-PSpiceFil
6
7
8	**** CIRCUIT DESCRIPTION
9
10
11	******************************************************************************
12
13
14
15
16	** Creating circuit file "TRANSIENT.cir"
17	** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
18
19	*Libraries:
20	* Profile Libraries :
21	* Local Libraries :
22	.LIB "../../../ina302a3.lib"
23	.LIB "../../../ina302a2.lib"
24	.LIB "../../../ina302a1.lib"
25	* From [PSPICE NETLIST] section of C:\Users\a0282827\AppData\Roaming\SPB_Data\cdssetup\OrCAD_PSpice/16.6.0/PSpice.ini file:
26	.lib "nom.lib"
27
28	*Analysis directives:
29	.TRAN 0 20m 0 20u
30	.OPTIONS ADVCONV
31	.PROBE64 V(alias()) I(alias()) W(alias()) D(alias()) NOISE(alias(*))
32	.INC "..\SCHEMATIC1.net"
33
34
35
36	** INCLUDING SCHEMATIC1.net **
37	* source INA302 TEST CIRCUIT
38	X_U1 A1_INP A1_INN REF A1_LATCH1 A1_LATCH2 N04903 N04907 N04743
39	+ A1_ALERT1 A1_ALERT2 VCC A1_OUT 0 INA302A1
40	C_C1 0 N04743 100f TC=0,0
41	R_R6 0 N04903 25k TC=0,0
42	R_R7 0 N04907 37.5k TC=0,0
43	R_R8 0 A1_OUT 10Meg TC=0,0
44	C_C2 0 A1_OUT 500p TC=0,0
45	R_R9 A1_ALERT1 VCC 10k TC=0,0
46	R_R10 A1_ALERT2 VCC 10k TC=0,0
47	V_V1 VCC 0 5Vdc
48	V_V2 REF 0 2.5Vdc
49	V_V3 SIG 0 AC 1
50	+SIN 0 5.9 1k 0 0 0
51	V_V4 A1_INP 0 12Vdc
52	R_R11 A1_INN A1_INP 10k TC=0,0
53	V_V5 A1_LATCH1 0
54	+PWL 0 0 5m 0 5.000001m 5 9.5m 5 9.500001m 0
55	V_V6 A1_LATCH2 0
56	+PWL 0 0 13m 0 13.000001m 5 18.5m 5 18.500001m 0
57	I_I1 A1_INN 0 DC 0Adc AC 0Aac
58	+SIN 0 5.9 1k 0 0 0
59
60	** RESUMING TRANSIENT.cir **
61	.END
62
63
64	** 01/23/20 16:28:32 * PSpice 16.6.0 (October 2012) * ID# 0 ******
65
66	** Profile: "SCHEMATIC1-TRANSIENT" [ C:\Users\a0282827\Downloads\PSpice Library\^INA302\INA302_PSpice\INA302 Test Circuit-PSpiceFil
67
68
69	**** Diode MODEL PARAMETERS
70
71
72	******************************************************************************
73
74
75
76
77	X_U1.D_1 X_U1.X_U1_U1.XU2.DVN
78	IS 10.000000E-15 100.000000E-18
79	KF 3.162278E-12
80
81
82
83	** 01/23/20 16:28:32 * PSpice 16.6.0 (October 2012) * ID# 0 ******
84
85	** Profile: "SCHEMATIC1-TRANSIENT" [ C:\Users\a0282827\Downloads\PSpice Library\^INA302\INA302_PSpice\INA302 Test Circuit-PSpiceFil
86
87
88	**** Voltage Controlled Switch MODEL PARAMETERS
89
90
91	******************************************************************************
92
93
94
95
96	X_U1.X_S3._S3 X_U1.X_S4._S4 X_U1.X_S1._S1 X_U1.X_S2._S2
97	RON 1 1 1 1
98	ROFF 100.000000E+06 100.000000E+06 1.000000E+06 1.000000E+06
99	VON 3 3 3 3.25
100	VOFF 2 2 2 3.1
101
102
103
104	** 01/23/20 16:28:32 * PSpice 16.6.0 (October 2012) * ID# 0 ******
105
106	** Profile: "SCHEMATIC1-TRANSIENT" [ C:\Users\a0282827\Downloads\PSpice Library\^INA302\INA302_PSpice\INA302 Test Circuit-PSpiceFil
107
108
109	**** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C
110
111
112	******************************************************************************
113
114
115
116	NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
117
118
119	( REF) 2.5000 ( SIG) 0.0000 ( VCC) 5.0000 (A1_INN) 10.7180
120
121	(A1_INP) 12.0000 (A1_OUT) 4.9479 (N04743) 4.9988 (N04903) 2.0000
122
123	(N04907) 3.0000 (A1_ALERT1) 500.0E-06 (A1_ALERT2) 500.0E-06
124
125	(A1_LATCH1) 0.0000 (A1_LATCH2) 0.0000
126
127	(X_U1.S1_IN) 4.9999 (X_U1.S3_IN) 0.0000
128
129	(X_U1.S4_IN) 0.0000 (X_U1.INT_5V) 5.0000
130
131	(X_U1.N25241) 3.0000 (X_U1.N44121) 2.0000
132
133	(X_U1.N157605) 1.0000 (X_U1.N169176) 4.9988
134
135	(X_U1.N173762) 1.0000 (X_U1.N174877) 5.0000
136
137	(X_U1.OPA_OUT) 4.9479 (X_U1.U100_P1) 5.3400
138
139	(X_U1.U100_P2) 5.3404 (X_U1.U100_Z1) 0.0000
140
141	(X_U1.U1_CMIN) 11.3590 (X_U1.U1_VMID) 2.5000
142
143	(X_U1.X_U6.NA) 2.5000 (X_U1.X_U6.NB) 3.5000
144
145	(X_U1.X_U6.NC) 3.5000 (X_U1.X_U7.NA) 2.5000
146
147	(X_U1.X_U7.NB) 3.5000 (X_U1.X_U7.NC) 3.5000
148
149	(X_U1.COMP1_OUT) 5.0000 (X_U1.COMP2_OUT) 5.0000
150
151	(X_U1.U1_N66933) 4.9479 (X_U1.U1_N67297) -10.7180
152
153	(X_U1.U1_N67459) 10.7180 (X_U1.U1_N67465) 12.0000
154
155	(X_U1.U1_N67543) 0.0000 (X_U1.U2_N01012) 4.9489
156
157	(X_U1.U2_N03015) 1.9985 (X_U1.U4_N01012) 4.9489
158
159	(X_U1.U4_N03015) 2.9985 (X_U1.X_U1_U1.7) 4.9479
160
161	(X_U1.X_U1_U1.9) 4.9485 (X_U1.X_U6.GNDF) 2.5000
162
163	(X_U1.X_U7.GNDF) 2.5000 (X_U1.CNTRL1_OUT) 0.0000
164
165	(X_U1.CNTRL2_OUT) 0.0000 (X_U1.U100_N_SUM) 5.3404
166
167	(X_U1.U1_N161902) 34.08E-06 (X_U1.U1_N167670) .6407
168
169	(X_U1.U1_N168091) -.6410 (X_U1.U1_OPA_INN) 2.0063
170
171	(X_U1.U1_OPA_INP) 3.1100 (X_U1.X_U1_U1.10) 82.14E+03
172
173	(X_U1.X_U1_U1.11) 82.14E+03 (X_U1.X_U1_U1.12) 3.1101
174
175	(X_U1.X_U1_U1.13) 2.0063 (X_U1.X_U1_U1.14) 3.1101
176
177	(X_U1.X_U1_U1.15) 2.0063 (X_U1.X_U1_U1.20) 3.1100
178
179	(X_U1.X_U1_U1.21) 2.0063 (X_U1.X_U1_U1.22) 2.0063
180
181	(X_U1.X_U1_U1.23) 3.1100 (X_U1.COMP_VCC_5V) 5.0000
182
183	(X_U1.U1_CMRR_OUT) 34.08E-06 (X_U1.U1_VINN_MID) 1.8590
184
185	(X_U1.U1_VINP_MID) 3.1407 (X_U1.U1_VSN_WOCM) -.6410
186
187	(X_U1.U1_VSP_WOCM) .6407 (X_U1.X_U101.nmid) 2.5000
188
189	(X_U1.X_U102.nmid) 2.5000 (X_U1.U100_N165884) 5.3404
190
191	(X_U1.U100_N165960) 0.0000 (X_U1.U100_N166036) 5.3400
192
193	(X_U1.U100_N166302) 8.6775 (X_U1.U100_N166724) 400.5E-06
194
195	(X_U1.X_U1_U1.GNDF) 2.5000 (X_U1.X_U2_U1.nmid) 2.5000
196
197	(X_U1.X_U4_U1.nmid) 2.5000 (X_U1.X_U6.NABnotC) 2.5000
198
199	(X_U1.X_U7.NABnotC) 2.5000 (X_U1.X_U1_U1.VIMON) 11.77E-06
200
201	(X_U1.X_U1_U1.XU2.3) 0.0000 (X_U1.X_U1_U1.XU2.4) 0.0000
202
203	(X_U1.X_U1_U1.XU2.5) 0.0000 (X_U1.X_U1_U1.XU2.6) 0.0000
204
205	(X_U1.X_U1_U1.XU2.7) .8338 (X_U1.X_U1_U1.XU2.8) .8338
206
207	(X_U1.X_U1_U1.XU4.1) 2.5000 (X_U1.X_U1_U1.XU4.2) 2.5000
208
209	(X_U1.X_U1_U1.XU4.3) 2.5000 (X_U1.X_U1_U1.XU4.4) 2.5000
210
211	(X_U1.X_U1_U1.XU5.1) 2.5000 (X_U1.X_U1_U1.XU5.2) 2.5000
212
213	(X_U1.U100_AOL_ZO_IN) 6.675E-06 (X_U1.U100_OUT_E4_ZO) 5.3404
214
215	(X_U1.X_U1_U1.XU13.OUTx) 4.9479 (X_U1.X_U1_U1.XU13.OUTy) 4.9479
216
217	(X_U1.X_U1_U1.XU11.VDD_CLP) 2.4485 (X_U1.X_U1_U1.XU11.VSS_CLP) -2.4800
218
219
220
221
222	VOLTAGE SOURCE CURRENTS
223	NAME CURRENT
224
225	V_V1 -1.672E-03
226	V_V2 -5.983E-08
227	V_V3 0.000E+00
228	V_V4 -2.727E-04
229	V_V5 0.000E+00
230	V_V6 0.000E+00
231	X_U1.V_V1 0.000E+00
232	X_U1.V_V2 0.000E+00
233	X_U1.V_V4 0.000E+00
234	X_U1.V_U2_V1 0.000E+00
235	X_U1.V_U4_V1 0.000E+00
236	X_U1.X_U1_U1.XU1.V1 1.165E-08
237	X_U1.X_U1_U1.XU1.V2 -1.153E-08
238	X_U1.X_U1_U1.XU3.V1 2.890E-12
239	X_U1.X_U1_U1.XU13.VSENS 1.177E-05
240
241	TOTAL POWER DISSIPATION 1.16E-02 WATTS
242
243	Reducing minimum delta to make the circuit converge.
244	Reducing minimum delta to make the circuit converge.
245	Reducing minimum delta to make the circuit converge.
246	Reducing minimum delta to make the circuit converge.
247	Reducing minimum delta to make the circuit converge.
248
249	ERROR(ORPSIM-15138): Convergence problem in Transient Analysis at Time = 11.14E-06.
250	Time step = 938.5E-21, minimum allowable step size = 1.000E-18
251
252	These voltages failed to converge:
253
254	V(X_U1.N169176) = 5.783V \ 4.999V
255	V(X_U1.U1_CMRR_OUT) = -66.60mV \ -71.57mV
256
257	These supply currents failed to converge:
258
259	I(X_U1.X_U101.emid) = -78.38mA \ -4.992nA
260	I(X_U1.X_U101.eout) = -78.38mA \ -4.992nA
261	I(X_U1.X_U1_U1.XU2.E3) = -315.19nA \ 486.33nA
262	I(X_U1.X_U1_U1.XU0.EGNDF) = -9.219mA \ -4.482mA
263	I(X_U1.X_U1_U1.XU1.V2) = -547.89uA \ -550.27uA
264	I(X_U1.X_U1_U1.XU3.V1) = 485.69nA \ -317.58nA
265
266	These devices failed to converge:
267	X_U1.D_D1
268
269
270
271	Last node voltages tried were:
272
273	NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
274
275
276	( REF) 2.5000 ( SIG) .4126 ( VCC) 5.0000 (A1_INN)-3961.0000
277
278	(A1_INP) 12.0000 (A1_OUT) 2.9585 (N04743) 4.9988 (N04903) 2.0000
279
280	(N04907) 3.0000 (A1_ALERT1) 500.0E-06 (A1_ALERT2) 500.0E-06
281
282	(A1_LATCH1) 0.0000 (A1_LATCH2) 0.0000
283
284	(X_U1.S1_IN) 4.9999 (X_U1.S3_IN) 0.0000
285
286	(X_U1.S4_IN) 0.0000 (X_U1.INT_5V) 5.0000
287
288	(X_U1.N25241) 3.0000 (X_U1.N44121) 2.0000
289
290	(X_U1.N157605) 1.0000 (X_U1.N169176) 5.7826
291
292	(X_U1.N173762) 1.0000 (X_U1.N174877) 5.0000
293
294	(X_U1.OPA_OUT) 2.9583 (X_U1.U100_P1) 5.3400
295
296	(X_U1.U100_P2) -229.2000 (X_U1.U100_Z1) -261.1000
297
298	(X_U1.U1_CMIN)-1974.5000 (X_U1.U1_VMID) 2.5000
299
300	(X_U1.X_U6.NA) 2.5000 (X_U1.X_U6.NB) 3.5000
301
302	(X_U1.X_U6.NC) 3.5000 (X_U1.X_U7.NA) 2.5000
303
304	(X_U1.X_U7.NB) 3.5000 (X_U1.X_U7.NC) 3.5000
305
306	(X_U1.COMP1_OUT) 5.0000 (X_U1.COMP2_OUT) 5.0000
307
308	(X_U1.U1_N66933) 2.9583 (X_U1.U1_N67297) 3961.0000
309
310	(X_U1.U1_N67459)-3961.0000 (X_U1.U1_N67465) 11.9920
311
312	(X_U1.U1_N67543) 0.0000 (X_U1.U2_N01012) 2.9985
313
314	(X_U1.U2_N03015) 1.9985 (X_U1.U4_N01012) 2.9985
315
316	(X_U1.U4_N03015) 2.9985 (X_U1.X_U1_U1.7) 2.9583
317
318	(X_U1.X_U1_U1.9) 3.3354 (X_U1.X_U6.GNDF) 2.5000
319
320	(X_U1.X_U7.GNDF) 2.5000 (X_U1.CNTRL1_OUT) 0.0000
321
322	(X_U1.CNTRL2_OUT) 0.0000 (X_U1.U100_N_SUM) -255.7700
323
324	(X_U1.U1_N161902) -.0059 (X_U1.U1_N167670) 1986.5000
325
326	(X_U1.U1_N168091)-1986.5000 (X_U1.U1_OPA_INN)-1882.9000
327
328	(X_U1.U1_OPA_INP) 1887.9000 (X_U1.X_U1_U1.10) 82.14E+03
329
330	(X_U1.X_U1_U1.11) 82.14E+03 (X_U1.X_U1_U1.12) 1887.9000
331
332	(X_U1.X_U1_U1.13)-1882.9000 (X_U1.X_U1_U1.14) 5.0000
333
334	(X_U1.X_U1_U1.15) 111.0E-18 (X_U1.X_U1_U1.20) 1887.9000
335
336	(X_U1.X_U1_U1.21)-1882.9000 (X_U1.X_U1_U1.22)-1882.9000
337
338	(X_U1.X_U1_U1.23) 1887.9000 (X_U1.COMP_VCC_5V) 5.0000
339
340	(X_U1.U1_CMRR_OUT) -.0666 (X_U1.U1_VINN_MID)-1984.0000
341
342	(X_U1.U1_VINP_MID) 1989.0000 (X_U1.U1_VSN_WOCM)-1986.5000
343
344	(X_U1.U1_VSP_WOCM) 1986.5000 (X_U1.X_U101.nmid) 2.5000
345
346	(X_U1.X_U102.nmid) 2.5000 (X_U1.U100_N165884) -255.7700
347
348	(X_U1.U100_N165960) -.2141 (X_U1.U100_N166036) -157.9800
349
350	(X_U1.U100_N166302) -256.7200 (X_U1.U100_N166724) -.0118
351
352	(X_U1.X_U1_U1.GNDF) 2.5000 (X_U1.X_U2_U1.nmid) 2.5000
353
354	(X_U1.X_U4_U1.nmid) 2.5000 (X_U1.X_U6.NABnotC) 2.5000
355
356	(X_U1.X_U7.NABnotC) 2.5000 (X_U1.X_U1_U1.VIMON) .0075
357
358	(X_U1.X_U1_U1.XU2.3) 0.0000 (X_U1.X_U1_U1.XU2.4) 0.0000
359
360	(X_U1.X_U1_U1.XU2.5) 0.0000 (X_U1.X_U1_U1.XU2.6) 0.0000
361
362	(X_U1.X_U1_U1.XU2.7) .8338 (X_U1.X_U1_U1.XU2.8) .8338
363
364	(X_U1.X_U1_U1.XU4.1) 2.5000 (X_U1.X_U1_U1.XU4.2) 2.5000
365
366	(X_U1.X_U1_U1.XU4.3) 2.5000 (X_U1.X_U1_U1.XU4.4) 2.5000
367
368	(X_U1.X_U1_U1.XU5.1) 2.5000 (X_U1.X_U1_U1.XU5.2) 2.5000
369
370	(X_U1.U100_AOL_ZO_IN)-197.5E-06 (X_U1.U100_OUT_E4_ZO) -229.2000
371
372	(X_U1.X_U1_U1.XU13.OUTx) 2.9658 (X_U1.X_U1_U1.XU13.OUTy) 2.9583
373
374	(X_U1.X_U1_U1.XU11.VDD_CLP) .8354 (X_U1.X_U1_U1.XU11.VSS_CLP) -2.4800
375
376
377	** Interrupt **

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