source: trunk/firmware/SES/Drivers/EEPROM/stm32g0xx_ll_bus.h@ 5

Last change on this file since 5 was 1, checked in by f.jahn, 3 years ago
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1/**
2 ******************************************************************************
3 * @file stm32g0xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37/* Define to prevent recursive inclusion -------------------------------------*/
38#ifndef STM32G0xx_LL_BUS_H
39#define STM32G0xx_LL_BUS_H
40
41#ifdef __cplusplus
42extern "C" {
43#endif
44
45/* Includes ------------------------------------------------------------------*/
46#include "stm32g0xx.h"
47
48/** @addtogroup STM32G0xx_LL_Driver
49 * @{
50 */
51
52#if defined(RCC)
53
54/** @defgroup BUS_LL BUS
55 * @{
56 */
57
58/* Private types -------------------------------------------------------------*/
59/* Private variables ---------------------------------------------------------*/
60
61/* Private constants ---------------------------------------------------------*/
62
63/* Private macros ------------------------------------------------------------*/
64
65/* Exported types ------------------------------------------------------------*/
66/* Exported constants --------------------------------------------------------*/
67/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
75#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
76#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
77#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN
78#if defined(CRC)
79#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
80#endif
81#if defined(AES)
82#define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
83#endif /* AES */
84#if defined(RNG)
85#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN
86#endif
87/**
88 * @}
89 */
90
91
92/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
93 * @{
94 */
95#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
96#if defined(TIM2)
97#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
98#endif /* TIM2 */
99#if defined(TIM3)
100#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
101#endif /* TIM3 */
102#if defined(TIM6)
103#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APBENR1_TIM6EN
104#endif /* TIM6 */
105#if defined(TIM7)
106#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APBENR1_TIM7EN
107#endif /* TIM7 */
108#define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
109#define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
110#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
111#define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
112#if defined(USART3)
113#define LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN
114#endif
115#if defined(USART4)
116#define LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN
117#endif /* USART4 */
118#if defined(LPUART1)
119#define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APBENR1_LPUART1EN
120#endif
121#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
122#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN
123#if defined(CEC)
124#define LL_APB1_GRP1_PERIPH_CEC RCC_APBENR1_CECEN
125#endif /* CEC */
126#if defined(UCPD1)
127#define LL_APB1_GRP1_PERIPH_UCPD1 RCC_APBENR1_UCPD1EN
128#endif
129#if defined(UCPD2)
130#define LL_APB1_GRP1_PERIPH_UCPD2 RCC_APBENR1_UCPD2EN
131#endif
132#define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
133#define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
134#if defined(DAC1)
135#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APBENR1_DAC1EN
136#endif
137#if defined(LPTIM2)
138#define LL_APB1_GRP1_PERIPH_LPTIM2 RCC_APBENR1_LPTIM2EN
139#endif
140#if defined(LPTIM1)
141#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIM1EN
142#endif
143/**
144 * @}
145 */
146
147/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
148 * @{
149 */
150#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
151#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
152#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN
153#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APBENR2_SPI1EN
154#define LL_APB2_GRP1_PERIPH_USART1 RCC_APBENR2_USART1EN
155#if defined(TIM14)
156#define LL_APB2_GRP1_PERIPH_TIM14 RCC_APBENR2_TIM14EN
157#endif /* TIM14 */
158#if defined(TIM15)
159#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APBENR2_TIM15EN
160#endif
161#if defined(TIM16)
162#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APBENR2_TIM16EN
163#endif
164#if defined(TIM17)
165#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APBENR2_TIM17EN
166#endif /* TIM17 */
167#if defined(ADC)
168#define LL_APB2_GRP1_PERIPH_ADC RCC_APBENR2_ADCEN
169#endif
170/**
171 * @}
172 */
173
174/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
175 * @{
176 */
177#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
178#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
179#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
180#define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
181#define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
182#if defined(GPIOE)
183#define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN
184#endif /* GPIOE */
185#if defined(GPIOF)
186#define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN
187#endif /* GPIOF */
188/**
189 * @}
190 */
191
192/**
193 * @}
194 */
195
196/* Exported macro ------------------------------------------------------------*/
197/* Exported functions --------------------------------------------------------*/
198/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
199 * @{
200 */
201
202/** @defgroup BUS_LL_EF_AHB1 AHB1
203 * @{
204 */
205
206/**
207 * @brief Enable AHB1 peripherals clock.
208 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
209 * AHBENR FLASHEN LL_AHB1_GRP1_EnableClock\n
210 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
211 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
212 * AHBENR RNGEN LL_AHB1_GRP1_EnableClock
213 * @param Periphs This parameter can be a combination of the following values:
214 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
215 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
216 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
217 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
218 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
219 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
220 * @retval None
221*/
222__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
223{
224 __IO uint32_t tmpreg;
225 SET_BIT(RCC->AHBENR, Periphs);
226 /* Delay after an RCC peripheral clock enabling */
227 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
228 (void)tmpreg;
229}
230
231/**
232 * @brief Check if AHB1 peripheral clock is enabled or not
233 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
234 * AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
235 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
236 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
237 * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock
238 * @param Periphs This parameter can be a combination of the following values:
239 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
240 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
241 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
242 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
243 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
244 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
245 * @retval State of Periphs (1 or 0).
246*/
247__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
248{
249 return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
250}
251
252/**
253 * @brief Disable AHB1 peripherals clock.
254 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
255 * AHBENR FLASHEN LL_AHB1_GRP1_DisableClock\n
256 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
257 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
258 * AHBENR RNGEN LL_AHB1_GRP1_DisableClock
259 * @param Periphs This parameter can be a combination of the following values:
260 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
261 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
262 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
263 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
264 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
265 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
266 * @retval None
267*/
268__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
269{
270 CLEAR_BIT(RCC->AHBENR, Periphs);
271}
272
273/**
274 * @brief Force AHB1 peripherals reset.
275 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
276 * AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
277 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
278 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
279 * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset
280* @param Periphs This parameter can be a combination of the following values:
281 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
282 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
283 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
284 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
285 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
286 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
287 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
288 * @retval None
289*/
290__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
291{
292 SET_BIT(RCC->AHBRSTR, Periphs);
293}
294
295/**
296 * @brief Release AHB1 peripherals reset.
297 * @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
298 * AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
299 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
300 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
301 * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset
302 * @param Periphs This parameter can be a combination of the following values:
303 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
304 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
305 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
306 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
307 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
308 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
309 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
310 * @retval None
311*/
312__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
313{
314 CLEAR_BIT(RCC->AHBRSTR, Periphs);
315}
316
317/**
318 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
319 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
320 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
321 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
322 * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
323 * AHBSMENR AESSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
324 * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockStopSleep
325 * @param Periphs This parameter can be a combination of the following values:
326 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
327 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
328 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
329 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
330 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
331 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
332 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
333 * @retval None
334*/
335__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
336{
337 __IO uint32_t tmpreg;
338 SET_BIT(RCC->AHBSMENR, Periphs);
339 /* Delay after an RCC peripheral clock enabling */
340 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
341 (void)tmpreg;
342}
343
344/**
345 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
346 * @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
347 * AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
348 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
349 * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
350 * AHBSMENR AESSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
351 * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockStopSleep
352 * @param Periphs This parameter can be a combination of the following values:
353 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
354 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
355 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
356 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
357 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
358 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
359 * @note (*) RNG & CRYP Peripherals available only on STM32G081xx
360 * @retval None
361*/
362__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
363{
364 CLEAR_BIT(RCC->AHBSMENR, Periphs);
365}
366
367/**
368 * @}
369 */
370
371/** @defgroup BUS_LL_EF_APB1 APB1
372 * @{
373 */
374
375/**
376 * @brief Enable APB1 peripherals clock.
377 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
378 * APBENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
379 * APBENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
380 * APBENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
381 * APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
382 * APBENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
383 * APBENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
384 * APBENR1 USART2EN LL_APB1_GRP1_EnableClock\n
385 * APBENR1 USART3EN LL_APB1_GRP1_EnableClock\n
386 * APBENR1 USART4EN LL_APB1_GRP1_EnableClock\n
387 * APBENR1 LPUART1EN LL_APB1_GRP1_EnableClock\n
388 * APBENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
389 * APBENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
390 * APBENR1 CECEN LL_APB1_GRP1_EnableClock\n
391 * APBENR1 UCPD1EN LL_APB1_GRP1_EnableClock\n
392 * APBENR1 UCPD2EN LL_APB1_GRP1_EnableClock\n
393 * APBENR1 DBGEN LL_APB1_GRP1_EnableClock\n
394 * APBENR1 PWREN LL_APB1_GRP1_EnableClock\n
395 * APBENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
396 * APBENR1 LPTIM2EN LL_APB1_GRP1_EnableClock\n
397 * APBENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
398 * @param Periphs This parameter can be a combination of the following values:
399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
402 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
403 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
404 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
405 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
406 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
407 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
408 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
409 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
410 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
411 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
412 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
413 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
414 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
415 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
416 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
417 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
418 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
419 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
420 * @note Peripheral marked with (1) are not available all devices
421 * @retval None
422*/
423__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
424{
425 __IO uint32_t tmpreg;
426 SET_BIT(RCC->APBENR1, Periphs);
427 /* Delay after an RCC peripheral clock enabling */
428 tmpreg = READ_BIT(RCC->APBENR1, Periphs);
429 (void)tmpreg;
430}
431
432/**
433 * @brief Check if APB1 peripheral clock is enabled or not
434 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
435 * APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
436 * APBENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
437 * APBENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
438 * APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
439 * APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
440 * APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
441 * APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
442 * APBENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
443 * APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock\n
444 * APBENR1 LPUART1EN LL_APB1_GRP1_IsEnabledClock\n
445 * APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
446 * APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
447 * APBENR1 CECEN LL_APB1_GRP1_IsEnabledClock\n
448 * APBENR1 UCPD1EN LL_APB1_GRP1_IsEnabledClock\n
449 * APBENR1 UCPD2EN LL_APB1_GRP1_IsEnabledClock\n
450 * APBENR1 DBGEN LL_APB1_GRP1_IsEnabledClock\n
451 * APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
452 * APBENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
453 * APBENR1 LPTIM2EN LL_APB1_GRP1_IsEnabledClock\n
454 * APBENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
455 * @param Periphs This parameter can be a combination of the following values:
456 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
457 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
458 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
459 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
460 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
461 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
462 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
463 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
464 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
465 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
466 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
467 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
468 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
469 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
470 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
471 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
472 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
473 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
474 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
475 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
476 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
477 * @note Peripheral marked with (1) are not available all devices
478 * @retval State of Periphs (1 or 0).
479*/
480__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
481{
482 return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
483}
484
485/**
486 * @brief Disable APB1 peripherals clock.
487 * @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
488 * APBENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
489 * APBENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
490 * APBENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
491 * APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
492 * APBENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
493 * APBENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
494 * APBENR1 USART2EN LL_APB1_GRP1_DisableClock\n
495 * APBENR1 USART3EN LL_APB1_GRP1_DisableClock\n
496 * APBENR1 USART4EN LL_APB1_GRP1_DisableClock\n
497 * APBENR1 LPUART1EN LL_APB1_GRP1_DisableClock\n
498 * APBENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
499 * APBENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
500 * APBENR1 CECEN LL_APB1_GRP1_DisableClock\n
501 * APBENR1 UCPD1EN LL_APB1_GRP1_DisableClock\n
502 * APBENR1 UCPD2EN LL_APB1_GRP1_DisableClock\n
503 * APBENR1 DBGEN LL_APB1_GRP1_DisableClock\n
504 * APBENR1 PWREN LL_APB1_GRP1_DisableClock\n
505 * APBENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
506 * APBENR1 LPTIM2EN LL_APB1_GRP1_DisableClock\n
507 * APBENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
508 * @param Periphs This parameter can be a combination of the following values:
509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
510 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
513 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
514 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
515 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
516 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
517 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
518 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
519 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
520 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
521 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
522 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
523 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
524 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
525 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
526 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
527 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
528 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
529 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
530 * @note Peripheral marked with (1) are not available all devices
531 * @retval None
532*/
533__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
534{
535 CLEAR_BIT(RCC->APBENR1, Periphs);
536}
537
538/**
539 * @brief Force APB1 peripherals reset.
540 * @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
541 * APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
542 * APBRSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
543 * APBRSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
544 * APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset\n
545 * APBRSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n
546 * APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
547 * APBRSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
548 * APBRSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
549 * APBRSTR1 USART4RST LL_APB1_GRP1_ForceReset\n
550 * APBRSTR1 LPUART1RST LL_APB1_GRP1_ForceReset\n
551 * APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
552 * APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
553 * APBRSTR1 CECRST LL_APB1_GRP1_ForceReset\n
554 * APBRSTR1 UCPD1RST LL_APB1_GRP1_ForceReset\n
555 * APBRSTR1 UCPD2RST LL_APB1_GRP1_ForceReset\n
556 * APBRSTR1 DBGRST LL_APB1_GRP1_ForceReset\n
557 * APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
558 * APBRSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
559 * APBRSTR1 LPTIM2RST LL_APB1_GRP1_ForceReset\n
560 * APBRSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
561 * @param Periphs This parameter can be a combination of the following values:
562 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
563 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
564 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
565 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
566 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
567 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
568 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
569 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
570 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
571 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
572 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
573 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
574 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
575 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
576 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
577 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
578 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
579 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
580 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
581 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
582 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
583 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
584 * @note Peripheral marked with (1) are not available all devices
585 * @retval None
586*/
587__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
588{
589 SET_BIT(RCC->APBRSTR1, Periphs);
590}
591
592/**
593 * @brief Release APB1 peripherals reset.
594 * @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
595 * APBRSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
596 * APBRSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
597 * APBRSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
598 * APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset\n
599 * APBRSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n
600 * APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
601 * APBRSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
602 * APBRSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
603 * APBRSTR1 USART4RST LL_APB1_GRP1_ReleaseReset\n
604 * APBRSTR1 LPUART1RST LL_APB1_GRP1_ReleaseReset\n
605 * APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
606 * APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
607 * APBRSTR1 CECRST LL_APB1_GRP1_ReleaseReset\n
608 * APBRSTR1 UCPD1RST LL_APB1_GRP1_ReleaseReset\n
609 * APBRSTR1 UCPD2RST LL_APB1_GRP1_ReleaseReset\n
610 * APBRSTR1 DBGRST LL_APB1_GRP1_ReleaseReset\n
611 * APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
612 * APBRSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
613 * APBRSTR1 LPTIM2RST LL_APB1_GRP1_ReleaseReset\n
614 * APBRSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
615 * @param Periphs This parameter can be a combination of the following values:
616 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
621 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
622 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
623 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
624 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
625 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
626 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
627 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
628 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
629 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
630 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
631 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
632 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
633 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
634 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
635 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
636 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
637 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
638 * @note Peripheral marked with (1) are not available all devices
639 * @retval None
640*/
641__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
642{
643 CLEAR_BIT(RCC->APBRSTR1, Periphs);
644}
645
646/**
647 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
648 * @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
649 * APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
650 * APBSMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
651 * APBSMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
652 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
653 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
654 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
655 * APBSMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
656 * APBSMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
657 * APBSMENR1 USART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
658 * APBSMENR1 LPUART1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
659 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
660 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
661 * APBSMENR1 CECSMEN LL_APB1_GRP1_EnableClockStopSleep\n
662 * APBSMENR1 UCPD1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
663 * APBSMENR1 UCPD2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
664 * APBSMENR1 DBGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
665 * APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
666 * APBSMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
667 * APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
668 * APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
669 * @param Periphs This parameter can be a combination of the following values:
670 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
671 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
672 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
673 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
674 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
675 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
676 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
677 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
678 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
679 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
680 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
681 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
682 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
683 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
684 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
685 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
686 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
687 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
688 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
689 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
690 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
691 * @note Peripheral marked with (1) are not available all devices
692 * @retval None
693*/
694__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
695{
696 __IO uint32_t tmpreg;
697 SET_BIT(RCC->APBSMENR1, Periphs);
698 /* Delay after an RCC peripheral clock enabling */
699 tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
700 (void)tmpreg;
701}
702
703/**
704 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
705 * @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
706 * APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
707 * APBSMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
708 * APBSMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
709 * APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
710 * APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
711 * APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
712 * APBSMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
713 * APBSMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
714 * APBSMENR1 USART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
715 * APBSMENR1 LPUART1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
716 * APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
717 * APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
718 * APBSMENR1 CECSMEN LL_APB1_GRP1_DisableClockStopSleep\n
719 * APBSMENR1 UCPD1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
720 * APBSMENR1 UCPD2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
721 * APBSMENR1 DBGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
722 * APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
723 * APBSMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
724 * APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
725 * APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
726 * @param Periphs This parameter can be a combination of the following values:
727 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
728 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
729 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
730 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
731 * @arg @ref LL_APB1_GRP1_PERIPH_RTC
732 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
733 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
734 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
735 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
736 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
737 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
738 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
739 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
740 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
741 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
742 * @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
743 * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
744 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
745 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
746 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
747 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
748 * @note Peripheral marked with (1) are not available all devices
749 * @retval None
750*/
751__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
752{
753 CLEAR_BIT(RCC->APBSMENR1, Periphs);
754}
755
756/**
757 * @}
758 */
759
760/** @defgroup BUS_LL_EF_APB2 APB2
761 * @{
762 */
763
764/**
765 * @brief Enable APB2 peripherals clock.
766 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_EnableClock\n
767 * APBENR2 TIM1EN LL_APB2_GRP1_EnableClock\n
768 * APBENR2 SPI1EN LL_APB2_GRP1_EnableClock\n
769 * APBENR2 USART1EN LL_APB2_GRP1_EnableClock\n
770 * APBENR2 TIM14EN LL_APB2_GRP1_EnableClock\n
771 * APBENR2 TIM15EN LL_APB2_GRP1_EnableClock\n (*)
772 * APBENR2 TIM16EN LL_APB2_GRP1_EnableClock\n
773 * APBENR2 TIM17EN LL_APB2_GRP1_EnableClock\n
774 * APBENR2 ADCEN LL_APB2_GRP1_EnableClock
775 * @param Periphs This parameter can be a combination of the following values:
776 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
777 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
778 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
779 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
780 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
781 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
782 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
783 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
784 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
785 * @note (*) peripheral not available on all devices
786 * @retval None
787*/
788__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
789{
790 __IO uint32_t tmpreg;
791 SET_BIT(RCC->APBENR2, Periphs);
792 /* Delay after an RCC peripheral clock enabling */
793 tmpreg = READ_BIT(RCC->APBENR2, Periphs);
794 (void)tmpreg;
795}
796
797/**
798 * @brief Check if APB2 peripheral clock is enabled or not
799 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
800 * APBENR2 TIM1EN LL_APB2_GRP1_IsEnabledClock\n
801 * APBENR2 SPI1EN LL_APB2_GRP1_IsEnabledClock\n
802 * APBENR2 USART1EN LL_APB2_GRP1_IsEnabledClock\n
803 * APBENR2 TIM14EN LL_APB2_GRP1_IsEnabledClock\n
804 * APBENR2 TIM15EN LL_APB2_GRP1_IsEnabledClock\n (*)
805 * APBENR2 TIM16EN LL_APB2_GRP1_IsEnabledClock\n
806 * APBENR2 TIM17EN LL_APB2_GRP1_IsEnabledClock\n
807 * APBENR2 ADCEN LL_APB2_GRP1_IsEnabledClock
808 * @param Periphs This parameter can be a combination of the following values:
809 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
810 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
811 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
812 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
813 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
814 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
815 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
816 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
817 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
818 * @note (*) peripheral not available on all devices
819 * @retval State of Periphs (1 or 0).
820*/
821__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
822{
823 return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
824}
825
826/**
827 * @brief Disable APB2 peripherals clock.
828 * @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_DisableClock\n
829 * APBENR2 TIM1EN LL_APB2_GRP1_DisableClock\n
830 * APBENR2 SPI1EN LL_APB2_GRP1_DisableClock\n
831 * APBENR2 USART1EN LL_APB2_GRP1_DisableClock\n
832 * APBENR2 TIM14EN LL_APB2_GRP1_DisableClock\n
833 * APBENR2 TIM15EN LL_APB2_GRP1_DisableClock\n (*)
834 * APBENR2 TIM16EN LL_APB2_GRP1_DisableClock\n
835 * APBENR2 TIM17EN LL_APB2_GRP1_DisableClock\n
836 * APBENR2 ADCEN LL_APB2_GRP1_DisableClock
837 * @param Periphs This parameter can be a combination of the following values:
838 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
839 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
840 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
841 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
842 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
843 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
844 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
845 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
846 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
847 * @note (*) peripheral not available on all devices
848 * @retval None
849*/
850__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
851{
852 CLEAR_BIT(RCC->APBENR2, Periphs);
853}
854
855/**
856 * @brief Force APB2 peripherals reset.
857 * @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ForceReset\n
858 * APBRSTR2 TIM1RST LL_APB2_GRP1_ForceReset\n
859 * APBRSTR2 SPI1RST LL_APB2_GRP1_ForceReset\n
860 * APBRSTR2 USART1RST LL_APB2_GRP1_ForceReset\n
861 * APBRSTR2 TIM14RST LL_APB2_GRP1_ForceReset\n
862 * APBRSTR2 TIM15RST LL_APB2_GRP1_ForceReset\n (*)
863 * APBRSTR2 TIM16RST LL_APB2_GRP1_ForceReset\n
864 * APBRSTR2 TIM17RST LL_APB2_GRP1_ForceReset\n
865 * APBRSTR2 ADCRST LL_APB2_GRP1_ForceReset
866 * @param Periphs This parameter can be a combination of the following values:
867 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
868 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
869 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
870 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
871 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
872 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
873 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
874 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
875 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
876 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
877 * @note (*) peripheral not available on all devices
878 * @retval None
879*/
880__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
881{
882 SET_BIT(RCC->APBRSTR2, Periphs);
883}
884
885/**
886 * @brief Release APB2 peripherals reset.
887 * @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
888 * APBRSTR2 TIM1RST LL_APB2_GRP1_ReleaseReset\n
889 * APBRSTR2 SPI1RST LL_APB2_GRP1_ReleaseReset\n
890 * APBRSTR2 USART1RST LL_APB2_GRP1_ReleaseReset\n
891 * APBRSTR2 TIM14RST LL_APB2_GRP1_ReleaseReset\n
892 * APBRSTR2 TIM15RST LL_APB2_GRP1_ReleaseReset\n (*)
893 * APBRSTR2 TIM16RST LL_APB2_GRP1_ReleaseReset\n
894 * APBRSTR2 TIM17RST LL_APB2_GRP1_ReleaseReset\n
895 * APBRSTR2 ADCRST LL_APB2_GRP1_ReleaseReset
896 * @param Periphs This parameter can be a combination of the following values:
897 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
898 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
899 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
900 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
901 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
903 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
904 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
905 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
906 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
907 * @note (*) peripheral not available on all devices
908 * @retval None
909*/
910__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
911{
912 CLEAR_BIT(RCC->APBRSTR2, Periphs);
913}
914
915/**
916 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
917 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
918 * APBSMENR2 TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
919 * APBSMENR2 SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
920 * APBSMENR2 USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
921 * APBSMENR2 TIM14SMEN LL_APB2_GRP1_EnableClockStopSleep\n
922 * APBSMENR2 TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n (*)
923 * APBSMENR2 TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
924 * APBSMENR2 TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
925 * APBSMENR2 ADCSMEN LL_APB2_GRP1_EnableClockStopSleep
926 * @param Periphs This parameter can be a combination of the following values:
927 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
928 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
929 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
930 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
931 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
933 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
935 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
936 * @note (*) peripheral not available on all devices
937 * @retval None
938*/
939__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
940{
941 __IO uint32_t tmpreg;
942 SET_BIT(RCC->APBSMENR2, Periphs);
943 /* Delay after an RCC peripheral clock enabling */
944 tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
945 (void)tmpreg;
946}
947
948/**
949 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
950 * @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
951 * APBSMENR2 TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
952 * APBSMENR2 SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
953 * APBSMENR2 USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
954 * APBSMENR2 TIM14SMEN LL_APB2_GRP1_DisableClockStopSleep\n
955 * APBSMENR2 TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n (*)
956 * APBSMENR2 TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
957 * APBSMENR2 TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
958 * APBSMENR2 ADCSMEN LL_APB2_GRP1_DisableClockStopSleep
959 * @param Periphs This parameter can be a combination of the following values:
960 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
961 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
962 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
963 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
964 * @arg @ref LL_APB2_GRP1_PERIPH_TIM14
965 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
966 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
967 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
968 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
969 * @note (*) peripheral not available on all devices
970 * @retval None
971*/
972__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
973{
974 CLEAR_BIT(RCC->APBSMENR2, Periphs);
975}
976
977/**
978 * @}
979 */
980
981/** @defgroup BUS_LL_EF_IOP IOP
982 * @{
983 */
984
985/**
986 * @brief Enable IOP peripherals clock.
987 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
988 * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
989 * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
990 * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
991 * IOPENR GPIOFEN LL_IOP_GRP1_EnableClock
992 * @param Periphs This parameter can be a combination of the following values:
993 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
994 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
995 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
996 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
997 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
998 * @retval None
999*/
1000__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
1001{
1002 __IO uint32_t tmpreg;
1003 SET_BIT(RCC->IOPENR, Periphs);
1004 /* Delay after an RCC peripheral clock enabling */
1005 tmpreg = READ_BIT(RCC->IOPENR, Periphs);
1006 (void)tmpreg;
1007}
1008
1009/**
1010 * @brief Check if IOP peripheral clock is enabled or not
1011 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
1012 * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
1013 * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
1014 * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
1015 * IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock
1016 * @param Periphs This parameter can be a combination of the following values:
1017 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1018 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1019 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1020 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1021 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1022 * @retval State of Periphs (1 or 0).
1023*/
1024__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
1025{
1026 return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
1027}
1028
1029/**
1030 * @brief Disable IOP peripherals clock.
1031 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
1032 * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
1033 * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
1034 * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
1035 * IOPENR GPIOFEN LL_IOP_GRP1_DisableClock
1036 * @param Periphs This parameter can be a combination of the following values:
1037 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1038 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1039 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1040 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1041 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1042 * @retval None
1043*/
1044__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
1045{
1046 CLEAR_BIT(RCC->IOPENR, Periphs);
1047}
1048
1049/**
1050 * @brief Disable IOP peripherals clock.
1051 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset\n
1052 * IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset\n
1053 * IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset\n
1054 * IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset\n
1055 * IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset
1056 * @param Periphs This parameter can be a combination of the following values:
1057 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1058 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1059 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1060 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1061 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1062 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1063 * @retval None
1064*/
1065__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
1066{
1067 SET_BIT(RCC->IOPRSTR, Periphs);
1068}
1069
1070/**
1071 * @brief Release IOP peripherals reset.
1072 * @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset\n
1073 * IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset\n
1074 * IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset\n
1075 * IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset\n
1076 * IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset
1077 * @param Periphs This parameter can be a combination of the following values:
1078 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
1079 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1080 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1081 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1082 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1083 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1084 * @retval None
1085*/
1086__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
1087{
1088 CLEAR_BIT(RCC->IOPRSTR, Periphs);
1089}
1090
1091/**
1092 * @brief Enable IOP peripheral clocks in Sleep and Stop modes
1093 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep\n
1094 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1095 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1096 * IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep\n
1097 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep
1098 * @param Periphs This parameter can be a combination of the following values:
1099 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1100 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1101 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1102 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1103 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1104 * @retval None
1105*/
1106__STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
1107{
1108 __IO uint32_t tmpreg;
1109 SET_BIT(RCC->IOPSMENR, Periphs);
1110 /* Delay after an RCC peripheral clock enabling */
1111 tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
1112 (void)tmpreg;
1113}
1114
1115/**
1116 * @brief Disable IOP peripheral clocks in Sleep and Stop modes
1117 * @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep\n
1118 * IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1119 * IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1120 * IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep\n
1121 * IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep
1122 * @param Periphs This parameter can be a combination of the following values:
1123 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
1124 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
1125 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
1126 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
1127 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
1128 * @retval None
1129*/
1130__STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
1131{
1132 CLEAR_BIT(RCC->IOPSMENR, Periphs);
1133}
1134
1135/**
1136 * @}
1137 */
1138
1139
1140/**
1141 * @}
1142 */
1143
1144/**
1145 * @}
1146 */
1147
1148#endif /* defined(RCC) */
1149
1150/**
1151 * @}
1152 */
1153
1154#ifdef __cplusplus
1155}
1156#endif
1157
1158#endif /* STM32G0xx_LL_BUS_H */
1159
1160/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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